drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include "intel_drv.h"
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include <linux/pci.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/acpi.h>
  41 #include <linux/pnp.h>
  42 #include <linux/vga_switcheroo.h>
  43 #include <linux/slab.h>
  44 #include <acpi/video.h>
  45 #include <asm/pat.h>
  46
  47 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  48
  49 #define BEGIN_LP_RING(n) \
  50         intel_ring_begin(LP_RING(dev_priv), (n))
  51
  52 #define OUT_RING(x) \
  53         intel_ring_emit(LP_RING(dev_priv), x)
  54
  55 #define ADVANCE_LP_RING() \
  56         intel_ring_advance(LP_RING(dev_priv))
  57
  58 /**
  59  * Lock test for when it's just for synchronization of ring access.
  60  *
  61  * In that case, we don't need to do it when GEM is initialized as nobody else
  62  * has access to the ring.
  63  */
  64 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  65         if (LP_RING(dev->dev_private)->obj == NULL)                     \
  66                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  67 } while (0)
  68
  69 static inline u32
  70 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  71 {
  72         if (I915_NEED_GFX_HWS(dev_priv->dev))
  73                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  74         else
  75                 return intel_read_status_page(LP_RING(dev_priv), reg);
  76 }
  77
  78 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  79 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  80 #define I915_BREADCRUMB_INDEX           0x21
  81
  82 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  83 {
  84         drm_i915_private_t *dev_priv = dev->dev_private;
  85         struct drm_i915_master_private *master_priv;
  86
  87         if (dev->primary->master) {
  88                 master_priv = dev->primary->master->driver_priv;
  89                 if (master_priv->sarea_priv)
  90                         master_priv->sarea_priv->last_dispatch =
  91                                 READ_BREADCRUMB(dev_priv);
  92         }
  93 }
  94
  95 static void i915_write_hws_pga(struct drm_device *dev)
  96 {
  97         drm_i915_private_t *dev_priv = dev->dev_private;
  98         u32 addr;
  99
 100         addr = dev_priv->status_page_dmah->busaddr;
 101         if (INTEL_INFO(dev)->gen >= 4)
 102                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 103         I915_WRITE(HWS_PGA, addr);
 104 }
 105
 106 /**
 107  * Frees the hardware status page, whether it's a physical address or a virtual
 108  * address set up by the X Server.
 109  */
 110 static void i915_free_hws(struct drm_device *dev)
 111 {
 112         drm_i915_private_t *dev_priv = dev->dev_private;
 113         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 114
 115         if (dev_priv->status_page_dmah) {
 116                 drm_pci_free(dev, dev_priv->status_page_dmah);
 117                 dev_priv->status_page_dmah = NULL;
 118         }
 119
 120         if (ring->status_page.gfx_addr) {
 121                 ring->status_page.gfx_addr = 0;
 122                 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
 123         }
 124
 125         /* Need to rewrite hardware status page */
 126         I915_WRITE(HWS_PGA, 0x1ffff000);
 127 }
 128
 129 void i915_kernel_lost_context(struct drm_device * dev)
 130 {
 131         drm_i915_private_t *dev_priv = dev->dev_private;
 132         struct drm_i915_master_private *master_priv;
 133         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 134
 135         /*
 136          * We should never lose context on the ring with modesetting
 137          * as we don't expose it to userspace
 138          */
 139         if (drm_core_check_feature(dev, DRIVER_MODESET))
 140                 return;
 141
 142         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 143         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 144         ring->space = ring->head - (ring->tail + 8);
 145         if (ring->space < 0)
 146                 ring->space += ring->size;
 147
 148         if (!dev->primary->master)
 149                 return;
 150
 151         master_priv = dev->primary->master->driver_priv;
 152         if (ring->head == ring->tail && master_priv->sarea_priv)
 153                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 154 }
 155
 156 static int i915_dma_cleanup(struct drm_device * dev)
 157 {
 158         drm_i915_private_t *dev_priv = dev->dev_private;
 159         int i;
 160
 161         /* Make sure interrupts are disabled here because the uninstall ioctl
 162          * may not have been called from userspace and after dev_private
 163          * is freed, it's too late.
 164          */
 165         if (dev->irq_enabled)
 166                 drm_irq_uninstall(dev);
 167
 168         mutex_lock(&dev->struct_mutex);
 169         for (i = 0; i < I915_NUM_RINGS; i++)
 170                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 171         mutex_unlock(&dev->struct_mutex);
 172
 173         /* Clear the HWS virtual address at teardown */
 174         if (I915_NEED_GFX_HWS(dev))
 175                 i915_free_hws(dev);
 176
 177         return 0;
 178 }
 179
 180 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 181 {
 182         drm_i915_private_t *dev_priv = dev->dev_private;
 183         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 184         int ret;
 185
 186         master_priv->sarea = drm_getsarea(dev);
 187         if (master_priv->sarea) {
 188                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 189                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 190         } else {
 191                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 192         }
 193
 194         if (init->ring_size != 0) {
 195                 if (LP_RING(dev_priv)->obj != NULL) {
 196                         i915_dma_cleanup(dev);
 197                         DRM_ERROR("Client tried to initialize ringbuffer in "
 198                                   "GEM mode\n");
 199                         return -EINVAL;
 200                 }
 201
 202                 ret = intel_render_ring_init_dri(dev,
 203                                                  init->ring_start,
 204                                                  init->ring_size);
 205                 if (ret) {
 206                         i915_dma_cleanup(dev);
 207                         return ret;
 208                 }
 209         }
 210
 211         dev_priv->dri1.cpp = init->cpp;
 212         dev_priv->dri1.back_offset = init->back_offset;
 213         dev_priv->dri1.front_offset = init->front_offset;
 214         dev_priv->dri1.current_page = 0;
 215         if (master_priv->sarea_priv)
 216                 master_priv->sarea_priv->pf_current_page = 0;
 217
 218         /* Allow hardware batchbuffers unless told otherwise.
 219          */
 220         dev_priv->dri1.allow_batchbuffer = 1;
 221
 222         return 0;
 223 }
 224
 225 static int i915_dma_resume(struct drm_device * dev)
 226 {
 227         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 228         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 229
 230         DRM_DEBUG_DRIVER("%s\n", __func__);
 231
 232         if (ring->virtual_start == NULL) {
 233                 DRM_ERROR("can not ioremap virtual address for"
 234                           " ring buffer\n");
 235                 return -ENOMEM;
 236         }
 237
 238         /* Program Hardware Status Page */
 239         if (!ring->status_page.page_addr) {
 240                 DRM_ERROR("Can not find hardware status page\n");
 241                 return -EINVAL;
 242         }
 243         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 244                                 ring->status_page.page_addr);
 245         if (ring->status_page.gfx_addr != 0)
 246                 intel_ring_setup_status_page(ring);
 247         else
 248                 i915_write_hws_pga(dev);
 249
 250         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 251
 252         return 0;
 253 }
 254
 255 static int i915_dma_init(struct drm_device *dev, void *data,
 256                          struct drm_file *file_priv)
 257 {
 258         drm_i915_init_t *init = data;
 259         int retcode = 0;
 260
 261         if (drm_core_check_feature(dev, DRIVER_MODESET))
 262                 return -ENODEV;
 263
 264         switch (init->func) {
 265         case I915_INIT_DMA:
 266                 retcode = i915_initialize(dev, init);
 267                 break;
 268         case I915_CLEANUP_DMA:
 269                 retcode = i915_dma_cleanup(dev);
 270                 break;
 271         case I915_RESUME_DMA:
 272                 retcode = i915_dma_resume(dev);
 273                 break;
 274         default:
 275                 retcode = -EINVAL;
 276                 break;
 277         }
 278
 279         return retcode;
 280 }
 281
 282 /* Implement basically the same security restrictions as hardware does
 283  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 284  *
 285  * Most of the calculations below involve calculating the size of a
 286  * particular instruction.  It's important to get the size right as
 287  * that tells us where the next instruction to check is.  Any illegal
 288  * instruction detected will be given a size of zero, which is a
 289  * signal to abort the rest of the buffer.
 290  */
 291 static int validate_cmd(int cmd)
 292 {
 293         switch (((cmd >> 29) & 0x7)) {
 294         case 0x0:
 295                 switch ((cmd >> 23) & 0x3f) {
 296                 case 0x0:
 297                         return 1;       /* MI_NOOP */
 298                 case 0x4:
 299                         return 1;       /* MI_FLUSH */
 300                 default:
 301                         return 0;       /* disallow everything else */
 302                 }
 303                 break;
 304         case 0x1:
 305                 return 0;       /* reserved */
 306         case 0x2:
 307                 return (cmd & 0xff) + 2;        /* 2d commands */
 308         case 0x3:
 309                 if (((cmd >> 24) & 0x1f) <= 0x18)
 310                         return 1;
 311
 312                 switch ((cmd >> 24) & 0x1f) {
 313                 case 0x1c:
 314                         return 1;
 315                 case 0x1d:
 316                         switch ((cmd >> 16) & 0xff) {
 317                         case 0x3:
 318                                 return (cmd & 0x1f) + 2;
 319                         case 0x4:
 320                                 return (cmd & 0xf) + 2;
 321                         default:
 322                                 return (cmd & 0xffff) + 2;
 323                         }
 324                 case 0x1e:
 325                         if (cmd & (1 << 23))
 326                                 return (cmd & 0xffff) + 1;
 327                         else
 328                                 return 1;
 329                 case 0x1f:
 330                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 331                                 return (cmd & 0x1ffff) + 2;
 332                         else if (cmd & (1 << 17))       /* indirect random */
 333                                 if ((cmd & 0xffff) == 0)
 334                                         return 0;       /* unknown length, too hard */
 335                                 else
 336                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 337                         else
 338                                 return 2;       /* indirect sequential */
 339                 default:
 340                         return 0;
 341                 }
 342         default:
 343                 return 0;
 344         }
 345
 346         return 0;
 347 }
 348
 349 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 350 {
 351         drm_i915_private_t *dev_priv = dev->dev_private;
 352         int i, ret;
 353
 354         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 355                 return -EINVAL;
 356
 357         for (i = 0; i < dwords;) {
 358                 int sz = validate_cmd(buffer[i]);
 359                 if (sz == 0 || i + sz > dwords)
 360                         return -EINVAL;
 361                 i += sz;
 362         }
 363
 364         ret = BEGIN_LP_RING((dwords+1)&~1);
 365         if (ret)
 366                 return ret;
 367
 368         for (i = 0; i < dwords; i++)
 369                 OUT_RING(buffer[i]);
 370         if (dwords & 1)
 371                 OUT_RING(0);
 372
 373         ADVANCE_LP_RING();
 374
 375         return 0;
 376 }
 377
 378 int
 379 i915_emit_box(struct drm_device *dev,
 380               struct drm_clip_rect *box,
 381               int DR1, int DR4)
 382 {
 383         struct drm_i915_private *dev_priv = dev->dev_private;
 384         int ret;
 385
 386         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 387             box->y2 <= 0 || box->x2 <= 0) {
 388                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 389                           box->x1, box->y1, box->x2, box->y2);
 390                 return -EINVAL;
 391         }
 392
 393         if (INTEL_INFO(dev)->gen >= 4) {
 394                 ret = BEGIN_LP_RING(4);
 395                 if (ret)
 396                         return ret;
 397
 398                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 399                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 400                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 401                 OUT_RING(DR4);
 402         } else {
 403                 ret = BEGIN_LP_RING(6);
 404                 if (ret)
 405                         return ret;
 406
 407                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 408                 OUT_RING(DR1);
 409                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 410                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 411                 OUT_RING(DR4);
 412                 OUT_RING(0);
 413         }
 414         ADVANCE_LP_RING();
 415
 416         return 0;
 417 }
 418
 419 /* XXX: Emitting the counter should really be moved to part of the IRQ
 420  * emit. For now, do it in both places:
 421  */
 422
 423 static void i915_emit_breadcrumb(struct drm_device *dev)
 424 {
 425         drm_i915_private_t *dev_priv = dev->dev_private;
 426         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 427
 428         dev_priv->dri1.counter++;
 429         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 430                 dev_priv->dri1.counter = 0;
 431         if (master_priv->sarea_priv)
 432                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 433
 434         if (BEGIN_LP_RING(4) == 0) {
 435                 OUT_RING(MI_STORE_DWORD_INDEX);
 436                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 437                 OUT_RING(dev_priv->dri1.counter);
 438                 OUT_RING(0);
 439                 ADVANCE_LP_RING();
 440         }
 441 }
 442
 443 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 444                                    drm_i915_cmdbuffer_t *cmd,
 445                                    struct drm_clip_rect *cliprects,
 446                                    void *cmdbuf)
 447 {
 448         int nbox = cmd->num_cliprects;
 449         int i = 0, count, ret;
 450
 451         if (cmd->sz & 0x3) {
 452                 DRM_ERROR("alignment");
 453                 return -EINVAL;
 454         }
 455
 456         i915_kernel_lost_context(dev);
 457
 458         count = nbox ? nbox : 1;
 459
 460         for (i = 0; i < count; i++) {
 461                 if (i < nbox) {
 462                         ret = i915_emit_box(dev, &cliprects[i],
 463                                             cmd->DR1, cmd->DR4);
 464                         if (ret)
 465                                 return ret;
 466                 }
 467
 468                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 469                 if (ret)
 470                         return ret;
 471         }
 472
 473         i915_emit_breadcrumb(dev);
 474         return 0;
 475 }
 476
 477 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 478                                      drm_i915_batchbuffer_t * batch,
 479                                      struct drm_clip_rect *cliprects)
 480 {
 481         struct drm_i915_private *dev_priv = dev->dev_private;
 482         int nbox = batch->num_cliprects;
 483         int i, count, ret;
 484
 485         if ((batch->start | batch->used) & 0x7) {
 486                 DRM_ERROR("alignment");
 487                 return -EINVAL;
 488         }
 489
 490         i915_kernel_lost_context(dev);
 491
 492         count = nbox ? nbox : 1;
 493         for (i = 0; i < count; i++) {
 494                 if (i < nbox) {
 495                         ret = i915_emit_box(dev, &cliprects[i],
 496                                             batch->DR1, batch->DR4);
 497                         if (ret)
 498                                 return ret;
 499                 }
 500
 501                 if (!IS_I830(dev) && !IS_845G(dev)) {
 502                         ret = BEGIN_LP_RING(2);
 503                         if (ret)
 504                                 return ret;
 505
 506                         if (INTEL_INFO(dev)->gen >= 4) {
 507                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 508                                 OUT_RING(batch->start);
 509                         } else {
 510                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 511                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 512                         }
 513                 } else {
 514                         ret = BEGIN_LP_RING(4);
 515                         if (ret)
 516                                 return ret;
 517
 518                         OUT_RING(MI_BATCH_BUFFER);
 519                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 520                         OUT_RING(batch->start + batch->used - 4);
 521                         OUT_RING(0);
 522                 }
 523                 ADVANCE_LP_RING();
 524         }
 525
 526
 527         if (IS_G4X(dev) || IS_GEN5(dev)) {
 528                 if (BEGIN_LP_RING(2) == 0) {
 529                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 530                         OUT_RING(MI_NOOP);
 531                         ADVANCE_LP_RING();
 532                 }
 533         }
 534
 535         i915_emit_breadcrumb(dev);
 536         return 0;
 537 }
 538
 539 static int i915_dispatch_flip(struct drm_device * dev)
 540 {
 541         drm_i915_private_t *dev_priv = dev->dev_private;
 542         struct drm_i915_master_private *master_priv =
 543                 dev->primary->master->driver_priv;
 544         int ret;
 545
 546         if (!master_priv->sarea_priv)
 547                 return -EINVAL;
 548
 549         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 550                           __func__,
 551                          dev_priv->dri1.current_page,
 552                          master_priv->sarea_priv->pf_current_page);
 553
 554         i915_kernel_lost_context(dev);
 555
 556         ret = BEGIN_LP_RING(10);
 557         if (ret)
 558                 return ret;
 559
 560         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 561         OUT_RING(0);
 562
 563         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 564         OUT_RING(0);
 565         if (dev_priv->dri1.current_page == 0) {
 566                 OUT_RING(dev_priv->dri1.back_offset);
 567                 dev_priv->dri1.current_page = 1;
 568         } else {
 569                 OUT_RING(dev_priv->dri1.front_offset);
 570                 dev_priv->dri1.current_page = 0;
 571         }
 572         OUT_RING(0);
 573
 574         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 575         OUT_RING(0);
 576
 577         ADVANCE_LP_RING();
 578
 579         master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 580
 581         if (BEGIN_LP_RING(4) == 0) {
 582                 OUT_RING(MI_STORE_DWORD_INDEX);
 583                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 584                 OUT_RING(dev_priv->dri1.counter);
 585                 OUT_RING(0);
 586                 ADVANCE_LP_RING();
 587         }
 588
 589         master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 590         return 0;
 591 }
 592
 593 static int i915_quiescent(struct drm_device *dev)
 594 {
 595         struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
 596
 597         i915_kernel_lost_context(dev);
 598         return intel_wait_ring_idle(ring);
 599 }
 600
 601 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 602                             struct drm_file *file_priv)
 603 {
 604         int ret;
 605
 606         if (drm_core_check_feature(dev, DRIVER_MODESET))
 607                 return -ENODEV;
 608
 609         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 610
 611         mutex_lock(&dev->struct_mutex);
 612         ret = i915_quiescent(dev);
 613         mutex_unlock(&dev->struct_mutex);
 614
 615         return ret;
 616 }
 617
 618 static int i915_batchbuffer(struct drm_device *dev, void *data,
 619                             struct drm_file *file_priv)
 620 {
 621         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 622         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 623         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 624             master_priv->sarea_priv;
 625         drm_i915_batchbuffer_t *batch = data;
 626         int ret;
 627         struct drm_clip_rect *cliprects = NULL;
 628
 629         if (drm_core_check_feature(dev, DRIVER_MODESET))
 630                 return -ENODEV;
 631
 632         if (!dev_priv->dri1.allow_batchbuffer) {
 633                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 634                 return -EINVAL;
 635         }
 636
 637         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 638                         batch->start, batch->used, batch->num_cliprects);
 639
 640         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 641
 642         if (batch->num_cliprects < 0)
 643                 return -EINVAL;
 644
 645         if (batch->num_cliprects) {
 646                 cliprects = kcalloc(batch->num_cliprects,
 647                                     sizeof(struct drm_clip_rect),
 648                                     GFP_KERNEL);
 649                 if (cliprects == NULL)
 650                         return -ENOMEM;
 651
 652                 ret = copy_from_user(cliprects, batch->cliprects,
 653                                      batch->num_cliprects *
 654                                      sizeof(struct drm_clip_rect));
 655                 if (ret != 0) {
 656                         ret = -EFAULT;
 657                         goto fail_free;
 658                 }
 659         }
 660
 661         mutex_lock(&dev->struct_mutex);
 662         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 663         mutex_unlock(&dev->struct_mutex);
 664
 665         if (sarea_priv)
 666                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 667
 668 fail_free:
 669         kfree(cliprects);
 670
 671         return ret;
 672 }
 673
 674 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 675                           struct drm_file *file_priv)
 676 {
 677         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 678         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 679         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 680             master_priv->sarea_priv;
 681         drm_i915_cmdbuffer_t *cmdbuf = data;
 682         struct drm_clip_rect *cliprects = NULL;
 683         void *batch_data;
 684         int ret;
 685
 686         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 687                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 688
 689         if (drm_core_check_feature(dev, DRIVER_MODESET))
 690                 return -ENODEV;
 691
 692         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 693
 694         if (cmdbuf->num_cliprects < 0)
 695                 return -EINVAL;
 696
 697         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 698         if (batch_data == NULL)
 699                 return -ENOMEM;
 700
 701         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 702         if (ret != 0) {
 703                 ret = -EFAULT;
 704                 goto fail_batch_free;
 705         }
 706
 707         if (cmdbuf->num_cliprects) {
 708                 cliprects = kcalloc(cmdbuf->num_cliprects,
 709                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 710                 if (cliprects == NULL) {
 711                         ret = -ENOMEM;
 712                         goto fail_batch_free;
 713                 }
 714
 715                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 716                                      cmdbuf->num_cliprects *
 717                                      sizeof(struct drm_clip_rect));
 718                 if (ret != 0) {
 719                         ret = -EFAULT;
 720                         goto fail_clip_free;
 721                 }
 722         }
 723
 724         mutex_lock(&dev->struct_mutex);
 725         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 726         mutex_unlock(&dev->struct_mutex);
 727         if (ret) {
 728                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 729                 goto fail_clip_free;
 730         }
 731
 732         if (sarea_priv)
 733                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 734
 735 fail_clip_free:
 736         kfree(cliprects);
 737 fail_batch_free:
 738         kfree(batch_data);
 739
 740         return ret;
 741 }
 742
 743 static int i915_emit_irq(struct drm_device * dev)
 744 {
 745         drm_i915_private_t *dev_priv = dev->dev_private;
 746         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 747
 748         i915_kernel_lost_context(dev);
 749
 750         DRM_DEBUG_DRIVER("\n");
 751
 752         dev_priv->dri1.counter++;
 753         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 754                 dev_priv->dri1.counter = 1;
 755         if (master_priv->sarea_priv)
 756                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 757
 758         if (BEGIN_LP_RING(4) == 0) {
 759                 OUT_RING(MI_STORE_DWORD_INDEX);
 760                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 761                 OUT_RING(dev_priv->dri1.counter);
 762                 OUT_RING(MI_USER_INTERRUPT);
 763                 ADVANCE_LP_RING();
 764         }
 765
 766         return dev_priv->dri1.counter;
 767 }
 768
 769 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 770 {
 771         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 772         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 773         int ret = 0;
 774         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 775
 776         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 777                   READ_BREADCRUMB(dev_priv));
 778
 779         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 780                 if (master_priv->sarea_priv)
 781                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 782                 return 0;
 783         }
 784
 785         if (master_priv->sarea_priv)
 786                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 787
 788         if (ring->irq_get(ring)) {
 789                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 790                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 791                 ring->irq_put(ring);
 792         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 793                 ret = -EBUSY;
 794
 795         if (ret == -EBUSY) {
 796                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 797                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 798         }
 799
 800         return ret;
 801 }
 802
 803 /* Needs the lock as it touches the ring.
 804  */
 805 static int i915_irq_emit(struct drm_device *dev, void *data,
 806                          struct drm_file *file_priv)
 807 {
 808         drm_i915_private_t *dev_priv = dev->dev_private;
 809         drm_i915_irq_emit_t *emit = data;
 810         int result;
 811
 812         if (drm_core_check_feature(dev, DRIVER_MODESET))
 813                 return -ENODEV;
 814
 815         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 816                 DRM_ERROR("called with no initialization\n");
 817                 return -EINVAL;
 818         }
 819
 820         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 821
 822         mutex_lock(&dev->struct_mutex);
 823         result = i915_emit_irq(dev);
 824         mutex_unlock(&dev->struct_mutex);
 825
 826         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 827                 DRM_ERROR("copy_to_user\n");
 828                 return -EFAULT;
 829         }
 830
 831         return 0;
 832 }
 833
 834 /* Doesn't need the hardware lock.
 835  */
 836 static int i915_irq_wait(struct drm_device *dev, void *data,
 837                          struct drm_file *file_priv)
 838 {
 839         drm_i915_private_t *dev_priv = dev->dev_private;
 840         drm_i915_irq_wait_t *irqwait = data;
 841
 842         if (drm_core_check_feature(dev, DRIVER_MODESET))
 843                 return -ENODEV;
 844
 845         if (!dev_priv) {
 846                 DRM_ERROR("called with no initialization\n");
 847                 return -EINVAL;
 848         }
 849
 850         return i915_wait_irq(dev, irqwait->irq_seq);
 851 }
 852
 853 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 854                          struct drm_file *file_priv)
 855 {
 856         drm_i915_private_t *dev_priv = dev->dev_private;
 857         drm_i915_vblank_pipe_t *pipe = data;
 858
 859         if (drm_core_check_feature(dev, DRIVER_MODESET))
 860                 return -ENODEV;
 861
 862         if (!dev_priv) {
 863                 DRM_ERROR("called with no initialization\n");
 864                 return -EINVAL;
 865         }
 866
 867         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 868
 869         return 0;
 870 }
 871
 872 /**
 873  * Schedule buffer swap at given vertical blank.
 874  */
 875 static int i915_vblank_swap(struct drm_device *dev, void *data,
 876                      struct drm_file *file_priv)
 877 {
 878         /* The delayed swap mechanism was fundamentally racy, and has been
 879          * removed.  The model was that the client requested a delayed flip/swap
 880          * from the kernel, then waited for vblank before continuing to perform
 881          * rendering.  The problem was that the kernel might wake the client
 882          * up before it dispatched the vblank swap (since the lock has to be
 883          * held while touching the ringbuffer), in which case the client would
 884          * clear and start the next frame before the swap occurred, and
 885          * flicker would occur in addition to likely missing the vblank.
 886          *
 887          * In the absence of this ioctl, userland falls back to a correct path
 888          * of waiting for a vblank, then dispatching the swap on its own.
 889          * Context switching to userland and back is plenty fast enough for
 890          * meeting the requirements of vblank swapping.
 891          */
 892         return -EINVAL;
 893 }
 894
 895 static int i915_flip_bufs(struct drm_device *dev, void *data,
 896                           struct drm_file *file_priv)
 897 {
 898         int ret;
 899
 900         if (drm_core_check_feature(dev, DRIVER_MODESET))
 901                 return -ENODEV;
 902
 903         DRM_DEBUG_DRIVER("%s\n", __func__);
 904
 905         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 906
 907         mutex_lock(&dev->struct_mutex);
 908         ret = i915_dispatch_flip(dev);
 909         mutex_unlock(&dev->struct_mutex);
 910
 911         return ret;
 912 }
 913
 914 static int i915_getparam(struct drm_device *dev, void *data,
 915                          struct drm_file *file_priv)
 916 {
 917         drm_i915_private_t *dev_priv = dev->dev_private;
 918         drm_i915_getparam_t *param = data;
 919         int value;
 920
 921         if (!dev_priv) {
 922                 DRM_ERROR("called with no initialization\n");
 923                 return -EINVAL;
 924         }
 925
 926         switch (param->param) {
 927         case I915_PARAM_IRQ_ACTIVE:
 928                 value = dev->pdev->irq ? 1 : 0;
 929                 break;
 930         case I915_PARAM_ALLOW_BATCHBUFFER:
 931                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 932                 break;
 933         case I915_PARAM_LAST_DISPATCH:
 934                 value = READ_BREADCRUMB(dev_priv);
 935                 break;
 936         case I915_PARAM_CHIPSET_ID:
 937                 value = dev->pci_device;
 938                 break;
 939         case I915_PARAM_HAS_GEM:
 940                 value = 1;
 941                 break;
 942         case I915_PARAM_NUM_FENCES_AVAIL:
 943                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 944                 break;
 945         case I915_PARAM_HAS_OVERLAY:
 946                 value = dev_priv->overlay ? 1 : 0;
 947                 break;
 948         case I915_PARAM_HAS_PAGEFLIPPING:
 949                 value = 1;
 950                 break;
 951         case I915_PARAM_HAS_EXECBUF2:
 952                 /* depends on GEM */
 953                 value = 1;
 954                 break;
 955         case I915_PARAM_HAS_BSD:
 956                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 957                 break;
 958         case I915_PARAM_HAS_BLT:
 959                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 960                 break;
 961         case I915_PARAM_HAS_RELAXED_FENCING:
 962                 value = 1;
 963                 break;
 964         case I915_PARAM_HAS_COHERENT_RINGS:
 965                 value = 1;
 966                 break;
 967         case I915_PARAM_HAS_EXEC_CONSTANTS:
 968                 value = INTEL_INFO(dev)->gen >= 4;
 969                 break;
 970         case I915_PARAM_HAS_RELAXED_DELTA:
 971                 value = 1;
 972                 break;
 973         case I915_PARAM_HAS_GEN7_SOL_RESET:
 974                 value = 1;
 975                 break;
 976         case I915_PARAM_HAS_LLC:
 977                 value = HAS_LLC(dev);
 978                 break;
 979         case I915_PARAM_HAS_ALIASING_PPGTT:
 980                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 981                 break;
 982         case I915_PARAM_HAS_WAIT_TIMEOUT:
 983                 value = 1;
 984                 break;
 985         case I915_PARAM_HAS_SEMAPHORES:
 986                 value = i915_semaphore_is_enabled(dev);
 987                 break;
 988         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 989                 value = 1;
 990                 break;
 991         case I915_PARAM_HAS_SECURE_BATCHES:
 992                 value = capable(CAP_SYS_ADMIN);
 993                 break;
 994         default:
 995                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 996                                  param->param);
 997                 return -EINVAL;
 998         }
 999
1000         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1001                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1002                 return -EFAULT;
1003         }
1004
1005         return 0;
1006 }
1007
1008 static int i915_setparam(struct drm_device *dev, void *data,
1009                          struct drm_file *file_priv)
1010 {
1011         drm_i915_private_t *dev_priv = dev->dev_private;
1012         drm_i915_setparam_t *param = data;
1013
1014         if (!dev_priv) {
1015                 DRM_ERROR("called with no initialization\n");
1016                 return -EINVAL;
1017         }
1018
1019         switch (param->param) {
1020         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1021                 break;
1022         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1023                 break;
1024         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1025                 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1026                 break;
1027         case I915_SETPARAM_NUM_USED_FENCES:
1028                 if (param->value > dev_priv->num_fence_regs ||
1029                     param->value < 0)
1030                         return -EINVAL;
1031                 /* Userspace can use first N regs */
1032                 dev_priv->fence_reg_start = param->value;
1033                 break;
1034         default:
1035                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1036                                         param->param);
1037                 return -EINVAL;
1038         }
1039
1040         return 0;
1041 }
1042
1043 static int i915_set_status_page(struct drm_device *dev, void *data,
1044                                 struct drm_file *file_priv)
1045 {
1046         drm_i915_private_t *dev_priv = dev->dev_private;
1047         drm_i915_hws_addr_t *hws = data;
1048         struct intel_ring_buffer *ring;
1049
1050         if (drm_core_check_feature(dev, DRIVER_MODESET))
1051                 return -ENODEV;
1052
1053         if (!I915_NEED_GFX_HWS(dev))
1054                 return -EINVAL;
1055
1056         if (!dev_priv) {
1057                 DRM_ERROR("called with no initialization\n");
1058                 return -EINVAL;
1059         }
1060
1061         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1062                 WARN(1, "tried to set status page when mode setting active\n");
1063                 return 0;
1064         }
1065
1066         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1067
1068         ring = LP_RING(dev_priv);
1069         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1070
1071         dev_priv->dri1.gfx_hws_cpu_addr =
1072                 ioremap_wc(dev_priv->mm.gtt_base_addr + hws->addr, 4096);
1073         if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1074                 i915_dma_cleanup(dev);
1075                 ring->status_page.gfx_addr = 0;
1076                 DRM_ERROR("can not ioremap virtual address for"
1077                                 " G33 hw status page\n");
1078                 return -ENOMEM;
1079         }
1080
1081         memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1082         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1083
1084         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1085                          ring->status_page.gfx_addr);
1086         DRM_DEBUG_DRIVER("load hws at %p\n",
1087                          ring->status_page.page_addr);
1088         return 0;
1089 }
1090
1091 static int i915_get_bridge_dev(struct drm_device *dev)
1092 {
1093         struct drm_i915_private *dev_priv = dev->dev_private;
1094
1095         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1096         if (!dev_priv->bridge_dev) {
1097                 DRM_ERROR("bridge device not found\n");
1098                 return -1;
1099         }
1100         return 0;
1101 }
1102
1103 #define MCHBAR_I915 0x44
1104 #define MCHBAR_I965 0x48
1105 #define MCHBAR_SIZE (4*4096)
1106
1107 #define DEVEN_REG 0x54
1108 #define   DEVEN_MCHBAR_EN (1 << 28)
1109
1110 /* Allocate space for the MCH regs if needed, return nonzero on error */
1111 static int
1112 intel_alloc_mchbar_resource(struct drm_device *dev)
1113 {
1114         drm_i915_private_t *dev_priv = dev->dev_private;
1115         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1116         u32 temp_lo, temp_hi = 0;
1117         u64 mchbar_addr;
1118         int ret;
1119
1120         if (INTEL_INFO(dev)->gen >= 4)
1121                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1122         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1123         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1124
1125         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1126 #ifdef CONFIG_PNP
1127         if (mchbar_addr &&
1128             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1129                 return 0;
1130 #endif
1131
1132         /* Get some space for it */
1133         dev_priv->mch_res.name = "i915 MCHBAR";
1134         dev_priv->mch_res.flags = IORESOURCE_MEM;
1135         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1136                                      &dev_priv->mch_res,
1137                                      MCHBAR_SIZE, MCHBAR_SIZE,
1138                                      PCIBIOS_MIN_MEM,
1139                                      0, pcibios_align_resource,
1140                                      dev_priv->bridge_dev);
1141         if (ret) {
1142                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1143                 dev_priv->mch_res.start = 0;
1144                 return ret;
1145         }
1146
1147         if (INTEL_INFO(dev)->gen >= 4)
1148                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1149                                        upper_32_bits(dev_priv->mch_res.start));
1150
1151         pci_write_config_dword(dev_priv->bridge_dev, reg,
1152                                lower_32_bits(dev_priv->mch_res.start));
1153         return 0;
1154 }
1155
1156 /* Setup MCHBAR if possible, return true if we should disable it again */
1157 static void
1158 intel_setup_mchbar(struct drm_device *dev)
1159 {
1160         drm_i915_private_t *dev_priv = dev->dev_private;
1161         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1162         u32 temp;
1163         bool enabled;
1164
1165         dev_priv->mchbar_need_disable = false;
1166
1167         if (IS_I915G(dev) || IS_I915GM(dev)) {
1168                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1169                 enabled = !!(temp & DEVEN_MCHBAR_EN);
1170         } else {
1171                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1172                 enabled = temp & 1;
1173         }
1174
1175         /* If it's already enabled, don't have to do anything */
1176         if (enabled)
1177                 return;
1178
1179         if (intel_alloc_mchbar_resource(dev))
1180                 return;
1181
1182         dev_priv->mchbar_need_disable = true;
1183
1184         /* Space is allocated or reserved, so enable it. */
1185         if (IS_I915G(dev) || IS_I915GM(dev)) {
1186                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1187                                        temp | DEVEN_MCHBAR_EN);
1188         } else {
1189                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1190                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1191         }
1192 }
1193
1194 static void
1195 intel_teardown_mchbar(struct drm_device *dev)
1196 {
1197         drm_i915_private_t *dev_priv = dev->dev_private;
1198         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1199         u32 temp;
1200
1201         if (dev_priv->mchbar_need_disable) {
1202                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1203                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1204                         temp &= ~DEVEN_MCHBAR_EN;
1205                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1206                 } else {
1207                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1208                         temp &= ~1;
1209                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1210                 }
1211         }
1212
1213         if (dev_priv->mch_res.start)
1214                 release_resource(&dev_priv->mch_res);
1215 }
1216
1217 /* true = enable decode, false = disable decoder */
1218 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1219 {
1220         struct drm_device *dev = cookie;
1221
1222         intel_modeset_vga_set_state(dev, state);
1223         if (state)
1224                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1225                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1226         else
1227                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1228 }
1229
1230 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1231 {
1232         struct drm_device *dev = pci_get_drvdata(pdev);
1233         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1234         if (state == VGA_SWITCHEROO_ON) {
1235                 pr_info("switched on\n");
1236                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1237                 /* i915 resume handler doesn't set to D0 */
1238                 pci_set_power_state(dev->pdev, PCI_D0);
1239                 i915_resume(dev);
1240                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1241         } else {
1242                 pr_err("switched off\n");
1243                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1244                 i915_suspend(dev, pmm);
1245                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1246         }
1247 }
1248
1249 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1250 {
1251         struct drm_device *dev = pci_get_drvdata(pdev);
1252         bool can_switch;
1253
1254         spin_lock(&dev->count_lock);
1255         can_switch = (dev->open_count == 0);
1256         spin_unlock(&dev->count_lock);
1257         return can_switch;
1258 }
1259
1260 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1261         .set_gpu_state = i915_switcheroo_set_state,
1262         .reprobe = NULL,
1263         .can_switch = i915_switcheroo_can_switch,
1264 };
1265
1266 static int i915_load_modeset_init(struct drm_device *dev)
1267 {
1268         struct drm_i915_private *dev_priv = dev->dev_private;
1269         int ret;
1270
1271         ret = intel_parse_bios(dev);
1272         if (ret)
1273                 DRM_INFO("failed to find VBIOS tables\n");
1274
1275         /* If we have > 1 VGA cards, then we need to arbitrate access
1276          * to the common VGA resources.
1277          *
1278          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1279          * then we do not take part in VGA arbitration and the
1280          * vga_client_register() fails with -ENODEV.
1281          */
1282         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1283         if (ret && ret != -ENODEV)
1284                 goto out;
1285
1286         intel_register_dsm_handler();
1287
1288         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1289         if (ret)
1290                 goto cleanup_vga_client;
1291
1292         /* Initialise stolen first so that we may reserve preallocated
1293          * objects for the BIOS to KMS transition.
1294          */
1295         ret = i915_gem_init_stolen(dev);
1296         if (ret)
1297                 goto cleanup_vga_switcheroo;
1298
1299         intel_modeset_init(dev);
1300
1301         ret = i915_gem_init(dev);
1302         if (ret)
1303                 goto cleanup_gem_stolen;
1304
1305         intel_modeset_gem_init(dev);
1306
1307         INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1308
1309         ret = drm_irq_install(dev);
1310         if (ret)
1311                 goto cleanup_gem;
1312
1313         /* Always safe in the mode setting case. */
1314         /* FIXME: do pre/post-mode set stuff in core KMS code */
1315         dev->vblank_disable_allowed = 1;
1316
1317         ret = intel_fbdev_init(dev);
1318         if (ret)
1319                 goto cleanup_irq;
1320
1321         drm_kms_helper_poll_init(dev);
1322
1323         /* We're off and running w/KMS */
1324         dev_priv->mm.suspended = 0;
1325
1326         return 0;
1327
1328 cleanup_irq:
1329         drm_irq_uninstall(dev);
1330 cleanup_gem:
1331         mutex_lock(&dev->struct_mutex);
1332         i915_gem_cleanup_ringbuffer(dev);
1333         mutex_unlock(&dev->struct_mutex);
1334         i915_gem_cleanup_aliasing_ppgtt(dev);
1335 cleanup_gem_stolen:
1336         i915_gem_cleanup_stolen(dev);
1337 cleanup_vga_switcheroo:
1338         vga_switcheroo_unregister_client(dev->pdev);
1339 cleanup_vga_client:
1340         vga_client_register(dev->pdev, NULL, NULL, NULL);
1341 out:
1342         return ret;
1343 }
1344
1345 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1346 {
1347         struct drm_i915_master_private *master_priv;
1348
1349         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1350         if (!master_priv)
1351                 return -ENOMEM;
1352
1353         master->driver_priv = master_priv;
1354         return 0;
1355 }
1356
1357 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1358 {
1359         struct drm_i915_master_private *master_priv = master->driver_priv;
1360
1361         if (!master_priv)
1362                 return;
1363
1364         kfree(master_priv);
1365
1366         master->driver_priv = NULL;
1367 }
1368
1369 static void
1370 i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1371                 unsigned long size)
1372 {
1373         dev_priv->mm.gtt_mtrr = -1;
1374
1375 #if defined(CONFIG_X86_PAT)
1376         if (cpu_has_pat)
1377                 return;
1378 #endif
1379
1380         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1381          * one would think, because the kernel disables PAT on first
1382          * generation Core chips because WC PAT gets overridden by a UC
1383          * MTRR if present.  Even if a UC MTRR isn't present.
1384          */
1385         dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
1386         if (dev_priv->mm.gtt_mtrr < 0) {
1387                 DRM_INFO("MTRR allocation failed.  Graphics "
1388                          "performance may suffer.\n");
1389         }
1390 }
1391
1392 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1393 {
1394         struct apertures_struct *ap;
1395         struct pci_dev *pdev = dev_priv->dev->pdev;
1396         bool primary;
1397
1398         ap = alloc_apertures(1);
1399         if (!ap)
1400                 return;
1401
1402         ap->ranges[0].base = dev_priv->mm.gtt->gma_bus_addr;
1403         ap->ranges[0].size =
1404                 dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1405         primary =
1406                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1407
1408         remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1409
1410         kfree(ap);
1411 }
1412
1413 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1414 {
1415         const struct intel_device_info *info = dev_priv->info;
1416
1417 #define DEV_INFO_FLAG(name) info->name ? #name "," : ""
1418 #define DEV_INFO_SEP ,
1419         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1420                          "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
1421                          info->gen,
1422                          dev_priv->dev->pdev->device,
1423                          DEV_INFO_FLAGS);
1424 #undef DEV_INFO_FLAG
1425 #undef DEV_INFO_SEP
1426 }
1427
1428 /**
1429  * i915_driver_load - setup chip and create an initial config
1430  * @dev: DRM device
1431  * @flags: startup flags
1432  *
1433  * The driver load routine has to do several things:
1434  *   - drive output discovery via intel_modeset_init()
1435  *   - initialize the memory manager
1436  *   - allocate initial config memory
1437  *   - setup the DRM framebuffer with the allocated memory
1438  */
1439 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1440 {
1441         struct drm_i915_private *dev_priv;
1442         struct intel_device_info *info;
1443         int ret = 0, mmio_bar, mmio_size;
1444         uint32_t aperture_size;
1445
1446         info = (struct intel_device_info *) flags;
1447
1448         /* Refuse to load on gen6+ without kms enabled. */
1449         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1450                 return -ENODEV;
1451
1452         /* i915 has 4 more counters */
1453         dev->counters += 4;
1454         dev->types[6] = _DRM_STAT_IRQ;
1455         dev->types[7] = _DRM_STAT_PRIMARY;
1456         dev->types[8] = _DRM_STAT_SECONDARY;
1457         dev->types[9] = _DRM_STAT_DMA;
1458
1459         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1460         if (dev_priv == NULL)
1461                 return -ENOMEM;
1462
1463         dev->dev_private = (void *)dev_priv;
1464         dev_priv->dev = dev;
1465         dev_priv->info = info;
1466
1467         i915_dump_device_info(dev_priv);
1468
1469         if (i915_get_bridge_dev(dev)) {
1470                 ret = -EIO;
1471                 goto free_priv;
1472         }
1473
1474         ret = i915_gem_gtt_init(dev);
1475         if (ret)
1476                 goto put_bridge;
1477
1478         if (drm_core_check_feature(dev, DRIVER_MODESET))
1479                 i915_kick_out_firmware_fb(dev_priv);
1480
1481         pci_set_master(dev->pdev);
1482
1483         /* overlay on gen2 is broken and can't address above 1G */
1484         if (IS_GEN2(dev))
1485                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1486
1487         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1488          * using 32bit addressing, overwriting memory if HWS is located
1489          * above 4GB.
1490          *
1491          * The documentation also mentions an issue with undefined
1492          * behaviour if any general state is accessed within a page above 4GB,
1493          * which also needs to be handled carefully.
1494          */
1495         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1496                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1497
1498         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1499         /* Before gen4, the registers and the GTT are behind different BARs.
1500          * However, from gen4 onwards, the registers and the GTT are shared
1501          * in the same BAR, so we want to restrict this ioremap from
1502          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1503          * the register BAR remains the same size for all the earlier
1504          * generations up to Ironlake.
1505          */
1506         if (info->gen < 5)
1507                 mmio_size = 512*1024;
1508         else
1509                 mmio_size = 2*1024*1024;
1510
1511         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1512         if (!dev_priv->regs) {
1513                 DRM_ERROR("failed to map registers\n");
1514                 ret = -EIO;
1515                 goto put_gmch;
1516         }
1517
1518         aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1519         dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr;
1520
1521         dev_priv->mm.gtt_mapping =
1522                 io_mapping_create_wc(dev_priv->mm.gtt_base_addr,
1523                                      aperture_size);
1524         if (dev_priv->mm.gtt_mapping == NULL) {
1525                 ret = -EIO;
1526                 goto out_rmmap;
1527         }
1528
1529         i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr,
1530                         aperture_size);
1531
1532         /* The i915 workqueue is primarily used for batched retirement of
1533          * requests (and thus managing bo) once the task has been completed
1534          * by the GPU. i915_gem_retire_requests() is called directly when we
1535          * need high-priority retirement, such as waiting for an explicit
1536          * bo.
1537          *
1538          * It is also used for periodic low-priority events, such as
1539          * idle-timers and recording error state.
1540          *
1541          * All tasks on the workqueue are expected to acquire the dev mutex
1542          * so there is no point in running more than one instance of the
1543          * workqueue at any time.  Use an ordered one.
1544          */
1545         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1546         if (dev_priv->wq == NULL) {
1547                 DRM_ERROR("Failed to create our workqueue.\n");
1548                 ret = -ENOMEM;
1549                 goto out_mtrrfree;
1550         }
1551
1552         /* This must be called before any calls to HAS_PCH_* */
1553         intel_detect_pch(dev);
1554
1555         intel_irq_init(dev);
1556         intel_gt_init(dev);
1557
1558         /* Try to make sure MCHBAR is enabled before poking at it */
1559         intel_setup_mchbar(dev);
1560         intel_setup_gmbus(dev);
1561         intel_opregion_setup(dev);
1562
1563         intel_setup_bios(dev);
1564
1565         i915_gem_load(dev);
1566
1567         /* On the 945G/GM, the chipset reports the MSI capability on the
1568          * integrated graphics even though the support isn't actually there
1569          * according to the published specs.  It doesn't appear to function
1570          * correctly in testing on 945G.
1571          * This may be a side effect of MSI having been made available for PEG
1572          * and the registers being closely associated.
1573          *
1574          * According to chipset errata, on the 965GM, MSI interrupts may
1575          * be lost or delayed, but we use them anyways to avoid
1576          * stuck interrupts on some machines.
1577          */
1578         if (!IS_I945G(dev) && !IS_I945GM(dev))
1579                 pci_enable_msi(dev->pdev);
1580
1581         spin_lock_init(&dev_priv->irq_lock);
1582         spin_lock_init(&dev_priv->error_lock);
1583         spin_lock_init(&dev_priv->rps.lock);
1584         spin_lock_init(&dev_priv->dpio_lock);
1585
1586         mutex_init(&dev_priv->rps.hw_lock);
1587
1588         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1589                 dev_priv->num_pipe = 3;
1590         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1591                 dev_priv->num_pipe = 2;
1592         else
1593                 dev_priv->num_pipe = 1;
1594
1595         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1596         if (ret)
1597                 goto out_gem_unload;
1598
1599         /* Start out suspended */
1600         dev_priv->mm.suspended = 1;
1601
1602         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1603                 ret = i915_load_modeset_init(dev);
1604                 if (ret < 0) {
1605                         DRM_ERROR("failed to init modeset\n");
1606                         goto out_gem_unload;
1607                 }
1608         }
1609
1610         i915_setup_sysfs(dev);
1611
1612         /* Must be done after probing outputs */
1613         intel_opregion_init(dev);
1614         acpi_video_register();
1615
1616         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1617                     (unsigned long) dev);
1618
1619         if (IS_GEN5(dev))
1620                 intel_gpu_ips_init(dev_priv);
1621
1622         return 0;
1623
1624 out_gem_unload:
1625         if (dev_priv->mm.inactive_shrinker.shrink)
1626                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1627
1628         if (dev->pdev->msi_enabled)
1629                 pci_disable_msi(dev->pdev);
1630
1631         intel_teardown_gmbus(dev);
1632         intel_teardown_mchbar(dev);
1633         destroy_workqueue(dev_priv->wq);
1634 out_mtrrfree:
1635         if (dev_priv->mm.gtt_mtrr >= 0) {
1636                 mtrr_del(dev_priv->mm.gtt_mtrr,
1637                          dev_priv->mm.gtt_base_addr,
1638                          aperture_size);
1639                 dev_priv->mm.gtt_mtrr = -1;
1640         }
1641         io_mapping_free(dev_priv->mm.gtt_mapping);
1642 out_rmmap:
1643         pci_iounmap(dev->pdev, dev_priv->regs);
1644 put_gmch:
1645         i915_gem_gtt_fini(dev);
1646 put_bridge:
1647         pci_dev_put(dev_priv->bridge_dev);
1648 free_priv:
1649         kfree(dev_priv);
1650         return ret;
1651 }
1652
1653 int i915_driver_unload(struct drm_device *dev)
1654 {
1655         struct drm_i915_private *dev_priv = dev->dev_private;
1656         int ret;
1657
1658         intel_gpu_ips_teardown();
1659
1660         i915_teardown_sysfs(dev);
1661
1662         if (dev_priv->mm.inactive_shrinker.shrink)
1663                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1664
1665         mutex_lock(&dev->struct_mutex);
1666         ret = i915_gpu_idle(dev);
1667         if (ret)
1668                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1669         i915_gem_retire_requests(dev);
1670         mutex_unlock(&dev->struct_mutex);
1671
1672         /* Cancel the retire work handler, which should be idle now. */
1673         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1674
1675         io_mapping_free(dev_priv->mm.gtt_mapping);
1676         if (dev_priv->mm.gtt_mtrr >= 0) {
1677                 mtrr_del(dev_priv->mm.gtt_mtrr,
1678                          dev_priv->mm.gtt_base_addr,
1679                          dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);
1680                 dev_priv->mm.gtt_mtrr = -1;
1681         }
1682
1683         acpi_video_unregister();
1684
1685         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1686                 intel_fbdev_fini(dev);
1687                 intel_modeset_cleanup(dev);
1688                 cancel_work_sync(&dev_priv->console_resume_work);
1689
1690                 /*
1691                  * free the memory space allocated for the child device
1692                  * config parsed from VBT
1693                  */
1694                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1695                         kfree(dev_priv->child_dev);
1696                         dev_priv->child_dev = NULL;
1697                         dev_priv->child_dev_num = 0;
1698                 }
1699
1700                 vga_switcheroo_unregister_client(dev->pdev);
1701                 vga_client_register(dev->pdev, NULL, NULL, NULL);
1702         }
1703
1704         /* Free error state after interrupts are fully disabled. */
1705         del_timer_sync(&dev_priv->hangcheck_timer);
1706         cancel_work_sync(&dev_priv->error_work);
1707         i915_destroy_error_state(dev);
1708
1709         if (dev->pdev->msi_enabled)
1710                 pci_disable_msi(dev->pdev);
1711
1712         intel_opregion_fini(dev);
1713
1714         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1715                 /* Flush any outstanding unpin_work. */
1716                 flush_workqueue(dev_priv->wq);
1717
1718                 mutex_lock(&dev->struct_mutex);
1719                 i915_gem_free_all_phys_object(dev);
1720                 i915_gem_cleanup_ringbuffer(dev);
1721                 i915_gem_context_fini(dev);
1722                 mutex_unlock(&dev->struct_mutex);
1723                 i915_gem_cleanup_aliasing_ppgtt(dev);
1724                 i915_gem_cleanup_stolen(dev);
1725                 drm_mm_takedown(&dev_priv->mm.stolen);
1726
1727                 intel_cleanup_overlay(dev);
1728
1729                 if (!I915_NEED_GFX_HWS(dev))
1730                         i915_free_hws(dev);
1731         }
1732
1733         if (dev_priv->regs != NULL)
1734                 pci_iounmap(dev->pdev, dev_priv->regs);
1735
1736         intel_teardown_gmbus(dev);
1737         intel_teardown_mchbar(dev);
1738
1739         destroy_workqueue(dev_priv->wq);
1740
1741         pci_dev_put(dev_priv->bridge_dev);
1742         kfree(dev->dev_private);
1743
1744         return 0;
1745 }
1746
1747 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1748 {
1749         struct drm_i915_file_private *file_priv;
1750
1751         DRM_DEBUG_DRIVER("\n");
1752         file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
1753         if (!file_priv)
1754                 return -ENOMEM;
1755
1756         file->driver_priv = file_priv;
1757
1758         spin_lock_init(&file_priv->mm.lock);
1759         INIT_LIST_HEAD(&file_priv->mm.request_list);
1760
1761         idr_init(&file_priv->context_idr);
1762
1763         return 0;
1764 }
1765
1766 /**
1767  * i915_driver_lastclose - clean up after all DRM clients have exited
1768  * @dev: DRM device
1769  *
1770  * Take care of cleaning up after all DRM clients have exited.  In the
1771  * mode setting case, we want to restore the kernel's initial mode (just
1772  * in case the last client left us in a bad state).
1773  *
1774  * Additionally, in the non-mode setting case, we'll tear down the GTT
1775  * and DMA structures, since the kernel won't be using them, and clea
1776  * up any GEM state.
1777  */
1778 void i915_driver_lastclose(struct drm_device * dev)
1779 {
1780         drm_i915_private_t *dev_priv = dev->dev_private;
1781
1782         /* On gen6+ we refuse to init without kms enabled, but then the drm core
1783          * goes right around and calls lastclose. Check for this and don't clean
1784          * up anything. */
1785         if (!dev_priv)
1786                 return;
1787
1788         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1789                 intel_fb_restore_mode(dev);
1790                 vga_switcheroo_process_delayed_switch();
1791                 return;
1792         }
1793
1794         i915_gem_lastclose(dev);
1795
1796         i915_dma_cleanup(dev);
1797 }
1798
1799 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1800 {
1801         i915_gem_context_close(dev, file_priv);
1802         i915_gem_release(dev, file_priv);
1803 }
1804
1805 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1806 {
1807         struct drm_i915_file_private *file_priv = file->driver_priv;
1808
1809         kfree(file_priv);
1810 }
1811
1812 struct drm_ioctl_desc i915_ioctls[] = {
1813         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1814         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1815         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1816         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1817         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1818         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1819         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1820         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1821         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1822         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1823         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1824         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1825         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1826         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1827         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
1828         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1829         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1830         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1831         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1832         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1833         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1834         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1835         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1836         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1837         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1838         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1839         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1840         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1841         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1842         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1843         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1844         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1845         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1846         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1847         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1848         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1849         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1850         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1851         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1852         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1853         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1854         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1855         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1856         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1857         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1858         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1859         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1860         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
1861 };
1862
1863 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1864
1865 /*
1866  * This is really ugly: Because old userspace abused the linux agp interface to
1867  * manage the gtt, we need to claim that all intel devices are agp.  For
1868  * otherwise the drm core refuses to initialize the agp support code.
1869  */
1870 int i915_driver_device_is_agp(struct drm_device * dev)
1871 {
1872         return 1;
1873 }