1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
36 #include "i915_trace.h"
37 #include "../../../platform/x86/intel_ips.h"
38 #include <linux/pci.h>
39 #include <linux/vgaarb.h>
40 #include <linux/acpi.h>
41 #include <linux/pnp.h>
42 #include <linux/vga_switcheroo.h>
43 #include <linux/slab.h>
44 #include <acpi/video.h>
46 static void i915_write_hws_pga(struct drm_device *dev)
48 drm_i915_private_t *dev_priv = dev->dev_private;
51 addr = dev_priv->status_page_dmah->busaddr;
52 if (INTEL_INFO(dev)->gen >= 4)
53 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
54 I915_WRITE(HWS_PGA, addr);
58 * Sets up the hardware status page for devices that need a physical address
61 static int i915_init_phys_hws(struct drm_device *dev)
63 drm_i915_private_t *dev_priv = dev->dev_private;
64 struct intel_ring_buffer *ring = LP_RING(dev_priv);
66 /* Program Hardware Status Page */
67 dev_priv->status_page_dmah =
68 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
70 if (!dev_priv->status_page_dmah) {
71 DRM_ERROR("Can not allocate hardware status page\n");
74 ring->status_page.page_addr =
75 (void __force __iomem *)dev_priv->status_page_dmah->vaddr;
77 memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
79 i915_write_hws_pga(dev);
81 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
86 * Frees the hardware status page, whether it's a physical address or a virtual
87 * address set up by the X Server.
89 static void i915_free_hws(struct drm_device *dev)
91 drm_i915_private_t *dev_priv = dev->dev_private;
92 struct intel_ring_buffer *ring = LP_RING(dev_priv);
94 if (dev_priv->status_page_dmah) {
95 drm_pci_free(dev, dev_priv->status_page_dmah);
96 dev_priv->status_page_dmah = NULL;
99 if (ring->status_page.gfx_addr) {
100 ring->status_page.gfx_addr = 0;
101 drm_core_ioremapfree(&dev_priv->hws_map, dev);
104 /* Need to rewrite hardware status page */
105 I915_WRITE(HWS_PGA, 0x1ffff000);
108 void i915_kernel_lost_context(struct drm_device * dev)
110 drm_i915_private_t *dev_priv = dev->dev_private;
111 struct drm_i915_master_private *master_priv;
112 struct intel_ring_buffer *ring = LP_RING(dev_priv);
115 * We should never lose context on the ring with modesetting
116 * as we don't expose it to userspace
118 if (drm_core_check_feature(dev, DRIVER_MODESET))
121 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
122 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
123 ring->space = ring->head - (ring->tail + 8);
125 ring->space += ring->size;
127 if (!dev->primary->master)
130 master_priv = dev->primary->master->driver_priv;
131 if (ring->head == ring->tail && master_priv->sarea_priv)
132 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
135 static int i915_dma_cleanup(struct drm_device * dev)
137 drm_i915_private_t *dev_priv = dev->dev_private;
140 /* Make sure interrupts are disabled here because the uninstall ioctl
141 * may not have been called from userspace and after dev_private
142 * is freed, it's too late.
144 if (dev->irq_enabled)
145 drm_irq_uninstall(dev);
147 mutex_lock(&dev->struct_mutex);
148 for (i = 0; i < I915_NUM_RINGS; i++)
149 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
150 mutex_unlock(&dev->struct_mutex);
152 /* Clear the HWS virtual address at teardown */
153 if (I915_NEED_GFX_HWS(dev))
159 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
161 drm_i915_private_t *dev_priv = dev->dev_private;
162 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
165 master_priv->sarea = drm_getsarea(dev);
166 if (master_priv->sarea) {
167 master_priv->sarea_priv = (drm_i915_sarea_t *)
168 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
170 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
173 if (init->ring_size != 0) {
174 if (LP_RING(dev_priv)->obj != NULL) {
175 i915_dma_cleanup(dev);
176 DRM_ERROR("Client tried to initialize ringbuffer in "
181 ret = intel_render_ring_init_dri(dev,
185 i915_dma_cleanup(dev);
190 dev_priv->cpp = init->cpp;
191 dev_priv->back_offset = init->back_offset;
192 dev_priv->front_offset = init->front_offset;
193 dev_priv->current_page = 0;
194 if (master_priv->sarea_priv)
195 master_priv->sarea_priv->pf_current_page = 0;
197 /* Allow hardware batchbuffers unless told otherwise.
199 dev_priv->allow_batchbuffer = 1;
204 static int i915_dma_resume(struct drm_device * dev)
206 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
207 struct intel_ring_buffer *ring = LP_RING(dev_priv);
209 DRM_DEBUG_DRIVER("%s\n", __func__);
211 if (ring->map.handle == NULL) {
212 DRM_ERROR("can not ioremap virtual address for"
217 /* Program Hardware Status Page */
218 if (!ring->status_page.page_addr) {
219 DRM_ERROR("Can not find hardware status page\n");
222 DRM_DEBUG_DRIVER("hw status page @ %p\n",
223 ring->status_page.page_addr);
224 if (ring->status_page.gfx_addr != 0)
225 intel_ring_setup_status_page(ring);
227 i915_write_hws_pga(dev);
229 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
234 static int i915_dma_init(struct drm_device *dev, void *data,
235 struct drm_file *file_priv)
237 drm_i915_init_t *init = data;
240 switch (init->func) {
242 retcode = i915_initialize(dev, init);
244 case I915_CLEANUP_DMA:
245 retcode = i915_dma_cleanup(dev);
247 case I915_RESUME_DMA:
248 retcode = i915_dma_resume(dev);
258 /* Implement basically the same security restrictions as hardware does
259 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
261 * Most of the calculations below involve calculating the size of a
262 * particular instruction. It's important to get the size right as
263 * that tells us where the next instruction to check is. Any illegal
264 * instruction detected will be given a size of zero, which is a
265 * signal to abort the rest of the buffer.
267 static int validate_cmd(int cmd)
269 switch (((cmd >> 29) & 0x7)) {
271 switch ((cmd >> 23) & 0x3f) {
273 return 1; /* MI_NOOP */
275 return 1; /* MI_FLUSH */
277 return 0; /* disallow everything else */
281 return 0; /* reserved */
283 return (cmd & 0xff) + 2; /* 2d commands */
285 if (((cmd >> 24) & 0x1f) <= 0x18)
288 switch ((cmd >> 24) & 0x1f) {
292 switch ((cmd >> 16) & 0xff) {
294 return (cmd & 0x1f) + 2;
296 return (cmd & 0xf) + 2;
298 return (cmd & 0xffff) + 2;
302 return (cmd & 0xffff) + 1;
306 if ((cmd & (1 << 23)) == 0) /* inline vertices */
307 return (cmd & 0x1ffff) + 2;
308 else if (cmd & (1 << 17)) /* indirect random */
309 if ((cmd & 0xffff) == 0)
310 return 0; /* unknown length, too hard */
312 return (((cmd & 0xffff) + 1) / 2) + 1;
314 return 2; /* indirect sequential */
325 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
327 drm_i915_private_t *dev_priv = dev->dev_private;
330 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
333 for (i = 0; i < dwords;) {
334 int sz = validate_cmd(buffer[i]);
335 if (sz == 0 || i + sz > dwords)
340 ret = BEGIN_LP_RING((dwords+1)&~1);
344 for (i = 0; i < dwords; i++)
355 i915_emit_box(struct drm_device *dev,
356 struct drm_clip_rect *box,
359 struct drm_i915_private *dev_priv = dev->dev_private;
362 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
363 box->y2 <= 0 || box->x2 <= 0) {
364 DRM_ERROR("Bad box %d,%d..%d,%d\n",
365 box->x1, box->y1, box->x2, box->y2);
369 if (INTEL_INFO(dev)->gen >= 4) {
370 ret = BEGIN_LP_RING(4);
374 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
375 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
376 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
379 ret = BEGIN_LP_RING(6);
383 OUT_RING(GFX_OP_DRAWRECT_INFO);
385 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
386 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
395 /* XXX: Emitting the counter should really be moved to part of the IRQ
396 * emit. For now, do it in both places:
399 static void i915_emit_breadcrumb(struct drm_device *dev)
401 drm_i915_private_t *dev_priv = dev->dev_private;
402 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
405 if (dev_priv->counter > 0x7FFFFFFFUL)
406 dev_priv->counter = 0;
407 if (master_priv->sarea_priv)
408 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
410 if (BEGIN_LP_RING(4) == 0) {
411 OUT_RING(MI_STORE_DWORD_INDEX);
412 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
413 OUT_RING(dev_priv->counter);
419 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
420 drm_i915_cmdbuffer_t *cmd,
421 struct drm_clip_rect *cliprects,
424 int nbox = cmd->num_cliprects;
425 int i = 0, count, ret;
428 DRM_ERROR("alignment");
432 i915_kernel_lost_context(dev);
434 count = nbox ? nbox : 1;
436 for (i = 0; i < count; i++) {
438 ret = i915_emit_box(dev, &cliprects[i],
444 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
449 i915_emit_breadcrumb(dev);
453 static int i915_dispatch_batchbuffer(struct drm_device * dev,
454 drm_i915_batchbuffer_t * batch,
455 struct drm_clip_rect *cliprects)
457 struct drm_i915_private *dev_priv = dev->dev_private;
458 int nbox = batch->num_cliprects;
461 if ((batch->start | batch->used) & 0x7) {
462 DRM_ERROR("alignment");
466 i915_kernel_lost_context(dev);
468 count = nbox ? nbox : 1;
469 for (i = 0; i < count; i++) {
471 ret = i915_emit_box(dev, &cliprects[i],
472 batch->DR1, batch->DR4);
477 if (!IS_I830(dev) && !IS_845G(dev)) {
478 ret = BEGIN_LP_RING(2);
482 if (INTEL_INFO(dev)->gen >= 4) {
483 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
484 OUT_RING(batch->start);
486 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
487 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
490 ret = BEGIN_LP_RING(4);
494 OUT_RING(MI_BATCH_BUFFER);
495 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
496 OUT_RING(batch->start + batch->used - 4);
503 if (IS_G4X(dev) || IS_GEN5(dev)) {
504 if (BEGIN_LP_RING(2) == 0) {
505 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
511 i915_emit_breadcrumb(dev);
515 static int i915_dispatch_flip(struct drm_device * dev)
517 drm_i915_private_t *dev_priv = dev->dev_private;
518 struct drm_i915_master_private *master_priv =
519 dev->primary->master->driver_priv;
522 if (!master_priv->sarea_priv)
525 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
527 dev_priv->current_page,
528 master_priv->sarea_priv->pf_current_page);
530 i915_kernel_lost_context(dev);
532 ret = BEGIN_LP_RING(10);
536 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
539 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
541 if (dev_priv->current_page == 0) {
542 OUT_RING(dev_priv->back_offset);
543 dev_priv->current_page = 1;
545 OUT_RING(dev_priv->front_offset);
546 dev_priv->current_page = 0;
550 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
555 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
557 if (BEGIN_LP_RING(4) == 0) {
558 OUT_RING(MI_STORE_DWORD_INDEX);
559 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
560 OUT_RING(dev_priv->counter);
565 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
569 static int i915_quiescent(struct drm_device *dev)
571 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
573 i915_kernel_lost_context(dev);
574 return intel_wait_ring_idle(ring);
577 static int i915_flush_ioctl(struct drm_device *dev, void *data,
578 struct drm_file *file_priv)
582 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
584 mutex_lock(&dev->struct_mutex);
585 ret = i915_quiescent(dev);
586 mutex_unlock(&dev->struct_mutex);
591 static int i915_batchbuffer(struct drm_device *dev, void *data,
592 struct drm_file *file_priv)
594 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
595 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
596 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
597 master_priv->sarea_priv;
598 drm_i915_batchbuffer_t *batch = data;
600 struct drm_clip_rect *cliprects = NULL;
602 if (!dev_priv->allow_batchbuffer) {
603 DRM_ERROR("Batchbuffer ioctl disabled\n");
607 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
608 batch->start, batch->used, batch->num_cliprects);
610 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
612 if (batch->num_cliprects < 0)
615 if (batch->num_cliprects) {
616 cliprects = kcalloc(batch->num_cliprects,
617 sizeof(struct drm_clip_rect),
619 if (cliprects == NULL)
622 ret = copy_from_user(cliprects, batch->cliprects,
623 batch->num_cliprects *
624 sizeof(struct drm_clip_rect));
631 mutex_lock(&dev->struct_mutex);
632 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
633 mutex_unlock(&dev->struct_mutex);
636 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
644 static int i915_cmdbuffer(struct drm_device *dev, void *data,
645 struct drm_file *file_priv)
647 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
648 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
649 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
650 master_priv->sarea_priv;
651 drm_i915_cmdbuffer_t *cmdbuf = data;
652 struct drm_clip_rect *cliprects = NULL;
656 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
657 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
659 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
661 if (cmdbuf->num_cliprects < 0)
664 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
665 if (batch_data == NULL)
668 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
671 goto fail_batch_free;
674 if (cmdbuf->num_cliprects) {
675 cliprects = kcalloc(cmdbuf->num_cliprects,
676 sizeof(struct drm_clip_rect), GFP_KERNEL);
677 if (cliprects == NULL) {
679 goto fail_batch_free;
682 ret = copy_from_user(cliprects, cmdbuf->cliprects,
683 cmdbuf->num_cliprects *
684 sizeof(struct drm_clip_rect));
691 mutex_lock(&dev->struct_mutex);
692 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
693 mutex_unlock(&dev->struct_mutex);
695 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
700 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
710 static int i915_flip_bufs(struct drm_device *dev, void *data,
711 struct drm_file *file_priv)
715 DRM_DEBUG_DRIVER("%s\n", __func__);
717 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
719 mutex_lock(&dev->struct_mutex);
720 ret = i915_dispatch_flip(dev);
721 mutex_unlock(&dev->struct_mutex);
726 static int i915_getparam(struct drm_device *dev, void *data,
727 struct drm_file *file_priv)
729 drm_i915_private_t *dev_priv = dev->dev_private;
730 drm_i915_getparam_t *param = data;
734 DRM_ERROR("called with no initialization\n");
738 switch (param->param) {
739 case I915_PARAM_IRQ_ACTIVE:
740 value = dev->pdev->irq ? 1 : 0;
742 case I915_PARAM_ALLOW_BATCHBUFFER:
743 value = dev_priv->allow_batchbuffer ? 1 : 0;
745 case I915_PARAM_LAST_DISPATCH:
746 value = READ_BREADCRUMB(dev_priv);
748 case I915_PARAM_CHIPSET_ID:
749 value = dev->pci_device;
751 case I915_PARAM_HAS_GEM:
752 value = dev_priv->has_gem;
754 case I915_PARAM_NUM_FENCES_AVAIL:
755 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
757 case I915_PARAM_HAS_OVERLAY:
758 value = dev_priv->overlay ? 1 : 0;
760 case I915_PARAM_HAS_PAGEFLIPPING:
763 case I915_PARAM_HAS_EXECBUF2:
765 value = dev_priv->has_gem;
767 case I915_PARAM_HAS_BSD:
768 value = HAS_BSD(dev);
770 case I915_PARAM_HAS_BLT:
771 value = HAS_BLT(dev);
773 case I915_PARAM_HAS_RELAXED_FENCING:
776 case I915_PARAM_HAS_COHERENT_RINGS:
779 case I915_PARAM_HAS_EXEC_CONSTANTS:
780 value = INTEL_INFO(dev)->gen >= 4;
782 case I915_PARAM_HAS_RELAXED_DELTA:
786 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
791 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
792 DRM_ERROR("DRM_COPY_TO_USER failed\n");
799 static int i915_setparam(struct drm_device *dev, void *data,
800 struct drm_file *file_priv)
802 drm_i915_private_t *dev_priv = dev->dev_private;
803 drm_i915_setparam_t *param = data;
806 DRM_ERROR("called with no initialization\n");
810 switch (param->param) {
811 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
813 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
814 dev_priv->tex_lru_log_granularity = param->value;
816 case I915_SETPARAM_ALLOW_BATCHBUFFER:
817 dev_priv->allow_batchbuffer = param->value;
819 case I915_SETPARAM_NUM_USED_FENCES:
820 if (param->value > dev_priv->num_fence_regs ||
823 /* Userspace can use first N regs */
824 dev_priv->fence_reg_start = param->value;
827 DRM_DEBUG_DRIVER("unknown parameter %d\n",
835 static int i915_set_status_page(struct drm_device *dev, void *data,
836 struct drm_file *file_priv)
838 drm_i915_private_t *dev_priv = dev->dev_private;
839 drm_i915_hws_addr_t *hws = data;
840 struct intel_ring_buffer *ring = LP_RING(dev_priv);
842 if (!I915_NEED_GFX_HWS(dev))
846 DRM_ERROR("called with no initialization\n");
850 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
851 WARN(1, "tried to set status page when mode setting active\n");
855 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
857 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
859 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
860 dev_priv->hws_map.size = 4*1024;
861 dev_priv->hws_map.type = 0;
862 dev_priv->hws_map.flags = 0;
863 dev_priv->hws_map.mtrr = 0;
865 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
866 if (dev_priv->hws_map.handle == NULL) {
867 i915_dma_cleanup(dev);
868 ring->status_page.gfx_addr = 0;
869 DRM_ERROR("can not ioremap virtual address for"
870 " G33 hw status page\n");
873 ring->status_page.page_addr =
874 (void __force __iomem *)dev_priv->hws_map.handle;
875 memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
876 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
878 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
879 ring->status_page.gfx_addr);
880 DRM_DEBUG_DRIVER("load hws at %p\n",
881 ring->status_page.page_addr);
885 static int i915_get_bridge_dev(struct drm_device *dev)
887 struct drm_i915_private *dev_priv = dev->dev_private;
889 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
890 if (!dev_priv->bridge_dev) {
891 DRM_ERROR("bridge device not found\n");
897 #define MCHBAR_I915 0x44
898 #define MCHBAR_I965 0x48
899 #define MCHBAR_SIZE (4*4096)
901 #define DEVEN_REG 0x54
902 #define DEVEN_MCHBAR_EN (1 << 28)
904 /* Allocate space for the MCH regs if needed, return nonzero on error */
906 intel_alloc_mchbar_resource(struct drm_device *dev)
908 drm_i915_private_t *dev_priv = dev->dev_private;
909 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
910 u32 temp_lo, temp_hi = 0;
914 if (INTEL_INFO(dev)->gen >= 4)
915 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
916 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
917 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
919 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
922 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
926 /* Get some space for it */
927 dev_priv->mch_res.name = "i915 MCHBAR";
928 dev_priv->mch_res.flags = IORESOURCE_MEM;
929 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
931 MCHBAR_SIZE, MCHBAR_SIZE,
933 0, pcibios_align_resource,
934 dev_priv->bridge_dev);
936 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
937 dev_priv->mch_res.start = 0;
941 if (INTEL_INFO(dev)->gen >= 4)
942 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
943 upper_32_bits(dev_priv->mch_res.start));
945 pci_write_config_dword(dev_priv->bridge_dev, reg,
946 lower_32_bits(dev_priv->mch_res.start));
950 /* Setup MCHBAR if possible, return true if we should disable it again */
952 intel_setup_mchbar(struct drm_device *dev)
954 drm_i915_private_t *dev_priv = dev->dev_private;
955 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
959 dev_priv->mchbar_need_disable = false;
961 if (IS_I915G(dev) || IS_I915GM(dev)) {
962 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
963 enabled = !!(temp & DEVEN_MCHBAR_EN);
965 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
969 /* If it's already enabled, don't have to do anything */
973 if (intel_alloc_mchbar_resource(dev))
976 dev_priv->mchbar_need_disable = true;
978 /* Space is allocated or reserved, so enable it. */
979 if (IS_I915G(dev) || IS_I915GM(dev)) {
980 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
981 temp | DEVEN_MCHBAR_EN);
983 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
984 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
989 intel_teardown_mchbar(struct drm_device *dev)
991 drm_i915_private_t *dev_priv = dev->dev_private;
992 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
995 if (dev_priv->mchbar_need_disable) {
996 if (IS_I915G(dev) || IS_I915GM(dev)) {
997 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
998 temp &= ~DEVEN_MCHBAR_EN;
999 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1001 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1003 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1007 if (dev_priv->mch_res.start)
1008 release_resource(&dev_priv->mch_res);
1011 #define PTE_ADDRESS_MASK 0xfffff000
1012 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1013 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1014 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1015 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
1016 #define PTE_MAPPING_TYPE_MASK (3 << 1)
1017 #define PTE_VALID (1 << 0)
1020 * i915_stolen_to_phys - take an offset into stolen memory and turn it into
1023 * @offset: address to translate
1025 * Some chip functions require allocations from stolen space and need the
1026 * physical address of the memory in question.
1028 static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 struct pci_dev *pdev = dev_priv->bridge_dev;
1035 /* On the machines I have tested the Graphics Base of Stolen Memory
1036 * is unreliable, so compute the base by subtracting the stolen memory
1037 * from the Top of Low Usable DRAM which is where the BIOS places
1038 * the graphics stolen memory.
1040 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1041 /* top 32bits are reserved = 0 */
1042 pci_read_config_dword(pdev, 0xA4, &base);
1044 /* XXX presume 8xx is the same as i915 */
1045 pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
1048 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1050 pci_read_config_word(pdev, 0xb0, &val);
1051 base = val >> 4 << 20;
1054 pci_read_config_byte(pdev, 0x9c, &val);
1055 base = val >> 3 << 27;
1057 base -= dev_priv->mm.gtt->stolen_size;
1060 return base + offset;
1063 static void i915_warn_stolen(struct drm_device *dev)
1065 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1066 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1069 static void i915_setup_compression(struct drm_device *dev, int size)
1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1073 unsigned long cfb_base;
1074 unsigned long ll_base = 0;
1076 compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);
1078 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1082 cfb_base = i915_stolen_to_phys(dev, compressed_fb->start);
1086 if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) {
1087 compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen,
1090 compressed_llb = drm_mm_get_block(compressed_llb,
1092 if (!compressed_llb)
1095 ll_base = i915_stolen_to_phys(dev, compressed_llb->start);
1100 dev_priv->cfb_size = size;
1102 intel_disable_fbc(dev);
1103 dev_priv->compressed_fb = compressed_fb;
1104 if (HAS_PCH_SPLIT(dev))
1105 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1106 else if (IS_GM45(dev)) {
1107 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1109 I915_WRITE(FBC_CFB_BASE, cfb_base);
1110 I915_WRITE(FBC_LL_BASE, ll_base);
1111 dev_priv->compressed_llb = compressed_llb;
1114 DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
1115 cfb_base, ll_base, size >> 20);
1119 drm_mm_put_block(compressed_llb);
1121 drm_mm_put_block(compressed_fb);
1123 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1124 i915_warn_stolen(dev);
1127 static void i915_cleanup_compression(struct drm_device *dev)
1129 struct drm_i915_private *dev_priv = dev->dev_private;
1131 drm_mm_put_block(dev_priv->compressed_fb);
1132 if (dev_priv->compressed_llb)
1133 drm_mm_put_block(dev_priv->compressed_llb);
1136 /* true = enable decode, false = disable decoder */
1137 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1139 struct drm_device *dev = cookie;
1141 intel_modeset_vga_set_state(dev, state);
1143 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1144 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1146 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1149 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1151 struct drm_device *dev = pci_get_drvdata(pdev);
1152 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1153 if (state == VGA_SWITCHEROO_ON) {
1154 printk(KERN_INFO "i915: switched on\n");
1155 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1156 /* i915 resume handler doesn't set to D0 */
1157 pci_set_power_state(dev->pdev, PCI_D0);
1159 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1161 printk(KERN_ERR "i915: switched off\n");
1162 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1163 i915_suspend(dev, pmm);
1164 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1168 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1170 struct drm_device *dev = pci_get_drvdata(pdev);
1173 spin_lock(&dev->count_lock);
1174 can_switch = (dev->open_count == 0);
1175 spin_unlock(&dev->count_lock);
1179 static int i915_load_gem_init(struct drm_device *dev)
1181 struct drm_i915_private *dev_priv = dev->dev_private;
1182 unsigned long prealloc_size, gtt_size, mappable_size;
1185 prealloc_size = dev_priv->mm.gtt->stolen_size;
1186 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1187 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1189 /* Basic memrange allocator for stolen space */
1190 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
1192 /* Let GEM Manage all of the aperture.
1194 * However, leave one page at the end still bound to the scratch page.
1195 * There are a number of places where the hardware apparently
1196 * prefetches past the end of the object, and we've seen multiple
1197 * hangs with the GPU head pointer stuck in a batchbuffer bound
1198 * at the last page of the aperture. One page should be enough to
1199 * keep any prefetching inside of the aperture.
1201 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
1203 mutex_lock(&dev->struct_mutex);
1204 ret = i915_gem_init_ringbuffer(dev);
1205 mutex_unlock(&dev->struct_mutex);
1209 /* Try to set up FBC with a reasonable compressed buffer size */
1210 if (I915_HAS_FBC(dev) && i915_powersave) {
1213 /* Leave 1M for line length buffer & misc. */
1215 /* Try to get a 32M buffer... */
1216 if (prealloc_size > (36*1024*1024))
1217 cfb_size = 32*1024*1024;
1218 else /* fall back to 7/8 of the stolen space */
1219 cfb_size = prealloc_size * 7 / 8;
1220 i915_setup_compression(dev, cfb_size);
1223 /* Allow hardware batchbuffers unless told otherwise. */
1224 dev_priv->allow_batchbuffer = 1;
1228 static int i915_load_modeset_init(struct drm_device *dev)
1230 struct drm_i915_private *dev_priv = dev->dev_private;
1233 ret = intel_parse_bios(dev);
1235 DRM_INFO("failed to find VBIOS tables\n");
1237 /* If we have > 1 VGA cards, then we need to arbitrate access
1238 * to the common VGA resources.
1240 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1241 * then we do not take part in VGA arbitration and the
1242 * vga_client_register() fails with -ENODEV.
1244 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1245 if (ret && ret != -ENODEV)
1248 intel_register_dsm_handler();
1250 ret = vga_switcheroo_register_client(dev->pdev,
1251 i915_switcheroo_set_state,
1253 i915_switcheroo_can_switch);
1255 goto cleanup_vga_client;
1257 /* IIR "flip pending" bit means done if this bit is set */
1258 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1259 dev_priv->flip_pending_is_done = true;
1261 intel_modeset_init(dev);
1263 ret = i915_load_gem_init(dev);
1265 goto cleanup_vga_switcheroo;
1267 intel_modeset_gem_init(dev);
1269 if (HAS_PCH_SPLIT(dev)) {
1270 dev->driver->irq_handler = ironlake_irq_handler;
1271 dev->driver->irq_preinstall = ironlake_irq_preinstall;
1272 dev->driver->irq_postinstall = ironlake_irq_postinstall;
1273 dev->driver->irq_uninstall = ironlake_irq_uninstall;
1274 dev->driver->enable_vblank = ironlake_enable_vblank;
1275 dev->driver->disable_vblank = ironlake_disable_vblank;
1277 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
1278 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
1279 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
1280 dev->driver->irq_handler = i915_driver_irq_handler;
1281 dev->driver->enable_vblank = i915_enable_vblank;
1282 dev->driver->disable_vblank = i915_disable_vblank;
1285 ret = drm_irq_install(dev);
1289 /* Always safe in the mode setting case. */
1290 /* FIXME: do pre/post-mode set stuff in core KMS code */
1291 dev->vblank_disable_allowed = 1;
1293 ret = intel_fbdev_init(dev);
1297 drm_kms_helper_poll_init(dev);
1299 /* We're off and running w/KMS */
1300 dev_priv->mm.suspended = 0;
1305 drm_irq_uninstall(dev);
1307 mutex_lock(&dev->struct_mutex);
1308 i915_gem_cleanup_ringbuffer(dev);
1309 mutex_unlock(&dev->struct_mutex);
1310 cleanup_vga_switcheroo:
1311 vga_switcheroo_unregister_client(dev->pdev);
1313 vga_client_register(dev->pdev, NULL, NULL, NULL);
1318 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1320 struct drm_i915_master_private *master_priv;
1322 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1326 master->driver_priv = master_priv;
1330 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1332 struct drm_i915_master_private *master_priv = master->driver_priv;
1339 master->driver_priv = NULL;
1342 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1344 drm_i915_private_t *dev_priv = dev->dev_private;
1347 tmp = I915_READ(CLKCFG);
1349 switch (tmp & CLKCFG_FSB_MASK) {
1350 case CLKCFG_FSB_533:
1351 dev_priv->fsb_freq = 533; /* 133*4 */
1353 case CLKCFG_FSB_800:
1354 dev_priv->fsb_freq = 800; /* 200*4 */
1356 case CLKCFG_FSB_667:
1357 dev_priv->fsb_freq = 667; /* 167*4 */
1359 case CLKCFG_FSB_400:
1360 dev_priv->fsb_freq = 400; /* 100*4 */
1364 switch (tmp & CLKCFG_MEM_MASK) {
1365 case CLKCFG_MEM_533:
1366 dev_priv->mem_freq = 533;
1368 case CLKCFG_MEM_667:
1369 dev_priv->mem_freq = 667;
1371 case CLKCFG_MEM_800:
1372 dev_priv->mem_freq = 800;
1376 /* detect pineview DDR3 setting */
1377 tmp = I915_READ(CSHRDDR3CTL);
1378 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1381 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1383 drm_i915_private_t *dev_priv = dev->dev_private;
1386 ddrpll = I915_READ16(DDRMPLL1);
1387 csipll = I915_READ16(CSIPLL0);
1389 switch (ddrpll & 0xff) {
1391 dev_priv->mem_freq = 800;
1394 dev_priv->mem_freq = 1066;
1397 dev_priv->mem_freq = 1333;
1400 dev_priv->mem_freq = 1600;
1403 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1405 dev_priv->mem_freq = 0;
1409 dev_priv->r_t = dev_priv->mem_freq;
1411 switch (csipll & 0x3ff) {
1413 dev_priv->fsb_freq = 3200;
1416 dev_priv->fsb_freq = 3733;
1419 dev_priv->fsb_freq = 4266;
1422 dev_priv->fsb_freq = 4800;
1425 dev_priv->fsb_freq = 5333;
1428 dev_priv->fsb_freq = 5866;
1431 dev_priv->fsb_freq = 6400;
1434 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1436 dev_priv->fsb_freq = 0;
1440 if (dev_priv->fsb_freq == 3200) {
1442 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1449 static const struct cparams {
1455 { 1, 1333, 301, 28664 },
1456 { 1, 1066, 294, 24460 },
1457 { 1, 800, 294, 25192 },
1458 { 0, 1333, 276, 27605 },
1459 { 0, 1066, 276, 27605 },
1460 { 0, 800, 231, 23784 },
1463 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1465 u64 total_count, diff, ret;
1466 u32 count1, count2, count3, m = 0, c = 0;
1467 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1470 diff1 = now - dev_priv->last_time1;
1472 count1 = I915_READ(DMIEC);
1473 count2 = I915_READ(DDREC);
1474 count3 = I915_READ(CSIEC);
1476 total_count = count1 + count2 + count3;
1478 /* FIXME: handle per-counter overflow */
1479 if (total_count < dev_priv->last_count1) {
1480 diff = ~0UL - dev_priv->last_count1;
1481 diff += total_count;
1483 diff = total_count - dev_priv->last_count1;
1486 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1487 if (cparams[i].i == dev_priv->c_m &&
1488 cparams[i].t == dev_priv->r_t) {
1495 diff = div_u64(diff, diff1);
1496 ret = ((m * diff) + c);
1497 ret = div_u64(ret, 10);
1499 dev_priv->last_count1 = total_count;
1500 dev_priv->last_time1 = now;
1505 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1507 unsigned long m, x, b;
1510 tsfs = I915_READ(TSFS);
1512 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1513 x = I915_READ8(TR1);
1515 b = tsfs & TSFS_INTR_MASK;
1517 return ((m * x) / 127) - b;
1520 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1522 static const struct v_table {
1523 u16 vd; /* in .1 mil */
1524 u16 vm; /* in .1 mil */
1655 if (dev_priv->info->is_mobile)
1656 return v_table[pxvid].vm;
1658 return v_table[pxvid].vd;
1661 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1663 struct timespec now, diff1;
1665 unsigned long diffms;
1668 getrawmonotonic(&now);
1669 diff1 = timespec_sub(now, dev_priv->last_time2);
1671 /* Don't divide by 0 */
1672 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1676 count = I915_READ(GFXEC);
1678 if (count < dev_priv->last_count2) {
1679 diff = ~0UL - dev_priv->last_count2;
1682 diff = count - dev_priv->last_count2;
1685 dev_priv->last_count2 = count;
1686 dev_priv->last_time2 = now;
1688 /* More magic constants... */
1690 diff = div_u64(diff, diffms * 10);
1691 dev_priv->gfx_power = diff;
1694 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1696 unsigned long t, corr, state1, corr2, state2;
1699 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1700 pxvid = (pxvid >> 24) & 0x7f;
1701 ext_v = pvid_to_extvid(dev_priv, pxvid);
1705 t = i915_mch_val(dev_priv);
1707 /* Revel in the empirically derived constants */
1709 /* Correction factor in 1/100000 units */
1711 corr = ((t * 2349) + 135940);
1713 corr = ((t * 964) + 29317);
1715 corr = ((t * 301) + 1004);
1717 corr = corr * ((150142 * state1) / 10000 - 78642);
1719 corr2 = (corr * dev_priv->corr);
1721 state2 = (corr2 * state1) / 10000;
1722 state2 /= 100; /* convert to mW */
1724 i915_update_gfx_val(dev_priv);
1726 return dev_priv->gfx_power + state2;
1729 /* Global for IPS driver to get at the current i915 device */
1730 static struct drm_i915_private *i915_mch_dev;
1732 * Lock protecting IPS related data structures
1734 * - dev_priv->max_delay
1735 * - dev_priv->min_delay
1737 * - dev_priv->gpu_busy
1739 static DEFINE_SPINLOCK(mchdev_lock);
1742 * i915_read_mch_val - return value for IPS use
1744 * Calculate and return a value for the IPS driver to use when deciding whether
1745 * we have thermal and power headroom to increase CPU or GPU power budget.
1747 unsigned long i915_read_mch_val(void)
1749 struct drm_i915_private *dev_priv;
1750 unsigned long chipset_val, graphics_val, ret = 0;
1752 spin_lock(&mchdev_lock);
1755 dev_priv = i915_mch_dev;
1757 chipset_val = i915_chipset_val(dev_priv);
1758 graphics_val = i915_gfx_val(dev_priv);
1760 ret = chipset_val + graphics_val;
1763 spin_unlock(&mchdev_lock);
1767 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1770 * i915_gpu_raise - raise GPU frequency limit
1772 * Raise the limit; IPS indicates we have thermal headroom.
1774 bool i915_gpu_raise(void)
1776 struct drm_i915_private *dev_priv;
1779 spin_lock(&mchdev_lock);
1780 if (!i915_mch_dev) {
1784 dev_priv = i915_mch_dev;
1786 if (dev_priv->max_delay > dev_priv->fmax)
1787 dev_priv->max_delay--;
1790 spin_unlock(&mchdev_lock);
1794 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1797 * i915_gpu_lower - lower GPU frequency limit
1799 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1800 * frequency maximum.
1802 bool i915_gpu_lower(void)
1804 struct drm_i915_private *dev_priv;
1807 spin_lock(&mchdev_lock);
1808 if (!i915_mch_dev) {
1812 dev_priv = i915_mch_dev;
1814 if (dev_priv->max_delay < dev_priv->min_delay)
1815 dev_priv->max_delay++;
1818 spin_unlock(&mchdev_lock);
1822 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1825 * i915_gpu_busy - indicate GPU business to IPS
1827 * Tell the IPS driver whether or not the GPU is busy.
1829 bool i915_gpu_busy(void)
1831 struct drm_i915_private *dev_priv;
1834 spin_lock(&mchdev_lock);
1837 dev_priv = i915_mch_dev;
1839 ret = dev_priv->busy;
1842 spin_unlock(&mchdev_lock);
1846 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1849 * i915_gpu_turbo_disable - disable graphics turbo
1851 * Disable graphics turbo by resetting the max frequency and setting the
1852 * current frequency to the default.
1854 bool i915_gpu_turbo_disable(void)
1856 struct drm_i915_private *dev_priv;
1859 spin_lock(&mchdev_lock);
1860 if (!i915_mch_dev) {
1864 dev_priv = i915_mch_dev;
1866 dev_priv->max_delay = dev_priv->fstart;
1868 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1872 spin_unlock(&mchdev_lock);
1876 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1879 * Tells the intel_ips driver that the i915 driver is now loaded, if
1880 * IPS got loaded first.
1882 * This awkward dance is so that neither module has to depend on the
1883 * other in order for IPS to do the appropriate communication of
1884 * GPU turbo limits to i915.
1887 ips_ping_for_i915_load(void)
1891 link = symbol_get(ips_link_to_i915_driver);
1894 symbol_put(ips_link_to_i915_driver);
1899 * i915_driver_load - setup chip and create an initial config
1901 * @flags: startup flags
1903 * The driver load routine has to do several things:
1904 * - drive output discovery via intel_modeset_init()
1905 * - initialize the memory manager
1906 * - allocate initial config memory
1907 * - setup the DRM framebuffer with the allocated memory
1909 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1911 struct drm_i915_private *dev_priv;
1912 int ret = 0, mmio_bar;
1915 /* i915 has 4 more counters */
1917 dev->types[6] = _DRM_STAT_IRQ;
1918 dev->types[7] = _DRM_STAT_PRIMARY;
1919 dev->types[8] = _DRM_STAT_SECONDARY;
1920 dev->types[9] = _DRM_STAT_DMA;
1922 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1923 if (dev_priv == NULL)
1926 dev->dev_private = (void *)dev_priv;
1927 dev_priv->dev = dev;
1928 dev_priv->info = (struct intel_device_info *) flags;
1930 if (i915_get_bridge_dev(dev)) {
1935 /* overlay on gen2 is broken and can't address above 1G */
1937 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1939 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1940 * using 32bit addressing, overwriting memory if HWS is located
1943 * The documentation also mentions an issue with undefined
1944 * behaviour if any general state is accessed within a page above 4GB,
1945 * which also needs to be handled carefully.
1947 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1948 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1950 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1951 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1952 if (!dev_priv->regs) {
1953 DRM_ERROR("failed to map registers\n");
1958 dev_priv->mm.gtt = intel_gtt_get();
1959 if (!dev_priv->mm.gtt) {
1960 DRM_ERROR("Failed to initialize GTT\n");
1965 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1967 dev_priv->mm.gtt_mapping =
1968 io_mapping_create_wc(dev->agp->base, agp_size);
1969 if (dev_priv->mm.gtt_mapping == NULL) {
1974 /* Set up a WC MTRR for non-PAT systems. This is more common than
1975 * one would think, because the kernel disables PAT on first
1976 * generation Core chips because WC PAT gets overridden by a UC
1977 * MTRR if present. Even if a UC MTRR isn't present.
1979 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1981 MTRR_TYPE_WRCOMB, 1);
1982 if (dev_priv->mm.gtt_mtrr < 0) {
1983 DRM_INFO("MTRR allocation failed. Graphics "
1984 "performance may suffer.\n");
1987 /* The i915 workqueue is primarily used for batched retirement of
1988 * requests (and thus managing bo) once the task has been completed
1989 * by the GPU. i915_gem_retire_requests() is called directly when we
1990 * need high-priority retirement, such as waiting for an explicit
1993 * It is also used for periodic low-priority events, such as
1994 * idle-timers and recording error state.
1996 * All tasks on the workqueue are expected to acquire the dev mutex
1997 * so there is no point in running more than one instance of the
1998 * workqueue at any time: max_active = 1 and NON_REENTRANT.
2000 dev_priv->wq = alloc_workqueue("i915",
2001 WQ_UNBOUND | WQ_NON_REENTRANT,
2003 if (dev_priv->wq == NULL) {
2004 DRM_ERROR("Failed to create our workqueue.\n");
2009 /* enable GEM by default */
2010 dev_priv->has_gem = 1;
2012 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2013 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2014 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
2015 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2016 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2019 /* Try to make sure MCHBAR is enabled before poking at it */
2020 intel_setup_mchbar(dev);
2021 intel_setup_gmbus(dev);
2022 intel_opregion_setup(dev);
2024 /* Make sure the bios did its job and set up vital registers */
2025 intel_setup_bios(dev);
2030 if (!I915_NEED_GFX_HWS(dev)) {
2031 ret = i915_init_phys_hws(dev);
2033 goto out_gem_unload;
2036 if (IS_PINEVIEW(dev))
2037 i915_pineview_get_mem_freq(dev);
2038 else if (IS_GEN5(dev))
2039 i915_ironlake_get_mem_freq(dev);
2041 /* On the 945G/GM, the chipset reports the MSI capability on the
2042 * integrated graphics even though the support isn't actually there
2043 * according to the published specs. It doesn't appear to function
2044 * correctly in testing on 945G.
2045 * This may be a side effect of MSI having been made available for PEG
2046 * and the registers being closely associated.
2048 * According to chipset errata, on the 965GM, MSI interrupts may
2049 * be lost or delayed, but we use them anyways to avoid
2050 * stuck interrupts on some machines.
2052 if (!IS_I945G(dev) && !IS_I945GM(dev))
2053 pci_enable_msi(dev->pdev);
2055 spin_lock_init(&dev_priv->irq_lock);
2056 spin_lock_init(&dev_priv->error_lock);
2057 spin_lock_init(&dev_priv->rps_lock);
2059 if (IS_MOBILE(dev) || !IS_GEN2(dev))
2060 dev_priv->num_pipe = 2;
2062 dev_priv->num_pipe = 1;
2064 ret = drm_vblank_init(dev, dev_priv->num_pipe);
2066 goto out_gem_unload;
2068 /* Start out suspended */
2069 dev_priv->mm.suspended = 1;
2071 intel_detect_pch(dev);
2073 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2074 ret = i915_load_modeset_init(dev);
2076 DRM_ERROR("failed to init modeset\n");
2077 goto out_gem_unload;
2081 /* Must be done after probing outputs */
2082 intel_opregion_init(dev);
2083 acpi_video_register();
2085 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2086 (unsigned long) dev);
2088 spin_lock(&mchdev_lock);
2089 i915_mch_dev = dev_priv;
2090 dev_priv->mchdev_lock = &mchdev_lock;
2091 spin_unlock(&mchdev_lock);
2093 ips_ping_for_i915_load();
2098 if (dev->pdev->msi_enabled)
2099 pci_disable_msi(dev->pdev);
2101 intel_teardown_gmbus(dev);
2102 intel_teardown_mchbar(dev);
2103 destroy_workqueue(dev_priv->wq);
2105 io_mapping_free(dev_priv->mm.gtt_mapping);
2107 pci_iounmap(dev->pdev, dev_priv->regs);
2109 pci_dev_put(dev_priv->bridge_dev);
2115 int i915_driver_unload(struct drm_device *dev)
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2120 spin_lock(&mchdev_lock);
2121 i915_mch_dev = NULL;
2122 spin_unlock(&mchdev_lock);
2124 if (dev_priv->mm.inactive_shrinker.shrink)
2125 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2127 mutex_lock(&dev->struct_mutex);
2128 ret = i915_gpu_idle(dev);
2130 DRM_ERROR("failed to idle hardware: %d\n", ret);
2131 mutex_unlock(&dev->struct_mutex);
2133 /* Cancel the retire work handler, which should be idle now. */
2134 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2136 io_mapping_free(dev_priv->mm.gtt_mapping);
2137 if (dev_priv->mm.gtt_mtrr >= 0) {
2138 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2139 dev->agp->agp_info.aper_size * 1024 * 1024);
2140 dev_priv->mm.gtt_mtrr = -1;
2143 acpi_video_unregister();
2145 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2146 intel_fbdev_fini(dev);
2147 intel_modeset_cleanup(dev);
2150 * free the memory space allocated for the child device
2151 * config parsed from VBT
2153 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2154 kfree(dev_priv->child_dev);
2155 dev_priv->child_dev = NULL;
2156 dev_priv->child_dev_num = 0;
2159 vga_switcheroo_unregister_client(dev->pdev);
2160 vga_client_register(dev->pdev, NULL, NULL, NULL);
2163 /* Free error state after interrupts are fully disabled. */
2164 del_timer_sync(&dev_priv->hangcheck_timer);
2165 cancel_work_sync(&dev_priv->error_work);
2166 i915_destroy_error_state(dev);
2168 if (dev->pdev->msi_enabled)
2169 pci_disable_msi(dev->pdev);
2171 intel_opregion_fini(dev);
2173 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2174 /* Flush any outstanding unpin_work. */
2175 flush_workqueue(dev_priv->wq);
2177 i915_gem_free_all_phys_object(dev);
2179 mutex_lock(&dev->struct_mutex);
2180 i915_gem_cleanup_ringbuffer(dev);
2181 mutex_unlock(&dev->struct_mutex);
2182 if (I915_HAS_FBC(dev) && i915_powersave)
2183 i915_cleanup_compression(dev);
2184 drm_mm_takedown(&dev_priv->mm.stolen);
2186 intel_cleanup_overlay(dev);
2188 if (!I915_NEED_GFX_HWS(dev))
2192 if (dev_priv->regs != NULL)
2193 pci_iounmap(dev->pdev, dev_priv->regs);
2195 intel_teardown_gmbus(dev);
2196 intel_teardown_mchbar(dev);
2198 destroy_workqueue(dev_priv->wq);
2200 pci_dev_put(dev_priv->bridge_dev);
2201 kfree(dev->dev_private);
2206 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2208 struct drm_i915_file_private *file_priv;
2210 DRM_DEBUG_DRIVER("\n");
2211 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2215 file->driver_priv = file_priv;
2217 spin_lock_init(&file_priv->mm.lock);
2218 INIT_LIST_HEAD(&file_priv->mm.request_list);
2224 * i915_driver_lastclose - clean up after all DRM clients have exited
2227 * Take care of cleaning up after all DRM clients have exited. In the
2228 * mode setting case, we want to restore the kernel's initial mode (just
2229 * in case the last client left us in a bad state).
2231 * Additionally, in the non-mode setting case, we'll tear down the AGP
2232 * and DMA structures, since the kernel won't be using them, and clea
2235 void i915_driver_lastclose(struct drm_device * dev)
2237 drm_i915_private_t *dev_priv = dev->dev_private;
2239 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2240 intel_fb_restore_mode(dev);
2241 vga_switcheroo_process_delayed_switch();
2245 i915_gem_lastclose(dev);
2247 if (dev_priv->agp_heap)
2248 i915_mem_takedown(&(dev_priv->agp_heap));
2250 i915_dma_cleanup(dev);
2253 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2255 drm_i915_private_t *dev_priv = dev->dev_private;
2256 i915_gem_release(dev, file_priv);
2257 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2258 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2261 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2263 struct drm_i915_file_private *file_priv = file->driver_priv;
2268 struct drm_ioctl_desc i915_ioctls[] = {
2269 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2270 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2271 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2272 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2273 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2274 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2275 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2276 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2277 DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2278 DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2279 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2280 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2281 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2282 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2283 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2284 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2285 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2286 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2287 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2288 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2289 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2290 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2291 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2292 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2293 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2294 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2295 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2296 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2297 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2298 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2299 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2300 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2301 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2302 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2303 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2304 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2305 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2306 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2307 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2308 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2311 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2314 * Determine if the device really is AGP or not.
2316 * All Intel graphics chipsets are treated as AGP, even if they are really
2319 * \param dev The device to be tested.
2322 * A value of 1 is always retured to indictate every i9x5 is AGP.
2324 int i915_driver_device_is_agp(struct drm_device * dev)