1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include "intel_drv.h"
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include <linux/pci.h>
39 #include <linux/vgaarb.h>
40 #include <linux/acpi.h>
41 #include <linux/pnp.h>
42 #include <linux/vga_switcheroo.h>
43 #include <linux/slab.h>
44 #include <acpi/video.h>
46 #include <linux/pm_runtime.h>
48 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
50 #define BEGIN_LP_RING(n) \
51 intel_ring_begin(LP_RING(dev_priv), (n))
54 intel_ring_emit(LP_RING(dev_priv), x)
56 #define ADVANCE_LP_RING() \
57 __intel_ring_advance(LP_RING(dev_priv))
60 * Lock test for when it's just for synchronization of ring access.
62 * In that case, we don't need to do it when GEM is initialized as nobody else
63 * has access to the ring.
65 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
66 if (LP_RING(dev->dev_private)->obj == NULL) \
67 LOCK_TEST_WITH_RETURN(dev, file); \
71 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
73 if (I915_NEED_GFX_HWS(dev_priv->dev))
74 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
76 return intel_read_status_page(LP_RING(dev_priv), reg);
79 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
80 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
81 #define I915_BREADCRUMB_INDEX 0x21
83 void i915_update_dri1_breadcrumb(struct drm_device *dev)
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 struct drm_i915_master_private *master_priv;
89 * The dri breadcrumb update races against the drm master disappearing.
90 * Instead of trying to fix this (this is by far not the only ums issue)
91 * just don't do the update in kms mode.
93 if (drm_core_check_feature(dev, DRIVER_MODESET))
96 if (dev->primary->master) {
97 master_priv = dev->primary->master->driver_priv;
98 if (master_priv->sarea_priv)
99 master_priv->sarea_priv->last_dispatch =
100 READ_BREADCRUMB(dev_priv);
104 static void i915_write_hws_pga(struct drm_device *dev)
106 struct drm_i915_private *dev_priv = dev->dev_private;
109 addr = dev_priv->status_page_dmah->busaddr;
110 if (INTEL_INFO(dev)->gen >= 4)
111 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
112 I915_WRITE(HWS_PGA, addr);
116 * Frees the hardware status page, whether it's a physical address or a virtual
117 * address set up by the X Server.
119 static void i915_free_hws(struct drm_device *dev)
121 struct drm_i915_private *dev_priv = dev->dev_private;
122 struct intel_ring_buffer *ring = LP_RING(dev_priv);
124 if (dev_priv->status_page_dmah) {
125 drm_pci_free(dev, dev_priv->status_page_dmah);
126 dev_priv->status_page_dmah = NULL;
129 if (ring->status_page.gfx_addr) {
130 ring->status_page.gfx_addr = 0;
131 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
134 /* Need to rewrite hardware status page */
135 I915_WRITE(HWS_PGA, 0x1ffff000);
138 void i915_kernel_lost_context(struct drm_device * dev)
140 struct drm_i915_private *dev_priv = dev->dev_private;
141 struct drm_i915_master_private *master_priv;
142 struct intel_ring_buffer *ring = LP_RING(dev_priv);
145 * We should never lose context on the ring with modesetting
146 * as we don't expose it to userspace
148 if (drm_core_check_feature(dev, DRIVER_MODESET))
151 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
152 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
153 ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
155 ring->space += ring->size;
157 if (!dev->primary->master)
160 master_priv = dev->primary->master->driver_priv;
161 if (ring->head == ring->tail && master_priv->sarea_priv)
162 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
165 static int i915_dma_cleanup(struct drm_device * dev)
167 struct drm_i915_private *dev_priv = dev->dev_private;
170 /* Make sure interrupts are disabled here because the uninstall ioctl
171 * may not have been called from userspace and after dev_private
172 * is freed, it's too late.
174 if (dev->irq_enabled)
175 drm_irq_uninstall(dev);
177 mutex_lock(&dev->struct_mutex);
178 for (i = 0; i < I915_NUM_RINGS; i++)
179 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
180 mutex_unlock(&dev->struct_mutex);
182 /* Clear the HWS virtual address at teardown */
183 if (I915_NEED_GFX_HWS(dev))
189 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
191 struct drm_i915_private *dev_priv = dev->dev_private;
192 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
195 master_priv->sarea = drm_getsarea(dev);
196 if (master_priv->sarea) {
197 master_priv->sarea_priv = (drm_i915_sarea_t *)
198 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
200 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
203 if (init->ring_size != 0) {
204 if (LP_RING(dev_priv)->obj != NULL) {
205 i915_dma_cleanup(dev);
206 DRM_ERROR("Client tried to initialize ringbuffer in "
211 ret = intel_render_ring_init_dri(dev,
215 i915_dma_cleanup(dev);
220 dev_priv->dri1.cpp = init->cpp;
221 dev_priv->dri1.back_offset = init->back_offset;
222 dev_priv->dri1.front_offset = init->front_offset;
223 dev_priv->dri1.current_page = 0;
224 if (master_priv->sarea_priv)
225 master_priv->sarea_priv->pf_current_page = 0;
227 /* Allow hardware batchbuffers unless told otherwise.
229 dev_priv->dri1.allow_batchbuffer = 1;
234 static int i915_dma_resume(struct drm_device * dev)
236 struct drm_i915_private *dev_priv = dev->dev_private;
237 struct intel_ring_buffer *ring = LP_RING(dev_priv);
239 DRM_DEBUG_DRIVER("%s\n", __func__);
241 if (ring->virtual_start == NULL) {
242 DRM_ERROR("can not ioremap virtual address for"
247 /* Program Hardware Status Page */
248 if (!ring->status_page.page_addr) {
249 DRM_ERROR("Can not find hardware status page\n");
252 DRM_DEBUG_DRIVER("hw status page @ %p\n",
253 ring->status_page.page_addr);
254 if (ring->status_page.gfx_addr != 0)
255 intel_ring_setup_status_page(ring);
257 i915_write_hws_pga(dev);
259 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
264 static int i915_dma_init(struct drm_device *dev, void *data,
265 struct drm_file *file_priv)
267 drm_i915_init_t *init = data;
270 if (drm_core_check_feature(dev, DRIVER_MODESET))
273 switch (init->func) {
275 retcode = i915_initialize(dev, init);
277 case I915_CLEANUP_DMA:
278 retcode = i915_dma_cleanup(dev);
280 case I915_RESUME_DMA:
281 retcode = i915_dma_resume(dev);
291 /* Implement basically the same security restrictions as hardware does
292 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
294 * Most of the calculations below involve calculating the size of a
295 * particular instruction. It's important to get the size right as
296 * that tells us where the next instruction to check is. Any illegal
297 * instruction detected will be given a size of zero, which is a
298 * signal to abort the rest of the buffer.
300 static int validate_cmd(int cmd)
302 switch (((cmd >> 29) & 0x7)) {
304 switch ((cmd >> 23) & 0x3f) {
306 return 1; /* MI_NOOP */
308 return 1; /* MI_FLUSH */
310 return 0; /* disallow everything else */
314 return 0; /* reserved */
316 return (cmd & 0xff) + 2; /* 2d commands */
318 if (((cmd >> 24) & 0x1f) <= 0x18)
321 switch ((cmd >> 24) & 0x1f) {
325 switch ((cmd >> 16) & 0xff) {
327 return (cmd & 0x1f) + 2;
329 return (cmd & 0xf) + 2;
331 return (cmd & 0xffff) + 2;
335 return (cmd & 0xffff) + 1;
339 if ((cmd & (1 << 23)) == 0) /* inline vertices */
340 return (cmd & 0x1ffff) + 2;
341 else if (cmd & (1 << 17)) /* indirect random */
342 if ((cmd & 0xffff) == 0)
343 return 0; /* unknown length, too hard */
345 return (((cmd & 0xffff) + 1) / 2) + 1;
347 return 2; /* indirect sequential */
358 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
360 struct drm_i915_private *dev_priv = dev->dev_private;
363 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
366 for (i = 0; i < dwords;) {
367 int sz = validate_cmd(buffer[i]);
368 if (sz == 0 || i + sz > dwords)
373 ret = BEGIN_LP_RING((dwords+1)&~1);
377 for (i = 0; i < dwords; i++)
388 i915_emit_box(struct drm_device *dev,
389 struct drm_clip_rect *box,
392 struct drm_i915_private *dev_priv = dev->dev_private;
395 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
396 box->y2 <= 0 || box->x2 <= 0) {
397 DRM_ERROR("Bad box %d,%d..%d,%d\n",
398 box->x1, box->y1, box->x2, box->y2);
402 if (INTEL_INFO(dev)->gen >= 4) {
403 ret = BEGIN_LP_RING(4);
407 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
408 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
409 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
412 ret = BEGIN_LP_RING(6);
416 OUT_RING(GFX_OP_DRAWRECT_INFO);
418 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
419 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
428 /* XXX: Emitting the counter should really be moved to part of the IRQ
429 * emit. For now, do it in both places:
432 static void i915_emit_breadcrumb(struct drm_device *dev)
434 struct drm_i915_private *dev_priv = dev->dev_private;
435 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
437 dev_priv->dri1.counter++;
438 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
439 dev_priv->dri1.counter = 0;
440 if (master_priv->sarea_priv)
441 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
443 if (BEGIN_LP_RING(4) == 0) {
444 OUT_RING(MI_STORE_DWORD_INDEX);
445 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
446 OUT_RING(dev_priv->dri1.counter);
452 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
453 drm_i915_cmdbuffer_t *cmd,
454 struct drm_clip_rect *cliprects,
457 int nbox = cmd->num_cliprects;
458 int i = 0, count, ret;
461 DRM_ERROR("alignment");
465 i915_kernel_lost_context(dev);
467 count = nbox ? nbox : 1;
469 for (i = 0; i < count; i++) {
471 ret = i915_emit_box(dev, &cliprects[i],
477 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
482 i915_emit_breadcrumb(dev);
486 static int i915_dispatch_batchbuffer(struct drm_device * dev,
487 drm_i915_batchbuffer_t * batch,
488 struct drm_clip_rect *cliprects)
490 struct drm_i915_private *dev_priv = dev->dev_private;
491 int nbox = batch->num_cliprects;
494 if ((batch->start | batch->used) & 0x7) {
495 DRM_ERROR("alignment");
499 i915_kernel_lost_context(dev);
501 count = nbox ? nbox : 1;
502 for (i = 0; i < count; i++) {
504 ret = i915_emit_box(dev, &cliprects[i],
505 batch->DR1, batch->DR4);
510 if (!IS_I830(dev) && !IS_845G(dev)) {
511 ret = BEGIN_LP_RING(2);
515 if (INTEL_INFO(dev)->gen >= 4) {
516 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
517 OUT_RING(batch->start);
519 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
520 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
523 ret = BEGIN_LP_RING(4);
527 OUT_RING(MI_BATCH_BUFFER);
528 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
529 OUT_RING(batch->start + batch->used - 4);
536 if (IS_G4X(dev) || IS_GEN5(dev)) {
537 if (BEGIN_LP_RING(2) == 0) {
538 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
544 i915_emit_breadcrumb(dev);
548 static int i915_dispatch_flip(struct drm_device * dev)
550 struct drm_i915_private *dev_priv = dev->dev_private;
551 struct drm_i915_master_private *master_priv =
552 dev->primary->master->driver_priv;
555 if (!master_priv->sarea_priv)
558 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
560 dev_priv->dri1.current_page,
561 master_priv->sarea_priv->pf_current_page);
563 i915_kernel_lost_context(dev);
565 ret = BEGIN_LP_RING(10);
569 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
572 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
574 if (dev_priv->dri1.current_page == 0) {
575 OUT_RING(dev_priv->dri1.back_offset);
576 dev_priv->dri1.current_page = 1;
578 OUT_RING(dev_priv->dri1.front_offset);
579 dev_priv->dri1.current_page = 0;
583 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
588 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
590 if (BEGIN_LP_RING(4) == 0) {
591 OUT_RING(MI_STORE_DWORD_INDEX);
592 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
593 OUT_RING(dev_priv->dri1.counter);
598 master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
602 static int i915_quiescent(struct drm_device *dev)
604 i915_kernel_lost_context(dev);
605 return intel_ring_idle(LP_RING(dev->dev_private));
608 static int i915_flush_ioctl(struct drm_device *dev, void *data,
609 struct drm_file *file_priv)
613 if (drm_core_check_feature(dev, DRIVER_MODESET))
616 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
618 mutex_lock(&dev->struct_mutex);
619 ret = i915_quiescent(dev);
620 mutex_unlock(&dev->struct_mutex);
625 static int i915_batchbuffer(struct drm_device *dev, void *data,
626 struct drm_file *file_priv)
628 struct drm_i915_private *dev_priv = dev->dev_private;
629 struct drm_i915_master_private *master_priv;
630 drm_i915_sarea_t *sarea_priv;
631 drm_i915_batchbuffer_t *batch = data;
633 struct drm_clip_rect *cliprects = NULL;
635 if (drm_core_check_feature(dev, DRIVER_MODESET))
638 master_priv = dev->primary->master->driver_priv;
639 sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv;
641 if (!dev_priv->dri1.allow_batchbuffer) {
642 DRM_ERROR("Batchbuffer ioctl disabled\n");
646 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
647 batch->start, batch->used, batch->num_cliprects);
649 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
651 if (batch->num_cliprects < 0)
654 if (batch->num_cliprects) {
655 cliprects = kcalloc(batch->num_cliprects,
658 if (cliprects == NULL)
661 ret = copy_from_user(cliprects, batch->cliprects,
662 batch->num_cliprects *
663 sizeof(struct drm_clip_rect));
670 mutex_lock(&dev->struct_mutex);
671 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
672 mutex_unlock(&dev->struct_mutex);
675 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
683 static int i915_cmdbuffer(struct drm_device *dev, void *data,
684 struct drm_file *file_priv)
686 struct drm_i915_private *dev_priv = dev->dev_private;
687 struct drm_i915_master_private *master_priv;
688 drm_i915_sarea_t *sarea_priv;
689 drm_i915_cmdbuffer_t *cmdbuf = data;
690 struct drm_clip_rect *cliprects = NULL;
694 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
695 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
697 if (drm_core_check_feature(dev, DRIVER_MODESET))
700 master_priv = dev->primary->master->driver_priv;
701 sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv;
703 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
705 if (cmdbuf->num_cliprects < 0)
708 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
709 if (batch_data == NULL)
712 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
715 goto fail_batch_free;
718 if (cmdbuf->num_cliprects) {
719 cliprects = kcalloc(cmdbuf->num_cliprects,
720 sizeof(*cliprects), GFP_KERNEL);
721 if (cliprects == NULL) {
723 goto fail_batch_free;
726 ret = copy_from_user(cliprects, cmdbuf->cliprects,
727 cmdbuf->num_cliprects *
728 sizeof(struct drm_clip_rect));
735 mutex_lock(&dev->struct_mutex);
736 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
737 mutex_unlock(&dev->struct_mutex);
739 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
744 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
754 static int i915_emit_irq(struct drm_device * dev)
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
759 i915_kernel_lost_context(dev);
761 DRM_DEBUG_DRIVER("\n");
763 dev_priv->dri1.counter++;
764 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
765 dev_priv->dri1.counter = 1;
766 if (master_priv->sarea_priv)
767 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
769 if (BEGIN_LP_RING(4) == 0) {
770 OUT_RING(MI_STORE_DWORD_INDEX);
771 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
772 OUT_RING(dev_priv->dri1.counter);
773 OUT_RING(MI_USER_INTERRUPT);
777 return dev_priv->dri1.counter;
780 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
782 struct drm_i915_private *dev_priv = dev->dev_private;
783 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
785 struct intel_ring_buffer *ring = LP_RING(dev_priv);
787 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
788 READ_BREADCRUMB(dev_priv));
790 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
791 if (master_priv->sarea_priv)
792 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
796 if (master_priv->sarea_priv)
797 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
799 if (ring->irq_get(ring)) {
800 DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ,
801 READ_BREADCRUMB(dev_priv) >= irq_nr);
803 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
807 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
808 READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
814 /* Needs the lock as it touches the ring.
816 static int i915_irq_emit(struct drm_device *dev, void *data,
817 struct drm_file *file_priv)
819 struct drm_i915_private *dev_priv = dev->dev_private;
820 drm_i915_irq_emit_t *emit = data;
823 if (drm_core_check_feature(dev, DRIVER_MODESET))
826 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
827 DRM_ERROR("called with no initialization\n");
831 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
833 mutex_lock(&dev->struct_mutex);
834 result = i915_emit_irq(dev);
835 mutex_unlock(&dev->struct_mutex);
837 if (copy_to_user(emit->irq_seq, &result, sizeof(int))) {
838 DRM_ERROR("copy_to_user\n");
845 /* Doesn't need the hardware lock.
847 static int i915_irq_wait(struct drm_device *dev, void *data,
848 struct drm_file *file_priv)
850 struct drm_i915_private *dev_priv = dev->dev_private;
851 drm_i915_irq_wait_t *irqwait = data;
853 if (drm_core_check_feature(dev, DRIVER_MODESET))
857 DRM_ERROR("called with no initialization\n");
861 return i915_wait_irq(dev, irqwait->irq_seq);
864 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
865 struct drm_file *file_priv)
867 struct drm_i915_private *dev_priv = dev->dev_private;
868 drm_i915_vblank_pipe_t *pipe = data;
870 if (drm_core_check_feature(dev, DRIVER_MODESET))
874 DRM_ERROR("called with no initialization\n");
878 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
884 * Schedule buffer swap at given vertical blank.
886 static int i915_vblank_swap(struct drm_device *dev, void *data,
887 struct drm_file *file_priv)
889 /* The delayed swap mechanism was fundamentally racy, and has been
890 * removed. The model was that the client requested a delayed flip/swap
891 * from the kernel, then waited for vblank before continuing to perform
892 * rendering. The problem was that the kernel might wake the client
893 * up before it dispatched the vblank swap (since the lock has to be
894 * held while touching the ringbuffer), in which case the client would
895 * clear and start the next frame before the swap occurred, and
896 * flicker would occur in addition to likely missing the vblank.
898 * In the absence of this ioctl, userland falls back to a correct path
899 * of waiting for a vblank, then dispatching the swap on its own.
900 * Context switching to userland and back is plenty fast enough for
901 * meeting the requirements of vblank swapping.
906 static int i915_flip_bufs(struct drm_device *dev, void *data,
907 struct drm_file *file_priv)
911 if (drm_core_check_feature(dev, DRIVER_MODESET))
914 DRM_DEBUG_DRIVER("%s\n", __func__);
916 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
918 mutex_lock(&dev->struct_mutex);
919 ret = i915_dispatch_flip(dev);
920 mutex_unlock(&dev->struct_mutex);
925 static int i915_getparam(struct drm_device *dev, void *data,
926 struct drm_file *file_priv)
928 struct drm_i915_private *dev_priv = dev->dev_private;
929 drm_i915_getparam_t *param = data;
933 DRM_ERROR("called with no initialization\n");
937 switch (param->param) {
938 case I915_PARAM_IRQ_ACTIVE:
939 value = dev->pdev->irq ? 1 : 0;
941 case I915_PARAM_ALLOW_BATCHBUFFER:
942 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
944 case I915_PARAM_LAST_DISPATCH:
945 value = READ_BREADCRUMB(dev_priv);
947 case I915_PARAM_CHIPSET_ID:
948 value = dev->pdev->device;
950 case I915_PARAM_HAS_GEM:
953 case I915_PARAM_NUM_FENCES_AVAIL:
954 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
956 case I915_PARAM_HAS_OVERLAY:
957 value = dev_priv->overlay ? 1 : 0;
959 case I915_PARAM_HAS_PAGEFLIPPING:
962 case I915_PARAM_HAS_EXECBUF2:
966 case I915_PARAM_HAS_BSD:
967 value = intel_ring_initialized(&dev_priv->ring[VCS]);
969 case I915_PARAM_HAS_BLT:
970 value = intel_ring_initialized(&dev_priv->ring[BCS]);
972 case I915_PARAM_HAS_VEBOX:
973 value = intel_ring_initialized(&dev_priv->ring[VECS]);
975 case I915_PARAM_HAS_RELAXED_FENCING:
978 case I915_PARAM_HAS_COHERENT_RINGS:
981 case I915_PARAM_HAS_EXEC_CONSTANTS:
982 value = INTEL_INFO(dev)->gen >= 4;
984 case I915_PARAM_HAS_RELAXED_DELTA:
987 case I915_PARAM_HAS_GEN7_SOL_RESET:
990 case I915_PARAM_HAS_LLC:
991 value = HAS_LLC(dev);
993 case I915_PARAM_HAS_WT:
996 case I915_PARAM_HAS_ALIASING_PPGTT:
997 value = dev_priv->mm.aliasing_ppgtt || USES_FULL_PPGTT(dev);
999 case I915_PARAM_HAS_WAIT_TIMEOUT:
1002 case I915_PARAM_HAS_SEMAPHORES:
1003 value = i915_semaphore_is_enabled(dev);
1005 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
1008 case I915_PARAM_HAS_SECURE_BATCHES:
1009 value = capable(CAP_SYS_ADMIN);
1011 case I915_PARAM_HAS_PINNED_BATCHES:
1014 case I915_PARAM_HAS_EXEC_NO_RELOC:
1017 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1021 DRM_DEBUG("Unknown parameter %d\n", param->param);
1025 if (copy_to_user(param->value, &value, sizeof(int))) {
1026 DRM_ERROR("copy_to_user failed\n");
1033 static int i915_setparam(struct drm_device *dev, void *data,
1034 struct drm_file *file_priv)
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037 drm_i915_setparam_t *param = data;
1040 DRM_ERROR("called with no initialization\n");
1044 switch (param->param) {
1045 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1047 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1049 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1050 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1052 case I915_SETPARAM_NUM_USED_FENCES:
1053 if (param->value > dev_priv->num_fence_regs ||
1056 /* Userspace can use first N regs */
1057 dev_priv->fence_reg_start = param->value;
1060 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1068 static int i915_set_status_page(struct drm_device *dev, void *data,
1069 struct drm_file *file_priv)
1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 drm_i915_hws_addr_t *hws = data;
1073 struct intel_ring_buffer *ring;
1075 if (drm_core_check_feature(dev, DRIVER_MODESET))
1078 if (!I915_NEED_GFX_HWS(dev))
1082 DRM_ERROR("called with no initialization\n");
1086 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1087 WARN(1, "tried to set status page when mode setting active\n");
1091 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1093 ring = LP_RING(dev_priv);
1094 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1096 dev_priv->dri1.gfx_hws_cpu_addr =
1097 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1098 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1099 i915_dma_cleanup(dev);
1100 ring->status_page.gfx_addr = 0;
1101 DRM_ERROR("can not ioremap virtual address for"
1102 " G33 hw status page\n");
1106 memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1107 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1109 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1110 ring->status_page.gfx_addr);
1111 DRM_DEBUG_DRIVER("load hws at %p\n",
1112 ring->status_page.page_addr);
1116 static int i915_get_bridge_dev(struct drm_device *dev)
1118 struct drm_i915_private *dev_priv = dev->dev_private;
1120 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1121 if (!dev_priv->bridge_dev) {
1122 DRM_ERROR("bridge device not found\n");
1128 #define MCHBAR_I915 0x44
1129 #define MCHBAR_I965 0x48
1130 #define MCHBAR_SIZE (4*4096)
1132 #define DEVEN_REG 0x54
1133 #define DEVEN_MCHBAR_EN (1 << 28)
1135 /* Allocate space for the MCH regs if needed, return nonzero on error */
1137 intel_alloc_mchbar_resource(struct drm_device *dev)
1139 struct drm_i915_private *dev_priv = dev->dev_private;
1140 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1141 u32 temp_lo, temp_hi = 0;
1145 if (INTEL_INFO(dev)->gen >= 4)
1146 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1147 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1148 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1150 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1153 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1157 /* Get some space for it */
1158 dev_priv->mch_res.name = "i915 MCHBAR";
1159 dev_priv->mch_res.flags = IORESOURCE_MEM;
1160 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1162 MCHBAR_SIZE, MCHBAR_SIZE,
1164 0, pcibios_align_resource,
1165 dev_priv->bridge_dev);
1167 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1168 dev_priv->mch_res.start = 0;
1172 if (INTEL_INFO(dev)->gen >= 4)
1173 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1174 upper_32_bits(dev_priv->mch_res.start));
1176 pci_write_config_dword(dev_priv->bridge_dev, reg,
1177 lower_32_bits(dev_priv->mch_res.start));
1181 /* Setup MCHBAR if possible, return true if we should disable it again */
1183 intel_setup_mchbar(struct drm_device *dev)
1185 struct drm_i915_private *dev_priv = dev->dev_private;
1186 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1190 if (IS_VALLEYVIEW(dev))
1193 dev_priv->mchbar_need_disable = false;
1195 if (IS_I915G(dev) || IS_I915GM(dev)) {
1196 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1197 enabled = !!(temp & DEVEN_MCHBAR_EN);
1199 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1203 /* If it's already enabled, don't have to do anything */
1207 if (intel_alloc_mchbar_resource(dev))
1210 dev_priv->mchbar_need_disable = true;
1212 /* Space is allocated or reserved, so enable it. */
1213 if (IS_I915G(dev) || IS_I915GM(dev)) {
1214 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1215 temp | DEVEN_MCHBAR_EN);
1217 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1218 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1223 intel_teardown_mchbar(struct drm_device *dev)
1225 struct drm_i915_private *dev_priv = dev->dev_private;
1226 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1229 if (dev_priv->mchbar_need_disable) {
1230 if (IS_I915G(dev) || IS_I915GM(dev)) {
1231 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1232 temp &= ~DEVEN_MCHBAR_EN;
1233 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1235 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1237 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1241 if (dev_priv->mch_res.start)
1242 release_resource(&dev_priv->mch_res);
1245 /* true = enable decode, false = disable decoder */
1246 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1248 struct drm_device *dev = cookie;
1250 intel_modeset_vga_set_state(dev, state);
1252 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1253 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1255 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1258 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1260 struct drm_device *dev = pci_get_drvdata(pdev);
1261 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1262 if (state == VGA_SWITCHEROO_ON) {
1263 pr_info("switched on\n");
1264 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1265 /* i915 resume handler doesn't set to D0 */
1266 pci_set_power_state(dev->pdev, PCI_D0);
1268 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1270 pr_err("switched off\n");
1271 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1272 i915_suspend(dev, pmm);
1273 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1277 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1279 struct drm_device *dev = pci_get_drvdata(pdev);
1282 spin_lock(&dev->count_lock);
1283 can_switch = (dev->open_count == 0);
1284 spin_unlock(&dev->count_lock);
1288 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1289 .set_gpu_state = i915_switcheroo_set_state,
1291 .can_switch = i915_switcheroo_can_switch,
1294 static int i915_load_modeset_init(struct drm_device *dev)
1296 struct drm_i915_private *dev_priv = dev->dev_private;
1299 ret = intel_parse_bios(dev);
1301 DRM_INFO("failed to find VBIOS tables\n");
1303 /* If we have > 1 VGA cards, then we need to arbitrate access
1304 * to the common VGA resources.
1306 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1307 * then we do not take part in VGA arbitration and the
1308 * vga_client_register() fails with -ENODEV.
1310 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1311 if (ret && ret != -ENODEV)
1314 intel_register_dsm_handler();
1316 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
1318 goto cleanup_vga_client;
1320 /* Initialise stolen first so that we may reserve preallocated
1321 * objects for the BIOS to KMS transition.
1323 ret = i915_gem_init_stolen(dev);
1325 goto cleanup_vga_switcheroo;
1327 intel_power_domains_init_hw(dev_priv);
1329 ret = drm_irq_install(dev);
1331 goto cleanup_gem_stolen;
1333 /* Important: The output setup functions called by modeset_init need
1334 * working irqs for e.g. gmbus and dp aux transfers. */
1335 intel_modeset_init(dev);
1337 ret = i915_gem_init(dev);
1341 INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1343 intel_modeset_gem_init(dev);
1345 /* Always safe in the mode setting case. */
1346 /* FIXME: do pre/post-mode set stuff in core KMS code */
1347 dev->vblank_disable_allowed = true;
1348 if (INTEL_INFO(dev)->num_pipes == 0) {
1349 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
1353 ret = intel_fbdev_init(dev);
1357 /* Only enable hotplug handling once the fbdev is fully set up. */
1358 intel_hpd_init(dev);
1361 * Some ports require correctly set-up hpd registers for detection to
1362 * work properly (leading to ghost connected connector status), e.g. VGA
1363 * on gm45. Hence we can only set up the initial fbdev config after hpd
1364 * irqs are fully enabled. Now we should scan for the initial config
1365 * only once hotplug handling is enabled, but due to screwed-up locking
1366 * around kms/fbdev init we can't protect the fdbev initial config
1367 * scanning against hotplug events. Hence do this first and ignore the
1368 * tiny window where we will loose hotplug notifactions.
1370 intel_fbdev_initial_config(dev);
1372 /* Only enable hotplug handling once the fbdev is fully set up. */
1373 dev_priv->enable_hotplug_processing = true;
1375 drm_kms_helper_poll_init(dev);
1380 mutex_lock(&dev->struct_mutex);
1381 i915_gem_cleanup_ringbuffer(dev);
1382 i915_gem_context_fini(dev);
1383 mutex_unlock(&dev->struct_mutex);
1384 WARN_ON(dev_priv->mm.aliasing_ppgtt);
1385 drm_mm_takedown(&dev_priv->gtt.base.mm);
1387 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
1388 drm_irq_uninstall(dev);
1390 i915_gem_cleanup_stolen(dev);
1391 cleanup_vga_switcheroo:
1392 vga_switcheroo_unregister_client(dev->pdev);
1394 vga_client_register(dev->pdev, NULL, NULL, NULL);
1399 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1401 struct drm_i915_master_private *master_priv;
1403 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1407 master->driver_priv = master_priv;
1411 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1413 struct drm_i915_master_private *master_priv = master->driver_priv;
1420 master->driver_priv = NULL;
1423 #if IS_ENABLED(CONFIG_FB)
1424 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1426 struct apertures_struct *ap;
1427 struct pci_dev *pdev = dev_priv->dev->pdev;
1430 ap = alloc_apertures(1);
1434 ap->ranges[0].base = dev_priv->gtt.mappable_base;
1435 ap->ranges[0].size = dev_priv->gtt.mappable_end;
1438 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1440 remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1445 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1450 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1452 const struct intel_device_info *info = &dev_priv->info;
1454 #define PRINT_S(name) "%s"
1456 #define PRINT_FLAG(name) info->name ? #name "," : ""
1458 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1459 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1461 dev_priv->dev->pdev->device,
1462 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1470 * Determine various intel_device_info fields at runtime.
1472 * Use it when either:
1473 * - it's judged too laborious to fill n static structures with the limit
1474 * when a simple if statement does the job,
1475 * - run-time checks (eg read fuse/strap registers) are needed.
1477 * This function needs to be called:
1478 * - after the MMIO has been setup as we are reading registers,
1479 * - after the PCH has been detected,
1480 * - before the first usage of the fields it can tweak.
1482 static void intel_device_info_runtime_init(struct drm_device *dev)
1484 struct drm_i915_private *dev_priv = dev->dev_private;
1485 struct intel_device_info *info;
1488 info = (struct intel_device_info *)&dev_priv->info;
1490 if (IS_VALLEYVIEW(dev))
1492 info->num_sprites[pipe] = 2;
1495 info->num_sprites[pipe] = 1;
1497 if (i915.disable_display) {
1498 DRM_INFO("Display disabled (module parameter)\n");
1499 info->num_pipes = 0;
1500 } else if (info->num_pipes > 0 &&
1501 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
1502 !IS_VALLEYVIEW(dev)) {
1503 u32 fuse_strap = I915_READ(FUSE_STRAP);
1504 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
1507 * SFUSE_STRAP is supposed to have a bit signalling the display
1508 * is fused off. Unfortunately it seems that, at least in
1509 * certain cases, fused off display means that PCH display
1510 * reads don't land anywhere. In that case, we read 0s.
1512 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1513 * should be set when taking over after the firmware.
1515 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1516 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1517 (dev_priv->pch_type == PCH_CPT &&
1518 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1519 DRM_INFO("Display fused off, disabling\n");
1520 info->num_pipes = 0;
1526 * i915_driver_load - setup chip and create an initial config
1528 * @flags: startup flags
1530 * The driver load routine has to do several things:
1531 * - drive output discovery via intel_modeset_init()
1532 * - initialize the memory manager
1533 * - allocate initial config memory
1534 * - setup the DRM framebuffer with the allocated memory
1536 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1538 struct drm_i915_private *dev_priv;
1539 struct intel_device_info *info, *device_info;
1540 int ret = 0, mmio_bar, mmio_size;
1541 uint32_t aperture_size;
1543 info = (struct intel_device_info *) flags;
1545 /* Refuse to load on gen6+ without kms enabled. */
1546 if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
1547 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
1548 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
1552 /* UMS needs agp support. */
1553 if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp)
1556 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1557 if (dev_priv == NULL)
1560 dev->dev_private = (void *)dev_priv;
1561 dev_priv->dev = dev;
1563 /* copy initial configuration to dev_priv->info */
1564 device_info = (struct intel_device_info *)&dev_priv->info;
1565 *device_info = *info;
1567 spin_lock_init(&dev_priv->irq_lock);
1568 spin_lock_init(&dev_priv->gpu_error.lock);
1569 spin_lock_init(&dev_priv->backlight_lock);
1570 spin_lock_init(&dev_priv->uncore.lock);
1571 spin_lock_init(&dev_priv->mm.object_stat_lock);
1572 mutex_init(&dev_priv->dpio_lock);
1573 mutex_init(&dev_priv->modeset_restore_lock);
1575 intel_pm_setup(dev);
1577 intel_display_crc_init(dev);
1579 i915_dump_device_info(dev_priv);
1581 /* Not all pre-production machines fall into this category, only the
1582 * very first ones. Almost everything should work, except for maybe
1583 * suspend/resume. And we don't implement workarounds that affect only
1584 * pre-production machines. */
1585 if (IS_HSW_EARLY_SDV(dev))
1586 DRM_INFO("This is an early pre-production Haswell machine. "
1587 "It may not be fully functional.\n");
1589 if (i915_get_bridge_dev(dev)) {
1594 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1595 /* Before gen4, the registers and the GTT are behind different BARs.
1596 * However, from gen4 onwards, the registers and the GTT are shared
1597 * in the same BAR, so we want to restrict this ioremap from
1598 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1599 * the register BAR remains the same size for all the earlier
1600 * generations up to Ironlake.
1603 mmio_size = 512*1024;
1605 mmio_size = 2*1024*1024;
1607 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1608 if (!dev_priv->regs) {
1609 DRM_ERROR("failed to map registers\n");
1614 /* This must be called before any calls to HAS_PCH_* */
1615 intel_detect_pch(dev);
1617 intel_uncore_init(dev);
1619 ret = i915_gem_gtt_init(dev);
1623 if (drm_core_check_feature(dev, DRIVER_MODESET))
1624 i915_kick_out_firmware_fb(dev_priv);
1626 pci_set_master(dev->pdev);
1628 /* overlay on gen2 is broken and can't address above 1G */
1630 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1632 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1633 * using 32bit addressing, overwriting memory if HWS is located
1636 * The documentation also mentions an issue with undefined
1637 * behaviour if any general state is accessed within a page above 4GB,
1638 * which also needs to be handled carefully.
1640 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1641 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1643 aperture_size = dev_priv->gtt.mappable_end;
1645 dev_priv->gtt.mappable =
1646 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1648 if (dev_priv->gtt.mappable == NULL) {
1653 dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1656 /* The i915 workqueue is primarily used for batched retirement of
1657 * requests (and thus managing bo) once the task has been completed
1658 * by the GPU. i915_gem_retire_requests() is called directly when we
1659 * need high-priority retirement, such as waiting for an explicit
1662 * It is also used for periodic low-priority events, such as
1663 * idle-timers and recording error state.
1665 * All tasks on the workqueue are expected to acquire the dev mutex
1666 * so there is no point in running more than one instance of the
1667 * workqueue at any time. Use an ordered one.
1669 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1670 if (dev_priv->wq == NULL) {
1671 DRM_ERROR("Failed to create our workqueue.\n");
1676 intel_irq_init(dev);
1677 intel_uncore_sanitize(dev);
1679 /* Try to make sure MCHBAR is enabled before poking at it */
1680 intel_setup_mchbar(dev);
1681 intel_setup_gmbus(dev);
1682 intel_opregion_setup(dev);
1684 intel_setup_bios(dev);
1688 /* On the 945G/GM, the chipset reports the MSI capability on the
1689 * integrated graphics even though the support isn't actually there
1690 * according to the published specs. It doesn't appear to function
1691 * correctly in testing on 945G.
1692 * This may be a side effect of MSI having been made available for PEG
1693 * and the registers being closely associated.
1695 * According to chipset errata, on the 965GM, MSI interrupts may
1696 * be lost or delayed, but we use them anyways to avoid
1697 * stuck interrupts on some machines.
1699 if (!IS_I945G(dev) && !IS_I945GM(dev))
1700 pci_enable_msi(dev->pdev);
1702 intel_device_info_runtime_init(dev);
1704 if (INTEL_INFO(dev)->num_pipes) {
1705 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1707 goto out_gem_unload;
1710 intel_power_domains_init(dev_priv);
1712 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1713 ret = i915_load_modeset_init(dev);
1715 DRM_ERROR("failed to init modeset\n");
1716 goto out_power_well;
1719 /* Start out suspended in ums mode. */
1720 dev_priv->ums.mm_suspended = 1;
1723 i915_setup_sysfs(dev);
1725 if (INTEL_INFO(dev)->num_pipes) {
1726 /* Must be done after probing outputs */
1727 intel_opregion_init(dev);
1728 acpi_video_register();
1732 intel_gpu_ips_init(dev_priv);
1734 intel_init_runtime_pm(dev_priv);
1739 intel_power_domains_remove(dev_priv);
1740 drm_vblank_cleanup(dev);
1742 if (dev_priv->mm.inactive_shrinker.scan_objects)
1743 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1745 if (dev->pdev->msi_enabled)
1746 pci_disable_msi(dev->pdev);
1748 intel_teardown_gmbus(dev);
1749 intel_teardown_mchbar(dev);
1750 pm_qos_remove_request(&dev_priv->pm_qos);
1751 destroy_workqueue(dev_priv->wq);
1753 arch_phys_wc_del(dev_priv->gtt.mtrr);
1754 io_mapping_free(dev_priv->gtt.mappable);
1756 list_del(&dev_priv->gtt.base.global_link);
1757 drm_mm_takedown(&dev_priv->gtt.base.mm);
1758 dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1760 intel_uncore_fini(dev);
1761 pci_iounmap(dev->pdev, dev_priv->regs);
1763 pci_dev_put(dev_priv->bridge_dev);
1766 kmem_cache_destroy(dev_priv->slab);
1771 int i915_driver_unload(struct drm_device *dev)
1773 struct drm_i915_private *dev_priv = dev->dev_private;
1776 ret = i915_gem_suspend(dev);
1778 DRM_ERROR("failed to idle hardware: %d\n", ret);
1782 intel_fini_runtime_pm(dev_priv);
1784 intel_gpu_ips_teardown();
1786 /* The i915.ko module is still not prepared to be loaded when
1787 * the power well is not enabled, so just enable it in case
1788 * we're going to unload/reload. */
1789 intel_display_set_init_power(dev_priv, true);
1790 intel_power_domains_remove(dev_priv);
1792 i915_teardown_sysfs(dev);
1794 if (dev_priv->mm.inactive_shrinker.scan_objects)
1795 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1797 io_mapping_free(dev_priv->gtt.mappable);
1798 arch_phys_wc_del(dev_priv->gtt.mtrr);
1800 acpi_video_unregister();
1802 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1803 intel_fbdev_fini(dev);
1804 intel_modeset_cleanup(dev);
1805 cancel_work_sync(&dev_priv->console_resume_work);
1808 * free the memory space allocated for the child device
1809 * config parsed from VBT
1811 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1812 kfree(dev_priv->vbt.child_dev);
1813 dev_priv->vbt.child_dev = NULL;
1814 dev_priv->vbt.child_dev_num = 0;
1817 vga_switcheroo_unregister_client(dev->pdev);
1818 vga_client_register(dev->pdev, NULL, NULL, NULL);
1821 /* Free error state after interrupts are fully disabled. */
1822 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1823 cancel_work_sync(&dev_priv->gpu_error.work);
1824 i915_destroy_error_state(dev);
1826 if (dev->pdev->msi_enabled)
1827 pci_disable_msi(dev->pdev);
1829 intel_opregion_fini(dev);
1831 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1832 /* Flush any outstanding unpin_work. */
1833 flush_workqueue(dev_priv->wq);
1835 mutex_lock(&dev->struct_mutex);
1836 i915_gem_free_all_phys_object(dev);
1837 i915_gem_cleanup_ringbuffer(dev);
1838 i915_gem_context_fini(dev);
1839 WARN_ON(dev_priv->mm.aliasing_ppgtt);
1840 mutex_unlock(&dev->struct_mutex);
1841 i915_gem_cleanup_stolen(dev);
1843 if (!I915_NEED_GFX_HWS(dev))
1847 list_del(&dev_priv->gtt.base.global_link);
1848 WARN_ON(!list_empty(&dev_priv->vm_list));
1850 drm_vblank_cleanup(dev);
1852 intel_teardown_gmbus(dev);
1853 intel_teardown_mchbar(dev);
1855 destroy_workqueue(dev_priv->wq);
1856 pm_qos_remove_request(&dev_priv->pm_qos);
1858 dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1860 intel_uncore_fini(dev);
1861 if (dev_priv->regs != NULL)
1862 pci_iounmap(dev->pdev, dev_priv->regs);
1865 kmem_cache_destroy(dev_priv->slab);
1867 pci_dev_put(dev_priv->bridge_dev);
1868 kfree(dev->dev_private);
1873 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1877 ret = i915_gem_open(dev, file);
1885 * i915_driver_lastclose - clean up after all DRM clients have exited
1888 * Take care of cleaning up after all DRM clients have exited. In the
1889 * mode setting case, we want to restore the kernel's initial mode (just
1890 * in case the last client left us in a bad state).
1892 * Additionally, in the non-mode setting case, we'll tear down the GTT
1893 * and DMA structures, since the kernel won't be using them, and clea
1896 void i915_driver_lastclose(struct drm_device * dev)
1898 struct drm_i915_private *dev_priv = dev->dev_private;
1900 /* On gen6+ we refuse to init without kms enabled, but then the drm core
1901 * goes right around and calls lastclose. Check for this and don't clean
1906 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1907 intel_fbdev_restore_mode(dev);
1908 vga_switcheroo_process_delayed_switch();
1912 i915_gem_lastclose(dev);
1914 i915_dma_cleanup(dev);
1917 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1919 mutex_lock(&dev->struct_mutex);
1920 i915_gem_context_close(dev, file_priv);
1921 i915_gem_release(dev, file_priv);
1922 mutex_unlock(&dev->struct_mutex);
1925 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1927 struct drm_i915_file_private *file_priv = file->driver_priv;
1932 const struct drm_ioctl_desc i915_ioctls[] = {
1933 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1934 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1935 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1936 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1937 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1938 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1939 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1940 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1941 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1942 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1943 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1944 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1945 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1946 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1947 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
1948 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1949 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1950 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1951 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1952 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1953 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1954 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1955 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1956 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1957 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1958 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1959 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1960 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1961 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1962 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1963 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1964 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1965 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1966 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1967 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1968 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1969 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1970 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1971 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1972 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1973 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1974 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1975 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1976 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1977 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1978 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1979 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1980 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1981 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1984 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1987 * This is really ugly: Because old userspace abused the linux agp interface to
1988 * manage the gtt, we need to claim that all intel devices are agp. For
1989 * otherwise the drm core refuses to initialize the agp support code.
1991 int i915_driver_device_is_agp(struct drm_device * dev)