1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include "intel_drv.h"
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include <linux/pci.h>
39 #include <linux/vgaarb.h>
40 #include <linux/acpi.h>
41 #include <linux/pnp.h>
42 #include <linux/vga_switcheroo.h>
43 #include <linux/slab.h>
44 #include <acpi/video.h>
47 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
49 #define BEGIN_LP_RING(n) \
50 intel_ring_begin(LP_RING(dev_priv), (n))
53 intel_ring_emit(LP_RING(dev_priv), x)
55 #define ADVANCE_LP_RING() \
56 intel_ring_advance(LP_RING(dev_priv))
59 * Lock test for when it's just for synchronization of ring access.
61 * In that case, we don't need to do it when GEM is initialized as nobody else
62 * has access to the ring.
64 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
65 if (LP_RING(dev->dev_private)->obj == NULL) \
66 LOCK_TEST_WITH_RETURN(dev, file); \
70 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
72 if (I915_NEED_GFX_HWS(dev_priv->dev))
73 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
75 return intel_read_status_page(LP_RING(dev_priv), reg);
78 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
79 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
80 #define I915_BREADCRUMB_INDEX 0x21
82 void i915_update_dri1_breadcrumb(struct drm_device *dev)
84 drm_i915_private_t *dev_priv = dev->dev_private;
85 struct drm_i915_master_private *master_priv;
87 if (dev->primary->master) {
88 master_priv = dev->primary->master->driver_priv;
89 if (master_priv->sarea_priv)
90 master_priv->sarea_priv->last_dispatch =
91 READ_BREADCRUMB(dev_priv);
95 static void i915_write_hws_pga(struct drm_device *dev)
97 drm_i915_private_t *dev_priv = dev->dev_private;
100 addr = dev_priv->status_page_dmah->busaddr;
101 if (INTEL_INFO(dev)->gen >= 4)
102 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
103 I915_WRITE(HWS_PGA, addr);
107 * Frees the hardware status page, whether it's a physical address or a virtual
108 * address set up by the X Server.
110 static void i915_free_hws(struct drm_device *dev)
112 drm_i915_private_t *dev_priv = dev->dev_private;
113 struct intel_ring_buffer *ring = LP_RING(dev_priv);
115 if (dev_priv->status_page_dmah) {
116 drm_pci_free(dev, dev_priv->status_page_dmah);
117 dev_priv->status_page_dmah = NULL;
120 if (ring->status_page.gfx_addr) {
121 ring->status_page.gfx_addr = 0;
122 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
125 /* Need to rewrite hardware status page */
126 I915_WRITE(HWS_PGA, 0x1ffff000);
129 void i915_kernel_lost_context(struct drm_device * dev)
131 drm_i915_private_t *dev_priv = dev->dev_private;
132 struct drm_i915_master_private *master_priv;
133 struct intel_ring_buffer *ring = LP_RING(dev_priv);
136 * We should never lose context on the ring with modesetting
137 * as we don't expose it to userspace
139 if (drm_core_check_feature(dev, DRIVER_MODESET))
142 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
143 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
144 ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
146 ring->space += ring->size;
148 if (!dev->primary->master)
151 master_priv = dev->primary->master->driver_priv;
152 if (ring->head == ring->tail && master_priv->sarea_priv)
153 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
156 static int i915_dma_cleanup(struct drm_device * dev)
158 drm_i915_private_t *dev_priv = dev->dev_private;
161 /* Make sure interrupts are disabled here because the uninstall ioctl
162 * may not have been called from userspace and after dev_private
163 * is freed, it's too late.
165 if (dev->irq_enabled)
166 drm_irq_uninstall(dev);
168 mutex_lock(&dev->struct_mutex);
169 for (i = 0; i < I915_NUM_RINGS; i++)
170 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
171 mutex_unlock(&dev->struct_mutex);
173 /* Clear the HWS virtual address at teardown */
174 if (I915_NEED_GFX_HWS(dev))
180 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
182 drm_i915_private_t *dev_priv = dev->dev_private;
183 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
186 master_priv->sarea = drm_getsarea(dev);
187 if (master_priv->sarea) {
188 master_priv->sarea_priv = (drm_i915_sarea_t *)
189 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
191 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
194 if (init->ring_size != 0) {
195 if (LP_RING(dev_priv)->obj != NULL) {
196 i915_dma_cleanup(dev);
197 DRM_ERROR("Client tried to initialize ringbuffer in "
202 ret = intel_render_ring_init_dri(dev,
206 i915_dma_cleanup(dev);
211 dev_priv->dri1.cpp = init->cpp;
212 dev_priv->dri1.back_offset = init->back_offset;
213 dev_priv->dri1.front_offset = init->front_offset;
214 dev_priv->dri1.current_page = 0;
215 if (master_priv->sarea_priv)
216 master_priv->sarea_priv->pf_current_page = 0;
218 /* Allow hardware batchbuffers unless told otherwise.
220 dev_priv->dri1.allow_batchbuffer = 1;
225 static int i915_dma_resume(struct drm_device * dev)
227 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
228 struct intel_ring_buffer *ring = LP_RING(dev_priv);
230 DRM_DEBUG_DRIVER("%s\n", __func__);
232 if (ring->virtual_start == NULL) {
233 DRM_ERROR("can not ioremap virtual address for"
238 /* Program Hardware Status Page */
239 if (!ring->status_page.page_addr) {
240 DRM_ERROR("Can not find hardware status page\n");
243 DRM_DEBUG_DRIVER("hw status page @ %p\n",
244 ring->status_page.page_addr);
245 if (ring->status_page.gfx_addr != 0)
246 intel_ring_setup_status_page(ring);
248 i915_write_hws_pga(dev);
250 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
255 static int i915_dma_init(struct drm_device *dev, void *data,
256 struct drm_file *file_priv)
258 drm_i915_init_t *init = data;
261 if (drm_core_check_feature(dev, DRIVER_MODESET))
264 switch (init->func) {
266 retcode = i915_initialize(dev, init);
268 case I915_CLEANUP_DMA:
269 retcode = i915_dma_cleanup(dev);
271 case I915_RESUME_DMA:
272 retcode = i915_dma_resume(dev);
282 /* Implement basically the same security restrictions as hardware does
283 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
285 * Most of the calculations below involve calculating the size of a
286 * particular instruction. It's important to get the size right as
287 * that tells us where the next instruction to check is. Any illegal
288 * instruction detected will be given a size of zero, which is a
289 * signal to abort the rest of the buffer.
291 static int validate_cmd(int cmd)
293 switch (((cmd >> 29) & 0x7)) {
295 switch ((cmd >> 23) & 0x3f) {
297 return 1; /* MI_NOOP */
299 return 1; /* MI_FLUSH */
301 return 0; /* disallow everything else */
305 return 0; /* reserved */
307 return (cmd & 0xff) + 2; /* 2d commands */
309 if (((cmd >> 24) & 0x1f) <= 0x18)
312 switch ((cmd >> 24) & 0x1f) {
316 switch ((cmd >> 16) & 0xff) {
318 return (cmd & 0x1f) + 2;
320 return (cmd & 0xf) + 2;
322 return (cmd & 0xffff) + 2;
326 return (cmd & 0xffff) + 1;
330 if ((cmd & (1 << 23)) == 0) /* inline vertices */
331 return (cmd & 0x1ffff) + 2;
332 else if (cmd & (1 << 17)) /* indirect random */
333 if ((cmd & 0xffff) == 0)
334 return 0; /* unknown length, too hard */
336 return (((cmd & 0xffff) + 1) / 2) + 1;
338 return 2; /* indirect sequential */
349 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
351 drm_i915_private_t *dev_priv = dev->dev_private;
354 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
357 for (i = 0; i < dwords;) {
358 int sz = validate_cmd(buffer[i]);
359 if (sz == 0 || i + sz > dwords)
364 ret = BEGIN_LP_RING((dwords+1)&~1);
368 for (i = 0; i < dwords; i++)
379 i915_emit_box(struct drm_device *dev,
380 struct drm_clip_rect *box,
383 struct drm_i915_private *dev_priv = dev->dev_private;
386 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
387 box->y2 <= 0 || box->x2 <= 0) {
388 DRM_ERROR("Bad box %d,%d..%d,%d\n",
389 box->x1, box->y1, box->x2, box->y2);
393 if (INTEL_INFO(dev)->gen >= 4) {
394 ret = BEGIN_LP_RING(4);
398 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
399 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
400 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
403 ret = BEGIN_LP_RING(6);
407 OUT_RING(GFX_OP_DRAWRECT_INFO);
409 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
410 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
419 /* XXX: Emitting the counter should really be moved to part of the IRQ
420 * emit. For now, do it in both places:
423 static void i915_emit_breadcrumb(struct drm_device *dev)
425 drm_i915_private_t *dev_priv = dev->dev_private;
426 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
428 dev_priv->dri1.counter++;
429 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
430 dev_priv->dri1.counter = 0;
431 if (master_priv->sarea_priv)
432 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
434 if (BEGIN_LP_RING(4) == 0) {
435 OUT_RING(MI_STORE_DWORD_INDEX);
436 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
437 OUT_RING(dev_priv->dri1.counter);
443 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
444 drm_i915_cmdbuffer_t *cmd,
445 struct drm_clip_rect *cliprects,
448 int nbox = cmd->num_cliprects;
449 int i = 0, count, ret;
452 DRM_ERROR("alignment");
456 i915_kernel_lost_context(dev);
458 count = nbox ? nbox : 1;
460 for (i = 0; i < count; i++) {
462 ret = i915_emit_box(dev, &cliprects[i],
468 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
473 i915_emit_breadcrumb(dev);
477 static int i915_dispatch_batchbuffer(struct drm_device * dev,
478 drm_i915_batchbuffer_t * batch,
479 struct drm_clip_rect *cliprects)
481 struct drm_i915_private *dev_priv = dev->dev_private;
482 int nbox = batch->num_cliprects;
485 if ((batch->start | batch->used) & 0x7) {
486 DRM_ERROR("alignment");
490 i915_kernel_lost_context(dev);
492 count = nbox ? nbox : 1;
493 for (i = 0; i < count; i++) {
495 ret = i915_emit_box(dev, &cliprects[i],
496 batch->DR1, batch->DR4);
501 if (!IS_I830(dev) && !IS_845G(dev)) {
502 ret = BEGIN_LP_RING(2);
506 if (INTEL_INFO(dev)->gen >= 4) {
507 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
508 OUT_RING(batch->start);
510 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
511 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
514 ret = BEGIN_LP_RING(4);
518 OUT_RING(MI_BATCH_BUFFER);
519 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
520 OUT_RING(batch->start + batch->used - 4);
527 if (IS_G4X(dev) || IS_GEN5(dev)) {
528 if (BEGIN_LP_RING(2) == 0) {
529 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
535 i915_emit_breadcrumb(dev);
539 static int i915_dispatch_flip(struct drm_device * dev)
541 drm_i915_private_t *dev_priv = dev->dev_private;
542 struct drm_i915_master_private *master_priv =
543 dev->primary->master->driver_priv;
546 if (!master_priv->sarea_priv)
549 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
551 dev_priv->dri1.current_page,
552 master_priv->sarea_priv->pf_current_page);
554 i915_kernel_lost_context(dev);
556 ret = BEGIN_LP_RING(10);
560 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
563 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
565 if (dev_priv->dri1.current_page == 0) {
566 OUT_RING(dev_priv->dri1.back_offset);
567 dev_priv->dri1.current_page = 1;
569 OUT_RING(dev_priv->dri1.front_offset);
570 dev_priv->dri1.current_page = 0;
574 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
579 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
581 if (BEGIN_LP_RING(4) == 0) {
582 OUT_RING(MI_STORE_DWORD_INDEX);
583 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
584 OUT_RING(dev_priv->dri1.counter);
589 master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
593 static int i915_quiescent(struct drm_device *dev)
595 i915_kernel_lost_context(dev);
596 return intel_ring_idle(LP_RING(dev->dev_private));
599 static int i915_flush_ioctl(struct drm_device *dev, void *data,
600 struct drm_file *file_priv)
604 if (drm_core_check_feature(dev, DRIVER_MODESET))
607 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
609 mutex_lock(&dev->struct_mutex);
610 ret = i915_quiescent(dev);
611 mutex_unlock(&dev->struct_mutex);
616 static int i915_batchbuffer(struct drm_device *dev, void *data,
617 struct drm_file *file_priv)
619 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
620 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
621 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
622 master_priv->sarea_priv;
623 drm_i915_batchbuffer_t *batch = data;
625 struct drm_clip_rect *cliprects = NULL;
627 if (drm_core_check_feature(dev, DRIVER_MODESET))
630 if (!dev_priv->dri1.allow_batchbuffer) {
631 DRM_ERROR("Batchbuffer ioctl disabled\n");
635 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
636 batch->start, batch->used, batch->num_cliprects);
638 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
640 if (batch->num_cliprects < 0)
643 if (batch->num_cliprects) {
644 cliprects = kcalloc(batch->num_cliprects,
645 sizeof(struct drm_clip_rect),
647 if (cliprects == NULL)
650 ret = copy_from_user(cliprects, batch->cliprects,
651 batch->num_cliprects *
652 sizeof(struct drm_clip_rect));
659 mutex_lock(&dev->struct_mutex);
660 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
661 mutex_unlock(&dev->struct_mutex);
664 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
672 static int i915_cmdbuffer(struct drm_device *dev, void *data,
673 struct drm_file *file_priv)
675 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
676 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
677 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
678 master_priv->sarea_priv;
679 drm_i915_cmdbuffer_t *cmdbuf = data;
680 struct drm_clip_rect *cliprects = NULL;
684 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
685 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
687 if (drm_core_check_feature(dev, DRIVER_MODESET))
690 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
692 if (cmdbuf->num_cliprects < 0)
695 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
696 if (batch_data == NULL)
699 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
702 goto fail_batch_free;
705 if (cmdbuf->num_cliprects) {
706 cliprects = kcalloc(cmdbuf->num_cliprects,
707 sizeof(struct drm_clip_rect), GFP_KERNEL);
708 if (cliprects == NULL) {
710 goto fail_batch_free;
713 ret = copy_from_user(cliprects, cmdbuf->cliprects,
714 cmdbuf->num_cliprects *
715 sizeof(struct drm_clip_rect));
722 mutex_lock(&dev->struct_mutex);
723 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
724 mutex_unlock(&dev->struct_mutex);
726 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
731 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
741 static int i915_emit_irq(struct drm_device * dev)
743 drm_i915_private_t *dev_priv = dev->dev_private;
744 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
746 i915_kernel_lost_context(dev);
748 DRM_DEBUG_DRIVER("\n");
750 dev_priv->dri1.counter++;
751 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
752 dev_priv->dri1.counter = 1;
753 if (master_priv->sarea_priv)
754 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
756 if (BEGIN_LP_RING(4) == 0) {
757 OUT_RING(MI_STORE_DWORD_INDEX);
758 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
759 OUT_RING(dev_priv->dri1.counter);
760 OUT_RING(MI_USER_INTERRUPT);
764 return dev_priv->dri1.counter;
767 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
769 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
770 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
772 struct intel_ring_buffer *ring = LP_RING(dev_priv);
774 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
775 READ_BREADCRUMB(dev_priv));
777 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
778 if (master_priv->sarea_priv)
779 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
783 if (master_priv->sarea_priv)
784 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
786 if (ring->irq_get(ring)) {
787 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
788 READ_BREADCRUMB(dev_priv) >= irq_nr);
790 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
794 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
795 READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
801 /* Needs the lock as it touches the ring.
803 static int i915_irq_emit(struct drm_device *dev, void *data,
804 struct drm_file *file_priv)
806 drm_i915_private_t *dev_priv = dev->dev_private;
807 drm_i915_irq_emit_t *emit = data;
810 if (drm_core_check_feature(dev, DRIVER_MODESET))
813 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
814 DRM_ERROR("called with no initialization\n");
818 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
820 mutex_lock(&dev->struct_mutex);
821 result = i915_emit_irq(dev);
822 mutex_unlock(&dev->struct_mutex);
824 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
825 DRM_ERROR("copy_to_user\n");
832 /* Doesn't need the hardware lock.
834 static int i915_irq_wait(struct drm_device *dev, void *data,
835 struct drm_file *file_priv)
837 drm_i915_private_t *dev_priv = dev->dev_private;
838 drm_i915_irq_wait_t *irqwait = data;
840 if (drm_core_check_feature(dev, DRIVER_MODESET))
844 DRM_ERROR("called with no initialization\n");
848 return i915_wait_irq(dev, irqwait->irq_seq);
851 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
852 struct drm_file *file_priv)
854 drm_i915_private_t *dev_priv = dev->dev_private;
855 drm_i915_vblank_pipe_t *pipe = data;
857 if (drm_core_check_feature(dev, DRIVER_MODESET))
861 DRM_ERROR("called with no initialization\n");
865 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
871 * Schedule buffer swap at given vertical blank.
873 static int i915_vblank_swap(struct drm_device *dev, void *data,
874 struct drm_file *file_priv)
876 /* The delayed swap mechanism was fundamentally racy, and has been
877 * removed. The model was that the client requested a delayed flip/swap
878 * from the kernel, then waited for vblank before continuing to perform
879 * rendering. The problem was that the kernel might wake the client
880 * up before it dispatched the vblank swap (since the lock has to be
881 * held while touching the ringbuffer), in which case the client would
882 * clear and start the next frame before the swap occurred, and
883 * flicker would occur in addition to likely missing the vblank.
885 * In the absence of this ioctl, userland falls back to a correct path
886 * of waiting for a vblank, then dispatching the swap on its own.
887 * Context switching to userland and back is plenty fast enough for
888 * meeting the requirements of vblank swapping.
893 static int i915_flip_bufs(struct drm_device *dev, void *data,
894 struct drm_file *file_priv)
898 if (drm_core_check_feature(dev, DRIVER_MODESET))
901 DRM_DEBUG_DRIVER("%s\n", __func__);
903 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
905 mutex_lock(&dev->struct_mutex);
906 ret = i915_dispatch_flip(dev);
907 mutex_unlock(&dev->struct_mutex);
912 static int i915_getparam(struct drm_device *dev, void *data,
913 struct drm_file *file_priv)
915 drm_i915_private_t *dev_priv = dev->dev_private;
916 drm_i915_getparam_t *param = data;
920 DRM_ERROR("called with no initialization\n");
924 switch (param->param) {
925 case I915_PARAM_IRQ_ACTIVE:
926 value = dev->pdev->irq ? 1 : 0;
928 case I915_PARAM_ALLOW_BATCHBUFFER:
929 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
931 case I915_PARAM_LAST_DISPATCH:
932 value = READ_BREADCRUMB(dev_priv);
934 case I915_PARAM_CHIPSET_ID:
935 value = dev->pci_device;
937 case I915_PARAM_HAS_GEM:
940 case I915_PARAM_NUM_FENCES_AVAIL:
941 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
943 case I915_PARAM_HAS_OVERLAY:
944 value = dev_priv->overlay ? 1 : 0;
946 case I915_PARAM_HAS_PAGEFLIPPING:
949 case I915_PARAM_HAS_EXECBUF2:
953 case I915_PARAM_HAS_BSD:
954 value = intel_ring_initialized(&dev_priv->ring[VCS]);
956 case I915_PARAM_HAS_BLT:
957 value = intel_ring_initialized(&dev_priv->ring[BCS]);
959 case I915_PARAM_HAS_RELAXED_FENCING:
962 case I915_PARAM_HAS_COHERENT_RINGS:
965 case I915_PARAM_HAS_EXEC_CONSTANTS:
966 value = INTEL_INFO(dev)->gen >= 4;
968 case I915_PARAM_HAS_RELAXED_DELTA:
971 case I915_PARAM_HAS_GEN7_SOL_RESET:
974 case I915_PARAM_HAS_LLC:
975 value = HAS_LLC(dev);
977 case I915_PARAM_HAS_ALIASING_PPGTT:
978 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
980 case I915_PARAM_HAS_WAIT_TIMEOUT:
983 case I915_PARAM_HAS_SEMAPHORES:
984 value = i915_semaphore_is_enabled(dev);
986 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
989 case I915_PARAM_HAS_SECURE_BATCHES:
990 value = capable(CAP_SYS_ADMIN);
992 case I915_PARAM_HAS_PINNED_BATCHES:
995 case I915_PARAM_HAS_EXEC_NO_RELOC:
998 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1002 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
1007 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1008 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1015 static int i915_setparam(struct drm_device *dev, void *data,
1016 struct drm_file *file_priv)
1018 drm_i915_private_t *dev_priv = dev->dev_private;
1019 drm_i915_setparam_t *param = data;
1022 DRM_ERROR("called with no initialization\n");
1026 switch (param->param) {
1027 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1029 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1031 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1032 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1034 case I915_SETPARAM_NUM_USED_FENCES:
1035 if (param->value > dev_priv->num_fence_regs ||
1038 /* Userspace can use first N regs */
1039 dev_priv->fence_reg_start = param->value;
1042 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1050 static int i915_set_status_page(struct drm_device *dev, void *data,
1051 struct drm_file *file_priv)
1053 drm_i915_private_t *dev_priv = dev->dev_private;
1054 drm_i915_hws_addr_t *hws = data;
1055 struct intel_ring_buffer *ring;
1057 if (drm_core_check_feature(dev, DRIVER_MODESET))
1060 if (!I915_NEED_GFX_HWS(dev))
1064 DRM_ERROR("called with no initialization\n");
1068 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1069 WARN(1, "tried to set status page when mode setting active\n");
1073 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1075 ring = LP_RING(dev_priv);
1076 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1078 dev_priv->dri1.gfx_hws_cpu_addr =
1079 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1080 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1081 i915_dma_cleanup(dev);
1082 ring->status_page.gfx_addr = 0;
1083 DRM_ERROR("can not ioremap virtual address for"
1084 " G33 hw status page\n");
1088 memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1089 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1091 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1092 ring->status_page.gfx_addr);
1093 DRM_DEBUG_DRIVER("load hws at %p\n",
1094 ring->status_page.page_addr);
1098 static int i915_get_bridge_dev(struct drm_device *dev)
1100 struct drm_i915_private *dev_priv = dev->dev_private;
1102 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1103 if (!dev_priv->bridge_dev) {
1104 DRM_ERROR("bridge device not found\n");
1110 #define MCHBAR_I915 0x44
1111 #define MCHBAR_I965 0x48
1112 #define MCHBAR_SIZE (4*4096)
1114 #define DEVEN_REG 0x54
1115 #define DEVEN_MCHBAR_EN (1 << 28)
1117 /* Allocate space for the MCH regs if needed, return nonzero on error */
1119 intel_alloc_mchbar_resource(struct drm_device *dev)
1121 drm_i915_private_t *dev_priv = dev->dev_private;
1122 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1123 u32 temp_lo, temp_hi = 0;
1127 if (INTEL_INFO(dev)->gen >= 4)
1128 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1129 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1130 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1132 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1135 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1139 /* Get some space for it */
1140 dev_priv->mch_res.name = "i915 MCHBAR";
1141 dev_priv->mch_res.flags = IORESOURCE_MEM;
1142 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1144 MCHBAR_SIZE, MCHBAR_SIZE,
1146 0, pcibios_align_resource,
1147 dev_priv->bridge_dev);
1149 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1150 dev_priv->mch_res.start = 0;
1154 if (INTEL_INFO(dev)->gen >= 4)
1155 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1156 upper_32_bits(dev_priv->mch_res.start));
1158 pci_write_config_dword(dev_priv->bridge_dev, reg,
1159 lower_32_bits(dev_priv->mch_res.start));
1163 /* Setup MCHBAR if possible, return true if we should disable it again */
1165 intel_setup_mchbar(struct drm_device *dev)
1167 drm_i915_private_t *dev_priv = dev->dev_private;
1168 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1172 dev_priv->mchbar_need_disable = false;
1174 if (IS_I915G(dev) || IS_I915GM(dev)) {
1175 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1176 enabled = !!(temp & DEVEN_MCHBAR_EN);
1178 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1182 /* If it's already enabled, don't have to do anything */
1186 if (intel_alloc_mchbar_resource(dev))
1189 dev_priv->mchbar_need_disable = true;
1191 /* Space is allocated or reserved, so enable it. */
1192 if (IS_I915G(dev) || IS_I915GM(dev)) {
1193 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1194 temp | DEVEN_MCHBAR_EN);
1196 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1197 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1202 intel_teardown_mchbar(struct drm_device *dev)
1204 drm_i915_private_t *dev_priv = dev->dev_private;
1205 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1208 if (dev_priv->mchbar_need_disable) {
1209 if (IS_I915G(dev) || IS_I915GM(dev)) {
1210 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1211 temp &= ~DEVEN_MCHBAR_EN;
1212 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1214 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1216 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1220 if (dev_priv->mch_res.start)
1221 release_resource(&dev_priv->mch_res);
1224 /* true = enable decode, false = disable decoder */
1225 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1227 struct drm_device *dev = cookie;
1229 intel_modeset_vga_set_state(dev, state);
1231 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1232 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1234 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1237 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1239 struct drm_device *dev = pci_get_drvdata(pdev);
1240 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1241 if (state == VGA_SWITCHEROO_ON) {
1242 pr_info("switched on\n");
1243 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1244 /* i915 resume handler doesn't set to D0 */
1245 pci_set_power_state(dev->pdev, PCI_D0);
1247 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1249 pr_err("switched off\n");
1250 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1251 i915_suspend(dev, pmm);
1252 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1256 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1258 struct drm_device *dev = pci_get_drvdata(pdev);
1261 spin_lock(&dev->count_lock);
1262 can_switch = (dev->open_count == 0);
1263 spin_unlock(&dev->count_lock);
1267 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1268 .set_gpu_state = i915_switcheroo_set_state,
1270 .can_switch = i915_switcheroo_can_switch,
1273 static int i915_load_modeset_init(struct drm_device *dev)
1275 struct drm_i915_private *dev_priv = dev->dev_private;
1278 ret = intel_parse_bios(dev);
1280 DRM_INFO("failed to find VBIOS tables\n");
1282 /* If we have > 1 VGA cards, then we need to arbitrate access
1283 * to the common VGA resources.
1285 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1286 * then we do not take part in VGA arbitration and the
1287 * vga_client_register() fails with -ENODEV.
1289 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1290 if (ret && ret != -ENODEV)
1293 intel_register_dsm_handler();
1295 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1297 goto cleanup_vga_client;
1299 /* Initialise stolen first so that we may reserve preallocated
1300 * objects for the BIOS to KMS transition.
1302 ret = i915_gem_init_stolen(dev);
1304 goto cleanup_vga_switcheroo;
1306 ret = drm_irq_install(dev);
1308 goto cleanup_gem_stolen;
1310 /* Important: The output setup functions called by modeset_init need
1311 * working irqs for e.g. gmbus and dp aux transfers. */
1312 intel_modeset_init(dev);
1314 ret = i915_gem_init(dev);
1318 INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1320 intel_modeset_gem_init(dev);
1322 /* Always safe in the mode setting case. */
1323 /* FIXME: do pre/post-mode set stuff in core KMS code */
1324 dev->vblank_disable_allowed = 1;
1326 ret = intel_fbdev_init(dev);
1330 /* Only enable hotplug handling once the fbdev is fully set up. */
1331 intel_hpd_init(dev);
1334 * Some ports require correctly set-up hpd registers for detection to
1335 * work properly (leading to ghost connected connector status), e.g. VGA
1336 * on gm45. Hence we can only set up the initial fbdev config after hpd
1337 * irqs are fully enabled. Now we should scan for the initial config
1338 * only once hotplug handling is enabled, but due to screwed-up locking
1339 * around kms/fbdev init we can't protect the fdbev initial config
1340 * scanning against hotplug events. Hence do this first and ignore the
1341 * tiny window where we will loose hotplug notifactions.
1343 intel_fbdev_initial_config(dev);
1345 /* Only enable hotplug handling once the fbdev is fully set up. */
1346 dev_priv->enable_hotplug_processing = true;
1348 drm_kms_helper_poll_init(dev);
1350 /* We're off and running w/KMS */
1351 dev_priv->mm.suspended = 0;
1356 mutex_lock(&dev->struct_mutex);
1357 i915_gem_cleanup_ringbuffer(dev);
1358 mutex_unlock(&dev->struct_mutex);
1359 i915_gem_cleanup_aliasing_ppgtt(dev);
1361 drm_irq_uninstall(dev);
1363 i915_gem_cleanup_stolen(dev);
1364 cleanup_vga_switcheroo:
1365 vga_switcheroo_unregister_client(dev->pdev);
1367 vga_client_register(dev->pdev, NULL, NULL, NULL);
1372 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1374 struct drm_i915_master_private *master_priv;
1376 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1380 master->driver_priv = master_priv;
1384 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1386 struct drm_i915_master_private *master_priv = master->driver_priv;
1393 master->driver_priv = NULL;
1397 i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1400 dev_priv->mm.gtt_mtrr = -1;
1402 #if defined(CONFIG_X86_PAT)
1407 /* Set up a WC MTRR for non-PAT systems. This is more common than
1408 * one would think, because the kernel disables PAT on first
1409 * generation Core chips because WC PAT gets overridden by a UC
1410 * MTRR if present. Even if a UC MTRR isn't present.
1412 dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
1413 if (dev_priv->mm.gtt_mtrr < 0) {
1414 DRM_INFO("MTRR allocation failed. Graphics "
1415 "performance may suffer.\n");
1419 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1421 struct apertures_struct *ap;
1422 struct pci_dev *pdev = dev_priv->dev->pdev;
1425 ap = alloc_apertures(1);
1429 ap->ranges[0].base = dev_priv->gtt.mappable_base;
1430 ap->ranges[0].size = dev_priv->gtt.mappable_end - dev_priv->gtt.start;
1433 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1435 remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1440 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1442 const struct intel_device_info *info = dev_priv->info;
1444 #define DEV_INFO_FLAG(name) info->name ? #name "," : ""
1445 #define DEV_INFO_SEP ,
1446 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1447 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
1449 dev_priv->dev->pdev->device,
1451 #undef DEV_INFO_FLAG
1456 * intel_early_sanitize_regs - clean up BIOS state
1459 * This function must be called before we do any I915_READ or I915_WRITE. Its
1460 * purpose is to clean up any state left by the BIOS that may affect us when
1461 * reading and/or writing registers.
1463 static void intel_early_sanitize_regs(struct drm_device *dev)
1465 struct drm_i915_private *dev_priv = dev->dev_private;
1467 if (IS_HASWELL(dev))
1468 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1472 * i915_driver_load - setup chip and create an initial config
1474 * @flags: startup flags
1476 * The driver load routine has to do several things:
1477 * - drive output discovery via intel_modeset_init()
1478 * - initialize the memory manager
1479 * - allocate initial config memory
1480 * - setup the DRM framebuffer with the allocated memory
1482 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1484 struct drm_i915_private *dev_priv;
1485 struct intel_device_info *info;
1486 int ret = 0, mmio_bar, mmio_size;
1487 uint32_t aperture_size;
1489 info = (struct intel_device_info *) flags;
1491 /* Refuse to load on gen6+ without kms enabled. */
1492 if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1495 /* i915 has 4 more counters */
1497 dev->types[6] = _DRM_STAT_IRQ;
1498 dev->types[7] = _DRM_STAT_PRIMARY;
1499 dev->types[8] = _DRM_STAT_SECONDARY;
1500 dev->types[9] = _DRM_STAT_DMA;
1502 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1503 if (dev_priv == NULL)
1506 dev->dev_private = (void *)dev_priv;
1507 dev_priv->dev = dev;
1508 dev_priv->info = info;
1510 i915_dump_device_info(dev_priv);
1512 if (i915_get_bridge_dev(dev)) {
1517 ret = i915_gem_gtt_init(dev);
1521 if (drm_core_check_feature(dev, DRIVER_MODESET))
1522 i915_kick_out_firmware_fb(dev_priv);
1524 pci_set_master(dev->pdev);
1526 /* overlay on gen2 is broken and can't address above 1G */
1528 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1530 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1531 * using 32bit addressing, overwriting memory if HWS is located
1534 * The documentation also mentions an issue with undefined
1535 * behaviour if any general state is accessed within a page above 4GB,
1536 * which also needs to be handled carefully.
1538 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1539 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1541 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1542 /* Before gen4, the registers and the GTT are behind different BARs.
1543 * However, from gen4 onwards, the registers and the GTT are shared
1544 * in the same BAR, so we want to restrict this ioremap from
1545 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1546 * the register BAR remains the same size for all the earlier
1547 * generations up to Ironlake.
1550 mmio_size = 512*1024;
1552 mmio_size = 2*1024*1024;
1554 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1555 if (!dev_priv->regs) {
1556 DRM_ERROR("failed to map registers\n");
1561 intel_early_sanitize_regs(dev);
1563 aperture_size = dev_priv->gtt.mappable_end;
1565 dev_priv->gtt.mappable =
1566 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1568 if (dev_priv->gtt.mappable == NULL) {
1573 i915_mtrr_setup(dev_priv, dev_priv->gtt.mappable_base,
1576 /* The i915 workqueue is primarily used for batched retirement of
1577 * requests (and thus managing bo) once the task has been completed
1578 * by the GPU. i915_gem_retire_requests() is called directly when we
1579 * need high-priority retirement, such as waiting for an explicit
1582 * It is also used for periodic low-priority events, such as
1583 * idle-timers and recording error state.
1585 * All tasks on the workqueue are expected to acquire the dev mutex
1586 * so there is no point in running more than one instance of the
1587 * workqueue at any time. Use an ordered one.
1589 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1590 if (dev_priv->wq == NULL) {
1591 DRM_ERROR("Failed to create our workqueue.\n");
1596 /* This must be called before any calls to HAS_PCH_* */
1597 intel_detect_pch(dev);
1599 intel_irq_init(dev);
1602 /* Try to make sure MCHBAR is enabled before poking at it */
1603 intel_setup_mchbar(dev);
1604 intel_setup_gmbus(dev);
1605 intel_opregion_setup(dev);
1607 intel_setup_bios(dev);
1611 /* On the 945G/GM, the chipset reports the MSI capability on the
1612 * integrated graphics even though the support isn't actually there
1613 * according to the published specs. It doesn't appear to function
1614 * correctly in testing on 945G.
1615 * This may be a side effect of MSI having been made available for PEG
1616 * and the registers being closely associated.
1618 * According to chipset errata, on the 965GM, MSI interrupts may
1619 * be lost or delayed, but we use them anyways to avoid
1620 * stuck interrupts on some machines.
1622 if (!IS_I945G(dev) && !IS_I945GM(dev))
1623 pci_enable_msi(dev->pdev);
1625 spin_lock_init(&dev_priv->irq_lock);
1626 spin_lock_init(&dev_priv->gpu_error.lock);
1627 spin_lock_init(&dev_priv->rps.lock);
1628 mutex_init(&dev_priv->dpio_lock);
1630 mutex_init(&dev_priv->rps.hw_lock);
1631 mutex_init(&dev_priv->modeset_restore_lock);
1633 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1634 dev_priv->num_pipe = 3;
1635 else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1636 dev_priv->num_pipe = 2;
1638 dev_priv->num_pipe = 1;
1640 ret = drm_vblank_init(dev, dev_priv->num_pipe);
1642 goto out_gem_unload;
1644 /* Start out suspended */
1645 dev_priv->mm.suspended = 1;
1647 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1648 ret = i915_load_modeset_init(dev);
1650 DRM_ERROR("failed to init modeset\n");
1651 goto out_gem_unload;
1655 i915_setup_sysfs(dev);
1657 /* Must be done after probing outputs */
1658 intel_opregion_init(dev);
1659 acpi_video_register();
1662 intel_gpu_ips_init(dev_priv);
1667 if (dev_priv->mm.inactive_shrinker.shrink)
1668 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1670 if (dev->pdev->msi_enabled)
1671 pci_disable_msi(dev->pdev);
1673 intel_teardown_gmbus(dev);
1674 intel_teardown_mchbar(dev);
1675 destroy_workqueue(dev_priv->wq);
1677 if (dev_priv->mm.gtt_mtrr >= 0) {
1678 mtrr_del(dev_priv->mm.gtt_mtrr,
1679 dev_priv->gtt.mappable_base,
1681 dev_priv->mm.gtt_mtrr = -1;
1683 io_mapping_free(dev_priv->gtt.mappable);
1685 pci_iounmap(dev->pdev, dev_priv->regs);
1687 dev_priv->gtt.gtt_remove(dev);
1689 pci_dev_put(dev_priv->bridge_dev);
1695 int i915_driver_unload(struct drm_device *dev)
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1700 intel_gpu_ips_teardown();
1702 i915_teardown_sysfs(dev);
1704 if (dev_priv->mm.inactive_shrinker.shrink)
1705 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1707 mutex_lock(&dev->struct_mutex);
1708 ret = i915_gpu_idle(dev);
1710 DRM_ERROR("failed to idle hardware: %d\n", ret);
1711 i915_gem_retire_requests(dev);
1712 mutex_unlock(&dev->struct_mutex);
1714 /* Cancel the retire work handler, which should be idle now. */
1715 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1717 io_mapping_free(dev_priv->gtt.mappable);
1718 if (dev_priv->mm.gtt_mtrr >= 0) {
1719 mtrr_del(dev_priv->mm.gtt_mtrr,
1720 dev_priv->gtt.mappable_base,
1721 dev_priv->gtt.mappable_end);
1722 dev_priv->mm.gtt_mtrr = -1;
1725 acpi_video_unregister();
1727 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1728 intel_fbdev_fini(dev);
1729 intel_modeset_cleanup(dev);
1730 cancel_work_sync(&dev_priv->console_resume_work);
1733 * free the memory space allocated for the child device
1734 * config parsed from VBT
1736 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1737 kfree(dev_priv->child_dev);
1738 dev_priv->child_dev = NULL;
1739 dev_priv->child_dev_num = 0;
1742 vga_switcheroo_unregister_client(dev->pdev);
1743 vga_client_register(dev->pdev, NULL, NULL, NULL);
1746 /* Free error state after interrupts are fully disabled. */
1747 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1748 cancel_work_sync(&dev_priv->gpu_error.work);
1749 i915_destroy_error_state(dev);
1751 if (dev->pdev->msi_enabled)
1752 pci_disable_msi(dev->pdev);
1754 intel_opregion_fini(dev);
1756 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1757 /* Flush any outstanding unpin_work. */
1758 flush_workqueue(dev_priv->wq);
1760 mutex_lock(&dev->struct_mutex);
1761 i915_gem_free_all_phys_object(dev);
1762 i915_gem_cleanup_ringbuffer(dev);
1763 i915_gem_context_fini(dev);
1764 mutex_unlock(&dev->struct_mutex);
1765 i915_gem_cleanup_aliasing_ppgtt(dev);
1766 i915_gem_cleanup_stolen(dev);
1768 if (!I915_NEED_GFX_HWS(dev))
1772 if (dev_priv->regs != NULL)
1773 pci_iounmap(dev->pdev, dev_priv->regs);
1775 intel_teardown_gmbus(dev);
1776 intel_teardown_mchbar(dev);
1778 destroy_workqueue(dev_priv->wq);
1779 pm_qos_remove_request(&dev_priv->pm_qos);
1782 kmem_cache_destroy(dev_priv->slab);
1784 pci_dev_put(dev_priv->bridge_dev);
1785 kfree(dev->dev_private);
1790 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1792 struct drm_i915_file_private *file_priv;
1794 DRM_DEBUG_DRIVER("\n");
1795 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
1799 file->driver_priv = file_priv;
1801 spin_lock_init(&file_priv->mm.lock);
1802 INIT_LIST_HEAD(&file_priv->mm.request_list);
1804 idr_init(&file_priv->context_idr);
1810 * i915_driver_lastclose - clean up after all DRM clients have exited
1813 * Take care of cleaning up after all DRM clients have exited. In the
1814 * mode setting case, we want to restore the kernel's initial mode (just
1815 * in case the last client left us in a bad state).
1817 * Additionally, in the non-mode setting case, we'll tear down the GTT
1818 * and DMA structures, since the kernel won't be using them, and clea
1821 void i915_driver_lastclose(struct drm_device * dev)
1823 drm_i915_private_t *dev_priv = dev->dev_private;
1825 /* On gen6+ we refuse to init without kms enabled, but then the drm core
1826 * goes right around and calls lastclose. Check for this and don't clean
1831 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1832 intel_fb_restore_mode(dev);
1833 vga_switcheroo_process_delayed_switch();
1837 i915_gem_lastclose(dev);
1839 i915_dma_cleanup(dev);
1842 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1844 i915_gem_context_close(dev, file_priv);
1845 i915_gem_release(dev, file_priv);
1848 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1850 struct drm_i915_file_private *file_priv = file->driver_priv;
1855 struct drm_ioctl_desc i915_ioctls[] = {
1856 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1857 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1858 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1859 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1860 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1861 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1862 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1863 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1864 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1865 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1866 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1867 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1868 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1869 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1870 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
1871 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1872 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1873 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1874 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1875 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1876 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1877 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1878 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1879 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1880 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1881 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1882 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1883 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1884 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1885 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1886 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1887 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1888 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1889 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1890 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1891 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1892 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1893 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1894 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1895 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1896 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1897 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1898 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1899 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1900 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1901 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1902 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1903 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
1906 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1909 * This is really ugly: Because old userspace abused the linux agp interface to
1910 * manage the gtt, we need to claim that all intel devices are agp. For
1911 * otherwise the drm core refuses to initialize the agp support code.
1913 int i915_driver_device_is_agp(struct drm_device * dev)