drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include <drm/drm_legacy.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38 #include "i915_vgpu.h"
  39 #include "i915_trace.h"
  40 #include <linux/pci.h>
  41 #include <linux/console.h>
  42 #include <linux/vt.h>
  43 #include <linux/vgaarb.h>
  44 #include <linux/acpi.h>
  45 #include <linux/pnp.h>
  46 #include <linux/vga_switcheroo.h>
  47 #include <linux/slab.h>
  48 #include <acpi/video.h>
  49 #include <linux/pm.h>
  50 #include <linux/pm_runtime.h>
  51 #include <linux/oom.h>
  52
  53
  54 static int i915_getparam(struct drm_device *dev, void *data,
  55                          struct drm_file *file_priv)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58         drm_i915_getparam_t *param = data;
  59         int value;
  60
  61         switch (param->param) {
  62         case I915_PARAM_IRQ_ACTIVE:
  63         case I915_PARAM_ALLOW_BATCHBUFFER:
  64         case I915_PARAM_LAST_DISPATCH:
  65                 /* Reject all old ums/dri params. */
  66                 return -ENODEV;
  67         case I915_PARAM_CHIPSET_ID:
  68                 value = dev->pdev->device;
  69                 break;
  70         case I915_PARAM_REVISION:
  71                 value = dev->pdev->revision;
  72                 break;
  73         case I915_PARAM_HAS_GEM:
  74                 value = 1;
  75                 break;
  76         case I915_PARAM_NUM_FENCES_AVAIL:
  77                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
  78                 break;
  79         case I915_PARAM_HAS_OVERLAY:
  80                 value = dev_priv->overlay ? 1 : 0;
  81                 break;
  82         case I915_PARAM_HAS_PAGEFLIPPING:
  83                 value = 1;
  84                 break;
  85         case I915_PARAM_HAS_EXECBUF2:
  86                 /* depends on GEM */
  87                 value = 1;
  88                 break;
  89         case I915_PARAM_HAS_BSD:
  90                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
  91                 break;
  92         case I915_PARAM_HAS_BLT:
  93                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
  94                 break;
  95         case I915_PARAM_HAS_VEBOX:
  96                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
  97                 break;
  98         case I915_PARAM_HAS_BSD2:
  99                 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
 100                 break;
 101         case I915_PARAM_HAS_RELAXED_FENCING:
 102                 value = 1;
 103                 break;
 104         case I915_PARAM_HAS_COHERENT_RINGS:
 105                 value = 1;
 106                 break;
 107         case I915_PARAM_HAS_EXEC_CONSTANTS:
 108                 value = INTEL_INFO(dev)->gen >= 4;
 109                 break;
 110         case I915_PARAM_HAS_RELAXED_DELTA:
 111                 value = 1;
 112                 break;
 113         case I915_PARAM_HAS_GEN7_SOL_RESET:
 114                 value = 1;
 115                 break;
 116         case I915_PARAM_HAS_LLC:
 117                 value = HAS_LLC(dev);
 118                 break;
 119         case I915_PARAM_HAS_WT:
 120                 value = HAS_WT(dev);
 121                 break;
 122         case I915_PARAM_HAS_ALIASING_PPGTT:
 123                 value = USES_PPGTT(dev);
 124                 break;
 125         case I915_PARAM_HAS_WAIT_TIMEOUT:
 126                 value = 1;
 127                 break;
 128         case I915_PARAM_HAS_SEMAPHORES:
 129                 value = i915_semaphore_is_enabled(dev);
 130                 break;
 131         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 132                 value = 1;
 133                 break;
 134         case I915_PARAM_HAS_SECURE_BATCHES:
 135                 value = capable(CAP_SYS_ADMIN);
 136                 break;
 137         case I915_PARAM_HAS_PINNED_BATCHES:
 138                 value = 1;
 139                 break;
 140         case I915_PARAM_HAS_EXEC_NO_RELOC:
 141                 value = 1;
 142                 break;
 143         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 144                 value = 1;
 145                 break;
 146         case I915_PARAM_CMD_PARSER_VERSION:
 147                 value = i915_cmd_parser_get_version();
 148                 break;
 149         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 150                 value = 1;
 151                 break;
 152         case I915_PARAM_MMAP_VERSION:
 153                 value = 1;
 154                 break;
 155         case I915_PARAM_SUBSLICE_TOTAL:
 156                 value = INTEL_INFO(dev)->subslice_total;
 157                 if (!value)
 158                         return -ENODEV;
 159                 break;
 160         case I915_PARAM_EU_TOTAL:
 161                 value = INTEL_INFO(dev)->eu_total;
 162                 if (!value)
 163                         return -ENODEV;
 164                 break;
 165         case I915_PARAM_HAS_GPU_RESET:
 166                 value = i915.enable_hangcheck &&
 167                         intel_has_gpu_reset(dev);
 168                 break;
 169         case I915_PARAM_HAS_RESOURCE_STREAMER:
 170                 value = HAS_RESOURCE_STREAMER(dev);
 171                 break;
 172         default:
 173                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 174                 return -EINVAL;
 175         }
 176
 177         if (copy_to_user(param->value, &value, sizeof(int))) {
 178                 DRM_ERROR("copy_to_user failed\n");
 179                 return -EFAULT;
 180         }
 181
 182         return 0;
 183 }
 184
 185 static int i915_setparam(struct drm_device *dev, void *data,
 186                          struct drm_file *file_priv)
 187 {
 188         struct drm_i915_private *dev_priv = dev->dev_private;
 189         drm_i915_setparam_t *param = data;
 190
 191         switch (param->param) {
 192         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 193         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 194         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 195                 /* Reject all old ums/dri params. */
 196                 return -ENODEV;
 197
 198         case I915_SETPARAM_NUM_USED_FENCES:
 199                 if (param->value > dev_priv->num_fence_regs ||
 200                     param->value < 0)
 201                         return -EINVAL;
 202                 /* Userspace can use first N regs */
 203                 dev_priv->fence_reg_start = param->value;
 204                 break;
 205         default:
 206                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 207                                         param->param);
 208                 return -EINVAL;
 209         }
 210
 211         return 0;
 212 }
 213
 214 static int i915_get_bridge_dev(struct drm_device *dev)
 215 {
 216         struct drm_i915_private *dev_priv = dev->dev_private;
 217
 218         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 219         if (!dev_priv->bridge_dev) {
 220                 DRM_ERROR("bridge device not found\n");
 221                 return -1;
 222         }
 223         return 0;
 224 }
 225
 226 #define MCHBAR_I915 0x44
 227 #define MCHBAR_I965 0x48
 228 #define MCHBAR_SIZE (4*4096)
 229
 230 #define DEVEN_REG 0x54
 231 #define   DEVEN_MCHBAR_EN (1 << 28)
 232
 233 /* Allocate space for the MCH regs if needed, return nonzero on error */
 234 static int
 235 intel_alloc_mchbar_resource(struct drm_device *dev)
 236 {
 237         struct drm_i915_private *dev_priv = dev->dev_private;
 238         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 239         u32 temp_lo, temp_hi = 0;
 240         u64 mchbar_addr;
 241         int ret;
 242
 243         if (INTEL_INFO(dev)->gen >= 4)
 244                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 245         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 246         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 247
 248         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 249 #ifdef CONFIG_PNP
 250         if (mchbar_addr &&
 251             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 252                 return 0;
 253 #endif
 254
 255         /* Get some space for it */
 256         dev_priv->mch_res.name = "i915 MCHBAR";
 257         dev_priv->mch_res.flags = IORESOURCE_MEM;
 258         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 259                                      &dev_priv->mch_res,
 260                                      MCHBAR_SIZE, MCHBAR_SIZE,
 261                                      PCIBIOS_MIN_MEM,
 262                                      0, pcibios_align_resource,
 263                                      dev_priv->bridge_dev);
 264         if (ret) {
 265                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 266                 dev_priv->mch_res.start = 0;
 267                 return ret;
 268         }
 269
 270         if (INTEL_INFO(dev)->gen >= 4)
 271                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 272                                        upper_32_bits(dev_priv->mch_res.start));
 273
 274         pci_write_config_dword(dev_priv->bridge_dev, reg,
 275                                lower_32_bits(dev_priv->mch_res.start));
 276         return 0;
 277 }
 278
 279 /* Setup MCHBAR if possible, return true if we should disable it again */
 280 static void
 281 intel_setup_mchbar(struct drm_device *dev)
 282 {
 283         struct drm_i915_private *dev_priv = dev->dev_private;
 284         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 285         u32 temp;
 286         bool enabled;
 287
 288         if (IS_VALLEYVIEW(dev))
 289                 return;
 290
 291         dev_priv->mchbar_need_disable = false;
 292
 293         if (IS_I915G(dev) || IS_I915GM(dev)) {
 294                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 295                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 296         } else {
 297                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 298                 enabled = temp & 1;
 299         }
 300
 301         /* If it's already enabled, don't have to do anything */
 302         if (enabled)
 303                 return;
 304
 305         if (intel_alloc_mchbar_resource(dev))
 306                 return;
 307
 308         dev_priv->mchbar_need_disable = true;
 309
 310         /* Space is allocated or reserved, so enable it. */
 311         if (IS_I915G(dev) || IS_I915GM(dev)) {
 312                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 313                                        temp | DEVEN_MCHBAR_EN);
 314         } else {
 315                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 316                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 317         }
 318 }
 319
 320 static void
 321 intel_teardown_mchbar(struct drm_device *dev)
 322 {
 323         struct drm_i915_private *dev_priv = dev->dev_private;
 324         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 325         u32 temp;
 326
 327         if (dev_priv->mchbar_need_disable) {
 328                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 329                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 330                         temp &= ~DEVEN_MCHBAR_EN;
 331                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 332                 } else {
 333                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 334                         temp &= ~1;
 335                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 336                 }
 337         }
 338
 339         if (dev_priv->mch_res.start)
 340                 release_resource(&dev_priv->mch_res);
 341 }
 342
 343 /* true = enable decode, false = disable decoder */
 344 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 345 {
 346         struct drm_device *dev = cookie;
 347
 348         intel_modeset_vga_set_state(dev, state);
 349         if (state)
 350                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 351                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 352         else
 353                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 354 }
 355
 356 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 357 {
 358         struct drm_device *dev = pci_get_drvdata(pdev);
 359         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 360
 361         if (state == VGA_SWITCHEROO_ON) {
 362                 pr_info("switched on\n");
 363                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 364                 /* i915 resume handler doesn't set to D0 */
 365                 pci_set_power_state(dev->pdev, PCI_D0);
 366                 i915_resume_switcheroo(dev);
 367                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 368         } else {
 369                 pr_info("switched off\n");
 370                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 371                 i915_suspend_switcheroo(dev, pmm);
 372                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 373         }
 374 }
 375
 376 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 377 {
 378         struct drm_device *dev = pci_get_drvdata(pdev);
 379
 380         /*
 381          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 382          * locking inversion with the driver load path. And the access here is
 383          * completely racy anyway. So don't bother with locking for now.
 384          */
 385         return dev->open_count == 0;
 386 }
 387
 388 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 389         .set_gpu_state = i915_switcheroo_set_state,
 390         .reprobe = NULL,
 391         .can_switch = i915_switcheroo_can_switch,
 392 };
 393
 394 static int i915_load_modeset_init(struct drm_device *dev)
 395 {
 396         struct drm_i915_private *dev_priv = dev->dev_private;
 397         int ret;
 398
 399         ret = intel_parse_bios(dev);
 400         if (ret)
 401                 DRM_INFO("failed to find VBIOS tables\n");
 402
 403         /* If we have > 1 VGA cards, then we need to arbitrate access
 404          * to the common VGA resources.
 405          *
 406          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 407          * then we do not take part in VGA arbitration and the
 408          * vga_client_register() fails with -ENODEV.
 409          */
 410         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 411         if (ret && ret != -ENODEV)
 412                 goto out;
 413
 414         intel_register_dsm_handler();
 415
 416         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 417         if (ret)
 418                 goto cleanup_vga_client;
 419
 420         /* Initialise stolen first so that we may reserve preallocated
 421          * objects for the BIOS to KMS transition.
 422          */
 423         ret = i915_gem_init_stolen(dev);
 424         if (ret)
 425                 goto cleanup_vga_switcheroo;
 426
 427         intel_power_domains_init_hw(dev_priv, false);
 428
 429         intel_csr_ucode_init(dev_priv);
 430
 431         ret = intel_irq_install(dev_priv);
 432         if (ret)
 433                 goto cleanup_gem_stolen;
 434
 435         /* Important: The output setup functions called by modeset_init need
 436          * working irqs for e.g. gmbus and dp aux transfers. */
 437         intel_modeset_init(dev);
 438
 439         /* intel_guc_ucode_init() needs the mutex to allocate GEM objects */
 440         mutex_lock(&dev->struct_mutex);
 441         intel_guc_ucode_init(dev);
 442         mutex_unlock(&dev->struct_mutex);
 443
 444         ret = i915_gem_init(dev);
 445         if (ret)
 446                 goto cleanup_irq;
 447
 448         intel_modeset_gem_init(dev);
 449
 450         /* Always safe in the mode setting case. */
 451         /* FIXME: do pre/post-mode set stuff in core KMS code */
 452         dev->vblank_disable_allowed = true;
 453         if (INTEL_INFO(dev)->num_pipes == 0)
 454                 return 0;
 455
 456         ret = intel_fbdev_init(dev);
 457         if (ret)
 458                 goto cleanup_gem;
 459
 460         /* Only enable hotplug handling once the fbdev is fully set up. */
 461         intel_hpd_init(dev_priv);
 462
 463         /*
 464          * Some ports require correctly set-up hpd registers for detection to
 465          * work properly (leading to ghost connected connector status), e.g. VGA
 466          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 467          * irqs are fully enabled. Now we should scan for the initial config
 468          * only once hotplug handling is enabled, but due to screwed-up locking
 469          * around kms/fbdev init we can't protect the fdbev initial config
 470          * scanning against hotplug events. Hence do this first and ignore the
 471          * tiny window where we will loose hotplug notifactions.
 472          */
 473         intel_fbdev_initial_config_async(dev);
 474
 475         drm_kms_helper_poll_init(dev);
 476
 477         return 0;
 478
 479 cleanup_gem:
 480         mutex_lock(&dev->struct_mutex);
 481         i915_gem_cleanup_ringbuffer(dev);
 482         i915_gem_context_fini(dev);
 483         mutex_unlock(&dev->struct_mutex);
 484 cleanup_irq:
 485         mutex_lock(&dev->struct_mutex);
 486         intel_guc_ucode_fini(dev);
 487         mutex_unlock(&dev->struct_mutex);
 488         drm_irq_uninstall(dev);
 489 cleanup_gem_stolen:
 490         i915_gem_cleanup_stolen(dev);
 491 cleanup_vga_switcheroo:
 492         vga_switcheroo_unregister_client(dev->pdev);
 493 cleanup_vga_client:
 494         vga_client_register(dev->pdev, NULL, NULL, NULL);
 495 out:
 496         return ret;
 497 }
 498
 499 #if IS_ENABLED(CONFIG_FB)
 500 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 501 {
 502         struct apertures_struct *ap;
 503         struct pci_dev *pdev = dev_priv->dev->pdev;
 504         bool primary;
 505         int ret;
 506
 507         ap = alloc_apertures(1);
 508         if (!ap)
 509                 return -ENOMEM;
 510
 511         ap->ranges[0].base = dev_priv->gtt.mappable_base;
 512         ap->ranges[0].size = dev_priv->gtt.mappable_end;
 513
 514         primary =
 515                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 516
 517         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 518
 519         kfree(ap);
 520
 521         return ret;
 522 }
 523 #else
 524 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 525 {
 526         return 0;
 527 }
 528 #endif
 529
 530 #if !defined(CONFIG_VGA_CONSOLE)
 531 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 532 {
 533         return 0;
 534 }
 535 #elif !defined(CONFIG_DUMMY_CONSOLE)
 536 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 537 {
 538         return -ENODEV;
 539 }
 540 #else
 541 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 542 {
 543         int ret = 0;
 544
 545         DRM_INFO("Replacing VGA console driver\n");
 546
 547         console_lock();
 548         if (con_is_bound(&vga_con))
 549                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 550         if (ret == 0) {
 551                 ret = do_unregister_con_driver(&vga_con);
 552
 553                 /* Ignore "already unregistered". */
 554                 if (ret == -ENODEV)
 555                         ret = 0;
 556         }
 557         console_unlock();
 558
 559         return ret;
 560 }
 561 #endif
 562
 563 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 564 {
 565         const struct intel_device_info *info = &dev_priv->info;
 566
 567 #define PRINT_S(name) "%s"
 568 #define SEP_EMPTY
 569 #define PRINT_FLAG(name) info->name ? #name "," : ""
 570 #define SEP_COMMA ,
 571         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
 572                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
 573                          info->gen,
 574                          dev_priv->dev->pdev->device,
 575                          dev_priv->dev->pdev->revision,
 576                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
 577 #undef PRINT_S
 578 #undef SEP_EMPTY
 579 #undef PRINT_FLAG
 580 #undef SEP_COMMA
 581 }
 582
 583 static void cherryview_sseu_info_init(struct drm_device *dev)
 584 {
 585         struct drm_i915_private *dev_priv = dev->dev_private;
 586         struct intel_device_info *info;
 587         u32 fuse, eu_dis;
 588
 589         info = (struct intel_device_info *)&dev_priv->info;
 590         fuse = I915_READ(CHV_FUSE_GT);
 591
 592         info->slice_total = 1;
 593
 594         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 595                 info->subslice_per_slice++;
 596                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 597                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
 598                 info->eu_total += 8 - hweight32(eu_dis);
 599         }
 600
 601         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
 602                 info->subslice_per_slice++;
 603                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
 604                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
 605                 info->eu_total += 8 - hweight32(eu_dis);
 606         }
 607
 608         info->subslice_total = info->subslice_per_slice;
 609         /*
 610          * CHV expected to always have a uniform distribution of EU
 611          * across subslices.
 612         */
 613         info->eu_per_subslice = info->subslice_total ?
 614                                 info->eu_total / info->subslice_total :
 615                                 0;
 616         /*
 617          * CHV supports subslice power gating on devices with more than
 618          * one subslice, and supports EU power gating on devices with
 619          * more than one EU pair per subslice.
 620         */
 621         info->has_slice_pg = 0;
 622         info->has_subslice_pg = (info->subslice_total > 1);
 623         info->has_eu_pg = (info->eu_per_subslice > 2);
 624 }
 625
 626 static void gen9_sseu_info_init(struct drm_device *dev)
 627 {
 628         struct drm_i915_private *dev_priv = dev->dev_private;
 629         struct intel_device_info *info;
 630         int s_max = 3, ss_max = 4, eu_max = 8;
 631         int s, ss;
 632         u32 fuse2, s_enable, ss_disable, eu_disable;
 633         u8 eu_mask = 0xff;
 634
 635         info = (struct intel_device_info *)&dev_priv->info;
 636         fuse2 = I915_READ(GEN8_FUSE2);
 637         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
 638                    GEN8_F2_S_ENA_SHIFT;
 639         ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
 640                      GEN9_F2_SS_DIS_SHIFT;
 641
 642         info->slice_total = hweight32(s_enable);
 643         /*
 644          * The subslice disable field is global, i.e. it applies
 645          * to each of the enabled slices.
 646         */
 647         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 648         info->subslice_total = info->slice_total *
 649                                info->subslice_per_slice;
 650
 651         /*
 652          * Iterate through enabled slices and subslices to
 653          * count the total enabled EU.
 654         */
 655         for (s = 0; s < s_max; s++) {
 656                 if (!(s_enable & (0x1 << s)))
 657                         /* skip disabled slice */
 658                         continue;
 659
 660                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
 661                 for (ss = 0; ss < ss_max; ss++) {
 662                         int eu_per_ss;
 663
 664                         if (ss_disable & (0x1 << ss))
 665                                 /* skip disabled subslice */
 666                                 continue;
 667
 668                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
 669                                                       eu_mask);
 670
 671                         /*
 672                          * Record which subslice(s) has(have) 7 EUs. we
 673                          * can tune the hash used to spread work among
 674                          * subslices if they are unbalanced.
 675                          */
 676                         if (eu_per_ss == 7)
 677                                 info->subslice_7eu[s] |= 1 << ss;
 678
 679                         info->eu_total += eu_per_ss;
 680                 }
 681         }
 682
 683         /*
 684          * SKL is expected to always have a uniform distribution
 685          * of EU across subslices with the exception that any one
 686          * EU in any one subslice may be fused off for die
 687          * recovery. BXT is expected to be perfectly uniform in EU
 688          * distribution.
 689         */
 690         info->eu_per_subslice = info->subslice_total ?
 691                                 DIV_ROUND_UP(info->eu_total,
 692                                              info->subslice_total) : 0;
 693         /*
 694          * SKL supports slice power gating on devices with more than
 695          * one slice, and supports EU power gating on devices with
 696          * more than one EU pair per subslice. BXT supports subslice
 697          * power gating on devices with more than one subslice, and
 698          * supports EU power gating on devices with more than one EU
 699          * pair per subslice.
 700         */
 701         info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
 702                                (info->slice_total > 1));
 703         info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
 704         info->has_eu_pg = (info->eu_per_subslice > 2);
 705 }
 706
 707 static void broadwell_sseu_info_init(struct drm_device *dev)
 708 {
 709         struct drm_i915_private *dev_priv = dev->dev_private;
 710         struct intel_device_info *info;
 711         const int s_max = 3, ss_max = 3, eu_max = 8;
 712         int s, ss;
 713         u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
 714
 715         fuse2 = I915_READ(GEN8_FUSE2);
 716         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 717         ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
 718
 719         eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
 720         eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
 721                         ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
 722                          (32 - GEN8_EU_DIS0_S1_SHIFT));
 723         eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
 724                         ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
 725                          (32 - GEN8_EU_DIS1_S2_SHIFT));
 726
 727
 728         info = (struct intel_device_info *)&dev_priv->info;
 729         info->slice_total = hweight32(s_enable);
 730
 731         /*
 732          * The subslice disable field is global, i.e. it applies
 733          * to each of the enabled slices.
 734          */
 735         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 736         info->subslice_total = info->slice_total * info->subslice_per_slice;
 737
 738         /*
 739          * Iterate through enabled slices and subslices to
 740          * count the total enabled EU.
 741          */
 742         for (s = 0; s < s_max; s++) {
 743                 if (!(s_enable & (0x1 << s)))
 744                         /* skip disabled slice */
 745                         continue;
 746
 747                 for (ss = 0; ss < ss_max; ss++) {
 748                         u32 n_disabled;
 749
 750                         if (ss_disable & (0x1 << ss))
 751                                 /* skip disabled subslice */
 752                                 continue;
 753
 754                         n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
 755
 756                         /*
 757                          * Record which subslices have 7 EUs.
 758                          */
 759                         if (eu_max - n_disabled == 7)
 760                                 info->subslice_7eu[s] |= 1 << ss;
 761
 762                         info->eu_total += eu_max - n_disabled;
 763                 }
 764         }
 765
 766         /*
 767          * BDW is expected to always have a uniform distribution of EU across
 768          * subslices with the exception that any one EU in any one subslice may
 769          * be fused off for die recovery.
 770          */
 771         info->eu_per_subslice = info->subslice_total ?
 772                 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
 773
 774         /*
 775          * BDW supports slice power gating on devices with more than
 776          * one slice.
 777          */
 778         info->has_slice_pg = (info->slice_total > 1);
 779         info->has_subslice_pg = 0;
 780         info->has_eu_pg = 0;
 781 }
 782
 783 /*
 784  * Determine various intel_device_info fields at runtime.
 785  *
 786  * Use it when either:
 787  *   - it's judged too laborious to fill n static structures with the limit
 788  *     when a simple if statement does the job,
 789  *   - run-time checks (eg read fuse/strap registers) are needed.
 790  *
 791  * This function needs to be called:
 792  *   - after the MMIO has been setup as we are reading registers,
 793  *   - after the PCH has been detected,
 794  *   - before the first usage of the fields it can tweak.
 795  */
 796 static void intel_device_info_runtime_init(struct drm_device *dev)
 797 {
 798         struct drm_i915_private *dev_priv = dev->dev_private;
 799         struct intel_device_info *info;
 800         enum pipe pipe;
 801
 802         info = (struct intel_device_info *)&dev_priv->info;
 803
 804         /*
 805          * Skylake and Broxton currently don't expose the topmost plane as its
 806          * use is exclusive with the legacy cursor and we only want to expose
 807          * one of those, not both. Until we can safely expose the topmost plane
 808          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 809          * we don't expose the topmost plane at all to prevent ABI breakage
 810          * down the line.
 811          */
 812         if (IS_BROXTON(dev)) {
 813                 info->num_sprites[PIPE_A] = 2;
 814                 info->num_sprites[PIPE_B] = 2;
 815                 info->num_sprites[PIPE_C] = 1;
 816         } else if (IS_VALLEYVIEW(dev))
 817                 for_each_pipe(dev_priv, pipe)
 818                         info->num_sprites[pipe] = 2;
 819         else
 820                 for_each_pipe(dev_priv, pipe)
 821                         info->num_sprites[pipe] = 1;
 822
 823         if (i915.disable_display) {
 824                 DRM_INFO("Display disabled (module parameter)\n");
 825                 info->num_pipes = 0;
 826         } else if (info->num_pipes > 0 &&
 827                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
 828                    !IS_VALLEYVIEW(dev)) {
 829                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 830                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 831
 832                 /*
 833                  * SFUSE_STRAP is supposed to have a bit signalling the display
 834                  * is fused off. Unfortunately it seems that, at least in
 835                  * certain cases, fused off display means that PCH display
 836                  * reads don't land anywhere. In that case, we read 0s.
 837                  *
 838                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 839                  * should be set when taking over after the firmware.
 840                  */
 841                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 842                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 843                     (dev_priv->pch_type == PCH_CPT &&
 844                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 845                         DRM_INFO("Display fused off, disabling\n");
 846                         info->num_pipes = 0;
 847                 }
 848         }
 849
 850         /* Initialize slice/subslice/EU info */
 851         if (IS_CHERRYVIEW(dev))
 852                 cherryview_sseu_info_init(dev);
 853         else if (IS_BROADWELL(dev))
 854                 broadwell_sseu_info_init(dev);
 855         else if (INTEL_INFO(dev)->gen >= 9)
 856                 gen9_sseu_info_init(dev);
 857
 858         DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
 859         DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
 860         DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
 861         DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
 862         DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
 863         DRM_DEBUG_DRIVER("has slice power gating: %s\n",
 864                          info->has_slice_pg ? "y" : "n");
 865         DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
 866                          info->has_subslice_pg ? "y" : "n");
 867         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
 868                          info->has_eu_pg ? "y" : "n");
 869 }
 870
 871 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 872 {
 873         if (!IS_VALLEYVIEW(dev_priv))
 874                 return;
 875
 876         /*
 877          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 878          * CHV x1 PHY (DP/HDMI D)
 879          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 880          */
 881         if (IS_CHERRYVIEW(dev_priv)) {
 882                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 883                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 884         } else {
 885                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 886         }
 887 }
 888
 889 /**
 890  * i915_driver_load - setup chip and create an initial config
 891  * @dev: DRM device
 892  * @flags: startup flags
 893  *
 894  * The driver load routine has to do several things:
 895  *   - drive output discovery via intel_modeset_init()
 896  *   - initialize the memory manager
 897  *   - allocate initial config memory
 898  *   - setup the DRM framebuffer with the allocated memory
 899  */
 900 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 901 {
 902         struct drm_i915_private *dev_priv;
 903         struct intel_device_info *info, *device_info;
 904         int ret = 0, mmio_bar, mmio_size;
 905         uint32_t aperture_size;
 906
 907         info = (struct intel_device_info *) flags;
 908
 909         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 910         if (dev_priv == NULL)
 911                 return -ENOMEM;
 912
 913         dev->dev_private = dev_priv;
 914         dev_priv->dev = dev;
 915
 916         /* Setup the write-once "constant" device info */
 917         device_info = (struct intel_device_info *)&dev_priv->info;
 918         memcpy(device_info, info, sizeof(dev_priv->info));
 919         device_info->device_id = dev->pdev->device;
 920
 921         spin_lock_init(&dev_priv->irq_lock);
 922         spin_lock_init(&dev_priv->gpu_error.lock);
 923         mutex_init(&dev_priv->backlight_lock);
 924         spin_lock_init(&dev_priv->uncore.lock);
 925         spin_lock_init(&dev_priv->mm.object_stat_lock);
 926         spin_lock_init(&dev_priv->mmio_flip_lock);
 927         mutex_init(&dev_priv->sb_lock);
 928         mutex_init(&dev_priv->modeset_restore_lock);
 929         mutex_init(&dev_priv->av_mutex);
 930
 931         intel_pm_setup(dev);
 932
 933         intel_display_crc_init(dev);
 934
 935         i915_dump_device_info(dev_priv);
 936
 937         /* Not all pre-production machines fall into this category, only the
 938          * very first ones. Almost everything should work, except for maybe
 939          * suspend/resume. And we don't implement workarounds that affect only
 940          * pre-production machines. */
 941         if (IS_HSW_EARLY_SDV(dev))
 942                 DRM_INFO("This is an early pre-production Haswell machine. "
 943                          "It may not be fully functional.\n");
 944
 945         if (i915_get_bridge_dev(dev)) {
 946                 ret = -EIO;
 947                 goto free_priv;
 948         }
 949
 950         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 951         /* Before gen4, the registers and the GTT are behind different BARs.
 952          * However, from gen4 onwards, the registers and the GTT are shared
 953          * in the same BAR, so we want to restrict this ioremap from
 954          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 955          * the register BAR remains the same size for all the earlier
 956          * generations up to Ironlake.
 957          */
 958         if (info->gen < 5)
 959                 mmio_size = 512*1024;
 960         else
 961                 mmio_size = 2*1024*1024;
 962
 963         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 964         if (!dev_priv->regs) {
 965                 DRM_ERROR("failed to map registers\n");
 966                 ret = -EIO;
 967                 goto put_bridge;
 968         }
 969
 970         /* This must be called before any calls to HAS_PCH_* */
 971         intel_detect_pch(dev);
 972
 973         intel_uncore_init(dev);
 974
 975         ret = i915_gem_gtt_init(dev);
 976         if (ret)
 977                 goto out_freecsr;
 978
 979         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
 980          * otherwise the vga fbdev driver falls over. */
 981         ret = i915_kick_out_firmware_fb(dev_priv);
 982         if (ret) {
 983                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
 984                 goto out_gtt;
 985         }
 986
 987         ret = i915_kick_out_vgacon(dev_priv);
 988         if (ret) {
 989                 DRM_ERROR("failed to remove conflicting VGA console\n");
 990                 goto out_gtt;
 991         }
 992
 993         pci_set_master(dev->pdev);
 994
 995         /* overlay on gen2 is broken and can't address above 1G */
 996         if (IS_GEN2(dev))
 997                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
 998
 999         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1000          * using 32bit addressing, overwriting memory if HWS is located
1001          * above 4GB.
1002          *
1003          * The documentation also mentions an issue with undefined
1004          * behaviour if any general state is accessed within a page above 4GB,
1005          * which also needs to be handled carefully.
1006          */
1007         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1008                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1009
1010         aperture_size = dev_priv->gtt.mappable_end;
1011
1012         dev_priv->gtt.mappable =
1013                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1014                                      aperture_size);
1015         if (dev_priv->gtt.mappable == NULL) {
1016                 ret = -EIO;
1017                 goto out_gtt;
1018         }
1019
1020         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1021                                               aperture_size);
1022
1023         /* The i915 workqueue is primarily used for batched retirement of
1024          * requests (and thus managing bo) once the task has been completed
1025          * by the GPU. i915_gem_retire_requests() is called directly when we
1026          * need high-priority retirement, such as waiting for an explicit
1027          * bo.
1028          *
1029          * It is also used for periodic low-priority events, such as
1030          * idle-timers and recording error state.
1031          *
1032          * All tasks on the workqueue are expected to acquire the dev mutex
1033          * so there is no point in running more than one instance of the
1034          * workqueue at any time.  Use an ordered one.
1035          */
1036         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1037         if (dev_priv->wq == NULL) {
1038                 DRM_ERROR("Failed to create our workqueue.\n");
1039                 ret = -ENOMEM;
1040                 goto out_mtrrfree;
1041         }
1042
1043         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1044         if (dev_priv->hotplug.dp_wq == NULL) {
1045                 DRM_ERROR("Failed to create our dp workqueue.\n");
1046                 ret = -ENOMEM;
1047                 goto out_freewq;
1048         }
1049
1050         dev_priv->gpu_error.hangcheck_wq =
1051                 alloc_ordered_workqueue("i915-hangcheck", 0);
1052         if (dev_priv->gpu_error.hangcheck_wq == NULL) {
1053                 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
1054                 ret = -ENOMEM;
1055                 goto out_freedpwq;
1056         }
1057
1058         intel_irq_init(dev_priv);
1059         intel_uncore_sanitize(dev);
1060
1061         /* Try to make sure MCHBAR is enabled before poking at it */
1062         intel_setup_mchbar(dev);
1063         intel_setup_gmbus(dev);
1064         intel_opregion_setup(dev);
1065
1066         i915_gem_load(dev);
1067
1068         /* On the 945G/GM, the chipset reports the MSI capability on the
1069          * integrated graphics even though the support isn't actually there
1070          * according to the published specs.  It doesn't appear to function
1071          * correctly in testing on 945G.
1072          * This may be a side effect of MSI having been made available for PEG
1073          * and the registers being closely associated.
1074          *
1075          * According to chipset errata, on the 965GM, MSI interrupts may
1076          * be lost or delayed, but we use them anyways to avoid
1077          * stuck interrupts on some machines.
1078          */
1079         if (!IS_I945G(dev) && !IS_I945GM(dev))
1080                 pci_enable_msi(dev->pdev);
1081
1082         intel_device_info_runtime_init(dev);
1083
1084         intel_init_dpio(dev_priv);
1085
1086         if (INTEL_INFO(dev)->num_pipes) {
1087                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1088                 if (ret)
1089                         goto out_gem_unload;
1090         }
1091
1092         intel_power_domains_init(dev_priv);
1093
1094         ret = i915_load_modeset_init(dev);
1095         if (ret < 0) {
1096                 DRM_ERROR("failed to init modeset\n");
1097                 goto out_power_well;
1098         }
1099
1100         /*
1101          * Notify a valid surface after modesetting,
1102          * when running inside a VM.
1103          */
1104         if (intel_vgpu_active(dev))
1105                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1106
1107         i915_setup_sysfs(dev);
1108
1109         if (INTEL_INFO(dev)->num_pipes) {
1110                 /* Must be done after probing outputs */
1111                 intel_opregion_init(dev);
1112                 acpi_video_register();
1113         }
1114
1115         if (IS_GEN5(dev))
1116                 intel_gpu_ips_init(dev_priv);
1117
1118         intel_runtime_pm_enable(dev_priv);
1119
1120         i915_audio_component_init(dev_priv);
1121
1122         return 0;
1123
1124 out_power_well:
1125         intel_power_domains_fini(dev_priv);
1126         drm_vblank_cleanup(dev);
1127 out_gem_unload:
1128         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1129         unregister_shrinker(&dev_priv->mm.shrinker);
1130
1131         if (dev->pdev->msi_enabled)
1132                 pci_disable_msi(dev->pdev);
1133
1134         intel_teardown_gmbus(dev);
1135         intel_teardown_mchbar(dev);
1136         pm_qos_remove_request(&dev_priv->pm_qos);
1137         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1138 out_freedpwq:
1139         destroy_workqueue(dev_priv->hotplug.dp_wq);
1140 out_freewq:
1141         destroy_workqueue(dev_priv->wq);
1142 out_mtrrfree:
1143         arch_phys_wc_del(dev_priv->gtt.mtrr);
1144         io_mapping_free(dev_priv->gtt.mappable);
1145 out_gtt:
1146         i915_global_gtt_cleanup(dev);
1147 out_freecsr:
1148         intel_csr_ucode_fini(dev_priv);
1149         intel_uncore_fini(dev);
1150         pci_iounmap(dev->pdev, dev_priv->regs);
1151 put_bridge:
1152         pci_dev_put(dev_priv->bridge_dev);
1153 free_priv:
1154         kmem_cache_destroy(dev_priv->requests);
1155         kmem_cache_destroy(dev_priv->vmas);
1156         kmem_cache_destroy(dev_priv->objects);
1157         kfree(dev_priv);
1158         return ret;
1159 }
1160
1161 int i915_driver_unload(struct drm_device *dev)
1162 {
1163         struct drm_i915_private *dev_priv = dev->dev_private;
1164         int ret;
1165
1166         intel_fbdev_fini(dev);
1167
1168         i915_audio_component_cleanup(dev_priv);
1169
1170         ret = i915_gem_suspend(dev);
1171         if (ret) {
1172                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1173                 return ret;
1174         }
1175
1176         intel_power_domains_fini(dev_priv);
1177
1178         intel_gpu_ips_teardown();
1179
1180         i915_teardown_sysfs(dev);
1181
1182         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1183         unregister_shrinker(&dev_priv->mm.shrinker);
1184
1185         io_mapping_free(dev_priv->gtt.mappable);
1186         arch_phys_wc_del(dev_priv->gtt.mtrr);
1187
1188         acpi_video_unregister();
1189
1190         drm_vblank_cleanup(dev);
1191
1192         intel_modeset_cleanup(dev);
1193
1194         /*
1195          * free the memory space allocated for the child device
1196          * config parsed from VBT
1197          */
1198         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1199                 kfree(dev_priv->vbt.child_dev);
1200                 dev_priv->vbt.child_dev = NULL;
1201                 dev_priv->vbt.child_dev_num = 0;
1202         }
1203         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1204         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1205         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1206         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1207
1208         vga_switcheroo_unregister_client(dev->pdev);
1209         vga_client_register(dev->pdev, NULL, NULL, NULL);
1210
1211         /* Free error state after interrupts are fully disabled. */
1212         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1213         i915_destroy_error_state(dev);
1214
1215         if (dev->pdev->msi_enabled)
1216                 pci_disable_msi(dev->pdev);
1217
1218         intel_opregion_fini(dev);
1219
1220         /* Flush any outstanding unpin_work. */
1221         flush_workqueue(dev_priv->wq);
1222
1223         mutex_lock(&dev->struct_mutex);
1224         intel_guc_ucode_fini(dev);
1225         i915_gem_cleanup_ringbuffer(dev);
1226         i915_gem_context_fini(dev);
1227         mutex_unlock(&dev->struct_mutex);
1228         intel_fbc_cleanup_cfb(dev_priv);
1229         i915_gem_cleanup_stolen(dev);
1230
1231         intel_csr_ucode_fini(dev_priv);
1232
1233         intel_teardown_gmbus(dev);
1234         intel_teardown_mchbar(dev);
1235
1236         destroy_workqueue(dev_priv->hotplug.dp_wq);
1237         destroy_workqueue(dev_priv->wq);
1238         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1239         pm_qos_remove_request(&dev_priv->pm_qos);
1240
1241         i915_global_gtt_cleanup(dev);
1242
1243         intel_uncore_fini(dev);
1244         if (dev_priv->regs != NULL)
1245                 pci_iounmap(dev->pdev, dev_priv->regs);
1246
1247         kmem_cache_destroy(dev_priv->requests);
1248         kmem_cache_destroy(dev_priv->vmas);
1249         kmem_cache_destroy(dev_priv->objects);
1250         pci_dev_put(dev_priv->bridge_dev);
1251         kfree(dev_priv);
1252
1253         return 0;
1254 }
1255
1256 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1257 {
1258         int ret;
1259
1260         ret = i915_gem_open(dev, file);
1261         if (ret)
1262                 return ret;
1263
1264         return 0;
1265 }
1266
1267 /**
1268  * i915_driver_lastclose - clean up after all DRM clients have exited
1269  * @dev: DRM device
1270  *
1271  * Take care of cleaning up after all DRM clients have exited.  In the
1272  * mode setting case, we want to restore the kernel's initial mode (just
1273  * in case the last client left us in a bad state).
1274  *
1275  * Additionally, in the non-mode setting case, we'll tear down the GTT
1276  * and DMA structures, since the kernel won't be using them, and clea
1277  * up any GEM state.
1278  */
1279 void i915_driver_lastclose(struct drm_device *dev)
1280 {
1281         intel_fbdev_restore_mode(dev);
1282         vga_switcheroo_process_delayed_switch();
1283 }
1284
1285 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1286 {
1287         mutex_lock(&dev->struct_mutex);
1288         i915_gem_context_close(dev, file);
1289         i915_gem_release(dev, file);
1290         mutex_unlock(&dev->struct_mutex);
1291
1292         intel_modeset_preclose(dev, file);
1293 }
1294
1295 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1296 {
1297         struct drm_i915_file_private *file_priv = file->driver_priv;
1298
1299         kfree(file_priv);
1300 }
1301
1302 static int
1303 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1304                           struct drm_file *file)
1305 {
1306         return -ENODEV;
1307 }
1308
1309 const struct drm_ioctl_desc i915_ioctls[] = {
1310         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1311         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1312         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1313         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1314         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1315         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1316         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1317         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1318         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1319         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1320         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1321         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1322         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1323         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1324         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1325         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1326         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1327         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1328         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1329         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1330         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1331         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1332         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1333         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1334         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1335         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1336         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1337         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1338         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1339         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1340         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1341         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1342         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1343         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1344         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1345         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1346         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1347         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1348         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1349         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1350         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1351         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1352         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1353         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1354         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1355         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1356         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1357         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1358         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1359         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1360         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1361         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1362 };
1363
1364 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);