drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include <linux/pci.h>
  38 #include <linux/vgaarb.h>
  39 #include <linux/acpi.h>
  40 #include <linux/pnp.h>
  41 #include <linux/vga_switcheroo.h>
  42 #include <linux/slab.h>
  43 #include <acpi/video.h>
  44
  45 /**
  46  * Sets up the hardware status page for devices that need a physical address
  47  * in the register.
  48  */
  49 static int i915_init_phys_hws(struct drm_device *dev)
  50 {
  51         drm_i915_private_t *dev_priv = dev->dev_private;
  52         /* Program Hardware Status Page */
  53         dev_priv->status_page_dmah =
  54                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  55
  56         if (!dev_priv->status_page_dmah) {
  57                 DRM_ERROR("Can not allocate hardware status page\n");
  58                 return -ENOMEM;
  59         }
  60         dev_priv->render_ring.status_page.page_addr
  61                 = dev_priv->status_page_dmah->vaddr;
  62         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  63
  64         memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
  65
  66         if (INTEL_INFO(dev)->gen >= 4)
  67                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
  68                                              0xf0;
  69
  70         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  71         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  72         return 0;
  73 }
  74
  75 /**
  76  * Frees the hardware status page, whether it's a physical address or a virtual
  77  * address set up by the X Server.
  78  */
  79 static void i915_free_hws(struct drm_device *dev)
  80 {
  81         drm_i915_private_t *dev_priv = dev->dev_private;
  82         if (dev_priv->status_page_dmah) {
  83                 drm_pci_free(dev, dev_priv->status_page_dmah);
  84                 dev_priv->status_page_dmah = NULL;
  85         }
  86
  87         if (dev_priv->render_ring.status_page.gfx_addr) {
  88                 dev_priv->render_ring.status_page.gfx_addr = 0;
  89                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
  90         }
  91
  92         /* Need to rewrite hardware status page */
  93         I915_WRITE(HWS_PGA, 0x1ffff000);
  94 }
  95
  96 void i915_kernel_lost_context(struct drm_device * dev)
  97 {
  98         drm_i915_private_t *dev_priv = dev->dev_private;
  99         struct drm_i915_master_private *master_priv;
 100         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 101
 102         /*
 103          * We should never lose context on the ring with modesetting
 104          * as we don't expose it to userspace
 105          */
 106         if (drm_core_check_feature(dev, DRIVER_MODESET))
 107                 return;
 108
 109         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 110         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 111         ring->space = ring->head - (ring->tail + 8);
 112         if (ring->space < 0)
 113                 ring->space += ring->size;
 114
 115         if (!dev->primary->master)
 116                 return;
 117
 118         master_priv = dev->primary->master->driver_priv;
 119         if (ring->head == ring->tail && master_priv->sarea_priv)
 120                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 121 }
 122
 123 static int i915_dma_cleanup(struct drm_device * dev)
 124 {
 125         drm_i915_private_t *dev_priv = dev->dev_private;
 126         /* Make sure interrupts are disabled here because the uninstall ioctl
 127          * may not have been called from userspace and after dev_private
 128          * is freed, it's too late.
 129          */
 130         if (dev->irq_enabled)
 131                 drm_irq_uninstall(dev);
 132
 133         mutex_lock(&dev->struct_mutex);
 134         intel_cleanup_ring_buffer(&dev_priv->render_ring);
 135         intel_cleanup_ring_buffer(&dev_priv->bsd_ring);
 136         intel_cleanup_ring_buffer(&dev_priv->blt_ring);
 137         mutex_unlock(&dev->struct_mutex);
 138
 139         /* Clear the HWS virtual address at teardown */
 140         if (I915_NEED_GFX_HWS(dev))
 141                 i915_free_hws(dev);
 142
 143         return 0;
 144 }
 145
 146 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 147 {
 148         drm_i915_private_t *dev_priv = dev->dev_private;
 149         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 150
 151         master_priv->sarea = drm_getsarea(dev);
 152         if (master_priv->sarea) {
 153                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 154                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 155         } else {
 156                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 157         }
 158
 159         if (init->ring_size != 0) {
 160                 if (dev_priv->render_ring.obj != NULL) {
 161                         i915_dma_cleanup(dev);
 162                         DRM_ERROR("Client tried to initialize ringbuffer in "
 163                                   "GEM mode\n");
 164                         return -EINVAL;
 165                 }
 166
 167                 dev_priv->render_ring.size = init->ring_size;
 168
 169                 dev_priv->render_ring.map.offset = init->ring_start;
 170                 dev_priv->render_ring.map.size = init->ring_size;
 171                 dev_priv->render_ring.map.type = 0;
 172                 dev_priv->render_ring.map.flags = 0;
 173                 dev_priv->render_ring.map.mtrr = 0;
 174
 175                 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
 176
 177                 if (dev_priv->render_ring.map.handle == NULL) {
 178                         i915_dma_cleanup(dev);
 179                         DRM_ERROR("can not ioremap virtual address for"
 180                                   " ring buffer\n");
 181                         return -ENOMEM;
 182                 }
 183         }
 184
 185         dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
 186
 187         dev_priv->cpp = init->cpp;
 188         dev_priv->back_offset = init->back_offset;
 189         dev_priv->front_offset = init->front_offset;
 190         dev_priv->current_page = 0;
 191         if (master_priv->sarea_priv)
 192                 master_priv->sarea_priv->pf_current_page = 0;
 193
 194         /* Allow hardware batchbuffers unless told otherwise.
 195          */
 196         dev_priv->allow_batchbuffer = 1;
 197
 198         return 0;
 199 }
 200
 201 static int i915_dma_resume(struct drm_device * dev)
 202 {
 203         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 204
 205         struct intel_ring_buffer *ring;
 206         DRM_DEBUG_DRIVER("%s\n", __func__);
 207
 208         ring = &dev_priv->render_ring;
 209
 210         if (ring->map.handle == NULL) {
 211                 DRM_ERROR("can not ioremap virtual address for"
 212                           " ring buffer\n");
 213                 return -ENOMEM;
 214         }
 215
 216         /* Program Hardware Status Page */
 217         if (!ring->status_page.page_addr) {
 218                 DRM_ERROR("Can not find hardware status page\n");
 219                 return -EINVAL;
 220         }
 221         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 222                                 ring->status_page.page_addr);
 223         if (ring->status_page.gfx_addr != 0)
 224                 intel_ring_setup_status_page(ring);
 225         else
 226                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 227
 228         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 229
 230         return 0;
 231 }
 232
 233 static int i915_dma_init(struct drm_device *dev, void *data,
 234                          struct drm_file *file_priv)
 235 {
 236         drm_i915_init_t *init = data;
 237         int retcode = 0;
 238
 239         switch (init->func) {
 240         case I915_INIT_DMA:
 241                 retcode = i915_initialize(dev, init);
 242                 break;
 243         case I915_CLEANUP_DMA:
 244                 retcode = i915_dma_cleanup(dev);
 245                 break;
 246         case I915_RESUME_DMA:
 247                 retcode = i915_dma_resume(dev);
 248                 break;
 249         default:
 250                 retcode = -EINVAL;
 251                 break;
 252         }
 253
 254         return retcode;
 255 }
 256
 257 /* Implement basically the same security restrictions as hardware does
 258  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 259  *
 260  * Most of the calculations below involve calculating the size of a
 261  * particular instruction.  It's important to get the size right as
 262  * that tells us where the next instruction to check is.  Any illegal
 263  * instruction detected will be given a size of zero, which is a
 264  * signal to abort the rest of the buffer.
 265  */
 266 static int validate_cmd(int cmd)
 267 {
 268         switch (((cmd >> 29) & 0x7)) {
 269         case 0x0:
 270                 switch ((cmd >> 23) & 0x3f) {
 271                 case 0x0:
 272                         return 1;       /* MI_NOOP */
 273                 case 0x4:
 274                         return 1;       /* MI_FLUSH */
 275                 default:
 276                         return 0;       /* disallow everything else */
 277                 }
 278                 break;
 279         case 0x1:
 280                 return 0;       /* reserved */
 281         case 0x2:
 282                 return (cmd & 0xff) + 2;        /* 2d commands */
 283         case 0x3:
 284                 if (((cmd >> 24) & 0x1f) <= 0x18)
 285                         return 1;
 286
 287                 switch ((cmd >> 24) & 0x1f) {
 288                 case 0x1c:
 289                         return 1;
 290                 case 0x1d:
 291                         switch ((cmd >> 16) & 0xff) {
 292                         case 0x3:
 293                                 return (cmd & 0x1f) + 2;
 294                         case 0x4:
 295                                 return (cmd & 0xf) + 2;
 296                         default:
 297                                 return (cmd & 0xffff) + 2;
 298                         }
 299                 case 0x1e:
 300                         if (cmd & (1 << 23))
 301                                 return (cmd & 0xffff) + 1;
 302                         else
 303                                 return 1;
 304                 case 0x1f:
 305                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 306                                 return (cmd & 0x1ffff) + 2;
 307                         else if (cmd & (1 << 17))       /* indirect random */
 308                                 if ((cmd & 0xffff) == 0)
 309                                         return 0;       /* unknown length, too hard */
 310                                 else
 311                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 312                         else
 313                                 return 2;       /* indirect sequential */
 314                 default:
 315                         return 0;
 316                 }
 317         default:
 318                 return 0;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 325 {
 326         drm_i915_private_t *dev_priv = dev->dev_private;
 327         int i, ret;
 328
 329         if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
 330                 return -EINVAL;
 331
 332         for (i = 0; i < dwords;) {
 333                 int sz = validate_cmd(buffer[i]);
 334                 if (sz == 0 || i + sz > dwords)
 335                         return -EINVAL;
 336                 i += sz;
 337         }
 338
 339         ret = BEGIN_LP_RING((dwords+1)&~1);
 340         if (ret)
 341                 return ret;
 342
 343         for (i = 0; i < dwords; i++)
 344                 OUT_RING(buffer[i]);
 345         if (dwords & 1)
 346                 OUT_RING(0);
 347
 348         ADVANCE_LP_RING();
 349
 350         return 0;
 351 }
 352
 353 int
 354 i915_emit_box(struct drm_device *dev,
 355               struct drm_clip_rect *box,
 356               int DR1, int DR4)
 357 {
 358         struct drm_i915_private *dev_priv = dev->dev_private;
 359         int ret;
 360
 361         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 362             box->y2 <= 0 || box->x2 <= 0) {
 363                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 364                           box->x1, box->y1, box->x2, box->y2);
 365                 return -EINVAL;
 366         }
 367
 368         if (INTEL_INFO(dev)->gen >= 4) {
 369                 ret = BEGIN_LP_RING(4);
 370                 if (ret)
 371                         return ret;
 372
 373                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 374                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 375                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 376                 OUT_RING(DR4);
 377         } else {
 378                 ret = BEGIN_LP_RING(6);
 379                 if (ret)
 380                         return ret;
 381
 382                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 383                 OUT_RING(DR1);
 384                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 385                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 386                 OUT_RING(DR4);
 387                 OUT_RING(0);
 388         }
 389         ADVANCE_LP_RING();
 390
 391         return 0;
 392 }
 393
 394 /* XXX: Emitting the counter should really be moved to part of the IRQ
 395  * emit. For now, do it in both places:
 396  */
 397
 398 static void i915_emit_breadcrumb(struct drm_device *dev)
 399 {
 400         drm_i915_private_t *dev_priv = dev->dev_private;
 401         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 402
 403         dev_priv->counter++;
 404         if (dev_priv->counter > 0x7FFFFFFFUL)
 405                 dev_priv->counter = 0;
 406         if (master_priv->sarea_priv)
 407                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 408
 409         if (BEGIN_LP_RING(4) == 0) {
 410                 OUT_RING(MI_STORE_DWORD_INDEX);
 411                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 412                 OUT_RING(dev_priv->counter);
 413                 OUT_RING(0);
 414                 ADVANCE_LP_RING();
 415         }
 416 }
 417
 418 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 419                                    drm_i915_cmdbuffer_t *cmd,
 420                                    struct drm_clip_rect *cliprects,
 421                                    void *cmdbuf)
 422 {
 423         int nbox = cmd->num_cliprects;
 424         int i = 0, count, ret;
 425
 426         if (cmd->sz & 0x3) {
 427                 DRM_ERROR("alignment");
 428                 return -EINVAL;
 429         }
 430
 431         i915_kernel_lost_context(dev);
 432
 433         count = nbox ? nbox : 1;
 434
 435         for (i = 0; i < count; i++) {
 436                 if (i < nbox) {
 437                         ret = i915_emit_box(dev, &cliprects[i],
 438                                             cmd->DR1, cmd->DR4);
 439                         if (ret)
 440                                 return ret;
 441                 }
 442
 443                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 444                 if (ret)
 445                         return ret;
 446         }
 447
 448         i915_emit_breadcrumb(dev);
 449         return 0;
 450 }
 451
 452 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 453                                      drm_i915_batchbuffer_t * batch,
 454                                      struct drm_clip_rect *cliprects)
 455 {
 456         struct drm_i915_private *dev_priv = dev->dev_private;
 457         int nbox = batch->num_cliprects;
 458         int i, count, ret;
 459
 460         if ((batch->start | batch->used) & 0x7) {
 461                 DRM_ERROR("alignment");
 462                 return -EINVAL;
 463         }
 464
 465         i915_kernel_lost_context(dev);
 466
 467         count = nbox ? nbox : 1;
 468         for (i = 0; i < count; i++) {
 469                 if (i < nbox) {
 470                         ret = i915_emit_box(dev, &cliprects[i],
 471                                             batch->DR1, batch->DR4);
 472                         if (ret)
 473                                 return ret;
 474                 }
 475
 476                 if (!IS_I830(dev) && !IS_845G(dev)) {
 477                         ret = BEGIN_LP_RING(2);
 478                         if (ret)
 479                                 return ret;
 480
 481                         if (INTEL_INFO(dev)->gen >= 4) {
 482                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 483                                 OUT_RING(batch->start);
 484                         } else {
 485                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 486                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 487                         }
 488                 } else {
 489                         ret = BEGIN_LP_RING(4);
 490                         if (ret)
 491                                 return ret;
 492
 493                         OUT_RING(MI_BATCH_BUFFER);
 494                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 495                         OUT_RING(batch->start + batch->used - 4);
 496                         OUT_RING(0);
 497                 }
 498                 ADVANCE_LP_RING();
 499         }
 500
 501
 502         if (IS_G4X(dev) || IS_GEN5(dev)) {
 503                 if (BEGIN_LP_RING(2) == 0) {
 504                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 505                         OUT_RING(MI_NOOP);
 506                         ADVANCE_LP_RING();
 507                 }
 508         }
 509
 510         i915_emit_breadcrumb(dev);
 511         return 0;
 512 }
 513
 514 static int i915_dispatch_flip(struct drm_device * dev)
 515 {
 516         drm_i915_private_t *dev_priv = dev->dev_private;
 517         struct drm_i915_master_private *master_priv =
 518                 dev->primary->master->driver_priv;
 519         int ret;
 520
 521         if (!master_priv->sarea_priv)
 522                 return -EINVAL;
 523
 524         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 525                           __func__,
 526                          dev_priv->current_page,
 527                          master_priv->sarea_priv->pf_current_page);
 528
 529         i915_kernel_lost_context(dev);
 530
 531         ret = BEGIN_LP_RING(10);
 532         if (ret)
 533                 return ret;
 534
 535         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 536         OUT_RING(0);
 537
 538         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 539         OUT_RING(0);
 540         if (dev_priv->current_page == 0) {
 541                 OUT_RING(dev_priv->back_offset);
 542                 dev_priv->current_page = 1;
 543         } else {
 544                 OUT_RING(dev_priv->front_offset);
 545                 dev_priv->current_page = 0;
 546         }
 547         OUT_RING(0);
 548
 549         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 550         OUT_RING(0);
 551
 552         ADVANCE_LP_RING();
 553
 554         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 555
 556         if (BEGIN_LP_RING(4) == 0) {
 557                 OUT_RING(MI_STORE_DWORD_INDEX);
 558                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 559                 OUT_RING(dev_priv->counter);
 560                 OUT_RING(0);
 561                 ADVANCE_LP_RING();
 562         }
 563
 564         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 565         return 0;
 566 }
 567
 568 static int i915_quiescent(struct drm_device * dev)
 569 {
 570         drm_i915_private_t *dev_priv = dev->dev_private;
 571
 572         i915_kernel_lost_context(dev);
 573         return intel_wait_ring_buffer(&dev_priv->render_ring,
 574                                       dev_priv->render_ring.size - 8);
 575 }
 576
 577 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 578                             struct drm_file *file_priv)
 579 {
 580         int ret;
 581
 582         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 583
 584         mutex_lock(&dev->struct_mutex);
 585         ret = i915_quiescent(dev);
 586         mutex_unlock(&dev->struct_mutex);
 587
 588         return ret;
 589 }
 590
 591 static int i915_batchbuffer(struct drm_device *dev, void *data,
 592                             struct drm_file *file_priv)
 593 {
 594         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 595         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 596         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 597             master_priv->sarea_priv;
 598         drm_i915_batchbuffer_t *batch = data;
 599         int ret;
 600         struct drm_clip_rect *cliprects = NULL;
 601
 602         if (!dev_priv->allow_batchbuffer) {
 603                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 604                 return -EINVAL;
 605         }
 606
 607         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 608                         batch->start, batch->used, batch->num_cliprects);
 609
 610         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 611
 612         if (batch->num_cliprects < 0)
 613                 return -EINVAL;
 614
 615         if (batch->num_cliprects) {
 616                 cliprects = kcalloc(batch->num_cliprects,
 617                                     sizeof(struct drm_clip_rect),
 618                                     GFP_KERNEL);
 619                 if (cliprects == NULL)
 620                         return -ENOMEM;
 621
 622                 ret = copy_from_user(cliprects, batch->cliprects,
 623                                      batch->num_cliprects *
 624                                      sizeof(struct drm_clip_rect));
 625                 if (ret != 0) {
 626                         ret = -EFAULT;
 627                         goto fail_free;
 628                 }
 629         }
 630
 631         mutex_lock(&dev->struct_mutex);
 632         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 633         mutex_unlock(&dev->struct_mutex);
 634
 635         if (sarea_priv)
 636                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 637
 638 fail_free:
 639         kfree(cliprects);
 640
 641         return ret;
 642 }
 643
 644 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 645                           struct drm_file *file_priv)
 646 {
 647         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 648         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 649         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 650             master_priv->sarea_priv;
 651         drm_i915_cmdbuffer_t *cmdbuf = data;
 652         struct drm_clip_rect *cliprects = NULL;
 653         void *batch_data;
 654         int ret;
 655
 656         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 657                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 658
 659         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 660
 661         if (cmdbuf->num_cliprects < 0)
 662                 return -EINVAL;
 663
 664         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 665         if (batch_data == NULL)
 666                 return -ENOMEM;
 667
 668         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 669         if (ret != 0) {
 670                 ret = -EFAULT;
 671                 goto fail_batch_free;
 672         }
 673
 674         if (cmdbuf->num_cliprects) {
 675                 cliprects = kcalloc(cmdbuf->num_cliprects,
 676                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 677                 if (cliprects == NULL) {
 678                         ret = -ENOMEM;
 679                         goto fail_batch_free;
 680                 }
 681
 682                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 683                                      cmdbuf->num_cliprects *
 684                                      sizeof(struct drm_clip_rect));
 685                 if (ret != 0) {
 686                         ret = -EFAULT;
 687                         goto fail_clip_free;
 688                 }
 689         }
 690
 691         mutex_lock(&dev->struct_mutex);
 692         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 693         mutex_unlock(&dev->struct_mutex);
 694         if (ret) {
 695                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 696                 goto fail_clip_free;
 697         }
 698
 699         if (sarea_priv)
 700                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 701
 702 fail_clip_free:
 703         kfree(cliprects);
 704 fail_batch_free:
 705         kfree(batch_data);
 706
 707         return ret;
 708 }
 709
 710 static int i915_flip_bufs(struct drm_device *dev, void *data,
 711                           struct drm_file *file_priv)
 712 {
 713         int ret;
 714
 715         DRM_DEBUG_DRIVER("%s\n", __func__);
 716
 717         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 718
 719         mutex_lock(&dev->struct_mutex);
 720         ret = i915_dispatch_flip(dev);
 721         mutex_unlock(&dev->struct_mutex);
 722
 723         return ret;
 724 }
 725
 726 static int i915_getparam(struct drm_device *dev, void *data,
 727                          struct drm_file *file_priv)
 728 {
 729         drm_i915_private_t *dev_priv = dev->dev_private;
 730         drm_i915_getparam_t *param = data;
 731         int value;
 732
 733         if (!dev_priv) {
 734                 DRM_ERROR("called with no initialization\n");
 735                 return -EINVAL;
 736         }
 737
 738         switch (param->param) {
 739         case I915_PARAM_IRQ_ACTIVE:
 740                 value = dev->pdev->irq ? 1 : 0;
 741                 break;
 742         case I915_PARAM_ALLOW_BATCHBUFFER:
 743                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 744                 break;
 745         case I915_PARAM_LAST_DISPATCH:
 746                 value = READ_BREADCRUMB(dev_priv);
 747                 break;
 748         case I915_PARAM_CHIPSET_ID:
 749                 value = dev->pci_device;
 750                 break;
 751         case I915_PARAM_HAS_GEM:
 752                 value = dev_priv->has_gem;
 753                 break;
 754         case I915_PARAM_NUM_FENCES_AVAIL:
 755                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 756                 break;
 757         case I915_PARAM_HAS_OVERLAY:
 758                 value = dev_priv->overlay ? 1 : 0;
 759                 break;
 760         case I915_PARAM_HAS_PAGEFLIPPING:
 761                 value = 1;
 762                 break;
 763         case I915_PARAM_HAS_EXECBUF2:
 764                 /* depends on GEM */
 765                 value = dev_priv->has_gem;
 766                 break;
 767         case I915_PARAM_HAS_BSD:
 768                 value = HAS_BSD(dev);
 769                 break;
 770         case I915_PARAM_HAS_BLT:
 771                 value = HAS_BLT(dev);
 772                 break;
 773         case I915_PARAM_HAS_RELAXED_FENCING:
 774                 value = 1;
 775                 break;
 776         default:
 777                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 778                                  param->param);
 779                 return -EINVAL;
 780         }
 781
 782         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 783                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 784                 return -EFAULT;
 785         }
 786
 787         return 0;
 788 }
 789
 790 static int i915_setparam(struct drm_device *dev, void *data,
 791                          struct drm_file *file_priv)
 792 {
 793         drm_i915_private_t *dev_priv = dev->dev_private;
 794         drm_i915_setparam_t *param = data;
 795
 796         if (!dev_priv) {
 797                 DRM_ERROR("called with no initialization\n");
 798                 return -EINVAL;
 799         }
 800
 801         switch (param->param) {
 802         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 803                 break;
 804         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 805                 dev_priv->tex_lru_log_granularity = param->value;
 806                 break;
 807         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 808                 dev_priv->allow_batchbuffer = param->value;
 809                 break;
 810         case I915_SETPARAM_NUM_USED_FENCES:
 811                 if (param->value > dev_priv->num_fence_regs ||
 812                     param->value < 0)
 813                         return -EINVAL;
 814                 /* Userspace can use first N regs */
 815                 dev_priv->fence_reg_start = param->value;
 816                 break;
 817         default:
 818                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 819                                         param->param);
 820                 return -EINVAL;
 821         }
 822
 823         return 0;
 824 }
 825
 826 static int i915_set_status_page(struct drm_device *dev, void *data,
 827                                 struct drm_file *file_priv)
 828 {
 829         drm_i915_private_t *dev_priv = dev->dev_private;
 830         drm_i915_hws_addr_t *hws = data;
 831         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 832
 833         if (!I915_NEED_GFX_HWS(dev))
 834                 return -EINVAL;
 835
 836         if (!dev_priv) {
 837                 DRM_ERROR("called with no initialization\n");
 838                 return -EINVAL;
 839         }
 840
 841         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 842                 WARN(1, "tried to set status page when mode setting active\n");
 843                 return 0;
 844         }
 845
 846         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 847
 848         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 849
 850         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 851         dev_priv->hws_map.size = 4*1024;
 852         dev_priv->hws_map.type = 0;
 853         dev_priv->hws_map.flags = 0;
 854         dev_priv->hws_map.mtrr = 0;
 855
 856         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 857         if (dev_priv->hws_map.handle == NULL) {
 858                 i915_dma_cleanup(dev);
 859                 ring->status_page.gfx_addr = 0;
 860                 DRM_ERROR("can not ioremap virtual address for"
 861                                 " G33 hw status page\n");
 862                 return -ENOMEM;
 863         }
 864         ring->status_page.page_addr = dev_priv->hws_map.handle;
 865         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 866         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 867
 868         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 869                          ring->status_page.gfx_addr);
 870         DRM_DEBUG_DRIVER("load hws at %p\n",
 871                          ring->status_page.page_addr);
 872         return 0;
 873 }
 874
 875 static int i915_get_bridge_dev(struct drm_device *dev)
 876 {
 877         struct drm_i915_private *dev_priv = dev->dev_private;
 878
 879         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
 880         if (!dev_priv->bridge_dev) {
 881                 DRM_ERROR("bridge device not found\n");
 882                 return -1;
 883         }
 884         return 0;
 885 }
 886
 887 #define MCHBAR_I915 0x44
 888 #define MCHBAR_I965 0x48
 889 #define MCHBAR_SIZE (4*4096)
 890
 891 #define DEVEN_REG 0x54
 892 #define   DEVEN_MCHBAR_EN (1 << 28)
 893
 894 /* Allocate space for the MCH regs if needed, return nonzero on error */
 895 static int
 896 intel_alloc_mchbar_resource(struct drm_device *dev)
 897 {
 898         drm_i915_private_t *dev_priv = dev->dev_private;
 899         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 900         u32 temp_lo, temp_hi = 0;
 901         u64 mchbar_addr;
 902         int ret;
 903
 904         if (INTEL_INFO(dev)->gen >= 4)
 905                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 906         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 907         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 908
 909         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 910 #ifdef CONFIG_PNP
 911         if (mchbar_addr &&
 912             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 913                 return 0;
 914 #endif
 915
 916         /* Get some space for it */
 917         dev_priv->mch_res.name = "i915 MCHBAR";
 918         dev_priv->mch_res.flags = IORESOURCE_MEM;
 919         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 920                                      &dev_priv->mch_res,
 921                                      MCHBAR_SIZE, MCHBAR_SIZE,
 922                                      PCIBIOS_MIN_MEM,
 923                                      0, pcibios_align_resource,
 924                                      dev_priv->bridge_dev);
 925         if (ret) {
 926                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 927                 dev_priv->mch_res.start = 0;
 928                 return ret;
 929         }
 930
 931         if (INTEL_INFO(dev)->gen >= 4)
 932                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 933                                        upper_32_bits(dev_priv->mch_res.start));
 934
 935         pci_write_config_dword(dev_priv->bridge_dev, reg,
 936                                lower_32_bits(dev_priv->mch_res.start));
 937         return 0;
 938 }
 939
 940 /* Setup MCHBAR if possible, return true if we should disable it again */
 941 static void
 942 intel_setup_mchbar(struct drm_device *dev)
 943 {
 944         drm_i915_private_t *dev_priv = dev->dev_private;
 945         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 946         u32 temp;
 947         bool enabled;
 948
 949         dev_priv->mchbar_need_disable = false;
 950
 951         if (IS_I915G(dev) || IS_I915GM(dev)) {
 952                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 953                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 954         } else {
 955                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 956                 enabled = temp & 1;
 957         }
 958
 959         /* If it's already enabled, don't have to do anything */
 960         if (enabled)
 961                 return;
 962
 963         if (intel_alloc_mchbar_resource(dev))
 964                 return;
 965
 966         dev_priv->mchbar_need_disable = true;
 967
 968         /* Space is allocated or reserved, so enable it. */
 969         if (IS_I915G(dev) || IS_I915GM(dev)) {
 970                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 971                                        temp | DEVEN_MCHBAR_EN);
 972         } else {
 973                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 974                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 975         }
 976 }
 977
 978 static void
 979 intel_teardown_mchbar(struct drm_device *dev)
 980 {
 981         drm_i915_private_t *dev_priv = dev->dev_private;
 982         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 983         u32 temp;
 984
 985         if (dev_priv->mchbar_need_disable) {
 986                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 987                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 988                         temp &= ~DEVEN_MCHBAR_EN;
 989                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 990                 } else {
 991                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 992                         temp &= ~1;
 993                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 994                 }
 995         }
 996
 997         if (dev_priv->mch_res.start)
 998                 release_resource(&dev_priv->mch_res);
 999 }
1000
1001 #define PTE_ADDRESS_MASK                0xfffff000
1002 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1003 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1004 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1005 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1006 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1007 #define PTE_VALID                       (1 << 0)
1008
1009 /**
1010  * i915_stolen_to_phys - take an offset into stolen memory and turn it into
1011  *                       a physical one
1012  * @dev: drm device
1013  * @offset: address to translate
1014  *
1015  * Some chip functions require allocations from stolen space and need the
1016  * physical address of the memory in question.
1017  */
1018 static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         struct pci_dev *pdev = dev_priv->bridge_dev;
1022         u32 base;
1023
1024 #if 0
1025         /* On the machines I have tested the Graphics Base of Stolen Memory
1026          * is unreliable, so compute the base by subtracting the stolen memory
1027          * from the Top of Low Usable DRAM which is where the BIOS places
1028          * the graphics stolen memory.
1029          */
1030         if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1031                 /* top 32bits are reserved = 0 */
1032                 pci_read_config_dword(pdev, 0xA4, &base);
1033         } else {
1034                 /* XXX presume 8xx is the same as i915 */
1035                 pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
1036         }
1037 #else
1038         if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1039                 u16 val;
1040                 pci_read_config_word(pdev, 0xb0, &val);
1041                 base = val >> 4 << 20;
1042         } else {
1043                 u8 val;
1044                 pci_read_config_byte(pdev, 0x9c, &val);
1045                 base = val >> 3 << 27;
1046         }
1047         base -= dev_priv->mm.gtt->stolen_size;
1048 #endif
1049
1050         return base + offset;
1051 }
1052
1053 static void i915_warn_stolen(struct drm_device *dev)
1054 {
1055         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1056         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1057 }
1058
1059 static void i915_setup_compression(struct drm_device *dev, int size)
1060 {
1061         struct drm_i915_private *dev_priv = dev->dev_private;
1062         struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1063         unsigned long cfb_base;
1064         unsigned long ll_base = 0;
1065
1066         compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);
1067         if (compressed_fb)
1068                 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1069         if (!compressed_fb)
1070                 goto err;
1071
1072         cfb_base = i915_stolen_to_phys(dev, compressed_fb->start);
1073         if (!cfb_base)
1074                 goto err_fb;
1075
1076         if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
1077                 compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen,
1078                                                     4096, 4096, 0);
1079                 if (compressed_llb)
1080                         compressed_llb = drm_mm_get_block(compressed_llb,
1081                                                           4096, 4096);
1082                 if (!compressed_llb)
1083                         goto err_fb;
1084
1085                 ll_base = i915_stolen_to_phys(dev, compressed_llb->start);
1086                 if (!ll_base)
1087                         goto err_llb;
1088         }
1089
1090         dev_priv->cfb_size = size;
1091
1092         intel_disable_fbc(dev);
1093         dev_priv->compressed_fb = compressed_fb;
1094         if (IS_IRONLAKE_M(dev))
1095                 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1096         else if (IS_GM45(dev)) {
1097                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1098         } else {
1099                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1100                 I915_WRITE(FBC_LL_BASE, ll_base);
1101                 dev_priv->compressed_llb = compressed_llb;
1102         }
1103
1104         DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
1105                       cfb_base, ll_base, size >> 20);
1106         return;
1107
1108 err_llb:
1109         drm_mm_put_block(compressed_llb);
1110 err_fb:
1111         drm_mm_put_block(compressed_fb);
1112 err:
1113         dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1114         i915_warn_stolen(dev);
1115 }
1116
1117 static void i915_cleanup_compression(struct drm_device *dev)
1118 {
1119         struct drm_i915_private *dev_priv = dev->dev_private;
1120
1121         drm_mm_put_block(dev_priv->compressed_fb);
1122         if (dev_priv->compressed_llb)
1123                 drm_mm_put_block(dev_priv->compressed_llb);
1124 }
1125
1126 /* true = enable decode, false = disable decoder */
1127 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1128 {
1129         struct drm_device *dev = cookie;
1130
1131         intel_modeset_vga_set_state(dev, state);
1132         if (state)
1133                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1134                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1135         else
1136                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1137 }
1138
1139 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1140 {
1141         struct drm_device *dev = pci_get_drvdata(pdev);
1142         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1143         if (state == VGA_SWITCHEROO_ON) {
1144                 printk(KERN_INFO "i915: switched on\n");
1145                 /* i915 resume handler doesn't set to D0 */
1146                 pci_set_power_state(dev->pdev, PCI_D0);
1147                 i915_resume(dev);
1148         } else {
1149                 printk(KERN_ERR "i915: switched off\n");
1150                 i915_suspend(dev, pmm);
1151         }
1152 }
1153
1154 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1155 {
1156         struct drm_device *dev = pci_get_drvdata(pdev);
1157         bool can_switch;
1158
1159         spin_lock(&dev->count_lock);
1160         can_switch = (dev->open_count == 0);
1161         spin_unlock(&dev->count_lock);
1162         return can_switch;
1163 }
1164
1165 static int i915_load_modeset_init(struct drm_device *dev)
1166 {
1167         struct drm_i915_private *dev_priv = dev->dev_private;
1168         unsigned long prealloc_size, gtt_size, mappable_size;
1169         int ret = 0;
1170
1171         prealloc_size = dev_priv->mm.gtt->stolen_size;
1172         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1173         mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1174
1175         /* Basic memrange allocator for stolen space */
1176         drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
1177
1178         /* Let GEM Manage all of the aperture.
1179          *
1180          * However, leave one page at the end still bound to the scratch page.
1181          * There are a number of places where the hardware apparently
1182          * prefetches past the end of the object, and we've seen multiple
1183          * hangs with the GPU head pointer stuck in a batchbuffer bound
1184          * at the last page of the aperture.  One page should be enough to
1185          * keep any prefetching inside of the aperture.
1186          */
1187         i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
1188
1189         mutex_lock(&dev->struct_mutex);
1190         ret = i915_gem_init_ringbuffer(dev);
1191         mutex_unlock(&dev->struct_mutex);
1192         if (ret)
1193                 goto out;
1194
1195         /* Try to set up FBC with a reasonable compressed buffer size */
1196         if (I915_HAS_FBC(dev) && i915_powersave) {
1197                 int cfb_size;
1198
1199                 /* Leave 1M for line length buffer & misc. */
1200
1201                 /* Try to get a 32M buffer... */
1202                 if (prealloc_size > (36*1024*1024))
1203                         cfb_size = 32*1024*1024;
1204                 else /* fall back to 7/8 of the stolen space */
1205                         cfb_size = prealloc_size * 7 / 8;
1206                 i915_setup_compression(dev, cfb_size);
1207         }
1208
1209         /* Allow hardware batchbuffers unless told otherwise. */
1210         dev_priv->allow_batchbuffer = 1;
1211
1212         ret = intel_parse_bios(dev);
1213         if (ret)
1214                 DRM_INFO("failed to find VBIOS tables\n");
1215
1216         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1217         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1218         if (ret)
1219                 goto cleanup_ringbuffer;
1220
1221         intel_register_dsm_handler();
1222
1223         ret = vga_switcheroo_register_client(dev->pdev,
1224                                              i915_switcheroo_set_state,
1225                                              i915_switcheroo_can_switch);
1226         if (ret)
1227                 goto cleanup_vga_client;
1228
1229         /* IIR "flip pending" bit means done if this bit is set */
1230         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1231                 dev_priv->flip_pending_is_done = true;
1232
1233         intel_modeset_init(dev);
1234
1235         ret = drm_irq_install(dev);
1236         if (ret)
1237                 goto cleanup_vga_switcheroo;
1238
1239         /* Always safe in the mode setting case. */
1240         /* FIXME: do pre/post-mode set stuff in core KMS code */
1241         dev->vblank_disable_allowed = 1;
1242
1243         ret = intel_fbdev_init(dev);
1244         if (ret)
1245                 goto cleanup_irq;
1246
1247         drm_kms_helper_poll_init(dev);
1248
1249         /* We're off and running w/KMS */
1250         dev_priv->mm.suspended = 0;
1251
1252         return 0;
1253
1254 cleanup_irq:
1255         drm_irq_uninstall(dev);
1256 cleanup_vga_switcheroo:
1257         vga_switcheroo_unregister_client(dev->pdev);
1258 cleanup_vga_client:
1259         vga_client_register(dev->pdev, NULL, NULL, NULL);
1260 cleanup_ringbuffer:
1261         mutex_lock(&dev->struct_mutex);
1262         i915_gem_cleanup_ringbuffer(dev);
1263         mutex_unlock(&dev->struct_mutex);
1264 out:
1265         return ret;
1266 }
1267
1268 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1269 {
1270         struct drm_i915_master_private *master_priv;
1271
1272         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1273         if (!master_priv)
1274                 return -ENOMEM;
1275
1276         master->driver_priv = master_priv;
1277         return 0;
1278 }
1279
1280 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1281 {
1282         struct drm_i915_master_private *master_priv = master->driver_priv;
1283
1284         if (!master_priv)
1285                 return;
1286
1287         kfree(master_priv);
1288
1289         master->driver_priv = NULL;
1290 }
1291
1292 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1293 {
1294         drm_i915_private_t *dev_priv = dev->dev_private;
1295         u32 tmp;
1296
1297         tmp = I915_READ(CLKCFG);
1298
1299         switch (tmp & CLKCFG_FSB_MASK) {
1300         case CLKCFG_FSB_533:
1301                 dev_priv->fsb_freq = 533; /* 133*4 */
1302                 break;
1303         case CLKCFG_FSB_800:
1304                 dev_priv->fsb_freq = 800; /* 200*4 */
1305                 break;
1306         case CLKCFG_FSB_667:
1307                 dev_priv->fsb_freq =  667; /* 167*4 */
1308                 break;
1309         case CLKCFG_FSB_400:
1310                 dev_priv->fsb_freq = 400; /* 100*4 */
1311                 break;
1312         }
1313
1314         switch (tmp & CLKCFG_MEM_MASK) {
1315         case CLKCFG_MEM_533:
1316                 dev_priv->mem_freq = 533;
1317                 break;
1318         case CLKCFG_MEM_667:
1319                 dev_priv->mem_freq = 667;
1320                 break;
1321         case CLKCFG_MEM_800:
1322                 dev_priv->mem_freq = 800;
1323                 break;
1324         }
1325
1326         /* detect pineview DDR3 setting */
1327         tmp = I915_READ(CSHRDDR3CTL);
1328         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1329 }
1330
1331 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1332 {
1333         drm_i915_private_t *dev_priv = dev->dev_private;
1334         u16 ddrpll, csipll;
1335
1336         ddrpll = I915_READ16(DDRMPLL1);
1337         csipll = I915_READ16(CSIPLL0);
1338
1339         switch (ddrpll & 0xff) {
1340         case 0xc:
1341                 dev_priv->mem_freq = 800;
1342                 break;
1343         case 0x10:
1344                 dev_priv->mem_freq = 1066;
1345                 break;
1346         case 0x14:
1347                 dev_priv->mem_freq = 1333;
1348                 break;
1349         case 0x18:
1350                 dev_priv->mem_freq = 1600;
1351                 break;
1352         default:
1353                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1354                                  ddrpll & 0xff);
1355                 dev_priv->mem_freq = 0;
1356                 break;
1357         }
1358
1359         dev_priv->r_t = dev_priv->mem_freq;
1360
1361         switch (csipll & 0x3ff) {
1362         case 0x00c:
1363                 dev_priv->fsb_freq = 3200;
1364                 break;
1365         case 0x00e:
1366                 dev_priv->fsb_freq = 3733;
1367                 break;
1368         case 0x010:
1369                 dev_priv->fsb_freq = 4266;
1370                 break;
1371         case 0x012:
1372                 dev_priv->fsb_freq = 4800;
1373                 break;
1374         case 0x014:
1375                 dev_priv->fsb_freq = 5333;
1376                 break;
1377         case 0x016:
1378                 dev_priv->fsb_freq = 5866;
1379                 break;
1380         case 0x018:
1381                 dev_priv->fsb_freq = 6400;
1382                 break;
1383         default:
1384                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1385                                  csipll & 0x3ff);
1386                 dev_priv->fsb_freq = 0;
1387                 break;
1388         }
1389
1390         if (dev_priv->fsb_freq == 3200) {
1391                 dev_priv->c_m = 0;
1392         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1393                 dev_priv->c_m = 1;
1394         } else {
1395                 dev_priv->c_m = 2;
1396         }
1397 }
1398
1399 static const struct cparams {
1400         u16 i;
1401         u16 t;
1402         u16 m;
1403         u16 c;
1404 } cparams[] = {
1405         { 1, 1333, 301, 28664 },
1406         { 1, 1066, 294, 24460 },
1407         { 1, 800, 294, 25192 },
1408         { 0, 1333, 276, 27605 },
1409         { 0, 1066, 276, 27605 },
1410         { 0, 800, 231, 23784 },
1411 };
1412
1413 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1414 {
1415         u64 total_count, diff, ret;
1416         u32 count1, count2, count3, m = 0, c = 0;
1417         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1418         int i;
1419
1420         diff1 = now - dev_priv->last_time1;
1421
1422         count1 = I915_READ(DMIEC);
1423         count2 = I915_READ(DDREC);
1424         count3 = I915_READ(CSIEC);
1425
1426         total_count = count1 + count2 + count3;
1427
1428         /* FIXME: handle per-counter overflow */
1429         if (total_count < dev_priv->last_count1) {
1430                 diff = ~0UL - dev_priv->last_count1;
1431                 diff += total_count;
1432         } else {
1433                 diff = total_count - dev_priv->last_count1;
1434         }
1435
1436         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1437                 if (cparams[i].i == dev_priv->c_m &&
1438                     cparams[i].t == dev_priv->r_t) {
1439                         m = cparams[i].m;
1440                         c = cparams[i].c;
1441                         break;
1442                 }
1443         }
1444
1445         diff = div_u64(diff, diff1);
1446         ret = ((m * diff) + c);
1447         ret = div_u64(ret, 10);
1448
1449         dev_priv->last_count1 = total_count;
1450         dev_priv->last_time1 = now;
1451
1452         return ret;
1453 }
1454
1455 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1456 {
1457         unsigned long m, x, b;
1458         u32 tsfs;
1459
1460         tsfs = I915_READ(TSFS);
1461
1462         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1463         x = I915_READ8(TR1);
1464
1465         b = tsfs & TSFS_INTR_MASK;
1466
1467         return ((m * x) / 127) - b;
1468 }
1469
1470 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1471 {
1472         static const struct v_table {
1473                 u16 vd; /* in .1 mil */
1474                 u16 vm; /* in .1 mil */
1475         } v_table[] = {
1476                 { 0, 0, },
1477                 { 375, 0, },
1478                 { 500, 0, },
1479                 { 625, 0, },
1480                 { 750, 0, },
1481                 { 875, 0, },
1482                 { 1000, 0, },
1483                 { 1125, 0, },
1484                 { 4125, 3000, },
1485                 { 4125, 3000, },
1486                 { 4125, 3000, },
1487                 { 4125, 3000, },
1488                 { 4125, 3000, },
1489                 { 4125, 3000, },
1490                 { 4125, 3000, },
1491                 { 4125, 3000, },
1492                 { 4125, 3000, },
1493                 { 4125, 3000, },
1494                 { 4125, 3000, },
1495                 { 4125, 3000, },
1496                 { 4125, 3000, },
1497                 { 4125, 3000, },
1498                 { 4125, 3000, },
1499                 { 4125, 3000, },
1500                 { 4125, 3000, },
1501                 { 4125, 3000, },
1502                 { 4125, 3000, },
1503                 { 4125, 3000, },
1504                 { 4125, 3000, },
1505                 { 4125, 3000, },
1506                 { 4125, 3000, },
1507                 { 4125, 3000, },
1508                 { 4250, 3125, },
1509                 { 4375, 3250, },
1510                 { 4500, 3375, },
1511                 { 4625, 3500, },
1512                 { 4750, 3625, },
1513                 { 4875, 3750, },
1514                 { 5000, 3875, },
1515                 { 5125, 4000, },
1516                 { 5250, 4125, },
1517                 { 5375, 4250, },
1518                 { 5500, 4375, },
1519                 { 5625, 4500, },
1520                 { 5750, 4625, },
1521                 { 5875, 4750, },
1522                 { 6000, 4875, },
1523                 { 6125, 5000, },
1524                 { 6250, 5125, },
1525                 { 6375, 5250, },
1526                 { 6500, 5375, },
1527                 { 6625, 5500, },
1528                 { 6750, 5625, },
1529                 { 6875, 5750, },
1530                 { 7000, 5875, },
1531                 { 7125, 6000, },
1532                 { 7250, 6125, },
1533                 { 7375, 6250, },
1534                 { 7500, 6375, },
1535                 { 7625, 6500, },
1536                 { 7750, 6625, },
1537                 { 7875, 6750, },
1538                 { 8000, 6875, },
1539                 { 8125, 7000, },
1540                 { 8250, 7125, },
1541                 { 8375, 7250, },
1542                 { 8500, 7375, },
1543                 { 8625, 7500, },
1544                 { 8750, 7625, },
1545                 { 8875, 7750, },
1546                 { 9000, 7875, },
1547                 { 9125, 8000, },
1548                 { 9250, 8125, },
1549                 { 9375, 8250, },
1550                 { 9500, 8375, },
1551                 { 9625, 8500, },
1552                 { 9750, 8625, },
1553                 { 9875, 8750, },
1554                 { 10000, 8875, },
1555                 { 10125, 9000, },
1556                 { 10250, 9125, },
1557                 { 10375, 9250, },
1558                 { 10500, 9375, },
1559                 { 10625, 9500, },
1560                 { 10750, 9625, },
1561                 { 10875, 9750, },
1562                 { 11000, 9875, },
1563                 { 11125, 10000, },
1564                 { 11250, 10125, },
1565                 { 11375, 10250, },
1566                 { 11500, 10375, },
1567                 { 11625, 10500, },
1568                 { 11750, 10625, },
1569                 { 11875, 10750, },
1570                 { 12000, 10875, },
1571                 { 12125, 11000, },
1572                 { 12250, 11125, },
1573                 { 12375, 11250, },
1574                 { 12500, 11375, },
1575                 { 12625, 11500, },
1576                 { 12750, 11625, },
1577                 { 12875, 11750, },
1578                 { 13000, 11875, },
1579                 { 13125, 12000, },
1580                 { 13250, 12125, },
1581                 { 13375, 12250, },
1582                 { 13500, 12375, },
1583                 { 13625, 12500, },
1584                 { 13750, 12625, },
1585                 { 13875, 12750, },
1586                 { 14000, 12875, },
1587                 { 14125, 13000, },
1588                 { 14250, 13125, },
1589                 { 14375, 13250, },
1590                 { 14500, 13375, },
1591                 { 14625, 13500, },
1592                 { 14750, 13625, },
1593                 { 14875, 13750, },
1594                 { 15000, 13875, },
1595                 { 15125, 14000, },
1596                 { 15250, 14125, },
1597                 { 15375, 14250, },
1598                 { 15500, 14375, },
1599                 { 15625, 14500, },
1600                 { 15750, 14625, },
1601                 { 15875, 14750, },
1602                 { 16000, 14875, },
1603                 { 16125, 15000, },
1604         };
1605         if (dev_priv->info->is_mobile)
1606                 return v_table[pxvid].vm;
1607         else
1608                 return v_table[pxvid].vd;
1609 }
1610
1611 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1612 {
1613         struct timespec now, diff1;
1614         u64 diff;
1615         unsigned long diffms;
1616         u32 count;
1617
1618         getrawmonotonic(&now);
1619         diff1 = timespec_sub(now, dev_priv->last_time2);
1620
1621         /* Don't divide by 0 */
1622         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1623         if (!diffms)
1624                 return;
1625
1626         count = I915_READ(GFXEC);
1627
1628         if (count < dev_priv->last_count2) {
1629                 diff = ~0UL - dev_priv->last_count2;
1630                 diff += count;
1631         } else {
1632                 diff = count - dev_priv->last_count2;
1633         }
1634
1635         dev_priv->last_count2 = count;
1636         dev_priv->last_time2 = now;
1637
1638         /* More magic constants... */
1639         diff = diff * 1181;
1640         diff = div_u64(diff, diffms * 10);
1641         dev_priv->gfx_power = diff;
1642 }
1643
1644 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1645 {
1646         unsigned long t, corr, state1, corr2, state2;
1647         u32 pxvid, ext_v;
1648
1649         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1650         pxvid = (pxvid >> 24) & 0x7f;
1651         ext_v = pvid_to_extvid(dev_priv, pxvid);
1652
1653         state1 = ext_v;
1654
1655         t = i915_mch_val(dev_priv);
1656
1657         /* Revel in the empirically derived constants */
1658
1659         /* Correction factor in 1/100000 units */
1660         if (t > 80)
1661                 corr = ((t * 2349) + 135940);
1662         else if (t >= 50)
1663                 corr = ((t * 964) + 29317);
1664         else /* < 50 */
1665                 corr = ((t * 301) + 1004);
1666
1667         corr = corr * ((150142 * state1) / 10000 - 78642);
1668         corr /= 100000;
1669         corr2 = (corr * dev_priv->corr);
1670
1671         state2 = (corr2 * state1) / 10000;
1672         state2 /= 100; /* convert to mW */
1673
1674         i915_update_gfx_val(dev_priv);
1675
1676         return dev_priv->gfx_power + state2;
1677 }
1678
1679 /* Global for IPS driver to get at the current i915 device */
1680 static struct drm_i915_private *i915_mch_dev;
1681 /*
1682  * Lock protecting IPS related data structures
1683  *   - i915_mch_dev
1684  *   - dev_priv->max_delay
1685  *   - dev_priv->min_delay
1686  *   - dev_priv->fmax
1687  *   - dev_priv->gpu_busy
1688  */
1689 static DEFINE_SPINLOCK(mchdev_lock);
1690
1691 /**
1692  * i915_read_mch_val - return value for IPS use
1693  *
1694  * Calculate and return a value for the IPS driver to use when deciding whether
1695  * we have thermal and power headroom to increase CPU or GPU power budget.
1696  */
1697 unsigned long i915_read_mch_val(void)
1698 {
1699         struct drm_i915_private *dev_priv;
1700         unsigned long chipset_val, graphics_val, ret = 0;
1701
1702         spin_lock(&mchdev_lock);
1703         if (!i915_mch_dev)
1704                 goto out_unlock;
1705         dev_priv = i915_mch_dev;
1706
1707         chipset_val = i915_chipset_val(dev_priv);
1708         graphics_val = i915_gfx_val(dev_priv);
1709
1710         ret = chipset_val + graphics_val;
1711
1712 out_unlock:
1713         spin_unlock(&mchdev_lock);
1714
1715         return ret;
1716 }
1717 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1718
1719 /**
1720  * i915_gpu_raise - raise GPU frequency limit
1721  *
1722  * Raise the limit; IPS indicates we have thermal headroom.
1723  */
1724 bool i915_gpu_raise(void)
1725 {
1726         struct drm_i915_private *dev_priv;
1727         bool ret = true;
1728
1729         spin_lock(&mchdev_lock);
1730         if (!i915_mch_dev) {
1731                 ret = false;
1732                 goto out_unlock;
1733         }
1734         dev_priv = i915_mch_dev;
1735
1736         if (dev_priv->max_delay > dev_priv->fmax)
1737                 dev_priv->max_delay--;
1738
1739 out_unlock:
1740         spin_unlock(&mchdev_lock);
1741
1742         return ret;
1743 }
1744 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1745
1746 /**
1747  * i915_gpu_lower - lower GPU frequency limit
1748  *
1749  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1750  * frequency maximum.
1751  */
1752 bool i915_gpu_lower(void)
1753 {
1754         struct drm_i915_private *dev_priv;
1755         bool ret = true;
1756
1757         spin_lock(&mchdev_lock);
1758         if (!i915_mch_dev) {
1759                 ret = false;
1760                 goto out_unlock;
1761         }
1762         dev_priv = i915_mch_dev;
1763
1764         if (dev_priv->max_delay < dev_priv->min_delay)
1765                 dev_priv->max_delay++;
1766
1767 out_unlock:
1768         spin_unlock(&mchdev_lock);
1769
1770         return ret;
1771 }
1772 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1773
1774 /**
1775  * i915_gpu_busy - indicate GPU business to IPS
1776  *
1777  * Tell the IPS driver whether or not the GPU is busy.
1778  */
1779 bool i915_gpu_busy(void)
1780 {
1781         struct drm_i915_private *dev_priv;
1782         bool ret = false;
1783
1784         spin_lock(&mchdev_lock);
1785         if (!i915_mch_dev)
1786                 goto out_unlock;
1787         dev_priv = i915_mch_dev;
1788
1789         ret = dev_priv->busy;
1790
1791 out_unlock:
1792         spin_unlock(&mchdev_lock);
1793
1794         return ret;
1795 }
1796 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1797
1798 /**
1799  * i915_gpu_turbo_disable - disable graphics turbo
1800  *
1801  * Disable graphics turbo by resetting the max frequency and setting the
1802  * current frequency to the default.
1803  */
1804 bool i915_gpu_turbo_disable(void)
1805 {
1806         struct drm_i915_private *dev_priv;
1807         bool ret = true;
1808
1809         spin_lock(&mchdev_lock);
1810         if (!i915_mch_dev) {
1811                 ret = false;
1812                 goto out_unlock;
1813         }
1814         dev_priv = i915_mch_dev;
1815
1816         dev_priv->max_delay = dev_priv->fstart;
1817
1818         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1819                 ret = false;
1820
1821 out_unlock:
1822         spin_unlock(&mchdev_lock);
1823
1824         return ret;
1825 }
1826 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1827
1828 /**
1829  * i915_driver_load - setup chip and create an initial config
1830  * @dev: DRM device
1831  * @flags: startup flags
1832  *
1833  * The driver load routine has to do several things:
1834  *   - drive output discovery via intel_modeset_init()
1835  *   - initialize the memory manager
1836  *   - allocate initial config memory
1837  *   - setup the DRM framebuffer with the allocated memory
1838  */
1839 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1840 {
1841         struct drm_i915_private *dev_priv;
1842         int ret = 0, mmio_bar;
1843         uint32_t agp_size;
1844
1845         /* i915 has 4 more counters */
1846         dev->counters += 4;
1847         dev->types[6] = _DRM_STAT_IRQ;
1848         dev->types[7] = _DRM_STAT_PRIMARY;
1849         dev->types[8] = _DRM_STAT_SECONDARY;
1850         dev->types[9] = _DRM_STAT_DMA;
1851
1852         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1853         if (dev_priv == NULL)
1854                 return -ENOMEM;
1855
1856         dev->dev_private = (void *)dev_priv;
1857         dev_priv->dev = dev;
1858         dev_priv->info = (struct intel_device_info *) flags;
1859
1860         if (i915_get_bridge_dev(dev)) {
1861                 ret = -EIO;
1862                 goto free_priv;
1863         }
1864
1865         /* overlay on gen2 is broken and can't address above 1G */
1866         if (IS_GEN2(dev))
1867                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1868
1869         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1870         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1871         if (!dev_priv->regs) {
1872                 DRM_ERROR("failed to map registers\n");
1873                 ret = -EIO;
1874                 goto put_bridge;
1875         }
1876
1877         dev_priv->mm.gtt = intel_gtt_get();
1878         if (!dev_priv->mm.gtt) {
1879                 DRM_ERROR("Failed to initialize GTT\n");
1880                 ret = -ENODEV;
1881                 goto out_iomapfree;
1882         }
1883
1884         agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1885
1886         dev_priv->mm.gtt_mapping =
1887                 io_mapping_create_wc(dev->agp->base, agp_size);
1888         if (dev_priv->mm.gtt_mapping == NULL) {
1889                 ret = -EIO;
1890                 goto out_rmmap;
1891         }
1892
1893         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1894          * one would think, because the kernel disables PAT on first
1895          * generation Core chips because WC PAT gets overridden by a UC
1896          * MTRR if present.  Even if a UC MTRR isn't present.
1897          */
1898         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1899                                          agp_size,
1900                                          MTRR_TYPE_WRCOMB, 1);
1901         if (dev_priv->mm.gtt_mtrr < 0) {
1902                 DRM_INFO("MTRR allocation failed.  Graphics "
1903                          "performance may suffer.\n");
1904         }
1905
1906         /* The i915 workqueue is primarily used for batched retirement of
1907          * requests (and thus managing bo) once the task has been completed
1908          * by the GPU. i915_gem_retire_requests() is called directly when we
1909          * need high-priority retirement, such as waiting for an explicit
1910          * bo.
1911          *
1912          * It is also used for periodic low-priority events, such as
1913          * idle-timers and recording error state.
1914          *
1915          * All tasks on the workqueue are expected to acquire the dev mutex
1916          * so there is no point in running more than one instance of the
1917          * workqueue at any time: max_active = 1 and NON_REENTRANT.
1918          */
1919         dev_priv->wq = alloc_workqueue("i915",
1920                                        WQ_UNBOUND | WQ_NON_REENTRANT,
1921                                        1);
1922         if (dev_priv->wq == NULL) {
1923                 DRM_ERROR("Failed to create our workqueue.\n");
1924                 ret = -ENOMEM;
1925                 goto out_iomapfree;
1926         }
1927
1928         /* enable GEM by default */
1929         dev_priv->has_gem = 1;
1930
1931         if (dev_priv->has_gem == 0 &&
1932             drm_core_check_feature(dev, DRIVER_MODESET)) {
1933                 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
1934                 ret = -ENODEV;
1935                 goto out_workqueue_free;
1936         }
1937
1938         dev->driver->get_vblank_counter = i915_get_vblank_counter;
1939         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1940         if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
1941                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1942                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1943         }
1944
1945         /* Try to make sure MCHBAR is enabled before poking at it */
1946         intel_setup_mchbar(dev);
1947         intel_setup_gmbus(dev);
1948         intel_opregion_setup(dev);
1949
1950         /* Make sure the bios did its job and set up vital registers */
1951         intel_setup_bios(dev);
1952
1953         i915_gem_load(dev);
1954
1955         /* Init HWS */
1956         if (!I915_NEED_GFX_HWS(dev)) {
1957                 ret = i915_init_phys_hws(dev);
1958                 if (ret)
1959                         goto out_gem_unload;
1960         }
1961
1962         if (IS_PINEVIEW(dev))
1963                 i915_pineview_get_mem_freq(dev);
1964         else if (IS_GEN5(dev))
1965                 i915_ironlake_get_mem_freq(dev);
1966
1967         /* On the 945G/GM, the chipset reports the MSI capability on the
1968          * integrated graphics even though the support isn't actually there
1969          * according to the published specs.  It doesn't appear to function
1970          * correctly in testing on 945G.
1971          * This may be a side effect of MSI having been made available for PEG
1972          * and the registers being closely associated.
1973          *
1974          * According to chipset errata, on the 965GM, MSI interrupts may
1975          * be lost or delayed, but we use them anyways to avoid
1976          * stuck interrupts on some machines.
1977          */
1978         if (!IS_I945G(dev) && !IS_I945GM(dev))
1979                 pci_enable_msi(dev->pdev);
1980
1981         spin_lock_init(&dev_priv->user_irq_lock);
1982         spin_lock_init(&dev_priv->error_lock);
1983         dev_priv->trace_irq_seqno = 0;
1984
1985         ret = drm_vblank_init(dev, I915_NUM_PIPE);
1986         if (ret)
1987                 goto out_gem_unload;
1988
1989         /* Start out suspended */
1990         dev_priv->mm.suspended = 1;
1991
1992         intel_detect_pch(dev);
1993
1994         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1995                 ret = i915_load_modeset_init(dev);
1996                 if (ret < 0) {
1997                         DRM_ERROR("failed to init modeset\n");
1998                         goto out_gem_unload;
1999                 }
2000         }
2001
2002         /* Must be done after probing outputs */
2003         intel_opregion_init(dev);
2004         acpi_video_register();
2005
2006         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2007                     (unsigned long) dev);
2008
2009         spin_lock(&mchdev_lock);
2010         i915_mch_dev = dev_priv;
2011         dev_priv->mchdev_lock = &mchdev_lock;
2012         spin_unlock(&mchdev_lock);
2013
2014         return 0;
2015
2016 out_gem_unload:
2017         if (dev->pdev->msi_enabled)
2018                 pci_disable_msi(dev->pdev);
2019
2020         intel_teardown_gmbus(dev);
2021         intel_teardown_mchbar(dev);
2022 out_workqueue_free:
2023         destroy_workqueue(dev_priv->wq);
2024 out_iomapfree:
2025         io_mapping_free(dev_priv->mm.gtt_mapping);
2026 out_rmmap:
2027         pci_iounmap(dev->pdev, dev_priv->regs);
2028 put_bridge:
2029         pci_dev_put(dev_priv->bridge_dev);
2030 free_priv:
2031         kfree(dev_priv);
2032         return ret;
2033 }
2034
2035 int i915_driver_unload(struct drm_device *dev)
2036 {
2037         struct drm_i915_private *dev_priv = dev->dev_private;
2038         int ret;
2039
2040         spin_lock(&mchdev_lock);
2041         i915_mch_dev = NULL;
2042         spin_unlock(&mchdev_lock);
2043
2044         if (dev_priv->mm.inactive_shrinker.shrink)
2045                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2046
2047         mutex_lock(&dev->struct_mutex);
2048         ret = i915_gpu_idle(dev);
2049         if (ret)
2050                 DRM_ERROR("failed to idle hardware: %d\n", ret);
2051         mutex_unlock(&dev->struct_mutex);
2052
2053         /* Cancel the retire work handler, which should be idle now. */
2054         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2055
2056         io_mapping_free(dev_priv->mm.gtt_mapping);
2057         if (dev_priv->mm.gtt_mtrr >= 0) {
2058                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2059                          dev->agp->agp_info.aper_size * 1024 * 1024);
2060                 dev_priv->mm.gtt_mtrr = -1;
2061         }
2062
2063         acpi_video_unregister();
2064
2065         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2066                 intel_fbdev_fini(dev);
2067                 intel_modeset_cleanup(dev);
2068
2069                 /*
2070                  * free the memory space allocated for the child device
2071                  * config parsed from VBT
2072                  */
2073                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2074                         kfree(dev_priv->child_dev);
2075                         dev_priv->child_dev = NULL;
2076                         dev_priv->child_dev_num = 0;
2077                 }
2078
2079                 vga_switcheroo_unregister_client(dev->pdev);
2080                 vga_client_register(dev->pdev, NULL, NULL, NULL);
2081         }
2082
2083         /* Free error state after interrupts are fully disabled. */
2084         del_timer_sync(&dev_priv->hangcheck_timer);
2085         cancel_work_sync(&dev_priv->error_work);
2086         i915_destroy_error_state(dev);
2087
2088         if (dev->pdev->msi_enabled)
2089                 pci_disable_msi(dev->pdev);
2090
2091         intel_opregion_fini(dev);
2092
2093         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2094                 /* Flush any outstanding unpin_work. */
2095                 flush_workqueue(dev_priv->wq);
2096
2097                 i915_gem_free_all_phys_object(dev);
2098
2099                 mutex_lock(&dev->struct_mutex);
2100                 i915_gem_cleanup_ringbuffer(dev);
2101                 mutex_unlock(&dev->struct_mutex);
2102                 if (I915_HAS_FBC(dev) && i915_powersave)
2103                         i915_cleanup_compression(dev);
2104                 drm_mm_takedown(&dev_priv->mm.stolen);
2105
2106                 intel_cleanup_overlay(dev);
2107
2108                 if (!I915_NEED_GFX_HWS(dev))
2109                         i915_free_hws(dev);
2110         }
2111
2112         if (dev_priv->regs != NULL)
2113                 pci_iounmap(dev->pdev, dev_priv->regs);
2114
2115         intel_teardown_gmbus(dev);
2116         intel_teardown_mchbar(dev);
2117
2118         destroy_workqueue(dev_priv->wq);
2119
2120         pci_dev_put(dev_priv->bridge_dev);
2121         kfree(dev->dev_private);
2122
2123         return 0;
2124 }
2125
2126 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2127 {
2128         struct drm_i915_file_private *file_priv;
2129
2130         DRM_DEBUG_DRIVER("\n");
2131         file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2132         if (!file_priv)
2133                 return -ENOMEM;
2134
2135         file->driver_priv = file_priv;
2136
2137         spin_lock_init(&file_priv->mm.lock);
2138         INIT_LIST_HEAD(&file_priv->mm.request_list);
2139
2140         return 0;
2141 }
2142
2143 /**
2144  * i915_driver_lastclose - clean up after all DRM clients have exited
2145  * @dev: DRM device
2146  *
2147  * Take care of cleaning up after all DRM clients have exited.  In the
2148  * mode setting case, we want to restore the kernel's initial mode (just
2149  * in case the last client left us in a bad state).
2150  *
2151  * Additionally, in the non-mode setting case, we'll tear down the AGP
2152  * and DMA structures, since the kernel won't be using them, and clea
2153  * up any GEM state.
2154  */
2155 void i915_driver_lastclose(struct drm_device * dev)
2156 {
2157         drm_i915_private_t *dev_priv = dev->dev_private;
2158
2159         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2160                 drm_fb_helper_restore();
2161                 vga_switcheroo_process_delayed_switch();
2162                 return;
2163         }
2164
2165         i915_gem_lastclose(dev);
2166
2167         if (dev_priv->agp_heap)
2168                 i915_mem_takedown(&(dev_priv->agp_heap));
2169
2170         i915_dma_cleanup(dev);
2171 }
2172
2173 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2174 {
2175         drm_i915_private_t *dev_priv = dev->dev_private;
2176         i915_gem_release(dev, file_priv);
2177         if (!drm_core_check_feature(dev, DRIVER_MODESET))
2178                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2179 }
2180
2181 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2182 {
2183         struct drm_i915_file_private *file_priv = file->driver_priv;
2184
2185         kfree(file_priv);
2186 }
2187
2188 struct drm_ioctl_desc i915_ioctls[] = {
2189         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2190         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2191         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2192         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2193         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2194         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2195         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2196         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2197         DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2198         DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2199         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2200         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2201         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2202         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2203         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
2204         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2205         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2206         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2207         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2208         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2209         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2210         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2211         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2212         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2213         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2214         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2215         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2216         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2217         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2218         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2219         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2220         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2221         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2222         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2223         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2224         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2225         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2226         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2227         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2228         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2229 };
2230
2231 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2232
2233 /**
2234  * Determine if the device really is AGP or not.
2235  *
2236  * All Intel graphics chipsets are treated as AGP, even if they are really
2237  * PCI-e.
2238  *
2239  * \param dev   The device to be tested.
2240  *
2241  * \returns
2242  * A value of 1 is always retured to indictate every i9x5 is AGP.
2243  */
2244 int i915_driver_device_is_agp(struct drm_device * dev)
2245 {
2246         return 1;
2247 }