drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include <drm/drm_legacy.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38 #include "i915_vgpu.h"
  39 #include "i915_trace.h"
  40 #include <linux/pci.h>
  41 #include <linux/console.h>
  42 #include <linux/vt.h>
  43 #include <linux/vgaarb.h>
  44 #include <linux/acpi.h>
  45 #include <linux/pnp.h>
  46 #include <linux/vga_switcheroo.h>
  47 #include <linux/slab.h>
  48 #include <acpi/video.h>
  49 #include <linux/pm.h>
  50 #include <linux/pm_runtime.h>
  51 #include <linux/oom.h>
  52
  53
  54 static int i915_getparam(struct drm_device *dev, void *data,
  55                          struct drm_file *file_priv)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58         drm_i915_getparam_t *param = data;
  59         int value;
  60
  61         switch (param->param) {
  62         case I915_PARAM_IRQ_ACTIVE:
  63         case I915_PARAM_ALLOW_BATCHBUFFER:
  64         case I915_PARAM_LAST_DISPATCH:
  65                 /* Reject all old ums/dri params. */
  66                 return -ENODEV;
  67         case I915_PARAM_CHIPSET_ID:
  68                 value = dev->pdev->device;
  69                 break;
  70         case I915_PARAM_REVISION:
  71                 value = dev->pdev->revision;
  72                 break;
  73         case I915_PARAM_HAS_GEM:
  74                 value = 1;
  75                 break;
  76         case I915_PARAM_NUM_FENCES_AVAIL:
  77                 value = dev_priv->num_fence_regs;
  78                 break;
  79         case I915_PARAM_HAS_OVERLAY:
  80                 value = dev_priv->overlay ? 1 : 0;
  81                 break;
  82         case I915_PARAM_HAS_PAGEFLIPPING:
  83                 value = 1;
  84                 break;
  85         case I915_PARAM_HAS_EXECBUF2:
  86                 /* depends on GEM */
  87                 value = 1;
  88                 break;
  89         case I915_PARAM_HAS_BSD:
  90                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
  91                 break;
  92         case I915_PARAM_HAS_BLT:
  93                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
  94                 break;
  95         case I915_PARAM_HAS_VEBOX:
  96                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
  97                 break;
  98         case I915_PARAM_HAS_BSD2:
  99                 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
 100                 break;
 101         case I915_PARAM_HAS_RELAXED_FENCING:
 102                 value = 1;
 103                 break;
 104         case I915_PARAM_HAS_COHERENT_RINGS:
 105                 value = 1;
 106                 break;
 107         case I915_PARAM_HAS_EXEC_CONSTANTS:
 108                 value = INTEL_INFO(dev)->gen >= 4;
 109                 break;
 110         case I915_PARAM_HAS_RELAXED_DELTA:
 111                 value = 1;
 112                 break;
 113         case I915_PARAM_HAS_GEN7_SOL_RESET:
 114                 value = 1;
 115                 break;
 116         case I915_PARAM_HAS_LLC:
 117                 value = HAS_LLC(dev);
 118                 break;
 119         case I915_PARAM_HAS_WT:
 120                 value = HAS_WT(dev);
 121                 break;
 122         case I915_PARAM_HAS_ALIASING_PPGTT:
 123                 value = USES_PPGTT(dev);
 124                 break;
 125         case I915_PARAM_HAS_WAIT_TIMEOUT:
 126                 value = 1;
 127                 break;
 128         case I915_PARAM_HAS_SEMAPHORES:
 129                 value = i915_semaphore_is_enabled(dev);
 130                 break;
 131         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 132                 value = 1;
 133                 break;
 134         case I915_PARAM_HAS_SECURE_BATCHES:
 135                 value = capable(CAP_SYS_ADMIN);
 136                 break;
 137         case I915_PARAM_HAS_PINNED_BATCHES:
 138                 value = 1;
 139                 break;
 140         case I915_PARAM_HAS_EXEC_NO_RELOC:
 141                 value = 1;
 142                 break;
 143         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 144                 value = 1;
 145                 break;
 146         case I915_PARAM_CMD_PARSER_VERSION:
 147                 value = i915_cmd_parser_get_version();
 148                 break;
 149         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 150                 value = 1;
 151                 break;
 152         case I915_PARAM_MMAP_VERSION:
 153                 value = 1;
 154                 break;
 155         case I915_PARAM_SUBSLICE_TOTAL:
 156                 value = INTEL_INFO(dev)->subslice_total;
 157                 if (!value)
 158                         return -ENODEV;
 159                 break;
 160         case I915_PARAM_EU_TOTAL:
 161                 value = INTEL_INFO(dev)->eu_total;
 162                 if (!value)
 163                         return -ENODEV;
 164                 break;
 165         case I915_PARAM_HAS_GPU_RESET:
 166                 value = i915.enable_hangcheck &&
 167                         intel_has_gpu_reset(dev);
 168                 break;
 169         case I915_PARAM_HAS_RESOURCE_STREAMER:
 170                 value = HAS_RESOURCE_STREAMER(dev);
 171                 break;
 172         case I915_PARAM_HAS_EXEC_SOFTPIN:
 173                 value = 1;
 174                 break;
 175         default:
 176                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 177                 return -EINVAL;
 178         }
 179
 180         if (copy_to_user(param->value, &value, sizeof(int))) {
 181                 DRM_ERROR("copy_to_user failed\n");
 182                 return -EFAULT;
 183         }
 184
 185         return 0;
 186 }
 187
 188 static int i915_get_bridge_dev(struct drm_device *dev)
 189 {
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191
 192         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 193         if (!dev_priv->bridge_dev) {
 194                 DRM_ERROR("bridge device not found\n");
 195                 return -1;
 196         }
 197         return 0;
 198 }
 199
 200 #define MCHBAR_I915 0x44
 201 #define MCHBAR_I965 0x48
 202 #define MCHBAR_SIZE (4*4096)
 203
 204 #define DEVEN_REG 0x54
 205 #define   DEVEN_MCHBAR_EN (1 << 28)
 206
 207 /* Allocate space for the MCH regs if needed, return nonzero on error */
 208 static int
 209 intel_alloc_mchbar_resource(struct drm_device *dev)
 210 {
 211         struct drm_i915_private *dev_priv = dev->dev_private;
 212         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 213         u32 temp_lo, temp_hi = 0;
 214         u64 mchbar_addr;
 215         int ret;
 216
 217         if (INTEL_INFO(dev)->gen >= 4)
 218                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 219         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 220         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 221
 222         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 223 #ifdef CONFIG_PNP
 224         if (mchbar_addr &&
 225             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 226                 return 0;
 227 #endif
 228
 229         /* Get some space for it */
 230         dev_priv->mch_res.name = "i915 MCHBAR";
 231         dev_priv->mch_res.flags = IORESOURCE_MEM;
 232         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 233                                      &dev_priv->mch_res,
 234                                      MCHBAR_SIZE, MCHBAR_SIZE,
 235                                      PCIBIOS_MIN_MEM,
 236                                      0, pcibios_align_resource,
 237                                      dev_priv->bridge_dev);
 238         if (ret) {
 239                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 240                 dev_priv->mch_res.start = 0;
 241                 return ret;
 242         }
 243
 244         if (INTEL_INFO(dev)->gen >= 4)
 245                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 246                                        upper_32_bits(dev_priv->mch_res.start));
 247
 248         pci_write_config_dword(dev_priv->bridge_dev, reg,
 249                                lower_32_bits(dev_priv->mch_res.start));
 250         return 0;
 251 }
 252
 253 /* Setup MCHBAR if possible, return true if we should disable it again */
 254 static void
 255 intel_setup_mchbar(struct drm_device *dev)
 256 {
 257         struct drm_i915_private *dev_priv = dev->dev_private;
 258         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 259         u32 temp;
 260         bool enabled;
 261
 262         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 263                 return;
 264
 265         dev_priv->mchbar_need_disable = false;
 266
 267         if (IS_I915G(dev) || IS_I915GM(dev)) {
 268                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 269                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 270         } else {
 271                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 272                 enabled = temp & 1;
 273         }
 274
 275         /* If it's already enabled, don't have to do anything */
 276         if (enabled)
 277                 return;
 278
 279         if (intel_alloc_mchbar_resource(dev))
 280                 return;
 281
 282         dev_priv->mchbar_need_disable = true;
 283
 284         /* Space is allocated or reserved, so enable it. */
 285         if (IS_I915G(dev) || IS_I915GM(dev)) {
 286                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 287                                        temp | DEVEN_MCHBAR_EN);
 288         } else {
 289                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 290                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 291         }
 292 }
 293
 294 static void
 295 intel_teardown_mchbar(struct drm_device *dev)
 296 {
 297         struct drm_i915_private *dev_priv = dev->dev_private;
 298         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 299         u32 temp;
 300
 301         if (dev_priv->mchbar_need_disable) {
 302                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 303                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 304                         temp &= ~DEVEN_MCHBAR_EN;
 305                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 306                 } else {
 307                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 308                         temp &= ~1;
 309                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 310                 }
 311         }
 312
 313         if (dev_priv->mch_res.start)
 314                 release_resource(&dev_priv->mch_res);
 315 }
 316
 317 /* true = enable decode, false = disable decoder */
 318 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 319 {
 320         struct drm_device *dev = cookie;
 321
 322         intel_modeset_vga_set_state(dev, state);
 323         if (state)
 324                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 325                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 326         else
 327                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 328 }
 329
 330 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 331 {
 332         struct drm_device *dev = pci_get_drvdata(pdev);
 333         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 334
 335         if (state == VGA_SWITCHEROO_ON) {
 336                 pr_info("switched on\n");
 337                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 338                 /* i915 resume handler doesn't set to D0 */
 339                 pci_set_power_state(dev->pdev, PCI_D0);
 340                 i915_resume_switcheroo(dev);
 341                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 342         } else {
 343                 pr_info("switched off\n");
 344                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 345                 i915_suspend_switcheroo(dev, pmm);
 346                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 347         }
 348 }
 349
 350 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 351 {
 352         struct drm_device *dev = pci_get_drvdata(pdev);
 353
 354         /*
 355          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 356          * locking inversion with the driver load path. And the access here is
 357          * completely racy anyway. So don't bother with locking for now.
 358          */
 359         return dev->open_count == 0;
 360 }
 361
 362 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 363         .set_gpu_state = i915_switcheroo_set_state,
 364         .reprobe = NULL,
 365         .can_switch = i915_switcheroo_can_switch,
 366 };
 367
 368 static int i915_load_modeset_init(struct drm_device *dev)
 369 {
 370         struct drm_i915_private *dev_priv = dev->dev_private;
 371         int ret;
 372
 373         ret = intel_bios_init(dev_priv);
 374         if (ret)
 375                 DRM_INFO("failed to find VBIOS tables\n");
 376
 377         /* If we have > 1 VGA cards, then we need to arbitrate access
 378          * to the common VGA resources.
 379          *
 380          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 381          * then we do not take part in VGA arbitration and the
 382          * vga_client_register() fails with -ENODEV.
 383          */
 384         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 385         if (ret && ret != -ENODEV)
 386                 goto out;
 387
 388         intel_register_dsm_handler();
 389
 390         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 391         if (ret)
 392                 goto cleanup_vga_client;
 393
 394         /* Initialise stolen first so that we may reserve preallocated
 395          * objects for the BIOS to KMS transition.
 396          */
 397         ret = i915_gem_init_stolen(dev);
 398         if (ret)
 399                 goto cleanup_vga_switcheroo;
 400
 401         intel_power_domains_init_hw(dev_priv, false);
 402
 403         intel_csr_ucode_init(dev_priv);
 404
 405         ret = intel_irq_install(dev_priv);
 406         if (ret)
 407                 goto cleanup_csr;
 408
 409         intel_setup_gmbus(dev);
 410
 411         /* Important: The output setup functions called by modeset_init need
 412          * working irqs for e.g. gmbus and dp aux transfers. */
 413         intel_modeset_init(dev);
 414
 415         intel_guc_ucode_init(dev);
 416
 417         ret = i915_gem_init(dev);
 418         if (ret)
 419                 goto cleanup_irq;
 420
 421         intel_modeset_gem_init(dev);
 422
 423         /* Always safe in the mode setting case. */
 424         /* FIXME: do pre/post-mode set stuff in core KMS code */
 425         dev->vblank_disable_allowed = true;
 426         if (INTEL_INFO(dev)->num_pipes == 0)
 427                 return 0;
 428
 429         ret = intel_fbdev_init(dev);
 430         if (ret)
 431                 goto cleanup_gem;
 432
 433         /* Only enable hotplug handling once the fbdev is fully set up. */
 434         intel_hpd_init(dev_priv);
 435
 436         /*
 437          * Some ports require correctly set-up hpd registers for detection to
 438          * work properly (leading to ghost connected connector status), e.g. VGA
 439          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 440          * irqs are fully enabled. Now we should scan for the initial config
 441          * only once hotplug handling is enabled, but due to screwed-up locking
 442          * around kms/fbdev init we can't protect the fdbev initial config
 443          * scanning against hotplug events. Hence do this first and ignore the
 444          * tiny window where we will loose hotplug notifactions.
 445          */
 446         intel_fbdev_initial_config_async(dev);
 447
 448         drm_kms_helper_poll_init(dev);
 449
 450         return 0;
 451
 452 cleanup_gem:
 453         mutex_lock(&dev->struct_mutex);
 454         i915_gem_cleanup_ringbuffer(dev);
 455         i915_gem_context_fini(dev);
 456         mutex_unlock(&dev->struct_mutex);
 457 cleanup_irq:
 458         intel_guc_ucode_fini(dev);
 459         drm_irq_uninstall(dev);
 460         intel_teardown_gmbus(dev);
 461 cleanup_csr:
 462         intel_csr_ucode_fini(dev_priv);
 463         i915_gem_cleanup_stolen(dev);
 464 cleanup_vga_switcheroo:
 465         vga_switcheroo_unregister_client(dev->pdev);
 466 cleanup_vga_client:
 467         vga_client_register(dev->pdev, NULL, NULL, NULL);
 468 out:
 469         return ret;
 470 }
 471
 472 #if IS_ENABLED(CONFIG_FB)
 473 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 474 {
 475         struct apertures_struct *ap;
 476         struct pci_dev *pdev = dev_priv->dev->pdev;
 477         bool primary;
 478         int ret;
 479
 480         ap = alloc_apertures(1);
 481         if (!ap)
 482                 return -ENOMEM;
 483
 484         ap->ranges[0].base = dev_priv->gtt.mappable_base;
 485         ap->ranges[0].size = dev_priv->gtt.mappable_end;
 486
 487         primary =
 488                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 489
 490         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 491
 492         kfree(ap);
 493
 494         return ret;
 495 }
 496 #else
 497 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 498 {
 499         return 0;
 500 }
 501 #endif
 502
 503 #if !defined(CONFIG_VGA_CONSOLE)
 504 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 505 {
 506         return 0;
 507 }
 508 #elif !defined(CONFIG_DUMMY_CONSOLE)
 509 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 510 {
 511         return -ENODEV;
 512 }
 513 #else
 514 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 515 {
 516         int ret = 0;
 517
 518         DRM_INFO("Replacing VGA console driver\n");
 519
 520         console_lock();
 521         if (con_is_bound(&vga_con))
 522                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 523         if (ret == 0) {
 524                 ret = do_unregister_con_driver(&vga_con);
 525
 526                 /* Ignore "already unregistered". */
 527                 if (ret == -ENODEV)
 528                         ret = 0;
 529         }
 530         console_unlock();
 531
 532         return ret;
 533 }
 534 #endif
 535
 536 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 537 {
 538         const struct intel_device_info *info = &dev_priv->info;
 539
 540 #define PRINT_S(name) "%s"
 541 #define SEP_EMPTY
 542 #define PRINT_FLAG(name) info->name ? #name "," : ""
 543 #define SEP_COMMA ,
 544         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
 545                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
 546                          info->gen,
 547                          dev_priv->dev->pdev->device,
 548                          dev_priv->dev->pdev->revision,
 549                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
 550 #undef PRINT_S
 551 #undef SEP_EMPTY
 552 #undef PRINT_FLAG
 553 #undef SEP_COMMA
 554 }
 555
 556 static void cherryview_sseu_info_init(struct drm_device *dev)
 557 {
 558         struct drm_i915_private *dev_priv = dev->dev_private;
 559         struct intel_device_info *info;
 560         u32 fuse, eu_dis;
 561
 562         info = (struct intel_device_info *)&dev_priv->info;
 563         fuse = I915_READ(CHV_FUSE_GT);
 564
 565         info->slice_total = 1;
 566
 567         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 568                 info->subslice_per_slice++;
 569                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 570                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
 571                 info->eu_total += 8 - hweight32(eu_dis);
 572         }
 573
 574         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
 575                 info->subslice_per_slice++;
 576                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
 577                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
 578                 info->eu_total += 8 - hweight32(eu_dis);
 579         }
 580
 581         info->subslice_total = info->subslice_per_slice;
 582         /*
 583          * CHV expected to always have a uniform distribution of EU
 584          * across subslices.
 585         */
 586         info->eu_per_subslice = info->subslice_total ?
 587                                 info->eu_total / info->subslice_total :
 588                                 0;
 589         /*
 590          * CHV supports subslice power gating on devices with more than
 591          * one subslice, and supports EU power gating on devices with
 592          * more than one EU pair per subslice.
 593         */
 594         info->has_slice_pg = 0;
 595         info->has_subslice_pg = (info->subslice_total > 1);
 596         info->has_eu_pg = (info->eu_per_subslice > 2);
 597 }
 598
 599 static void gen9_sseu_info_init(struct drm_device *dev)
 600 {
 601         struct drm_i915_private *dev_priv = dev->dev_private;
 602         struct intel_device_info *info;
 603         int s_max = 3, ss_max = 4, eu_max = 8;
 604         int s, ss;
 605         u32 fuse2, s_enable, ss_disable, eu_disable;
 606         u8 eu_mask = 0xff;
 607
 608         info = (struct intel_device_info *)&dev_priv->info;
 609         fuse2 = I915_READ(GEN8_FUSE2);
 610         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
 611                    GEN8_F2_S_ENA_SHIFT;
 612         ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
 613                      GEN9_F2_SS_DIS_SHIFT;
 614
 615         info->slice_total = hweight32(s_enable);
 616         /*
 617          * The subslice disable field is global, i.e. it applies
 618          * to each of the enabled slices.
 619         */
 620         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 621         info->subslice_total = info->slice_total *
 622                                info->subslice_per_slice;
 623
 624         /*
 625          * Iterate through enabled slices and subslices to
 626          * count the total enabled EU.
 627         */
 628         for (s = 0; s < s_max; s++) {
 629                 if (!(s_enable & (0x1 << s)))
 630                         /* skip disabled slice */
 631                         continue;
 632
 633                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
 634                 for (ss = 0; ss < ss_max; ss++) {
 635                         int eu_per_ss;
 636
 637                         if (ss_disable & (0x1 << ss))
 638                                 /* skip disabled subslice */
 639                                 continue;
 640
 641                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
 642                                                       eu_mask);
 643
 644                         /*
 645                          * Record which subslice(s) has(have) 7 EUs. we
 646                          * can tune the hash used to spread work among
 647                          * subslices if they are unbalanced.
 648                          */
 649                         if (eu_per_ss == 7)
 650                                 info->subslice_7eu[s] |= 1 << ss;
 651
 652                         info->eu_total += eu_per_ss;
 653                 }
 654         }
 655
 656         /*
 657          * SKL is expected to always have a uniform distribution
 658          * of EU across subslices with the exception that any one
 659          * EU in any one subslice may be fused off for die
 660          * recovery. BXT is expected to be perfectly uniform in EU
 661          * distribution.
 662         */
 663         info->eu_per_subslice = info->subslice_total ?
 664                                 DIV_ROUND_UP(info->eu_total,
 665                                              info->subslice_total) : 0;
 666         /*
 667          * SKL supports slice power gating on devices with more than
 668          * one slice, and supports EU power gating on devices with
 669          * more than one EU pair per subslice. BXT supports subslice
 670          * power gating on devices with more than one subslice, and
 671          * supports EU power gating on devices with more than one EU
 672          * pair per subslice.
 673         */
 674         info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
 675                                (info->slice_total > 1));
 676         info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
 677         info->has_eu_pg = (info->eu_per_subslice > 2);
 678 }
 679
 680 static void broadwell_sseu_info_init(struct drm_device *dev)
 681 {
 682         struct drm_i915_private *dev_priv = dev->dev_private;
 683         struct intel_device_info *info;
 684         const int s_max = 3, ss_max = 3, eu_max = 8;
 685         int s, ss;
 686         u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
 687
 688         fuse2 = I915_READ(GEN8_FUSE2);
 689         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 690         ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
 691
 692         eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
 693         eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
 694                         ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
 695                          (32 - GEN8_EU_DIS0_S1_SHIFT));
 696         eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
 697                         ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
 698                          (32 - GEN8_EU_DIS1_S2_SHIFT));
 699
 700
 701         info = (struct intel_device_info *)&dev_priv->info;
 702         info->slice_total = hweight32(s_enable);
 703
 704         /*
 705          * The subslice disable field is global, i.e. it applies
 706          * to each of the enabled slices.
 707          */
 708         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 709         info->subslice_total = info->slice_total * info->subslice_per_slice;
 710
 711         /*
 712          * Iterate through enabled slices and subslices to
 713          * count the total enabled EU.
 714          */
 715         for (s = 0; s < s_max; s++) {
 716                 if (!(s_enable & (0x1 << s)))
 717                         /* skip disabled slice */
 718                         continue;
 719
 720                 for (ss = 0; ss < ss_max; ss++) {
 721                         u32 n_disabled;
 722
 723                         if (ss_disable & (0x1 << ss))
 724                                 /* skip disabled subslice */
 725                                 continue;
 726
 727                         n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
 728
 729                         /*
 730                          * Record which subslices have 7 EUs.
 731                          */
 732                         if (eu_max - n_disabled == 7)
 733                                 info->subslice_7eu[s] |= 1 << ss;
 734
 735                         info->eu_total += eu_max - n_disabled;
 736                 }
 737         }
 738
 739         /*
 740          * BDW is expected to always have a uniform distribution of EU across
 741          * subslices with the exception that any one EU in any one subslice may
 742          * be fused off for die recovery.
 743          */
 744         info->eu_per_subslice = info->subslice_total ?
 745                 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
 746
 747         /*
 748          * BDW supports slice power gating on devices with more than
 749          * one slice.
 750          */
 751         info->has_slice_pg = (info->slice_total > 1);
 752         info->has_subslice_pg = 0;
 753         info->has_eu_pg = 0;
 754 }
 755
 756 /*
 757  * Determine various intel_device_info fields at runtime.
 758  *
 759  * Use it when either:
 760  *   - it's judged too laborious to fill n static structures with the limit
 761  *     when a simple if statement does the job,
 762  *   - run-time checks (eg read fuse/strap registers) are needed.
 763  *
 764  * This function needs to be called:
 765  *   - after the MMIO has been setup as we are reading registers,
 766  *   - after the PCH has been detected,
 767  *   - before the first usage of the fields it can tweak.
 768  */
 769 static void intel_device_info_runtime_init(struct drm_device *dev)
 770 {
 771         struct drm_i915_private *dev_priv = dev->dev_private;
 772         struct intel_device_info *info;
 773         enum pipe pipe;
 774
 775         info = (struct intel_device_info *)&dev_priv->info;
 776
 777         /*
 778          * Skylake and Broxton currently don't expose the topmost plane as its
 779          * use is exclusive with the legacy cursor and we only want to expose
 780          * one of those, not both. Until we can safely expose the topmost plane
 781          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 782          * we don't expose the topmost plane at all to prevent ABI breakage
 783          * down the line.
 784          */
 785         if (IS_BROXTON(dev)) {
 786                 info->num_sprites[PIPE_A] = 2;
 787                 info->num_sprites[PIPE_B] = 2;
 788                 info->num_sprites[PIPE_C] = 1;
 789         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 790                 for_each_pipe(dev_priv, pipe)
 791                         info->num_sprites[pipe] = 2;
 792         else
 793                 for_each_pipe(dev_priv, pipe)
 794                         info->num_sprites[pipe] = 1;
 795
 796         if (i915.disable_display) {
 797                 DRM_INFO("Display disabled (module parameter)\n");
 798                 info->num_pipes = 0;
 799         } else if (info->num_pipes > 0 &&
 800                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
 801                    HAS_PCH_SPLIT(dev)) {
 802                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 803                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 804
 805                 /*
 806                  * SFUSE_STRAP is supposed to have a bit signalling the display
 807                  * is fused off. Unfortunately it seems that, at least in
 808                  * certain cases, fused off display means that PCH display
 809                  * reads don't land anywhere. In that case, we read 0s.
 810                  *
 811                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 812                  * should be set when taking over after the firmware.
 813                  */
 814                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 815                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 816                     (dev_priv->pch_type == PCH_CPT &&
 817                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 818                         DRM_INFO("Display fused off, disabling\n");
 819                         info->num_pipes = 0;
 820                 }
 821         }
 822
 823         /* Initialize slice/subslice/EU info */
 824         if (IS_CHERRYVIEW(dev))
 825                 cherryview_sseu_info_init(dev);
 826         else if (IS_BROADWELL(dev))
 827                 broadwell_sseu_info_init(dev);
 828         else if (INTEL_INFO(dev)->gen >= 9)
 829                 gen9_sseu_info_init(dev);
 830
 831         DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
 832         DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
 833         DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
 834         DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
 835         DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
 836         DRM_DEBUG_DRIVER("has slice power gating: %s\n",
 837                          info->has_slice_pg ? "y" : "n");
 838         DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
 839                          info->has_subslice_pg ? "y" : "n");
 840         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
 841                          info->has_eu_pg ? "y" : "n");
 842 }
 843
 844 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 845 {
 846         /*
 847          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 848          * CHV x1 PHY (DP/HDMI D)
 849          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 850          */
 851         if (IS_CHERRYVIEW(dev_priv)) {
 852                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 853                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 854         } else if (IS_VALLEYVIEW(dev_priv)) {
 855                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 856         }
 857 }
 858
 859 /**
 860  * i915_driver_load - setup chip and create an initial config
 861  * @dev: DRM device
 862  * @flags: startup flags
 863  *
 864  * The driver load routine has to do several things:
 865  *   - drive output discovery via intel_modeset_init()
 866  *   - initialize the memory manager
 867  *   - allocate initial config memory
 868  *   - setup the DRM framebuffer with the allocated memory
 869  */
 870 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 871 {
 872         struct drm_i915_private *dev_priv;
 873         struct intel_device_info *info, *device_info;
 874         int ret = 0, mmio_bar, mmio_size;
 875         uint32_t aperture_size;
 876
 877         info = (struct intel_device_info *) flags;
 878
 879         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 880         if (dev_priv == NULL)
 881                 return -ENOMEM;
 882
 883         dev->dev_private = dev_priv;
 884         dev_priv->dev = dev;
 885
 886         /* Setup the write-once "constant" device info */
 887         device_info = (struct intel_device_info *)&dev_priv->info;
 888         memcpy(device_info, info, sizeof(dev_priv->info));
 889         device_info->device_id = dev->pdev->device;
 890
 891         spin_lock_init(&dev_priv->irq_lock);
 892         spin_lock_init(&dev_priv->gpu_error.lock);
 893         mutex_init(&dev_priv->backlight_lock);
 894         spin_lock_init(&dev_priv->uncore.lock);
 895         spin_lock_init(&dev_priv->mm.object_stat_lock);
 896         spin_lock_init(&dev_priv->mmio_flip_lock);
 897         mutex_init(&dev_priv->sb_lock);
 898         mutex_init(&dev_priv->modeset_restore_lock);
 899         mutex_init(&dev_priv->av_mutex);
 900
 901         intel_pm_setup(dev);
 902
 903         intel_runtime_pm_get(dev_priv);
 904
 905         intel_display_crc_init(dev);
 906
 907         i915_dump_device_info(dev_priv);
 908
 909         /* Not all pre-production machines fall into this category, only the
 910          * very first ones. Almost everything should work, except for maybe
 911          * suspend/resume. And we don't implement workarounds that affect only
 912          * pre-production machines. */
 913         if (IS_HSW_EARLY_SDV(dev))
 914                 DRM_INFO("This is an early pre-production Haswell machine. "
 915                          "It may not be fully functional.\n");
 916
 917         if (i915_get_bridge_dev(dev)) {
 918                 ret = -EIO;
 919                 goto out_runtime_pm_put;
 920         }
 921
 922         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 923         /* Before gen4, the registers and the GTT are behind different BARs.
 924          * However, from gen4 onwards, the registers and the GTT are shared
 925          * in the same BAR, so we want to restrict this ioremap from
 926          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 927          * the register BAR remains the same size for all the earlier
 928          * generations up to Ironlake.
 929          */
 930         if (info->gen < 5)
 931                 mmio_size = 512*1024;
 932         else
 933                 mmio_size = 2*1024*1024;
 934
 935         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 936         if (!dev_priv->regs) {
 937                 DRM_ERROR("failed to map registers\n");
 938                 ret = -EIO;
 939                 goto put_bridge;
 940         }
 941
 942         /* This must be called before any calls to HAS_PCH_* */
 943         intel_detect_pch(dev);
 944
 945         intel_uncore_init(dev);
 946
 947         ret = i915_gem_gtt_init(dev);
 948         if (ret)
 949                 goto out_uncore_fini;
 950
 951         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
 952          * otherwise the vga fbdev driver falls over. */
 953         ret = i915_kick_out_firmware_fb(dev_priv);
 954         if (ret) {
 955                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
 956                 goto out_gtt;
 957         }
 958
 959         ret = i915_kick_out_vgacon(dev_priv);
 960         if (ret) {
 961                 DRM_ERROR("failed to remove conflicting VGA console\n");
 962                 goto out_gtt;
 963         }
 964
 965         pci_set_master(dev->pdev);
 966
 967         /* overlay on gen2 is broken and can't address above 1G */
 968         if (IS_GEN2(dev))
 969                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
 970
 971         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
 972          * using 32bit addressing, overwriting memory if HWS is located
 973          * above 4GB.
 974          *
 975          * The documentation also mentions an issue with undefined
 976          * behaviour if any general state is accessed within a page above 4GB,
 977          * which also needs to be handled carefully.
 978          */
 979         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
 980                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
 981
 982         aperture_size = dev_priv->gtt.mappable_end;
 983
 984         dev_priv->gtt.mappable =
 985                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
 986                                      aperture_size);
 987         if (dev_priv->gtt.mappable == NULL) {
 988                 ret = -EIO;
 989                 goto out_gtt;
 990         }
 991
 992         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
 993                                               aperture_size);
 994
 995         /* The i915 workqueue is primarily used for batched retirement of
 996          * requests (and thus managing bo) once the task has been completed
 997          * by the GPU. i915_gem_retire_requests() is called directly when we
 998          * need high-priority retirement, such as waiting for an explicit
 999          * bo.
1000          *
1001          * It is also used for periodic low-priority events, such as
1002          * idle-timers and recording error state.
1003          *
1004          * All tasks on the workqueue are expected to acquire the dev mutex
1005          * so there is no point in running more than one instance of the
1006          * workqueue at any time.  Use an ordered one.
1007          */
1008         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1009         if (dev_priv->wq == NULL) {
1010                 DRM_ERROR("Failed to create our workqueue.\n");
1011                 ret = -ENOMEM;
1012                 goto out_mtrrfree;
1013         }
1014
1015         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1016         if (dev_priv->hotplug.dp_wq == NULL) {
1017                 DRM_ERROR("Failed to create our dp workqueue.\n");
1018                 ret = -ENOMEM;
1019                 goto out_freewq;
1020         }
1021
1022         dev_priv->gpu_error.hangcheck_wq =
1023                 alloc_ordered_workqueue("i915-hangcheck", 0);
1024         if (dev_priv->gpu_error.hangcheck_wq == NULL) {
1025                 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
1026                 ret = -ENOMEM;
1027                 goto out_freedpwq;
1028         }
1029
1030         intel_irq_init(dev_priv);
1031         intel_uncore_sanitize(dev);
1032
1033         /* Try to make sure MCHBAR is enabled before poking at it */
1034         intel_setup_mchbar(dev);
1035         intel_opregion_setup(dev);
1036
1037         i915_gem_load_init(dev);
1038         i915_gem_shrinker_init(dev_priv);
1039
1040         /* On the 945G/GM, the chipset reports the MSI capability on the
1041          * integrated graphics even though the support isn't actually there
1042          * according to the published specs.  It doesn't appear to function
1043          * correctly in testing on 945G.
1044          * This may be a side effect of MSI having been made available for PEG
1045          * and the registers being closely associated.
1046          *
1047          * According to chipset errata, on the 965GM, MSI interrupts may
1048          * be lost or delayed, but we use them anyways to avoid
1049          * stuck interrupts on some machines.
1050          */
1051         if (!IS_I945G(dev) && !IS_I945GM(dev))
1052                 pci_enable_msi(dev->pdev);
1053
1054         intel_device_info_runtime_init(dev);
1055
1056         intel_init_dpio(dev_priv);
1057
1058         if (INTEL_INFO(dev)->num_pipes) {
1059                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1060                 if (ret)
1061                         goto out_gem_unload;
1062         }
1063
1064         intel_power_domains_init(dev_priv);
1065
1066         ret = i915_load_modeset_init(dev);
1067         if (ret < 0) {
1068                 DRM_ERROR("failed to init modeset\n");
1069                 goto out_power_well;
1070         }
1071
1072         /*
1073          * Notify a valid surface after modesetting,
1074          * when running inside a VM.
1075          */
1076         if (intel_vgpu_active(dev))
1077                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1078
1079         i915_setup_sysfs(dev);
1080
1081         if (INTEL_INFO(dev)->num_pipes) {
1082                 /* Must be done after probing outputs */
1083                 intel_opregion_init(dev);
1084                 acpi_video_register();
1085         }
1086
1087         if (IS_GEN5(dev))
1088                 intel_gpu_ips_init(dev_priv);
1089
1090         intel_runtime_pm_enable(dev_priv);
1091
1092         i915_audio_component_init(dev_priv);
1093
1094         intel_runtime_pm_put(dev_priv);
1095
1096         return 0;
1097
1098 out_power_well:
1099         intel_power_domains_fini(dev_priv);
1100         drm_vblank_cleanup(dev);
1101 out_gem_unload:
1102         i915_gem_shrinker_cleanup(dev_priv);
1103
1104         if (dev->pdev->msi_enabled)
1105                 pci_disable_msi(dev->pdev);
1106
1107         intel_teardown_mchbar(dev);
1108         pm_qos_remove_request(&dev_priv->pm_qos);
1109         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1110 out_freedpwq:
1111         destroy_workqueue(dev_priv->hotplug.dp_wq);
1112 out_freewq:
1113         destroy_workqueue(dev_priv->wq);
1114 out_mtrrfree:
1115         arch_phys_wc_del(dev_priv->gtt.mtrr);
1116         io_mapping_free(dev_priv->gtt.mappable);
1117 out_gtt:
1118         i915_global_gtt_cleanup(dev);
1119 out_uncore_fini:
1120         intel_uncore_fini(dev);
1121         pci_iounmap(dev->pdev, dev_priv->regs);
1122 put_bridge:
1123         pci_dev_put(dev_priv->bridge_dev);
1124         i915_gem_load_cleanup(dev);
1125 out_runtime_pm_put:
1126         intel_runtime_pm_put(dev_priv);
1127
1128         kfree(dev_priv);
1129         return ret;
1130 }
1131
1132 int i915_driver_unload(struct drm_device *dev)
1133 {
1134         struct drm_i915_private *dev_priv = dev->dev_private;
1135         int ret;
1136
1137         intel_fbdev_fini(dev);
1138
1139         i915_audio_component_cleanup(dev_priv);
1140
1141         ret = i915_gem_suspend(dev);
1142         if (ret) {
1143                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1144                 return ret;
1145         }
1146
1147         intel_power_domains_fini(dev_priv);
1148
1149         intel_gpu_ips_teardown();
1150
1151         i915_teardown_sysfs(dev);
1152
1153         i915_gem_shrinker_cleanup(dev_priv);
1154
1155         io_mapping_free(dev_priv->gtt.mappable);
1156         arch_phys_wc_del(dev_priv->gtt.mtrr);
1157
1158         acpi_video_unregister();
1159
1160         drm_vblank_cleanup(dev);
1161
1162         intel_modeset_cleanup(dev);
1163
1164         /*
1165          * free the memory space allocated for the child device
1166          * config parsed from VBT
1167          */
1168         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1169                 kfree(dev_priv->vbt.child_dev);
1170                 dev_priv->vbt.child_dev = NULL;
1171                 dev_priv->vbt.child_dev_num = 0;
1172         }
1173         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1174         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1175         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1176         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1177
1178         vga_switcheroo_unregister_client(dev->pdev);
1179         vga_client_register(dev->pdev, NULL, NULL, NULL);
1180
1181         intel_csr_ucode_fini(dev_priv);
1182
1183         /* Free error state after interrupts are fully disabled. */
1184         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1185         i915_destroy_error_state(dev);
1186
1187         if (dev->pdev->msi_enabled)
1188                 pci_disable_msi(dev->pdev);
1189
1190         intel_opregion_fini(dev);
1191
1192         /* Flush any outstanding unpin_work. */
1193         flush_workqueue(dev_priv->wq);
1194
1195         intel_guc_ucode_fini(dev);
1196         mutex_lock(&dev->struct_mutex);
1197         i915_gem_cleanup_ringbuffer(dev);
1198         i915_gem_context_fini(dev);
1199         mutex_unlock(&dev->struct_mutex);
1200         intel_fbc_cleanup_cfb(dev_priv);
1201         i915_gem_cleanup_stolen(dev);
1202
1203         intel_teardown_mchbar(dev);
1204
1205         destroy_workqueue(dev_priv->hotplug.dp_wq);
1206         destroy_workqueue(dev_priv->wq);
1207         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1208         pm_qos_remove_request(&dev_priv->pm_qos);
1209
1210         i915_global_gtt_cleanup(dev);
1211
1212         intel_uncore_fini(dev);
1213         if (dev_priv->regs != NULL)
1214                 pci_iounmap(dev->pdev, dev_priv->regs);
1215
1216         i915_gem_load_cleanup(dev);
1217         pci_dev_put(dev_priv->bridge_dev);
1218         kfree(dev_priv);
1219
1220         return 0;
1221 }
1222
1223 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1224 {
1225         int ret;
1226
1227         ret = i915_gem_open(dev, file);
1228         if (ret)
1229                 return ret;
1230
1231         return 0;
1232 }
1233
1234 /**
1235  * i915_driver_lastclose - clean up after all DRM clients have exited
1236  * @dev: DRM device
1237  *
1238  * Take care of cleaning up after all DRM clients have exited.  In the
1239  * mode setting case, we want to restore the kernel's initial mode (just
1240  * in case the last client left us in a bad state).
1241  *
1242  * Additionally, in the non-mode setting case, we'll tear down the GTT
1243  * and DMA structures, since the kernel won't be using them, and clea
1244  * up any GEM state.
1245  */
1246 void i915_driver_lastclose(struct drm_device *dev)
1247 {
1248         intel_fbdev_restore_mode(dev);
1249         vga_switcheroo_process_delayed_switch();
1250 }
1251
1252 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1253 {
1254         mutex_lock(&dev->struct_mutex);
1255         i915_gem_context_close(dev, file);
1256         i915_gem_release(dev, file);
1257         mutex_unlock(&dev->struct_mutex);
1258
1259         intel_modeset_preclose(dev, file);
1260 }
1261
1262 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1263 {
1264         struct drm_i915_file_private *file_priv = file->driver_priv;
1265
1266         kfree(file_priv);
1267 }
1268
1269 static int
1270 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1271                           struct drm_file *file)
1272 {
1273         return -ENODEV;
1274 }
1275
1276 const struct drm_ioctl_desc i915_ioctls[] = {
1277         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1278         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1279         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1280         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1281         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1282         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1283         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1284         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1285         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1286         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1287         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1288         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1289         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1290         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1291         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1292         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1293         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1294         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1295         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1296         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
1297         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1298         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1299         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1300         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1301         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1302         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1303         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1304         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1305         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1306         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1307         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1308         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1309         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
1310         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1311         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1312         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
1313         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
1314         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1315         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1316         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1317         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
1318         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
1319         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
1320         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
1321         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1322         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1323         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1324         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1325         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_RENDER_ALLOW),
1326         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1327         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1328         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1329 };
1330
1331 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);