drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include "drm_crtc_helper.h"
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 0;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect [default], 1=lid open, "
  54                 "-1=lid closed)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 static struct drm_driver driver;
 122 extern int intel_agp_enabled;
 123
 124 #define INTEL_VGA_DEVICE(id, info) {            \
 125         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 126         .class_mask = 0xff0000,                 \
 127         .vendor = 0x8086,                       \
 128         .device = id,                           \
 129         .subvendor = PCI_ANY_ID,                \
 130         .subdevice = PCI_ANY_ID,                \
 131         .driver_data = (unsigned long) info }
 132
 133 static const struct intel_device_info intel_i830_info = {
 134         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 135         .has_overlay = 1, .overlay_needs_physical = 1,
 136 };
 137
 138 static const struct intel_device_info intel_845g_info = {
 139         .gen = 2,
 140         .has_overlay = 1, .overlay_needs_physical = 1,
 141 };
 142
 143 static const struct intel_device_info intel_i85x_info = {
 144         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 145         .cursor_needs_physical = 1,
 146         .has_overlay = 1, .overlay_needs_physical = 1,
 147 };
 148
 149 static const struct intel_device_info intel_i865g_info = {
 150         .gen = 2,
 151         .has_overlay = 1, .overlay_needs_physical = 1,
 152 };
 153
 154 static const struct intel_device_info intel_i915g_info = {
 155         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 156         .has_overlay = 1, .overlay_needs_physical = 1,
 157 };
 158 static const struct intel_device_info intel_i915gm_info = {
 159         .gen = 3, .is_mobile = 1,
 160         .cursor_needs_physical = 1,
 161         .has_overlay = 1, .overlay_needs_physical = 1,
 162         .supports_tv = 1,
 163 };
 164 static const struct intel_device_info intel_i945g_info = {
 165         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 166         .has_overlay = 1, .overlay_needs_physical = 1,
 167 };
 168 static const struct intel_device_info intel_i945gm_info = {
 169         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 170         .has_hotplug = 1, .cursor_needs_physical = 1,
 171         .has_overlay = 1, .overlay_needs_physical = 1,
 172         .supports_tv = 1,
 173 };
 174
 175 static const struct intel_device_info intel_i965g_info = {
 176         .gen = 4, .is_broadwater = 1,
 177         .has_hotplug = 1,
 178         .has_overlay = 1,
 179 };
 180
 181 static const struct intel_device_info intel_i965gm_info = {
 182         .gen = 4, .is_crestline = 1,
 183         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         .supports_tv = 1,
 186 };
 187
 188 static const struct intel_device_info intel_g33_info = {
 189         .gen = 3, .is_g33 = 1,
 190         .need_gfx_hws = 1, .has_hotplug = 1,
 191         .has_overlay = 1,
 192 };
 193
 194 static const struct intel_device_info intel_g45_info = {
 195         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 196         .has_pipe_cxsr = 1, .has_hotplug = 1,
 197         .has_bsd_ring = 1,
 198 };
 199
 200 static const struct intel_device_info intel_gm45_info = {
 201         .gen = 4, .is_g4x = 1,
 202         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 203         .has_pipe_cxsr = 1, .has_hotplug = 1,
 204         .supports_tv = 1,
 205         .has_bsd_ring = 1,
 206 };
 207
 208 static const struct intel_device_info intel_pineview_info = {
 209         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 210         .need_gfx_hws = 1, .has_hotplug = 1,
 211         .has_overlay = 1,
 212 };
 213
 214 static const struct intel_device_info intel_ironlake_d_info = {
 215         .gen = 5,
 216         .need_gfx_hws = 1, .has_hotplug = 1,
 217         .has_bsd_ring = 1,
 218         .has_pch_split = 1,
 219 };
 220
 221 static const struct intel_device_info intel_ironlake_m_info = {
 222         .gen = 5, .is_mobile = 1,
 223         .need_gfx_hws = 1, .has_hotplug = 1,
 224         .has_fbc = 1,
 225         .has_bsd_ring = 1,
 226         .has_pch_split = 1,
 227 };
 228
 229 static const struct intel_device_info intel_sandybridge_d_info = {
 230         .gen = 6,
 231         .need_gfx_hws = 1, .has_hotplug = 1,
 232         .has_bsd_ring = 1,
 233         .has_blt_ring = 1,
 234         .has_llc = 1,
 235         .has_pch_split = 1,
 236 };
 237
 238 static const struct intel_device_info intel_sandybridge_m_info = {
 239         .gen = 6, .is_mobile = 1,
 240         .need_gfx_hws = 1, .has_hotplug = 1,
 241         .has_fbc = 1,
 242         .has_bsd_ring = 1,
 243         .has_blt_ring = 1,
 244         .has_llc = 1,
 245         .has_pch_split = 1,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_d_info = {
 249         .is_ivybridge = 1, .gen = 7,
 250         .need_gfx_hws = 1, .has_hotplug = 1,
 251         .has_bsd_ring = 1,
 252         .has_blt_ring = 1,
 253         .has_llc = 1,
 254         .has_pch_split = 1,
 255 };
 256
 257 static const struct intel_device_info intel_ivybridge_m_info = {
 258         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 259         .need_gfx_hws = 1, .has_hotplug = 1,
 260         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 261         .has_bsd_ring = 1,
 262         .has_blt_ring = 1,
 263         .has_llc = 1,
 264         .has_pch_split = 1,
 265 };
 266
 267 static const struct intel_device_info intel_valleyview_m_info = {
 268         .gen = 7, .is_mobile = 1,
 269         .need_gfx_hws = 1, .has_hotplug = 1,
 270         .has_fbc = 0,
 271         .has_bsd_ring = 1,
 272         .has_blt_ring = 1,
 273         .is_valleyview = 1,
 274 };
 275
 276 static const struct intel_device_info intel_valleyview_d_info = {
 277         .gen = 7,
 278         .need_gfx_hws = 1, .has_hotplug = 1,
 279         .has_fbc = 0,
 280         .has_bsd_ring = 1,
 281         .has_blt_ring = 1,
 282         .is_valleyview = 1,
 283 };
 284
 285 static const struct intel_device_info intel_haswell_d_info = {
 286         .is_haswell = 1, .gen = 7,
 287         .need_gfx_hws = 1, .has_hotplug = 1,
 288         .has_bsd_ring = 1,
 289         .has_blt_ring = 1,
 290         .has_llc = 1,
 291         .has_pch_split = 1,
 292 };
 293
 294 static const struct intel_device_info intel_haswell_m_info = {
 295         .is_haswell = 1, .gen = 7, .is_mobile = 1,
 296         .need_gfx_hws = 1, .has_hotplug = 1,
 297         .has_bsd_ring = 1,
 298         .has_blt_ring = 1,
 299         .has_llc = 1,
 300         .has_pch_split = 1,
 301 };
 302
 303 static const struct pci_device_id pciidlist[] = {               /* aka */
 304         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 305         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 306         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 307         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 308         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 309         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 310         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 311         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 312         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 313         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 314         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 315         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 316         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 317         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 318         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 319         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 320         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 321         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 322         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 323         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 324         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 325         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 326         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 327         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 328         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 329         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 330         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 331         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 332         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 333         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 334         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 335         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 336         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 337         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 338         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 339         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 340         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 341         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 342         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 343         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 344         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 345         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 346         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 347         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 348         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 349         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 350         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 351         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 352         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 353         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 354         INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
 355         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 356         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 357         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 358         {0, 0, 0}
 359 };
 360
 361 #if defined(CONFIG_DRM_I915_KMS)
 362 MODULE_DEVICE_TABLE(pci, pciidlist);
 363 #endif
 364
 365 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 366 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 367 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 368 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 369 #define INTEL_PCH_LPT_DEVICE_ID_TYPE    0x8c00
 370
 371 void intel_detect_pch(struct drm_device *dev)
 372 {
 373         struct drm_i915_private *dev_priv = dev->dev_private;
 374         struct pci_dev *pch;
 375
 376         /*
 377          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 378          * make graphics device passthrough work easy for VMM, that only
 379          * need to expose ISA bridge to let driver know the real hardware
 380          * underneath. This is a requirement from virtualization team.
 381          */
 382         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 383         if (pch) {
 384                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 385                         int id;
 386                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 387
 388                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 389                                 dev_priv->pch_type = PCH_IBX;
 390                                 dev_priv->num_pch_pll = 2;
 391                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 392                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 393                                 dev_priv->pch_type = PCH_CPT;
 394                                 dev_priv->num_pch_pll = 2;
 395                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 396                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 397                                 /* PantherPoint is CPT compatible */
 398                                 dev_priv->pch_type = PCH_CPT;
 399                                 dev_priv->num_pch_pll = 2;
 400                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 401                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 402                                 dev_priv->pch_type = PCH_LPT;
 403                                 dev_priv->num_pch_pll = 0;
 404                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 405                         }
 406                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 407                 }
 408                 pci_dev_put(pch);
 409         }
 410 }
 411
 412 bool i915_semaphore_is_enabled(struct drm_device *dev)
 413 {
 414         if (INTEL_INFO(dev)->gen < 6)
 415                 return 0;
 416
 417         if (i915_semaphores >= 0)
 418                 return i915_semaphores;
 419
 420 #ifdef CONFIG_INTEL_IOMMU
 421         /* Enable semaphores on SNB when IO remapping is off */
 422         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 423                 return false;
 424 #endif
 425
 426         return 1;
 427 }
 428
 429 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 430 {
 431         int count;
 432
 433         count = 0;
 434         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 435                 udelay(10);
 436
 437         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 438         POSTING_READ(FORCEWAKE);
 439
 440         count = 0;
 441         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 442                 udelay(10);
 443 }
 444
 445 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 446 {
 447         int count;
 448
 449         count = 0;
 450         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
 451                 udelay(10);
 452
 453         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
 454         POSTING_READ(FORCEWAKE_MT);
 455
 456         count = 0;
 457         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
 458                 udelay(10);
 459 }
 460
 461 /*
 462  * Generally this is called implicitly by the register read function. However,
 463  * if some sequence requires the GT to not power down then this function should
 464  * be called at the beginning of the sequence followed by a call to
 465  * gen6_gt_force_wake_put() at the end of the sequence.
 466  */
 467 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 468 {
 469         unsigned long irqflags;
 470
 471         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 472         if (dev_priv->forcewake_count++ == 0)
 473                 dev_priv->display.force_wake_get(dev_priv);
 474         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 475 }
 476
 477 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 478 {
 479         u32 gtfifodbg;
 480         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
 481         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
 482              "MMIO read or write has been dropped %x\n", gtfifodbg))
 483                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
 484 }
 485
 486 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 487 {
 488         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 489         /* The below doubles as a POSTING_READ */
 490         gen6_gt_check_fifodbg(dev_priv);
 491 }
 492
 493 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 494 {
 495         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
 496         /* The below doubles as a POSTING_READ */
 497         gen6_gt_check_fifodbg(dev_priv);
 498 }
 499
 500 /*
 501  * see gen6_gt_force_wake_get()
 502  */
 503 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 504 {
 505         unsigned long irqflags;
 506
 507         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 508         if (--dev_priv->forcewake_count == 0)
 509                 dev_priv->display.force_wake_put(dev_priv);
 510         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 511 }
 512
 513 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 514 {
 515         int ret = 0;
 516
 517         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 518                 int loop = 500;
 519                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 520                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 521                         udelay(10);
 522                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 523                 }
 524                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 525                         ++ret;
 526                 dev_priv->gt_fifo_count = fifo;
 527         }
 528         dev_priv->gt_fifo_count--;
 529
 530         return ret;
 531 }
 532
 533 void vlv_force_wake_get(struct drm_i915_private *dev_priv)
 534 {
 535         int count;
 536
 537         count = 0;
 538
 539         /* Already awake? */
 540         if ((I915_READ(0x130094) & 0xa1) == 0xa1)
 541                 return;
 542
 543         I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
 544         POSTING_READ(FORCEWAKE_VLV);
 545
 546         count = 0;
 547         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
 548                 udelay(10);
 549 }
 550
 551 void vlv_force_wake_put(struct drm_i915_private *dev_priv)
 552 {
 553         I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
 554         /* FIXME: confirm VLV behavior with Punit folks */
 555         POSTING_READ(FORCEWAKE_VLV);
 556 }
 557
 558 static int i915_drm_freeze(struct drm_device *dev)
 559 {
 560         struct drm_i915_private *dev_priv = dev->dev_private;
 561
 562         drm_kms_helper_poll_disable(dev);
 563
 564         pci_save_state(dev->pdev);
 565
 566         /* If KMS is active, we do the leavevt stuff here */
 567         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 568                 int error = i915_gem_idle(dev);
 569                 if (error) {
 570                         dev_err(&dev->pdev->dev,
 571                                 "GEM idle failed, resume might fail\n");
 572                         return error;
 573                 }
 574                 drm_irq_uninstall(dev);
 575         }
 576
 577         i915_save_state(dev);
 578
 579         intel_opregion_fini(dev);
 580
 581         /* Modeset on resume, not lid events */
 582         dev_priv->modeset_on_lid = 0;
 583
 584         console_lock();
 585         intel_fbdev_set_suspend(dev, 1);
 586         console_unlock();
 587
 588         return 0;
 589 }
 590
 591 int i915_suspend(struct drm_device *dev, pm_message_t state)
 592 {
 593         int error;
 594
 595         if (!dev || !dev->dev_private) {
 596                 DRM_ERROR("dev: %p\n", dev);
 597                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 598                 return -ENODEV;
 599         }
 600
 601         if (state.event == PM_EVENT_PRETHAW)
 602                 return 0;
 603
 604
 605         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 606                 return 0;
 607
 608         error = i915_drm_freeze(dev);
 609         if (error)
 610                 return error;
 611
 612         if (state.event == PM_EVENT_SUSPEND) {
 613                 /* Shut down the device */
 614                 pci_disable_device(dev->pdev);
 615                 pci_set_power_state(dev->pdev, PCI_D3hot);
 616         }
 617
 618         return 0;
 619 }
 620
 621 static int i915_drm_thaw(struct drm_device *dev)
 622 {
 623         struct drm_i915_private *dev_priv = dev->dev_private;
 624         int error = 0;
 625
 626         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 627                 mutex_lock(&dev->struct_mutex);
 628                 i915_gem_restore_gtt_mappings(dev);
 629                 mutex_unlock(&dev->struct_mutex);
 630         }
 631
 632         i915_restore_state(dev);
 633         intel_opregion_setup(dev);
 634
 635         /* KMS EnterVT equivalent */
 636         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 637                 if (HAS_PCH_SPLIT(dev))
 638                         ironlake_init_pch_refclk(dev);
 639
 640                 mutex_lock(&dev->struct_mutex);
 641                 dev_priv->mm.suspended = 0;
 642
 643                 error = i915_gem_init_hw(dev);
 644                 mutex_unlock(&dev->struct_mutex);
 645
 646                 intel_modeset_init_hw(dev);
 647                 drm_mode_config_reset(dev);
 648                 drm_irq_install(dev);
 649
 650                 /* Resume the modeset for every activated CRTC */
 651                 mutex_lock(&dev->mode_config.mutex);
 652                 drm_helper_resume_force_mode(dev);
 653                 mutex_unlock(&dev->mode_config.mutex);
 654         }
 655
 656         intel_opregion_init(dev);
 657
 658         dev_priv->modeset_on_lid = 0;
 659
 660         console_lock();
 661         intel_fbdev_set_suspend(dev, 0);
 662         console_unlock();
 663         return error;
 664 }
 665
 666 int i915_resume(struct drm_device *dev)
 667 {
 668         int ret;
 669
 670         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 671                 return 0;
 672
 673         if (pci_enable_device(dev->pdev))
 674                 return -EIO;
 675
 676         pci_set_master(dev->pdev);
 677
 678         ret = i915_drm_thaw(dev);
 679         if (ret)
 680                 return ret;
 681
 682         drm_kms_helper_poll_enable(dev);
 683         return 0;
 684 }
 685
 686 static int i8xx_do_reset(struct drm_device *dev)
 687 {
 688         struct drm_i915_private *dev_priv = dev->dev_private;
 689
 690         if (IS_I85X(dev))
 691                 return -ENODEV;
 692
 693         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 694         POSTING_READ(D_STATE);
 695
 696         if (IS_I830(dev) || IS_845G(dev)) {
 697                 I915_WRITE(DEBUG_RESET_I830,
 698                            DEBUG_RESET_DISPLAY |
 699                            DEBUG_RESET_RENDER |
 700                            DEBUG_RESET_FULL);
 701                 POSTING_READ(DEBUG_RESET_I830);
 702                 msleep(1);
 703
 704                 I915_WRITE(DEBUG_RESET_I830, 0);
 705                 POSTING_READ(DEBUG_RESET_I830);
 706         }
 707
 708         msleep(1);
 709
 710         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 711         POSTING_READ(D_STATE);
 712
 713         return 0;
 714 }
 715
 716 static int i965_reset_complete(struct drm_device *dev)
 717 {
 718         u8 gdrst;
 719         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 720         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 721 }
 722
 723 static int i965_do_reset(struct drm_device *dev)
 724 {
 725         int ret;
 726         u8 gdrst;
 727
 728         /*
 729          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 730          * well as the reset bit (GR/bit 0).  Setting the GR bit
 731          * triggers the reset; when done, the hardware will clear it.
 732          */
 733         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 734         pci_write_config_byte(dev->pdev, I965_GDRST,
 735                               gdrst | GRDOM_RENDER |
 736                               GRDOM_RESET_ENABLE);
 737         ret =  wait_for(i965_reset_complete(dev), 500);
 738         if (ret)
 739                 return ret;
 740
 741         /* We can't reset render&media without also resetting display ... */
 742         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 743         pci_write_config_byte(dev->pdev, I965_GDRST,
 744                               gdrst | GRDOM_MEDIA |
 745                               GRDOM_RESET_ENABLE);
 746
 747         return wait_for(i965_reset_complete(dev), 500);
 748 }
 749
 750 static int ironlake_do_reset(struct drm_device *dev)
 751 {
 752         struct drm_i915_private *dev_priv = dev->dev_private;
 753         u32 gdrst;
 754         int ret;
 755
 756         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 757         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 758                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 759         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 760         if (ret)
 761                 return ret;
 762
 763         /* We can't reset render&media without also resetting display ... */
 764         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 765         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 766                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 767         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 768 }
 769
 770 static int gen6_do_reset(struct drm_device *dev)
 771 {
 772         struct drm_i915_private *dev_priv = dev->dev_private;
 773         int     ret;
 774         unsigned long irqflags;
 775
 776         /* Hold gt_lock across reset to prevent any register access
 777          * with forcewake not set correctly
 778          */
 779         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 780
 781         /* Reset the chip */
 782
 783         /* GEN6_GDRST is not in the gt power well, no need to check
 784          * for fifo space for the write or forcewake the chip for
 785          * the read
 786          */
 787         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 788
 789         /* Spin waiting for the device to ack the reset request */
 790         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 791
 792         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 793         if (dev_priv->forcewake_count)
 794                 dev_priv->display.force_wake_get(dev_priv);
 795         else
 796                 dev_priv->display.force_wake_put(dev_priv);
 797
 798         /* Restore fifo count */
 799         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 800
 801         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 802         return ret;
 803 }
 804
 805 int intel_gpu_reset(struct drm_device *dev)
 806 {
 807         struct drm_i915_private *dev_priv = dev->dev_private;
 808         int ret = -ENODEV;
 809
 810         switch (INTEL_INFO(dev)->gen) {
 811         case 7:
 812         case 6:
 813                 ret = gen6_do_reset(dev);
 814                 break;
 815         case 5:
 816                 ret = ironlake_do_reset(dev);
 817                 break;
 818         case 4:
 819                 ret = i965_do_reset(dev);
 820                 break;
 821         case 2:
 822                 ret = i8xx_do_reset(dev);
 823                 break;
 824         }
 825
 826         /* Also reset the gpu hangman. */
 827         if (dev_priv->stop_rings) {
 828                 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
 829                 dev_priv->stop_rings = 0;
 830                 if (ret == -ENODEV) {
 831                         DRM_ERROR("Reset not implemented, but ignoring "
 832                                   "error for simulated gpu hangs\n");
 833                         ret = 0;
 834                 }
 835         }
 836
 837         return ret;
 838 }
 839
 840 /**
 841  * i915_reset - reset chip after a hang
 842  * @dev: drm device to reset
 843  *
 844  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 845  * reset or otherwise an error code.
 846  *
 847  * Procedure is fairly simple:
 848  *   - reset the chip using the reset reg
 849  *   - re-init context state
 850  *   - re-init hardware status page
 851  *   - re-init ring buffer
 852  *   - re-init interrupt state
 853  *   - re-init display
 854  */
 855 int i915_reset(struct drm_device *dev)
 856 {
 857         drm_i915_private_t *dev_priv = dev->dev_private;
 858         int ret;
 859
 860         if (!i915_try_reset)
 861                 return 0;
 862
 863         if (!mutex_trylock(&dev->struct_mutex))
 864                 return -EBUSY;
 865
 866         i915_gem_reset(dev);
 867
 868         ret = -ENODEV;
 869         if (get_seconds() - dev_priv->last_gpu_reset < 5)
 870                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 871         else
 872                 ret = intel_gpu_reset(dev);
 873
 874         dev_priv->last_gpu_reset = get_seconds();
 875         if (ret) {
 876                 DRM_ERROR("Failed to reset chip.\n");
 877                 mutex_unlock(&dev->struct_mutex);
 878                 return ret;
 879         }
 880
 881         /* Ok, now get things going again... */
 882
 883         /*
 884          * Everything depends on having the GTT running, so we need to start
 885          * there.  Fortunately we don't need to do this unless we reset the
 886          * chip at a PCI level.
 887          *
 888          * Next we need to restore the context, but we don't use those
 889          * yet either...
 890          *
 891          * Ring buffer needs to be re-initialized in the KMS case, or if X
 892          * was running at the time of the reset (i.e. we weren't VT
 893          * switched away).
 894          */
 895         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 896                         !dev_priv->mm.suspended) {
 897                 struct intel_ring_buffer *ring;
 898                 int i;
 899
 900                 dev_priv->mm.suspended = 0;
 901
 902                 i915_gem_init_swizzling(dev);
 903
 904                 for_each_ring(ring, dev_priv, i)
 905                         ring->init(ring);
 906
 907                 i915_gem_context_init(dev);
 908                 i915_gem_init_ppgtt(dev);
 909
 910                 /*
 911                  * It would make sense to re-init all the other hw state, at
 912                  * least the rps/rc6/emon init done within modeset_init_hw. For
 913                  * some unknown reason, this blows up my ilk, so don't.
 914                  */
 915
 916                 mutex_unlock(&dev->struct_mutex);
 917
 918                 drm_irq_uninstall(dev);
 919                 drm_irq_install(dev);
 920         } else {
 921                 mutex_unlock(&dev->struct_mutex);
 922         }
 923
 924         return 0;
 925 }
 926
 927
 928 static int __devinit
 929 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 930 {
 931         /* Only bind to function 0 of the device. Early generations
 932          * used function 1 as a placeholder for multi-head. This causes
 933          * us confusion instead, especially on the systems where both
 934          * functions have the same PCI-ID!
 935          */
 936         if (PCI_FUNC(pdev->devfn))
 937                 return -ENODEV;
 938
 939         return drm_get_pci_dev(pdev, ent, &driver);
 940 }
 941
 942 static void
 943 i915_pci_remove(struct pci_dev *pdev)
 944 {
 945         struct drm_device *dev = pci_get_drvdata(pdev);
 946
 947         drm_put_dev(dev);
 948 }
 949
 950 static int i915_pm_suspend(struct device *dev)
 951 {
 952         struct pci_dev *pdev = to_pci_dev(dev);
 953         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 954         int error;
 955
 956         if (!drm_dev || !drm_dev->dev_private) {
 957                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 958                 return -ENODEV;
 959         }
 960
 961         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 962                 return 0;
 963
 964         error = i915_drm_freeze(drm_dev);
 965         if (error)
 966                 return error;
 967
 968         pci_disable_device(pdev);
 969         pci_set_power_state(pdev, PCI_D3hot);
 970
 971         return 0;
 972 }
 973
 974 static int i915_pm_resume(struct device *dev)
 975 {
 976         struct pci_dev *pdev = to_pci_dev(dev);
 977         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 978
 979         return i915_resume(drm_dev);
 980 }
 981
 982 static int i915_pm_freeze(struct device *dev)
 983 {
 984         struct pci_dev *pdev = to_pci_dev(dev);
 985         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 986
 987         if (!drm_dev || !drm_dev->dev_private) {
 988                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 989                 return -ENODEV;
 990         }
 991
 992         return i915_drm_freeze(drm_dev);
 993 }
 994
 995 static int i915_pm_thaw(struct device *dev)
 996 {
 997         struct pci_dev *pdev = to_pci_dev(dev);
 998         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 999
1000         return i915_drm_thaw(drm_dev);
1001 }
1002
1003 static int i915_pm_poweroff(struct device *dev)
1004 {
1005         struct pci_dev *pdev = to_pci_dev(dev);
1006         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1007
1008         return i915_drm_freeze(drm_dev);
1009 }
1010
1011 static const struct dev_pm_ops i915_pm_ops = {
1012         .suspend = i915_pm_suspend,
1013         .resume = i915_pm_resume,
1014         .freeze = i915_pm_freeze,
1015         .thaw = i915_pm_thaw,
1016         .poweroff = i915_pm_poweroff,
1017         .restore = i915_pm_resume,
1018 };
1019
1020 static const struct vm_operations_struct i915_gem_vm_ops = {
1021         .fault = i915_gem_fault,
1022         .open = drm_gem_vm_open,
1023         .close = drm_gem_vm_close,
1024 };
1025
1026 static const struct file_operations i915_driver_fops = {
1027         .owner = THIS_MODULE,
1028         .open = drm_open,
1029         .release = drm_release,
1030         .unlocked_ioctl = drm_ioctl,
1031         .mmap = drm_gem_mmap,
1032         .poll = drm_poll,
1033         .fasync = drm_fasync,
1034         .read = drm_read,
1035 #ifdef CONFIG_COMPAT
1036         .compat_ioctl = i915_compat_ioctl,
1037 #endif
1038         .llseek = noop_llseek,
1039 };
1040
1041 static struct drm_driver driver = {
1042         /* Don't use MTRRs here; the Xserver or userspace app should
1043          * deal with them for Intel hardware.
1044          */
1045         .driver_features =
1046             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1047             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1048         .load = i915_driver_load,
1049         .unload = i915_driver_unload,
1050         .open = i915_driver_open,
1051         .lastclose = i915_driver_lastclose,
1052         .preclose = i915_driver_preclose,
1053         .postclose = i915_driver_postclose,
1054
1055         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1056         .suspend = i915_suspend,
1057         .resume = i915_resume,
1058
1059         .device_is_agp = i915_driver_device_is_agp,
1060         .reclaim_buffers = drm_core_reclaim_buffers,
1061         .master_create = i915_master_create,
1062         .master_destroy = i915_master_destroy,
1063 #if defined(CONFIG_DEBUG_FS)
1064         .debugfs_init = i915_debugfs_init,
1065         .debugfs_cleanup = i915_debugfs_cleanup,
1066 #endif
1067         .gem_init_object = i915_gem_init_object,
1068         .gem_free_object = i915_gem_free_object,
1069         .gem_vm_ops = &i915_gem_vm_ops,
1070
1071         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1072         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1073         .gem_prime_export = i915_gem_prime_export,
1074         .gem_prime_import = i915_gem_prime_import,
1075
1076         .dumb_create = i915_gem_dumb_create,
1077         .dumb_map_offset = i915_gem_mmap_gtt,
1078         .dumb_destroy = i915_gem_dumb_destroy,
1079         .ioctls = i915_ioctls,
1080         .fops = &i915_driver_fops,
1081         .name = DRIVER_NAME,
1082         .desc = DRIVER_DESC,
1083         .date = DRIVER_DATE,
1084         .major = DRIVER_MAJOR,
1085         .minor = DRIVER_MINOR,
1086         .patchlevel = DRIVER_PATCHLEVEL,
1087 };
1088
1089 static struct pci_driver i915_pci_driver = {
1090         .name = DRIVER_NAME,
1091         .id_table = pciidlist,
1092         .probe = i915_pci_probe,
1093         .remove = i915_pci_remove,
1094         .driver.pm = &i915_pm_ops,
1095 };
1096
1097 static int __init i915_init(void)
1098 {
1099         if (!intel_agp_enabled) {
1100                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
1101                 return -ENODEV;
1102         }
1103
1104         driver.num_ioctls = i915_max_ioctl;
1105
1106         /*
1107          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1108          * explicitly disabled with the module pararmeter.
1109          *
1110          * Otherwise, just follow the parameter (defaulting to off).
1111          *
1112          * Allow optional vga_text_mode_force boot option to override
1113          * the default behavior.
1114          */
1115 #if defined(CONFIG_DRM_I915_KMS)
1116         if (i915_modeset != 0)
1117                 driver.driver_features |= DRIVER_MODESET;
1118 #endif
1119         if (i915_modeset == 1)
1120                 driver.driver_features |= DRIVER_MODESET;
1121
1122 #ifdef CONFIG_VGA_CONSOLE
1123         if (vgacon_text_force() && i915_modeset == -1)
1124                 driver.driver_features &= ~DRIVER_MODESET;
1125 #endif
1126
1127         if (!(driver.driver_features & DRIVER_MODESET))
1128                 driver.get_vblank_timestamp = NULL;
1129
1130         return drm_pci_init(&driver, &i915_pci_driver);
1131 }
1132
1133 static void __exit i915_exit(void)
1134 {
1135         drm_pci_exit(&driver, &i915_pci_driver);
1136 }
1137
1138 module_init(i915_init);
1139 module_exit(i915_exit);
1140
1141 MODULE_AUTHOR(DRIVER_AUTHOR);
1142 MODULE_DESCRIPTION(DRIVER_DESC);
1143 MODULE_LICENSE("GPL and additional rights");
1144
1145 /* We give fast paths for the really cool registers */
1146 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1147        (((dev_priv)->info->gen >= 6) && \
1148         ((reg) < 0x40000) &&            \
1149         ((reg) != FORCEWAKE)) && \
1150        (!IS_VALLEYVIEW((dev_priv)->dev))
1151
1152 static bool IS_DISPLAYREG(u32 reg)
1153 {
1154         /*
1155          * This should make it easier to transition modules over to the
1156          * new register block scheme, since we can do it incrementally.
1157          */
1158         if (reg >= 0x180000)
1159                 return false;
1160
1161         if (reg >= RENDER_RING_BASE &&
1162             reg < RENDER_RING_BASE + 0xff)
1163                 return false;
1164         if (reg >= GEN6_BSD_RING_BASE &&
1165             reg < GEN6_BSD_RING_BASE + 0xff)
1166                 return false;
1167         if (reg >= BLT_RING_BASE &&
1168             reg < BLT_RING_BASE + 0xff)
1169                 return false;
1170
1171         if (reg == PGTBL_ER)
1172                 return false;
1173
1174         if (reg >= IPEIR_I965 &&
1175             reg < HWSTAM)
1176                 return false;
1177
1178         if (reg == MI_MODE)
1179                 return false;
1180
1181         if (reg == GFX_MODE_GEN7)
1182                 return false;
1183
1184         if (reg == RENDER_HWS_PGA_GEN7 ||
1185             reg == BSD_HWS_PGA_GEN7 ||
1186             reg == BLT_HWS_PGA_GEN7)
1187                 return false;
1188
1189         if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
1190             reg == GEN6_BSD_RNCID)
1191                 return false;
1192
1193         if (reg == GEN6_BLITTER_ECOSKPD)
1194                 return false;
1195
1196         if (reg >= 0x4000c &&
1197             reg <= 0x4002c)
1198                 return false;
1199
1200         if (reg >= 0x4f000 &&
1201             reg <= 0x4f08f)
1202                 return false;
1203
1204         if (reg >= 0x4f100 &&
1205             reg <= 0x4f11f)
1206                 return false;
1207
1208         if (reg >= VLV_MASTER_IER &&
1209             reg <= GEN6_PMIER)
1210                 return false;
1211
1212         if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
1213             reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
1214                 return false;
1215
1216         if (reg >= VLV_IIR_RW &&
1217             reg <= VLV_ISR)
1218                 return false;
1219
1220         if (reg == FORCEWAKE_VLV ||
1221             reg == FORCEWAKE_ACK_VLV)
1222                 return false;
1223
1224         if (reg == GEN6_GDRST)
1225                 return false;
1226
1227         return true;
1228 }
1229
1230 #define __i915_read(x, y) \
1231 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1232         u##x val = 0; \
1233         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1234                 unsigned long irqflags; \
1235                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1236                 if (dev_priv->forcewake_count == 0) \
1237                         dev_priv->display.force_wake_get(dev_priv); \
1238                 val = read##y(dev_priv->regs + reg); \
1239                 if (dev_priv->forcewake_count == 0) \
1240                         dev_priv->display.force_wake_put(dev_priv); \
1241                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1242         } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1243                 val = read##y(dev_priv->regs + reg + 0x180000);         \
1244         } else { \
1245                 val = read##y(dev_priv->regs + reg); \
1246         } \
1247         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1248         return val; \
1249 }
1250
1251 __i915_read(8, b)
1252 __i915_read(16, w)
1253 __i915_read(32, l)
1254 __i915_read(64, q)
1255 #undef __i915_read
1256
1257 #define __i915_write(x, y) \
1258 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1259         u32 __fifo_ret = 0; \
1260         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1261         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1262                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1263         } \
1264         if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1265                 write##y(val, dev_priv->regs + reg + 0x180000);         \
1266         } else {                                                        \
1267                 write##y(val, dev_priv->regs + reg);                    \
1268         }                                                               \
1269         if (unlikely(__fifo_ret)) { \
1270                 gen6_gt_check_fifodbg(dev_priv); \
1271         } \
1272 }
1273 __i915_write(8, b)
1274 __i915_write(16, w)
1275 __i915_write(32, l)
1276 __i915_write(64, q)
1277 #undef __i915_write