drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_vgpu.h"
  52 #include "intel_drv.h"
  53 #include "intel_uc.h"
  54
  55 static struct drm_driver driver;
  56
  57 static unsigned int i915_load_fail_count;
  58
  59 bool __i915_inject_load_failure(const char *func, int line)
  60 {
  61         if (i915_load_fail_count >= i915.inject_load_failure)
  62                 return false;
  63
  64         if (++i915_load_fail_count == i915.inject_load_failure) {
  65                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  66                          i915.inject_load_failure, func, line);
  67                 return true;
  68         }
  69
  70         return false;
  71 }
  72
  73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  75                     "providing the dmesg log by booting with drm.debug=0xf"
  76
  77 void
  78 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  79               const char *fmt, ...)
  80 {
  81         static bool shown_bug_once;
  82         struct device *kdev = dev_priv->drm.dev;
  83         bool is_error = level[1] <= KERN_ERR[1];
  84         bool is_debug = level[1] == KERN_DEBUG[1];
  85         struct va_format vaf;
  86         va_list args;
  87
  88         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  89                 return;
  90
  91         va_start(args, fmt);
  92
  93         vaf.fmt = fmt;
  94         vaf.va = &args;
  95
  96         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  97                    __builtin_return_address(0), &vaf);
  98
  99         if (is_error && !shown_bug_once) {
 100                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 101                 shown_bug_once = true;
 102         }
 103
 104         va_end(args);
 105 }
 106
 107 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 108 {
 109         return i915.inject_load_failure &&
 110                i915_load_fail_count == i915.inject_load_failure;
 111 }
 112
 113 #define i915_load_error(dev_priv, fmt, ...)                                  \
 114         __i915_printk(dev_priv,                                              \
 115                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 116                       fmt, ##__VA_ARGS__)
 117
 118
 119 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 120 {
 121         enum intel_pch ret = PCH_NOP;
 122
 123         /*
 124          * In a virtualized passthrough environment we can be in a
 125          * setup where the ISA bridge is not able to be passed through.
 126          * In this case, a south bridge can be emulated and we have to
 127          * make an educated guess as to which PCH is really there.
 128          */
 129
 130         if (IS_GEN5(dev_priv)) {
 131                 ret = PCH_IBX;
 132                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 133         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 134                 ret = PCH_CPT;
 135                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 136         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 137                 ret = PCH_LPT;
 138                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 139         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 140                 ret = PCH_SPT;
 141                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 142         }
 143
 144         return ret;
 145 }
 146
 147 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 148 {
 149         struct pci_dev *pch = NULL;
 150
 151         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 152          * (which really amounts to a PCH but no South Display).
 153          */
 154         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 155                 dev_priv->pch_type = PCH_NOP;
 156                 return;
 157         }
 158
 159         /*
 160          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 161          * make graphics device passthrough work easy for VMM, that only
 162          * need to expose ISA bridge to let driver know the real hardware
 163          * underneath. This is a requirement from virtualization team.
 164          *
 165          * In some virtualized environments (e.g. XEN), there is irrelevant
 166          * ISA bridge in the system. To work reliably, we should scan trhough
 167          * all the ISA bridge devices and check for the first match, instead
 168          * of only checking the first one.
 169          */
 170         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 171                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 172                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 173                         dev_priv->pch_id = id;
 174
 175                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 176                                 dev_priv->pch_type = PCH_IBX;
 177                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 178                                 WARN_ON(!IS_GEN5(dev_priv));
 179                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 180                                 dev_priv->pch_type = PCH_CPT;
 181                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 182                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 183                                         IS_IVYBRIDGE(dev_priv)));
 184                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 185                                 /* PantherPoint is CPT compatible */
 186                                 dev_priv->pch_type = PCH_CPT;
 187                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 188                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 189                                         IS_IVYBRIDGE(dev_priv)));
 190                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 191                                 dev_priv->pch_type = PCH_LPT;
 192                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 193                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 194                                         !IS_BROADWELL(dev_priv));
 195                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 196                                         IS_BDW_ULT(dev_priv));
 197                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 198                                 dev_priv->pch_type = PCH_LPT;
 199                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 200                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 201                                         !IS_BROADWELL(dev_priv));
 202                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 203                                         !IS_BDW_ULT(dev_priv));
 204                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 205                                 dev_priv->pch_type = PCH_SPT;
 206                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 207                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 208                                         !IS_KABYLAKE(dev_priv));
 209                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 210                                 dev_priv->pch_type = PCH_SPT;
 211                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 212                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 213                                         !IS_KABYLAKE(dev_priv));
 214                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 215                                 dev_priv->pch_type = PCH_KBP;
 216                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 217                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 218                                         !IS_KABYLAKE(dev_priv));
 219                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 220                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 221                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 222                                     pch->subsystem_vendor ==
 223                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 224                                     pch->subsystem_device ==
 225                                             PCI_SUBDEVICE_ID_QEMU)) {
 226                                 dev_priv->pch_type =
 227                                         intel_virt_detect_pch(dev_priv);
 228                         } else
 229                                 continue;
 230
 231                         break;
 232                 }
 233         }
 234         if (!pch)
 235                 DRM_DEBUG_KMS("No PCH found.\n");
 236
 237         pci_dev_put(pch);
 238 }
 239
 240 static int i915_getparam(struct drm_device *dev, void *data,
 241                          struct drm_file *file_priv)
 242 {
 243         struct drm_i915_private *dev_priv = to_i915(dev);
 244         struct pci_dev *pdev = dev_priv->drm.pdev;
 245         drm_i915_getparam_t *param = data;
 246         int value;
 247
 248         switch (param->param) {
 249         case I915_PARAM_IRQ_ACTIVE:
 250         case I915_PARAM_ALLOW_BATCHBUFFER:
 251         case I915_PARAM_LAST_DISPATCH:
 252         case I915_PARAM_HAS_EXEC_CONSTANTS:
 253                 /* Reject all old ums/dri params. */
 254                 return -ENODEV;
 255         case I915_PARAM_CHIPSET_ID:
 256                 value = pdev->device;
 257                 break;
 258         case I915_PARAM_REVISION:
 259                 value = pdev->revision;
 260                 break;
 261         case I915_PARAM_NUM_FENCES_AVAIL:
 262                 value = dev_priv->num_fence_regs;
 263                 break;
 264         case I915_PARAM_HAS_OVERLAY:
 265                 value = dev_priv->overlay ? 1 : 0;
 266                 break;
 267         case I915_PARAM_HAS_BSD:
 268                 value = !!dev_priv->engine[VCS];
 269                 break;
 270         case I915_PARAM_HAS_BLT:
 271                 value = !!dev_priv->engine[BCS];
 272                 break;
 273         case I915_PARAM_HAS_VEBOX:
 274                 value = !!dev_priv->engine[VECS];
 275                 break;
 276         case I915_PARAM_HAS_BSD2:
 277                 value = !!dev_priv->engine[VCS2];
 278                 break;
 279         case I915_PARAM_HAS_LLC:
 280                 value = HAS_LLC(dev_priv);
 281                 break;
 282         case I915_PARAM_HAS_WT:
 283                 value = HAS_WT(dev_priv);
 284                 break;
 285         case I915_PARAM_HAS_ALIASING_PPGTT:
 286                 value = USES_PPGTT(dev_priv);
 287                 break;
 288         case I915_PARAM_HAS_SEMAPHORES:
 289                 value = i915.semaphores;
 290                 break;
 291         case I915_PARAM_HAS_SECURE_BATCHES:
 292                 value = capable(CAP_SYS_ADMIN);
 293                 break;
 294         case I915_PARAM_CMD_PARSER_VERSION:
 295                 value = i915_cmd_parser_get_version(dev_priv);
 296                 break;
 297         case I915_PARAM_SUBSLICE_TOTAL:
 298                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 299                 if (!value)
 300                         return -ENODEV;
 301                 break;
 302         case I915_PARAM_EU_TOTAL:
 303                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 304                 if (!value)
 305                         return -ENODEV;
 306                 break;
 307         case I915_PARAM_HAS_GPU_RESET:
 308                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 309                 break;
 310         case I915_PARAM_HAS_RESOURCE_STREAMER:
 311                 value = HAS_RESOURCE_STREAMER(dev_priv);
 312                 break;
 313         case I915_PARAM_HAS_POOLED_EU:
 314                 value = HAS_POOLED_EU(dev_priv);
 315                 break;
 316         case I915_PARAM_MIN_EU_IN_POOL:
 317                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 318                 break;
 319         case I915_PARAM_HUC_STATUS:
 320                 intel_runtime_pm_get(dev_priv);
 321                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 322                 intel_runtime_pm_put(dev_priv);
 323                 break;
 324         case I915_PARAM_MMAP_GTT_VERSION:
 325                 /* Though we've started our numbering from 1, and so class all
 326                  * earlier versions as 0, in effect their value is undefined as
 327                  * the ioctl will report EINVAL for the unknown param!
 328                  */
 329                 value = i915_gem_mmap_gtt_version();
 330                 break;
 331         case I915_PARAM_HAS_SCHEDULER:
 332                 value = dev_priv->engine[RCS] &&
 333                         dev_priv->engine[RCS]->schedule;
 334                 break;
 335         case I915_PARAM_MMAP_VERSION:
 336                 /* Remember to bump this if the version changes! */
 337         case I915_PARAM_HAS_GEM:
 338         case I915_PARAM_HAS_PAGEFLIPPING:
 339         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 340         case I915_PARAM_HAS_RELAXED_FENCING:
 341         case I915_PARAM_HAS_COHERENT_RINGS:
 342         case I915_PARAM_HAS_RELAXED_DELTA:
 343         case I915_PARAM_HAS_GEN7_SOL_RESET:
 344         case I915_PARAM_HAS_WAIT_TIMEOUT:
 345         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 346         case I915_PARAM_HAS_PINNED_BATCHES:
 347         case I915_PARAM_HAS_EXEC_NO_RELOC:
 348         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 349         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 350         case I915_PARAM_HAS_EXEC_SOFTPIN:
 351         case I915_PARAM_HAS_EXEC_ASYNC:
 352         case I915_PARAM_HAS_EXEC_FENCE:
 353         case I915_PARAM_HAS_EXEC_CAPTURE:
 354                 /* For the time being all of these are always true;
 355                  * if some supported hardware does not have one of these
 356                  * features this value needs to be provided from
 357                  * INTEL_INFO(), a feature macro, or similar.
 358                  */
 359                 value = 1;
 360                 break;
 361         default:
 362                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 363                 return -EINVAL;
 364         }
 365
 366         if (put_user(value, param->value))
 367                 return -EFAULT;
 368
 369         return 0;
 370 }
 371
 372 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 373 {
 374         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 375         if (!dev_priv->bridge_dev) {
 376                 DRM_ERROR("bridge device not found\n");
 377                 return -1;
 378         }
 379         return 0;
 380 }
 381
 382 /* Allocate space for the MCH regs if needed, return nonzero on error */
 383 static int
 384 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 385 {
 386         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 387         u32 temp_lo, temp_hi = 0;
 388         u64 mchbar_addr;
 389         int ret;
 390
 391         if (INTEL_GEN(dev_priv) >= 4)
 392                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 393         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 394         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 395
 396         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 397 #ifdef CONFIG_PNP
 398         if (mchbar_addr &&
 399             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 400                 return 0;
 401 #endif
 402
 403         /* Get some space for it */
 404         dev_priv->mch_res.name = "i915 MCHBAR";
 405         dev_priv->mch_res.flags = IORESOURCE_MEM;
 406         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 407                                      &dev_priv->mch_res,
 408                                      MCHBAR_SIZE, MCHBAR_SIZE,
 409                                      PCIBIOS_MIN_MEM,
 410                                      0, pcibios_align_resource,
 411                                      dev_priv->bridge_dev);
 412         if (ret) {
 413                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 414                 dev_priv->mch_res.start = 0;
 415                 return ret;
 416         }
 417
 418         if (INTEL_GEN(dev_priv) >= 4)
 419                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 420                                        upper_32_bits(dev_priv->mch_res.start));
 421
 422         pci_write_config_dword(dev_priv->bridge_dev, reg,
 423                                lower_32_bits(dev_priv->mch_res.start));
 424         return 0;
 425 }
 426
 427 /* Setup MCHBAR if possible, return true if we should disable it again */
 428 static void
 429 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 430 {
 431         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 432         u32 temp;
 433         bool enabled;
 434
 435         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 436                 return;
 437
 438         dev_priv->mchbar_need_disable = false;
 439
 440         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 441                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 442                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 443         } else {
 444                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 445                 enabled = temp & 1;
 446         }
 447
 448         /* If it's already enabled, don't have to do anything */
 449         if (enabled)
 450                 return;
 451
 452         if (intel_alloc_mchbar_resource(dev_priv))
 453                 return;
 454
 455         dev_priv->mchbar_need_disable = true;
 456
 457         /* Space is allocated or reserved, so enable it. */
 458         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 459                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 460                                        temp | DEVEN_MCHBAR_EN);
 461         } else {
 462                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 463                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 464         }
 465 }
 466
 467 static void
 468 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 469 {
 470         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 471
 472         if (dev_priv->mchbar_need_disable) {
 473                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 474                         u32 deven_val;
 475
 476                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 477                                               &deven_val);
 478                         deven_val &= ~DEVEN_MCHBAR_EN;
 479                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 480                                                deven_val);
 481                 } else {
 482                         u32 mchbar_val;
 483
 484                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 485                                               &mchbar_val);
 486                         mchbar_val &= ~1;
 487                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 488                                                mchbar_val);
 489                 }
 490         }
 491
 492         if (dev_priv->mch_res.start)
 493                 release_resource(&dev_priv->mch_res);
 494 }
 495
 496 /* true = enable decode, false = disable decoder */
 497 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 498 {
 499         struct drm_i915_private *dev_priv = cookie;
 500
 501         intel_modeset_vga_set_state(dev_priv, state);
 502         if (state)
 503                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 504                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 505         else
 506                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 507 }
 508
 509 static int i915_resume_switcheroo(struct drm_device *dev);
 510 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 511
 512 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 513 {
 514         struct drm_device *dev = pci_get_drvdata(pdev);
 515         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 516
 517         if (state == VGA_SWITCHEROO_ON) {
 518                 pr_info("switched on\n");
 519                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 520                 /* i915 resume handler doesn't set to D0 */
 521                 pci_set_power_state(pdev, PCI_D0);
 522                 i915_resume_switcheroo(dev);
 523                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 524         } else {
 525                 pr_info("switched off\n");
 526                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 527                 i915_suspend_switcheroo(dev, pmm);
 528                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 529         }
 530 }
 531
 532 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 533 {
 534         struct drm_device *dev = pci_get_drvdata(pdev);
 535
 536         /*
 537          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 538          * locking inversion with the driver load path. And the access here is
 539          * completely racy anyway. So don't bother with locking for now.
 540          */
 541         return dev->open_count == 0;
 542 }
 543
 544 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 545         .set_gpu_state = i915_switcheroo_set_state,
 546         .reprobe = NULL,
 547         .can_switch = i915_switcheroo_can_switch,
 548 };
 549
 550 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 551 {
 552         mutex_lock(&dev_priv->drm.struct_mutex);
 553         intel_uc_fini_hw(dev_priv);
 554         i915_gem_cleanup_engines(dev_priv);
 555         i915_gem_context_fini(dev_priv);
 556         mutex_unlock(&dev_priv->drm.struct_mutex);
 557
 558         i915_gem_drain_freed_objects(dev_priv);
 559
 560         WARN_ON(!list_empty(&dev_priv->context_list));
 561 }
 562
 563 static int i915_load_modeset_init(struct drm_device *dev)
 564 {
 565         struct drm_i915_private *dev_priv = to_i915(dev);
 566         struct pci_dev *pdev = dev_priv->drm.pdev;
 567         int ret;
 568
 569         if (i915_inject_load_failure())
 570                 return -ENODEV;
 571
 572         intel_bios_init(dev_priv);
 573
 574         /* If we have > 1 VGA cards, then we need to arbitrate access
 575          * to the common VGA resources.
 576          *
 577          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 578          * then we do not take part in VGA arbitration and the
 579          * vga_client_register() fails with -ENODEV.
 580          */
 581         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 582         if (ret && ret != -ENODEV)
 583                 goto out;
 584
 585         intel_register_dsm_handler();
 586
 587         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 588         if (ret)
 589                 goto cleanup_vga_client;
 590
 591         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 592         intel_update_rawclk(dev_priv);
 593
 594         intel_power_domains_init_hw(dev_priv, false);
 595
 596         intel_csr_ucode_init(dev_priv);
 597
 598         ret = intel_irq_install(dev_priv);
 599         if (ret)
 600                 goto cleanup_csr;
 601
 602         intel_setup_gmbus(dev_priv);
 603
 604         /* Important: The output setup functions called by modeset_init need
 605          * working irqs for e.g. gmbus and dp aux transfers. */
 606         ret = intel_modeset_init(dev);
 607         if (ret)
 608                 goto cleanup_irq;
 609
 610         intel_uc_init_fw(dev_priv);
 611
 612         ret = i915_gem_init(dev_priv);
 613         if (ret)
 614                 goto cleanup_uc;
 615
 616         intel_modeset_gem_init(dev);
 617
 618         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 619                 return 0;
 620
 621         ret = intel_fbdev_init(dev);
 622         if (ret)
 623                 goto cleanup_gem;
 624
 625         /* Only enable hotplug handling once the fbdev is fully set up. */
 626         intel_hpd_init(dev_priv);
 627
 628         drm_kms_helper_poll_init(dev);
 629
 630         return 0;
 631
 632 cleanup_gem:
 633         if (i915_gem_suspend(dev_priv))
 634                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 635         i915_gem_fini(dev_priv);
 636 cleanup_uc:
 637         intel_uc_fini_fw(dev_priv);
 638 cleanup_irq:
 639         drm_irq_uninstall(dev);
 640         intel_teardown_gmbus(dev_priv);
 641 cleanup_csr:
 642         intel_csr_ucode_fini(dev_priv);
 643         intel_power_domains_fini(dev_priv);
 644         vga_switcheroo_unregister_client(pdev);
 645 cleanup_vga_client:
 646         vga_client_register(pdev, NULL, NULL, NULL);
 647 out:
 648         return ret;
 649 }
 650
 651 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 652 {
 653         struct apertures_struct *ap;
 654         struct pci_dev *pdev = dev_priv->drm.pdev;
 655         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 656         bool primary;
 657         int ret;
 658
 659         ap = alloc_apertures(1);
 660         if (!ap)
 661                 return -ENOMEM;
 662
 663         ap->ranges[0].base = ggtt->mappable_base;
 664         ap->ranges[0].size = ggtt->mappable_end;
 665
 666         primary =
 667                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 668
 669         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 670
 671         kfree(ap);
 672
 673         return ret;
 674 }
 675
 676 #if !defined(CONFIG_VGA_CONSOLE)
 677 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 678 {
 679         return 0;
 680 }
 681 #elif !defined(CONFIG_DUMMY_CONSOLE)
 682 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 683 {
 684         return -ENODEV;
 685 }
 686 #else
 687 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 688 {
 689         int ret = 0;
 690
 691         DRM_INFO("Replacing VGA console driver\n");
 692
 693         console_lock();
 694         if (con_is_bound(&vga_con))
 695                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 696         if (ret == 0) {
 697                 ret = do_unregister_con_driver(&vga_con);
 698
 699                 /* Ignore "already unregistered". */
 700                 if (ret == -ENODEV)
 701                         ret = 0;
 702         }
 703         console_unlock();
 704
 705         return ret;
 706 }
 707 #endif
 708
 709 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 710 {
 711         /*
 712          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 713          * CHV x1 PHY (DP/HDMI D)
 714          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 715          */
 716         if (IS_CHERRYVIEW(dev_priv)) {
 717                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 718                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 719         } else if (IS_VALLEYVIEW(dev_priv)) {
 720                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 721         }
 722 }
 723
 724 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 725 {
 726         /*
 727          * The i915 workqueue is primarily used for batched retirement of
 728          * requests (and thus managing bo) once the task has been completed
 729          * by the GPU. i915_gem_retire_requests() is called directly when we
 730          * need high-priority retirement, such as waiting for an explicit
 731          * bo.
 732          *
 733          * It is also used for periodic low-priority events, such as
 734          * idle-timers and recording error state.
 735          *
 736          * All tasks on the workqueue are expected to acquire the dev mutex
 737          * so there is no point in running more than one instance of the
 738          * workqueue at any time.  Use an ordered one.
 739          */
 740         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 741         if (dev_priv->wq == NULL)
 742                 goto out_err;
 743
 744         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 745         if (dev_priv->hotplug.dp_wq == NULL)
 746                 goto out_free_wq;
 747
 748         return 0;
 749
 750 out_free_wq:
 751         destroy_workqueue(dev_priv->wq);
 752 out_err:
 753         DRM_ERROR("Failed to allocate workqueues.\n");
 754
 755         return -ENOMEM;
 756 }
 757
 758 static void i915_engines_cleanup(struct drm_i915_private *i915)
 759 {
 760         struct intel_engine_cs *engine;
 761         enum intel_engine_id id;
 762
 763         for_each_engine(engine, i915, id)
 764                 kfree(engine);
 765 }
 766
 767 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 768 {
 769         destroy_workqueue(dev_priv->hotplug.dp_wq);
 770         destroy_workqueue(dev_priv->wq);
 771 }
 772
 773 /*
 774  * We don't keep the workarounds for pre-production hardware, so we expect our
 775  * driver to fail on these machines in one way or another. A little warning on
 776  * dmesg may help both the user and the bug triagers.
 777  */
 778 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 779 {
 780         bool pre = false;
 781
 782         pre |= IS_HSW_EARLY_SDV(dev_priv);
 783         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 784         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 785
 786         if (pre) {
 787                 DRM_ERROR("This is a pre-production stepping. "
 788                           "It may not be fully functional.\n");
 789                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 790         }
 791 }
 792
 793 /**
 794  * i915_driver_init_early - setup state not requiring device access
 795  * @dev_priv: device private
 796  *
 797  * Initialize everything that is a "SW-only" state, that is state not
 798  * requiring accessing the device or exposing the driver via kernel internal
 799  * or userspace interfaces. Example steps belonging here: lock initialization,
 800  * system memory allocation, setting up device specific attributes and
 801  * function hooks not requiring accessing the device.
 802  */
 803 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 804                                   const struct pci_device_id *ent)
 805 {
 806         const struct intel_device_info *match_info =
 807                 (struct intel_device_info *)ent->driver_data;
 808         struct intel_device_info *device_info;
 809         int ret = 0;
 810
 811         if (i915_inject_load_failure())
 812                 return -ENODEV;
 813
 814         /* Setup the write-once "constant" device info */
 815         device_info = mkwrite_device_info(dev_priv);
 816         memcpy(device_info, match_info, sizeof(*device_info));
 817         device_info->device_id = dev_priv->drm.pdev->device;
 818
 819         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 820         device_info->gen_mask = BIT(device_info->gen - 1);
 821
 822         spin_lock_init(&dev_priv->irq_lock);
 823         spin_lock_init(&dev_priv->gpu_error.lock);
 824         mutex_init(&dev_priv->backlight_lock);
 825         spin_lock_init(&dev_priv->uncore.lock);
 826
 827         spin_lock_init(&dev_priv->mm.object_stat_lock);
 828         spin_lock_init(&dev_priv->mmio_flip_lock);
 829         mutex_init(&dev_priv->sb_lock);
 830         mutex_init(&dev_priv->modeset_restore_lock);
 831         mutex_init(&dev_priv->av_mutex);
 832         mutex_init(&dev_priv->wm.wm_mutex);
 833         mutex_init(&dev_priv->pps_mutex);
 834
 835         intel_uc_init_early(dev_priv);
 836         i915_memcpy_init_early(dev_priv);
 837
 838         ret = i915_workqueues_init(dev_priv);
 839         if (ret < 0)
 840                 goto err_engines;
 841
 842         /* This must be called before any calls to HAS_PCH_* */
 843         intel_detect_pch(dev_priv);
 844
 845         intel_pm_setup(dev_priv);
 846         intel_init_dpio(dev_priv);
 847         intel_power_domains_init(dev_priv);
 848         intel_irq_init(dev_priv);
 849         intel_hangcheck_init(dev_priv);
 850         intel_init_display_hooks(dev_priv);
 851         intel_init_clock_gating_hooks(dev_priv);
 852         intel_init_audio_hooks(dev_priv);
 853         ret = i915_gem_load_init(dev_priv);
 854         if (ret < 0)
 855                 goto err_irq;
 856
 857         intel_display_crc_init(dev_priv);
 858
 859         intel_device_info_dump(dev_priv);
 860
 861         intel_detect_preproduction_hw(dev_priv);
 862
 863         i915_perf_init(dev_priv);
 864
 865         return 0;
 866
 867 err_irq:
 868         intel_irq_fini(dev_priv);
 869         i915_workqueues_cleanup(dev_priv);
 870 err_engines:
 871         i915_engines_cleanup(dev_priv);
 872         return ret;
 873 }
 874
 875 /**
 876  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 877  * @dev_priv: device private
 878  */
 879 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 880 {
 881         i915_perf_fini(dev_priv);
 882         i915_gem_load_cleanup(dev_priv);
 883         intel_irq_fini(dev_priv);
 884         i915_workqueues_cleanup(dev_priv);
 885         i915_engines_cleanup(dev_priv);
 886 }
 887
 888 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 889 {
 890         struct pci_dev *pdev = dev_priv->drm.pdev;
 891         int mmio_bar;
 892         int mmio_size;
 893
 894         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 895         /*
 896          * Before gen4, the registers and the GTT are behind different BARs.
 897          * However, from gen4 onwards, the registers and the GTT are shared
 898          * in the same BAR, so we want to restrict this ioremap from
 899          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 900          * the register BAR remains the same size for all the earlier
 901          * generations up to Ironlake.
 902          */
 903         if (INTEL_GEN(dev_priv) < 5)
 904                 mmio_size = 512 * 1024;
 905         else
 906                 mmio_size = 2 * 1024 * 1024;
 907         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 908         if (dev_priv->regs == NULL) {
 909                 DRM_ERROR("failed to map registers\n");
 910
 911                 return -EIO;
 912         }
 913
 914         /* Try to make sure MCHBAR is enabled before poking at it */
 915         intel_setup_mchbar(dev_priv);
 916
 917         return 0;
 918 }
 919
 920 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 921 {
 922         struct pci_dev *pdev = dev_priv->drm.pdev;
 923
 924         intel_teardown_mchbar(dev_priv);
 925         pci_iounmap(pdev, dev_priv->regs);
 926 }
 927
 928 /**
 929  * i915_driver_init_mmio - setup device MMIO
 930  * @dev_priv: device private
 931  *
 932  * Setup minimal device state necessary for MMIO accesses later in the
 933  * initialization sequence. The setup here should avoid any other device-wide
 934  * side effects or exposing the driver via kernel internal or user space
 935  * interfaces.
 936  */
 937 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 938 {
 939         int ret;
 940
 941         if (i915_inject_load_failure())
 942                 return -ENODEV;
 943
 944         if (i915_get_bridge_dev(dev_priv))
 945                 return -EIO;
 946
 947         ret = i915_mmio_setup(dev_priv);
 948         if (ret < 0)
 949                 goto err_bridge;
 950
 951         intel_uncore_init(dev_priv);
 952
 953         ret = intel_engines_init_mmio(dev_priv);
 954         if (ret)
 955                 goto err_uncore;
 956
 957         i915_gem_init_mmio(dev_priv);
 958
 959         return 0;
 960
 961 err_uncore:
 962         intel_uncore_fini(dev_priv);
 963 err_bridge:
 964         pci_dev_put(dev_priv->bridge_dev);
 965
 966         return ret;
 967 }
 968
 969 /**
 970  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 971  * @dev_priv: device private
 972  */
 973 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 974 {
 975         intel_uncore_fini(dev_priv);
 976         i915_mmio_cleanup(dev_priv);
 977         pci_dev_put(dev_priv->bridge_dev);
 978 }
 979
 980 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 981 {
 982         i915.enable_execlists =
 983                 intel_sanitize_enable_execlists(dev_priv,
 984                                                 i915.enable_execlists);
 985
 986         /*
 987          * i915.enable_ppgtt is read-only, so do an early pass to validate the
 988          * user's requested state against the hardware/driver capabilities.  We
 989          * do this now so that we can print out any log messages once rather
 990          * than every time we check intel_enable_ppgtt().
 991          */
 992         i915.enable_ppgtt =
 993                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
 994         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 995
 996         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
 997         DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
 998
 999         intel_uc_sanitize_options(dev_priv);
1000
1001         intel_gvt_sanitize_options(dev_priv);
1002 }
1003
1004 /**
1005  * i915_driver_init_hw - setup state requiring device access
1006  * @dev_priv: device private
1007  *
1008  * Setup state that requires accessing the device, but doesn't require
1009  * exposing the driver via kernel internal or userspace interfaces.
1010  */
1011 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1012 {
1013         struct pci_dev *pdev = dev_priv->drm.pdev;
1014         int ret;
1015
1016         if (i915_inject_load_failure())
1017                 return -ENODEV;
1018
1019         intel_device_info_runtime_init(dev_priv);
1020
1021         intel_sanitize_options(dev_priv);
1022
1023         ret = i915_ggtt_probe_hw(dev_priv);
1024         if (ret)
1025                 return ret;
1026
1027         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1028          * otherwise the vga fbdev driver falls over. */
1029         ret = i915_kick_out_firmware_fb(dev_priv);
1030         if (ret) {
1031                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1032                 goto out_ggtt;
1033         }
1034
1035         ret = i915_kick_out_vgacon(dev_priv);
1036         if (ret) {
1037                 DRM_ERROR("failed to remove conflicting VGA console\n");
1038                 goto out_ggtt;
1039         }
1040
1041         ret = i915_ggtt_init_hw(dev_priv);
1042         if (ret)
1043                 return ret;
1044
1045         ret = i915_ggtt_enable_hw(dev_priv);
1046         if (ret) {
1047                 DRM_ERROR("failed to enable GGTT\n");
1048                 goto out_ggtt;
1049         }
1050
1051         pci_set_master(pdev);
1052
1053         /* overlay on gen2 is broken and can't address above 1G */
1054         if (IS_GEN2(dev_priv)) {
1055                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1056                 if (ret) {
1057                         DRM_ERROR("failed to set DMA mask\n");
1058
1059                         goto out_ggtt;
1060                 }
1061         }
1062
1063         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1064          * using 32bit addressing, overwriting memory if HWS is located
1065          * above 4GB.
1066          *
1067          * The documentation also mentions an issue with undefined
1068          * behaviour if any general state is accessed within a page above 4GB,
1069          * which also needs to be handled carefully.
1070          */
1071         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1072                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1073
1074                 if (ret) {
1075                         DRM_ERROR("failed to set DMA mask\n");
1076
1077                         goto out_ggtt;
1078                 }
1079         }
1080
1081         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1082                            PM_QOS_DEFAULT_VALUE);
1083
1084         intel_uncore_sanitize(dev_priv);
1085
1086         intel_opregion_setup(dev_priv);
1087
1088         i915_gem_load_init_fences(dev_priv);
1089
1090         /* On the 945G/GM, the chipset reports the MSI capability on the
1091          * integrated graphics even though the support isn't actually there
1092          * according to the published specs.  It doesn't appear to function
1093          * correctly in testing on 945G.
1094          * This may be a side effect of MSI having been made available for PEG
1095          * and the registers being closely associated.
1096          *
1097          * According to chipset errata, on the 965GM, MSI interrupts may
1098          * be lost or delayed, but we use them anyways to avoid
1099          * stuck interrupts on some machines.
1100          */
1101         if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
1102                 if (pci_enable_msi(pdev) < 0)
1103                         DRM_DEBUG_DRIVER("can't enable MSI");
1104         }
1105
1106         ret = intel_gvt_init(dev_priv);
1107         if (ret)
1108                 goto out_ggtt;
1109
1110         return 0;
1111
1112 out_ggtt:
1113         i915_ggtt_cleanup_hw(dev_priv);
1114
1115         return ret;
1116 }
1117
1118 /**
1119  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1120  * @dev_priv: device private
1121  */
1122 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1123 {
1124         struct pci_dev *pdev = dev_priv->drm.pdev;
1125
1126         if (pdev->msi_enabled)
1127                 pci_disable_msi(pdev);
1128
1129         pm_qos_remove_request(&dev_priv->pm_qos);
1130         i915_ggtt_cleanup_hw(dev_priv);
1131 }
1132
1133 /**
1134  * i915_driver_register - register the driver with the rest of the system
1135  * @dev_priv: device private
1136  *
1137  * Perform any steps necessary to make the driver available via kernel
1138  * internal or userspace interfaces.
1139  */
1140 static void i915_driver_register(struct drm_i915_private *dev_priv)
1141 {
1142         struct drm_device *dev = &dev_priv->drm;
1143
1144         i915_gem_shrinker_init(dev_priv);
1145
1146         /*
1147          * Notify a valid surface after modesetting,
1148          * when running inside a VM.
1149          */
1150         if (intel_vgpu_active(dev_priv))
1151                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1152
1153         /* Reveal our presence to userspace */
1154         if (drm_dev_register(dev, 0) == 0) {
1155                 i915_debugfs_register(dev_priv);
1156                 i915_guc_log_register(dev_priv);
1157                 i915_setup_sysfs(dev_priv);
1158
1159                 /* Depends on sysfs having been initialized */
1160                 i915_perf_register(dev_priv);
1161         } else
1162                 DRM_ERROR("Failed to register driver for userspace access!\n");
1163
1164         if (INTEL_INFO(dev_priv)->num_pipes) {
1165                 /* Must be done after probing outputs */
1166                 intel_opregion_register(dev_priv);
1167                 acpi_video_register();
1168         }
1169
1170         if (IS_GEN5(dev_priv))
1171                 intel_gpu_ips_init(dev_priv);
1172
1173         intel_audio_init(dev_priv);
1174
1175         /*
1176          * Some ports require correctly set-up hpd registers for detection to
1177          * work properly (leading to ghost connected connector status), e.g. VGA
1178          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1179          * irqs are fully enabled. We do it last so that the async config
1180          * cannot run before the connectors are registered.
1181          */
1182         intel_fbdev_initial_config_async(dev);
1183 }
1184
1185 /**
1186  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1187  * @dev_priv: device private
1188  */
1189 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1190 {
1191         intel_audio_deinit(dev_priv);
1192
1193         intel_gpu_ips_teardown();
1194         acpi_video_unregister();
1195         intel_opregion_unregister(dev_priv);
1196
1197         i915_perf_unregister(dev_priv);
1198
1199         i915_teardown_sysfs(dev_priv);
1200         i915_guc_log_unregister(dev_priv);
1201         drm_dev_unregister(&dev_priv->drm);
1202
1203         i915_gem_shrinker_cleanup(dev_priv);
1204 }
1205
1206 /**
1207  * i915_driver_load - setup chip and create an initial config
1208  * @pdev: PCI device
1209  * @ent: matching PCI ID entry
1210  *
1211  * The driver load routine has to do several things:
1212  *   - drive output discovery via intel_modeset_init()
1213  *   - initialize the memory manager
1214  *   - allocate initial config memory
1215  *   - setup the DRM framebuffer with the allocated memory
1216  */
1217 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1218 {
1219         const struct intel_device_info *match_info =
1220                 (struct intel_device_info *)ent->driver_data;
1221         struct drm_i915_private *dev_priv;
1222         int ret;
1223
1224         /* Enable nuclear pageflip on ILK+ */
1225         if (!i915.nuclear_pageflip && match_info->gen < 5)
1226                 driver.driver_features &= ~DRIVER_ATOMIC;
1227
1228         ret = -ENOMEM;
1229         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1230         if (dev_priv)
1231                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1232         if (ret) {
1233                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1234                 goto out_free;
1235         }
1236
1237         dev_priv->drm.pdev = pdev;
1238         dev_priv->drm.dev_private = dev_priv;
1239
1240         ret = pci_enable_device(pdev);
1241         if (ret)
1242                 goto out_fini;
1243
1244         pci_set_drvdata(pdev, &dev_priv->drm);
1245         /*
1246          * Disable the system suspend direct complete optimization, which can
1247          * leave the device suspended skipping the driver's suspend handlers
1248          * if the device was already runtime suspended. This is needed due to
1249          * the difference in our runtime and system suspend sequence and
1250          * becaue the HDA driver may require us to enable the audio power
1251          * domain during system suspend.
1252          */
1253         pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
1254
1255         ret = i915_driver_init_early(dev_priv, ent);
1256         if (ret < 0)
1257                 goto out_pci_disable;
1258
1259         intel_runtime_pm_get(dev_priv);
1260
1261         ret = i915_driver_init_mmio(dev_priv);
1262         if (ret < 0)
1263                 goto out_runtime_pm_put;
1264
1265         ret = i915_driver_init_hw(dev_priv);
1266         if (ret < 0)
1267                 goto out_cleanup_mmio;
1268
1269         /*
1270          * TODO: move the vblank init and parts of modeset init steps into one
1271          * of the i915_driver_init_/i915_driver_register functions according
1272          * to the role/effect of the given init step.
1273          */
1274         if (INTEL_INFO(dev_priv)->num_pipes) {
1275                 ret = drm_vblank_init(&dev_priv->drm,
1276                                       INTEL_INFO(dev_priv)->num_pipes);
1277                 if (ret)
1278                         goto out_cleanup_hw;
1279         }
1280
1281         ret = i915_load_modeset_init(&dev_priv->drm);
1282         if (ret < 0)
1283                 goto out_cleanup_vblank;
1284
1285         i915_driver_register(dev_priv);
1286
1287         intel_runtime_pm_enable(dev_priv);
1288
1289         dev_priv->ipc_enabled = false;
1290
1291         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1292                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1293         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1294                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1295
1296         intel_runtime_pm_put(dev_priv);
1297
1298         return 0;
1299
1300 out_cleanup_vblank:
1301         drm_vblank_cleanup(&dev_priv->drm);
1302 out_cleanup_hw:
1303         i915_driver_cleanup_hw(dev_priv);
1304 out_cleanup_mmio:
1305         i915_driver_cleanup_mmio(dev_priv);
1306 out_runtime_pm_put:
1307         intel_runtime_pm_put(dev_priv);
1308         i915_driver_cleanup_early(dev_priv);
1309 out_pci_disable:
1310         pci_disable_device(pdev);
1311 out_fini:
1312         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1313         drm_dev_fini(&dev_priv->drm);
1314 out_free:
1315         kfree(dev_priv);
1316         return ret;
1317 }
1318
1319 void i915_driver_unload(struct drm_device *dev)
1320 {
1321         struct drm_i915_private *dev_priv = to_i915(dev);
1322         struct pci_dev *pdev = dev_priv->drm.pdev;
1323
1324         intel_fbdev_fini(dev);
1325
1326         if (i915_gem_suspend(dev_priv))
1327                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1328
1329         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1330
1331         drm_atomic_helper_shutdown(dev);
1332
1333         intel_gvt_cleanup(dev_priv);
1334
1335         i915_driver_unregister(dev_priv);
1336
1337         drm_vblank_cleanup(dev);
1338
1339         intel_modeset_cleanup(dev);
1340
1341         /*
1342          * free the memory space allocated for the child device
1343          * config parsed from VBT
1344          */
1345         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1346                 kfree(dev_priv->vbt.child_dev);
1347                 dev_priv->vbt.child_dev = NULL;
1348                 dev_priv->vbt.child_dev_num = 0;
1349         }
1350         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1351         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1352         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1353         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1354
1355         vga_switcheroo_unregister_client(pdev);
1356         vga_client_register(pdev, NULL, NULL, NULL);
1357
1358         intel_csr_ucode_fini(dev_priv);
1359
1360         /* Free error state after interrupts are fully disabled. */
1361         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1362         i915_reset_error_state(dev_priv);
1363
1364         /* Flush any outstanding unpin_work. */
1365         drain_workqueue(dev_priv->wq);
1366
1367         i915_gem_fini(dev_priv);
1368         intel_uc_fini_fw(dev_priv);
1369         intel_fbc_cleanup_cfb(dev_priv);
1370
1371         intel_power_domains_fini(dev_priv);
1372
1373         i915_driver_cleanup_hw(dev_priv);
1374         i915_driver_cleanup_mmio(dev_priv);
1375
1376         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1377 }
1378
1379 static void i915_driver_release(struct drm_device *dev)
1380 {
1381         struct drm_i915_private *dev_priv = to_i915(dev);
1382
1383         i915_driver_cleanup_early(dev_priv);
1384         drm_dev_fini(&dev_priv->drm);
1385
1386         kfree(dev_priv);
1387 }
1388
1389 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1390 {
1391         int ret;
1392
1393         ret = i915_gem_open(dev, file);
1394         if (ret)
1395                 return ret;
1396
1397         return 0;
1398 }
1399
1400 /**
1401  * i915_driver_lastclose - clean up after all DRM clients have exited
1402  * @dev: DRM device
1403  *
1404  * Take care of cleaning up after all DRM clients have exited.  In the
1405  * mode setting case, we want to restore the kernel's initial mode (just
1406  * in case the last client left us in a bad state).
1407  *
1408  * Additionally, in the non-mode setting case, we'll tear down the GTT
1409  * and DMA structures, since the kernel won't be using them, and clea
1410  * up any GEM state.
1411  */
1412 static void i915_driver_lastclose(struct drm_device *dev)
1413 {
1414         intel_fbdev_restore_mode(dev);
1415         vga_switcheroo_process_delayed_switch();
1416 }
1417
1418 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1419 {
1420         struct drm_i915_file_private *file_priv = file->driver_priv;
1421
1422         mutex_lock(&dev->struct_mutex);
1423         i915_gem_context_close(dev, file);
1424         i915_gem_release(dev, file);
1425         mutex_unlock(&dev->struct_mutex);
1426
1427         kfree(file_priv);
1428 }
1429
1430 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1431 {
1432         struct drm_device *dev = &dev_priv->drm;
1433         struct intel_encoder *encoder;
1434
1435         drm_modeset_lock_all(dev);
1436         for_each_intel_encoder(dev, encoder)
1437                 if (encoder->suspend)
1438                         encoder->suspend(encoder);
1439         drm_modeset_unlock_all(dev);
1440 }
1441
1442 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1443                               bool rpm_resume);
1444 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1445
1446 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1447 {
1448 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1449         if (acpi_target_system_state() < ACPI_STATE_S3)
1450                 return true;
1451 #endif
1452         return false;
1453 }
1454
1455 static int i915_drm_suspend(struct drm_device *dev)
1456 {
1457         struct drm_i915_private *dev_priv = to_i915(dev);
1458         struct pci_dev *pdev = dev_priv->drm.pdev;
1459         pci_power_t opregion_target_state;
1460         int error;
1461
1462         /* ignore lid events during suspend */
1463         mutex_lock(&dev_priv->modeset_restore_lock);
1464         dev_priv->modeset_restore = MODESET_SUSPENDED;
1465         mutex_unlock(&dev_priv->modeset_restore_lock);
1466
1467         disable_rpm_wakeref_asserts(dev_priv);
1468
1469         /* We do a lot of poking in a lot of registers, make sure they work
1470          * properly. */
1471         intel_display_set_init_power(dev_priv, true);
1472
1473         drm_kms_helper_poll_disable(dev);
1474
1475         pci_save_state(pdev);
1476
1477         error = i915_gem_suspend(dev_priv);
1478         if (error) {
1479                 dev_err(&pdev->dev,
1480                         "GEM idle failed, resume might fail\n");
1481                 goto out;
1482         }
1483
1484         intel_display_suspend(dev);
1485
1486         intel_dp_mst_suspend(dev);
1487
1488         intel_runtime_pm_disable_interrupts(dev_priv);
1489         intel_hpd_cancel_work(dev_priv);
1490
1491         intel_suspend_encoders(dev_priv);
1492
1493         intel_suspend_hw(dev_priv);
1494
1495         i915_gem_suspend_gtt_mappings(dev_priv);
1496
1497         i915_save_state(dev_priv);
1498
1499         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1500         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1501
1502         intel_uncore_suspend(dev_priv);
1503         intel_opregion_unregister(dev_priv);
1504
1505         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1506
1507         dev_priv->suspend_count++;
1508
1509         intel_csr_ucode_suspend(dev_priv);
1510
1511 out:
1512         enable_rpm_wakeref_asserts(dev_priv);
1513
1514         return error;
1515 }
1516
1517 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1518 {
1519         struct drm_i915_private *dev_priv = to_i915(dev);
1520         struct pci_dev *pdev = dev_priv->drm.pdev;
1521         bool fw_csr;
1522         int ret;
1523
1524         disable_rpm_wakeref_asserts(dev_priv);
1525
1526         intel_display_set_init_power(dev_priv, false);
1527
1528         fw_csr = !IS_GEN9_LP(dev_priv) &&
1529                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1530         /*
1531          * In case of firmware assisted context save/restore don't manually
1532          * deinit the power domains. This also means the CSR/DMC firmware will
1533          * stay active, it will power down any HW resources as required and
1534          * also enable deeper system power states that would be blocked if the
1535          * firmware was inactive.
1536          */
1537         if (!fw_csr)
1538                 intel_power_domains_suspend(dev_priv);
1539
1540         ret = 0;
1541         if (IS_GEN9_LP(dev_priv))
1542                 bxt_enable_dc9(dev_priv);
1543         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1544                 hsw_enable_pc8(dev_priv);
1545         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1546                 ret = vlv_suspend_complete(dev_priv);
1547
1548         if (ret) {
1549                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1550                 if (!fw_csr)
1551                         intel_power_domains_init_hw(dev_priv, true);
1552
1553                 goto out;
1554         }
1555
1556         pci_disable_device(pdev);
1557         /*
1558          * During hibernation on some platforms the BIOS may try to access
1559          * the device even though it's already in D3 and hang the machine. So
1560          * leave the device in D0 on those platforms and hope the BIOS will
1561          * power down the device properly. The issue was seen on multiple old
1562          * GENs with different BIOS vendors, so having an explicit blacklist
1563          * is inpractical; apply the workaround on everything pre GEN6. The
1564          * platforms where the issue was seen:
1565          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1566          * Fujitsu FSC S7110
1567          * Acer Aspire 1830T
1568          */
1569         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1570                 pci_set_power_state(pdev, PCI_D3hot);
1571
1572         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1573
1574 out:
1575         enable_rpm_wakeref_asserts(dev_priv);
1576
1577         return ret;
1578 }
1579
1580 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1581 {
1582         int error;
1583
1584         if (!dev) {
1585                 DRM_ERROR("dev: %p\n", dev);
1586                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1587                 return -ENODEV;
1588         }
1589
1590         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1591                          state.event != PM_EVENT_FREEZE))
1592                 return -EINVAL;
1593
1594         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1595                 return 0;
1596
1597         error = i915_drm_suspend(dev);
1598         if (error)
1599                 return error;
1600
1601         return i915_drm_suspend_late(dev, false);
1602 }
1603
1604 static int i915_drm_resume(struct drm_device *dev)
1605 {
1606         struct drm_i915_private *dev_priv = to_i915(dev);
1607         int ret;
1608
1609         disable_rpm_wakeref_asserts(dev_priv);
1610         intel_sanitize_gt_powersave(dev_priv);
1611
1612         ret = i915_ggtt_enable_hw(dev_priv);
1613         if (ret)
1614                 DRM_ERROR("failed to re-enable GGTT\n");
1615
1616         intel_csr_ucode_resume(dev_priv);
1617
1618         i915_gem_resume(dev_priv);
1619
1620         i915_restore_state(dev_priv);
1621         intel_pps_unlock_regs_wa(dev_priv);
1622         intel_opregion_setup(dev_priv);
1623
1624         intel_init_pch_refclk(dev_priv);
1625
1626         /*
1627          * Interrupts have to be enabled before any batches are run. If not the
1628          * GPU will hang. i915_gem_init_hw() will initiate batches to
1629          * update/restore the context.
1630          *
1631          * drm_mode_config_reset() needs AUX interrupts.
1632          *
1633          * Modeset enabling in intel_modeset_init_hw() also needs working
1634          * interrupts.
1635          */
1636         intel_runtime_pm_enable_interrupts(dev_priv);
1637
1638         drm_mode_config_reset(dev);
1639
1640         mutex_lock(&dev->struct_mutex);
1641         if (i915_gem_init_hw(dev_priv)) {
1642                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1643                 i915_gem_set_wedged(dev_priv);
1644         }
1645         mutex_unlock(&dev->struct_mutex);
1646
1647         intel_guc_resume(dev_priv);
1648
1649         intel_modeset_init_hw(dev);
1650
1651         spin_lock_irq(&dev_priv->irq_lock);
1652         if (dev_priv->display.hpd_irq_setup)
1653                 dev_priv->display.hpd_irq_setup(dev_priv);
1654         spin_unlock_irq(&dev_priv->irq_lock);
1655
1656         intel_dp_mst_resume(dev);
1657
1658         intel_display_resume(dev);
1659
1660         drm_kms_helper_poll_enable(dev);
1661
1662         /*
1663          * ... but also need to make sure that hotplug processing
1664          * doesn't cause havoc. Like in the driver load code we don't
1665          * bother with the tiny race here where we might loose hotplug
1666          * notifications.
1667          * */
1668         intel_hpd_init(dev_priv);
1669
1670         intel_opregion_register(dev_priv);
1671
1672         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1673
1674         mutex_lock(&dev_priv->modeset_restore_lock);
1675         dev_priv->modeset_restore = MODESET_DONE;
1676         mutex_unlock(&dev_priv->modeset_restore_lock);
1677
1678         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1679
1680         intel_autoenable_gt_powersave(dev_priv);
1681
1682         enable_rpm_wakeref_asserts(dev_priv);
1683
1684         return 0;
1685 }
1686
1687 static int i915_drm_resume_early(struct drm_device *dev)
1688 {
1689         struct drm_i915_private *dev_priv = to_i915(dev);
1690         struct pci_dev *pdev = dev_priv->drm.pdev;
1691         int ret;
1692
1693         /*
1694          * We have a resume ordering issue with the snd-hda driver also
1695          * requiring our device to be power up. Due to the lack of a
1696          * parent/child relationship we currently solve this with an early
1697          * resume hook.
1698          *
1699          * FIXME: This should be solved with a special hdmi sink device or
1700          * similar so that power domains can be employed.
1701          */
1702
1703         /*
1704          * Note that we need to set the power state explicitly, since we
1705          * powered off the device during freeze and the PCI core won't power
1706          * it back up for us during thaw. Powering off the device during
1707          * freeze is not a hard requirement though, and during the
1708          * suspend/resume phases the PCI core makes sure we get here with the
1709          * device powered on. So in case we change our freeze logic and keep
1710          * the device powered we can also remove the following set power state
1711          * call.
1712          */
1713         ret = pci_set_power_state(pdev, PCI_D0);
1714         if (ret) {
1715                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1716                 goto out;
1717         }
1718
1719         /*
1720          * Note that pci_enable_device() first enables any parent bridge
1721          * device and only then sets the power state for this device. The
1722          * bridge enabling is a nop though, since bridge devices are resumed
1723          * first. The order of enabling power and enabling the device is
1724          * imposed by the PCI core as described above, so here we preserve the
1725          * same order for the freeze/thaw phases.
1726          *
1727          * TODO: eventually we should remove pci_disable_device() /
1728          * pci_enable_enable_device() from suspend/resume. Due to how they
1729          * depend on the device enable refcount we can't anyway depend on them
1730          * disabling/enabling the device.
1731          */
1732         if (pci_enable_device(pdev)) {
1733                 ret = -EIO;
1734                 goto out;
1735         }
1736
1737         pci_set_master(pdev);
1738
1739         disable_rpm_wakeref_asserts(dev_priv);
1740
1741         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1742                 ret = vlv_resume_prepare(dev_priv, false);
1743         if (ret)
1744                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1745                           ret);
1746
1747         intel_uncore_resume_early(dev_priv);
1748
1749         if (IS_GEN9_LP(dev_priv)) {
1750                 if (!dev_priv->suspended_to_idle)
1751                         gen9_sanitize_dc_state(dev_priv);
1752                 bxt_disable_dc9(dev_priv);
1753         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1754                 hsw_disable_pc8(dev_priv);
1755         }
1756
1757         intel_uncore_sanitize(dev_priv);
1758
1759         if (IS_GEN9_LP(dev_priv) ||
1760             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1761                 intel_power_domains_init_hw(dev_priv, true);
1762
1763         i915_gem_sanitize(dev_priv);
1764
1765         enable_rpm_wakeref_asserts(dev_priv);
1766
1767 out:
1768         dev_priv->suspended_to_idle = false;
1769
1770         return ret;
1771 }
1772
1773 static int i915_resume_switcheroo(struct drm_device *dev)
1774 {
1775         int ret;
1776
1777         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1778                 return 0;
1779
1780         ret = i915_drm_resume_early(dev);
1781         if (ret)
1782                 return ret;
1783
1784         return i915_drm_resume(dev);
1785 }
1786
1787 /**
1788  * i915_reset - reset chip after a hang
1789  * @dev_priv: device private to reset
1790  *
1791  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1792  * on failure.
1793  *
1794  * Caller must hold the struct_mutex.
1795  *
1796  * Procedure is fairly simple:
1797  *   - reset the chip using the reset reg
1798  *   - re-init context state
1799  *   - re-init hardware status page
1800  *   - re-init ring buffer
1801  *   - re-init interrupt state
1802  *   - re-init display
1803  */
1804 void i915_reset(struct drm_i915_private *dev_priv)
1805 {
1806         struct i915_gpu_error *error = &dev_priv->gpu_error;
1807         int ret;
1808
1809         lockdep_assert_held(&dev_priv->drm.struct_mutex);
1810         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1811
1812         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1813                 return;
1814
1815         /* Clear any previous failed attempts at recovery. Time to try again. */
1816         if (!i915_gem_unset_wedged(dev_priv))
1817                 goto wakeup;
1818
1819         error->reset_count++;
1820
1821         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1822         disable_irq(dev_priv->drm.irq);
1823         ret = i915_gem_reset_prepare(dev_priv);
1824         if (ret) {
1825                 DRM_ERROR("GPU recovery failed\n");
1826                 intel_gpu_reset(dev_priv, ALL_ENGINES);
1827                 goto error;
1828         }
1829
1830         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1831         if (ret) {
1832                 if (ret != -ENODEV)
1833                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1834                 else
1835                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1836                 goto error;
1837         }
1838
1839         i915_gem_reset(dev_priv);
1840         intel_overlay_reset(dev_priv);
1841
1842         /* Ok, now get things going again... */
1843
1844         /*
1845          * Everything depends on having the GTT running, so we need to start
1846          * there.  Fortunately we don't need to do this unless we reset the
1847          * chip at a PCI level.
1848          *
1849          * Next we need to restore the context, but we don't use those
1850          * yet either...
1851          *
1852          * Ring buffer needs to be re-initialized in the KMS case, or if X
1853          * was running at the time of the reset (i.e. we weren't VT
1854          * switched away).
1855          */
1856         ret = i915_gem_init_hw(dev_priv);
1857         if (ret) {
1858                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1859                 goto error;
1860         }
1861
1862         i915_queue_hangcheck(dev_priv);
1863
1864 finish:
1865         i915_gem_reset_finish(dev_priv);
1866         enable_irq(dev_priv->drm.irq);
1867
1868 wakeup:
1869         clear_bit(I915_RESET_HANDOFF, &error->flags);
1870         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1871         return;
1872
1873 error:
1874         i915_gem_set_wedged(dev_priv);
1875         goto finish;
1876 }
1877
1878 static int i915_pm_suspend(struct device *kdev)
1879 {
1880         struct pci_dev *pdev = to_pci_dev(kdev);
1881         struct drm_device *dev = pci_get_drvdata(pdev);
1882
1883         if (!dev) {
1884                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1885                 return -ENODEV;
1886         }
1887
1888         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1889                 return 0;
1890
1891         return i915_drm_suspend(dev);
1892 }
1893
1894 static int i915_pm_suspend_late(struct device *kdev)
1895 {
1896         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1897
1898         /*
1899          * We have a suspend ordering issue with the snd-hda driver also
1900          * requiring our device to be power up. Due to the lack of a
1901          * parent/child relationship we currently solve this with an late
1902          * suspend hook.
1903          *
1904          * FIXME: This should be solved with a special hdmi sink device or
1905          * similar so that power domains can be employed.
1906          */
1907         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1908                 return 0;
1909
1910         return i915_drm_suspend_late(dev, false);
1911 }
1912
1913 static int i915_pm_poweroff_late(struct device *kdev)
1914 {
1915         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1916
1917         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1918                 return 0;
1919
1920         return i915_drm_suspend_late(dev, true);
1921 }
1922
1923 static int i915_pm_resume_early(struct device *kdev)
1924 {
1925         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1926
1927         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1928                 return 0;
1929
1930         return i915_drm_resume_early(dev);
1931 }
1932
1933 static int i915_pm_resume(struct device *kdev)
1934 {
1935         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1936
1937         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1938                 return 0;
1939
1940         return i915_drm_resume(dev);
1941 }
1942
1943 /* freeze: before creating the hibernation_image */
1944 static int i915_pm_freeze(struct device *kdev)
1945 {
1946         int ret;
1947
1948         ret = i915_pm_suspend(kdev);
1949         if (ret)
1950                 return ret;
1951
1952         ret = i915_gem_freeze(kdev_to_i915(kdev));
1953         if (ret)
1954                 return ret;
1955
1956         return 0;
1957 }
1958
1959 static int i915_pm_freeze_late(struct device *kdev)
1960 {
1961         int ret;
1962
1963         ret = i915_pm_suspend_late(kdev);
1964         if (ret)
1965                 return ret;
1966
1967         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
1968         if (ret)
1969                 return ret;
1970
1971         return 0;
1972 }
1973
1974 /* thaw: called after creating the hibernation image, but before turning off. */
1975 static int i915_pm_thaw_early(struct device *kdev)
1976 {
1977         return i915_pm_resume_early(kdev);
1978 }
1979
1980 static int i915_pm_thaw(struct device *kdev)
1981 {
1982         return i915_pm_resume(kdev);
1983 }
1984
1985 /* restore: called after loading the hibernation image. */
1986 static int i915_pm_restore_early(struct device *kdev)
1987 {
1988         return i915_pm_resume_early(kdev);
1989 }
1990
1991 static int i915_pm_restore(struct device *kdev)
1992 {
1993         return i915_pm_resume(kdev);
1994 }
1995
1996 /*
1997  * Save all Gunit registers that may be lost after a D3 and a subsequent
1998  * S0i[R123] transition. The list of registers needing a save/restore is
1999  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2000  * registers in the following way:
2001  * - Driver: saved/restored by the driver
2002  * - Punit : saved/restored by the Punit firmware
2003  * - No, w/o marking: no need to save/restore, since the register is R/O or
2004  *                    used internally by the HW in a way that doesn't depend
2005  *                    keeping the content across a suspend/resume.
2006  * - Debug : used for debugging
2007  *
2008  * We save/restore all registers marked with 'Driver', with the following
2009  * exceptions:
2010  * - Registers out of use, including also registers marked with 'Debug'.
2011  *   These have no effect on the driver's operation, so we don't save/restore
2012  *   them to reduce the overhead.
2013  * - Registers that are fully setup by an initialization function called from
2014  *   the resume path. For example many clock gating and RPS/RC6 registers.
2015  * - Registers that provide the right functionality with their reset defaults.
2016  *
2017  * TODO: Except for registers that based on the above 3 criteria can be safely
2018  * ignored, we save/restore all others, practically treating the HW context as
2019  * a black-box for the driver. Further investigation is needed to reduce the
2020  * saved/restored registers even further, by following the same 3 criteria.
2021  */
2022 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2023 {
2024         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2025         int i;
2026
2027         /* GAM 0x4000-0x4770 */
2028         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2029         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2030         s->arb_mode             = I915_READ(ARB_MODE);
2031         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2032         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2033
2034         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2035                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2036
2037         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2038         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2039
2040         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2041         s->ecochk               = I915_READ(GAM_ECOCHK);
2042         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2043         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2044
2045         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2046
2047         /* MBC 0x9024-0x91D0, 0x8500 */
2048         s->g3dctl               = I915_READ(VLV_G3DCTL);
2049         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2050         s->mbctl                = I915_READ(GEN6_MBCTL);
2051
2052         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2053         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2054         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2055         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2056         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2057         s->rstctl               = I915_READ(GEN6_RSTCTL);
2058         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2059
2060         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2061         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2062         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2063         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2064         s->ecobus               = I915_READ(ECOBUS);
2065         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2066         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2067         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2068         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2069         s->rcedata              = I915_READ(VLV_RCEDATA);
2070         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2071
2072         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2073         s->gt_imr               = I915_READ(GTIMR);
2074         s->gt_ier               = I915_READ(GTIER);
2075         s->pm_imr               = I915_READ(GEN6_PMIMR);
2076         s->pm_ier               = I915_READ(GEN6_PMIER);
2077
2078         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2079                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2080
2081         /* GT SA CZ domain, 0x100000-0x138124 */
2082         s->tilectl              = I915_READ(TILECTL);
2083         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2084         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2085         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2086         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2087
2088         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2089         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2090         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2091         s->pcbr                 = I915_READ(VLV_PCBR);
2092         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2093
2094         /*
2095          * Not saving any of:
2096          * DFT,         0x9800-0x9EC0
2097          * SARB,        0xB000-0xB1FC
2098          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2099          * PCI CFG
2100          */
2101 }
2102
2103 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2104 {
2105         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2106         u32 val;
2107         int i;
2108
2109         /* GAM 0x4000-0x4770 */
2110         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2111         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2112         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2113         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2114         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2115
2116         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2117                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2118
2119         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2120         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2121
2122         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2123         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2124         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2125         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2126
2127         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2128
2129         /* MBC 0x9024-0x91D0, 0x8500 */
2130         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2131         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2132         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2133
2134         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2135         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2136         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2137         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2138         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2139         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2140         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2141
2142         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2143         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2144         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2145         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2146         I915_WRITE(ECOBUS,              s->ecobus);
2147         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2148         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2149         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2150         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2151         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2152         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2153
2154         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2155         I915_WRITE(GTIMR,               s->gt_imr);
2156         I915_WRITE(GTIER,               s->gt_ier);
2157         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2158         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2159
2160         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2161                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2162
2163         /* GT SA CZ domain, 0x100000-0x138124 */
2164         I915_WRITE(TILECTL,                     s->tilectl);
2165         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2166         /*
2167          * Preserve the GT allow wake and GFX force clock bit, they are not
2168          * be restored, as they are used to control the s0ix suspend/resume
2169          * sequence by the caller.
2170          */
2171         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2172         val &= VLV_GTLC_ALLOWWAKEREQ;
2173         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2174         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2175
2176         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2177         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2178         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2179         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2180
2181         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2182
2183         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2184         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2185         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2186         I915_WRITE(VLV_PCBR,                    s->pcbr);
2187         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2188 }
2189
2190 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2191                                   u32 mask, u32 val)
2192 {
2193         /* The HW does not like us polling for PW_STATUS frequently, so
2194          * use the sleeping loop rather than risk the busy spin within
2195          * intel_wait_for_register().
2196          *
2197          * Transitioning between RC6 states should be at most 2ms (see
2198          * valleyview_enable_rps) so use a 3ms timeout.
2199          */
2200         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2201                         3);
2202 }
2203
2204 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2205 {
2206         u32 val;
2207         int err;
2208
2209         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2210         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2211         if (force_on)
2212                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2213         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2214
2215         if (!force_on)
2216                 return 0;
2217
2218         err = intel_wait_for_register(dev_priv,
2219                                       VLV_GTLC_SURVIVABILITY_REG,
2220                                       VLV_GFX_CLK_STATUS_BIT,
2221                                       VLV_GFX_CLK_STATUS_BIT,
2222                                       20);
2223         if (err)
2224                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2225                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2226
2227         return err;
2228 }
2229
2230 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2231 {
2232         u32 mask;
2233         u32 val;
2234         int err;
2235
2236         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2237         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2238         if (allow)
2239                 val |= VLV_GTLC_ALLOWWAKEREQ;
2240         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2241         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2242
2243         mask = VLV_GTLC_ALLOWWAKEACK;
2244         val = allow ? mask : 0;
2245
2246         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2247         if (err)
2248                 DRM_ERROR("timeout disabling GT waking\n");
2249
2250         return err;
2251 }
2252
2253 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2254                                   bool wait_for_on)
2255 {
2256         u32 mask;
2257         u32 val;
2258
2259         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2260         val = wait_for_on ? mask : 0;
2261
2262         /*
2263          * RC6 transitioning can be delayed up to 2 msec (see
2264          * valleyview_enable_rps), use 3 msec for safety.
2265          */
2266         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2267                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2268                           onoff(wait_for_on));
2269 }
2270
2271 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2272 {
2273         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2274                 return;
2275
2276         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2277         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2278 }
2279
2280 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2281 {
2282         u32 mask;
2283         int err;
2284
2285         /*
2286          * Bspec defines the following GT well on flags as debug only, so
2287          * don't treat them as hard failures.
2288          */
2289         vlv_wait_for_gt_wells(dev_priv, false);
2290
2291         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2292         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2293
2294         vlv_check_no_gt_access(dev_priv);
2295
2296         err = vlv_force_gfx_clock(dev_priv, true);
2297         if (err)
2298                 goto err1;
2299
2300         err = vlv_allow_gt_wake(dev_priv, false);
2301         if (err)
2302                 goto err2;
2303
2304         if (!IS_CHERRYVIEW(dev_priv))
2305                 vlv_save_gunit_s0ix_state(dev_priv);
2306
2307         err = vlv_force_gfx_clock(dev_priv, false);
2308         if (err)
2309                 goto err2;
2310
2311         return 0;
2312
2313 err2:
2314         /* For safety always re-enable waking and disable gfx clock forcing */
2315         vlv_allow_gt_wake(dev_priv, true);
2316 err1:
2317         vlv_force_gfx_clock(dev_priv, false);
2318
2319         return err;
2320 }
2321
2322 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2323                                 bool rpm_resume)
2324 {
2325         int err;
2326         int ret;
2327
2328         /*
2329          * If any of the steps fail just try to continue, that's the best we
2330          * can do at this point. Return the first error code (which will also
2331          * leave RPM permanently disabled).
2332          */
2333         ret = vlv_force_gfx_clock(dev_priv, true);
2334
2335         if (!IS_CHERRYVIEW(dev_priv))
2336                 vlv_restore_gunit_s0ix_state(dev_priv);
2337
2338         err = vlv_allow_gt_wake(dev_priv, true);
2339         if (!ret)
2340                 ret = err;
2341
2342         err = vlv_force_gfx_clock(dev_priv, false);
2343         if (!ret)
2344                 ret = err;
2345
2346         vlv_check_no_gt_access(dev_priv);
2347
2348         if (rpm_resume)
2349                 intel_init_clock_gating(dev_priv);
2350
2351         return ret;
2352 }
2353
2354 static int intel_runtime_suspend(struct device *kdev)
2355 {
2356         struct pci_dev *pdev = to_pci_dev(kdev);
2357         struct drm_device *dev = pci_get_drvdata(pdev);
2358         struct drm_i915_private *dev_priv = to_i915(dev);
2359         int ret;
2360
2361         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2362                 return -ENODEV;
2363
2364         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2365                 return -ENODEV;
2366
2367         DRM_DEBUG_KMS("Suspending device\n");
2368
2369         disable_rpm_wakeref_asserts(dev_priv);
2370
2371         /*
2372          * We are safe here against re-faults, since the fault handler takes
2373          * an RPM reference.
2374          */
2375         i915_gem_runtime_suspend(dev_priv);
2376
2377         intel_guc_suspend(dev_priv);
2378
2379         intel_runtime_pm_disable_interrupts(dev_priv);
2380
2381         ret = 0;
2382         if (IS_GEN9_LP(dev_priv)) {
2383                 bxt_display_core_uninit(dev_priv);
2384                 bxt_enable_dc9(dev_priv);
2385         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2386                 hsw_enable_pc8(dev_priv);
2387         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2388                 ret = vlv_suspend_complete(dev_priv);
2389         }
2390
2391         if (ret) {
2392                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2393                 intel_runtime_pm_enable_interrupts(dev_priv);
2394
2395                 enable_rpm_wakeref_asserts(dev_priv);
2396
2397                 return ret;
2398         }
2399
2400         intel_uncore_suspend(dev_priv);
2401
2402         enable_rpm_wakeref_asserts(dev_priv);
2403         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2404
2405         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2406                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2407
2408         dev_priv->pm.suspended = true;
2409
2410         /*
2411          * FIXME: We really should find a document that references the arguments
2412          * used below!
2413          */
2414         if (IS_BROADWELL(dev_priv)) {
2415                 /*
2416                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2417                  * being detected, and the call we do at intel_runtime_resume()
2418                  * won't be able to restore them. Since PCI_D3hot matches the
2419                  * actual specification and appears to be working, use it.
2420                  */
2421                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2422         } else {
2423                 /*
2424                  * current versions of firmware which depend on this opregion
2425                  * notification have repurposed the D1 definition to mean
2426                  * "runtime suspended" vs. what you would normally expect (D3)
2427                  * to distinguish it from notifications that might be sent via
2428                  * the suspend path.
2429                  */
2430                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2431         }
2432
2433         assert_forcewakes_inactive(dev_priv);
2434
2435         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2436                 intel_hpd_poll_init(dev_priv);
2437
2438         DRM_DEBUG_KMS("Device suspended\n");
2439         return 0;
2440 }
2441
2442 static int intel_runtime_resume(struct device *kdev)
2443 {
2444         struct pci_dev *pdev = to_pci_dev(kdev);
2445         struct drm_device *dev = pci_get_drvdata(pdev);
2446         struct drm_i915_private *dev_priv = to_i915(dev);
2447         int ret = 0;
2448
2449         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2450                 return -ENODEV;
2451
2452         DRM_DEBUG_KMS("Resuming device\n");
2453
2454         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2455         disable_rpm_wakeref_asserts(dev_priv);
2456
2457         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2458         dev_priv->pm.suspended = false;
2459         if (intel_uncore_unclaimed_mmio(dev_priv))
2460                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2461
2462         intel_guc_resume(dev_priv);
2463
2464         if (IS_GEN6(dev_priv))
2465                 intel_init_pch_refclk(dev_priv);
2466
2467         if (IS_GEN9_LP(dev_priv)) {
2468                 bxt_disable_dc9(dev_priv);
2469                 bxt_display_core_init(dev_priv, true);
2470                 if (dev_priv->csr.dmc_payload &&
2471                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2472                         gen9_enable_dc5(dev_priv);
2473         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2474                 hsw_disable_pc8(dev_priv);
2475         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2476                 ret = vlv_resume_prepare(dev_priv, true);
2477         }
2478
2479         /*
2480          * No point of rolling back things in case of an error, as the best
2481          * we can do is to hope that things will still work (and disable RPM).
2482          */
2483         i915_gem_init_swizzling(dev_priv);
2484         i915_gem_restore_fences(dev_priv);
2485
2486         intel_runtime_pm_enable_interrupts(dev_priv);
2487
2488         /*
2489          * On VLV/CHV display interrupts are part of the display
2490          * power well, so hpd is reinitialized from there. For
2491          * everyone else do it here.
2492          */
2493         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2494                 intel_hpd_init(dev_priv);
2495
2496         enable_rpm_wakeref_asserts(dev_priv);
2497
2498         if (ret)
2499                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2500         else
2501                 DRM_DEBUG_KMS("Device resumed\n");
2502
2503         return ret;
2504 }
2505
2506 const struct dev_pm_ops i915_pm_ops = {
2507         /*
2508          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2509          * PMSG_RESUME]
2510          */
2511         .suspend = i915_pm_suspend,
2512         .suspend_late = i915_pm_suspend_late,
2513         .resume_early = i915_pm_resume_early,
2514         .resume = i915_pm_resume,
2515
2516         /*
2517          * S4 event handlers
2518          * @freeze, @freeze_late    : called (1) before creating the
2519          *                            hibernation image [PMSG_FREEZE] and
2520          *                            (2) after rebooting, before restoring
2521          *                            the image [PMSG_QUIESCE]
2522          * @thaw, @thaw_early       : called (1) after creating the hibernation
2523          *                            image, before writing it [PMSG_THAW]
2524          *                            and (2) after failing to create or
2525          *                            restore the image [PMSG_RECOVER]
2526          * @poweroff, @poweroff_late: called after writing the hibernation
2527          *                            image, before rebooting [PMSG_HIBERNATE]
2528          * @restore, @restore_early : called after rebooting and restoring the
2529          *                            hibernation image [PMSG_RESTORE]
2530          */
2531         .freeze = i915_pm_freeze,
2532         .freeze_late = i915_pm_freeze_late,
2533         .thaw_early = i915_pm_thaw_early,
2534         .thaw = i915_pm_thaw,
2535         .poweroff = i915_pm_suspend,
2536         .poweroff_late = i915_pm_poweroff_late,
2537         .restore_early = i915_pm_restore_early,
2538         .restore = i915_pm_restore,
2539
2540         /* S0ix (via runtime suspend) event handlers */
2541         .runtime_suspend = intel_runtime_suspend,
2542         .runtime_resume = intel_runtime_resume,
2543 };
2544
2545 static const struct vm_operations_struct i915_gem_vm_ops = {
2546         .fault = i915_gem_fault,
2547         .open = drm_gem_vm_open,
2548         .close = drm_gem_vm_close,
2549 };
2550
2551 static const struct file_operations i915_driver_fops = {
2552         .owner = THIS_MODULE,
2553         .open = drm_open,
2554         .release = drm_release,
2555         .unlocked_ioctl = drm_ioctl,
2556         .mmap = drm_gem_mmap,
2557         .poll = drm_poll,
2558         .read = drm_read,
2559         .compat_ioctl = i915_compat_ioctl,
2560         .llseek = noop_llseek,
2561 };
2562
2563 static int
2564 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2565                           struct drm_file *file)
2566 {
2567         return -ENODEV;
2568 }
2569
2570 static const struct drm_ioctl_desc i915_ioctls[] = {
2571         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2572         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2573         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2574         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2575         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2576         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2577         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2578         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2579         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2580         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2581         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2582         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2583         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2584         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2585         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2586         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2587         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2588         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2589         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2590         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2591         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2592         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2593         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2594         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2595         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2596         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2597         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2598         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2599         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2600         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2601         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2602         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2603         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2604         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2605         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2606         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2607         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2608         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2609         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2610         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2611         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2612         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2613         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2614         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2615         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2616         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2617         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2618         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2619         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2620         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2621         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2622         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2623         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2624 };
2625
2626 static struct drm_driver driver = {
2627         /* Don't use MTRRs here; the Xserver or userspace app should
2628          * deal with them for Intel hardware.
2629          */
2630         .driver_features =
2631             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2632             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC,
2633         .release = i915_driver_release,
2634         .open = i915_driver_open,
2635         .lastclose = i915_driver_lastclose,
2636         .postclose = i915_driver_postclose,
2637         .set_busid = drm_pci_set_busid,
2638
2639         .gem_close_object = i915_gem_close_object,
2640         .gem_free_object_unlocked = i915_gem_free_object,
2641         .gem_vm_ops = &i915_gem_vm_ops,
2642
2643         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2644         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2645         .gem_prime_export = i915_gem_prime_export,
2646         .gem_prime_import = i915_gem_prime_import,
2647
2648         .dumb_create = i915_gem_dumb_create,
2649         .dumb_map_offset = i915_gem_mmap_gtt,
2650         .dumb_destroy = drm_gem_dumb_destroy,
2651         .ioctls = i915_ioctls,
2652         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2653         .fops = &i915_driver_fops,
2654         .name = DRIVER_NAME,
2655         .desc = DRIVER_DESC,
2656         .date = DRIVER_DATE,
2657         .major = DRIVER_MAJOR,
2658         .minor = DRIVER_MINOR,
2659         .patchlevel = DRIVER_PATCHLEVEL,
2660 };
2661
2662 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2663 #include "selftests/mock_drm.c"
2664 #endif