drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include "drm_crtc_helper.h"
  39
  40 static int i915_modeset = -1;
  41 module_param_named(modeset, i915_modeset, int, 0400);
  42
  43 unsigned int i915_fbpercrtc = 0;
  44 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  45
  46 int i915_panel_ignore_lid = 0;
  47 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  48
  49 unsigned int i915_powersave = 1;
  50 module_param_named(powersave, i915_powersave, int, 0600);
  51
  52 unsigned int i915_semaphores = 1;
  53 module_param_named(semaphores, i915_semaphores, int, 0600);
  54
  55 unsigned int i915_enable_rc6 = 0;
  56 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
  57
  58 unsigned int i915_lvds_downclock = 0;
  59 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  60
  61 unsigned int i915_panel_use_ssc = 1;
  62 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  63
  64 int i915_vbt_sdvo_panel_type = -1;
  65 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
  66
  67 static bool i915_try_reset = true;
  68 module_param_named(reset, i915_try_reset, bool, 0600);
  69
  70 static struct drm_driver driver;
  71 extern int intel_agp_enabled;
  72
  73 #define INTEL_VGA_DEVICE(id, info) {            \
  74         .class = PCI_CLASS_DISPLAY_VGA << 8,    \
  75         .class_mask = 0xff0000,                 \
  76         .vendor = 0x8086,                       \
  77         .device = id,                           \
  78         .subvendor = PCI_ANY_ID,                \
  79         .subdevice = PCI_ANY_ID,                \
  80         .driver_data = (unsigned long) info }
  81
  82 static const struct intel_device_info intel_i830_info = {
  83         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
  84         .has_overlay = 1, .overlay_needs_physical = 1,
  85 };
  86
  87 static const struct intel_device_info intel_845g_info = {
  88         .gen = 2,
  89         .has_overlay = 1, .overlay_needs_physical = 1,
  90 };
  91
  92 static const struct intel_device_info intel_i85x_info = {
  93         .gen = 2, .is_i85x = 1, .is_mobile = 1,
  94         .cursor_needs_physical = 1,
  95         .has_overlay = 1, .overlay_needs_physical = 1,
  96 };
  97
  98 static const struct intel_device_info intel_i865g_info = {
  99         .gen = 2,
 100         .has_overlay = 1, .overlay_needs_physical = 1,
 101 };
 102
 103 static const struct intel_device_info intel_i915g_info = {
 104         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 105         .has_overlay = 1, .overlay_needs_physical = 1,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112 };
 113 static const struct intel_device_info intel_i945g_info = {
 114         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 115         .has_overlay = 1, .overlay_needs_physical = 1,
 116 };
 117 static const struct intel_device_info intel_i945gm_info = {
 118         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 119         .has_hotplug = 1, .cursor_needs_physical = 1,
 120         .has_overlay = 1, .overlay_needs_physical = 1,
 121         .supports_tv = 1,
 122 };
 123
 124 static const struct intel_device_info intel_i965g_info = {
 125         .gen = 4, .is_broadwater = 1,
 126         .has_hotplug = 1,
 127         .has_overlay = 1,
 128 };
 129
 130 static const struct intel_device_info intel_i965gm_info = {
 131         .gen = 4, .is_crestline = 1,
 132         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 133         .has_overlay = 1,
 134         .supports_tv = 1,
 135 };
 136
 137 static const struct intel_device_info intel_g33_info = {
 138         .gen = 3, .is_g33 = 1,
 139         .need_gfx_hws = 1, .has_hotplug = 1,
 140         .has_overlay = 1,
 141 };
 142
 143 static const struct intel_device_info intel_g45_info = {
 144         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 145         .has_pipe_cxsr = 1, .has_hotplug = 1,
 146         .has_bsd_ring = 1,
 147 };
 148
 149 static const struct intel_device_info intel_gm45_info = {
 150         .gen = 4, .is_g4x = 1,
 151         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 152         .has_pipe_cxsr = 1, .has_hotplug = 1,
 153         .supports_tv = 1,
 154         .has_bsd_ring = 1,
 155 };
 156
 157 static const struct intel_device_info intel_pineview_info = {
 158         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 159         .need_gfx_hws = 1, .has_hotplug = 1,
 160         .has_overlay = 1,
 161 };
 162
 163 static const struct intel_device_info intel_ironlake_d_info = {
 164         .gen = 5,
 165         .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .has_bsd_ring = 1,
 167 };
 168
 169 static const struct intel_device_info intel_ironlake_m_info = {
 170         .gen = 5, .is_mobile = 1,
 171         .need_gfx_hws = 1, .has_hotplug = 1,
 172         .has_fbc = 0, /* disabled due to buggy hardware */
 173         .has_bsd_ring = 1,
 174 };
 175
 176 static const struct intel_device_info intel_sandybridge_d_info = {
 177         .gen = 6,
 178         .need_gfx_hws = 1, .has_hotplug = 1,
 179         .has_bsd_ring = 1,
 180         .has_blt_ring = 1,
 181 };
 182
 183 static const struct intel_device_info intel_sandybridge_m_info = {
 184         .gen = 6, .is_mobile = 1,
 185         .need_gfx_hws = 1, .has_hotplug = 1,
 186         .has_fbc = 1,
 187         .has_bsd_ring = 1,
 188         .has_blt_ring = 1,
 189 };
 190
 191 static const struct pci_device_id pciidlist[] = {               /* aka */
 192         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 193         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 194         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 195         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 196         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 197         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 198         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 199         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 200         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 201         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 202         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 203         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 204         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 205         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 206         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 207         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 208         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 209         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 210         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 211         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 212         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 213         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 214         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 215         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 216         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 217         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 218         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 219         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 220         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 221         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 222         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 223         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 224         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 225         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 226         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 227         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 228         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 229         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 230         {0, 0, 0}
 231 };
 232
 233 #if defined(CONFIG_DRM_I915_KMS)
 234 MODULE_DEVICE_TABLE(pci, pciidlist);
 235 #endif
 236
 237 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 238 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 239 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 240
 241 void intel_detect_pch (struct drm_device *dev)
 242 {
 243         struct drm_i915_private *dev_priv = dev->dev_private;
 244         struct pci_dev *pch;
 245
 246         /*
 247          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 248          * make graphics device passthrough work easy for VMM, that only
 249          * need to expose ISA bridge to let driver know the real hardware
 250          * underneath. This is a requirement from virtualization team.
 251          */
 252         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 253         if (pch) {
 254                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 255                         int id;
 256                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 257
 258                         if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 259                                 dev_priv->pch_type = PCH_CPT;
 260                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 261                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 262                                 /* PantherPoint is CPT compatible */
 263                                 dev_priv->pch_type = PCH_CPT;
 264                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 265                         }
 266                 }
 267                 pci_dev_put(pch);
 268         }
 269 }
 270
 271 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 272 {
 273         int count;
 274
 275         count = 0;
 276         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 277                 udelay(10);
 278
 279         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 280         POSTING_READ(FORCEWAKE);
 281
 282         count = 0;
 283         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 284                 udelay(10);
 285 }
 286
 287 /*
 288  * Generally this is called implicitly by the register read function. However,
 289  * if some sequence requires the GT to not power down then this function should
 290  * be called at the beginning of the sequence followed by a call to
 291  * gen6_gt_force_wake_put() at the end of the sequence.
 292  */
 293 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 294 {
 295         WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
 296
 297         /* Forcewake is atomic in case we get in here without the lock */
 298         if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
 299                 __gen6_gt_force_wake_get(dev_priv);
 300 }
 301
 302 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 303 {
 304         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 305         POSTING_READ(FORCEWAKE);
 306 }
 307
 308 /*
 309  * see gen6_gt_force_wake_get()
 310  */
 311 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 312 {
 313         WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
 314
 315         if (atomic_dec_and_test(&dev_priv->forcewake_count))
 316                 __gen6_gt_force_wake_put(dev_priv);
 317 }
 318
 319 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 320 {
 321         int loop = 500;
 322         u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 323         while (fifo < 20 && loop--) {
 324                 udelay(10);
 325                 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 326         }
 327 }
 328
 329 static int i915_drm_freeze(struct drm_device *dev)
 330 {
 331         struct drm_i915_private *dev_priv = dev->dev_private;
 332
 333         drm_kms_helper_poll_disable(dev);
 334
 335         pci_save_state(dev->pdev);
 336
 337         /* If KMS is active, we do the leavevt stuff here */
 338         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 339                 int error = i915_gem_idle(dev);
 340                 if (error) {
 341                         dev_err(&dev->pdev->dev,
 342                                 "GEM idle failed, resume might fail\n");
 343                         return error;
 344                 }
 345                 drm_irq_uninstall(dev);
 346         }
 347
 348         i915_save_state(dev);
 349
 350         intel_opregion_fini(dev);
 351
 352         /* Modeset on resume, not lid events */
 353         dev_priv->modeset_on_lid = 0;
 354
 355         return 0;
 356 }
 357
 358 int i915_suspend(struct drm_device *dev, pm_message_t state)
 359 {
 360         int error;
 361
 362         if (!dev || !dev->dev_private) {
 363                 DRM_ERROR("dev: %p\n", dev);
 364                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 365                 return -ENODEV;
 366         }
 367
 368         if (state.event == PM_EVENT_PRETHAW)
 369                 return 0;
 370
 371
 372         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 373                 return 0;
 374
 375         error = i915_drm_freeze(dev);
 376         if (error)
 377                 return error;
 378
 379         if (state.event == PM_EVENT_SUSPEND) {
 380                 /* Shut down the device */
 381                 pci_disable_device(dev->pdev);
 382                 pci_set_power_state(dev->pdev, PCI_D3hot);
 383         }
 384
 385         return 0;
 386 }
 387
 388 static int i915_drm_thaw(struct drm_device *dev)
 389 {
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         int error = 0;
 392
 393         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 394                 mutex_lock(&dev->struct_mutex);
 395                 i915_gem_restore_gtt_mappings(dev);
 396                 mutex_unlock(&dev->struct_mutex);
 397         }
 398
 399         i915_restore_state(dev);
 400         intel_opregion_setup(dev);
 401
 402         /* KMS EnterVT equivalent */
 403         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 404                 mutex_lock(&dev->struct_mutex);
 405                 dev_priv->mm.suspended = 0;
 406
 407                 error = i915_gem_init_ringbuffer(dev);
 408                 mutex_unlock(&dev->struct_mutex);
 409
 410                 drm_mode_config_reset(dev);
 411                 drm_irq_install(dev);
 412
 413                 /* Resume the modeset for every activated CRTC */
 414                 drm_helper_resume_force_mode(dev);
 415
 416                 if (IS_IRONLAKE_M(dev))
 417                         ironlake_enable_rc6(dev);
 418         }
 419
 420         intel_opregion_init(dev);
 421
 422         dev_priv->modeset_on_lid = 0;
 423
 424         return error;
 425 }
 426
 427 int i915_resume(struct drm_device *dev)
 428 {
 429         int ret;
 430
 431         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 432                 return 0;
 433
 434         if (pci_enable_device(dev->pdev))
 435                 return -EIO;
 436
 437         pci_set_master(dev->pdev);
 438
 439         ret = i915_drm_thaw(dev);
 440         if (ret)
 441                 return ret;
 442
 443         drm_kms_helper_poll_enable(dev);
 444         return 0;
 445 }
 446
 447 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 448 {
 449         struct drm_i915_private *dev_priv = dev->dev_private;
 450
 451         if (IS_I85X(dev))
 452                 return -ENODEV;
 453
 454         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 455         POSTING_READ(D_STATE);
 456
 457         if (IS_I830(dev) || IS_845G(dev)) {
 458                 I915_WRITE(DEBUG_RESET_I830,
 459                            DEBUG_RESET_DISPLAY |
 460                            DEBUG_RESET_RENDER |
 461                            DEBUG_RESET_FULL);
 462                 POSTING_READ(DEBUG_RESET_I830);
 463                 msleep(1);
 464
 465                 I915_WRITE(DEBUG_RESET_I830, 0);
 466                 POSTING_READ(DEBUG_RESET_I830);
 467         }
 468
 469         msleep(1);
 470
 471         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 472         POSTING_READ(D_STATE);
 473
 474         return 0;
 475 }
 476
 477 static int i965_reset_complete(struct drm_device *dev)
 478 {
 479         u8 gdrst;
 480         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 481         return gdrst & 0x1;
 482 }
 483
 484 static int i965_do_reset(struct drm_device *dev, u8 flags)
 485 {
 486         u8 gdrst;
 487
 488         /*
 489          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 490          * well as the reset bit (GR/bit 0).  Setting the GR bit
 491          * triggers the reset; when done, the hardware will clear it.
 492          */
 493         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 494         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 495
 496         return wait_for(i965_reset_complete(dev), 500);
 497 }
 498
 499 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 500 {
 501         struct drm_i915_private *dev_priv = dev->dev_private;
 502         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 503         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 504         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 505 }
 506
 507 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 508 {
 509         struct drm_i915_private *dev_priv = dev->dev_private;
 510
 511         I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
 512         return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 513 }
 514
 515 /**
 516  * i965_reset - reset chip after a hang
 517  * @dev: drm device to reset
 518  * @flags: reset domains
 519  *
 520  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 521  * reset or otherwise an error code.
 522  *
 523  * Procedure is fairly simple:
 524  *   - reset the chip using the reset reg
 525  *   - re-init context state
 526  *   - re-init hardware status page
 527  *   - re-init ring buffer
 528  *   - re-init interrupt state
 529  *   - re-init display
 530  */
 531 int i915_reset(struct drm_device *dev, u8 flags)
 532 {
 533         drm_i915_private_t *dev_priv = dev->dev_private;
 534         /*
 535          * We really should only reset the display subsystem if we actually
 536          * need to
 537          */
 538         bool need_display = true;
 539         int ret;
 540
 541         if (!i915_try_reset)
 542                 return 0;
 543
 544         if (!mutex_trylock(&dev->struct_mutex))
 545                 return -EBUSY;
 546
 547         i915_gem_reset(dev);
 548
 549         ret = -ENODEV;
 550         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 551                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 552         } else switch (INTEL_INFO(dev)->gen) {
 553         case 6:
 554                 ret = gen6_do_reset(dev, flags);
 555                 break;
 556         case 5:
 557                 ret = ironlake_do_reset(dev, flags);
 558                 break;
 559         case 4:
 560                 ret = i965_do_reset(dev, flags);
 561                 break;
 562         case 2:
 563                 ret = i8xx_do_reset(dev, flags);
 564                 break;
 565         }
 566         dev_priv->last_gpu_reset = get_seconds();
 567         if (ret) {
 568                 DRM_ERROR("Failed to reset chip.\n");
 569                 mutex_unlock(&dev->struct_mutex);
 570                 return ret;
 571         }
 572
 573         /* Ok, now get things going again... */
 574
 575         /*
 576          * Everything depends on having the GTT running, so we need to start
 577          * there.  Fortunately we don't need to do this unless we reset the
 578          * chip at a PCI level.
 579          *
 580          * Next we need to restore the context, but we don't use those
 581          * yet either...
 582          *
 583          * Ring buffer needs to be re-initialized in the KMS case, or if X
 584          * was running at the time of the reset (i.e. we weren't VT
 585          * switched away).
 586          */
 587         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 588                         !dev_priv->mm.suspended) {
 589                 dev_priv->mm.suspended = 0;
 590
 591                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 592                 if (HAS_BSD(dev))
 593                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 594                 if (HAS_BLT(dev))
 595                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 596
 597                 mutex_unlock(&dev->struct_mutex);
 598                 drm_irq_uninstall(dev);
 599                 drm_mode_config_reset(dev);
 600                 drm_irq_install(dev);
 601                 mutex_lock(&dev->struct_mutex);
 602         }
 603
 604         mutex_unlock(&dev->struct_mutex);
 605
 606         /*
 607          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 608          * need to retrain the display link and cannot just restore the register
 609          * values.
 610          */
 611         if (need_display) {
 612                 mutex_lock(&dev->mode_config.mutex);
 613                 drm_helper_resume_force_mode(dev);
 614                 mutex_unlock(&dev->mode_config.mutex);
 615         }
 616
 617         return 0;
 618 }
 619
 620
 621 static int __devinit
 622 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 623 {
 624         /* Only bind to function 0 of the device. Early generations
 625          * used function 1 as a placeholder for multi-head. This causes
 626          * us confusion instead, especially on the systems where both
 627          * functions have the same PCI-ID!
 628          */
 629         if (PCI_FUNC(pdev->devfn))
 630                 return -ENODEV;
 631
 632         return drm_get_pci_dev(pdev, ent, &driver);
 633 }
 634
 635 static void
 636 i915_pci_remove(struct pci_dev *pdev)
 637 {
 638         struct drm_device *dev = pci_get_drvdata(pdev);
 639
 640         drm_put_dev(dev);
 641 }
 642
 643 static int i915_pm_suspend(struct device *dev)
 644 {
 645         struct pci_dev *pdev = to_pci_dev(dev);
 646         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 647         int error;
 648
 649         if (!drm_dev || !drm_dev->dev_private) {
 650                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 651                 return -ENODEV;
 652         }
 653
 654         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 655                 return 0;
 656
 657         error = i915_drm_freeze(drm_dev);
 658         if (error)
 659                 return error;
 660
 661         pci_disable_device(pdev);
 662         pci_set_power_state(pdev, PCI_D3hot);
 663
 664         return 0;
 665 }
 666
 667 static int i915_pm_resume(struct device *dev)
 668 {
 669         struct pci_dev *pdev = to_pci_dev(dev);
 670         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 671
 672         return i915_resume(drm_dev);
 673 }
 674
 675 static int i915_pm_freeze(struct device *dev)
 676 {
 677         struct pci_dev *pdev = to_pci_dev(dev);
 678         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 679
 680         if (!drm_dev || !drm_dev->dev_private) {
 681                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 682                 return -ENODEV;
 683         }
 684
 685         return i915_drm_freeze(drm_dev);
 686 }
 687
 688 static int i915_pm_thaw(struct device *dev)
 689 {
 690         struct pci_dev *pdev = to_pci_dev(dev);
 691         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 692
 693         return i915_drm_thaw(drm_dev);
 694 }
 695
 696 static int i915_pm_poweroff(struct device *dev)
 697 {
 698         struct pci_dev *pdev = to_pci_dev(dev);
 699         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 700
 701         return i915_drm_freeze(drm_dev);
 702 }
 703
 704 static const struct dev_pm_ops i915_pm_ops = {
 705      .suspend = i915_pm_suspend,
 706      .resume = i915_pm_resume,
 707      .freeze = i915_pm_freeze,
 708      .thaw = i915_pm_thaw,
 709      .poweroff = i915_pm_poweroff,
 710      .restore = i915_pm_resume,
 711 };
 712
 713 static struct vm_operations_struct i915_gem_vm_ops = {
 714         .fault = i915_gem_fault,
 715         .open = drm_gem_vm_open,
 716         .close = drm_gem_vm_close,
 717 };
 718
 719 static struct drm_driver driver = {
 720         /* don't use mtrr's here, the Xserver or user space app should
 721          * deal with them for intel hardware.
 722          */
 723         .driver_features =
 724             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 725             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 726         .load = i915_driver_load,
 727         .unload = i915_driver_unload,
 728         .open = i915_driver_open,
 729         .lastclose = i915_driver_lastclose,
 730         .preclose = i915_driver_preclose,
 731         .postclose = i915_driver_postclose,
 732
 733         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 734         .suspend = i915_suspend,
 735         .resume = i915_resume,
 736
 737         .device_is_agp = i915_driver_device_is_agp,
 738         .enable_vblank = i915_enable_vblank,
 739         .disable_vblank = i915_disable_vblank,
 740         .get_vblank_timestamp = i915_get_vblank_timestamp,
 741         .get_scanout_position = i915_get_crtc_scanoutpos,
 742         .irq_preinstall = i915_driver_irq_preinstall,
 743         .irq_postinstall = i915_driver_irq_postinstall,
 744         .irq_uninstall = i915_driver_irq_uninstall,
 745         .irq_handler = i915_driver_irq_handler,
 746         .reclaim_buffers = drm_core_reclaim_buffers,
 747         .master_create = i915_master_create,
 748         .master_destroy = i915_master_destroy,
 749 #if defined(CONFIG_DEBUG_FS)
 750         .debugfs_init = i915_debugfs_init,
 751         .debugfs_cleanup = i915_debugfs_cleanup,
 752 #endif
 753         .gem_init_object = i915_gem_init_object,
 754         .gem_free_object = i915_gem_free_object,
 755         .gem_vm_ops = &i915_gem_vm_ops,
 756         .dumb_create = i915_gem_dumb_create,
 757         .dumb_map_offset = i915_gem_mmap_gtt,
 758         .dumb_destroy = i915_gem_dumb_destroy,
 759         .ioctls = i915_ioctls,
 760         .fops = {
 761                  .owner = THIS_MODULE,
 762                  .open = drm_open,
 763                  .release = drm_release,
 764                  .unlocked_ioctl = drm_ioctl,
 765                  .mmap = drm_gem_mmap,
 766                  .poll = drm_poll,
 767                  .fasync = drm_fasync,
 768                  .read = drm_read,
 769 #ifdef CONFIG_COMPAT
 770                  .compat_ioctl = i915_compat_ioctl,
 771 #endif
 772                  .llseek = noop_llseek,
 773         },
 774
 775         .name = DRIVER_NAME,
 776         .desc = DRIVER_DESC,
 777         .date = DRIVER_DATE,
 778         .major = DRIVER_MAJOR,
 779         .minor = DRIVER_MINOR,
 780         .patchlevel = DRIVER_PATCHLEVEL,
 781 };
 782
 783 static struct pci_driver i915_pci_driver = {
 784         .name = DRIVER_NAME,
 785         .id_table = pciidlist,
 786         .probe = i915_pci_probe,
 787         .remove = i915_pci_remove,
 788         .driver.pm = &i915_pm_ops,
 789 };
 790
 791 static int __init i915_init(void)
 792 {
 793         if (!intel_agp_enabled) {
 794                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 795                 return -ENODEV;
 796         }
 797
 798         driver.num_ioctls = i915_max_ioctl;
 799
 800         /*
 801          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 802          * explicitly disabled with the module pararmeter.
 803          *
 804          * Otherwise, just follow the parameter (defaulting to off).
 805          *
 806          * Allow optional vga_text_mode_force boot option to override
 807          * the default behavior.
 808          */
 809 #if defined(CONFIG_DRM_I915_KMS)
 810         if (i915_modeset != 0)
 811                 driver.driver_features |= DRIVER_MODESET;
 812 #endif
 813         if (i915_modeset == 1)
 814                 driver.driver_features |= DRIVER_MODESET;
 815
 816 #ifdef CONFIG_VGA_CONSOLE
 817         if (vgacon_text_force() && i915_modeset == -1)
 818                 driver.driver_features &= ~DRIVER_MODESET;
 819 #endif
 820
 821         if (!(driver.driver_features & DRIVER_MODESET))
 822                 driver.get_vblank_timestamp = NULL;
 823
 824         return drm_pci_init(&driver, &i915_pci_driver);
 825 }
 826
 827 static void __exit i915_exit(void)
 828 {
 829         drm_pci_exit(&driver, &i915_pci_driver);
 830 }
 831
 832 module_init(i915_init);
 833 module_exit(i915_exit);
 834
 835 MODULE_AUTHOR(DRIVER_AUTHOR);
 836 MODULE_DESCRIPTION(DRIVER_DESC);
 837 MODULE_LICENSE("GPL and additional rights");