drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <linux/pm_runtime.h>
  40 #include <drm/drm_crtc_helper.h>
  41
  42 static struct drm_driver driver;
  43
  44 #define GEN_DEFAULT_PIPEOFFSETS \
  45         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  46                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  47         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  48                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  49         .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
  50         .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
  51         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  52
  53 #define GEN_CHV_PIPEOFFSETS \
  54         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  55                           CHV_PIPE_C_OFFSET }, \
  56         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  57                            CHV_TRANSCODER_C_OFFSET, }, \
  58         .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, \
  59                           CHV_DPLL_C_OFFSET }, \
  60         .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, \
  61                              CHV_DPLL_C_MD_OFFSET }, \
  62         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  63                              CHV_PALETTE_C_OFFSET }
  64
  65 #define CURSOR_OFFSETS \
  66         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  67
  68 #define IVB_CURSOR_OFFSETS \
  69         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  70
  71 static const struct intel_device_info intel_i830_info = {
  72         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  73         .has_overlay = 1, .overlay_needs_physical = 1,
  74         .ring_mask = RENDER_RING,
  75         GEN_DEFAULT_PIPEOFFSETS,
  76         CURSOR_OFFSETS,
  77 };
  78
  79 static const struct intel_device_info intel_845g_info = {
  80         .gen = 2, .num_pipes = 1,
  81         .has_overlay = 1, .overlay_needs_physical = 1,
  82         .ring_mask = RENDER_RING,
  83         GEN_DEFAULT_PIPEOFFSETS,
  84         CURSOR_OFFSETS,
  85 };
  86
  87 static const struct intel_device_info intel_i85x_info = {
  88         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  89         .cursor_needs_physical = 1,
  90         .has_overlay = 1, .overlay_needs_physical = 1,
  91         .has_fbc = 1,
  92         .ring_mask = RENDER_RING,
  93         GEN_DEFAULT_PIPEOFFSETS,
  94         CURSOR_OFFSETS,
  95 };
  96
  97 static const struct intel_device_info intel_i865g_info = {
  98         .gen = 2, .num_pipes = 1,
  99         .has_overlay = 1, .overlay_needs_physical = 1,
 100         .ring_mask = RENDER_RING,
 101         GEN_DEFAULT_PIPEOFFSETS,
 102         CURSOR_OFFSETS,
 103 };
 104
 105 static const struct intel_device_info intel_i915g_info = {
 106         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 107         .has_overlay = 1, .overlay_needs_physical = 1,
 108         .ring_mask = RENDER_RING,
 109         GEN_DEFAULT_PIPEOFFSETS,
 110         CURSOR_OFFSETS,
 111 };
 112 static const struct intel_device_info intel_i915gm_info = {
 113         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 114         .cursor_needs_physical = 1,
 115         .has_overlay = 1, .overlay_needs_physical = 1,
 116         .supports_tv = 1,
 117         .has_fbc = 1,
 118         .ring_mask = RENDER_RING,
 119         GEN_DEFAULT_PIPEOFFSETS,
 120         CURSOR_OFFSETS,
 121 };
 122 static const struct intel_device_info intel_i945g_info = {
 123         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 124         .has_overlay = 1, .overlay_needs_physical = 1,
 125         .ring_mask = RENDER_RING,
 126         GEN_DEFAULT_PIPEOFFSETS,
 127         CURSOR_OFFSETS,
 128 };
 129 static const struct intel_device_info intel_i945gm_info = {
 130         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 131         .has_hotplug = 1, .cursor_needs_physical = 1,
 132         .has_overlay = 1, .overlay_needs_physical = 1,
 133         .supports_tv = 1,
 134         .has_fbc = 1,
 135         .ring_mask = RENDER_RING,
 136         GEN_DEFAULT_PIPEOFFSETS,
 137         CURSOR_OFFSETS,
 138 };
 139
 140 static const struct intel_device_info intel_i965g_info = {
 141         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 142         .has_hotplug = 1,
 143         .has_overlay = 1,
 144         .ring_mask = RENDER_RING,
 145         GEN_DEFAULT_PIPEOFFSETS,
 146         CURSOR_OFFSETS,
 147 };
 148
 149 static const struct intel_device_info intel_i965gm_info = {
 150         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 151         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 152         .has_overlay = 1,
 153         .supports_tv = 1,
 154         .ring_mask = RENDER_RING,
 155         GEN_DEFAULT_PIPEOFFSETS,
 156         CURSOR_OFFSETS,
 157 };
 158
 159 static const struct intel_device_info intel_g33_info = {
 160         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 161         .need_gfx_hws = 1, .has_hotplug = 1,
 162         .has_overlay = 1,
 163         .ring_mask = RENDER_RING,
 164         GEN_DEFAULT_PIPEOFFSETS,
 165         CURSOR_OFFSETS,
 166 };
 167
 168 static const struct intel_device_info intel_g45_info = {
 169         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 170         .has_pipe_cxsr = 1, .has_hotplug = 1,
 171         .ring_mask = RENDER_RING | BSD_RING,
 172         GEN_DEFAULT_PIPEOFFSETS,
 173         CURSOR_OFFSETS,
 174 };
 175
 176 static const struct intel_device_info intel_gm45_info = {
 177         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 178         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 179         .has_pipe_cxsr = 1, .has_hotplug = 1,
 180         .supports_tv = 1,
 181         .ring_mask = RENDER_RING | BSD_RING,
 182         GEN_DEFAULT_PIPEOFFSETS,
 183         CURSOR_OFFSETS,
 184 };
 185
 186 static const struct intel_device_info intel_pineview_info = {
 187         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 188         .need_gfx_hws = 1, .has_hotplug = 1,
 189         .has_overlay = 1,
 190         GEN_DEFAULT_PIPEOFFSETS,
 191         CURSOR_OFFSETS,
 192 };
 193
 194 static const struct intel_device_info intel_ironlake_d_info = {
 195         .gen = 5, .num_pipes = 2,
 196         .need_gfx_hws = 1, .has_hotplug = 1,
 197         .ring_mask = RENDER_RING | BSD_RING,
 198         GEN_DEFAULT_PIPEOFFSETS,
 199         CURSOR_OFFSETS,
 200 };
 201
 202 static const struct intel_device_info intel_ironlake_m_info = {
 203         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 204         .need_gfx_hws = 1, .has_hotplug = 1,
 205         .has_fbc = 1,
 206         .ring_mask = RENDER_RING | BSD_RING,
 207         GEN_DEFAULT_PIPEOFFSETS,
 208         CURSOR_OFFSETS,
 209 };
 210
 211 static const struct intel_device_info intel_sandybridge_d_info = {
 212         .gen = 6, .num_pipes = 2,
 213         .need_gfx_hws = 1, .has_hotplug = 1,
 214         .has_fbc = 1,
 215         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 216         .has_llc = 1,
 217         GEN_DEFAULT_PIPEOFFSETS,
 218         CURSOR_OFFSETS,
 219 };
 220
 221 static const struct intel_device_info intel_sandybridge_m_info = {
 222         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 223         .need_gfx_hws = 1, .has_hotplug = 1,
 224         .has_fbc = 1,
 225         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 226         .has_llc = 1,
 227         GEN_DEFAULT_PIPEOFFSETS,
 228         CURSOR_OFFSETS,
 229 };
 230
 231 #define GEN7_FEATURES  \
 232         .gen = 7, .num_pipes = 3, \
 233         .need_gfx_hws = 1, .has_hotplug = 1, \
 234         .has_fbc = 1, \
 235         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 236         .has_llc = 1
 237
 238 static const struct intel_device_info intel_ivybridge_d_info = {
 239         GEN7_FEATURES,
 240         .is_ivybridge = 1,
 241         GEN_DEFAULT_PIPEOFFSETS,
 242         IVB_CURSOR_OFFSETS,
 243 };
 244
 245 static const struct intel_device_info intel_ivybridge_m_info = {
 246         GEN7_FEATURES,
 247         .is_ivybridge = 1,
 248         .is_mobile = 1,
 249         GEN_DEFAULT_PIPEOFFSETS,
 250         IVB_CURSOR_OFFSETS,
 251 };
 252
 253 static const struct intel_device_info intel_ivybridge_q_info = {
 254         GEN7_FEATURES,
 255         .is_ivybridge = 1,
 256         .num_pipes = 0, /* legal, last one wins */
 257         GEN_DEFAULT_PIPEOFFSETS,
 258         IVB_CURSOR_OFFSETS,
 259 };
 260
 261 static const struct intel_device_info intel_valleyview_m_info = {
 262         GEN7_FEATURES,
 263         .is_mobile = 1,
 264         .num_pipes = 2,
 265         .is_valleyview = 1,
 266         .display_mmio_offset = VLV_DISPLAY_BASE,
 267         .has_fbc = 0, /* legal, last one wins */
 268         .has_llc = 0, /* legal, last one wins */
 269         GEN_DEFAULT_PIPEOFFSETS,
 270         CURSOR_OFFSETS,
 271 };
 272
 273 static const struct intel_device_info intel_valleyview_d_info = {
 274         GEN7_FEATURES,
 275         .num_pipes = 2,
 276         .is_valleyview = 1,
 277         .display_mmio_offset = VLV_DISPLAY_BASE,
 278         .has_fbc = 0, /* legal, last one wins */
 279         .has_llc = 0, /* legal, last one wins */
 280         GEN_DEFAULT_PIPEOFFSETS,
 281         CURSOR_OFFSETS,
 282 };
 283
 284 static const struct intel_device_info intel_haswell_d_info = {
 285         GEN7_FEATURES,
 286         .is_haswell = 1,
 287         .has_ddi = 1,
 288         .has_fpga_dbg = 1,
 289         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 290         GEN_DEFAULT_PIPEOFFSETS,
 291         IVB_CURSOR_OFFSETS,
 292 };
 293
 294 static const struct intel_device_info intel_haswell_m_info = {
 295         GEN7_FEATURES,
 296         .is_haswell = 1,
 297         .is_mobile = 1,
 298         .has_ddi = 1,
 299         .has_fpga_dbg = 1,
 300         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 301         GEN_DEFAULT_PIPEOFFSETS,
 302         IVB_CURSOR_OFFSETS,
 303 };
 304
 305 static const struct intel_device_info intel_broadwell_d_info = {
 306         .gen = 8, .num_pipes = 3,
 307         .need_gfx_hws = 1, .has_hotplug = 1,
 308         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 309         .has_llc = 1,
 310         .has_ddi = 1,
 311         .has_fbc = 1,
 312         GEN_DEFAULT_PIPEOFFSETS,
 313         IVB_CURSOR_OFFSETS,
 314 };
 315
 316 static const struct intel_device_info intel_broadwell_m_info = {
 317         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 318         .need_gfx_hws = 1, .has_hotplug = 1,
 319         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 320         .has_llc = 1,
 321         .has_ddi = 1,
 322         .has_fbc = 1,
 323         GEN_DEFAULT_PIPEOFFSETS,
 324         IVB_CURSOR_OFFSETS,
 325 };
 326
 327 static const struct intel_device_info intel_broadwell_gt3d_info = {
 328         .gen = 8, .num_pipes = 3,
 329         .need_gfx_hws = 1, .has_hotplug = 1,
 330         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 331         .has_llc = 1,
 332         .has_ddi = 1,
 333         .has_fbc = 1,
 334         GEN_DEFAULT_PIPEOFFSETS,
 335         IVB_CURSOR_OFFSETS,
 336 };
 337
 338 static const struct intel_device_info intel_broadwell_gt3m_info = {
 339         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 340         .need_gfx_hws = 1, .has_hotplug = 1,
 341         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 342         .has_llc = 1,
 343         .has_ddi = 1,
 344         .has_fbc = 1,
 345         GEN_DEFAULT_PIPEOFFSETS,
 346         IVB_CURSOR_OFFSETS,
 347 };
 348
 349 static const struct intel_device_info intel_cherryview_info = {
 350         .is_preliminary = 1,
 351         .gen = 8, .num_pipes = 3,
 352         .need_gfx_hws = 1, .has_hotplug = 1,
 353         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 354         .is_valleyview = 1,
 355         .display_mmio_offset = VLV_DISPLAY_BASE,
 356         GEN_CHV_PIPEOFFSETS,
 357         CURSOR_OFFSETS,
 358 };
 359
 360 /*
 361  * Make sure any device matches here are from most specific to most
 362  * general.  For example, since the Quanta match is based on the subsystem
 363  * and subvendor IDs, we need it to come before the more general IVB
 364  * PCI ID matches, otherwise we'll use the wrong info struct above.
 365  */
 366 #define INTEL_PCI_IDS \
 367         INTEL_I830_IDS(&intel_i830_info),       \
 368         INTEL_I845G_IDS(&intel_845g_info),      \
 369         INTEL_I85X_IDS(&intel_i85x_info),       \
 370         INTEL_I865G_IDS(&intel_i865g_info),     \
 371         INTEL_I915G_IDS(&intel_i915g_info),     \
 372         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 373         INTEL_I945G_IDS(&intel_i945g_info),     \
 374         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 375         INTEL_I965G_IDS(&intel_i965g_info),     \
 376         INTEL_G33_IDS(&intel_g33_info),         \
 377         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 378         INTEL_GM45_IDS(&intel_gm45_info),       \
 379         INTEL_G45_IDS(&intel_g45_info),         \
 380         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 381         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 382         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 383         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 384         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 385         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 386         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 387         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 388         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 389         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 390         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 391         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 392         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 393         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 394         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 395         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 396         INTEL_CHV_IDS(&intel_cherryview_info)
 397
 398 static const struct pci_device_id pciidlist[] = {               /* aka */
 399         INTEL_PCI_IDS,
 400         {0, 0, 0}
 401 };
 402
 403 #if defined(CONFIG_DRM_I915_KMS)
 404 MODULE_DEVICE_TABLE(pci, pciidlist);
 405 #endif
 406
 407 void intel_detect_pch(struct drm_device *dev)
 408 {
 409         struct drm_i915_private *dev_priv = dev->dev_private;
 410         struct pci_dev *pch = NULL;
 411
 412         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 413          * (which really amounts to a PCH but no South Display).
 414          */
 415         if (INTEL_INFO(dev)->num_pipes == 0) {
 416                 dev_priv->pch_type = PCH_NOP;
 417                 return;
 418         }
 419
 420         /*
 421          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 422          * make graphics device passthrough work easy for VMM, that only
 423          * need to expose ISA bridge to let driver know the real hardware
 424          * underneath. This is a requirement from virtualization team.
 425          *
 426          * In some virtualized environments (e.g. XEN), there is irrelevant
 427          * ISA bridge in the system. To work reliably, we should scan trhough
 428          * all the ISA bridge devices and check for the first match, instead
 429          * of only checking the first one.
 430          */
 431         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 432                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 433                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 434                         dev_priv->pch_id = id;
 435
 436                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 437                                 dev_priv->pch_type = PCH_IBX;
 438                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 439                                 WARN_ON(!IS_GEN5(dev));
 440                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 441                                 dev_priv->pch_type = PCH_CPT;
 442                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 443                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 444                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 445                                 /* PantherPoint is CPT compatible */
 446                                 dev_priv->pch_type = PCH_CPT;
 447                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 448                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 449                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 450                                 dev_priv->pch_type = PCH_LPT;
 451                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 452                                 WARN_ON(!IS_HASWELL(dev));
 453                                 WARN_ON(IS_ULT(dev));
 454                         } else if (IS_BROADWELL(dev)) {
 455                                 dev_priv->pch_type = PCH_LPT;
 456                                 dev_priv->pch_id =
 457                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 458                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 459                                               "LynxPoint LP PCH\n");
 460                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 461                                 dev_priv->pch_type = PCH_LPT;
 462                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 463                                 WARN_ON(!IS_HASWELL(dev));
 464                                 WARN_ON(!IS_ULT(dev));
 465                         } else
 466                                 continue;
 467
 468                         break;
 469                 }
 470         }
 471         if (!pch)
 472                 DRM_DEBUG_KMS("No PCH found.\n");
 473
 474         pci_dev_put(pch);
 475 }
 476
 477 bool i915_semaphore_is_enabled(struct drm_device *dev)
 478 {
 479         if (INTEL_INFO(dev)->gen < 6)
 480                 return false;
 481
 482         if (i915.semaphores >= 0)
 483                 return i915.semaphores;
 484
 485         /* Until we get further testing... */
 486         if (IS_GEN8(dev))
 487                 return false;
 488
 489 #ifdef CONFIG_INTEL_IOMMU
 490         /* Enable semaphores on SNB when IO remapping is off */
 491         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 492                 return false;
 493 #endif
 494
 495         return true;
 496 }
 497
 498 static int i915_drm_freeze(struct drm_device *dev)
 499 {
 500         struct drm_i915_private *dev_priv = dev->dev_private;
 501         struct drm_crtc *crtc;
 502
 503         intel_runtime_pm_get(dev_priv);
 504
 505         /* ignore lid events during suspend */
 506         mutex_lock(&dev_priv->modeset_restore_lock);
 507         dev_priv->modeset_restore = MODESET_SUSPENDED;
 508         mutex_unlock(&dev_priv->modeset_restore_lock);
 509
 510         /* We do a lot of poking in a lot of registers, make sure they work
 511          * properly. */
 512         intel_display_set_init_power(dev_priv, true);
 513
 514         drm_kms_helper_poll_disable(dev);
 515
 516         pci_save_state(dev->pdev);
 517
 518         /* If KMS is active, we do the leavevt stuff here */
 519         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 520                 int error;
 521
 522                 error = i915_gem_suspend(dev);
 523                 if (error) {
 524                         dev_err(&dev->pdev->dev,
 525                                 "GEM idle failed, resume might fail\n");
 526                         return error;
 527                 }
 528
 529                 drm_irq_uninstall(dev);
 530                 dev_priv->enable_hotplug_processing = false;
 531
 532                 intel_disable_gt_powersave(dev);
 533
 534                 /*
 535                  * Disable CRTCs directly since we want to preserve sw state
 536                  * for _thaw.
 537                  */
 538                 drm_modeset_lock_all(dev);
 539                 for_each_crtc(dev, crtc) {
 540                         dev_priv->display.crtc_disable(crtc);
 541                 }
 542                 drm_modeset_unlock_all(dev);
 543
 544                 intel_modeset_suspend_hw(dev);
 545         }
 546
 547         i915_gem_suspend_gtt_mappings(dev);
 548
 549         i915_save_state(dev);
 550
 551         intel_opregion_fini(dev);
 552         intel_uncore_fini(dev);
 553
 554         console_lock();
 555         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 556         console_unlock();
 557
 558         dev_priv->suspend_count++;
 559
 560         return 0;
 561 }
 562
 563 int i915_suspend(struct drm_device *dev, pm_message_t state)
 564 {
 565         int error;
 566
 567         if (!dev || !dev->dev_private) {
 568                 DRM_ERROR("dev: %p\n", dev);
 569                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 570                 return -ENODEV;
 571         }
 572
 573         if (state.event == PM_EVENT_PRETHAW)
 574                 return 0;
 575
 576
 577         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 578                 return 0;
 579
 580         error = i915_drm_freeze(dev);
 581         if (error)
 582                 return error;
 583
 584         if (state.event == PM_EVENT_SUSPEND) {
 585                 /* Shut down the device */
 586                 pci_disable_device(dev->pdev);
 587                 pci_set_power_state(dev->pdev, PCI_D3hot);
 588         }
 589
 590         return 0;
 591 }
 592
 593 void intel_console_resume(struct work_struct *work)
 594 {
 595         struct drm_i915_private *dev_priv =
 596                 container_of(work, struct drm_i915_private,
 597                              console_resume_work);
 598         struct drm_device *dev = dev_priv->dev;
 599
 600         console_lock();
 601         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 602         console_unlock();
 603 }
 604
 605 static int i915_drm_thaw_early(struct drm_device *dev)
 606 {
 607         struct drm_i915_private *dev_priv = dev->dev_private;
 608
 609         intel_uncore_early_sanitize(dev);
 610         intel_uncore_sanitize(dev);
 611         intel_power_domains_init_hw(dev_priv);
 612
 613         return 0;
 614 }
 615
 616 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 617 {
 618         struct drm_i915_private *dev_priv = dev->dev_private;
 619
 620         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 621             restore_gtt_mappings) {
 622                 mutex_lock(&dev->struct_mutex);
 623                 i915_gem_restore_gtt_mappings(dev);
 624                 mutex_unlock(&dev->struct_mutex);
 625         }
 626
 627         i915_restore_state(dev);
 628         intel_opregion_setup(dev);
 629
 630         /* KMS EnterVT equivalent */
 631         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 632                 intel_init_pch_refclk(dev);
 633                 drm_mode_config_reset(dev);
 634
 635                 mutex_lock(&dev->struct_mutex);
 636                 if (i915_gem_init_hw(dev)) {
 637                         DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 638                         atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 639                 }
 640                 mutex_unlock(&dev->struct_mutex);
 641
 642                 /* We need working interrupts for modeset enabling ... */
 643                 drm_irq_install(dev, dev->pdev->irq);
 644
 645                 intel_modeset_init_hw(dev);
 646
 647                 drm_modeset_lock_all(dev);
 648                 intel_modeset_setup_hw_state(dev, true);
 649                 drm_modeset_unlock_all(dev);
 650
 651                 /*
 652                  * ... but also need to make sure that hotplug processing
 653                  * doesn't cause havoc. Like in the driver load code we don't
 654                  * bother with the tiny race here where we might loose hotplug
 655                  * notifications.
 656                  * */
 657                 intel_hpd_init(dev);
 658                 dev_priv->enable_hotplug_processing = true;
 659                 /* Config may have changed between suspend and resume */
 660                 drm_helper_hpd_irq_event(dev);
 661         }
 662
 663         intel_opregion_init(dev);
 664
 665         /*
 666          * The console lock can be pretty contented on resume due
 667          * to all the printk activity.  Try to keep it out of the hot
 668          * path of resume if possible.
 669          */
 670         if (console_trylock()) {
 671                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 672                 console_unlock();
 673         } else {
 674                 schedule_work(&dev_priv->console_resume_work);
 675         }
 676
 677         mutex_lock(&dev_priv->modeset_restore_lock);
 678         dev_priv->modeset_restore = MODESET_DONE;
 679         mutex_unlock(&dev_priv->modeset_restore_lock);
 680
 681         intel_runtime_pm_put(dev_priv);
 682         return 0;
 683 }
 684
 685 static int i915_drm_thaw(struct drm_device *dev)
 686 {
 687         if (drm_core_check_feature(dev, DRIVER_MODESET))
 688                 i915_check_and_clear_faults(dev);
 689
 690         return __i915_drm_thaw(dev, true);
 691 }
 692
 693 static int i915_resume_early(struct drm_device *dev)
 694 {
 695         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 696                 return 0;
 697
 698         /*
 699          * We have a resume ordering issue with the snd-hda driver also
 700          * requiring our device to be power up. Due to the lack of a
 701          * parent/child relationship we currently solve this with an early
 702          * resume hook.
 703          *
 704          * FIXME: This should be solved with a special hdmi sink device or
 705          * similar so that power domains can be employed.
 706          */
 707         if (pci_enable_device(dev->pdev))
 708                 return -EIO;
 709
 710         pci_set_master(dev->pdev);
 711
 712         return i915_drm_thaw_early(dev);
 713 }
 714
 715 int i915_resume(struct drm_device *dev)
 716 {
 717         struct drm_i915_private *dev_priv = dev->dev_private;
 718         int ret;
 719
 720         /*
 721          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 722          * earlier) need to restore the GTT mappings since the BIOS might clear
 723          * all our scratch PTEs.
 724          */
 725         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 726         if (ret)
 727                 return ret;
 728
 729         drm_kms_helper_poll_enable(dev);
 730         return 0;
 731 }
 732
 733 static int i915_resume_legacy(struct drm_device *dev)
 734 {
 735         i915_resume_early(dev);
 736         i915_resume(dev);
 737
 738         return 0;
 739 }
 740
 741 /**
 742  * i915_reset - reset chip after a hang
 743  * @dev: drm device to reset
 744  *
 745  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 746  * reset or otherwise an error code.
 747  *
 748  * Procedure is fairly simple:
 749  *   - reset the chip using the reset reg
 750  *   - re-init context state
 751  *   - re-init hardware status page
 752  *   - re-init ring buffer
 753  *   - re-init interrupt state
 754  *   - re-init display
 755  */
 756 int i915_reset(struct drm_device *dev)
 757 {
 758         struct drm_i915_private *dev_priv = dev->dev_private;
 759         bool simulated;
 760         int ret;
 761
 762         if (!i915.reset)
 763                 return 0;
 764
 765         mutex_lock(&dev->struct_mutex);
 766
 767         i915_gem_reset(dev);
 768
 769         simulated = dev_priv->gpu_error.stop_rings != 0;
 770
 771         ret = intel_gpu_reset(dev);
 772
 773         /* Also reset the gpu hangman. */
 774         if (simulated) {
 775                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 776                 dev_priv->gpu_error.stop_rings = 0;
 777                 if (ret == -ENODEV) {
 778                         DRM_INFO("Reset not implemented, but ignoring "
 779                                  "error for simulated gpu hangs\n");
 780                         ret = 0;
 781                 }
 782         }
 783
 784         if (ret) {
 785                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 786                 mutex_unlock(&dev->struct_mutex);
 787                 return ret;
 788         }
 789
 790         /* Ok, now get things going again... */
 791
 792         /*
 793          * Everything depends on having the GTT running, so we need to start
 794          * there.  Fortunately we don't need to do this unless we reset the
 795          * chip at a PCI level.
 796          *
 797          * Next we need to restore the context, but we don't use those
 798          * yet either...
 799          *
 800          * Ring buffer needs to be re-initialized in the KMS case, or if X
 801          * was running at the time of the reset (i.e. we weren't VT
 802          * switched away).
 803          */
 804         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 805                         !dev_priv->ums.mm_suspended) {
 806                 dev_priv->ums.mm_suspended = 0;
 807
 808                 ret = i915_gem_init_hw(dev);
 809                 mutex_unlock(&dev->struct_mutex);
 810                 if (ret) {
 811                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 812                         return ret;
 813                 }
 814
 815                 /*
 816                  * FIXME: This races pretty badly against concurrent holders of
 817                  * ring interrupts. This is possible since we've started to drop
 818                  * dev->struct_mutex in select places when waiting for the gpu.
 819                  */
 820
 821                 /*
 822                  * rps/rc6 re-init is necessary to restore state lost after the
 823                  * reset and the re-install of gt irqs. Skip for ironlake per
 824                  * previous concerns that it doesn't respond well to some forms
 825                  * of re-init after reset.
 826                  */
 827                 if (INTEL_INFO(dev)->gen > 5)
 828                         intel_reset_gt_powersave(dev);
 829
 830                 intel_hpd_init(dev);
 831         } else {
 832                 mutex_unlock(&dev->struct_mutex);
 833         }
 834
 835         return 0;
 836 }
 837
 838 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 839 {
 840         struct intel_device_info *intel_info =
 841                 (struct intel_device_info *) ent->driver_data;
 842
 843         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 844                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 845                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 846                 return -ENODEV;
 847         }
 848
 849         /* Only bind to function 0 of the device. Early generations
 850          * used function 1 as a placeholder for multi-head. This causes
 851          * us confusion instead, especially on the systems where both
 852          * functions have the same PCI-ID!
 853          */
 854         if (PCI_FUNC(pdev->devfn))
 855                 return -ENODEV;
 856
 857         driver.driver_features &= ~(DRIVER_USE_AGP);
 858
 859         return drm_get_pci_dev(pdev, ent, &driver);
 860 }
 861
 862 static void
 863 i915_pci_remove(struct pci_dev *pdev)
 864 {
 865         struct drm_device *dev = pci_get_drvdata(pdev);
 866
 867         drm_put_dev(dev);
 868 }
 869
 870 static int i915_pm_suspend(struct device *dev)
 871 {
 872         struct pci_dev *pdev = to_pci_dev(dev);
 873         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 874
 875         if (!drm_dev || !drm_dev->dev_private) {
 876                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 877                 return -ENODEV;
 878         }
 879
 880         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 881                 return 0;
 882
 883         return i915_drm_freeze(drm_dev);
 884 }
 885
 886 static int i915_pm_suspend_late(struct device *dev)
 887 {
 888         struct pci_dev *pdev = to_pci_dev(dev);
 889         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 890
 891         /*
 892          * We have a suspedn ordering issue with the snd-hda driver also
 893          * requiring our device to be power up. Due to the lack of a
 894          * parent/child relationship we currently solve this with an late
 895          * suspend hook.
 896          *
 897          * FIXME: This should be solved with a special hdmi sink device or
 898          * similar so that power domains can be employed.
 899          */
 900         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 901                 return 0;
 902
 903         pci_disable_device(pdev);
 904         pci_set_power_state(pdev, PCI_D3hot);
 905
 906         return 0;
 907 }
 908
 909 static int i915_pm_resume_early(struct device *dev)
 910 {
 911         struct pci_dev *pdev = to_pci_dev(dev);
 912         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 913
 914         return i915_resume_early(drm_dev);
 915 }
 916
 917 static int i915_pm_resume(struct device *dev)
 918 {
 919         struct pci_dev *pdev = to_pci_dev(dev);
 920         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 921
 922         return i915_resume(drm_dev);
 923 }
 924
 925 static int i915_pm_freeze(struct device *dev)
 926 {
 927         struct pci_dev *pdev = to_pci_dev(dev);
 928         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 929
 930         if (!drm_dev || !drm_dev->dev_private) {
 931                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 932                 return -ENODEV;
 933         }
 934
 935         return i915_drm_freeze(drm_dev);
 936 }
 937
 938 static int i915_pm_thaw_early(struct device *dev)
 939 {
 940         struct pci_dev *pdev = to_pci_dev(dev);
 941         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 942
 943         return i915_drm_thaw_early(drm_dev);
 944 }
 945
 946 static int i915_pm_thaw(struct device *dev)
 947 {
 948         struct pci_dev *pdev = to_pci_dev(dev);
 949         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 950
 951         return i915_drm_thaw(drm_dev);
 952 }
 953
 954 static int i915_pm_poweroff(struct device *dev)
 955 {
 956         struct pci_dev *pdev = to_pci_dev(dev);
 957         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 958
 959         return i915_drm_freeze(drm_dev);
 960 }
 961
 962 static int hsw_runtime_suspend(struct drm_i915_private *dev_priv)
 963 {
 964         hsw_enable_pc8(dev_priv);
 965
 966         return 0;
 967 }
 968
 969 static int snb_runtime_resume(struct drm_i915_private *dev_priv)
 970 {
 971         struct drm_device *dev = dev_priv->dev;
 972
 973         intel_init_pch_refclk(dev);
 974
 975         return 0;
 976 }
 977
 978 static int hsw_runtime_resume(struct drm_i915_private *dev_priv)
 979 {
 980         hsw_disable_pc8(dev_priv);
 981
 982         return 0;
 983 }
 984
 985 /*
 986  * Save all Gunit registers that may be lost after a D3 and a subsequent
 987  * S0i[R123] transition. The list of registers needing a save/restore is
 988  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
 989  * registers in the following way:
 990  * - Driver: saved/restored by the driver
 991  * - Punit : saved/restored by the Punit firmware
 992  * - No, w/o marking: no need to save/restore, since the register is R/O or
 993  *                    used internally by the HW in a way that doesn't depend
 994  *                    keeping the content across a suspend/resume.
 995  * - Debug : used for debugging
 996  *
 997  * We save/restore all registers marked with 'Driver', with the following
 998  * exceptions:
 999  * - Registers out of use, including also registers marked with 'Debug'.
1000  *   These have no effect on the driver's operation, so we don't save/restore
1001  *   them to reduce the overhead.
1002  * - Registers that are fully setup by an initialization function called from
1003  *   the resume path. For example many clock gating and RPS/RC6 registers.
1004  * - Registers that provide the right functionality with their reset defaults.
1005  *
1006  * TODO: Except for registers that based on the above 3 criteria can be safely
1007  * ignored, we save/restore all others, practically treating the HW context as
1008  * a black-box for the driver. Further investigation is needed to reduce the
1009  * saved/restored registers even further, by following the same 3 criteria.
1010  */
1011 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1012 {
1013         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1014         int i;
1015
1016         /* GAM 0x4000-0x4770 */
1017         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1018         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1019         s->arb_mode             = I915_READ(ARB_MODE);
1020         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1021         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1022
1023         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1024                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1025
1026         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1027         s->gfx_max_req_count    = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1028
1029         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1030         s->ecochk               = I915_READ(GAM_ECOCHK);
1031         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1032         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1033
1034         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1035
1036         /* MBC 0x9024-0x91D0, 0x8500 */
1037         s->g3dctl               = I915_READ(VLV_G3DCTL);
1038         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1039         s->mbctl                = I915_READ(GEN6_MBCTL);
1040
1041         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1042         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1043         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1044         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1045         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1046         s->rstctl               = I915_READ(GEN6_RSTCTL);
1047         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1048
1049         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1050         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1051         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1052         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1053         s->ecobus               = I915_READ(ECOBUS);
1054         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1055         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1056         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1057         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1058         s->rcedata              = I915_READ(VLV_RCEDATA);
1059         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1060
1061         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1062         s->gt_imr               = I915_READ(GTIMR);
1063         s->gt_ier               = I915_READ(GTIER);
1064         s->pm_imr               = I915_READ(GEN6_PMIMR);
1065         s->pm_ier               = I915_READ(GEN6_PMIER);
1066
1067         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1068                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1069
1070         /* GT SA CZ domain, 0x100000-0x138124 */
1071         s->tilectl              = I915_READ(TILECTL);
1072         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1073         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1074         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1075         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1076
1077         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1078         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1079         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1080         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1081
1082         /*
1083          * Not saving any of:
1084          * DFT,         0x9800-0x9EC0
1085          * SARB,        0xB000-0xB1FC
1086          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1087          * PCI CFG
1088          */
1089 }
1090
1091 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1092 {
1093         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1094         u32 val;
1095         int i;
1096
1097         /* GAM 0x4000-0x4770 */
1098         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1099         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1100         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1101         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1102         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1103
1104         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1105                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1106
1107         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1108         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1109
1110         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1111         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1112         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1113         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1114
1115         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1116
1117         /* MBC 0x9024-0x91D0, 0x8500 */
1118         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1119         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1120         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1121
1122         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1123         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1124         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1125         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1126         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1127         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1128         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1129
1130         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1131         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1132         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1133         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1134         I915_WRITE(ECOBUS,              s->ecobus);
1135         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1136         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1137         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1138         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1139         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1140         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1141
1142         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1143         I915_WRITE(GTIMR,               s->gt_imr);
1144         I915_WRITE(GTIER,               s->gt_ier);
1145         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1146         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1147
1148         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1149                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1150
1151         /* GT SA CZ domain, 0x100000-0x138124 */
1152         I915_WRITE(TILECTL,                     s->tilectl);
1153         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1154         /*
1155          * Preserve the GT allow wake and GFX force clock bit, they are not
1156          * be restored, as they are used to control the s0ix suspend/resume
1157          * sequence by the caller.
1158          */
1159         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1160         val &= VLV_GTLC_ALLOWWAKEREQ;
1161         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1162         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1163
1164         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1165         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1166         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1167         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1168
1169         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1170
1171         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1172         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1173         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1174         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1175 }
1176
1177 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1178 {
1179         u32 val;
1180         int err;
1181
1182         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1183         WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1184
1185 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1186         /* Wait for a previous force-off to settle */
1187         if (force_on) {
1188                 err = wait_for(!COND, 20);
1189                 if (err) {
1190                         DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1191                                   I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1192                         return err;
1193                 }
1194         }
1195
1196         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1197         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1198         if (force_on)
1199                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1200         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1201
1202         if (!force_on)
1203                 return 0;
1204
1205         err = wait_for(COND, 20);
1206         if (err)
1207                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1208                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1209
1210         return err;
1211 #undef COND
1212 }
1213
1214 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1215 {
1216         u32 val;
1217         int err = 0;
1218
1219         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1220         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1221         if (allow)
1222                 val |= VLV_GTLC_ALLOWWAKEREQ;
1223         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1224         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1225
1226 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1227               allow)
1228         err = wait_for(COND, 1);
1229         if (err)
1230                 DRM_ERROR("timeout disabling GT waking\n");
1231         return err;
1232 #undef COND
1233 }
1234
1235 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1236                                  bool wait_for_on)
1237 {
1238         u32 mask;
1239         u32 val;
1240         int err;
1241
1242         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1243         val = wait_for_on ? mask : 0;
1244 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1245         if (COND)
1246                 return 0;
1247
1248         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1249                         wait_for_on ? "on" : "off",
1250                         I915_READ(VLV_GTLC_PW_STATUS));
1251
1252         /*
1253          * RC6 transitioning can be delayed up to 2 msec (see
1254          * valleyview_enable_rps), use 3 msec for safety.
1255          */
1256         err = wait_for(COND, 3);
1257         if (err)
1258                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1259                           wait_for_on ? "on" : "off");
1260
1261         return err;
1262 #undef COND
1263 }
1264
1265 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1266 {
1267         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1268                 return;
1269
1270         DRM_ERROR("GT register access while GT waking disabled\n");
1271         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1272 }
1273
1274 static int vlv_runtime_suspend(struct drm_i915_private *dev_priv)
1275 {
1276         u32 mask;
1277         int err;
1278
1279         /*
1280          * Bspec defines the following GT well on flags as debug only, so
1281          * don't treat them as hard failures.
1282          */
1283         (void)vlv_wait_for_gt_wells(dev_priv, false);
1284
1285         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1286         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1287
1288         vlv_check_no_gt_access(dev_priv);
1289
1290         err = vlv_force_gfx_clock(dev_priv, true);
1291         if (err)
1292                 goto err1;
1293
1294         err = vlv_allow_gt_wake(dev_priv, false);
1295         if (err)
1296                 goto err2;
1297         vlv_save_gunit_s0ix_state(dev_priv);
1298
1299         err = vlv_force_gfx_clock(dev_priv, false);
1300         if (err)
1301                 goto err2;
1302
1303         return 0;
1304
1305 err2:
1306         /* For safety always re-enable waking and disable gfx clock forcing */
1307         vlv_allow_gt_wake(dev_priv, true);
1308 err1:
1309         vlv_force_gfx_clock(dev_priv, false);
1310
1311         return err;
1312 }
1313
1314 static int vlv_runtime_resume(struct drm_i915_private *dev_priv)
1315 {
1316         struct drm_device *dev = dev_priv->dev;
1317         int err;
1318         int ret;
1319
1320         /*
1321          * If any of the steps fail just try to continue, that's the best we
1322          * can do at this point. Return the first error code (which will also
1323          * leave RPM permanently disabled).
1324          */
1325         ret = vlv_force_gfx_clock(dev_priv, true);
1326
1327         vlv_restore_gunit_s0ix_state(dev_priv);
1328
1329         err = vlv_allow_gt_wake(dev_priv, true);
1330         if (!ret)
1331                 ret = err;
1332
1333         err = vlv_force_gfx_clock(dev_priv, false);
1334         if (!ret)
1335                 ret = err;
1336
1337         vlv_check_no_gt_access(dev_priv);
1338
1339         intel_init_clock_gating(dev);
1340         i915_gem_restore_fences(dev);
1341
1342         return ret;
1343 }
1344
1345 static int intel_runtime_suspend(struct device *device)
1346 {
1347         struct pci_dev *pdev = to_pci_dev(device);
1348         struct drm_device *dev = pci_get_drvdata(pdev);
1349         struct drm_i915_private *dev_priv = dev->dev_private;
1350         int ret;
1351
1352         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1353                 return -ENODEV;
1354
1355         WARN_ON(!HAS_RUNTIME_PM(dev));
1356         assert_force_wake_inactive(dev_priv);
1357
1358         DRM_DEBUG_KMS("Suspending device\n");
1359
1360         /*
1361          * We could deadlock here in case another thread holding struct_mutex
1362          * calls RPM suspend concurrently, since the RPM suspend will wait
1363          * first for this RPM suspend to finish. In this case the concurrent
1364          * RPM resume will be followed by its RPM suspend counterpart. Still
1365          * for consistency return -EAGAIN, which will reschedule this suspend.
1366          */
1367         if (!mutex_trylock(&dev->struct_mutex)) {
1368                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1369                 /*
1370                  * Bump the expiration timestamp, otherwise the suspend won't
1371                  * be rescheduled.
1372                  */
1373                 pm_runtime_mark_last_busy(device);
1374
1375                 return -EAGAIN;
1376         }
1377         /*
1378          * We are safe here against re-faults, since the fault handler takes
1379          * an RPM reference.
1380          */
1381         i915_gem_release_all_mmaps(dev_priv);
1382         mutex_unlock(&dev->struct_mutex);
1383
1384         /*
1385          * rps.work can't be rearmed here, since we get here only after making
1386          * sure the GPU is idle and the RPS freq is set to the minimum. See
1387          * intel_mark_idle().
1388          */
1389         cancel_work_sync(&dev_priv->rps.work);
1390         intel_runtime_pm_disable_interrupts(dev);
1391
1392         if (IS_GEN6(dev)) {
1393                 ret = 0;
1394         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1395                 ret = hsw_runtime_suspend(dev_priv);
1396         } else if (IS_VALLEYVIEW(dev)) {
1397                 ret = vlv_runtime_suspend(dev_priv);
1398         } else {
1399                 ret = -ENODEV;
1400                 WARN_ON(1);
1401         }
1402
1403         if (ret) {
1404                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1405                 intel_runtime_pm_restore_interrupts(dev);
1406
1407                 return ret;
1408         }
1409
1410         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1411         dev_priv->pm.suspended = true;
1412
1413         /*
1414          * current versions of firmware which depend on this opregion
1415          * notification have repurposed the D1 definition to mean
1416          * "runtime suspended" vs. what you would normally expect (D3)
1417          * to distinguish it from notifications that might be sent
1418          * via the suspend path.
1419          */
1420         intel_opregion_notify_adapter(dev, PCI_D1);
1421
1422         DRM_DEBUG_KMS("Device suspended\n");
1423         return 0;
1424 }
1425
1426 static int intel_runtime_resume(struct device *device)
1427 {
1428         struct pci_dev *pdev = to_pci_dev(device);
1429         struct drm_device *dev = pci_get_drvdata(pdev);
1430         struct drm_i915_private *dev_priv = dev->dev_private;
1431         int ret;
1432
1433         WARN_ON(!HAS_RUNTIME_PM(dev));
1434
1435         DRM_DEBUG_KMS("Resuming device\n");
1436
1437         intel_opregion_notify_adapter(dev, PCI_D0);
1438         dev_priv->pm.suspended = false;
1439
1440         if (IS_GEN6(dev)) {
1441                 ret = snb_runtime_resume(dev_priv);
1442         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1443                 ret = hsw_runtime_resume(dev_priv);
1444         } else if (IS_VALLEYVIEW(dev)) {
1445                 ret = vlv_runtime_resume(dev_priv);
1446         } else {
1447                 WARN_ON(1);
1448                 ret = -ENODEV;
1449         }
1450
1451         /*
1452          * No point of rolling back things in case of an error, as the best
1453          * we can do is to hope that things will still work (and disable RPM).
1454          */
1455         i915_gem_init_swizzling(dev);
1456         gen6_update_ring_freq(dev);
1457
1458         intel_runtime_pm_restore_interrupts(dev);
1459         intel_reset_gt_powersave(dev);
1460
1461         if (ret)
1462                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1463         else
1464                 DRM_DEBUG_KMS("Device resumed\n");
1465
1466         return ret;
1467 }
1468
1469 static const struct dev_pm_ops i915_pm_ops = {
1470         .suspend = i915_pm_suspend,
1471         .suspend_late = i915_pm_suspend_late,
1472         .resume_early = i915_pm_resume_early,
1473         .resume = i915_pm_resume,
1474         .freeze = i915_pm_freeze,
1475         .thaw_early = i915_pm_thaw_early,
1476         .thaw = i915_pm_thaw,
1477         .poweroff = i915_pm_poweroff,
1478         .restore_early = i915_pm_resume_early,
1479         .restore = i915_pm_resume,
1480         .runtime_suspend = intel_runtime_suspend,
1481         .runtime_resume = intel_runtime_resume,
1482 };
1483
1484 static const struct vm_operations_struct i915_gem_vm_ops = {
1485         .fault = i915_gem_fault,
1486         .open = drm_gem_vm_open,
1487         .close = drm_gem_vm_close,
1488 };
1489
1490 static const struct file_operations i915_driver_fops = {
1491         .owner = THIS_MODULE,
1492         .open = drm_open,
1493         .release = drm_release,
1494         .unlocked_ioctl = drm_ioctl,
1495         .mmap = drm_gem_mmap,
1496         .poll = drm_poll,
1497         .read = drm_read,
1498 #ifdef CONFIG_COMPAT
1499         .compat_ioctl = i915_compat_ioctl,
1500 #endif
1501         .llseek = noop_llseek,
1502 };
1503
1504 static struct drm_driver driver = {
1505         /* Don't use MTRRs here; the Xserver or userspace app should
1506          * deal with them for Intel hardware.
1507          */
1508         .driver_features =
1509             DRIVER_USE_AGP |
1510             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1511             DRIVER_RENDER,
1512         .load = i915_driver_load,
1513         .unload = i915_driver_unload,
1514         .open = i915_driver_open,
1515         .lastclose = i915_driver_lastclose,
1516         .preclose = i915_driver_preclose,
1517         .postclose = i915_driver_postclose,
1518
1519         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1520         .suspend = i915_suspend,
1521         .resume = i915_resume_legacy,
1522
1523         .device_is_agp = i915_driver_device_is_agp,
1524         .master_create = i915_master_create,
1525         .master_destroy = i915_master_destroy,
1526 #if defined(CONFIG_DEBUG_FS)
1527         .debugfs_init = i915_debugfs_init,
1528         .debugfs_cleanup = i915_debugfs_cleanup,
1529 #endif
1530         .gem_free_object = i915_gem_free_object,
1531         .gem_vm_ops = &i915_gem_vm_ops,
1532
1533         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1534         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1535         .gem_prime_export = i915_gem_prime_export,
1536         .gem_prime_import = i915_gem_prime_import,
1537
1538         .dumb_create = i915_gem_dumb_create,
1539         .dumb_map_offset = i915_gem_mmap_gtt,
1540         .dumb_destroy = drm_gem_dumb_destroy,
1541         .ioctls = i915_ioctls,
1542         .fops = &i915_driver_fops,
1543         .name = DRIVER_NAME,
1544         .desc = DRIVER_DESC,
1545         .date = DRIVER_DATE,
1546         .major = DRIVER_MAJOR,
1547         .minor = DRIVER_MINOR,
1548         .patchlevel = DRIVER_PATCHLEVEL,
1549 };
1550
1551 static struct pci_driver i915_pci_driver = {
1552         .name = DRIVER_NAME,
1553         .id_table = pciidlist,
1554         .probe = i915_pci_probe,
1555         .remove = i915_pci_remove,
1556         .driver.pm = &i915_pm_ops,
1557 };
1558
1559 static int __init i915_init(void)
1560 {
1561         driver.num_ioctls = i915_max_ioctl;
1562
1563         /*
1564          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1565          * explicitly disabled with the module pararmeter.
1566          *
1567          * Otherwise, just follow the parameter (defaulting to off).
1568          *
1569          * Allow optional vga_text_mode_force boot option to override
1570          * the default behavior.
1571          */
1572 #if defined(CONFIG_DRM_I915_KMS)
1573         if (i915.modeset != 0)
1574                 driver.driver_features |= DRIVER_MODESET;
1575 #endif
1576         if (i915.modeset == 1)
1577                 driver.driver_features |= DRIVER_MODESET;
1578
1579 #ifdef CONFIG_VGA_CONSOLE
1580         if (vgacon_text_force() && i915.modeset == -1)
1581                 driver.driver_features &= ~DRIVER_MODESET;
1582 #endif
1583
1584         if (!(driver.driver_features & DRIVER_MODESET)) {
1585                 driver.get_vblank_timestamp = NULL;
1586 #ifndef CONFIG_DRM_I915_UMS
1587                 /* Silently fail loading to not upset userspace. */
1588                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1589                 return 0;
1590 #endif
1591         }
1592
1593         return drm_pci_init(&driver, &i915_pci_driver);
1594 }
1595
1596 static void __exit i915_exit(void)
1597 {
1598 #ifndef CONFIG_DRM_I915_UMS
1599         if (!(driver.driver_features & DRIVER_MODESET))
1600                 return; /* Never loaded a driver. */
1601 #endif
1602
1603         drm_pci_exit(&driver, &i915_pci_driver);
1604 }
1605
1606 module_init(i915_init);
1607 module_exit(i915_exit);
1608
1609 MODULE_AUTHOR(DRIVER_AUTHOR);
1610 MODULE_DESCRIPTION(DRIVER_DESC);
1611 MODULE_LICENSE("GPL and additional rights");