1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
31 #include <linux/acpi.h>
33 #include <drm/i915_drm.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <drm/drm_crtc_helper.h>
43 static struct drm_driver driver;
45 #define GEN_DEFAULT_PIPEOFFSETS \
46 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
47 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
48 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
49 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
50 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
52 #define GEN_CHV_PIPEOFFSETS \
53 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
54 CHV_PIPE_C_OFFSET }, \
55 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
56 CHV_TRANSCODER_C_OFFSET, }, \
57 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
58 CHV_PALETTE_C_OFFSET }
60 #define CURSOR_OFFSETS \
61 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
63 #define IVB_CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
66 static const struct intel_device_info intel_i830_info = {
67 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
68 .has_overlay = 1, .overlay_needs_physical = 1,
69 .ring_mask = RENDER_RING,
70 GEN_DEFAULT_PIPEOFFSETS,
74 static const struct intel_device_info intel_845g_info = {
75 .gen = 2, .num_pipes = 1,
76 .has_overlay = 1, .overlay_needs_physical = 1,
77 .ring_mask = RENDER_RING,
78 GEN_DEFAULT_PIPEOFFSETS,
82 static const struct intel_device_info intel_i85x_info = {
83 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
84 .cursor_needs_physical = 1,
85 .has_overlay = 1, .overlay_needs_physical = 1,
87 .ring_mask = RENDER_RING,
88 GEN_DEFAULT_PIPEOFFSETS,
92 static const struct intel_device_info intel_i865g_info = {
93 .gen = 2, .num_pipes = 1,
94 .has_overlay = 1, .overlay_needs_physical = 1,
95 .ring_mask = RENDER_RING,
96 GEN_DEFAULT_PIPEOFFSETS,
100 static const struct intel_device_info intel_i915g_info = {
101 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
102 .has_overlay = 1, .overlay_needs_physical = 1,
103 .ring_mask = RENDER_RING,
104 GEN_DEFAULT_PIPEOFFSETS,
107 static const struct intel_device_info intel_i915gm_info = {
108 .gen = 3, .is_mobile = 1, .num_pipes = 2,
109 .cursor_needs_physical = 1,
110 .has_overlay = 1, .overlay_needs_physical = 1,
113 .ring_mask = RENDER_RING,
114 GEN_DEFAULT_PIPEOFFSETS,
117 static const struct intel_device_info intel_i945g_info = {
118 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
119 .has_overlay = 1, .overlay_needs_physical = 1,
120 .ring_mask = RENDER_RING,
121 GEN_DEFAULT_PIPEOFFSETS,
124 static const struct intel_device_info intel_i945gm_info = {
125 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
126 .has_hotplug = 1, .cursor_needs_physical = 1,
127 .has_overlay = 1, .overlay_needs_physical = 1,
130 .ring_mask = RENDER_RING,
131 GEN_DEFAULT_PIPEOFFSETS,
135 static const struct intel_device_info intel_i965g_info = {
136 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
139 .ring_mask = RENDER_RING,
140 GEN_DEFAULT_PIPEOFFSETS,
144 static const struct intel_device_info intel_i965gm_info = {
145 .gen = 4, .is_crestline = 1, .num_pipes = 2,
146 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
149 .ring_mask = RENDER_RING,
150 GEN_DEFAULT_PIPEOFFSETS,
154 static const struct intel_device_info intel_g33_info = {
155 .gen = 3, .is_g33 = 1, .num_pipes = 2,
156 .need_gfx_hws = 1, .has_hotplug = 1,
158 .ring_mask = RENDER_RING,
159 GEN_DEFAULT_PIPEOFFSETS,
163 static const struct intel_device_info intel_g45_info = {
164 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
165 .has_pipe_cxsr = 1, .has_hotplug = 1,
166 .ring_mask = RENDER_RING | BSD_RING,
167 GEN_DEFAULT_PIPEOFFSETS,
171 static const struct intel_device_info intel_gm45_info = {
172 .gen = 4, .is_g4x = 1, .num_pipes = 2,
173 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
174 .has_pipe_cxsr = 1, .has_hotplug = 1,
176 .ring_mask = RENDER_RING | BSD_RING,
177 GEN_DEFAULT_PIPEOFFSETS,
181 static const struct intel_device_info intel_pineview_info = {
182 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
183 .need_gfx_hws = 1, .has_hotplug = 1,
185 GEN_DEFAULT_PIPEOFFSETS,
189 static const struct intel_device_info intel_ironlake_d_info = {
190 .gen = 5, .num_pipes = 2,
191 .need_gfx_hws = 1, .has_hotplug = 1,
192 .ring_mask = RENDER_RING | BSD_RING,
193 GEN_DEFAULT_PIPEOFFSETS,
197 static const struct intel_device_info intel_ironlake_m_info = {
198 .gen = 5, .is_mobile = 1, .num_pipes = 2,
199 .need_gfx_hws = 1, .has_hotplug = 1,
201 .ring_mask = RENDER_RING | BSD_RING,
202 GEN_DEFAULT_PIPEOFFSETS,
206 static const struct intel_device_info intel_sandybridge_d_info = {
207 .gen = 6, .num_pipes = 2,
208 .need_gfx_hws = 1, .has_hotplug = 1,
210 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
212 GEN_DEFAULT_PIPEOFFSETS,
216 static const struct intel_device_info intel_sandybridge_m_info = {
217 .gen = 6, .is_mobile = 1, .num_pipes = 2,
218 .need_gfx_hws = 1, .has_hotplug = 1,
220 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
222 GEN_DEFAULT_PIPEOFFSETS,
226 #define GEN7_FEATURES \
227 .gen = 7, .num_pipes = 3, \
228 .need_gfx_hws = 1, .has_hotplug = 1, \
230 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
233 static const struct intel_device_info intel_ivybridge_d_info = {
236 GEN_DEFAULT_PIPEOFFSETS,
240 static const struct intel_device_info intel_ivybridge_m_info = {
244 GEN_DEFAULT_PIPEOFFSETS,
248 static const struct intel_device_info intel_ivybridge_q_info = {
251 .num_pipes = 0, /* legal, last one wins */
252 GEN_DEFAULT_PIPEOFFSETS,
256 static const struct intel_device_info intel_valleyview_m_info = {
261 .display_mmio_offset = VLV_DISPLAY_BASE,
262 .has_fbc = 0, /* legal, last one wins */
263 .has_llc = 0, /* legal, last one wins */
264 GEN_DEFAULT_PIPEOFFSETS,
268 static const struct intel_device_info intel_valleyview_d_info = {
272 .display_mmio_offset = VLV_DISPLAY_BASE,
273 .has_fbc = 0, /* legal, last one wins */
274 .has_llc = 0, /* legal, last one wins */
275 GEN_DEFAULT_PIPEOFFSETS,
279 static const struct intel_device_info intel_haswell_d_info = {
284 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
285 GEN_DEFAULT_PIPEOFFSETS,
289 static const struct intel_device_info intel_haswell_m_info = {
295 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
296 GEN_DEFAULT_PIPEOFFSETS,
300 static const struct intel_device_info intel_broadwell_d_info = {
301 .gen = 8, .num_pipes = 3,
302 .need_gfx_hws = 1, .has_hotplug = 1,
303 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
308 GEN_DEFAULT_PIPEOFFSETS,
312 static const struct intel_device_info intel_broadwell_m_info = {
313 .gen = 8, .is_mobile = 1, .num_pipes = 3,
314 .need_gfx_hws = 1, .has_hotplug = 1,
315 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
320 GEN_DEFAULT_PIPEOFFSETS,
324 static const struct intel_device_info intel_broadwell_gt3d_info = {
325 .gen = 8, .num_pipes = 3,
326 .need_gfx_hws = 1, .has_hotplug = 1,
327 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
332 GEN_DEFAULT_PIPEOFFSETS,
336 static const struct intel_device_info intel_broadwell_gt3m_info = {
337 .gen = 8, .is_mobile = 1, .num_pipes = 3,
338 .need_gfx_hws = 1, .has_hotplug = 1,
339 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
344 GEN_DEFAULT_PIPEOFFSETS,
348 static const struct intel_device_info intel_cherryview_info = {
350 .gen = 8, .num_pipes = 3,
351 .need_gfx_hws = 1, .has_hotplug = 1,
352 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
354 .display_mmio_offset = VLV_DISPLAY_BASE,
359 static const struct intel_device_info intel_skylake_info = {
362 .gen = 9, .num_pipes = 3,
363 .need_gfx_hws = 1, .has_hotplug = 1,
364 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
368 GEN_DEFAULT_PIPEOFFSETS,
373 * Make sure any device matches here are from most specific to most
374 * general. For example, since the Quanta match is based on the subsystem
375 * and subvendor IDs, we need it to come before the more general IVB
376 * PCI ID matches, otherwise we'll use the wrong info struct above.
378 #define INTEL_PCI_IDS \
379 INTEL_I830_IDS(&intel_i830_info), \
380 INTEL_I845G_IDS(&intel_845g_info), \
381 INTEL_I85X_IDS(&intel_i85x_info), \
382 INTEL_I865G_IDS(&intel_i865g_info), \
383 INTEL_I915G_IDS(&intel_i915g_info), \
384 INTEL_I915GM_IDS(&intel_i915gm_info), \
385 INTEL_I945G_IDS(&intel_i945g_info), \
386 INTEL_I945GM_IDS(&intel_i945gm_info), \
387 INTEL_I965G_IDS(&intel_i965g_info), \
388 INTEL_G33_IDS(&intel_g33_info), \
389 INTEL_I965GM_IDS(&intel_i965gm_info), \
390 INTEL_GM45_IDS(&intel_gm45_info), \
391 INTEL_G45_IDS(&intel_g45_info), \
392 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
393 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
394 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
395 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
396 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
397 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
398 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
399 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
400 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
401 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
402 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
403 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
404 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
405 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
406 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
407 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
408 INTEL_CHV_IDS(&intel_cherryview_info), \
409 INTEL_SKL_IDS(&intel_skylake_info)
411 static const struct pci_device_id pciidlist[] = { /* aka */
416 #if defined(CONFIG_DRM_I915_KMS)
417 MODULE_DEVICE_TABLE(pci, pciidlist);
420 void intel_detect_pch(struct drm_device *dev)
422 struct drm_i915_private *dev_priv = dev->dev_private;
423 struct pci_dev *pch = NULL;
425 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
426 * (which really amounts to a PCH but no South Display).
428 if (INTEL_INFO(dev)->num_pipes == 0) {
429 dev_priv->pch_type = PCH_NOP;
434 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
435 * make graphics device passthrough work easy for VMM, that only
436 * need to expose ISA bridge to let driver know the real hardware
437 * underneath. This is a requirement from virtualization team.
439 * In some virtualized environments (e.g. XEN), there is irrelevant
440 * ISA bridge in the system. To work reliably, we should scan trhough
441 * all the ISA bridge devices and check for the first match, instead
442 * of only checking the first one.
444 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
445 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
446 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
447 dev_priv->pch_id = id;
449 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
450 dev_priv->pch_type = PCH_IBX;
451 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
452 WARN_ON(!IS_GEN5(dev));
453 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
454 dev_priv->pch_type = PCH_CPT;
455 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
456 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
457 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
458 /* PantherPoint is CPT compatible */
459 dev_priv->pch_type = PCH_CPT;
460 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
461 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
462 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
463 dev_priv->pch_type = PCH_LPT;
464 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
465 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
466 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
467 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
468 dev_priv->pch_type = PCH_LPT;
469 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
470 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
471 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
472 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
473 dev_priv->pch_type = PCH_SPT;
474 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
475 WARN_ON(!IS_SKYLAKE(dev));
476 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
477 dev_priv->pch_type = PCH_SPT;
478 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
479 WARN_ON(!IS_SKYLAKE(dev));
487 DRM_DEBUG_KMS("No PCH found.\n");
492 bool i915_semaphore_is_enabled(struct drm_device *dev)
494 if (INTEL_INFO(dev)->gen < 6)
497 if (i915.semaphores >= 0)
498 return i915.semaphores;
500 /* TODO: make semaphores and Execlists play nicely together */
501 if (i915.enable_execlists)
504 /* Until we get further testing... */
508 #ifdef CONFIG_INTEL_IOMMU
509 /* Enable semaphores on SNB when IO remapping is off */
510 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
517 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
519 spin_lock_irq(&dev_priv->irq_lock);
521 dev_priv->long_hpd_port_mask = 0;
522 dev_priv->short_hpd_port_mask = 0;
523 dev_priv->hpd_event_bits = 0;
525 spin_unlock_irq(&dev_priv->irq_lock);
527 cancel_work_sync(&dev_priv->dig_port_work);
528 cancel_work_sync(&dev_priv->hotplug_work);
529 cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
532 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
534 struct drm_device *dev = dev_priv->dev;
535 struct drm_encoder *encoder;
537 drm_modeset_lock_all(dev);
538 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
539 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
541 if (intel_encoder->suspend)
542 intel_encoder->suspend(intel_encoder);
544 drm_modeset_unlock_all(dev);
547 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
548 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
551 static int i915_drm_suspend(struct drm_device *dev)
553 struct drm_i915_private *dev_priv = dev->dev_private;
554 struct drm_crtc *crtc;
555 pci_power_t opregion_target_state;
557 /* ignore lid events during suspend */
558 mutex_lock(&dev_priv->modeset_restore_lock);
559 dev_priv->modeset_restore = MODESET_SUSPENDED;
560 mutex_unlock(&dev_priv->modeset_restore_lock);
562 /* We do a lot of poking in a lot of registers, make sure they work
564 intel_display_set_init_power(dev_priv, true);
566 drm_kms_helper_poll_disable(dev);
568 pci_save_state(dev->pdev);
570 /* If KMS is active, we do the leavevt stuff here */
571 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
574 error = i915_gem_suspend(dev);
576 dev_err(&dev->pdev->dev,
577 "GEM idle failed, resume might fail\n");
581 intel_suspend_gt_powersave(dev);
584 * Disable CRTCs directly since we want to preserve sw state
585 * for _thaw. Also, power gate the CRTC power wells.
587 drm_modeset_lock_all(dev);
588 for_each_crtc(dev, crtc)
589 intel_crtc_control(crtc, false);
590 drm_modeset_unlock_all(dev);
592 intel_dp_mst_suspend(dev);
594 intel_runtime_pm_disable_interrupts(dev_priv);
595 intel_hpd_cancel_work(dev_priv);
597 intel_suspend_encoders(dev_priv);
599 intel_suspend_hw(dev);
602 i915_gem_suspend_gtt_mappings(dev);
604 i915_save_state(dev);
606 opregion_target_state = PCI_D3cold;
607 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
608 if (acpi_target_system_state() < ACPI_STATE_S3)
609 opregion_target_state = PCI_D1;
611 intel_opregion_notify_adapter(dev, opregion_target_state);
613 intel_uncore_forcewake_reset(dev, false);
614 intel_opregion_fini(dev);
616 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
618 dev_priv->suspend_count++;
620 intel_display_set_init_power(dev_priv, false);
625 static int i915_drm_suspend_late(struct drm_device *drm_dev)
627 struct drm_i915_private *dev_priv = drm_dev->dev_private;
630 ret = intel_suspend_complete(dev_priv);
633 DRM_ERROR("Suspend complete failed: %d\n", ret);
638 pci_disable_device(drm_dev->pdev);
639 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
644 int i915_suspend_legacy(struct drm_device *dev, pm_message_t state)
648 if (!dev || !dev->dev_private) {
649 DRM_ERROR("dev: %p\n", dev);
650 DRM_ERROR("DRM not initialized, aborting suspend.\n");
654 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
655 state.event != PM_EVENT_FREEZE))
658 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
661 error = i915_drm_suspend(dev);
665 return i915_drm_suspend_late(dev);
668 static int i915_drm_resume(struct drm_device *dev)
670 struct drm_i915_private *dev_priv = dev->dev_private;
672 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
673 mutex_lock(&dev->struct_mutex);
674 i915_gem_restore_gtt_mappings(dev);
675 mutex_unlock(&dev->struct_mutex);
678 i915_restore_state(dev);
679 intel_opregion_setup(dev);
681 /* KMS EnterVT equivalent */
682 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
683 intel_init_pch_refclk(dev);
684 drm_mode_config_reset(dev);
686 mutex_lock(&dev->struct_mutex);
687 if (i915_gem_init_hw(dev)) {
688 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
689 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
691 mutex_unlock(&dev->struct_mutex);
693 /* We need working interrupts for modeset enabling ... */
694 intel_runtime_pm_enable_interrupts(dev_priv);
696 intel_modeset_init_hw(dev);
698 spin_lock_irq(&dev_priv->irq_lock);
699 if (dev_priv->display.hpd_irq_setup)
700 dev_priv->display.hpd_irq_setup(dev);
701 spin_unlock_irq(&dev_priv->irq_lock);
703 drm_modeset_lock_all(dev);
704 intel_modeset_setup_hw_state(dev, true);
705 drm_modeset_unlock_all(dev);
707 intel_dp_mst_resume(dev);
710 * ... but also need to make sure that hotplug processing
711 * doesn't cause havoc. Like in the driver load code we don't
712 * bother with the tiny race here where we might loose hotplug
715 intel_hpd_init(dev_priv);
716 /* Config may have changed between suspend and resume */
717 drm_helper_hpd_irq_event(dev);
720 intel_opregion_init(dev);
722 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
724 mutex_lock(&dev_priv->modeset_restore_lock);
725 dev_priv->modeset_restore = MODESET_DONE;
726 mutex_unlock(&dev_priv->modeset_restore_lock);
728 intel_opregion_notify_adapter(dev, PCI_D0);
730 drm_kms_helper_poll_enable(dev);
735 static int i915_drm_resume_early(struct drm_device *dev)
737 struct drm_i915_private *dev_priv = dev->dev_private;
741 * We have a resume ordering issue with the snd-hda driver also
742 * requiring our device to be power up. Due to the lack of a
743 * parent/child relationship we currently solve this with an early
746 * FIXME: This should be solved with a special hdmi sink device or
747 * similar so that power domains can be employed.
749 if (pci_enable_device(dev->pdev))
752 pci_set_master(dev->pdev);
754 if (IS_VALLEYVIEW(dev_priv))
755 ret = vlv_resume_prepare(dev_priv, false);
757 DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
759 intel_uncore_early_sanitize(dev, true);
761 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
762 hsw_disable_pc8(dev_priv);
764 intel_uncore_sanitize(dev);
765 intel_power_domains_init_hw(dev_priv);
770 int i915_resume_legacy(struct drm_device *dev)
774 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
777 ret = i915_drm_resume_early(dev);
781 return i915_drm_resume(dev);
785 * i915_reset - reset chip after a hang
786 * @dev: drm device to reset
788 * Reset the chip. Useful if a hang is detected. Returns zero on successful
789 * reset or otherwise an error code.
791 * Procedure is fairly simple:
792 * - reset the chip using the reset reg
793 * - re-init context state
794 * - re-init hardware status page
795 * - re-init ring buffer
796 * - re-init interrupt state
799 int i915_reset(struct drm_device *dev)
801 struct drm_i915_private *dev_priv = dev->dev_private;
808 intel_reset_gt_powersave(dev);
810 mutex_lock(&dev->struct_mutex);
814 simulated = dev_priv->gpu_error.stop_rings != 0;
816 ret = intel_gpu_reset(dev);
818 /* Also reset the gpu hangman. */
820 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
821 dev_priv->gpu_error.stop_rings = 0;
822 if (ret == -ENODEV) {
823 DRM_INFO("Reset not implemented, but ignoring "
824 "error for simulated gpu hangs\n");
829 if (i915_stop_ring_allow_warn(dev_priv))
830 pr_notice("drm/i915: Resetting chip after gpu hang\n");
833 DRM_ERROR("Failed to reset chip: %i\n", ret);
834 mutex_unlock(&dev->struct_mutex);
838 intel_overlay_reset(dev_priv);
840 /* Ok, now get things going again... */
843 * Everything depends on having the GTT running, so we need to start
844 * there. Fortunately we don't need to do this unless we reset the
845 * chip at a PCI level.
847 * Next we need to restore the context, but we don't use those
850 * Ring buffer needs to be re-initialized in the KMS case, or if X
851 * was running at the time of the reset (i.e. we weren't VT
854 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
855 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
856 dev_priv->gpu_error.reload_in_reset = true;
858 ret = i915_gem_init_hw(dev);
860 dev_priv->gpu_error.reload_in_reset = false;
862 mutex_unlock(&dev->struct_mutex);
864 DRM_ERROR("Failed hw init on reset %d\n", ret);
869 * FIXME: This races pretty badly against concurrent holders of
870 * ring interrupts. This is possible since we've started to drop
871 * dev->struct_mutex in select places when waiting for the gpu.
875 * rps/rc6 re-init is necessary to restore state lost after the
876 * reset and the re-install of gt irqs. Skip for ironlake per
877 * previous concerns that it doesn't respond well to some forms
878 * of re-init after reset.
880 if (INTEL_INFO(dev)->gen > 5)
881 intel_enable_gt_powersave(dev);
883 mutex_unlock(&dev->struct_mutex);
889 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
891 struct intel_device_info *intel_info =
892 (struct intel_device_info *) ent->driver_data;
894 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
895 DRM_INFO("This hardware requires preliminary hardware support.\n"
896 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
900 /* Only bind to function 0 of the device. Early generations
901 * used function 1 as a placeholder for multi-head. This causes
902 * us confusion instead, especially on the systems where both
903 * functions have the same PCI-ID!
905 if (PCI_FUNC(pdev->devfn))
908 driver.driver_features &= ~(DRIVER_USE_AGP);
910 return drm_get_pci_dev(pdev, ent, &driver);
914 i915_pci_remove(struct pci_dev *pdev)
916 struct drm_device *dev = pci_get_drvdata(pdev);
921 static int i915_pm_suspend(struct device *dev)
923 struct pci_dev *pdev = to_pci_dev(dev);
924 struct drm_device *drm_dev = pci_get_drvdata(pdev);
926 if (!drm_dev || !drm_dev->dev_private) {
927 dev_err(dev, "DRM not initialized, aborting suspend.\n");
931 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
934 return i915_drm_suspend(drm_dev);
937 static int i915_pm_suspend_late(struct device *dev)
939 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
942 * We have a suspedn ordering issue with the snd-hda driver also
943 * requiring our device to be power up. Due to the lack of a
944 * parent/child relationship we currently solve this with an late
947 * FIXME: This should be solved with a special hdmi sink device or
948 * similar so that power domains can be employed.
950 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
953 return i915_drm_suspend_late(drm_dev);
956 static int i915_pm_resume_early(struct device *dev)
958 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
960 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
963 return i915_drm_resume_early(drm_dev);
966 static int i915_pm_resume(struct device *dev)
968 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
970 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
973 return i915_drm_resume(drm_dev);
976 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
978 hsw_enable_pc8(dev_priv);
984 * Save all Gunit registers that may be lost after a D3 and a subsequent
985 * S0i[R123] transition. The list of registers needing a save/restore is
986 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
987 * registers in the following way:
988 * - Driver: saved/restored by the driver
989 * - Punit : saved/restored by the Punit firmware
990 * - No, w/o marking: no need to save/restore, since the register is R/O or
991 * used internally by the HW in a way that doesn't depend
992 * keeping the content across a suspend/resume.
993 * - Debug : used for debugging
995 * We save/restore all registers marked with 'Driver', with the following
997 * - Registers out of use, including also registers marked with 'Debug'.
998 * These have no effect on the driver's operation, so we don't save/restore
999 * them to reduce the overhead.
1000 * - Registers that are fully setup by an initialization function called from
1001 * the resume path. For example many clock gating and RPS/RC6 registers.
1002 * - Registers that provide the right functionality with their reset defaults.
1004 * TODO: Except for registers that based on the above 3 criteria can be safely
1005 * ignored, we save/restore all others, practically treating the HW context as
1006 * a black-box for the driver. Further investigation is needed to reduce the
1007 * saved/restored registers even further, by following the same 3 criteria.
1009 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1011 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1014 /* GAM 0x4000-0x4770 */
1015 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1016 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1017 s->arb_mode = I915_READ(ARB_MODE);
1018 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1019 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1021 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1022 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1024 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1025 s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1027 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1028 s->ecochk = I915_READ(GAM_ECOCHK);
1029 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1030 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1032 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1034 /* MBC 0x9024-0x91D0, 0x8500 */
1035 s->g3dctl = I915_READ(VLV_G3DCTL);
1036 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1037 s->mbctl = I915_READ(GEN6_MBCTL);
1039 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1040 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1041 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1042 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1043 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1044 s->rstctl = I915_READ(GEN6_RSTCTL);
1045 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1047 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1048 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1049 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1050 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1051 s->ecobus = I915_READ(ECOBUS);
1052 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1053 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1054 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1055 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1056 s->rcedata = I915_READ(VLV_RCEDATA);
1057 s->spare2gh = I915_READ(VLV_SPAREG2H);
1059 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1060 s->gt_imr = I915_READ(GTIMR);
1061 s->gt_ier = I915_READ(GTIER);
1062 s->pm_imr = I915_READ(GEN6_PMIMR);
1063 s->pm_ier = I915_READ(GEN6_PMIER);
1065 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1066 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1068 /* GT SA CZ domain, 0x100000-0x138124 */
1069 s->tilectl = I915_READ(TILECTL);
1070 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1071 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1072 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1073 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1075 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1076 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1077 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1078 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1081 * Not saving any of:
1082 * DFT, 0x9800-0x9EC0
1083 * SARB, 0xB000-0xB1FC
1084 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1089 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1091 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1095 /* GAM 0x4000-0x4770 */
1096 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1097 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1098 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1099 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1100 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1102 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1103 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1105 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1106 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1108 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1109 I915_WRITE(GAM_ECOCHK, s->ecochk);
1110 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1111 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1113 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1115 /* MBC 0x9024-0x91D0, 0x8500 */
1116 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1117 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1118 I915_WRITE(GEN6_MBCTL, s->mbctl);
1120 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1121 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1122 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1123 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1124 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1125 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1126 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1128 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1129 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1130 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1131 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1132 I915_WRITE(ECOBUS, s->ecobus);
1133 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1134 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1135 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1136 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1137 I915_WRITE(VLV_RCEDATA, s->rcedata);
1138 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1140 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1141 I915_WRITE(GTIMR, s->gt_imr);
1142 I915_WRITE(GTIER, s->gt_ier);
1143 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1144 I915_WRITE(GEN6_PMIER, s->pm_ier);
1146 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1147 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1149 /* GT SA CZ domain, 0x100000-0x138124 */
1150 I915_WRITE(TILECTL, s->tilectl);
1151 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1153 * Preserve the GT allow wake and GFX force clock bit, they are not
1154 * be restored, as they are used to control the s0ix suspend/resume
1155 * sequence by the caller.
1157 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1158 val &= VLV_GTLC_ALLOWWAKEREQ;
1159 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1160 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1162 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1163 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1164 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1165 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1167 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1169 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1170 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1171 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1172 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1175 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1180 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1181 WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1183 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1184 /* Wait for a previous force-off to settle */
1186 err = wait_for(!COND, 20);
1188 DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1189 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1194 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1195 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1197 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1198 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1203 err = wait_for(COND, 20);
1205 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1206 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1212 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1217 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1218 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1220 val |= VLV_GTLC_ALLOWWAKEREQ;
1221 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1222 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1224 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1226 err = wait_for(COND, 1);
1228 DRM_ERROR("timeout disabling GT waking\n");
1233 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1240 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1241 val = wait_for_on ? mask : 0;
1242 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1246 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1247 wait_for_on ? "on" : "off",
1248 I915_READ(VLV_GTLC_PW_STATUS));
1251 * RC6 transitioning can be delayed up to 2 msec (see
1252 * valleyview_enable_rps), use 3 msec for safety.
1254 err = wait_for(COND, 3);
1256 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1257 wait_for_on ? "on" : "off");
1263 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1265 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1268 DRM_ERROR("GT register access while GT waking disabled\n");
1269 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1272 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1278 * Bspec defines the following GT well on flags as debug only, so
1279 * don't treat them as hard failures.
1281 (void)vlv_wait_for_gt_wells(dev_priv, false);
1283 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1284 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1286 vlv_check_no_gt_access(dev_priv);
1288 err = vlv_force_gfx_clock(dev_priv, true);
1292 err = vlv_allow_gt_wake(dev_priv, false);
1296 if (!IS_CHERRYVIEW(dev_priv->dev))
1297 vlv_save_gunit_s0ix_state(dev_priv);
1299 err = vlv_force_gfx_clock(dev_priv, false);
1306 /* For safety always re-enable waking and disable gfx clock forcing */
1307 vlv_allow_gt_wake(dev_priv, true);
1309 vlv_force_gfx_clock(dev_priv, false);
1314 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1317 struct drm_device *dev = dev_priv->dev;
1322 * If any of the steps fail just try to continue, that's the best we
1323 * can do at this point. Return the first error code (which will also
1324 * leave RPM permanently disabled).
1326 ret = vlv_force_gfx_clock(dev_priv, true);
1328 if (!IS_CHERRYVIEW(dev_priv->dev))
1329 vlv_restore_gunit_s0ix_state(dev_priv);
1331 err = vlv_allow_gt_wake(dev_priv, true);
1335 err = vlv_force_gfx_clock(dev_priv, false);
1339 vlv_check_no_gt_access(dev_priv);
1342 intel_init_clock_gating(dev);
1343 i915_gem_restore_fences(dev);
1349 static int intel_runtime_suspend(struct device *device)
1351 struct pci_dev *pdev = to_pci_dev(device);
1352 struct drm_device *dev = pci_get_drvdata(pdev);
1353 struct drm_i915_private *dev_priv = dev->dev_private;
1356 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1359 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1362 DRM_DEBUG_KMS("Suspending device\n");
1365 * We could deadlock here in case another thread holding struct_mutex
1366 * calls RPM suspend concurrently, since the RPM suspend will wait
1367 * first for this RPM suspend to finish. In this case the concurrent
1368 * RPM resume will be followed by its RPM suspend counterpart. Still
1369 * for consistency return -EAGAIN, which will reschedule this suspend.
1371 if (!mutex_trylock(&dev->struct_mutex)) {
1372 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1374 * Bump the expiration timestamp, otherwise the suspend won't
1377 pm_runtime_mark_last_busy(device);
1382 * We are safe here against re-faults, since the fault handler takes
1385 i915_gem_release_all_mmaps(dev_priv);
1386 mutex_unlock(&dev->struct_mutex);
1388 intel_suspend_gt_powersave(dev);
1389 intel_runtime_pm_disable_interrupts(dev_priv);
1391 ret = intel_suspend_complete(dev_priv);
1393 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1394 intel_runtime_pm_enable_interrupts(dev_priv);
1399 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1400 intel_uncore_forcewake_reset(dev, false);
1401 dev_priv->pm.suspended = true;
1404 * FIXME: We really should find a document that references the arguments
1407 if (IS_HASWELL(dev)) {
1409 * current versions of firmware which depend on this opregion
1410 * notification have repurposed the D1 definition to mean
1411 * "runtime suspended" vs. what you would normally expect (D3)
1412 * to distinguish it from notifications that might be sent via
1415 intel_opregion_notify_adapter(dev, PCI_D1);
1418 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1419 * being detected, and the call we do at intel_runtime_resume()
1420 * won't be able to restore them. Since PCI_D3hot matches the
1421 * actual specification and appears to be working, use it. Let's
1422 * assume the other non-Haswell platforms will stay the same as
1425 intel_opregion_notify_adapter(dev, PCI_D3hot);
1428 assert_forcewakes_inactive(dev_priv);
1430 DRM_DEBUG_KMS("Device suspended\n");
1434 static int intel_runtime_resume(struct device *device)
1436 struct pci_dev *pdev = to_pci_dev(device);
1437 struct drm_device *dev = pci_get_drvdata(pdev);
1438 struct drm_i915_private *dev_priv = dev->dev_private;
1441 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1444 DRM_DEBUG_KMS("Resuming device\n");
1446 intel_opregion_notify_adapter(dev, PCI_D0);
1447 dev_priv->pm.suspended = false;
1449 if (IS_GEN6(dev_priv))
1450 intel_init_pch_refclk(dev);
1451 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1452 hsw_disable_pc8(dev_priv);
1453 else if (IS_VALLEYVIEW(dev_priv))
1454 ret = vlv_resume_prepare(dev_priv, true);
1457 * No point of rolling back things in case of an error, as the best
1458 * we can do is to hope that things will still work (and disable RPM).
1460 i915_gem_init_swizzling(dev);
1461 gen6_update_ring_freq(dev);
1463 intel_runtime_pm_enable_interrupts(dev_priv);
1464 intel_enable_gt_powersave(dev);
1467 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1469 DRM_DEBUG_KMS("Device resumed\n");
1475 * This function implements common functionality of runtime and system
1478 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1480 struct drm_device *dev = dev_priv->dev;
1483 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1484 ret = hsw_suspend_complete(dev_priv);
1485 else if (IS_VALLEYVIEW(dev))
1486 ret = vlv_suspend_complete(dev_priv);
1493 static const struct dev_pm_ops i915_pm_ops = {
1495 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1498 .suspend = i915_pm_suspend,
1499 .suspend_late = i915_pm_suspend_late,
1500 .resume_early = i915_pm_resume_early,
1501 .resume = i915_pm_resume,
1505 * @freeze, @freeze_late : called (1) before creating the
1506 * hibernation image [PMSG_FREEZE] and
1507 * (2) after rebooting, before restoring
1508 * the image [PMSG_QUIESCE]
1509 * @thaw, @thaw_early : called (1) after creating the hibernation
1510 * image, before writing it [PMSG_THAW]
1511 * and (2) after failing to create or
1512 * restore the image [PMSG_RECOVER]
1513 * @poweroff, @poweroff_late: called after writing the hibernation
1514 * image, before rebooting [PMSG_HIBERNATE]
1515 * @restore, @restore_early : called after rebooting and restoring the
1516 * hibernation image [PMSG_RESTORE]
1518 .freeze = i915_pm_suspend,
1519 .freeze_late = i915_pm_suspend_late,
1520 .thaw_early = i915_pm_resume_early,
1521 .thaw = i915_pm_resume,
1522 .poweroff = i915_pm_suspend,
1523 .poweroff_late = i915_pm_suspend_late,
1524 .restore_early = i915_pm_resume_early,
1525 .restore = i915_pm_resume,
1527 /* S0ix (via runtime suspend) event handlers */
1528 .runtime_suspend = intel_runtime_suspend,
1529 .runtime_resume = intel_runtime_resume,
1532 static const struct vm_operations_struct i915_gem_vm_ops = {
1533 .fault = i915_gem_fault,
1534 .open = drm_gem_vm_open,
1535 .close = drm_gem_vm_close,
1538 static const struct file_operations i915_driver_fops = {
1539 .owner = THIS_MODULE,
1541 .release = drm_release,
1542 .unlocked_ioctl = drm_ioctl,
1543 .mmap = drm_gem_mmap,
1546 #ifdef CONFIG_COMPAT
1547 .compat_ioctl = i915_compat_ioctl,
1549 .llseek = noop_llseek,
1552 static struct drm_driver driver = {
1553 /* Don't use MTRRs here; the Xserver or userspace app should
1554 * deal with them for Intel hardware.
1558 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1560 .load = i915_driver_load,
1561 .unload = i915_driver_unload,
1562 .open = i915_driver_open,
1563 .lastclose = i915_driver_lastclose,
1564 .preclose = i915_driver_preclose,
1565 .postclose = i915_driver_postclose,
1566 .set_busid = drm_pci_set_busid,
1568 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1569 .suspend = i915_suspend_legacy,
1570 .resume = i915_resume_legacy,
1572 .device_is_agp = i915_driver_device_is_agp,
1573 #if defined(CONFIG_DEBUG_FS)
1574 .debugfs_init = i915_debugfs_init,
1575 .debugfs_cleanup = i915_debugfs_cleanup,
1577 .gem_free_object = i915_gem_free_object,
1578 .gem_vm_ops = &i915_gem_vm_ops,
1580 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1581 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1582 .gem_prime_export = i915_gem_prime_export,
1583 .gem_prime_import = i915_gem_prime_import,
1585 .dumb_create = i915_gem_dumb_create,
1586 .dumb_map_offset = i915_gem_mmap_gtt,
1587 .dumb_destroy = drm_gem_dumb_destroy,
1588 .ioctls = i915_ioctls,
1589 .fops = &i915_driver_fops,
1590 .name = DRIVER_NAME,
1591 .desc = DRIVER_DESC,
1592 .date = DRIVER_DATE,
1593 .major = DRIVER_MAJOR,
1594 .minor = DRIVER_MINOR,
1595 .patchlevel = DRIVER_PATCHLEVEL,
1598 static struct pci_driver i915_pci_driver = {
1599 .name = DRIVER_NAME,
1600 .id_table = pciidlist,
1601 .probe = i915_pci_probe,
1602 .remove = i915_pci_remove,
1603 .driver.pm = &i915_pm_ops,
1606 static int __init i915_init(void)
1608 driver.num_ioctls = i915_max_ioctl;
1611 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1612 * explicitly disabled with the module pararmeter.
1614 * Otherwise, just follow the parameter (defaulting to off).
1616 * Allow optional vga_text_mode_force boot option to override
1617 * the default behavior.
1619 #if defined(CONFIG_DRM_I915_KMS)
1620 if (i915.modeset != 0)
1621 driver.driver_features |= DRIVER_MODESET;
1623 if (i915.modeset == 1)
1624 driver.driver_features |= DRIVER_MODESET;
1626 #ifdef CONFIG_VGA_CONSOLE
1627 if (vgacon_text_force() && i915.modeset == -1)
1628 driver.driver_features &= ~DRIVER_MODESET;
1631 if (!(driver.driver_features & DRIVER_MODESET)) {
1632 driver.get_vblank_timestamp = NULL;
1633 #ifndef CONFIG_DRM_I915_UMS
1634 /* Silently fail loading to not upset userspace. */
1635 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1641 * FIXME: Note that we're lying to the DRM core here so that we can get access
1642 * to the atomic ioctl and the atomic properties. Only plane operations on
1643 * a single CRTC will actually work.
1645 if (i915.nuclear_pageflip)
1646 driver.driver_features |= DRIVER_ATOMIC;
1648 return drm_pci_init(&driver, &i915_pci_driver);
1651 static void __exit i915_exit(void)
1653 #ifndef CONFIG_DRM_I915_UMS
1654 if (!(driver.driver_features & DRIVER_MODESET))
1655 return; /* Never loaded a driver. */
1658 drm_pci_exit(&driver, &i915_pci_driver);
1661 module_init(i915_init);
1662 module_exit(i915_exit);
1664 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1665 MODULE_AUTHOR("Intel Corporation");
1667 MODULE_DESCRIPTION(DRIVER_DESC);
1668 MODULE_LICENSE("GPL and additional rights");