1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
32 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <drm/drm_crtc_helper.h>
41 static int i915_modeset __read_mostly = -1;
42 module_param_named(modeset, i915_modeset, int, 0400);
43 MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
47 unsigned int i915_fbpercrtc __always_unused = 0;
48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
50 int i915_panel_ignore_lid __read_mostly = 0;
51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect [default], 1=lid open, "
56 unsigned int i915_powersave __read_mostly = 1;
57 module_param_named(powersave, i915_powersave, int, 0600);
58 MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
61 int i915_semaphores __read_mostly = -1;
62 module_param_named(semaphores, i915_semaphores, int, 0600);
63 MODULE_PARM_DESC(semaphores,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
66 int i915_enable_rc6 __read_mostly = -1;
67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
68 MODULE_PARM_DESC(i915_enable_rc6,
69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
75 int i915_enable_fbc __read_mostly = -1;
76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
77 MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
79 "(default: -1 (use per-chip default))");
81 unsigned int i915_lvds_downclock __read_mostly = 0;
82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
83 MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
87 int i915_lvds_channel_mode __read_mostly;
88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89 MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
93 int i915_panel_use_ssc __read_mostly = -1;
94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
95 MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
97 "(default: auto from VBT)");
99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
105 static bool i915_try_reset __read_mostly = true;
106 module_param_named(reset, i915_try_reset, bool, 0600);
107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
109 bool i915_enable_hangcheck __read_mostly = true;
110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
111 MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
116 int i915_enable_ppgtt __read_mostly = -1;
117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
118 MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
121 static struct drm_driver driver;
122 extern int intel_agp_enabled;
124 #define INTEL_VGA_DEVICE(id, info) { \
125 .class = PCI_BASE_CLASS_DISPLAY << 16, \
126 .class_mask = 0xff0000, \
129 .subvendor = PCI_ANY_ID, \
130 .subdevice = PCI_ANY_ID, \
131 .driver_data = (unsigned long) info }
133 static const struct intel_device_info intel_i830_info = {
134 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
135 .has_overlay = 1, .overlay_needs_physical = 1,
138 static const struct intel_device_info intel_845g_info = {
140 .has_overlay = 1, .overlay_needs_physical = 1,
143 static const struct intel_device_info intel_i85x_info = {
144 .gen = 2, .is_i85x = 1, .is_mobile = 1,
145 .cursor_needs_physical = 1,
146 .has_overlay = 1, .overlay_needs_physical = 1,
149 static const struct intel_device_info intel_i865g_info = {
151 .has_overlay = 1, .overlay_needs_physical = 1,
154 static const struct intel_device_info intel_i915g_info = {
155 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
156 .has_overlay = 1, .overlay_needs_physical = 1,
158 static const struct intel_device_info intel_i915gm_info = {
159 .gen = 3, .is_mobile = 1,
160 .cursor_needs_physical = 1,
161 .has_overlay = 1, .overlay_needs_physical = 1,
164 static const struct intel_device_info intel_i945g_info = {
165 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
166 .has_overlay = 1, .overlay_needs_physical = 1,
168 static const struct intel_device_info intel_i945gm_info = {
169 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
170 .has_hotplug = 1, .cursor_needs_physical = 1,
171 .has_overlay = 1, .overlay_needs_physical = 1,
175 static const struct intel_device_info intel_i965g_info = {
176 .gen = 4, .is_broadwater = 1,
181 static const struct intel_device_info intel_i965gm_info = {
182 .gen = 4, .is_crestline = 1,
183 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
188 static const struct intel_device_info intel_g33_info = {
189 .gen = 3, .is_g33 = 1,
190 .need_gfx_hws = 1, .has_hotplug = 1,
194 static const struct intel_device_info intel_g45_info = {
195 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
196 .has_pipe_cxsr = 1, .has_hotplug = 1,
200 static const struct intel_device_info intel_gm45_info = {
201 .gen = 4, .is_g4x = 1,
202 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
203 .has_pipe_cxsr = 1, .has_hotplug = 1,
208 static const struct intel_device_info intel_pineview_info = {
209 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
210 .need_gfx_hws = 1, .has_hotplug = 1,
214 static const struct intel_device_info intel_ironlake_d_info = {
216 .need_gfx_hws = 1, .has_hotplug = 1,
220 static const struct intel_device_info intel_ironlake_m_info = {
221 .gen = 5, .is_mobile = 1,
222 .need_gfx_hws = 1, .has_hotplug = 1,
227 static const struct intel_device_info intel_sandybridge_d_info = {
229 .need_gfx_hws = 1, .has_hotplug = 1,
236 static const struct intel_device_info intel_sandybridge_m_info = {
237 .gen = 6, .is_mobile = 1,
238 .need_gfx_hws = 1, .has_hotplug = 1,
246 static const struct intel_device_info intel_ivybridge_d_info = {
247 .is_ivybridge = 1, .gen = 7,
248 .need_gfx_hws = 1, .has_hotplug = 1,
255 static const struct intel_device_info intel_ivybridge_m_info = {
256 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
257 .need_gfx_hws = 1, .has_hotplug = 1,
258 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
265 static const struct intel_device_info intel_valleyview_m_info = {
266 .gen = 7, .is_mobile = 1,
267 .need_gfx_hws = 1, .has_hotplug = 1,
274 static const struct intel_device_info intel_valleyview_d_info = {
276 .need_gfx_hws = 1, .has_hotplug = 1,
283 static const struct intel_device_info intel_haswell_d_info = {
284 .is_haswell = 1, .gen = 7,
285 .need_gfx_hws = 1, .has_hotplug = 1,
292 static const struct intel_device_info intel_haswell_m_info = {
293 .is_haswell = 1, .gen = 7, .is_mobile = 1,
294 .need_gfx_hws = 1, .has_hotplug = 1,
301 static const struct pci_device_id pciidlist[] = { /* aka */
302 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
303 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
304 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
305 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
306 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
307 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
308 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
309 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
310 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
311 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
312 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
313 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
314 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
315 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
316 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
317 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
318 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
319 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
320 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
321 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
322 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
323 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
324 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
325 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
326 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
327 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
328 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
329 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
330 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
331 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
332 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
333 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
334 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
335 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
336 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
337 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
338 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
339 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
340 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
341 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
342 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
343 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
344 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
345 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
346 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
347 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
348 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
349 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
350 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
351 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
352 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
353 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
354 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
355 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
356 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
357 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
358 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
359 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
360 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
361 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
362 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
363 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
364 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
365 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
366 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
367 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
368 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
369 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
370 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
371 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
372 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
373 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
374 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
375 INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
376 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
377 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
378 INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
379 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
380 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
381 INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
382 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
383 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
384 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
388 #if defined(CONFIG_DRM_I915_KMS)
389 MODULE_DEVICE_TABLE(pci, pciidlist);
392 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
393 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
394 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
395 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
396 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
398 void intel_detect_pch(struct drm_device *dev)
400 struct drm_i915_private *dev_priv = dev->dev_private;
404 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
405 * make graphics device passthrough work easy for VMM, that only
406 * need to expose ISA bridge to let driver know the real hardware
407 * underneath. This is a requirement from virtualization team.
409 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
411 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
413 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
415 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
416 dev_priv->pch_type = PCH_IBX;
417 dev_priv->num_pch_pll = 2;
418 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
419 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
420 dev_priv->pch_type = PCH_CPT;
421 dev_priv->num_pch_pll = 2;
422 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
423 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
424 /* PantherPoint is CPT compatible */
425 dev_priv->pch_type = PCH_CPT;
426 dev_priv->num_pch_pll = 2;
427 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
428 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
429 dev_priv->pch_type = PCH_LPT;
430 dev_priv->num_pch_pll = 0;
431 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
433 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
439 bool i915_semaphore_is_enabled(struct drm_device *dev)
441 if (INTEL_INFO(dev)->gen < 6)
444 if (i915_semaphores >= 0)
445 return i915_semaphores;
447 #ifdef CONFIG_INTEL_IOMMU
448 /* Enable semaphores on SNB when IO remapping is off */
449 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
456 static int i915_drm_freeze(struct drm_device *dev)
458 struct drm_i915_private *dev_priv = dev->dev_private;
460 drm_kms_helper_poll_disable(dev);
462 pci_save_state(dev->pdev);
464 /* If KMS is active, we do the leavevt stuff here */
465 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
466 int error = i915_gem_idle(dev);
468 dev_err(&dev->pdev->dev,
469 "GEM idle failed, resume might fail\n");
473 intel_modeset_disable(dev);
475 drm_irq_uninstall(dev);
478 i915_save_state(dev);
480 intel_opregion_fini(dev);
482 /* Modeset on resume, not lid events */
483 dev_priv->modeset_on_lid = 0;
486 intel_fbdev_set_suspend(dev, 1);
492 int i915_suspend(struct drm_device *dev, pm_message_t state)
496 if (!dev || !dev->dev_private) {
497 DRM_ERROR("dev: %p\n", dev);
498 DRM_ERROR("DRM not initialized, aborting suspend.\n");
502 if (state.event == PM_EVENT_PRETHAW)
506 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
509 error = i915_drm_freeze(dev);
513 if (state.event == PM_EVENT_SUSPEND) {
514 /* Shut down the device */
515 pci_disable_device(dev->pdev);
516 pci_set_power_state(dev->pdev, PCI_D3hot);
522 static int i915_drm_thaw(struct drm_device *dev)
524 struct drm_i915_private *dev_priv = dev->dev_private;
527 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
528 mutex_lock(&dev->struct_mutex);
529 i915_gem_restore_gtt_mappings(dev);
530 mutex_unlock(&dev->struct_mutex);
533 i915_restore_state(dev);
534 intel_opregion_setup(dev);
536 /* KMS EnterVT equivalent */
537 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
538 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
539 ironlake_init_pch_refclk(dev);
541 mutex_lock(&dev->struct_mutex);
542 dev_priv->mm.suspended = 0;
544 error = i915_gem_init_hw(dev);
545 mutex_unlock(&dev->struct_mutex);
547 intel_modeset_init_hw(dev);
548 intel_modeset_setup_hw_state(dev);
549 drm_mode_config_reset(dev);
550 drm_irq_install(dev);
553 intel_opregion_init(dev);
555 dev_priv->modeset_on_lid = 0;
558 intel_fbdev_set_suspend(dev, 0);
563 int i915_resume(struct drm_device *dev)
567 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
570 if (pci_enable_device(dev->pdev))
573 pci_set_master(dev->pdev);
575 ret = i915_drm_thaw(dev);
579 drm_kms_helper_poll_enable(dev);
583 static int i8xx_do_reset(struct drm_device *dev)
585 struct drm_i915_private *dev_priv = dev->dev_private;
590 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
591 POSTING_READ(D_STATE);
593 if (IS_I830(dev) || IS_845G(dev)) {
594 I915_WRITE(DEBUG_RESET_I830,
595 DEBUG_RESET_DISPLAY |
598 POSTING_READ(DEBUG_RESET_I830);
601 I915_WRITE(DEBUG_RESET_I830, 0);
602 POSTING_READ(DEBUG_RESET_I830);
607 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
608 POSTING_READ(D_STATE);
613 static int i965_reset_complete(struct drm_device *dev)
616 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
617 return (gdrst & GRDOM_RESET_ENABLE) == 0;
620 static int i965_do_reset(struct drm_device *dev)
626 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
627 * well as the reset bit (GR/bit 0). Setting the GR bit
628 * triggers the reset; when done, the hardware will clear it.
630 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
631 pci_write_config_byte(dev->pdev, I965_GDRST,
632 gdrst | GRDOM_RENDER |
634 ret = wait_for(i965_reset_complete(dev), 500);
638 /* We can't reset render&media without also resetting display ... */
639 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
640 pci_write_config_byte(dev->pdev, I965_GDRST,
641 gdrst | GRDOM_MEDIA |
644 return wait_for(i965_reset_complete(dev), 500);
647 static int ironlake_do_reset(struct drm_device *dev)
649 struct drm_i915_private *dev_priv = dev->dev_private;
653 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
654 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
655 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
656 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
660 /* We can't reset render&media without also resetting display ... */
661 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
662 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
663 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
664 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
667 static int gen6_do_reset(struct drm_device *dev)
669 struct drm_i915_private *dev_priv = dev->dev_private;
671 unsigned long irqflags;
673 /* Hold gt_lock across reset to prevent any register access
674 * with forcewake not set correctly
676 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
680 /* GEN6_GDRST is not in the gt power well, no need to check
681 * for fifo space for the write or forcewake the chip for
684 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
686 /* Spin waiting for the device to ack the reset request */
687 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
689 /* If reset with a user forcewake, try to restore, otherwise turn it off */
690 if (dev_priv->forcewake_count)
691 dev_priv->gt.force_wake_get(dev_priv);
693 dev_priv->gt.force_wake_put(dev_priv);
695 /* Restore fifo count */
696 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
698 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
702 int intel_gpu_reset(struct drm_device *dev)
704 struct drm_i915_private *dev_priv = dev->dev_private;
707 switch (INTEL_INFO(dev)->gen) {
710 ret = gen6_do_reset(dev);
713 ret = ironlake_do_reset(dev);
716 ret = i965_do_reset(dev);
719 ret = i8xx_do_reset(dev);
723 /* Also reset the gpu hangman. */
724 if (dev_priv->stop_rings) {
725 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
726 dev_priv->stop_rings = 0;
727 if (ret == -ENODEV) {
728 DRM_ERROR("Reset not implemented, but ignoring "
729 "error for simulated gpu hangs\n");
738 * i915_reset - reset chip after a hang
739 * @dev: drm device to reset
741 * Reset the chip. Useful if a hang is detected. Returns zero on successful
742 * reset or otherwise an error code.
744 * Procedure is fairly simple:
745 * - reset the chip using the reset reg
746 * - re-init context state
747 * - re-init hardware status page
748 * - re-init ring buffer
749 * - re-init interrupt state
752 int i915_reset(struct drm_device *dev)
754 drm_i915_private_t *dev_priv = dev->dev_private;
760 mutex_lock(&dev->struct_mutex);
765 if (get_seconds() - dev_priv->last_gpu_reset < 5)
766 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
768 ret = intel_gpu_reset(dev);
770 dev_priv->last_gpu_reset = get_seconds();
772 DRM_ERROR("Failed to reset chip.\n");
773 mutex_unlock(&dev->struct_mutex);
777 /* Ok, now get things going again... */
780 * Everything depends on having the GTT running, so we need to start
781 * there. Fortunately we don't need to do this unless we reset the
782 * chip at a PCI level.
784 * Next we need to restore the context, but we don't use those
787 * Ring buffer needs to be re-initialized in the KMS case, or if X
788 * was running at the time of the reset (i.e. we weren't VT
791 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
792 !dev_priv->mm.suspended) {
793 struct intel_ring_buffer *ring;
796 dev_priv->mm.suspended = 0;
798 i915_gem_init_swizzling(dev);
800 for_each_ring(ring, dev_priv, i)
803 i915_gem_context_init(dev);
804 i915_gem_init_ppgtt(dev);
807 * It would make sense to re-init all the other hw state, at
808 * least the rps/rc6/emon init done within modeset_init_hw. For
809 * some unknown reason, this blows up my ilk, so don't.
812 mutex_unlock(&dev->struct_mutex);
814 drm_irq_uninstall(dev);
815 drm_irq_install(dev);
817 mutex_unlock(&dev->struct_mutex);
824 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
826 struct intel_device_info *intel_info =
827 (struct intel_device_info *) ent->driver_data;
829 /* Only bind to function 0 of the device. Early generations
830 * used function 1 as a placeholder for multi-head. This causes
831 * us confusion instead, especially on the systems where both
832 * functions have the same PCI-ID!
834 if (PCI_FUNC(pdev->devfn))
837 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
838 * implementation for gen3 (and only gen3) that used legacy drm maps
839 * (gasp!) to share buffers between X and the client. Hence we need to
840 * keep around the fake agp stuff for gen3, even when kms is enabled. */
841 if (intel_info->gen != 3) {
842 driver.driver_features &=
843 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
844 } else if (!intel_agp_enabled) {
845 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
849 return drm_get_pci_dev(pdev, ent, &driver);
853 i915_pci_remove(struct pci_dev *pdev)
855 struct drm_device *dev = pci_get_drvdata(pdev);
860 static int i915_pm_suspend(struct device *dev)
862 struct pci_dev *pdev = to_pci_dev(dev);
863 struct drm_device *drm_dev = pci_get_drvdata(pdev);
866 if (!drm_dev || !drm_dev->dev_private) {
867 dev_err(dev, "DRM not initialized, aborting suspend.\n");
871 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
874 error = i915_drm_freeze(drm_dev);
878 pci_disable_device(pdev);
879 pci_set_power_state(pdev, PCI_D3hot);
884 static int i915_pm_resume(struct device *dev)
886 struct pci_dev *pdev = to_pci_dev(dev);
887 struct drm_device *drm_dev = pci_get_drvdata(pdev);
889 return i915_resume(drm_dev);
892 static int i915_pm_freeze(struct device *dev)
894 struct pci_dev *pdev = to_pci_dev(dev);
895 struct drm_device *drm_dev = pci_get_drvdata(pdev);
897 if (!drm_dev || !drm_dev->dev_private) {
898 dev_err(dev, "DRM not initialized, aborting suspend.\n");
902 return i915_drm_freeze(drm_dev);
905 static int i915_pm_thaw(struct device *dev)
907 struct pci_dev *pdev = to_pci_dev(dev);
908 struct drm_device *drm_dev = pci_get_drvdata(pdev);
910 return i915_drm_thaw(drm_dev);
913 static int i915_pm_poweroff(struct device *dev)
915 struct pci_dev *pdev = to_pci_dev(dev);
916 struct drm_device *drm_dev = pci_get_drvdata(pdev);
918 return i915_drm_freeze(drm_dev);
921 static const struct dev_pm_ops i915_pm_ops = {
922 .suspend = i915_pm_suspend,
923 .resume = i915_pm_resume,
924 .freeze = i915_pm_freeze,
925 .thaw = i915_pm_thaw,
926 .poweroff = i915_pm_poweroff,
927 .restore = i915_pm_resume,
930 static const struct vm_operations_struct i915_gem_vm_ops = {
931 .fault = i915_gem_fault,
932 .open = drm_gem_vm_open,
933 .close = drm_gem_vm_close,
936 static const struct file_operations i915_driver_fops = {
937 .owner = THIS_MODULE,
939 .release = drm_release,
940 .unlocked_ioctl = drm_ioctl,
941 .mmap = drm_gem_mmap,
943 .fasync = drm_fasync,
946 .compat_ioctl = i915_compat_ioctl,
948 .llseek = noop_llseek,
951 static struct drm_driver driver = {
952 /* Don't use MTRRs here; the Xserver or userspace app should
953 * deal with them for Intel hardware.
956 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
957 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
958 .load = i915_driver_load,
959 .unload = i915_driver_unload,
960 .open = i915_driver_open,
961 .lastclose = i915_driver_lastclose,
962 .preclose = i915_driver_preclose,
963 .postclose = i915_driver_postclose,
965 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
966 .suspend = i915_suspend,
967 .resume = i915_resume,
969 .device_is_agp = i915_driver_device_is_agp,
970 .master_create = i915_master_create,
971 .master_destroy = i915_master_destroy,
972 #if defined(CONFIG_DEBUG_FS)
973 .debugfs_init = i915_debugfs_init,
974 .debugfs_cleanup = i915_debugfs_cleanup,
976 .gem_init_object = i915_gem_init_object,
977 .gem_free_object = i915_gem_free_object,
978 .gem_vm_ops = &i915_gem_vm_ops,
980 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
981 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
982 .gem_prime_export = i915_gem_prime_export,
983 .gem_prime_import = i915_gem_prime_import,
985 .dumb_create = i915_gem_dumb_create,
986 .dumb_map_offset = i915_gem_mmap_gtt,
987 .dumb_destroy = i915_gem_dumb_destroy,
988 .ioctls = i915_ioctls,
989 .fops = &i915_driver_fops,
993 .major = DRIVER_MAJOR,
994 .minor = DRIVER_MINOR,
995 .patchlevel = DRIVER_PATCHLEVEL,
998 static struct pci_driver i915_pci_driver = {
1000 .id_table = pciidlist,
1001 .probe = i915_pci_probe,
1002 .remove = i915_pci_remove,
1003 .driver.pm = &i915_pm_ops,
1006 static int __init i915_init(void)
1008 driver.num_ioctls = i915_max_ioctl;
1011 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1012 * explicitly disabled with the module pararmeter.
1014 * Otherwise, just follow the parameter (defaulting to off).
1016 * Allow optional vga_text_mode_force boot option to override
1017 * the default behavior.
1019 #if defined(CONFIG_DRM_I915_KMS)
1020 if (i915_modeset != 0)
1021 driver.driver_features |= DRIVER_MODESET;
1023 if (i915_modeset == 1)
1024 driver.driver_features |= DRIVER_MODESET;
1026 #ifdef CONFIG_VGA_CONSOLE
1027 if (vgacon_text_force() && i915_modeset == -1)
1028 driver.driver_features &= ~DRIVER_MODESET;
1031 if (!(driver.driver_features & DRIVER_MODESET))
1032 driver.get_vblank_timestamp = NULL;
1034 return drm_pci_init(&driver, &i915_pci_driver);
1037 static void __exit i915_exit(void)
1039 drm_pci_exit(&driver, &i915_pci_driver);
1042 module_init(i915_init);
1043 module_exit(i915_exit);
1045 MODULE_AUTHOR(DRIVER_AUTHOR);
1046 MODULE_DESCRIPTION(DRIVER_DESC);
1047 MODULE_LICENSE("GPL and additional rights");
1049 /* We give fast paths for the really cool registers */
1050 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1051 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1052 ((reg) < 0x40000) && \
1053 ((reg) != FORCEWAKE))
1055 static bool IS_DISPLAYREG(u32 reg)
1058 * This should make it easier to transition modules over to the
1059 * new register block scheme, since we can do it incrementally.
1061 if (reg >= VLV_DISPLAY_BASE)
1064 if (reg >= RENDER_RING_BASE &&
1065 reg < RENDER_RING_BASE + 0xff)
1067 if (reg >= GEN6_BSD_RING_BASE &&
1068 reg < GEN6_BSD_RING_BASE + 0xff)
1070 if (reg >= BLT_RING_BASE &&
1071 reg < BLT_RING_BASE + 0xff)
1074 if (reg == PGTBL_ER)
1077 if (reg >= IPEIR_I965 &&
1084 if (reg == GFX_MODE_GEN7)
1087 if (reg == RENDER_HWS_PGA_GEN7 ||
1088 reg == BSD_HWS_PGA_GEN7 ||
1089 reg == BLT_HWS_PGA_GEN7)
1092 if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
1093 reg == GEN6_BSD_RNCID)
1096 if (reg == GEN6_BLITTER_ECOSKPD)
1099 if (reg >= 0x4000c &&
1103 if (reg >= 0x4f000 &&
1107 if (reg >= 0x4f100 &&
1111 if (reg >= VLV_MASTER_IER &&
1115 if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
1116 reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
1119 if (reg >= VLV_IIR_RW &&
1123 if (reg == FORCEWAKE_VLV ||
1124 reg == FORCEWAKE_ACK_VLV)
1127 if (reg == GEN6_GDRST)
1133 #define __i915_read(x, y) \
1134 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1136 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1137 unsigned long irqflags; \
1138 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1139 if (dev_priv->forcewake_count == 0) \
1140 dev_priv->gt.force_wake_get(dev_priv); \
1141 val = read##y(dev_priv->regs + reg); \
1142 if (dev_priv->forcewake_count == 0) \
1143 dev_priv->gt.force_wake_put(dev_priv); \
1144 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1145 } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1146 val = read##y(dev_priv->regs + reg + 0x180000); \
1148 val = read##y(dev_priv->regs + reg); \
1150 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1160 #define __i915_write(x, y) \
1161 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1162 u32 __fifo_ret = 0; \
1163 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1164 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1165 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1167 if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1168 write##y(val, dev_priv->regs + reg + 0x180000); \
1170 write##y(val, dev_priv->regs + reg); \
1172 if (unlikely(__fifo_ret)) { \
1173 gen6_gt_check_fifodbg(dev_priv); \
1175 if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1176 DRM_ERROR("Unclaimed write to %x\n", reg); \
1177 writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \
1186 static const struct register_whitelist {
1189 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1191 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1194 int i915_reg_read_ioctl(struct drm_device *dev,
1195 void *data, struct drm_file *file)
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 struct drm_i915_reg_read *reg = data;
1199 struct register_whitelist const *entry = whitelist;
1202 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1203 if (entry->offset == reg->offset &&
1204 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1208 if (i == ARRAY_SIZE(whitelist))
1211 switch (entry->size) {
1213 reg->val = I915_READ64(reg->offset);
1216 reg->val = I915_READ(reg->offset);
1219 reg->val = I915_READ16(reg->offset);
1222 reg->val = I915_READ8(reg->offset);