drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/i915_drm.h>
  47
  48 #include "i915_drv.h"
  49 #include "i915_trace.h"
  50 #include "i915_vgpu.h"
  51 #include "intel_drv.h"
  52
  53 static struct drm_driver driver;
  54
  55 static unsigned int i915_load_fail_count;
  56
  57 bool __i915_inject_load_failure(const char *func, int line)
  58 {
  59         if (i915_load_fail_count >= i915.inject_load_failure)
  60                 return false;
  61
  62         if (++i915_load_fail_count == i915.inject_load_failure) {
  63                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  64                          i915.inject_load_failure, func, line);
  65                 return true;
  66         }
  67
  68         return false;
  69 }
  70
  71 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  72 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  73                     "providing the dmesg log by booting with drm.debug=0xf"
  74
  75 void
  76 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  77               const char *fmt, ...)
  78 {
  79         static bool shown_bug_once;
  80         struct device *kdev = dev_priv->drm.dev;
  81         bool is_error = level[1] <= KERN_ERR[1];
  82         bool is_debug = level[1] == KERN_DEBUG[1];
  83         struct va_format vaf;
  84         va_list args;
  85
  86         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  87                 return;
  88
  89         va_start(args, fmt);
  90
  91         vaf.fmt = fmt;
  92         vaf.va = &args;
  93
  94         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  95                    __builtin_return_address(0), &vaf);
  96
  97         if (is_error && !shown_bug_once) {
  98                 dev_notice(kdev, "%s", FDO_BUG_MSG);
  99                 shown_bug_once = true;
 100         }
 101
 102         va_end(args);
 103 }
 104
 105 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 106 {
 107         return i915.inject_load_failure &&
 108                i915_load_fail_count == i915.inject_load_failure;
 109 }
 110
 111 #define i915_load_error(dev_priv, fmt, ...)                                  \
 112         __i915_printk(dev_priv,                                              \
 113                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 114                       fmt, ##__VA_ARGS__)
 115
 116
 117 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 118 {
 119         enum intel_pch ret = PCH_NOP;
 120
 121         /*
 122          * In a virtualized passthrough environment we can be in a
 123          * setup where the ISA bridge is not able to be passed through.
 124          * In this case, a south bridge can be emulated and we have to
 125          * make an educated guess as to which PCH is really there.
 126          */
 127
 128         if (IS_GEN5(dev_priv)) {
 129                 ret = PCH_IBX;
 130                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 131         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 132                 ret = PCH_CPT;
 133                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 134         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 135                 ret = PCH_LPT;
 136                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 137         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 138                 ret = PCH_SPT;
 139                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 140         }
 141
 142         return ret;
 143 }
 144
 145 static void intel_detect_pch(struct drm_device *dev)
 146 {
 147         struct drm_i915_private *dev_priv = to_i915(dev);
 148         struct pci_dev *pch = NULL;
 149
 150         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 151          * (which really amounts to a PCH but no South Display).
 152          */
 153         if (INTEL_INFO(dev)->num_pipes == 0) {
 154                 dev_priv->pch_type = PCH_NOP;
 155                 return;
 156         }
 157
 158         /*
 159          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 160          * make graphics device passthrough work easy for VMM, that only
 161          * need to expose ISA bridge to let driver know the real hardware
 162          * underneath. This is a requirement from virtualization team.
 163          *
 164          * In some virtualized environments (e.g. XEN), there is irrelevant
 165          * ISA bridge in the system. To work reliably, we should scan trhough
 166          * all the ISA bridge devices and check for the first match, instead
 167          * of only checking the first one.
 168          */
 169         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 170                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 171                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 172                         dev_priv->pch_id = id;
 173
 174                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 175                                 dev_priv->pch_type = PCH_IBX;
 176                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 177                                 WARN_ON(!IS_GEN5(dev_priv));
 178                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 179                                 dev_priv->pch_type = PCH_CPT;
 180                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 181                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 182                                         IS_IVYBRIDGE(dev_priv)));
 183                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 184                                 /* PantherPoint is CPT compatible */
 185                                 dev_priv->pch_type = PCH_CPT;
 186                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 187                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 188                                         IS_IVYBRIDGE(dev_priv)));
 189                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 190                                 dev_priv->pch_type = PCH_LPT;
 191                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 192                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 193                                         !IS_BROADWELL(dev_priv));
 194                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 195                                         IS_BDW_ULT(dev_priv));
 196                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 197                                 dev_priv->pch_type = PCH_LPT;
 198                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 199                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 200                                         !IS_BROADWELL(dev_priv));
 201                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 202                                         !IS_BDW_ULT(dev_priv));
 203                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 204                                 dev_priv->pch_type = PCH_SPT;
 205                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 206                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 207                                         !IS_KABYLAKE(dev_priv));
 208                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 209                                 dev_priv->pch_type = PCH_SPT;
 210                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 211                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 212                                         !IS_KABYLAKE(dev_priv));
 213                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 214                                 dev_priv->pch_type = PCH_KBP;
 215                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 216                                 WARN_ON(!IS_KABYLAKE(dev_priv));
 217                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 218                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 219                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 220                                     pch->subsystem_vendor ==
 221                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 222                                     pch->subsystem_device ==
 223                                             PCI_SUBDEVICE_ID_QEMU)) {
 224                                 dev_priv->pch_type =
 225                                         intel_virt_detect_pch(dev_priv);
 226                         } else
 227                                 continue;
 228
 229                         break;
 230                 }
 231         }
 232         if (!pch)
 233                 DRM_DEBUG_KMS("No PCH found.\n");
 234
 235         pci_dev_put(pch);
 236 }
 237
 238 static int i915_getparam(struct drm_device *dev, void *data,
 239                          struct drm_file *file_priv)
 240 {
 241         struct drm_i915_private *dev_priv = to_i915(dev);
 242         struct pci_dev *pdev = dev_priv->drm.pdev;
 243         drm_i915_getparam_t *param = data;
 244         int value;
 245
 246         switch (param->param) {
 247         case I915_PARAM_IRQ_ACTIVE:
 248         case I915_PARAM_ALLOW_BATCHBUFFER:
 249         case I915_PARAM_LAST_DISPATCH:
 250                 /* Reject all old ums/dri params. */
 251                 return -ENODEV;
 252         case I915_PARAM_CHIPSET_ID:
 253                 value = pdev->device;
 254                 break;
 255         case I915_PARAM_REVISION:
 256                 value = pdev->revision;
 257                 break;
 258         case I915_PARAM_NUM_FENCES_AVAIL:
 259                 value = dev_priv->num_fence_regs;
 260                 break;
 261         case I915_PARAM_HAS_OVERLAY:
 262                 value = dev_priv->overlay ? 1 : 0;
 263                 break;
 264         case I915_PARAM_HAS_BSD:
 265                 value = !!dev_priv->engine[VCS];
 266                 break;
 267         case I915_PARAM_HAS_BLT:
 268                 value = !!dev_priv->engine[BCS];
 269                 break;
 270         case I915_PARAM_HAS_VEBOX:
 271                 value = !!dev_priv->engine[VECS];
 272                 break;
 273         case I915_PARAM_HAS_BSD2:
 274                 value = !!dev_priv->engine[VCS2];
 275                 break;
 276         case I915_PARAM_HAS_EXEC_CONSTANTS:
 277                 value = INTEL_GEN(dev_priv) >= 4;
 278                 break;
 279         case I915_PARAM_HAS_LLC:
 280                 value = HAS_LLC(dev_priv);
 281                 break;
 282         case I915_PARAM_HAS_WT:
 283                 value = HAS_WT(dev_priv);
 284                 break;
 285         case I915_PARAM_HAS_ALIASING_PPGTT:
 286                 value = USES_PPGTT(dev_priv);
 287                 break;
 288         case I915_PARAM_HAS_SEMAPHORES:
 289                 value = i915.semaphores;
 290                 break;
 291         case I915_PARAM_HAS_SECURE_BATCHES:
 292                 value = capable(CAP_SYS_ADMIN);
 293                 break;
 294         case I915_PARAM_CMD_PARSER_VERSION:
 295                 value = i915_cmd_parser_get_version(dev_priv);
 296                 break;
 297         case I915_PARAM_SUBSLICE_TOTAL:
 298                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 299                 if (!value)
 300                         return -ENODEV;
 301                 break;
 302         case I915_PARAM_EU_TOTAL:
 303                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 304                 if (!value)
 305                         return -ENODEV;
 306                 break;
 307         case I915_PARAM_HAS_GPU_RESET:
 308                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 309                 break;
 310         case I915_PARAM_HAS_RESOURCE_STREAMER:
 311                 value = HAS_RESOURCE_STREAMER(dev_priv);
 312                 break;
 313         case I915_PARAM_HAS_POOLED_EU:
 314                 value = HAS_POOLED_EU(dev_priv);
 315                 break;
 316         case I915_PARAM_MIN_EU_IN_POOL:
 317                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 318                 break;
 319         case I915_PARAM_MMAP_GTT_VERSION:
 320                 /* Though we've started our numbering from 1, and so class all
 321                  * earlier versions as 0, in effect their value is undefined as
 322                  * the ioctl will report EINVAL for the unknown param!
 323                  */
 324                 value = i915_gem_mmap_gtt_version();
 325                 break;
 326         case I915_PARAM_MMAP_VERSION:
 327                 /* Remember to bump this if the version changes! */
 328         case I915_PARAM_HAS_GEM:
 329         case I915_PARAM_HAS_PAGEFLIPPING:
 330         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 331         case I915_PARAM_HAS_RELAXED_FENCING:
 332         case I915_PARAM_HAS_COHERENT_RINGS:
 333         case I915_PARAM_HAS_RELAXED_DELTA:
 334         case I915_PARAM_HAS_GEN7_SOL_RESET:
 335         case I915_PARAM_HAS_WAIT_TIMEOUT:
 336         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 337         case I915_PARAM_HAS_PINNED_BATCHES:
 338         case I915_PARAM_HAS_EXEC_NO_RELOC:
 339         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 340         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 341         case I915_PARAM_HAS_EXEC_SOFTPIN:
 342                 /* For the time being all of these are always true;
 343                  * if some supported hardware does not have one of these
 344                  * features this value needs to be provided from
 345                  * INTEL_INFO(), a feature macro, or similar.
 346                  */
 347                 value = 1;
 348                 break;
 349         default:
 350                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 351                 return -EINVAL;
 352         }
 353
 354         if (put_user(value, param->value))
 355                 return -EFAULT;
 356
 357         return 0;
 358 }
 359
 360 static int i915_get_bridge_dev(struct drm_device *dev)
 361 {
 362         struct drm_i915_private *dev_priv = to_i915(dev);
 363
 364         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 365         if (!dev_priv->bridge_dev) {
 366                 DRM_ERROR("bridge device not found\n");
 367                 return -1;
 368         }
 369         return 0;
 370 }
 371
 372 /* Allocate space for the MCH regs if needed, return nonzero on error */
 373 static int
 374 intel_alloc_mchbar_resource(struct drm_device *dev)
 375 {
 376         struct drm_i915_private *dev_priv = to_i915(dev);
 377         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 378         u32 temp_lo, temp_hi = 0;
 379         u64 mchbar_addr;
 380         int ret;
 381
 382         if (INTEL_INFO(dev)->gen >= 4)
 383                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 384         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 385         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 386
 387         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 388 #ifdef CONFIG_PNP
 389         if (mchbar_addr &&
 390             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 391                 return 0;
 392 #endif
 393
 394         /* Get some space for it */
 395         dev_priv->mch_res.name = "i915 MCHBAR";
 396         dev_priv->mch_res.flags = IORESOURCE_MEM;
 397         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 398                                      &dev_priv->mch_res,
 399                                      MCHBAR_SIZE, MCHBAR_SIZE,
 400                                      PCIBIOS_MIN_MEM,
 401                                      0, pcibios_align_resource,
 402                                      dev_priv->bridge_dev);
 403         if (ret) {
 404                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 405                 dev_priv->mch_res.start = 0;
 406                 return ret;
 407         }
 408
 409         if (INTEL_INFO(dev)->gen >= 4)
 410                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 411                                        upper_32_bits(dev_priv->mch_res.start));
 412
 413         pci_write_config_dword(dev_priv->bridge_dev, reg,
 414                                lower_32_bits(dev_priv->mch_res.start));
 415         return 0;
 416 }
 417
 418 /* Setup MCHBAR if possible, return true if we should disable it again */
 419 static void
 420 intel_setup_mchbar(struct drm_device *dev)
 421 {
 422         struct drm_i915_private *dev_priv = to_i915(dev);
 423         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 424         u32 temp;
 425         bool enabled;
 426
 427         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 428                 return;
 429
 430         dev_priv->mchbar_need_disable = false;
 431
 432         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 433                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 434                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 435         } else {
 436                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 437                 enabled = temp & 1;
 438         }
 439
 440         /* If it's already enabled, don't have to do anything */
 441         if (enabled)
 442                 return;
 443
 444         if (intel_alloc_mchbar_resource(dev))
 445                 return;
 446
 447         dev_priv->mchbar_need_disable = true;
 448
 449         /* Space is allocated or reserved, so enable it. */
 450         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 451                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 452                                        temp | DEVEN_MCHBAR_EN);
 453         } else {
 454                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 455                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 456         }
 457 }
 458
 459 static void
 460 intel_teardown_mchbar(struct drm_device *dev)
 461 {
 462         struct drm_i915_private *dev_priv = to_i915(dev);
 463         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 464
 465         if (dev_priv->mchbar_need_disable) {
 466                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 467                         u32 deven_val;
 468
 469                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 470                                               &deven_val);
 471                         deven_val &= ~DEVEN_MCHBAR_EN;
 472                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 473                                                deven_val);
 474                 } else {
 475                         u32 mchbar_val;
 476
 477                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 478                                               &mchbar_val);
 479                         mchbar_val &= ~1;
 480                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 481                                                mchbar_val);
 482                 }
 483         }
 484
 485         if (dev_priv->mch_res.start)
 486                 release_resource(&dev_priv->mch_res);
 487 }
 488
 489 /* true = enable decode, false = disable decoder */
 490 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 491 {
 492         struct drm_device *dev = cookie;
 493
 494         intel_modeset_vga_set_state(dev, state);
 495         if (state)
 496                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 497                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 498         else
 499                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 500 }
 501
 502 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 503 {
 504         struct drm_device *dev = pci_get_drvdata(pdev);
 505         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 506
 507         if (state == VGA_SWITCHEROO_ON) {
 508                 pr_info("switched on\n");
 509                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 510                 /* i915 resume handler doesn't set to D0 */
 511                 pci_set_power_state(pdev, PCI_D0);
 512                 i915_resume_switcheroo(dev);
 513                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 514         } else {
 515                 pr_info("switched off\n");
 516                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 517                 i915_suspend_switcheroo(dev, pmm);
 518                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 519         }
 520 }
 521
 522 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 523 {
 524         struct drm_device *dev = pci_get_drvdata(pdev);
 525
 526         /*
 527          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 528          * locking inversion with the driver load path. And the access here is
 529          * completely racy anyway. So don't bother with locking for now.
 530          */
 531         return dev->open_count == 0;
 532 }
 533
 534 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 535         .set_gpu_state = i915_switcheroo_set_state,
 536         .reprobe = NULL,
 537         .can_switch = i915_switcheroo_can_switch,
 538 };
 539
 540 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 541 {
 542         mutex_lock(&dev_priv->drm.struct_mutex);
 543         i915_gem_cleanup_engines(&dev_priv->drm);
 544         i915_gem_context_fini(&dev_priv->drm);
 545         mutex_unlock(&dev_priv->drm.struct_mutex);
 546
 547         rcu_barrier();
 548         flush_work(&dev_priv->mm.free_work);
 549
 550         WARN_ON(!list_empty(&dev_priv->context_list));
 551 }
 552
 553 static int i915_load_modeset_init(struct drm_device *dev)
 554 {
 555         struct drm_i915_private *dev_priv = to_i915(dev);
 556         struct pci_dev *pdev = dev_priv->drm.pdev;
 557         int ret;
 558
 559         if (i915_inject_load_failure())
 560                 return -ENODEV;
 561
 562         ret = intel_bios_init(dev_priv);
 563         if (ret)
 564                 DRM_INFO("failed to find VBIOS tables\n");
 565
 566         /* If we have > 1 VGA cards, then we need to arbitrate access
 567          * to the common VGA resources.
 568          *
 569          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 570          * then we do not take part in VGA arbitration and the
 571          * vga_client_register() fails with -ENODEV.
 572          */
 573         ret = vga_client_register(pdev, dev, NULL, i915_vga_set_decode);
 574         if (ret && ret != -ENODEV)
 575                 goto out;
 576
 577         intel_register_dsm_handler();
 578
 579         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 580         if (ret)
 581                 goto cleanup_vga_client;
 582
 583         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 584         intel_update_rawclk(dev_priv);
 585
 586         intel_power_domains_init_hw(dev_priv, false);
 587
 588         intel_csr_ucode_init(dev_priv);
 589
 590         ret = intel_irq_install(dev_priv);
 591         if (ret)
 592                 goto cleanup_csr;
 593
 594         intel_setup_gmbus(dev);
 595
 596         /* Important: The output setup functions called by modeset_init need
 597          * working irqs for e.g. gmbus and dp aux transfers. */
 598         ret = intel_modeset_init(dev);
 599         if (ret)
 600                 goto cleanup_irq;
 601
 602         intel_guc_init(dev);
 603
 604         ret = i915_gem_init(dev);
 605         if (ret)
 606                 goto cleanup_irq;
 607
 608         intel_modeset_gem_init(dev);
 609
 610         if (INTEL_INFO(dev)->num_pipes == 0)
 611                 return 0;
 612
 613         ret = intel_fbdev_init(dev);
 614         if (ret)
 615                 goto cleanup_gem;
 616
 617         /* Only enable hotplug handling once the fbdev is fully set up. */
 618         intel_hpd_init(dev_priv);
 619
 620         drm_kms_helper_poll_init(dev);
 621
 622         return 0;
 623
 624 cleanup_gem:
 625         if (i915_gem_suspend(dev))
 626                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 627         i915_gem_fini(dev_priv);
 628 cleanup_irq:
 629         intel_guc_fini(dev);
 630         drm_irq_uninstall(dev);
 631         intel_teardown_gmbus(dev);
 632 cleanup_csr:
 633         intel_csr_ucode_fini(dev_priv);
 634         intel_power_domains_fini(dev_priv);
 635         vga_switcheroo_unregister_client(pdev);
 636 cleanup_vga_client:
 637         vga_client_register(pdev, NULL, NULL, NULL);
 638 out:
 639         return ret;
 640 }
 641
 642 #if IS_ENABLED(CONFIG_FB)
 643 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 644 {
 645         struct apertures_struct *ap;
 646         struct pci_dev *pdev = dev_priv->drm.pdev;
 647         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 648         bool primary;
 649         int ret;
 650
 651         ap = alloc_apertures(1);
 652         if (!ap)
 653                 return -ENOMEM;
 654
 655         ap->ranges[0].base = ggtt->mappable_base;
 656         ap->ranges[0].size = ggtt->mappable_end;
 657
 658         primary =
 659                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 660
 661         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 662
 663         kfree(ap);
 664
 665         return ret;
 666 }
 667 #else
 668 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 669 {
 670         return 0;
 671 }
 672 #endif
 673
 674 #if !defined(CONFIG_VGA_CONSOLE)
 675 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 676 {
 677         return 0;
 678 }
 679 #elif !defined(CONFIG_DUMMY_CONSOLE)
 680 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 681 {
 682         return -ENODEV;
 683 }
 684 #else
 685 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 686 {
 687         int ret = 0;
 688
 689         DRM_INFO("Replacing VGA console driver\n");
 690
 691         console_lock();
 692         if (con_is_bound(&vga_con))
 693                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 694         if (ret == 0) {
 695                 ret = do_unregister_con_driver(&vga_con);
 696
 697                 /* Ignore "already unregistered". */
 698                 if (ret == -ENODEV)
 699                         ret = 0;
 700         }
 701         console_unlock();
 702
 703         return ret;
 704 }
 705 #endif
 706
 707 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 708 {
 709         /*
 710          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 711          * CHV x1 PHY (DP/HDMI D)
 712          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 713          */
 714         if (IS_CHERRYVIEW(dev_priv)) {
 715                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 716                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 717         } else if (IS_VALLEYVIEW(dev_priv)) {
 718                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 719         }
 720 }
 721
 722 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 723 {
 724         /*
 725          * The i915 workqueue is primarily used for batched retirement of
 726          * requests (and thus managing bo) once the task has been completed
 727          * by the GPU. i915_gem_retire_requests() is called directly when we
 728          * need high-priority retirement, such as waiting for an explicit
 729          * bo.
 730          *
 731          * It is also used for periodic low-priority events, such as
 732          * idle-timers and recording error state.
 733          *
 734          * All tasks on the workqueue are expected to acquire the dev mutex
 735          * so there is no point in running more than one instance of the
 736          * workqueue at any time.  Use an ordered one.
 737          */
 738         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 739         if (dev_priv->wq == NULL)
 740                 goto out_err;
 741
 742         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 743         if (dev_priv->hotplug.dp_wq == NULL)
 744                 goto out_free_wq;
 745
 746         return 0;
 747
 748 out_free_wq:
 749         destroy_workqueue(dev_priv->wq);
 750 out_err:
 751         DRM_ERROR("Failed to allocate workqueues.\n");
 752
 753         return -ENOMEM;
 754 }
 755
 756 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 757 {
 758         destroy_workqueue(dev_priv->hotplug.dp_wq);
 759         destroy_workqueue(dev_priv->wq);
 760 }
 761
 762 /*
 763  * We don't keep the workarounds for pre-production hardware, so we expect our
 764  * driver to fail on these machines in one way or another. A little warning on
 765  * dmesg may help both the user and the bug triagers.
 766  */
 767 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 768 {
 769         if (IS_HSW_EARLY_SDV(dev_priv) ||
 770             IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
 771                 DRM_ERROR("This is a pre-production stepping. "
 772                           "It may not be fully functional.\n");
 773 }
 774
 775 /**
 776  * i915_driver_init_early - setup state not requiring device access
 777  * @dev_priv: device private
 778  *
 779  * Initialize everything that is a "SW-only" state, that is state not
 780  * requiring accessing the device or exposing the driver via kernel internal
 781  * or userspace interfaces. Example steps belonging here: lock initialization,
 782  * system memory allocation, setting up device specific attributes and
 783  * function hooks not requiring accessing the device.
 784  */
 785 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 786                                   const struct pci_device_id *ent)
 787 {
 788         const struct intel_device_info *match_info =
 789                 (struct intel_device_info *)ent->driver_data;
 790         struct intel_device_info *device_info;
 791         int ret = 0;
 792
 793         if (i915_inject_load_failure())
 794                 return -ENODEV;
 795
 796         /* Setup the write-once "constant" device info */
 797         device_info = mkwrite_device_info(dev_priv);
 798         memcpy(device_info, match_info, sizeof(*device_info));
 799         device_info->device_id = dev_priv->drm.pdev->device;
 800
 801         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 802         device_info->gen_mask = BIT(device_info->gen - 1);
 803
 804         spin_lock_init(&dev_priv->irq_lock);
 805         spin_lock_init(&dev_priv->gpu_error.lock);
 806         mutex_init(&dev_priv->backlight_lock);
 807         spin_lock_init(&dev_priv->uncore.lock);
 808         spin_lock_init(&dev_priv->mm.object_stat_lock);
 809         spin_lock_init(&dev_priv->mmio_flip_lock);
 810         mutex_init(&dev_priv->sb_lock);
 811         mutex_init(&dev_priv->modeset_restore_lock);
 812         mutex_init(&dev_priv->av_mutex);
 813         mutex_init(&dev_priv->wm.wm_mutex);
 814         mutex_init(&dev_priv->pps_mutex);
 815
 816         i915_memcpy_init_early(dev_priv);
 817
 818         ret = i915_workqueues_init(dev_priv);
 819         if (ret < 0)
 820                 return ret;
 821
 822         ret = intel_gvt_init(dev_priv);
 823         if (ret < 0)
 824                 goto err_workqueues;
 825
 826         /* This must be called before any calls to HAS_PCH_* */
 827         intel_detect_pch(&dev_priv->drm);
 828
 829         intel_pm_setup(&dev_priv->drm);
 830         intel_init_dpio(dev_priv);
 831         intel_power_domains_init(dev_priv);
 832         intel_irq_init(dev_priv);
 833         intel_hangcheck_init(dev_priv);
 834         intel_init_display_hooks(dev_priv);
 835         intel_init_clock_gating_hooks(dev_priv);
 836         intel_init_audio_hooks(dev_priv);
 837         ret = i915_gem_load_init(&dev_priv->drm);
 838         if (ret < 0)
 839                 goto err_gvt;
 840
 841         intel_display_crc_init(dev_priv);
 842
 843         intel_device_info_dump(dev_priv);
 844
 845         intel_detect_preproduction_hw(dev_priv);
 846
 847         return 0;
 848
 849 err_gvt:
 850         intel_gvt_cleanup(dev_priv);
 851 err_workqueues:
 852         i915_workqueues_cleanup(dev_priv);
 853         return ret;
 854 }
 855
 856 /**
 857  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 858  * @dev_priv: device private
 859  */
 860 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 861 {
 862         i915_gem_load_cleanup(&dev_priv->drm);
 863         i915_workqueues_cleanup(dev_priv);
 864 }
 865
 866 static int i915_mmio_setup(struct drm_device *dev)
 867 {
 868         struct drm_i915_private *dev_priv = to_i915(dev);
 869         struct pci_dev *pdev = dev_priv->drm.pdev;
 870         int mmio_bar;
 871         int mmio_size;
 872
 873         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 874         /*
 875          * Before gen4, the registers and the GTT are behind different BARs.
 876          * However, from gen4 onwards, the registers and the GTT are shared
 877          * in the same BAR, so we want to restrict this ioremap from
 878          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 879          * the register BAR remains the same size for all the earlier
 880          * generations up to Ironlake.
 881          */
 882         if (INTEL_INFO(dev)->gen < 5)
 883                 mmio_size = 512 * 1024;
 884         else
 885                 mmio_size = 2 * 1024 * 1024;
 886         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 887         if (dev_priv->regs == NULL) {
 888                 DRM_ERROR("failed to map registers\n");
 889
 890                 return -EIO;
 891         }
 892
 893         /* Try to make sure MCHBAR is enabled before poking at it */
 894         intel_setup_mchbar(dev);
 895
 896         return 0;
 897 }
 898
 899 static void i915_mmio_cleanup(struct drm_device *dev)
 900 {
 901         struct drm_i915_private *dev_priv = to_i915(dev);
 902         struct pci_dev *pdev = dev_priv->drm.pdev;
 903
 904         intel_teardown_mchbar(dev);
 905         pci_iounmap(pdev, dev_priv->regs);
 906 }
 907
 908 /**
 909  * i915_driver_init_mmio - setup device MMIO
 910  * @dev_priv: device private
 911  *
 912  * Setup minimal device state necessary for MMIO accesses later in the
 913  * initialization sequence. The setup here should avoid any other device-wide
 914  * side effects or exposing the driver via kernel internal or user space
 915  * interfaces.
 916  */
 917 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 918 {
 919         struct drm_device *dev = &dev_priv->drm;
 920         int ret;
 921
 922         if (i915_inject_load_failure())
 923                 return -ENODEV;
 924
 925         if (i915_get_bridge_dev(dev))
 926                 return -EIO;
 927
 928         ret = i915_mmio_setup(dev);
 929         if (ret < 0)
 930                 goto put_bridge;
 931
 932         intel_uncore_init(dev_priv);
 933
 934         return 0;
 935
 936 put_bridge:
 937         pci_dev_put(dev_priv->bridge_dev);
 938
 939         return ret;
 940 }
 941
 942 /**
 943  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 944  * @dev_priv: device private
 945  */
 946 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 947 {
 948         struct drm_device *dev = &dev_priv->drm;
 949
 950         intel_uncore_fini(dev_priv);
 951         i915_mmio_cleanup(dev);
 952         pci_dev_put(dev_priv->bridge_dev);
 953 }
 954
 955 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 956 {
 957         i915.enable_execlists =
 958                 intel_sanitize_enable_execlists(dev_priv,
 959                                                 i915.enable_execlists);
 960
 961         /*
 962          * i915.enable_ppgtt is read-only, so do an early pass to validate the
 963          * user's requested state against the hardware/driver capabilities.  We
 964          * do this now so that we can print out any log messages once rather
 965          * than every time we check intel_enable_ppgtt().
 966          */
 967         i915.enable_ppgtt =
 968                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
 969         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 970
 971         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
 972         DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
 973 }
 974
 975 /**
 976  * i915_driver_init_hw - setup state requiring device access
 977  * @dev_priv: device private
 978  *
 979  * Setup state that requires accessing the device, but doesn't require
 980  * exposing the driver via kernel internal or userspace interfaces.
 981  */
 982 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 983 {
 984         struct pci_dev *pdev = dev_priv->drm.pdev;
 985         int ret;
 986
 987         if (i915_inject_load_failure())
 988                 return -ENODEV;
 989
 990         intel_device_info_runtime_init(dev_priv);
 991
 992         intel_sanitize_options(dev_priv);
 993
 994         ret = i915_ggtt_probe_hw(dev_priv);
 995         if (ret)
 996                 return ret;
 997
 998         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
 999          * otherwise the vga fbdev driver falls over. */
1000         ret = i915_kick_out_firmware_fb(dev_priv);
1001         if (ret) {
1002                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1003                 goto out_ggtt;
1004         }
1005
1006         ret = i915_kick_out_vgacon(dev_priv);
1007         if (ret) {
1008                 DRM_ERROR("failed to remove conflicting VGA console\n");
1009                 goto out_ggtt;
1010         }
1011
1012         ret = i915_ggtt_init_hw(dev_priv);
1013         if (ret)
1014                 return ret;
1015
1016         ret = i915_ggtt_enable_hw(dev_priv);
1017         if (ret) {
1018                 DRM_ERROR("failed to enable GGTT\n");
1019                 goto out_ggtt;
1020         }
1021
1022         pci_set_master(pdev);
1023
1024         /* overlay on gen2 is broken and can't address above 1G */
1025         if (IS_GEN2(dev_priv)) {
1026                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1027                 if (ret) {
1028                         DRM_ERROR("failed to set DMA mask\n");
1029
1030                         goto out_ggtt;
1031                 }
1032         }
1033
1034         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1035          * using 32bit addressing, overwriting memory if HWS is located
1036          * above 4GB.
1037          *
1038          * The documentation also mentions an issue with undefined
1039          * behaviour if any general state is accessed within a page above 4GB,
1040          * which also needs to be handled carefully.
1041          */
1042         if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv)) {
1043                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1044
1045                 if (ret) {
1046                         DRM_ERROR("failed to set DMA mask\n");
1047
1048                         goto out_ggtt;
1049                 }
1050         }
1051
1052         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1053                            PM_QOS_DEFAULT_VALUE);
1054
1055         intel_uncore_sanitize(dev_priv);
1056
1057         intel_opregion_setup(dev_priv);
1058
1059         i915_gem_load_init_fences(dev_priv);
1060
1061         /* On the 945G/GM, the chipset reports the MSI capability on the
1062          * integrated graphics even though the support isn't actually there
1063          * according to the published specs.  It doesn't appear to function
1064          * correctly in testing on 945G.
1065          * This may be a side effect of MSI having been made available for PEG
1066          * and the registers being closely associated.
1067          *
1068          * According to chipset errata, on the 965GM, MSI interrupts may
1069          * be lost or delayed, but we use them anyways to avoid
1070          * stuck interrupts on some machines.
1071          */
1072         if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
1073                 if (pci_enable_msi(pdev) < 0)
1074                         DRM_DEBUG_DRIVER("can't enable MSI");
1075         }
1076
1077         return 0;
1078
1079 out_ggtt:
1080         i915_ggtt_cleanup_hw(dev_priv);
1081
1082         return ret;
1083 }
1084
1085 /**
1086  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1087  * @dev_priv: device private
1088  */
1089 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1090 {
1091         struct pci_dev *pdev = dev_priv->drm.pdev;
1092
1093         if (pdev->msi_enabled)
1094                 pci_disable_msi(pdev);
1095
1096         pm_qos_remove_request(&dev_priv->pm_qos);
1097         i915_ggtt_cleanup_hw(dev_priv);
1098 }
1099
1100 /**
1101  * i915_driver_register - register the driver with the rest of the system
1102  * @dev_priv: device private
1103  *
1104  * Perform any steps necessary to make the driver available via kernel
1105  * internal or userspace interfaces.
1106  */
1107 static void i915_driver_register(struct drm_i915_private *dev_priv)
1108 {
1109         struct drm_device *dev = &dev_priv->drm;
1110
1111         i915_gem_shrinker_init(dev_priv);
1112
1113         /*
1114          * Notify a valid surface after modesetting,
1115          * when running inside a VM.
1116          */
1117         if (intel_vgpu_active(dev_priv))
1118                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1119
1120         /* Reveal our presence to userspace */
1121         if (drm_dev_register(dev, 0) == 0) {
1122                 i915_debugfs_register(dev_priv);
1123                 i915_guc_register(dev_priv);
1124                 i915_setup_sysfs(dev_priv);
1125         } else
1126                 DRM_ERROR("Failed to register driver for userspace access!\n");
1127
1128         if (INTEL_INFO(dev_priv)->num_pipes) {
1129                 /* Must be done after probing outputs */
1130                 intel_opregion_register(dev_priv);
1131                 acpi_video_register();
1132         }
1133
1134         if (IS_GEN5(dev_priv))
1135                 intel_gpu_ips_init(dev_priv);
1136
1137         i915_audio_component_init(dev_priv);
1138
1139         /*
1140          * Some ports require correctly set-up hpd registers for detection to
1141          * work properly (leading to ghost connected connector status), e.g. VGA
1142          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1143          * irqs are fully enabled. We do it last so that the async config
1144          * cannot run before the connectors are registered.
1145          */
1146         intel_fbdev_initial_config_async(dev);
1147 }
1148
1149 /**
1150  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1151  * @dev_priv: device private
1152  */
1153 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1154 {
1155         i915_audio_component_cleanup(dev_priv);
1156
1157         intel_gpu_ips_teardown();
1158         acpi_video_unregister();
1159         intel_opregion_unregister(dev_priv);
1160
1161         i915_teardown_sysfs(dev_priv);
1162         i915_guc_unregister(dev_priv);
1163         i915_debugfs_unregister(dev_priv);
1164         drm_dev_unregister(&dev_priv->drm);
1165
1166         i915_gem_shrinker_cleanup(dev_priv);
1167 }
1168
1169 /**
1170  * i915_driver_load - setup chip and create an initial config
1171  * @dev: DRM device
1172  * @flags: startup flags
1173  *
1174  * The driver load routine has to do several things:
1175  *   - drive output discovery via intel_modeset_init()
1176  *   - initialize the memory manager
1177  *   - allocate initial config memory
1178  *   - setup the DRM framebuffer with the allocated memory
1179  */
1180 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1181 {
1182         struct drm_i915_private *dev_priv;
1183         int ret;
1184
1185         if (i915.nuclear_pageflip)
1186                 driver.driver_features |= DRIVER_ATOMIC;
1187
1188         ret = -ENOMEM;
1189         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1190         if (dev_priv)
1191                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1192         if (ret) {
1193                 dev_printk(KERN_ERR, &pdev->dev,
1194                            "[" DRM_NAME ":%s] allocation failed\n", __func__);
1195                 kfree(dev_priv);
1196                 return ret;
1197         }
1198
1199         dev_priv->drm.pdev = pdev;
1200         dev_priv->drm.dev_private = dev_priv;
1201
1202         ret = pci_enable_device(pdev);
1203         if (ret)
1204                 goto out_free_priv;
1205
1206         pci_set_drvdata(pdev, &dev_priv->drm);
1207
1208         ret = i915_driver_init_early(dev_priv, ent);
1209         if (ret < 0)
1210                 goto out_pci_disable;
1211
1212         intel_runtime_pm_get(dev_priv);
1213
1214         ret = i915_driver_init_mmio(dev_priv);
1215         if (ret < 0)
1216                 goto out_runtime_pm_put;
1217
1218         ret = i915_driver_init_hw(dev_priv);
1219         if (ret < 0)
1220                 goto out_cleanup_mmio;
1221
1222         /*
1223          * TODO: move the vblank init and parts of modeset init steps into one
1224          * of the i915_driver_init_/i915_driver_register functions according
1225          * to the role/effect of the given init step.
1226          */
1227         if (INTEL_INFO(dev_priv)->num_pipes) {
1228                 ret = drm_vblank_init(&dev_priv->drm,
1229                                       INTEL_INFO(dev_priv)->num_pipes);
1230                 if (ret)
1231                         goto out_cleanup_hw;
1232         }
1233
1234         ret = i915_load_modeset_init(&dev_priv->drm);
1235         if (ret < 0)
1236                 goto out_cleanup_vblank;
1237
1238         i915_driver_register(dev_priv);
1239
1240         intel_runtime_pm_enable(dev_priv);
1241
1242         /* Everything is in place, we can now relax! */
1243         DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1244                  driver.name, driver.major, driver.minor, driver.patchlevel,
1245                  driver.date, pci_name(pdev), dev_priv->drm.primary->index);
1246         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1247                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1248         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1249                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1250
1251         intel_runtime_pm_put(dev_priv);
1252
1253         return 0;
1254
1255 out_cleanup_vblank:
1256         drm_vblank_cleanup(&dev_priv->drm);
1257 out_cleanup_hw:
1258         i915_driver_cleanup_hw(dev_priv);
1259 out_cleanup_mmio:
1260         i915_driver_cleanup_mmio(dev_priv);
1261 out_runtime_pm_put:
1262         intel_runtime_pm_put(dev_priv);
1263         i915_driver_cleanup_early(dev_priv);
1264 out_pci_disable:
1265         pci_disable_device(pdev);
1266 out_free_priv:
1267         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1268         drm_dev_unref(&dev_priv->drm);
1269         return ret;
1270 }
1271
1272 void i915_driver_unload(struct drm_device *dev)
1273 {
1274         struct drm_i915_private *dev_priv = to_i915(dev);
1275         struct pci_dev *pdev = dev_priv->drm.pdev;
1276
1277         intel_fbdev_fini(dev);
1278
1279         if (i915_gem_suspend(dev))
1280                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1281
1282         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1283
1284         i915_driver_unregister(dev_priv);
1285
1286         drm_vblank_cleanup(dev);
1287
1288         intel_modeset_cleanup(dev);
1289
1290         /*
1291          * free the memory space allocated for the child device
1292          * config parsed from VBT
1293          */
1294         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1295                 kfree(dev_priv->vbt.child_dev);
1296                 dev_priv->vbt.child_dev = NULL;
1297                 dev_priv->vbt.child_dev_num = 0;
1298         }
1299         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1300         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1301         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1302         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1303
1304         vga_switcheroo_unregister_client(pdev);
1305         vga_client_register(pdev, NULL, NULL, NULL);
1306
1307         intel_csr_ucode_fini(dev_priv);
1308
1309         /* Free error state after interrupts are fully disabled. */
1310         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1311         i915_destroy_error_state(dev);
1312
1313         /* Flush any outstanding unpin_work. */
1314         drain_workqueue(dev_priv->wq);
1315
1316         intel_guc_fini(dev);
1317         i915_gem_fini(dev_priv);
1318         intel_fbc_cleanup_cfb(dev_priv);
1319
1320         intel_power_domains_fini(dev_priv);
1321
1322         i915_driver_cleanup_hw(dev_priv);
1323         i915_driver_cleanup_mmio(dev_priv);
1324
1325         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1326
1327         i915_driver_cleanup_early(dev_priv);
1328 }
1329
1330 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1331 {
1332         int ret;
1333
1334         ret = i915_gem_open(dev, file);
1335         if (ret)
1336                 return ret;
1337
1338         return 0;
1339 }
1340
1341 /**
1342  * i915_driver_lastclose - clean up after all DRM clients have exited
1343  * @dev: DRM device
1344  *
1345  * Take care of cleaning up after all DRM clients have exited.  In the
1346  * mode setting case, we want to restore the kernel's initial mode (just
1347  * in case the last client left us in a bad state).
1348  *
1349  * Additionally, in the non-mode setting case, we'll tear down the GTT
1350  * and DMA structures, since the kernel won't be using them, and clea
1351  * up any GEM state.
1352  */
1353 static void i915_driver_lastclose(struct drm_device *dev)
1354 {
1355         intel_fbdev_restore_mode(dev);
1356         vga_switcheroo_process_delayed_switch();
1357 }
1358
1359 static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1360 {
1361         mutex_lock(&dev->struct_mutex);
1362         i915_gem_context_close(dev, file);
1363         i915_gem_release(dev, file);
1364         mutex_unlock(&dev->struct_mutex);
1365 }
1366
1367 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1368 {
1369         struct drm_i915_file_private *file_priv = file->driver_priv;
1370
1371         kfree(file_priv);
1372 }
1373
1374 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1375 {
1376         struct drm_device *dev = &dev_priv->drm;
1377         struct intel_encoder *encoder;
1378
1379         drm_modeset_lock_all(dev);
1380         for_each_intel_encoder(dev, encoder)
1381                 if (encoder->suspend)
1382                         encoder->suspend(encoder);
1383         drm_modeset_unlock_all(dev);
1384 }
1385
1386 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1387                               bool rpm_resume);
1388 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1389
1390 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1391 {
1392 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1393         if (acpi_target_system_state() < ACPI_STATE_S3)
1394                 return true;
1395 #endif
1396         return false;
1397 }
1398
1399 static int i915_drm_suspend(struct drm_device *dev)
1400 {
1401         struct drm_i915_private *dev_priv = to_i915(dev);
1402         struct pci_dev *pdev = dev_priv->drm.pdev;
1403         pci_power_t opregion_target_state;
1404         int error;
1405
1406         /* ignore lid events during suspend */
1407         mutex_lock(&dev_priv->modeset_restore_lock);
1408         dev_priv->modeset_restore = MODESET_SUSPENDED;
1409         mutex_unlock(&dev_priv->modeset_restore_lock);
1410
1411         disable_rpm_wakeref_asserts(dev_priv);
1412
1413         /* We do a lot of poking in a lot of registers, make sure they work
1414          * properly. */
1415         intel_display_set_init_power(dev_priv, true);
1416
1417         drm_kms_helper_poll_disable(dev);
1418
1419         pci_save_state(pdev);
1420
1421         error = i915_gem_suspend(dev);
1422         if (error) {
1423                 dev_err(&pdev->dev,
1424                         "GEM idle failed, resume might fail\n");
1425                 goto out;
1426         }
1427
1428         intel_guc_suspend(dev);
1429
1430         intel_display_suspend(dev);
1431
1432         intel_dp_mst_suspend(dev);
1433
1434         intel_runtime_pm_disable_interrupts(dev_priv);
1435         intel_hpd_cancel_work(dev_priv);
1436
1437         intel_suspend_encoders(dev_priv);
1438
1439         intel_suspend_hw(dev_priv);
1440
1441         i915_gem_suspend_gtt_mappings(dev);
1442
1443         i915_save_state(dev);
1444
1445         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1446         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1447
1448         intel_uncore_forcewake_reset(dev_priv, false);
1449         intel_opregion_unregister(dev_priv);
1450
1451         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1452
1453         dev_priv->suspend_count++;
1454
1455         intel_csr_ucode_suspend(dev_priv);
1456
1457 out:
1458         enable_rpm_wakeref_asserts(dev_priv);
1459
1460         return error;
1461 }
1462
1463 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1464 {
1465         struct drm_i915_private *dev_priv = to_i915(dev);
1466         struct pci_dev *pdev = dev_priv->drm.pdev;
1467         bool fw_csr;
1468         int ret;
1469
1470         disable_rpm_wakeref_asserts(dev_priv);
1471
1472         intel_display_set_init_power(dev_priv, false);
1473
1474         fw_csr = !IS_BROXTON(dev_priv) &&
1475                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1476         /*
1477          * In case of firmware assisted context save/restore don't manually
1478          * deinit the power domains. This also means the CSR/DMC firmware will
1479          * stay active, it will power down any HW resources as required and
1480          * also enable deeper system power states that would be blocked if the
1481          * firmware was inactive.
1482          */
1483         if (!fw_csr)
1484                 intel_power_domains_suspend(dev_priv);
1485
1486         ret = 0;
1487         if (IS_BROXTON(dev_priv))
1488                 bxt_enable_dc9(dev_priv);
1489         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1490                 hsw_enable_pc8(dev_priv);
1491         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1492                 ret = vlv_suspend_complete(dev_priv);
1493
1494         if (ret) {
1495                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1496                 if (!fw_csr)
1497                         intel_power_domains_init_hw(dev_priv, true);
1498
1499                 goto out;
1500         }
1501
1502         pci_disable_device(pdev);
1503         /*
1504          * During hibernation on some platforms the BIOS may try to access
1505          * the device even though it's already in D3 and hang the machine. So
1506          * leave the device in D0 on those platforms and hope the BIOS will
1507          * power down the device properly. The issue was seen on multiple old
1508          * GENs with different BIOS vendors, so having an explicit blacklist
1509          * is inpractical; apply the workaround on everything pre GEN6. The
1510          * platforms where the issue was seen:
1511          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1512          * Fujitsu FSC S7110
1513          * Acer Aspire 1830T
1514          */
1515         if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
1516                 pci_set_power_state(pdev, PCI_D3hot);
1517
1518         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1519
1520 out:
1521         enable_rpm_wakeref_asserts(dev_priv);
1522
1523         return ret;
1524 }
1525
1526 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1527 {
1528         int error;
1529
1530         if (!dev) {
1531                 DRM_ERROR("dev: %p\n", dev);
1532                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1533                 return -ENODEV;
1534         }
1535
1536         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1537                          state.event != PM_EVENT_FREEZE))
1538                 return -EINVAL;
1539
1540         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1541                 return 0;
1542
1543         error = i915_drm_suspend(dev);
1544         if (error)
1545                 return error;
1546
1547         return i915_drm_suspend_late(dev, false);
1548 }
1549
1550 static int i915_drm_resume(struct drm_device *dev)
1551 {
1552         struct drm_i915_private *dev_priv = to_i915(dev);
1553         int ret;
1554
1555         disable_rpm_wakeref_asserts(dev_priv);
1556         intel_sanitize_gt_powersave(dev_priv);
1557
1558         ret = i915_ggtt_enable_hw(dev_priv);
1559         if (ret)
1560                 DRM_ERROR("failed to re-enable GGTT\n");
1561
1562         intel_csr_ucode_resume(dev_priv);
1563
1564         i915_gem_resume(dev);
1565
1566         i915_restore_state(dev);
1567         intel_pps_unlock_regs_wa(dev_priv);
1568         intel_opregion_setup(dev_priv);
1569
1570         intel_init_pch_refclk(dev);
1571         drm_mode_config_reset(dev);
1572
1573         /*
1574          * Interrupts have to be enabled before any batches are run. If not the
1575          * GPU will hang. i915_gem_init_hw() will initiate batches to
1576          * update/restore the context.
1577          *
1578          * Modeset enabling in intel_modeset_init_hw() also needs working
1579          * interrupts.
1580          */
1581         intel_runtime_pm_enable_interrupts(dev_priv);
1582
1583         mutex_lock(&dev->struct_mutex);
1584         if (i915_gem_init_hw(dev)) {
1585                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1586                 i915_gem_set_wedged(dev_priv);
1587         }
1588         mutex_unlock(&dev->struct_mutex);
1589
1590         intel_guc_resume(dev);
1591
1592         intel_modeset_init_hw(dev);
1593
1594         spin_lock_irq(&dev_priv->irq_lock);
1595         if (dev_priv->display.hpd_irq_setup)
1596                 dev_priv->display.hpd_irq_setup(dev_priv);
1597         spin_unlock_irq(&dev_priv->irq_lock);
1598
1599         intel_dp_mst_resume(dev);
1600
1601         intel_display_resume(dev);
1602
1603         drm_kms_helper_poll_enable(dev);
1604
1605         /*
1606          * ... but also need to make sure that hotplug processing
1607          * doesn't cause havoc. Like in the driver load code we don't
1608          * bother with the tiny race here where we might loose hotplug
1609          * notifications.
1610          * */
1611         intel_hpd_init(dev_priv);
1612
1613         intel_opregion_register(dev_priv);
1614
1615         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1616
1617         mutex_lock(&dev_priv->modeset_restore_lock);
1618         dev_priv->modeset_restore = MODESET_DONE;
1619         mutex_unlock(&dev_priv->modeset_restore_lock);
1620
1621         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1622
1623         intel_autoenable_gt_powersave(dev_priv);
1624
1625         enable_rpm_wakeref_asserts(dev_priv);
1626
1627         return 0;
1628 }
1629
1630 static int i915_drm_resume_early(struct drm_device *dev)
1631 {
1632         struct drm_i915_private *dev_priv = to_i915(dev);
1633         struct pci_dev *pdev = dev_priv->drm.pdev;
1634         int ret;
1635
1636         /*
1637          * We have a resume ordering issue with the snd-hda driver also
1638          * requiring our device to be power up. Due to the lack of a
1639          * parent/child relationship we currently solve this with an early
1640          * resume hook.
1641          *
1642          * FIXME: This should be solved with a special hdmi sink device or
1643          * similar so that power domains can be employed.
1644          */
1645
1646         /*
1647          * Note that we need to set the power state explicitly, since we
1648          * powered off the device during freeze and the PCI core won't power
1649          * it back up for us during thaw. Powering off the device during
1650          * freeze is not a hard requirement though, and during the
1651          * suspend/resume phases the PCI core makes sure we get here with the
1652          * device powered on. So in case we change our freeze logic and keep
1653          * the device powered we can also remove the following set power state
1654          * call.
1655          */
1656         ret = pci_set_power_state(pdev, PCI_D0);
1657         if (ret) {
1658                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1659                 goto out;
1660         }
1661
1662         /*
1663          * Note that pci_enable_device() first enables any parent bridge
1664          * device and only then sets the power state for this device. The
1665          * bridge enabling is a nop though, since bridge devices are resumed
1666          * first. The order of enabling power and enabling the device is
1667          * imposed by the PCI core as described above, so here we preserve the
1668          * same order for the freeze/thaw phases.
1669          *
1670          * TODO: eventually we should remove pci_disable_device() /
1671          * pci_enable_enable_device() from suspend/resume. Due to how they
1672          * depend on the device enable refcount we can't anyway depend on them
1673          * disabling/enabling the device.
1674          */
1675         if (pci_enable_device(pdev)) {
1676                 ret = -EIO;
1677                 goto out;
1678         }
1679
1680         pci_set_master(pdev);
1681
1682         disable_rpm_wakeref_asserts(dev_priv);
1683
1684         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1685                 ret = vlv_resume_prepare(dev_priv, false);
1686         if (ret)
1687                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1688                           ret);
1689
1690         intel_uncore_early_sanitize(dev_priv, true);
1691
1692         if (IS_BROXTON(dev_priv)) {
1693                 if (!dev_priv->suspended_to_idle)
1694                         gen9_sanitize_dc_state(dev_priv);
1695                 bxt_disable_dc9(dev_priv);
1696         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1697                 hsw_disable_pc8(dev_priv);
1698         }
1699
1700         intel_uncore_sanitize(dev_priv);
1701
1702         if (IS_BROXTON(dev_priv) ||
1703             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1704                 intel_power_domains_init_hw(dev_priv, true);
1705
1706         enable_rpm_wakeref_asserts(dev_priv);
1707
1708 out:
1709         dev_priv->suspended_to_idle = false;
1710
1711         return ret;
1712 }
1713
1714 int i915_resume_switcheroo(struct drm_device *dev)
1715 {
1716         int ret;
1717
1718         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1719                 return 0;
1720
1721         ret = i915_drm_resume_early(dev);
1722         if (ret)
1723                 return ret;
1724
1725         return i915_drm_resume(dev);
1726 }
1727
1728 static void disable_engines_irq(struct drm_i915_private *dev_priv)
1729 {
1730         struct intel_engine_cs *engine;
1731         enum intel_engine_id id;
1732
1733         /* Ensure irq handler finishes, and not run again. */
1734         disable_irq(dev_priv->drm.irq);
1735         for_each_engine(engine, dev_priv, id)
1736                 tasklet_kill(&engine->irq_tasklet);
1737 }
1738
1739 static void enable_engines_irq(struct drm_i915_private *dev_priv)
1740 {
1741         enable_irq(dev_priv->drm.irq);
1742 }
1743
1744 /**
1745  * i915_reset - reset chip after a hang
1746  * @dev: drm device to reset
1747  *
1748  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1749  * on failure.
1750  *
1751  * Caller must hold the struct_mutex.
1752  *
1753  * Procedure is fairly simple:
1754  *   - reset the chip using the reset reg
1755  *   - re-init context state
1756  *   - re-init hardware status page
1757  *   - re-init ring buffer
1758  *   - re-init interrupt state
1759  *   - re-init display
1760  */
1761 void i915_reset(struct drm_i915_private *dev_priv)
1762 {
1763         struct drm_device *dev = &dev_priv->drm;
1764         struct i915_gpu_error *error = &dev_priv->gpu_error;
1765         int ret;
1766
1767         lockdep_assert_held(&dev->struct_mutex);
1768
1769         if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags))
1770                 return;
1771
1772         /* Clear any previous failed attempts at recovery. Time to try again. */
1773         __clear_bit(I915_WEDGED, &error->flags);
1774         error->reset_count++;
1775
1776         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1777
1778         disable_engines_irq(dev_priv);
1779         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1780         enable_engines_irq(dev_priv);
1781
1782         if (ret) {
1783                 if (ret != -ENODEV)
1784                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1785                 else
1786                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1787                 goto error;
1788         }
1789
1790         i915_gem_reset(dev_priv);
1791         intel_overlay_reset(dev_priv);
1792
1793         /* Ok, now get things going again... */
1794
1795         /*
1796          * Everything depends on having the GTT running, so we need to start
1797          * there.  Fortunately we don't need to do this unless we reset the
1798          * chip at a PCI level.
1799          *
1800          * Next we need to restore the context, but we don't use those
1801          * yet either...
1802          *
1803          * Ring buffer needs to be re-initialized in the KMS case, or if X
1804          * was running at the time of the reset (i.e. we weren't VT
1805          * switched away).
1806          */
1807         ret = i915_gem_init_hw(dev);
1808         if (ret) {
1809                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1810                 goto error;
1811         }
1812
1813 wakeup:
1814         wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
1815         return;
1816
1817 error:
1818         i915_gem_set_wedged(dev_priv);
1819         goto wakeup;
1820 }
1821
1822 static int i915_pm_suspend(struct device *kdev)
1823 {
1824         struct pci_dev *pdev = to_pci_dev(kdev);
1825         struct drm_device *dev = pci_get_drvdata(pdev);
1826
1827         if (!dev) {
1828                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1829                 return -ENODEV;
1830         }
1831
1832         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1833                 return 0;
1834
1835         return i915_drm_suspend(dev);
1836 }
1837
1838 static int i915_pm_suspend_late(struct device *kdev)
1839 {
1840         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1841
1842         /*
1843          * We have a suspend ordering issue with the snd-hda driver also
1844          * requiring our device to be power up. Due to the lack of a
1845          * parent/child relationship we currently solve this with an late
1846          * suspend hook.
1847          *
1848          * FIXME: This should be solved with a special hdmi sink device or
1849          * similar so that power domains can be employed.
1850          */
1851         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1852                 return 0;
1853
1854         return i915_drm_suspend_late(dev, false);
1855 }
1856
1857 static int i915_pm_poweroff_late(struct device *kdev)
1858 {
1859         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1860
1861         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1862                 return 0;
1863
1864         return i915_drm_suspend_late(dev, true);
1865 }
1866
1867 static int i915_pm_resume_early(struct device *kdev)
1868 {
1869         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1870
1871         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1872                 return 0;
1873
1874         return i915_drm_resume_early(dev);
1875 }
1876
1877 static int i915_pm_resume(struct device *kdev)
1878 {
1879         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1880
1881         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1882                 return 0;
1883
1884         return i915_drm_resume(dev);
1885 }
1886
1887 /* freeze: before creating the hibernation_image */
1888 static int i915_pm_freeze(struct device *kdev)
1889 {
1890         int ret;
1891
1892         ret = i915_pm_suspend(kdev);
1893         if (ret)
1894                 return ret;
1895
1896         ret = i915_gem_freeze(kdev_to_i915(kdev));
1897         if (ret)
1898                 return ret;
1899
1900         return 0;
1901 }
1902
1903 static int i915_pm_freeze_late(struct device *kdev)
1904 {
1905         int ret;
1906
1907         ret = i915_pm_suspend_late(kdev);
1908         if (ret)
1909                 return ret;
1910
1911         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
1912         if (ret)
1913                 return ret;
1914
1915         return 0;
1916 }
1917
1918 /* thaw: called after creating the hibernation image, but before turning off. */
1919 static int i915_pm_thaw_early(struct device *kdev)
1920 {
1921         return i915_pm_resume_early(kdev);
1922 }
1923
1924 static int i915_pm_thaw(struct device *kdev)
1925 {
1926         return i915_pm_resume(kdev);
1927 }
1928
1929 /* restore: called after loading the hibernation image. */
1930 static int i915_pm_restore_early(struct device *kdev)
1931 {
1932         return i915_pm_resume_early(kdev);
1933 }
1934
1935 static int i915_pm_restore(struct device *kdev)
1936 {
1937         return i915_pm_resume(kdev);
1938 }
1939
1940 /*
1941  * Save all Gunit registers that may be lost after a D3 and a subsequent
1942  * S0i[R123] transition. The list of registers needing a save/restore is
1943  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1944  * registers in the following way:
1945  * - Driver: saved/restored by the driver
1946  * - Punit : saved/restored by the Punit firmware
1947  * - No, w/o marking: no need to save/restore, since the register is R/O or
1948  *                    used internally by the HW in a way that doesn't depend
1949  *                    keeping the content across a suspend/resume.
1950  * - Debug : used for debugging
1951  *
1952  * We save/restore all registers marked with 'Driver', with the following
1953  * exceptions:
1954  * - Registers out of use, including also registers marked with 'Debug'.
1955  *   These have no effect on the driver's operation, so we don't save/restore
1956  *   them to reduce the overhead.
1957  * - Registers that are fully setup by an initialization function called from
1958  *   the resume path. For example many clock gating and RPS/RC6 registers.
1959  * - Registers that provide the right functionality with their reset defaults.
1960  *
1961  * TODO: Except for registers that based on the above 3 criteria can be safely
1962  * ignored, we save/restore all others, practically treating the HW context as
1963  * a black-box for the driver. Further investigation is needed to reduce the
1964  * saved/restored registers even further, by following the same 3 criteria.
1965  */
1966 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1967 {
1968         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1969         int i;
1970
1971         /* GAM 0x4000-0x4770 */
1972         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1973         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1974         s->arb_mode             = I915_READ(ARB_MODE);
1975         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1976         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1977
1978         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1979                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1980
1981         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1982         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1983
1984         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1985         s->ecochk               = I915_READ(GAM_ECOCHK);
1986         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1987         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1988
1989         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1990
1991         /* MBC 0x9024-0x91D0, 0x8500 */
1992         s->g3dctl               = I915_READ(VLV_G3DCTL);
1993         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1994         s->mbctl                = I915_READ(GEN6_MBCTL);
1995
1996         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1997         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1998         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1999         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2000         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2001         s->rstctl               = I915_READ(GEN6_RSTCTL);
2002         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2003
2004         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2005         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2006         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2007         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2008         s->ecobus               = I915_READ(ECOBUS);
2009         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2010         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2011         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2012         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2013         s->rcedata              = I915_READ(VLV_RCEDATA);
2014         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2015
2016         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2017         s->gt_imr               = I915_READ(GTIMR);
2018         s->gt_ier               = I915_READ(GTIER);
2019         s->pm_imr               = I915_READ(GEN6_PMIMR);
2020         s->pm_ier               = I915_READ(GEN6_PMIER);
2021
2022         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2023                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2024
2025         /* GT SA CZ domain, 0x100000-0x138124 */
2026         s->tilectl              = I915_READ(TILECTL);
2027         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2028         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2029         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2030         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2031
2032         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2033         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2034         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2035         s->pcbr                 = I915_READ(VLV_PCBR);
2036         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2037
2038         /*
2039          * Not saving any of:
2040          * DFT,         0x9800-0x9EC0
2041          * SARB,        0xB000-0xB1FC
2042          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2043          * PCI CFG
2044          */
2045 }
2046
2047 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2048 {
2049         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2050         u32 val;
2051         int i;
2052
2053         /* GAM 0x4000-0x4770 */
2054         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2055         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2056         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2057         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2058         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2059
2060         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2061                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2062
2063         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2064         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2065
2066         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2067         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2068         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2069         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2070
2071         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2072
2073         /* MBC 0x9024-0x91D0, 0x8500 */
2074         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2075         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2076         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2077
2078         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2079         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2080         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2081         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2082         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2083         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2084         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2085
2086         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2087         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2088         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2089         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2090         I915_WRITE(ECOBUS,              s->ecobus);
2091         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2092         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2093         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2094         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2095         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2096         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2097
2098         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2099         I915_WRITE(GTIMR,               s->gt_imr);
2100         I915_WRITE(GTIER,               s->gt_ier);
2101         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2102         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2103
2104         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2105                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2106
2107         /* GT SA CZ domain, 0x100000-0x138124 */
2108         I915_WRITE(TILECTL,                     s->tilectl);
2109         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2110         /*
2111          * Preserve the GT allow wake and GFX force clock bit, they are not
2112          * be restored, as they are used to control the s0ix suspend/resume
2113          * sequence by the caller.
2114          */
2115         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2116         val &= VLV_GTLC_ALLOWWAKEREQ;
2117         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2118         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2119
2120         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2121         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2122         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2123         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2124
2125         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2126
2127         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2128         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2129         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2130         I915_WRITE(VLV_PCBR,                    s->pcbr);
2131         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2132 }
2133
2134 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2135 {
2136         u32 val;
2137         int err;
2138
2139         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2140         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2141         if (force_on)
2142                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2143         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2144
2145         if (!force_on)
2146                 return 0;
2147
2148         err = intel_wait_for_register(dev_priv,
2149                                       VLV_GTLC_SURVIVABILITY_REG,
2150                                       VLV_GFX_CLK_STATUS_BIT,
2151                                       VLV_GFX_CLK_STATUS_BIT,
2152                                       20);
2153         if (err)
2154                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2155                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2156
2157         return err;
2158 }
2159
2160 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2161 {
2162         u32 val;
2163         int err = 0;
2164
2165         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2166         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2167         if (allow)
2168                 val |= VLV_GTLC_ALLOWWAKEREQ;
2169         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2170         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2171
2172         err = intel_wait_for_register(dev_priv,
2173                                       VLV_GTLC_PW_STATUS,
2174                                       VLV_GTLC_ALLOWWAKEACK,
2175                                       allow,
2176                                       1);
2177         if (err)
2178                 DRM_ERROR("timeout disabling GT waking\n");
2179
2180         return err;
2181 }
2182
2183 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2184                                  bool wait_for_on)
2185 {
2186         u32 mask;
2187         u32 val;
2188         int err;
2189
2190         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2191         val = wait_for_on ? mask : 0;
2192         if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
2193                 return 0;
2194
2195         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2196                       onoff(wait_for_on),
2197                       I915_READ(VLV_GTLC_PW_STATUS));
2198
2199         /*
2200          * RC6 transitioning can be delayed up to 2 msec (see
2201          * valleyview_enable_rps), use 3 msec for safety.
2202          */
2203         err = intel_wait_for_register(dev_priv,
2204                                       VLV_GTLC_PW_STATUS, mask, val,
2205                                       3);
2206         if (err)
2207                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2208                           onoff(wait_for_on));
2209
2210         return err;
2211 }
2212
2213 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2214 {
2215         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2216                 return;
2217
2218         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2219         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2220 }
2221
2222 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2223 {
2224         u32 mask;
2225         int err;
2226
2227         /*
2228          * Bspec defines the following GT well on flags as debug only, so
2229          * don't treat them as hard failures.
2230          */
2231         (void)vlv_wait_for_gt_wells(dev_priv, false);
2232
2233         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2234         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2235
2236         vlv_check_no_gt_access(dev_priv);
2237
2238         err = vlv_force_gfx_clock(dev_priv, true);
2239         if (err)
2240                 goto err1;
2241
2242         err = vlv_allow_gt_wake(dev_priv, false);
2243         if (err)
2244                 goto err2;
2245
2246         if (!IS_CHERRYVIEW(dev_priv))
2247                 vlv_save_gunit_s0ix_state(dev_priv);
2248
2249         err = vlv_force_gfx_clock(dev_priv, false);
2250         if (err)
2251                 goto err2;
2252
2253         return 0;
2254
2255 err2:
2256         /* For safety always re-enable waking and disable gfx clock forcing */
2257         vlv_allow_gt_wake(dev_priv, true);
2258 err1:
2259         vlv_force_gfx_clock(dev_priv, false);
2260
2261         return err;
2262 }
2263
2264 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2265                                 bool rpm_resume)
2266 {
2267         int err;
2268         int ret;
2269
2270         /*
2271          * If any of the steps fail just try to continue, that's the best we
2272          * can do at this point. Return the first error code (which will also
2273          * leave RPM permanently disabled).
2274          */
2275         ret = vlv_force_gfx_clock(dev_priv, true);
2276
2277         if (!IS_CHERRYVIEW(dev_priv))
2278                 vlv_restore_gunit_s0ix_state(dev_priv);
2279
2280         err = vlv_allow_gt_wake(dev_priv, true);
2281         if (!ret)
2282                 ret = err;
2283
2284         err = vlv_force_gfx_clock(dev_priv, false);
2285         if (!ret)
2286                 ret = err;
2287
2288         vlv_check_no_gt_access(dev_priv);
2289
2290         if (rpm_resume)
2291                 intel_init_clock_gating(dev_priv);
2292
2293         return ret;
2294 }
2295
2296 static int intel_runtime_suspend(struct device *kdev)
2297 {
2298         struct pci_dev *pdev = to_pci_dev(kdev);
2299         struct drm_device *dev = pci_get_drvdata(pdev);
2300         struct drm_i915_private *dev_priv = to_i915(dev);
2301         int ret;
2302
2303         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2304                 return -ENODEV;
2305
2306         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2307                 return -ENODEV;
2308
2309         DRM_DEBUG_KMS("Suspending device\n");
2310
2311         disable_rpm_wakeref_asserts(dev_priv);
2312
2313         /*
2314          * We are safe here against re-faults, since the fault handler takes
2315          * an RPM reference.
2316          */
2317         i915_gem_runtime_suspend(dev_priv);
2318
2319         intel_guc_suspend(dev);
2320
2321         intel_runtime_pm_disable_interrupts(dev_priv);
2322
2323         ret = 0;
2324         if (IS_BROXTON(dev_priv)) {
2325                 bxt_display_core_uninit(dev_priv);
2326                 bxt_enable_dc9(dev_priv);
2327         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2328                 hsw_enable_pc8(dev_priv);
2329         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2330                 ret = vlv_suspend_complete(dev_priv);
2331         }
2332
2333         if (ret) {
2334                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2335                 intel_runtime_pm_enable_interrupts(dev_priv);
2336
2337                 enable_rpm_wakeref_asserts(dev_priv);
2338
2339                 return ret;
2340         }
2341
2342         intel_uncore_forcewake_reset(dev_priv, false);
2343
2344         enable_rpm_wakeref_asserts(dev_priv);
2345         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2346
2347         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2348                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2349
2350         dev_priv->pm.suspended = true;
2351
2352         /*
2353          * FIXME: We really should find a document that references the arguments
2354          * used below!
2355          */
2356         if (IS_BROADWELL(dev_priv)) {
2357                 /*
2358                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2359                  * being detected, and the call we do at intel_runtime_resume()
2360                  * won't be able to restore them. Since PCI_D3hot matches the
2361                  * actual specification and appears to be working, use it.
2362                  */
2363                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2364         } else {
2365                 /*
2366                  * current versions of firmware which depend on this opregion
2367                  * notification have repurposed the D1 definition to mean
2368                  * "runtime suspended" vs. what you would normally expect (D3)
2369                  * to distinguish it from notifications that might be sent via
2370                  * the suspend path.
2371                  */
2372                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2373         }
2374
2375         assert_forcewakes_inactive(dev_priv);
2376
2377         if (!IS_VALLEYVIEW(dev_priv) || !IS_CHERRYVIEW(dev_priv))
2378                 intel_hpd_poll_init(dev_priv);
2379
2380         DRM_DEBUG_KMS("Device suspended\n");
2381         return 0;
2382 }
2383
2384 static int intel_runtime_resume(struct device *kdev)
2385 {
2386         struct pci_dev *pdev = to_pci_dev(kdev);
2387         struct drm_device *dev = pci_get_drvdata(pdev);
2388         struct drm_i915_private *dev_priv = to_i915(dev);
2389         int ret = 0;
2390
2391         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2392                 return -ENODEV;
2393
2394         DRM_DEBUG_KMS("Resuming device\n");
2395
2396         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2397         disable_rpm_wakeref_asserts(dev_priv);
2398
2399         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2400         dev_priv->pm.suspended = false;
2401         if (intel_uncore_unclaimed_mmio(dev_priv))
2402                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2403
2404         intel_guc_resume(dev);
2405
2406         if (IS_GEN6(dev_priv))
2407                 intel_init_pch_refclk(dev);
2408
2409         if (IS_BROXTON(dev_priv)) {
2410                 bxt_disable_dc9(dev_priv);
2411                 bxt_display_core_init(dev_priv, true);
2412                 if (dev_priv->csr.dmc_payload &&
2413                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2414                         gen9_enable_dc5(dev_priv);
2415         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2416                 hsw_disable_pc8(dev_priv);
2417         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2418                 ret = vlv_resume_prepare(dev_priv, true);
2419         }
2420
2421         /*
2422          * No point of rolling back things in case of an error, as the best
2423          * we can do is to hope that things will still work (and disable RPM).
2424          */
2425         i915_gem_init_swizzling(dev);
2426
2427         intel_runtime_pm_enable_interrupts(dev_priv);
2428
2429         /*
2430          * On VLV/CHV display interrupts are part of the display
2431          * power well, so hpd is reinitialized from there. For
2432          * everyone else do it here.
2433          */
2434         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2435                 intel_hpd_init(dev_priv);
2436
2437         enable_rpm_wakeref_asserts(dev_priv);
2438
2439         if (ret)
2440                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2441         else
2442                 DRM_DEBUG_KMS("Device resumed\n");
2443
2444         return ret;
2445 }
2446
2447 const struct dev_pm_ops i915_pm_ops = {
2448         /*
2449          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2450          * PMSG_RESUME]
2451          */
2452         .suspend = i915_pm_suspend,
2453         .suspend_late = i915_pm_suspend_late,
2454         .resume_early = i915_pm_resume_early,
2455         .resume = i915_pm_resume,
2456
2457         /*
2458          * S4 event handlers
2459          * @freeze, @freeze_late    : called (1) before creating the
2460          *                            hibernation image [PMSG_FREEZE] and
2461          *                            (2) after rebooting, before restoring
2462          *                            the image [PMSG_QUIESCE]
2463          * @thaw, @thaw_early       : called (1) after creating the hibernation
2464          *                            image, before writing it [PMSG_THAW]
2465          *                            and (2) after failing to create or
2466          *                            restore the image [PMSG_RECOVER]
2467          * @poweroff, @poweroff_late: called after writing the hibernation
2468          *                            image, before rebooting [PMSG_HIBERNATE]
2469          * @restore, @restore_early : called after rebooting and restoring the
2470          *                            hibernation image [PMSG_RESTORE]
2471          */
2472         .freeze = i915_pm_freeze,
2473         .freeze_late = i915_pm_freeze_late,
2474         .thaw_early = i915_pm_thaw_early,
2475         .thaw = i915_pm_thaw,
2476         .poweroff = i915_pm_suspend,
2477         .poweroff_late = i915_pm_poweroff_late,
2478         .restore_early = i915_pm_restore_early,
2479         .restore = i915_pm_restore,
2480
2481         /* S0ix (via runtime suspend) event handlers */
2482         .runtime_suspend = intel_runtime_suspend,
2483         .runtime_resume = intel_runtime_resume,
2484 };
2485
2486 static const struct vm_operations_struct i915_gem_vm_ops = {
2487         .fault = i915_gem_fault,
2488         .open = drm_gem_vm_open,
2489         .close = drm_gem_vm_close,
2490 };
2491
2492 static const struct file_operations i915_driver_fops = {
2493         .owner = THIS_MODULE,
2494         .open = drm_open,
2495         .release = drm_release,
2496         .unlocked_ioctl = drm_ioctl,
2497         .mmap = drm_gem_mmap,
2498         .poll = drm_poll,
2499         .read = drm_read,
2500 #ifdef CONFIG_COMPAT
2501         .compat_ioctl = i915_compat_ioctl,
2502 #endif
2503         .llseek = noop_llseek,
2504 };
2505
2506 static int
2507 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2508                           struct drm_file *file)
2509 {
2510         return -ENODEV;
2511 }
2512
2513 static const struct drm_ioctl_desc i915_ioctls[] = {
2514         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2515         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2516         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2517         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2518         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2519         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2520         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2521         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2522         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2523         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2524         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2525         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2526         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2527         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2528         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2529         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2530         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2531         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2532         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2533         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2534         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2535         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2536         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2537         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2538         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2539         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2540         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2541         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2542         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2543         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2544         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2545         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2546         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2547         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2548         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2549         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2550         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2551         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2552         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2553         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2554         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2555         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2556         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2557         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2558         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2559         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2560         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2561         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2562         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2563         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2564         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2565         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2566 };
2567
2568 static struct drm_driver driver = {
2569         /* Don't use MTRRs here; the Xserver or userspace app should
2570          * deal with them for Intel hardware.
2571          */
2572         .driver_features =
2573             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2574             DRIVER_RENDER | DRIVER_MODESET,
2575         .open = i915_driver_open,
2576         .lastclose = i915_driver_lastclose,
2577         .preclose = i915_driver_preclose,
2578         .postclose = i915_driver_postclose,
2579         .set_busid = drm_pci_set_busid,
2580
2581         .gem_close_object = i915_gem_close_object,
2582         .gem_free_object_unlocked = i915_gem_free_object,
2583         .gem_vm_ops = &i915_gem_vm_ops,
2584
2585         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2586         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2587         .gem_prime_export = i915_gem_prime_export,
2588         .gem_prime_import = i915_gem_prime_import,
2589
2590         .dumb_create = i915_gem_dumb_create,
2591         .dumb_map_offset = i915_gem_mmap_gtt,
2592         .dumb_destroy = drm_gem_dumb_destroy,
2593         .ioctls = i915_ioctls,
2594         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2595         .fops = &i915_driver_fops,
2596         .name = DRIVER_NAME,
2597         .desc = DRIVER_DESC,
2598         .date = DRIVER_DATE,
2599         .major = DRIVER_MAJOR,
2600         .minor = DRIVER_MINOR,
2601         .patchlevel = DRIVER_PATCHLEVEL,
2602 };