drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 1;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  54                 "-1=force lid closed, -2=force lid open)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0400);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 int i915_enable_psr __read_mostly = 0;
 122 module_param_named(enable_psr, i915_enable_psr, int, 0600);
 123 MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
 124
 125 unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT);
 126 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 127 MODULE_PARM_DESC(preliminary_hw_support,
 128                 "Enable preliminary hardware support.");
 129
 130 int i915_disable_power_well __read_mostly = 1;
 131 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
 132 MODULE_PARM_DESC(disable_power_well,
 133                  "Disable the power well when possible (default: true)");
 134
 135 int i915_enable_ips __read_mostly = 1;
 136 module_param_named(enable_ips, i915_enable_ips, int, 0600);
 137 MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
 138
 139 bool i915_fastboot __read_mostly = 0;
 140 module_param_named(fastboot, i915_fastboot, bool, 0600);
 141 MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
 142                  "(default: false)");
 143
 144 int i915_enable_pc8 __read_mostly = 1;
 145 module_param_named(enable_pc8, i915_enable_pc8, int, 0600);
 146 MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)");
 147
 148 int i915_pc8_timeout __read_mostly = 5000;
 149 module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600);
 150 MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)");
 151
 152 bool i915_prefault_disable __read_mostly;
 153 module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
 154 MODULE_PARM_DESC(prefault_disable,
 155                 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
 156
 157 static struct drm_driver driver;
 158
 159 static const struct intel_device_info intel_i830_info = {
 160         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 161         .has_overlay = 1, .overlay_needs_physical = 1,
 162         .ring_mask = RENDER_RING,
 163 };
 164
 165 static const struct intel_device_info intel_845g_info = {
 166         .gen = 2, .num_pipes = 1,
 167         .has_overlay = 1, .overlay_needs_physical = 1,
 168         .ring_mask = RENDER_RING,
 169 };
 170
 171 static const struct intel_device_info intel_i85x_info = {
 172         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
 173         .cursor_needs_physical = 1,
 174         .has_overlay = 1, .overlay_needs_physical = 1,
 175         .has_fbc = 1,
 176         .ring_mask = RENDER_RING,
 177 };
 178
 179 static const struct intel_device_info intel_i865g_info = {
 180         .gen = 2, .num_pipes = 1,
 181         .has_overlay = 1, .overlay_needs_physical = 1,
 182         .ring_mask = RENDER_RING,
 183 };
 184
 185 static const struct intel_device_info intel_i915g_info = {
 186         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 187         .has_overlay = 1, .overlay_needs_physical = 1,
 188         .ring_mask = RENDER_RING,
 189 };
 190 static const struct intel_device_info intel_i915gm_info = {
 191         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 192         .cursor_needs_physical = 1,
 193         .has_overlay = 1, .overlay_needs_physical = 1,
 194         .supports_tv = 1,
 195         .has_fbc = 1,
 196         .ring_mask = RENDER_RING,
 197 };
 198 static const struct intel_device_info intel_i945g_info = {
 199         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 200         .has_overlay = 1, .overlay_needs_physical = 1,
 201         .ring_mask = RENDER_RING,
 202 };
 203 static const struct intel_device_info intel_i945gm_info = {
 204         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 205         .has_hotplug = 1, .cursor_needs_physical = 1,
 206         .has_overlay = 1, .overlay_needs_physical = 1,
 207         .supports_tv = 1,
 208         .has_fbc = 1,
 209         .ring_mask = RENDER_RING,
 210 };
 211
 212 static const struct intel_device_info intel_i965g_info = {
 213         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 214         .has_hotplug = 1,
 215         .has_overlay = 1,
 216         .ring_mask = RENDER_RING,
 217 };
 218
 219 static const struct intel_device_info intel_i965gm_info = {
 220         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 221         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 222         .has_overlay = 1,
 223         .supports_tv = 1,
 224         .ring_mask = RENDER_RING,
 225 };
 226
 227 static const struct intel_device_info intel_g33_info = {
 228         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 229         .need_gfx_hws = 1, .has_hotplug = 1,
 230         .has_overlay = 1,
 231         .ring_mask = RENDER_RING,
 232 };
 233
 234 static const struct intel_device_info intel_g45_info = {
 235         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 236         .has_pipe_cxsr = 1, .has_hotplug = 1,
 237         .ring_mask = RENDER_RING | BSD_RING,
 238 };
 239
 240 static const struct intel_device_info intel_gm45_info = {
 241         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 242         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 243         .has_pipe_cxsr = 1, .has_hotplug = 1,
 244         .supports_tv = 1,
 245         .ring_mask = RENDER_RING | BSD_RING,
 246 };
 247
 248 static const struct intel_device_info intel_pineview_info = {
 249         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 250         .need_gfx_hws = 1, .has_hotplug = 1,
 251         .has_overlay = 1,
 252 };
 253
 254 static const struct intel_device_info intel_ironlake_d_info = {
 255         .gen = 5, .num_pipes = 2,
 256         .need_gfx_hws = 1, .has_hotplug = 1,
 257         .ring_mask = RENDER_RING | BSD_RING,
 258 };
 259
 260 static const struct intel_device_info intel_ironlake_m_info = {
 261         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 262         .need_gfx_hws = 1, .has_hotplug = 1,
 263         .has_fbc = 1,
 264         .ring_mask = RENDER_RING | BSD_RING,
 265 };
 266
 267 static const struct intel_device_info intel_sandybridge_d_info = {
 268         .gen = 6, .num_pipes = 2,
 269         .need_gfx_hws = 1, .has_hotplug = 1,
 270         .has_fbc = 1,
 271         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 272         .has_llc = 1,
 273 };
 274
 275 static const struct intel_device_info intel_sandybridge_m_info = {
 276         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 277         .need_gfx_hws = 1, .has_hotplug = 1,
 278         .has_fbc = 1,
 279         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 280         .has_llc = 1,
 281 };
 282
 283 #define GEN7_FEATURES  \
 284         .gen = 7, .num_pipes = 3, \
 285         .need_gfx_hws = 1, .has_hotplug = 1, \
 286         .has_fbc = 1, \
 287         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 288         .has_llc = 1
 289
 290 static const struct intel_device_info intel_ivybridge_d_info = {
 291         GEN7_FEATURES,
 292         .is_ivybridge = 1,
 293 };
 294
 295 static const struct intel_device_info intel_ivybridge_m_info = {
 296         GEN7_FEATURES,
 297         .is_ivybridge = 1,
 298         .is_mobile = 1,
 299 };
 300
 301 static const struct intel_device_info intel_ivybridge_q_info = {
 302         GEN7_FEATURES,
 303         .is_ivybridge = 1,
 304         .num_pipes = 0, /* legal, last one wins */
 305 };
 306
 307 static const struct intel_device_info intel_valleyview_m_info = {
 308         GEN7_FEATURES,
 309         .is_mobile = 1,
 310         .num_pipes = 2,
 311         .is_valleyview = 1,
 312         .display_mmio_offset = VLV_DISPLAY_BASE,
 313         .has_fbc = 0, /* legal, last one wins */
 314         .has_llc = 0, /* legal, last one wins */
 315 };
 316
 317 static const struct intel_device_info intel_valleyview_d_info = {
 318         GEN7_FEATURES,
 319         .num_pipes = 2,
 320         .is_valleyview = 1,
 321         .display_mmio_offset = VLV_DISPLAY_BASE,
 322         .has_fbc = 0, /* legal, last one wins */
 323         .has_llc = 0, /* legal, last one wins */
 324 };
 325
 326 static const struct intel_device_info intel_haswell_d_info = {
 327         GEN7_FEATURES,
 328         .is_haswell = 1,
 329         .has_ddi = 1,
 330         .has_fpga_dbg = 1,
 331         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 332 };
 333
 334 static const struct intel_device_info intel_haswell_m_info = {
 335         GEN7_FEATURES,
 336         .is_haswell = 1,
 337         .is_mobile = 1,
 338         .has_ddi = 1,
 339         .has_fpga_dbg = 1,
 340         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 341 };
 342
 343 static const struct intel_device_info intel_broadwell_d_info = {
 344         .is_preliminary = 1,
 345         .gen = 8, .num_pipes = 3,
 346         .need_gfx_hws = 1, .has_hotplug = 1,
 347         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 348         .has_llc = 1,
 349         .has_ddi = 1,
 350 };
 351
 352 static const struct intel_device_info intel_broadwell_m_info = {
 353         .is_preliminary = 1,
 354         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 355         .need_gfx_hws = 1, .has_hotplug = 1,
 356         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 357         .has_llc = 1,
 358         .has_ddi = 1,
 359 };
 360
 361 /*
 362  * Make sure any device matches here are from most specific to most
 363  * general.  For example, since the Quanta match is based on the subsystem
 364  * and subvendor IDs, we need it to come before the more general IVB
 365  * PCI ID matches, otherwise we'll use the wrong info struct above.
 366  */
 367 #define INTEL_PCI_IDS \
 368         INTEL_I830_IDS(&intel_i830_info),       \
 369         INTEL_I845G_IDS(&intel_845g_info),      \
 370         INTEL_I85X_IDS(&intel_i85x_info),       \
 371         INTEL_I865G_IDS(&intel_i865g_info),     \
 372         INTEL_I915G_IDS(&intel_i915g_info),     \
 373         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 374         INTEL_I945G_IDS(&intel_i945g_info),     \
 375         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 376         INTEL_I965G_IDS(&intel_i965g_info),     \
 377         INTEL_G33_IDS(&intel_g33_info),         \
 378         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 379         INTEL_GM45_IDS(&intel_gm45_info),       \
 380         INTEL_G45_IDS(&intel_g45_info),         \
 381         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 382         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 383         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 384         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 385         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 386         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 387         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 388         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 389         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 390         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 391         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 392         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 393         INTEL_BDW_M_IDS(&intel_broadwell_m_info),       \
 394         INTEL_BDW_D_IDS(&intel_broadwell_d_info)
 395
 396 static const struct pci_device_id pciidlist[] = {               /* aka */
 397         INTEL_PCI_IDS,
 398         {0, 0, 0}
 399 };
 400
 401 #if defined(CONFIG_DRM_I915_KMS)
 402 MODULE_DEVICE_TABLE(pci, pciidlist);
 403 #endif
 404
 405 void intel_detect_pch(struct drm_device *dev)
 406 {
 407         struct drm_i915_private *dev_priv = dev->dev_private;
 408         struct pci_dev *pch;
 409
 410         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 411          * (which really amounts to a PCH but no South Display).
 412          */
 413         if (INTEL_INFO(dev)->num_pipes == 0) {
 414                 dev_priv->pch_type = PCH_NOP;
 415                 return;
 416         }
 417
 418         /*
 419          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 420          * make graphics device passthrough work easy for VMM, that only
 421          * need to expose ISA bridge to let driver know the real hardware
 422          * underneath. This is a requirement from virtualization team.
 423          *
 424          * In some virtualized environments (e.g. XEN), there is irrelevant
 425          * ISA bridge in the system. To work reliably, we should scan trhough
 426          * all the ISA bridge devices and check for the first match, instead
 427          * of only checking the first one.
 428          */
 429         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 430         while (pch) {
 431                 struct pci_dev *curr = pch;
 432                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 433                         unsigned short id;
 434                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 435                         dev_priv->pch_id = id;
 436
 437                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 438                                 dev_priv->pch_type = PCH_IBX;
 439                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 440                                 WARN_ON(!IS_GEN5(dev));
 441                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 442                                 dev_priv->pch_type = PCH_CPT;
 443                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 444                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 445                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 446                                 /* PantherPoint is CPT compatible */
 447                                 dev_priv->pch_type = PCH_CPT;
 448                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 449                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 450                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 451                                 dev_priv->pch_type = PCH_LPT;
 452                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 453                                 WARN_ON(!IS_HASWELL(dev));
 454                                 WARN_ON(IS_ULT(dev));
 455                         } else if (IS_BROADWELL(dev)) {
 456                                 dev_priv->pch_type = PCH_LPT;
 457                                 dev_priv->pch_id =
 458                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 459                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 460                                               "LynxPoint LP PCH\n");
 461                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 462                                 dev_priv->pch_type = PCH_LPT;
 463                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 464                                 WARN_ON(!IS_HASWELL(dev));
 465                                 WARN_ON(!IS_ULT(dev));
 466                         } else {
 467                                 goto check_next;
 468                         }
 469                         pci_dev_put(pch);
 470                         break;
 471                 }
 472 check_next:
 473                 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr);
 474                 pci_dev_put(curr);
 475         }
 476         if (!pch)
 477                 DRM_DEBUG_KMS("No PCH found?\n");
 478 }
 479
 480 bool i915_semaphore_is_enabled(struct drm_device *dev)
 481 {
 482         if (INTEL_INFO(dev)->gen < 6)
 483                 return 0;
 484
 485         /* Until we get further testing... */
 486         if (IS_GEN8(dev)) {
 487                 WARN_ON(!i915_preliminary_hw_support);
 488                 return 0;
 489         }
 490
 491         if (i915_semaphores >= 0)
 492                 return i915_semaphores;
 493
 494 #ifdef CONFIG_INTEL_IOMMU
 495         /* Enable semaphores on SNB when IO remapping is off */
 496         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 497                 return false;
 498 #endif
 499
 500         return 1;
 501 }
 502
 503 static int i915_drm_freeze(struct drm_device *dev)
 504 {
 505         struct drm_i915_private *dev_priv = dev->dev_private;
 506         struct drm_crtc *crtc;
 507
 508         intel_runtime_pm_get(dev_priv);
 509
 510         /* ignore lid events during suspend */
 511         mutex_lock(&dev_priv->modeset_restore_lock);
 512         dev_priv->modeset_restore = MODESET_SUSPENDED;
 513         mutex_unlock(&dev_priv->modeset_restore_lock);
 514
 515         /* We do a lot of poking in a lot of registers, make sure they work
 516          * properly. */
 517         hsw_disable_package_c8(dev_priv);
 518         intel_display_set_init_power(dev, true);
 519
 520         drm_kms_helper_poll_disable(dev);
 521
 522         pci_save_state(dev->pdev);
 523
 524         /* If KMS is active, we do the leavevt stuff here */
 525         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 526                 int error;
 527
 528                 error = i915_gem_suspend(dev);
 529                 if (error) {
 530                         dev_err(&dev->pdev->dev,
 531                                 "GEM idle failed, resume might fail\n");
 532                         return error;
 533                 }
 534
 535                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 536
 537                 drm_irq_uninstall(dev);
 538                 dev_priv->enable_hotplug_processing = false;
 539                 /*
 540                  * Disable CRTCs directly since we want to preserve sw state
 541                  * for _thaw.
 542                  */
 543                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 544                         dev_priv->display.crtc_disable(crtc);
 545
 546                 intel_modeset_suspend_hw(dev);
 547         }
 548
 549         i915_gem_suspend_gtt_mappings(dev);
 550
 551         i915_save_state(dev);
 552
 553         intel_opregion_fini(dev);
 554
 555         console_lock();
 556         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 557         console_unlock();
 558
 559         return 0;
 560 }
 561
 562 int i915_suspend(struct drm_device *dev, pm_message_t state)
 563 {
 564         int error;
 565
 566         if (!dev || !dev->dev_private) {
 567                 DRM_ERROR("dev: %p\n", dev);
 568                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 569                 return -ENODEV;
 570         }
 571
 572         if (state.event == PM_EVENT_PRETHAW)
 573                 return 0;
 574
 575
 576         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 577                 return 0;
 578
 579         error = i915_drm_freeze(dev);
 580         if (error)
 581                 return error;
 582
 583         if (state.event == PM_EVENT_SUSPEND) {
 584                 /* Shut down the device */
 585                 pci_disable_device(dev->pdev);
 586                 pci_set_power_state(dev->pdev, PCI_D3hot);
 587         }
 588
 589         return 0;
 590 }
 591
 592 void intel_console_resume(struct work_struct *work)
 593 {
 594         struct drm_i915_private *dev_priv =
 595                 container_of(work, struct drm_i915_private,
 596                              console_resume_work);
 597         struct drm_device *dev = dev_priv->dev;
 598
 599         console_lock();
 600         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 601         console_unlock();
 602 }
 603
 604 static void intel_resume_hotplug(struct drm_device *dev)
 605 {
 606         struct drm_mode_config *mode_config = &dev->mode_config;
 607         struct intel_encoder *encoder;
 608
 609         mutex_lock(&mode_config->mutex);
 610         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 611
 612         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 613                 if (encoder->hot_plug)
 614                         encoder->hot_plug(encoder);
 615
 616         mutex_unlock(&mode_config->mutex);
 617
 618         /* Just fire off a uevent and let userspace tell us what to do */
 619         drm_helper_hpd_irq_event(dev);
 620 }
 621
 622 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 623 {
 624         struct drm_i915_private *dev_priv = dev->dev_private;
 625         int error = 0;
 626
 627         intel_uncore_early_sanitize(dev);
 628
 629         intel_uncore_sanitize(dev);
 630
 631         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 632             restore_gtt_mappings) {
 633                 mutex_lock(&dev->struct_mutex);
 634                 i915_gem_restore_gtt_mappings(dev);
 635                 mutex_unlock(&dev->struct_mutex);
 636         }
 637
 638         intel_power_domains_init_hw(dev);
 639
 640         i915_restore_state(dev);
 641         intel_opregion_setup(dev);
 642
 643         /* KMS EnterVT equivalent */
 644         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 645                 intel_init_pch_refclk(dev);
 646
 647                 mutex_lock(&dev->struct_mutex);
 648
 649                 error = i915_gem_init_hw(dev);
 650                 mutex_unlock(&dev->struct_mutex);
 651
 652                 /* We need working interrupts for modeset enabling ... */
 653                 drm_irq_install(dev);
 654
 655                 intel_modeset_init_hw(dev);
 656
 657                 drm_modeset_lock_all(dev);
 658                 intel_modeset_setup_hw_state(dev, true);
 659                 drm_modeset_unlock_all(dev);
 660
 661                 /*
 662                  * ... but also need to make sure that hotplug processing
 663                  * doesn't cause havoc. Like in the driver load code we don't
 664                  * bother with the tiny race here where we might loose hotplug
 665                  * notifications.
 666                  * */
 667                 intel_hpd_init(dev);
 668                 dev_priv->enable_hotplug_processing = true;
 669                 /* Config may have changed between suspend and resume */
 670                 intel_resume_hotplug(dev);
 671         }
 672
 673         intel_opregion_init(dev);
 674
 675         /*
 676          * The console lock can be pretty contented on resume due
 677          * to all the printk activity.  Try to keep it out of the hot
 678          * path of resume if possible.
 679          */
 680         if (console_trylock()) {
 681                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 682                 console_unlock();
 683         } else {
 684                 schedule_work(&dev_priv->console_resume_work);
 685         }
 686
 687         /* Undo what we did at i915_drm_freeze so the refcount goes back to the
 688          * expected level. */
 689         hsw_enable_package_c8(dev_priv);
 690
 691         mutex_lock(&dev_priv->modeset_restore_lock);
 692         dev_priv->modeset_restore = MODESET_DONE;
 693         mutex_unlock(&dev_priv->modeset_restore_lock);
 694
 695         intel_runtime_pm_put(dev_priv);
 696         return error;
 697 }
 698
 699 static int i915_drm_thaw(struct drm_device *dev)
 700 {
 701         if (drm_core_check_feature(dev, DRIVER_MODESET))
 702                 i915_check_and_clear_faults(dev);
 703
 704         return __i915_drm_thaw(dev, true);
 705 }
 706
 707 int i915_resume(struct drm_device *dev)
 708 {
 709         struct drm_i915_private *dev_priv = dev->dev_private;
 710         int ret;
 711
 712         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 713                 return 0;
 714
 715         if (pci_enable_device(dev->pdev))
 716                 return -EIO;
 717
 718         pci_set_master(dev->pdev);
 719
 720         /*
 721          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 722          * earlier) need to restore the GTT mappings since the BIOS might clear
 723          * all our scratch PTEs.
 724          */
 725         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 726         if (ret)
 727                 return ret;
 728
 729         drm_kms_helper_poll_enable(dev);
 730         return 0;
 731 }
 732
 733 /**
 734  * i915_reset - reset chip after a hang
 735  * @dev: drm device to reset
 736  *
 737  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 738  * reset or otherwise an error code.
 739  *
 740  * Procedure is fairly simple:
 741  *   - reset the chip using the reset reg
 742  *   - re-init context state
 743  *   - re-init hardware status page
 744  *   - re-init ring buffer
 745  *   - re-init interrupt state
 746  *   - re-init display
 747  */
 748 int i915_reset(struct drm_device *dev)
 749 {
 750         drm_i915_private_t *dev_priv = dev->dev_private;
 751         bool simulated;
 752         int ret;
 753
 754         if (!i915_try_reset)
 755                 return 0;
 756
 757         mutex_lock(&dev->struct_mutex);
 758
 759         i915_gem_reset(dev);
 760
 761         simulated = dev_priv->gpu_error.stop_rings != 0;
 762
 763         ret = intel_gpu_reset(dev);
 764
 765         /* Also reset the gpu hangman. */
 766         if (simulated) {
 767                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 768                 dev_priv->gpu_error.stop_rings = 0;
 769                 if (ret == -ENODEV) {
 770                         DRM_INFO("Reset not implemented, but ignoring "
 771                                  "error for simulated gpu hangs\n");
 772                         ret = 0;
 773                 }
 774         }
 775
 776         if (ret) {
 777                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 778                 mutex_unlock(&dev->struct_mutex);
 779                 return ret;
 780         }
 781
 782         /* Ok, now get things going again... */
 783
 784         /*
 785          * Everything depends on having the GTT running, so we need to start
 786          * there.  Fortunately we don't need to do this unless we reset the
 787          * chip at a PCI level.
 788          *
 789          * Next we need to restore the context, but we don't use those
 790          * yet either...
 791          *
 792          * Ring buffer needs to be re-initialized in the KMS case, or if X
 793          * was running at the time of the reset (i.e. we weren't VT
 794          * switched away).
 795          */
 796         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 797                         !dev_priv->ums.mm_suspended) {
 798                 dev_priv->ums.mm_suspended = 0;
 799
 800                 ret = i915_gem_init_hw(dev);
 801                 mutex_unlock(&dev->struct_mutex);
 802                 if (ret) {
 803                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 804                         return ret;
 805                 }
 806
 807                 drm_irq_uninstall(dev);
 808                 drm_irq_install(dev);
 809                 intel_hpd_init(dev);
 810         } else {
 811                 mutex_unlock(&dev->struct_mutex);
 812         }
 813
 814         return 0;
 815 }
 816
 817 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 818 {
 819         struct intel_device_info *intel_info =
 820                 (struct intel_device_info *) ent->driver_data;
 821
 822         if (IS_PRELIMINARY_HW(intel_info) && !i915_preliminary_hw_support) {
 823                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 824                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 825                 return -ENODEV;
 826         }
 827
 828         /* Only bind to function 0 of the device. Early generations
 829          * used function 1 as a placeholder for multi-head. This causes
 830          * us confusion instead, especially on the systems where both
 831          * functions have the same PCI-ID!
 832          */
 833         if (PCI_FUNC(pdev->devfn))
 834                 return -ENODEV;
 835
 836         driver.driver_features &= ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 837
 838         return drm_get_pci_dev(pdev, ent, &driver);
 839 }
 840
 841 static void
 842 i915_pci_remove(struct pci_dev *pdev)
 843 {
 844         struct drm_device *dev = pci_get_drvdata(pdev);
 845
 846         drm_put_dev(dev);
 847 }
 848
 849 static int i915_pm_suspend(struct device *dev)
 850 {
 851         struct pci_dev *pdev = to_pci_dev(dev);
 852         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 853         int error;
 854
 855         if (!drm_dev || !drm_dev->dev_private) {
 856                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 857                 return -ENODEV;
 858         }
 859
 860         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 861                 return 0;
 862
 863         error = i915_drm_freeze(drm_dev);
 864         if (error)
 865                 return error;
 866
 867         pci_disable_device(pdev);
 868         pci_set_power_state(pdev, PCI_D3hot);
 869
 870         return 0;
 871 }
 872
 873 static int i915_pm_resume(struct device *dev)
 874 {
 875         struct pci_dev *pdev = to_pci_dev(dev);
 876         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 877
 878         return i915_resume(drm_dev);
 879 }
 880
 881 static int i915_pm_freeze(struct device *dev)
 882 {
 883         struct pci_dev *pdev = to_pci_dev(dev);
 884         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 885
 886         if (!drm_dev || !drm_dev->dev_private) {
 887                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 888                 return -ENODEV;
 889         }
 890
 891         return i915_drm_freeze(drm_dev);
 892 }
 893
 894 static int i915_pm_thaw(struct device *dev)
 895 {
 896         struct pci_dev *pdev = to_pci_dev(dev);
 897         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 898
 899         return i915_drm_thaw(drm_dev);
 900 }
 901
 902 static int i915_pm_poweroff(struct device *dev)
 903 {
 904         struct pci_dev *pdev = to_pci_dev(dev);
 905         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 906
 907         return i915_drm_freeze(drm_dev);
 908 }
 909
 910 static int i915_runtime_suspend(struct device *device)
 911 {
 912         struct pci_dev *pdev = to_pci_dev(device);
 913         struct drm_device *dev = pci_get_drvdata(pdev);
 914         struct drm_i915_private *dev_priv = dev->dev_private;
 915
 916         WARN_ON(!HAS_RUNTIME_PM(dev));
 917
 918         DRM_DEBUG_KMS("Suspending device\n");
 919
 920         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
 921         dev_priv->pm.suspended = true;
 922         intel_opregion_notify_adapter(dev, PCI_D3cold);
 923
 924         return 0;
 925 }
 926
 927 static int i915_runtime_resume(struct device *device)
 928 {
 929         struct pci_dev *pdev = to_pci_dev(device);
 930         struct drm_device *dev = pci_get_drvdata(pdev);
 931         struct drm_i915_private *dev_priv = dev->dev_private;
 932
 933         WARN_ON(!HAS_RUNTIME_PM(dev));
 934
 935         DRM_DEBUG_KMS("Resuming device\n");
 936
 937         intel_opregion_notify_adapter(dev, PCI_D0);
 938         dev_priv->pm.suspended = false;
 939
 940         return 0;
 941 }
 942
 943 static const struct dev_pm_ops i915_pm_ops = {
 944         .suspend = i915_pm_suspend,
 945         .resume = i915_pm_resume,
 946         .freeze = i915_pm_freeze,
 947         .thaw = i915_pm_thaw,
 948         .poweroff = i915_pm_poweroff,
 949         .restore = i915_pm_resume,
 950         .runtime_suspend = i915_runtime_suspend,
 951         .runtime_resume = i915_runtime_resume,
 952 };
 953
 954 static const struct vm_operations_struct i915_gem_vm_ops = {
 955         .fault = i915_gem_fault,
 956         .open = drm_gem_vm_open,
 957         .close = drm_gem_vm_close,
 958 };
 959
 960 static const struct file_operations i915_driver_fops = {
 961         .owner = THIS_MODULE,
 962         .open = drm_open,
 963         .release = drm_release,
 964         .unlocked_ioctl = drm_ioctl,
 965         .mmap = drm_gem_mmap,
 966         .poll = drm_poll,
 967         .read = drm_read,
 968 #ifdef CONFIG_COMPAT
 969         .compat_ioctl = i915_compat_ioctl,
 970 #endif
 971         .llseek = noop_llseek,
 972 };
 973
 974 static struct drm_driver driver = {
 975         /* Don't use MTRRs here; the Xserver or userspace app should
 976          * deal with them for Intel hardware.
 977          */
 978         .driver_features =
 979             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
 980             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
 981             DRIVER_RENDER,
 982         .load = i915_driver_load,
 983         .unload = i915_driver_unload,
 984         .open = i915_driver_open,
 985         .lastclose = i915_driver_lastclose,
 986         .preclose = i915_driver_preclose,
 987         .postclose = i915_driver_postclose,
 988
 989         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 990         .suspend = i915_suspend,
 991         .resume = i915_resume,
 992
 993         .device_is_agp = i915_driver_device_is_agp,
 994         .master_create = i915_master_create,
 995         .master_destroy = i915_master_destroy,
 996 #if defined(CONFIG_DEBUG_FS)
 997         .debugfs_init = i915_debugfs_init,
 998         .debugfs_cleanup = i915_debugfs_cleanup,
 999 #endif
1000         .gem_free_object = i915_gem_free_object,
1001         .gem_vm_ops = &i915_gem_vm_ops,
1002
1003         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1004         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1005         .gem_prime_export = i915_gem_prime_export,
1006         .gem_prime_import = i915_gem_prime_import,
1007
1008         .dumb_create = i915_gem_dumb_create,
1009         .dumb_map_offset = i915_gem_mmap_gtt,
1010         .dumb_destroy = drm_gem_dumb_destroy,
1011         .ioctls = i915_ioctls,
1012         .fops = &i915_driver_fops,
1013         .name = DRIVER_NAME,
1014         .desc = DRIVER_DESC,
1015         .date = DRIVER_DATE,
1016         .major = DRIVER_MAJOR,
1017         .minor = DRIVER_MINOR,
1018         .patchlevel = DRIVER_PATCHLEVEL,
1019 };
1020
1021 static struct pci_driver i915_pci_driver = {
1022         .name = DRIVER_NAME,
1023         .id_table = pciidlist,
1024         .probe = i915_pci_probe,
1025         .remove = i915_pci_remove,
1026         .driver.pm = &i915_pm_ops,
1027 };
1028
1029 static int __init i915_init(void)
1030 {
1031         driver.num_ioctls = i915_max_ioctl;
1032
1033         /*
1034          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1035          * explicitly disabled with the module pararmeter.
1036          *
1037          * Otherwise, just follow the parameter (defaulting to off).
1038          *
1039          * Allow optional vga_text_mode_force boot option to override
1040          * the default behavior.
1041          */
1042 #if defined(CONFIG_DRM_I915_KMS)
1043         if (i915_modeset != 0)
1044                 driver.driver_features |= DRIVER_MODESET;
1045 #endif
1046         if (i915_modeset == 1)
1047                 driver.driver_features |= DRIVER_MODESET;
1048
1049 #ifdef CONFIG_VGA_CONSOLE
1050         if (vgacon_text_force() && i915_modeset == -1)
1051                 driver.driver_features &= ~DRIVER_MODESET;
1052 #endif
1053
1054         if (!(driver.driver_features & DRIVER_MODESET)) {
1055                 driver.get_vblank_timestamp = NULL;
1056 #ifndef CONFIG_DRM_I915_UMS
1057                 /* Silently fail loading to not upset userspace. */
1058                 return 0;
1059 #endif
1060         }
1061
1062         return drm_pci_init(&driver, &i915_pci_driver);
1063 }
1064
1065 static void __exit i915_exit(void)
1066 {
1067 #ifndef CONFIG_DRM_I915_UMS
1068         if (!(driver.driver_features & DRIVER_MODESET))
1069                 return; /* Never loaded a driver. */
1070 #endif
1071
1072         drm_pci_exit(&driver, &i915_pci_driver);
1073 }
1074
1075 module_init(i915_init);
1076 module_exit(i915_exit);
1077
1078 MODULE_AUTHOR(DRIVER_AUTHOR);
1079 MODULE_DESCRIPTION(DRIVER_DESC);
1080 MODULE_LICENSE("GPL and additional rights");