drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42
  43 static struct drm_driver driver;
  44
  45 #define GEN_DEFAULT_PIPEOFFSETS \
  46         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  47                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  48         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  49                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52 #define GEN_CHV_PIPEOFFSETS \
  53         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  54                           CHV_PIPE_C_OFFSET }, \
  55         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  56                            CHV_TRANSCODER_C_OFFSET, }, \
  57         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  58                              CHV_PALETTE_C_OFFSET }
  59
  60 #define CURSOR_OFFSETS \
  61         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  62
  63 #define IVB_CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  65
  66 static const struct intel_device_info intel_i830_info = {
  67         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  68         .has_overlay = 1, .overlay_needs_physical = 1,
  69         .ring_mask = RENDER_RING,
  70         GEN_DEFAULT_PIPEOFFSETS,
  71         CURSOR_OFFSETS,
  72 };
  73
  74 static const struct intel_device_info intel_845g_info = {
  75         .gen = 2, .num_pipes = 1,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_i85x_info = {
  83         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  84         .cursor_needs_physical = 1,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .has_fbc = 1,
  87         .ring_mask = RENDER_RING,
  88         GEN_DEFAULT_PIPEOFFSETS,
  89         CURSOR_OFFSETS,
  90 };
  91
  92 static const struct intel_device_info intel_i865g_info = {
  93         .gen = 2, .num_pipes = 1,
  94         .has_overlay = 1, .overlay_needs_physical = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i915g_info = {
 101         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112         .has_fbc = 1,
 113         .ring_mask = RENDER_RING,
 114         GEN_DEFAULT_PIPEOFFSETS,
 115         CURSOR_OFFSETS,
 116 };
 117 static const struct intel_device_info intel_i945g_info = {
 118         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 119         .has_overlay = 1, .overlay_needs_physical = 1,
 120         .ring_mask = RENDER_RING,
 121         GEN_DEFAULT_PIPEOFFSETS,
 122         CURSOR_OFFSETS,
 123 };
 124 static const struct intel_device_info intel_i945gm_info = {
 125         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 126         .has_hotplug = 1, .cursor_needs_physical = 1,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .supports_tv = 1,
 129         .has_fbc = 1,
 130         .ring_mask = RENDER_RING,
 131         GEN_DEFAULT_PIPEOFFSETS,
 132         CURSOR_OFFSETS,
 133 };
 134
 135 static const struct intel_device_info intel_i965g_info = {
 136         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 137         .has_hotplug = 1,
 138         .has_overlay = 1,
 139         .ring_mask = RENDER_RING,
 140         GEN_DEFAULT_PIPEOFFSETS,
 141         CURSOR_OFFSETS,
 142 };
 143
 144 static const struct intel_device_info intel_i965gm_info = {
 145         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 146         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 147         .has_overlay = 1,
 148         .supports_tv = 1,
 149         .ring_mask = RENDER_RING,
 150         GEN_DEFAULT_PIPEOFFSETS,
 151         CURSOR_OFFSETS,
 152 };
 153
 154 static const struct intel_device_info intel_g33_info = {
 155         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_overlay = 1,
 158         .ring_mask = RENDER_RING,
 159         GEN_DEFAULT_PIPEOFFSETS,
 160         CURSOR_OFFSETS,
 161 };
 162
 163 static const struct intel_device_info intel_g45_info = {
 164         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 165         .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .ring_mask = RENDER_RING | BSD_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_gm45_info = {
 172         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 173         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 174         .has_pipe_cxsr = 1, .has_hotplug = 1,
 175         .supports_tv = 1,
 176         .ring_mask = RENDER_RING | BSD_RING,
 177         GEN_DEFAULT_PIPEOFFSETS,
 178         CURSOR_OFFSETS,
 179 };
 180
 181 static const struct intel_device_info intel_pineview_info = {
 182         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_ironlake_d_info = {
 190         .gen = 5, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .ring_mask = RENDER_RING | BSD_RING,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_m_info = {
 198         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .has_fbc = 1,
 201         .ring_mask = RENDER_RING | BSD_RING,
 202         GEN_DEFAULT_PIPEOFFSETS,
 203         CURSOR_OFFSETS,
 204 };
 205
 206 static const struct intel_device_info intel_sandybridge_d_info = {
 207         .gen = 6, .num_pipes = 2,
 208         .need_gfx_hws = 1, .has_hotplug = 1,
 209         .has_fbc = 1,
 210         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 211         .has_llc = 1,
 212         GEN_DEFAULT_PIPEOFFSETS,
 213         CURSOR_OFFSETS,
 214 };
 215
 216 static const struct intel_device_info intel_sandybridge_m_info = {
 217         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 218         .need_gfx_hws = 1, .has_hotplug = 1,
 219         .has_fbc = 1,
 220         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 221         .has_llc = 1,
 222         GEN_DEFAULT_PIPEOFFSETS,
 223         CURSOR_OFFSETS,
 224 };
 225
 226 #define GEN7_FEATURES  \
 227         .gen = 7, .num_pipes = 3, \
 228         .need_gfx_hws = 1, .has_hotplug = 1, \
 229         .has_fbc = 1, \
 230         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 231         .has_llc = 1, \
 232         GEN_DEFAULT_PIPEOFFSETS, \
 233         IVB_CURSOR_OFFSETS
 234
 235 static const struct intel_device_info intel_ivybridge_d_info = {
 236         GEN7_FEATURES,
 237         .is_ivybridge = 1,
 238 };
 239
 240 static const struct intel_device_info intel_ivybridge_m_info = {
 241         GEN7_FEATURES,
 242         .is_ivybridge = 1,
 243         .is_mobile = 1,
 244 };
 245
 246 static const struct intel_device_info intel_ivybridge_q_info = {
 247         GEN7_FEATURES,
 248         .is_ivybridge = 1,
 249         .num_pipes = 0, /* legal, last one wins */
 250 };
 251
 252 #define VLV_FEATURES  \
 253         .gen = 7, .num_pipes = 2, \
 254         .need_gfx_hws = 1, .has_hotplug = 1, \
 255         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 256         .display_mmio_offset = VLV_DISPLAY_BASE, \
 257         GEN_DEFAULT_PIPEOFFSETS, \
 258         CURSOR_OFFSETS
 259
 260 static const struct intel_device_info intel_valleyview_m_info = {
 261         VLV_FEATURES,
 262         .is_valleyview = 1,
 263         .is_mobile = 1,
 264 };
 265
 266 static const struct intel_device_info intel_valleyview_d_info = {
 267         VLV_FEATURES,
 268         .is_valleyview = 1,
 269 };
 270
 271 #define HSW_FEATURES  \
 272         GEN7_FEATURES, \
 273         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 274         .has_ddi = 1, \
 275         .has_fpga_dbg = 1
 276
 277 static const struct intel_device_info intel_haswell_d_info = {
 278         HSW_FEATURES,
 279         .is_haswell = 1,
 280 };
 281
 282 static const struct intel_device_info intel_haswell_m_info = {
 283         HSW_FEATURES,
 284         .is_haswell = 1,
 285         .is_mobile = 1,
 286 };
 287
 288 static const struct intel_device_info intel_broadwell_d_info = {
 289         HSW_FEATURES,
 290         .gen = 8,
 291 };
 292
 293 static const struct intel_device_info intel_broadwell_m_info = {
 294         HSW_FEATURES,
 295         .gen = 8, .is_mobile = 1,
 296 };
 297
 298 static const struct intel_device_info intel_broadwell_gt3d_info = {
 299         HSW_FEATURES,
 300         .gen = 8,
 301         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 302 };
 303
 304 static const struct intel_device_info intel_broadwell_gt3m_info = {
 305         HSW_FEATURES,
 306         .gen = 8, .is_mobile = 1,
 307         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 308 };
 309
 310 static const struct intel_device_info intel_cherryview_info = {
 311         .gen = 8, .num_pipes = 3,
 312         .need_gfx_hws = 1, .has_hotplug = 1,
 313         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 314         .is_cherryview = 1,
 315         .display_mmio_offset = VLV_DISPLAY_BASE,
 316         GEN_CHV_PIPEOFFSETS,
 317         CURSOR_OFFSETS,
 318 };
 319
 320 static const struct intel_device_info intel_skylake_info = {
 321         HSW_FEATURES,
 322         .is_skylake = 1,
 323         .gen = 9,
 324 };
 325
 326 static const struct intel_device_info intel_skylake_gt3_info = {
 327         HSW_FEATURES,
 328         .is_skylake = 1,
 329         .gen = 9,
 330         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 331 };
 332
 333 static const struct intel_device_info intel_broxton_info = {
 334         .is_preliminary = 1,
 335         .is_broxton = 1,
 336         .gen = 9,
 337         .need_gfx_hws = 1, .has_hotplug = 1,
 338         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 339         .num_pipes = 3,
 340         .has_ddi = 1,
 341         .has_fpga_dbg = 1,
 342         .has_fbc = 1,
 343         GEN_DEFAULT_PIPEOFFSETS,
 344         IVB_CURSOR_OFFSETS,
 345 };
 346
 347 static const struct intel_device_info intel_kabylake_info = {
 348         HSW_FEATURES,
 349         .is_preliminary = 1,
 350         .is_kabylake = 1,
 351         .gen = 9,
 352 };
 353
 354 static const struct intel_device_info intel_kabylake_gt3_info = {
 355         HSW_FEATURES,
 356         .is_preliminary = 1,
 357         .is_kabylake = 1,
 358         .gen = 9,
 359         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 360 };
 361
 362 /*
 363  * Make sure any device matches here are from most specific to most
 364  * general.  For example, since the Quanta match is based on the subsystem
 365  * and subvendor IDs, we need it to come before the more general IVB
 366  * PCI ID matches, otherwise we'll use the wrong info struct above.
 367  */
 368 static const struct pci_device_id pciidlist[] = {
 369         INTEL_I830_IDS(&intel_i830_info),
 370         INTEL_I845G_IDS(&intel_845g_info),
 371         INTEL_I85X_IDS(&intel_i85x_info),
 372         INTEL_I865G_IDS(&intel_i865g_info),
 373         INTEL_I915G_IDS(&intel_i915g_info),
 374         INTEL_I915GM_IDS(&intel_i915gm_info),
 375         INTEL_I945G_IDS(&intel_i945g_info),
 376         INTEL_I945GM_IDS(&intel_i945gm_info),
 377         INTEL_I965G_IDS(&intel_i965g_info),
 378         INTEL_G33_IDS(&intel_g33_info),
 379         INTEL_I965GM_IDS(&intel_i965gm_info),
 380         INTEL_GM45_IDS(&intel_gm45_info),
 381         INTEL_G45_IDS(&intel_g45_info),
 382         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 383         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 384         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 385         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
 386         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
 387         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 388         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
 389         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
 390         INTEL_HSW_D_IDS(&intel_haswell_d_info),
 391         INTEL_HSW_M_IDS(&intel_haswell_m_info),
 392         INTEL_VLV_M_IDS(&intel_valleyview_m_info),
 393         INTEL_VLV_D_IDS(&intel_valleyview_d_info),
 394         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
 395         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
 396         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
 397         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
 398         INTEL_CHV_IDS(&intel_cherryview_info),
 399         INTEL_SKL_GT1_IDS(&intel_skylake_info),
 400         INTEL_SKL_GT2_IDS(&intel_skylake_info),
 401         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 402         INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
 403         INTEL_BXT_IDS(&intel_broxton_info),
 404         INTEL_KBL_GT1_IDS(&intel_kabylake_info),
 405         INTEL_KBL_GT2_IDS(&intel_kabylake_info),
 406         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 407         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 408         {0, 0, 0}
 409 };
 410
 411 MODULE_DEVICE_TABLE(pci, pciidlist);
 412
 413 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
 414 {
 415         enum intel_pch ret = PCH_NOP;
 416
 417         /*
 418          * In a virtualized passthrough environment we can be in a
 419          * setup where the ISA bridge is not able to be passed through.
 420          * In this case, a south bridge can be emulated and we have to
 421          * make an educated guess as to which PCH is really there.
 422          */
 423
 424         if (IS_GEN5(dev)) {
 425                 ret = PCH_IBX;
 426                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 427         } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
 428                 ret = PCH_CPT;
 429                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 430         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 431                 ret = PCH_LPT;
 432                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 433         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 434                 ret = PCH_SPT;
 435                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 436         }
 437
 438         return ret;
 439 }
 440
 441 void intel_detect_pch(struct drm_device *dev)
 442 {
 443         struct drm_i915_private *dev_priv = dev->dev_private;
 444         struct pci_dev *pch = NULL;
 445
 446         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 447          * (which really amounts to a PCH but no South Display).
 448          */
 449         if (INTEL_INFO(dev)->num_pipes == 0) {
 450                 dev_priv->pch_type = PCH_NOP;
 451                 return;
 452         }
 453
 454         /*
 455          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 456          * make graphics device passthrough work easy for VMM, that only
 457          * need to expose ISA bridge to let driver know the real hardware
 458          * underneath. This is a requirement from virtualization team.
 459          *
 460          * In some virtualized environments (e.g. XEN), there is irrelevant
 461          * ISA bridge in the system. To work reliably, we should scan trhough
 462          * all the ISA bridge devices and check for the first match, instead
 463          * of only checking the first one.
 464          */
 465         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 466                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 467                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 468                         dev_priv->pch_id = id;
 469
 470                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 471                                 dev_priv->pch_type = PCH_IBX;
 472                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 473                                 WARN_ON(!IS_GEN5(dev));
 474                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 475                                 dev_priv->pch_type = PCH_CPT;
 476                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 477                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 478                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 479                                 /* PantherPoint is CPT compatible */
 480                                 dev_priv->pch_type = PCH_CPT;
 481                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 482                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 483                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 484                                 dev_priv->pch_type = PCH_LPT;
 485                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 486                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 487                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 488                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 489                                 dev_priv->pch_type = PCH_LPT;
 490                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 491                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 492                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 493                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 494                                 dev_priv->pch_type = PCH_SPT;
 495                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 496                                 WARN_ON(!IS_SKYLAKE(dev) &&
 497                                         !IS_KABYLAKE(dev));
 498                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 499                                 dev_priv->pch_type = PCH_SPT;
 500                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 501                                 WARN_ON(!IS_SKYLAKE(dev) &&
 502                                         !IS_KABYLAKE(dev));
 503                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 504                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 505                                     pch->subsystem_vendor == 0x1af4 &&
 506                                     pch->subsystem_device == 0x1100)) {
 507                                 dev_priv->pch_type = intel_virt_detect_pch(dev);
 508                         } else
 509                                 continue;
 510
 511                         break;
 512                 }
 513         }
 514         if (!pch)
 515                 DRM_DEBUG_KMS("No PCH found.\n");
 516
 517         pci_dev_put(pch);
 518 }
 519
 520 bool i915_semaphore_is_enabled(struct drm_device *dev)
 521 {
 522         if (INTEL_INFO(dev)->gen < 6)
 523                 return false;
 524
 525         if (i915.semaphores >= 0)
 526                 return i915.semaphores;
 527
 528         /* TODO: make semaphores and Execlists play nicely together */
 529         if (i915.enable_execlists)
 530                 return false;
 531
 532         /* Until we get further testing... */
 533         if (IS_GEN8(dev))
 534                 return false;
 535
 536 #ifdef CONFIG_INTEL_IOMMU
 537         /* Enable semaphores on SNB when IO remapping is off */
 538         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 539                 return false;
 540 #endif
 541
 542         return true;
 543 }
 544
 545 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 546 {
 547         struct drm_device *dev = dev_priv->dev;
 548         struct intel_encoder *encoder;
 549
 550         drm_modeset_lock_all(dev);
 551         for_each_intel_encoder(dev, encoder)
 552                 if (encoder->suspend)
 553                         encoder->suspend(encoder);
 554         drm_modeset_unlock_all(dev);
 555 }
 556
 557 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
 558 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
 559                               bool rpm_resume);
 560 static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
 561
 562 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
 563 {
 564 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 565         if (acpi_target_system_state() < ACPI_STATE_S3)
 566                 return true;
 567 #endif
 568         return false;
 569 }
 570
 571 static int i915_drm_suspend(struct drm_device *dev)
 572 {
 573         struct drm_i915_private *dev_priv = dev->dev_private;
 574         pci_power_t opregion_target_state;
 575         int error;
 576
 577         /* ignore lid events during suspend */
 578         mutex_lock(&dev_priv->modeset_restore_lock);
 579         dev_priv->modeset_restore = MODESET_SUSPENDED;
 580         mutex_unlock(&dev_priv->modeset_restore_lock);
 581
 582         disable_rpm_wakeref_asserts(dev_priv);
 583
 584         /* We do a lot of poking in a lot of registers, make sure they work
 585          * properly. */
 586         intel_display_set_init_power(dev_priv, true);
 587
 588         drm_kms_helper_poll_disable(dev);
 589
 590         pci_save_state(dev->pdev);
 591
 592         error = i915_gem_suspend(dev);
 593         if (error) {
 594                 dev_err(&dev->pdev->dev,
 595                         "GEM idle failed, resume might fail\n");
 596                 goto out;
 597         }
 598
 599         intel_guc_suspend(dev);
 600
 601         intel_suspend_gt_powersave(dev);
 602
 603         /*
 604          * Disable CRTCs directly since we want to preserve sw state
 605          * for _thaw. Also, power gate the CRTC power wells.
 606          */
 607         drm_modeset_lock_all(dev);
 608         intel_display_suspend(dev);
 609         drm_modeset_unlock_all(dev);
 610
 611         intel_dp_mst_suspend(dev);
 612
 613         intel_runtime_pm_disable_interrupts(dev_priv);
 614         intel_hpd_cancel_work(dev_priv);
 615
 616         intel_suspend_encoders(dev_priv);
 617
 618         intel_suspend_hw(dev);
 619
 620         i915_gem_suspend_gtt_mappings(dev);
 621
 622         i915_save_state(dev);
 623
 624         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
 625         intel_opregion_notify_adapter(dev, opregion_target_state);
 626
 627         intel_uncore_forcewake_reset(dev, false);
 628         intel_opregion_fini(dev);
 629
 630         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 631
 632         dev_priv->suspend_count++;
 633
 634         intel_display_set_init_power(dev_priv, false);
 635
 636         if (HAS_CSR(dev_priv))
 637                 flush_work(&dev_priv->csr.work);
 638
 639 out:
 640         enable_rpm_wakeref_asserts(dev_priv);
 641
 642         return error;
 643 }
 644
 645 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
 646 {
 647         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 648         bool fw_csr;
 649         int ret;
 650
 651         disable_rpm_wakeref_asserts(dev_priv);
 652
 653         fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
 654         /*
 655          * In case of firmware assisted context save/restore don't manually
 656          * deinit the power domains. This also means the CSR/DMC firmware will
 657          * stay active, it will power down any HW resources as required and
 658          * also enable deeper system power states that would be blocked if the
 659          * firmware was inactive.
 660          */
 661         if (!fw_csr)
 662                 intel_power_domains_suspend(dev_priv);
 663
 664         ret = intel_suspend_complete(dev_priv);
 665
 666         if (ret) {
 667                 DRM_ERROR("Suspend complete failed: %d\n", ret);
 668                 if (!fw_csr)
 669                         intel_power_domains_init_hw(dev_priv, true);
 670
 671                 goto out;
 672         }
 673
 674         pci_disable_device(drm_dev->pdev);
 675         /*
 676          * During hibernation on some platforms the BIOS may try to access
 677          * the device even though it's already in D3 and hang the machine. So
 678          * leave the device in D0 on those platforms and hope the BIOS will
 679          * power down the device properly. The issue was seen on multiple old
 680          * GENs with different BIOS vendors, so having an explicit blacklist
 681          * is inpractical; apply the workaround on everything pre GEN6. The
 682          * platforms where the issue was seen:
 683          * Lenovo Thinkpad X301, X61s, X60, T60, X41
 684          * Fujitsu FSC S7110
 685          * Acer Aspire 1830T
 686          */
 687         if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
 688                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
 689
 690         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
 691
 692 out:
 693         enable_rpm_wakeref_asserts(dev_priv);
 694
 695         return ret;
 696 }
 697
 698 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
 699 {
 700         int error;
 701
 702         if (!dev || !dev->dev_private) {
 703                 DRM_ERROR("dev: %p\n", dev);
 704                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 705                 return -ENODEV;
 706         }
 707
 708         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
 709                          state.event != PM_EVENT_FREEZE))
 710                 return -EINVAL;
 711
 712         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 713                 return 0;
 714
 715         error = i915_drm_suspend(dev);
 716         if (error)
 717                 return error;
 718
 719         return i915_drm_suspend_late(dev, false);
 720 }
 721
 722 static int i915_drm_resume(struct drm_device *dev)
 723 {
 724         struct drm_i915_private *dev_priv = dev->dev_private;
 725
 726         disable_rpm_wakeref_asserts(dev_priv);
 727
 728         mutex_lock(&dev->struct_mutex);
 729         i915_gem_restore_gtt_mappings(dev);
 730         mutex_unlock(&dev->struct_mutex);
 731
 732         i915_restore_state(dev);
 733         intel_opregion_setup(dev);
 734
 735         intel_init_pch_refclk(dev);
 736         drm_mode_config_reset(dev);
 737
 738         /*
 739          * Interrupts have to be enabled before any batches are run. If not the
 740          * GPU will hang. i915_gem_init_hw() will initiate batches to
 741          * update/restore the context.
 742          *
 743          * Modeset enabling in intel_modeset_init_hw() also needs working
 744          * interrupts.
 745          */
 746         intel_runtime_pm_enable_interrupts(dev_priv);
 747
 748         mutex_lock(&dev->struct_mutex);
 749         if (i915_gem_init_hw(dev)) {
 750                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 751                         atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 752         }
 753         mutex_unlock(&dev->struct_mutex);
 754
 755         intel_guc_resume(dev);
 756
 757         intel_modeset_init_hw(dev);
 758
 759         spin_lock_irq(&dev_priv->irq_lock);
 760         if (dev_priv->display.hpd_irq_setup)
 761                 dev_priv->display.hpd_irq_setup(dev);
 762         spin_unlock_irq(&dev_priv->irq_lock);
 763
 764         drm_modeset_lock_all(dev);
 765         intel_display_resume(dev);
 766         drm_modeset_unlock_all(dev);
 767
 768         intel_dp_mst_resume(dev);
 769
 770         /*
 771          * ... but also need to make sure that hotplug processing
 772          * doesn't cause havoc. Like in the driver load code we don't
 773          * bother with the tiny race here where we might loose hotplug
 774          * notifications.
 775          * */
 776         intel_hpd_init(dev_priv);
 777         /* Config may have changed between suspend and resume */
 778         drm_helper_hpd_irq_event(dev);
 779
 780         intel_opregion_init(dev);
 781
 782         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 783
 784         mutex_lock(&dev_priv->modeset_restore_lock);
 785         dev_priv->modeset_restore = MODESET_DONE;
 786         mutex_unlock(&dev_priv->modeset_restore_lock);
 787
 788         intel_opregion_notify_adapter(dev, PCI_D0);
 789
 790         drm_kms_helper_poll_enable(dev);
 791
 792         enable_rpm_wakeref_asserts(dev_priv);
 793
 794         return 0;
 795 }
 796
 797 static int i915_drm_resume_early(struct drm_device *dev)
 798 {
 799         struct drm_i915_private *dev_priv = dev->dev_private;
 800         int ret = 0;
 801
 802         /*
 803          * We have a resume ordering issue with the snd-hda driver also
 804          * requiring our device to be power up. Due to the lack of a
 805          * parent/child relationship we currently solve this with an early
 806          * resume hook.
 807          *
 808          * FIXME: This should be solved with a special hdmi sink device or
 809          * similar so that power domains can be employed.
 810          */
 811         if (pci_enable_device(dev->pdev)) {
 812                 ret = -EIO;
 813                 goto out;
 814         }
 815
 816         pci_set_master(dev->pdev);
 817
 818         disable_rpm_wakeref_asserts(dev_priv);
 819
 820         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 821                 ret = vlv_resume_prepare(dev_priv, false);
 822         if (ret)
 823                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
 824                           ret);
 825
 826         intel_uncore_early_sanitize(dev, true);
 827
 828         if (IS_BROXTON(dev))
 829                 ret = bxt_resume_prepare(dev_priv);
 830         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 831                 hsw_disable_pc8(dev_priv);
 832
 833         intel_uncore_sanitize(dev);
 834
 835         if (!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
 836                 intel_power_domains_init_hw(dev_priv, true);
 837
 838 out:
 839         dev_priv->suspended_to_idle = false;
 840
 841         enable_rpm_wakeref_asserts(dev_priv);
 842
 843         return ret;
 844 }
 845
 846 int i915_resume_switcheroo(struct drm_device *dev)
 847 {
 848         int ret;
 849
 850         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 851                 return 0;
 852
 853         ret = i915_drm_resume_early(dev);
 854         if (ret)
 855                 return ret;
 856
 857         return i915_drm_resume(dev);
 858 }
 859
 860 /**
 861  * i915_reset - reset chip after a hang
 862  * @dev: drm device to reset
 863  *
 864  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 865  * reset or otherwise an error code.
 866  *
 867  * Procedure is fairly simple:
 868  *   - reset the chip using the reset reg
 869  *   - re-init context state
 870  *   - re-init hardware status page
 871  *   - re-init ring buffer
 872  *   - re-init interrupt state
 873  *   - re-init display
 874  */
 875 int i915_reset(struct drm_device *dev)
 876 {
 877         struct drm_i915_private *dev_priv = dev->dev_private;
 878         bool simulated;
 879         int ret;
 880
 881         intel_reset_gt_powersave(dev);
 882
 883         mutex_lock(&dev->struct_mutex);
 884
 885         i915_gem_reset(dev);
 886
 887         simulated = dev_priv->gpu_error.stop_rings != 0;
 888
 889         ret = intel_gpu_reset(dev);
 890
 891         /* Also reset the gpu hangman. */
 892         if (simulated) {
 893                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 894                 dev_priv->gpu_error.stop_rings = 0;
 895                 if (ret == -ENODEV) {
 896                         DRM_INFO("Reset not implemented, but ignoring "
 897                                  "error for simulated gpu hangs\n");
 898                         ret = 0;
 899                 }
 900         }
 901
 902         if (i915_stop_ring_allow_warn(dev_priv))
 903                 pr_notice("drm/i915: Resetting chip after gpu hang\n");
 904
 905         if (ret) {
 906                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 907                 mutex_unlock(&dev->struct_mutex);
 908                 return ret;
 909         }
 910
 911         intel_overlay_reset(dev_priv);
 912
 913         /* Ok, now get things going again... */
 914
 915         /*
 916          * Everything depends on having the GTT running, so we need to start
 917          * there.  Fortunately we don't need to do this unless we reset the
 918          * chip at a PCI level.
 919          *
 920          * Next we need to restore the context, but we don't use those
 921          * yet either...
 922          *
 923          * Ring buffer needs to be re-initialized in the KMS case, or if X
 924          * was running at the time of the reset (i.e. we weren't VT
 925          * switched away).
 926          */
 927
 928         /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
 929         dev_priv->gpu_error.reload_in_reset = true;
 930
 931         ret = i915_gem_init_hw(dev);
 932
 933         dev_priv->gpu_error.reload_in_reset = false;
 934
 935         mutex_unlock(&dev->struct_mutex);
 936         if (ret) {
 937                 DRM_ERROR("Failed hw init on reset %d\n", ret);
 938                 return ret;
 939         }
 940
 941         /*
 942          * rps/rc6 re-init is necessary to restore state lost after the
 943          * reset and the re-install of gt irqs. Skip for ironlake per
 944          * previous concerns that it doesn't respond well to some forms
 945          * of re-init after reset.
 946          */
 947         if (INTEL_INFO(dev)->gen > 5)
 948                 intel_enable_gt_powersave(dev);
 949
 950         return 0;
 951 }
 952
 953 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 954 {
 955         struct intel_device_info *intel_info =
 956                 (struct intel_device_info *) ent->driver_data;
 957
 958         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 959                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 960                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 961                 return -ENODEV;
 962         }
 963
 964         /* Only bind to function 0 of the device. Early generations
 965          * used function 1 as a placeholder for multi-head. This causes
 966          * us confusion instead, especially on the systems where both
 967          * functions have the same PCI-ID!
 968          */
 969         if (PCI_FUNC(pdev->devfn))
 970                 return -ENODEV;
 971
 972         return drm_get_pci_dev(pdev, ent, &driver);
 973 }
 974
 975 static void
 976 i915_pci_remove(struct pci_dev *pdev)
 977 {
 978         struct drm_device *dev = pci_get_drvdata(pdev);
 979
 980         drm_put_dev(dev);
 981 }
 982
 983 static int i915_pm_suspend(struct device *dev)
 984 {
 985         struct pci_dev *pdev = to_pci_dev(dev);
 986         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 987
 988         if (!drm_dev || !drm_dev->dev_private) {
 989                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 990                 return -ENODEV;
 991         }
 992
 993         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 994                 return 0;
 995
 996         return i915_drm_suspend(drm_dev);
 997 }
 998
 999 static int i915_pm_suspend_late(struct device *dev)
1000 {
1001         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1002
1003         /*
1004          * We have a suspend ordering issue with the snd-hda driver also
1005          * requiring our device to be power up. Due to the lack of a
1006          * parent/child relationship we currently solve this with an late
1007          * suspend hook.
1008          *
1009          * FIXME: This should be solved with a special hdmi sink device or
1010          * similar so that power domains can be employed.
1011          */
1012         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1013                 return 0;
1014
1015         return i915_drm_suspend_late(drm_dev, false);
1016 }
1017
1018 static int i915_pm_poweroff_late(struct device *dev)
1019 {
1020         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1021
1022         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1023                 return 0;
1024
1025         return i915_drm_suspend_late(drm_dev, true);
1026 }
1027
1028 static int i915_pm_resume_early(struct device *dev)
1029 {
1030         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1031
1032         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1033                 return 0;
1034
1035         return i915_drm_resume_early(drm_dev);
1036 }
1037
1038 static int i915_pm_resume(struct device *dev)
1039 {
1040         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1041
1042         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1043                 return 0;
1044
1045         return i915_drm_resume(drm_dev);
1046 }
1047
1048 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1049 {
1050         hsw_enable_pc8(dev_priv);
1051
1052         return 0;
1053 }
1054
1055 static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
1056 {
1057         struct drm_device *dev = dev_priv->dev;
1058
1059         /* TODO: when DC5 support is added disable DC5 here. */
1060
1061         broxton_ddi_phy_uninit(dev);
1062         broxton_uninit_cdclk(dev);
1063         bxt_enable_dc9(dev_priv);
1064
1065         return 0;
1066 }
1067
1068 static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
1069 {
1070         struct drm_device *dev = dev_priv->dev;
1071
1072         /* TODO: when CSR FW support is added make sure the FW is loaded */
1073
1074         bxt_disable_dc9(dev_priv);
1075
1076         /*
1077          * TODO: when DC5 support is added enable DC5 here if the CSR FW
1078          * is available.
1079          */
1080         broxton_init_cdclk(dev);
1081         broxton_ddi_phy_init(dev);
1082         intel_prepare_ddi(dev);
1083
1084         return 0;
1085 }
1086
1087 /*
1088  * Save all Gunit registers that may be lost after a D3 and a subsequent
1089  * S0i[R123] transition. The list of registers needing a save/restore is
1090  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1091  * registers in the following way:
1092  * - Driver: saved/restored by the driver
1093  * - Punit : saved/restored by the Punit firmware
1094  * - No, w/o marking: no need to save/restore, since the register is R/O or
1095  *                    used internally by the HW in a way that doesn't depend
1096  *                    keeping the content across a suspend/resume.
1097  * - Debug : used for debugging
1098  *
1099  * We save/restore all registers marked with 'Driver', with the following
1100  * exceptions:
1101  * - Registers out of use, including also registers marked with 'Debug'.
1102  *   These have no effect on the driver's operation, so we don't save/restore
1103  *   them to reduce the overhead.
1104  * - Registers that are fully setup by an initialization function called from
1105  *   the resume path. For example many clock gating and RPS/RC6 registers.
1106  * - Registers that provide the right functionality with their reset defaults.
1107  *
1108  * TODO: Except for registers that based on the above 3 criteria can be safely
1109  * ignored, we save/restore all others, practically treating the HW context as
1110  * a black-box for the driver. Further investigation is needed to reduce the
1111  * saved/restored registers even further, by following the same 3 criteria.
1112  */
1113 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1114 {
1115         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1116         int i;
1117
1118         /* GAM 0x4000-0x4770 */
1119         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1120         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1121         s->arb_mode             = I915_READ(ARB_MODE);
1122         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1123         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1124
1125         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1126                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1127
1128         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1129         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1130
1131         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1132         s->ecochk               = I915_READ(GAM_ECOCHK);
1133         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1134         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1135
1136         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1137
1138         /* MBC 0x9024-0x91D0, 0x8500 */
1139         s->g3dctl               = I915_READ(VLV_G3DCTL);
1140         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1141         s->mbctl                = I915_READ(GEN6_MBCTL);
1142
1143         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1144         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1145         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1146         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1147         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1148         s->rstctl               = I915_READ(GEN6_RSTCTL);
1149         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1150
1151         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1152         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1153         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1154         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1155         s->ecobus               = I915_READ(ECOBUS);
1156         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1157         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1158         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1159         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1160         s->rcedata              = I915_READ(VLV_RCEDATA);
1161         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1162
1163         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1164         s->gt_imr               = I915_READ(GTIMR);
1165         s->gt_ier               = I915_READ(GTIER);
1166         s->pm_imr               = I915_READ(GEN6_PMIMR);
1167         s->pm_ier               = I915_READ(GEN6_PMIER);
1168
1169         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1170                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
1171
1172         /* GT SA CZ domain, 0x100000-0x138124 */
1173         s->tilectl              = I915_READ(TILECTL);
1174         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1175         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1176         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1177         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1178
1179         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1180         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1181         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1182         s->pcbr                 = I915_READ(VLV_PCBR);
1183         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1184
1185         /*
1186          * Not saving any of:
1187          * DFT,         0x9800-0x9EC0
1188          * SARB,        0xB000-0xB1FC
1189          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1190          * PCI CFG
1191          */
1192 }
1193
1194 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1195 {
1196         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1197         u32 val;
1198         int i;
1199
1200         /* GAM 0x4000-0x4770 */
1201         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1202         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1203         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1204         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1205         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1206
1207         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1208                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
1209
1210         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1211         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1212
1213         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1214         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1215         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1216         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1217
1218         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1219
1220         /* MBC 0x9024-0x91D0, 0x8500 */
1221         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1222         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1223         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1224
1225         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1226         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1227         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1228         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1229         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1230         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1231         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1232
1233         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1234         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1235         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1236         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1237         I915_WRITE(ECOBUS,              s->ecobus);
1238         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1239         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1240         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1241         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1242         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1243         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1244
1245         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1246         I915_WRITE(GTIMR,               s->gt_imr);
1247         I915_WRITE(GTIER,               s->gt_ier);
1248         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1249         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1250
1251         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1252                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
1253
1254         /* GT SA CZ domain, 0x100000-0x138124 */
1255         I915_WRITE(TILECTL,                     s->tilectl);
1256         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1257         /*
1258          * Preserve the GT allow wake and GFX force clock bit, they are not
1259          * be restored, as they are used to control the s0ix suspend/resume
1260          * sequence by the caller.
1261          */
1262         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1263         val &= VLV_GTLC_ALLOWWAKEREQ;
1264         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1265         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1266
1267         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1268         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1269         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1270         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1271
1272         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1273
1274         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1275         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1276         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1277         I915_WRITE(VLV_PCBR,                    s->pcbr);
1278         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1279 }
1280
1281 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1282 {
1283         u32 val;
1284         int err;
1285
1286 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1287
1288         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1289         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1290         if (force_on)
1291                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1292         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1293
1294         if (!force_on)
1295                 return 0;
1296
1297         err = wait_for(COND, 20);
1298         if (err)
1299                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1300                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1301
1302         return err;
1303 #undef COND
1304 }
1305
1306 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1307 {
1308         u32 val;
1309         int err = 0;
1310
1311         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1312         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1313         if (allow)
1314                 val |= VLV_GTLC_ALLOWWAKEREQ;
1315         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1316         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1317
1318 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1319               allow)
1320         err = wait_for(COND, 1);
1321         if (err)
1322                 DRM_ERROR("timeout disabling GT waking\n");
1323         return err;
1324 #undef COND
1325 }
1326
1327 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1328                                  bool wait_for_on)
1329 {
1330         u32 mask;
1331         u32 val;
1332         int err;
1333
1334         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1335         val = wait_for_on ? mask : 0;
1336 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1337         if (COND)
1338                 return 0;
1339
1340         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1341                         wait_for_on ? "on" : "off",
1342                         I915_READ(VLV_GTLC_PW_STATUS));
1343
1344         /*
1345          * RC6 transitioning can be delayed up to 2 msec (see
1346          * valleyview_enable_rps), use 3 msec for safety.
1347          */
1348         err = wait_for(COND, 3);
1349         if (err)
1350                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1351                           wait_for_on ? "on" : "off");
1352
1353         return err;
1354 #undef COND
1355 }
1356
1357 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1358 {
1359         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1360                 return;
1361
1362         DRM_ERROR("GT register access while GT waking disabled\n");
1363         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1364 }
1365
1366 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1367 {
1368         u32 mask;
1369         int err;
1370
1371         /*
1372          * Bspec defines the following GT well on flags as debug only, so
1373          * don't treat them as hard failures.
1374          */
1375         (void)vlv_wait_for_gt_wells(dev_priv, false);
1376
1377         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1378         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1379
1380         vlv_check_no_gt_access(dev_priv);
1381
1382         err = vlv_force_gfx_clock(dev_priv, true);
1383         if (err)
1384                 goto err1;
1385
1386         err = vlv_allow_gt_wake(dev_priv, false);
1387         if (err)
1388                 goto err2;
1389
1390         if (!IS_CHERRYVIEW(dev_priv->dev))
1391                 vlv_save_gunit_s0ix_state(dev_priv);
1392
1393         err = vlv_force_gfx_clock(dev_priv, false);
1394         if (err)
1395                 goto err2;
1396
1397         return 0;
1398
1399 err2:
1400         /* For safety always re-enable waking and disable gfx clock forcing */
1401         vlv_allow_gt_wake(dev_priv, true);
1402 err1:
1403         vlv_force_gfx_clock(dev_priv, false);
1404
1405         return err;
1406 }
1407
1408 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1409                                 bool rpm_resume)
1410 {
1411         struct drm_device *dev = dev_priv->dev;
1412         int err;
1413         int ret;
1414
1415         /*
1416          * If any of the steps fail just try to continue, that's the best we
1417          * can do at this point. Return the first error code (which will also
1418          * leave RPM permanently disabled).
1419          */
1420         ret = vlv_force_gfx_clock(dev_priv, true);
1421
1422         if (!IS_CHERRYVIEW(dev_priv->dev))
1423                 vlv_restore_gunit_s0ix_state(dev_priv);
1424
1425         err = vlv_allow_gt_wake(dev_priv, true);
1426         if (!ret)
1427                 ret = err;
1428
1429         err = vlv_force_gfx_clock(dev_priv, false);
1430         if (!ret)
1431                 ret = err;
1432
1433         vlv_check_no_gt_access(dev_priv);
1434
1435         if (rpm_resume) {
1436                 intel_init_clock_gating(dev);
1437                 i915_gem_restore_fences(dev);
1438         }
1439
1440         return ret;
1441 }
1442
1443 static int intel_runtime_suspend(struct device *device)
1444 {
1445         struct pci_dev *pdev = to_pci_dev(device);
1446         struct drm_device *dev = pci_get_drvdata(pdev);
1447         struct drm_i915_private *dev_priv = dev->dev_private;
1448         int ret;
1449
1450         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1451                 return -ENODEV;
1452
1453         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1454                 return -ENODEV;
1455
1456         DRM_DEBUG_KMS("Suspending device\n");
1457
1458         /*
1459          * We could deadlock here in case another thread holding struct_mutex
1460          * calls RPM suspend concurrently, since the RPM suspend will wait
1461          * first for this RPM suspend to finish. In this case the concurrent
1462          * RPM resume will be followed by its RPM suspend counterpart. Still
1463          * for consistency return -EAGAIN, which will reschedule this suspend.
1464          */
1465         if (!mutex_trylock(&dev->struct_mutex)) {
1466                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1467                 /*
1468                  * Bump the expiration timestamp, otherwise the suspend won't
1469                  * be rescheduled.
1470                  */
1471                 pm_runtime_mark_last_busy(device);
1472
1473                 return -EAGAIN;
1474         }
1475
1476         disable_rpm_wakeref_asserts(dev_priv);
1477
1478         /*
1479          * We are safe here against re-faults, since the fault handler takes
1480          * an RPM reference.
1481          */
1482         i915_gem_release_all_mmaps(dev_priv);
1483         mutex_unlock(&dev->struct_mutex);
1484
1485         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1486
1487         intel_guc_suspend(dev);
1488
1489         intel_suspend_gt_powersave(dev);
1490         intel_runtime_pm_disable_interrupts(dev_priv);
1491
1492         ret = intel_suspend_complete(dev_priv);
1493         if (ret) {
1494                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1495                 intel_runtime_pm_enable_interrupts(dev_priv);
1496
1497                 enable_rpm_wakeref_asserts(dev_priv);
1498
1499                 return ret;
1500         }
1501
1502         intel_uncore_forcewake_reset(dev, false);
1503
1504         enable_rpm_wakeref_asserts(dev_priv);
1505         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1506         dev_priv->pm.suspended = true;
1507
1508         /*
1509          * FIXME: We really should find a document that references the arguments
1510          * used below!
1511          */
1512         if (IS_BROADWELL(dev)) {
1513                 /*
1514                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1515                  * being detected, and the call we do at intel_runtime_resume()
1516                  * won't be able to restore them. Since PCI_D3hot matches the
1517                  * actual specification and appears to be working, use it.
1518                  */
1519                 intel_opregion_notify_adapter(dev, PCI_D3hot);
1520         } else {
1521                 /*
1522                  * current versions of firmware which depend on this opregion
1523                  * notification have repurposed the D1 definition to mean
1524                  * "runtime suspended" vs. what you would normally expect (D3)
1525                  * to distinguish it from notifications that might be sent via
1526                  * the suspend path.
1527                  */
1528                 intel_opregion_notify_adapter(dev, PCI_D1);
1529         }
1530
1531         assert_forcewakes_inactive(dev_priv);
1532
1533         DRM_DEBUG_KMS("Device suspended\n");
1534         return 0;
1535 }
1536
1537 static int intel_runtime_resume(struct device *device)
1538 {
1539         struct pci_dev *pdev = to_pci_dev(device);
1540         struct drm_device *dev = pci_get_drvdata(pdev);
1541         struct drm_i915_private *dev_priv = dev->dev_private;
1542         int ret = 0;
1543
1544         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1545                 return -ENODEV;
1546
1547         DRM_DEBUG_KMS("Resuming device\n");
1548
1549         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1550         disable_rpm_wakeref_asserts(dev_priv);
1551
1552         intel_opregion_notify_adapter(dev, PCI_D0);
1553         dev_priv->pm.suspended = false;
1554
1555         intel_guc_resume(dev);
1556
1557         if (IS_GEN6(dev_priv))
1558                 intel_init_pch_refclk(dev);
1559
1560         if (IS_BROXTON(dev))
1561                 ret = bxt_resume_prepare(dev_priv);
1562         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1563                 hsw_disable_pc8(dev_priv);
1564         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1565                 ret = vlv_resume_prepare(dev_priv, true);
1566
1567         /*
1568          * No point of rolling back things in case of an error, as the best
1569          * we can do is to hope that things will still work (and disable RPM).
1570          */
1571         i915_gem_init_swizzling(dev);
1572         gen6_update_ring_freq(dev);
1573
1574         intel_runtime_pm_enable_interrupts(dev_priv);
1575
1576         /*
1577          * On VLV/CHV display interrupts are part of the display
1578          * power well, so hpd is reinitialized from there. For
1579          * everyone else do it here.
1580          */
1581         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1582                 intel_hpd_init(dev_priv);
1583
1584         intel_enable_gt_powersave(dev);
1585
1586         enable_rpm_wakeref_asserts(dev_priv);
1587
1588         if (ret)
1589                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1590         else
1591                 DRM_DEBUG_KMS("Device resumed\n");
1592
1593         return ret;
1594 }
1595
1596 /*
1597  * This function implements common functionality of runtime and system
1598  * suspend sequence.
1599  */
1600 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1601 {
1602         int ret;
1603
1604         if (IS_BROXTON(dev_priv))
1605                 ret = bxt_suspend_complete(dev_priv);
1606         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1607                 ret = hsw_suspend_complete(dev_priv);
1608         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1609                 ret = vlv_suspend_complete(dev_priv);
1610         else
1611                 ret = 0;
1612
1613         return ret;
1614 }
1615
1616 static const struct dev_pm_ops i915_pm_ops = {
1617         /*
1618          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1619          * PMSG_RESUME]
1620          */
1621         .suspend = i915_pm_suspend,
1622         .suspend_late = i915_pm_suspend_late,
1623         .resume_early = i915_pm_resume_early,
1624         .resume = i915_pm_resume,
1625
1626         /*
1627          * S4 event handlers
1628          * @freeze, @freeze_late    : called (1) before creating the
1629          *                            hibernation image [PMSG_FREEZE] and
1630          *                            (2) after rebooting, before restoring
1631          *                            the image [PMSG_QUIESCE]
1632          * @thaw, @thaw_early       : called (1) after creating the hibernation
1633          *                            image, before writing it [PMSG_THAW]
1634          *                            and (2) after failing to create or
1635          *                            restore the image [PMSG_RECOVER]
1636          * @poweroff, @poweroff_late: called after writing the hibernation
1637          *                            image, before rebooting [PMSG_HIBERNATE]
1638          * @restore, @restore_early : called after rebooting and restoring the
1639          *                            hibernation image [PMSG_RESTORE]
1640          */
1641         .freeze = i915_pm_suspend,
1642         .freeze_late = i915_pm_suspend_late,
1643         .thaw_early = i915_pm_resume_early,
1644         .thaw = i915_pm_resume,
1645         .poweroff = i915_pm_suspend,
1646         .poweroff_late = i915_pm_poweroff_late,
1647         .restore_early = i915_pm_resume_early,
1648         .restore = i915_pm_resume,
1649
1650         /* S0ix (via runtime suspend) event handlers */
1651         .runtime_suspend = intel_runtime_suspend,
1652         .runtime_resume = intel_runtime_resume,
1653 };
1654
1655 static const struct vm_operations_struct i915_gem_vm_ops = {
1656         .fault = i915_gem_fault,
1657         .open = drm_gem_vm_open,
1658         .close = drm_gem_vm_close,
1659 };
1660
1661 static const struct file_operations i915_driver_fops = {
1662         .owner = THIS_MODULE,
1663         .open = drm_open,
1664         .release = drm_release,
1665         .unlocked_ioctl = drm_ioctl,
1666         .mmap = drm_gem_mmap,
1667         .poll = drm_poll,
1668         .read = drm_read,
1669 #ifdef CONFIG_COMPAT
1670         .compat_ioctl = i915_compat_ioctl,
1671 #endif
1672         .llseek = noop_llseek,
1673 };
1674
1675 static struct drm_driver driver = {
1676         /* Don't use MTRRs here; the Xserver or userspace app should
1677          * deal with them for Intel hardware.
1678          */
1679         .driver_features =
1680             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1681             DRIVER_RENDER | DRIVER_MODESET,
1682         .load = i915_driver_load,
1683         .unload = i915_driver_unload,
1684         .open = i915_driver_open,
1685         .lastclose = i915_driver_lastclose,
1686         .preclose = i915_driver_preclose,
1687         .postclose = i915_driver_postclose,
1688         .set_busid = drm_pci_set_busid,
1689
1690 #if defined(CONFIG_DEBUG_FS)
1691         .debugfs_init = i915_debugfs_init,
1692         .debugfs_cleanup = i915_debugfs_cleanup,
1693 #endif
1694         .gem_free_object = i915_gem_free_object,
1695         .gem_vm_ops = &i915_gem_vm_ops,
1696
1697         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1698         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1699         .gem_prime_export = i915_gem_prime_export,
1700         .gem_prime_import = i915_gem_prime_import,
1701
1702         .dumb_create = i915_gem_dumb_create,
1703         .dumb_map_offset = i915_gem_mmap_gtt,
1704         .dumb_destroy = drm_gem_dumb_destroy,
1705         .ioctls = i915_ioctls,
1706         .fops = &i915_driver_fops,
1707         .name = DRIVER_NAME,
1708         .desc = DRIVER_DESC,
1709         .date = DRIVER_DATE,
1710         .major = DRIVER_MAJOR,
1711         .minor = DRIVER_MINOR,
1712         .patchlevel = DRIVER_PATCHLEVEL,
1713 };
1714
1715 static struct pci_driver i915_pci_driver = {
1716         .name = DRIVER_NAME,
1717         .id_table = pciidlist,
1718         .probe = i915_pci_probe,
1719         .remove = i915_pci_remove,
1720         .driver.pm = &i915_pm_ops,
1721 };
1722
1723 static int __init i915_init(void)
1724 {
1725         driver.num_ioctls = i915_max_ioctl;
1726
1727         /*
1728          * Enable KMS by default, unless explicitly overriden by
1729          * either the i915.modeset prarameter or by the
1730          * vga_text_mode_force boot option.
1731          */
1732
1733         if (i915.modeset == 0)
1734                 driver.driver_features &= ~DRIVER_MODESET;
1735
1736 #ifdef CONFIG_VGA_CONSOLE
1737         if (vgacon_text_force() && i915.modeset == -1)
1738                 driver.driver_features &= ~DRIVER_MODESET;
1739 #endif
1740
1741         if (!(driver.driver_features & DRIVER_MODESET)) {
1742                 /* Silently fail loading to not upset userspace. */
1743                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1744                 return 0;
1745         }
1746
1747         if (i915.nuclear_pageflip)
1748                 driver.driver_features |= DRIVER_ATOMIC;
1749
1750         return drm_pci_init(&driver, &i915_pci_driver);
1751 }
1752
1753 static void __exit i915_exit(void)
1754 {
1755         if (!(driver.driver_features & DRIVER_MODESET))
1756                 return; /* Never loaded a driver. */
1757
1758         drm_pci_exit(&driver, &i915_pci_driver);
1759 }
1760
1761 module_init(i915_init);
1762 module_exit(i915_exit);
1763
1764 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1765 MODULE_AUTHOR("Intel Corporation");
1766
1767 MODULE_DESCRIPTION(DRIVER_DESC);
1768 MODULE_LICENSE("GPL and additional rights");