1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "i915_params.h"
39 #include "intel_bios.h"
40 #include "intel_ringbuffer.h"
41 #include "intel_lrc.h"
42 #include "i915_gem_gtt.h"
43 #include "i915_gem_render_state.h"
44 #include <linux/io-mapping.h>
45 #include <linux/i2c.h>
46 #include <linux/i2c-algo-bit.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <linux/backlight.h>
51 #include <linux/hashtable.h>
52 #include <linux/intel-iommu.h>
53 #include <linux/kref.h>
54 #include <linux/pm_qos.h>
55 #include "intel_guc.h"
56 #include "intel_dpll_mgr.h"
58 /* General customization:
61 #define DRIVER_NAME "i915"
62 #define DRIVER_DESC "Intel Graphics"
63 #define DRIVER_DATE "20160314"
66 /* Many gcc seem to no see through this and fall over :( */
68 #define WARN_ON(x) ({ \
69 bool __i915_warn_cond = (x); \
70 if (__builtin_constant_p(__i915_warn_cond)) \
71 BUILD_BUG_ON(__i915_warn_cond); \
72 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
74 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
78 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
80 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
81 (long) (x), __func__);
83 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
84 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
85 * which may not necessarily be a user visible problem. This will either
86 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
87 * enable distros and users to tailor their preferred amount of i915 abrt
90 #define I915_STATE_WARN(condition, format...) ({ \
91 int __ret_warn_on = !!(condition); \
92 if (unlikely(__ret_warn_on)) \
93 if (!WARN(i915.verbose_state_checks, format)) \
95 unlikely(__ret_warn_on); \
98 #define I915_STATE_WARN_ON(x) \
99 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
101 static inline const char *yesno(bool v)
103 return v ? "yes" : "no";
106 static inline const char *onoff(bool v)
108 return v ? "on" : "off";
117 I915_MAX_PIPES = _PIPE_EDP
119 #define pipe_name(p) ((p) + 'A')
128 #define transcoder_name(t) ((t) + 'A')
131 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
132 * number of planes per CRTC. Not all platforms really have this many planes,
133 * which means some arrays of size I915_MAX_PLANES may have unused entries
134 * between the topmost sprite plane and the cursor plane.
143 #define plane_name(p) ((p) + 'A')
145 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
155 #define port_name(p) ((p) + 'A')
157 #define I915_NUM_PHYS_VLV 2
169 enum intel_display_power_domain {
173 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
174 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
175 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
176 POWER_DOMAIN_TRANSCODER_A,
177 POWER_DOMAIN_TRANSCODER_B,
178 POWER_DOMAIN_TRANSCODER_C,
179 POWER_DOMAIN_TRANSCODER_EDP,
180 POWER_DOMAIN_PORT_DDI_A_LANES,
181 POWER_DOMAIN_PORT_DDI_B_LANES,
182 POWER_DOMAIN_PORT_DDI_C_LANES,
183 POWER_DOMAIN_PORT_DDI_D_LANES,
184 POWER_DOMAIN_PORT_DDI_E_LANES,
185 POWER_DOMAIN_PORT_DSI,
186 POWER_DOMAIN_PORT_CRT,
187 POWER_DOMAIN_PORT_OTHER,
196 POWER_DOMAIN_MODESET,
202 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
203 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
204 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
205 #define POWER_DOMAIN_TRANSCODER(tran) \
206 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
207 (tran) + POWER_DOMAIN_TRANSCODER_A)
211 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
223 #define for_each_hpd_pin(__pin) \
224 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
226 struct i915_hotplug {
227 struct work_struct hotplug_work;
230 unsigned long last_jiffies;
235 HPD_MARK_DISABLED = 2
237 } stats[HPD_NUM_PINS];
239 struct delayed_work reenable_work;
241 struct intel_digital_port *irq_port[I915_MAX_PORTS];
244 struct work_struct dig_port_work;
247 * if we get a HPD irq from DP and a HPD irq from non-DP
248 * the non-DP HPD could block the workqueue on a mode config
249 * mutex getting, that userspace may have taken. However
250 * userspace is waiting on the DP workqueue to run which is
251 * blocked behind the non-DP one.
253 struct workqueue_struct *dp_wq;
256 #define I915_GEM_GPU_DOMAINS \
257 (I915_GEM_DOMAIN_RENDER | \
258 I915_GEM_DOMAIN_SAMPLER | \
259 I915_GEM_DOMAIN_COMMAND | \
260 I915_GEM_DOMAIN_INSTRUCTION | \
261 I915_GEM_DOMAIN_VERTEX)
263 #define for_each_pipe(__dev_priv, __p) \
264 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
265 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
266 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
267 for_each_if ((__mask) & (1 << (__p)))
268 #define for_each_plane(__dev_priv, __pipe, __p) \
270 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
272 #define for_each_sprite(__dev_priv, __p, __s) \
274 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
277 #define for_each_crtc(dev, crtc) \
278 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
280 #define for_each_intel_plane(dev, intel_plane) \
281 list_for_each_entry(intel_plane, \
282 &dev->mode_config.plane_list, \
285 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
286 list_for_each_entry(intel_plane, \
287 &(dev)->mode_config.plane_list, \
289 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
291 #define for_each_intel_crtc(dev, intel_crtc) \
292 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
294 #define for_each_intel_encoder(dev, intel_encoder) \
295 list_for_each_entry(intel_encoder, \
296 &(dev)->mode_config.encoder_list, \
299 #define for_each_intel_connector(dev, intel_connector) \
300 list_for_each_entry(intel_connector, \
301 &dev->mode_config.connector_list, \
304 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
305 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
306 for_each_if ((intel_encoder)->base.crtc == (__crtc))
308 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
309 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
310 for_each_if ((intel_connector)->base.encoder == (__encoder))
312 #define for_each_power_domain(domain, mask) \
313 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
314 for_each_if ((1 << (domain)) & (mask))
316 struct drm_i915_private;
317 struct i915_mm_struct;
318 struct i915_mmu_object;
320 struct drm_i915_file_private {
321 struct drm_i915_private *dev_priv;
322 struct drm_file *file;
326 struct list_head request_list;
327 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
328 * chosen to prevent the CPU getting more than a frame ahead of the GPU
329 * (when using lax throttling for the frontbuffer). We also use it to
330 * offer free GPU waitboosts for severely congested workloads.
332 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
334 struct idr context_idr;
336 struct intel_rps_client {
337 struct list_head link;
341 unsigned int bsd_ring;
344 /* Used by dp and fdi links */
345 struct intel_link_m_n {
353 void intel_link_compute_m_n(int bpp, int nlanes,
354 int pixel_clock, int link_clock,
355 struct intel_link_m_n *m_n);
357 /* Interface history:
360 * 1.2: Add Power Management
361 * 1.3: Add vblank support
362 * 1.4: Fix cmdbuffer path, add heap destroy
363 * 1.5: Add vblank pipe configuration
364 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
365 * - Support vertical blank on secondary display pipe
367 #define DRIVER_MAJOR 1
368 #define DRIVER_MINOR 6
369 #define DRIVER_PATCHLEVEL 0
371 #define WATCH_LISTS 0
373 struct opregion_header;
374 struct opregion_acpi;
375 struct opregion_swsci;
376 struct opregion_asle;
378 struct intel_opregion {
379 struct opregion_header *header;
380 struct opregion_acpi *acpi;
381 struct opregion_swsci *swsci;
382 u32 swsci_gbda_sub_functions;
383 u32 swsci_sbcb_sub_functions;
384 struct opregion_asle *asle;
389 struct work_struct asle_work;
391 #define OPREGION_SIZE (8*1024)
393 struct intel_overlay;
394 struct intel_overlay_error_state;
396 #define I915_FENCE_REG_NONE -1
397 #define I915_MAX_NUM_FENCES 32
398 /* 32 fences + sign bit for FENCE_REG_NONE */
399 #define I915_MAX_NUM_FENCE_BITS 6
401 struct drm_i915_fence_reg {
402 struct list_head lru_list;
403 struct drm_i915_gem_object *obj;
407 struct sdvo_device_mapping {
416 struct intel_display_error_state;
418 struct drm_i915_error_state {
427 /* Generic register state */
435 u32 error; /* gen6+ */
436 u32 err_int; /* gen7 */
437 u32 fault_data0; /* gen8, gen9 */
438 u32 fault_data1; /* gen8, gen9 */
444 u32 extra_instdone[I915_NUM_INSTDONE_REG];
445 u64 fence[I915_MAX_NUM_FENCES];
446 struct intel_overlay_error_state *overlay;
447 struct intel_display_error_state *display;
448 struct drm_i915_error_object *semaphore_obj;
450 struct drm_i915_error_ring {
452 /* Software tracked state */
455 enum intel_ring_hangcheck_action hangcheck_action;
458 /* our own tracking of ring head and tail */
462 u32 semaphore_seqno[I915_NUM_RINGS - 1];
481 u32 rc_psmi; /* sleep state */
482 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
484 struct drm_i915_error_object {
488 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
490 struct drm_i915_error_object *wa_ctx;
492 struct drm_i915_error_request {
507 char comm[TASK_COMM_LEN];
508 } ring[I915_NUM_RINGS];
510 struct drm_i915_error_buffer {
513 u32 rseqno[I915_NUM_RINGS], wseqno;
517 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
525 } **active_bo, **pinned_bo;
527 u32 *active_bo_count, *pinned_bo_count;
531 struct intel_connector;
532 struct intel_encoder;
533 struct intel_crtc_state;
534 struct intel_initial_plane_config;
539 struct drm_i915_display_funcs {
540 int (*get_display_clock_speed)(struct drm_device *dev);
541 int (*get_fifo_size)(struct drm_device *dev, int plane);
543 * find_dpll() - Find the best values for the PLL
544 * @limit: limits for the PLL
545 * @crtc: current CRTC
546 * @target: target frequency in kHz
547 * @refclk: reference clock frequency in kHz
548 * @match_clock: if provided, @best_clock P divider must
549 * match the P divider from @match_clock
550 * used for LVDS downclocking
551 * @best_clock: best PLL values found
553 * Returns true on success, false on failure.
555 bool (*find_dpll)(const struct intel_limit *limit,
556 struct intel_crtc_state *crtc_state,
557 int target, int refclk,
558 struct dpll *match_clock,
559 struct dpll *best_clock);
560 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
561 int (*compute_intermediate_wm)(struct drm_device *dev,
562 struct intel_crtc *intel_crtc,
563 struct intel_crtc_state *newstate);
564 void (*initial_watermarks)(struct intel_crtc_state *cstate);
565 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
566 void (*update_wm)(struct drm_crtc *crtc);
567 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
568 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
569 /* Returns the active state of the crtc, and if the crtc is active,
570 * fills out the pipe-config with the hw state. */
571 bool (*get_pipe_config)(struct intel_crtc *,
572 struct intel_crtc_state *);
573 void (*get_initial_plane_config)(struct intel_crtc *,
574 struct intel_initial_plane_config *);
575 int (*crtc_compute_clock)(struct intel_crtc *crtc,
576 struct intel_crtc_state *crtc_state);
577 void (*crtc_enable)(struct drm_crtc *crtc);
578 void (*crtc_disable)(struct drm_crtc *crtc);
579 void (*audio_codec_enable)(struct drm_connector *connector,
580 struct intel_encoder *encoder,
581 const struct drm_display_mode *adjusted_mode);
582 void (*audio_codec_disable)(struct intel_encoder *encoder);
583 void (*fdi_link_train)(struct drm_crtc *crtc);
584 void (*init_clock_gating)(struct drm_device *dev);
585 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
586 struct drm_framebuffer *fb,
587 struct drm_i915_gem_object *obj,
588 struct drm_i915_gem_request *req,
590 void (*hpd_irq_setup)(struct drm_device *dev);
591 /* clock updates for mode set */
593 /* render clock increase/decrease */
594 /* display clock increase/decrease */
595 /* pll clock increase/decrease */
598 enum forcewake_domain_id {
599 FW_DOMAIN_ID_RENDER = 0,
600 FW_DOMAIN_ID_BLITTER,
606 enum forcewake_domains {
607 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
608 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
609 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
610 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
615 struct intel_uncore_funcs {
616 void (*force_wake_get)(struct drm_i915_private *dev_priv,
617 enum forcewake_domains domains);
618 void (*force_wake_put)(struct drm_i915_private *dev_priv,
619 enum forcewake_domains domains);
621 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
622 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
623 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
624 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
626 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
627 uint8_t val, bool trace);
628 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
629 uint16_t val, bool trace);
630 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
631 uint32_t val, bool trace);
632 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
633 uint64_t val, bool trace);
636 struct intel_uncore {
637 spinlock_t lock; /** lock is also taken in irq contexts. */
639 struct intel_uncore_funcs funcs;
642 enum forcewake_domains fw_domains;
644 struct intel_uncore_forcewake_domain {
645 struct drm_i915_private *i915;
646 enum forcewake_domain_id id;
648 struct timer_list timer;
655 } fw_domain[FW_DOMAIN_ID_COUNT];
657 int unclaimed_mmio_check;
660 /* Iterate over initialised fw domains */
661 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
662 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
663 (i__) < FW_DOMAIN_ID_COUNT; \
664 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
665 for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
667 #define for_each_fw_domain(domain__, dev_priv__, i__) \
668 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
670 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
671 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
672 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
675 struct work_struct work;
677 uint32_t *dmc_payload;
678 uint32_t dmc_fw_size;
681 i915_reg_t mmioaddr[8];
682 uint32_t mmiodata[8];
684 uint32_t allowed_dc_mask;
687 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
688 func(is_mobile) sep \
691 func(is_i945gm) sep \
693 func(need_gfx_hws) sep \
695 func(is_pineview) sep \
696 func(is_broadwater) sep \
697 func(is_crestline) sep \
698 func(is_ivybridge) sep \
699 func(is_valleyview) sep \
700 func(is_cherryview) sep \
701 func(is_haswell) sep \
702 func(is_skylake) sep \
703 func(is_broxton) sep \
704 func(is_kabylake) sep \
705 func(is_preliminary) sep \
707 func(has_pipe_cxsr) sep \
708 func(has_hotplug) sep \
709 func(cursor_needs_physical) sep \
710 func(has_overlay) sep \
711 func(overlay_needs_physical) sep \
712 func(supports_tv) sep \
714 func(has_snoop) sep \
718 #define DEFINE_FLAG(name) u8 name:1
719 #define SEP_SEMICOLON ;
721 struct intel_device_info {
722 u32 display_mmio_offset;
725 u8 num_sprites[I915_MAX_PIPES];
727 u8 ring_mask; /* Rings supported by the HW */
728 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
729 /* Register offsets for the various display pipes and transcoders */
730 int pipe_offsets[I915_MAX_TRANSCODERS];
731 int trans_offsets[I915_MAX_TRANSCODERS];
732 int palette_offsets[I915_MAX_PIPES];
733 int cursor_offsets[I915_MAX_PIPES];
735 /* Slice/subslice/EU info */
738 u8 subslice_per_slice;
741 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
744 u8 has_subslice_pg:1;
751 enum i915_cache_level {
753 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
754 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
755 caches, eg sampler/render caches, and the
756 large Last-Level-Cache. LLC is coherent with
757 the CPU, but L3 is only visible to the GPU. */
758 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
761 struct i915_ctx_hang_stats {
762 /* This context had batch pending when hang was declared */
763 unsigned batch_pending;
765 /* This context had batch active when hang was declared */
766 unsigned batch_active;
768 /* Time when this context was last blamed for a GPU reset */
769 unsigned long guilty_ts;
771 /* If the contexts causes a second GPU hang within this time,
772 * it is permanently banned from submitting any more work.
774 unsigned long ban_period_seconds;
776 /* This context is banned to submit more work */
780 /* This must match up with the value previously used for execbuf2.rsvd1. */
781 #define DEFAULT_CONTEXT_HANDLE 0
783 #define CONTEXT_NO_ZEROMAP (1<<0)
785 * struct intel_context - as the name implies, represents a context.
786 * @ref: reference count.
787 * @user_handle: userspace tracking identity for this context.
788 * @remap_slice: l3 row remapping information.
789 * @flags: context specific flags:
790 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
791 * @file_priv: filp associated with this context (NULL for global default
793 * @hang_stats: information about the role of this context in possible GPU
795 * @ppgtt: virtual memory space used by this context.
796 * @legacy_hw_ctx: render context backing object and whether it is correctly
797 * initialized (legacy ring submission mechanism only).
798 * @link: link in the global list of contexts.
800 * Contexts are memory images used by the hardware to store copies of their
803 struct intel_context {
807 struct drm_i915_private *i915;
809 struct drm_i915_file_private *file_priv;
810 struct i915_ctx_hang_stats hang_stats;
811 struct i915_hw_ppgtt *ppgtt;
813 /* Legacy ring buffer submission */
815 struct drm_i915_gem_object *rcs_state;
821 struct drm_i915_gem_object *state;
822 struct intel_ringbuffer *ringbuf;
824 struct i915_vma *lrc_vma;
826 uint32_t *lrc_reg_state;
827 } engine[I915_NUM_RINGS];
829 struct list_head link;
841 /* This is always the inner lock when overlapping with struct_mutex and
842 * it's the outer lock when overlapping with stolen_lock. */
845 unsigned int possible_framebuffer_bits;
846 unsigned int busy_bits;
847 unsigned int visible_pipes_mask;
848 struct intel_crtc *crtc;
850 struct drm_mm_node compressed_fb;
851 struct drm_mm_node *compressed_llb;
858 struct intel_fbc_state_cache {
860 unsigned int mode_flags;
861 uint32_t hsw_bdw_pixel_rate;
865 unsigned int rotation;
873 uint32_t pixel_format;
876 unsigned int tiling_mode;
880 struct intel_fbc_reg_params {
884 unsigned int fence_y_offset;
889 uint32_t pixel_format;
897 struct intel_fbc_work {
899 u32 scheduled_vblank;
900 struct work_struct work;
903 const char *no_fbc_reason;
907 * HIGH_RR is the highest eDP panel refresh rate read from EDID
908 * LOW_RR is the lowest eDP panel refresh rate found from EDID
909 * parsing for same resolution.
911 enum drrs_refresh_rate_type {
914 DRRS_MAX_RR, /* RR count */
917 enum drrs_support_type {
918 DRRS_NOT_SUPPORTED = 0,
919 STATIC_DRRS_SUPPORT = 1,
920 SEAMLESS_DRRS_SUPPORT = 2
926 struct delayed_work work;
928 unsigned busy_frontbuffer_bits;
929 enum drrs_refresh_rate_type refresh_rate_type;
930 enum drrs_support_type type;
937 struct intel_dp *enabled;
939 struct delayed_work work;
940 unsigned busy_frontbuffer_bits;
947 PCH_NONE = 0, /* No PCH present */
948 PCH_IBX, /* Ibexpeak PCH */
949 PCH_CPT, /* Cougarpoint PCH */
950 PCH_LPT, /* Lynxpoint PCH */
951 PCH_SPT, /* Sunrisepoint PCH */
955 enum intel_sbi_destination {
960 #define QUIRK_PIPEA_FORCE (1<<0)
961 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
962 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
963 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
964 #define QUIRK_PIPEB_FORCE (1<<4)
965 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
968 struct intel_fbc_work;
971 struct i2c_adapter adapter;
975 struct i2c_algo_bit_data bit_algo;
976 struct drm_i915_private *dev_priv;
979 struct i915_suspend_saved_registers {
982 u32 savePP_ON_DELAYS;
983 u32 savePP_OFF_DELAYS;
989 u32 saveCACHE_MODE_0;
990 u32 saveMI_ARB_STATE;
994 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
995 u32 savePCH_PORT_HOTPLUG;
999 struct vlv_s0ix_state {
1006 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1007 u32 media_max_req_count;
1008 u32 gfx_max_req_count;
1034 u32 rp_down_timeout;
1040 /* Display 1 CZ domain */
1045 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1047 /* GT SA CZ domain */
1054 /* Display 2 CZ domain */
1058 u32 clock_gate_dis2;
1061 struct intel_rps_ei {
1067 struct intel_gen6_power_mgmt {
1069 * work, interrupts_enabled and pm_iir are protected by
1070 * dev_priv->irq_lock
1072 struct work_struct work;
1073 bool interrupts_enabled;
1076 /* Frequencies are stored in potentially platform dependent multiples.
1077 * In other words, *_freq needs to be multiplied by X to be interesting.
1078 * Soft limits are those which are used for the dynamic reclocking done
1079 * by the driver (raise frequencies under heavy loads, and lower for
1080 * lighter loads). Hard limits are those imposed by the hardware.
1082 * A distinction is made for overclocking, which is never enabled by
1083 * default, and is considered to be above the hard limit if it's
1086 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1087 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1088 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1089 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1090 u8 min_freq; /* AKA RPn. Minimum frequency */
1091 u8 idle_freq; /* Frequency to request when we are idle */
1092 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1093 u8 rp1_freq; /* "less than" RP0 power/freqency */
1094 u8 rp0_freq; /* Non-overclocked max frequency. */
1096 u8 up_threshold; /* Current %busy required to uplock */
1097 u8 down_threshold; /* Current %busy required to downclock */
1100 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1102 spinlock_t client_lock;
1103 struct list_head clients;
1107 struct delayed_work delayed_resume_work;
1110 struct intel_rps_client semaphores, mmioflips;
1112 /* manual wa residency calculations */
1113 struct intel_rps_ei up_ei, down_ei;
1116 * Protects RPS/RC6 register access and PCU communication.
1117 * Must be taken after struct_mutex if nested. Note that
1118 * this lock may be held for long periods of time when
1119 * talking to hw - so only take it when talking to hw!
1121 struct mutex hw_lock;
1124 /* defined intel_pm.c */
1125 extern spinlock_t mchdev_lock;
1127 struct intel_ilk_power_mgmt {
1135 unsigned long last_time1;
1136 unsigned long chipset_power;
1139 unsigned long gfx_power;
1146 struct drm_i915_private;
1147 struct i915_power_well;
1149 struct i915_power_well_ops {
1151 * Synchronize the well's hw state to match the current sw state, for
1152 * example enable/disable it based on the current refcount. Called
1153 * during driver init and resume time, possibly after first calling
1154 * the enable/disable handlers.
1156 void (*sync_hw)(struct drm_i915_private *dev_priv,
1157 struct i915_power_well *power_well);
1159 * Enable the well and resources that depend on it (for example
1160 * interrupts located on the well). Called after the 0->1 refcount
1163 void (*enable)(struct drm_i915_private *dev_priv,
1164 struct i915_power_well *power_well);
1166 * Disable the well and resources that depend on it. Called after
1167 * the 1->0 refcount transition.
1169 void (*disable)(struct drm_i915_private *dev_priv,
1170 struct i915_power_well *power_well);
1171 /* Returns the hw enabled state. */
1172 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1173 struct i915_power_well *power_well);
1176 /* Power well structure for haswell */
1177 struct i915_power_well {
1180 /* power well enable/disable usage count */
1182 /* cached hw enabled state */
1184 unsigned long domains;
1186 const struct i915_power_well_ops *ops;
1189 struct i915_power_domains {
1191 * Power wells needed for initialization at driver init and suspend
1192 * time are on. They are kept on until after the first modeset.
1196 int power_well_count;
1199 int domain_use_count[POWER_DOMAIN_NUM];
1200 struct i915_power_well *power_wells;
1203 #define MAX_L3_SLICES 2
1204 struct intel_l3_parity {
1205 u32 *remap_info[MAX_L3_SLICES];
1206 struct work_struct error_work;
1210 struct i915_gem_mm {
1211 /** Memory allocator for GTT stolen memory */
1212 struct drm_mm stolen;
1213 /** Protects the usage of the GTT stolen memory allocator. This is
1214 * always the inner lock when overlapping with struct_mutex. */
1215 struct mutex stolen_lock;
1217 /** List of all objects in gtt_space. Used to restore gtt
1218 * mappings on resume */
1219 struct list_head bound_list;
1221 * List of objects which are not bound to the GTT (thus
1222 * are idle and not used by the GPU) but still have
1223 * (presumably uncached) pages still attached.
1225 struct list_head unbound_list;
1227 /** Usable portion of the GTT for GEM */
1228 unsigned long stolen_base; /* limited to low memory (32-bit) */
1230 /** PPGTT used for aliasing the PPGTT with the GTT */
1231 struct i915_hw_ppgtt *aliasing_ppgtt;
1233 struct notifier_block oom_notifier;
1234 struct shrinker shrinker;
1235 bool shrinker_no_lock_stealing;
1237 /** LRU list of objects with fence regs on them. */
1238 struct list_head fence_list;
1241 * We leave the user IRQ off as much as possible,
1242 * but this means that requests will finish and never
1243 * be retired once the system goes idle. Set a timer to
1244 * fire periodically while the ring is running. When it
1245 * fires, go retire requests.
1247 struct delayed_work retire_work;
1250 * When we detect an idle GPU, we want to turn on
1251 * powersaving features. So once we see that there
1252 * are no more requests outstanding and no more
1253 * arrive within a small period of time, we fire
1254 * off the idle_work.
1256 struct delayed_work idle_work;
1259 * Are we in a non-interruptible section of code like
1265 * Is the GPU currently considered idle, or busy executing userspace
1266 * requests? Whilst idle, we attempt to power down the hardware and
1267 * display clocks. In order to reduce the effect on performance, there
1268 * is a slight delay before we do so.
1272 /* the indicator for dispatch video commands on two BSD rings */
1273 unsigned int bsd_ring_dispatch_index;
1275 /** Bit 6 swizzling required for X tiling */
1276 uint32_t bit_6_swizzle_x;
1277 /** Bit 6 swizzling required for Y tiling */
1278 uint32_t bit_6_swizzle_y;
1280 /* accounting, useful for userland debugging */
1281 spinlock_t object_stat_lock;
1282 size_t object_memory;
1286 struct drm_i915_error_state_buf {
1287 struct drm_i915_private *i915;
1296 struct i915_error_state_file_priv {
1297 struct drm_device *dev;
1298 struct drm_i915_error_state *error;
1301 struct i915_gpu_error {
1302 /* For hangcheck timer */
1303 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1304 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1305 /* Hang gpu twice in this window and your context gets banned */
1306 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1308 struct workqueue_struct *hangcheck_wq;
1309 struct delayed_work hangcheck_work;
1311 /* For reset and error_state handling. */
1313 /* Protected by the above dev->gpu_error.lock. */
1314 struct drm_i915_error_state *first_error;
1316 unsigned long missed_irq_rings;
1319 * State variable controlling the reset flow and count
1321 * This is a counter which gets incremented when reset is triggered,
1322 * and again when reset has been handled. So odd values (lowest bit set)
1323 * means that reset is in progress and even values that
1324 * (reset_counter >> 1):th reset was successfully completed.
1326 * If reset is not completed succesfully, the I915_WEDGE bit is
1327 * set meaning that hardware is terminally sour and there is no
1328 * recovery. All waiters on the reset_queue will be woken when
1331 * This counter is used by the wait_seqno code to notice that reset
1332 * event happened and it needs to restart the entire ioctl (since most
1333 * likely the seqno it waited for won't ever signal anytime soon).
1335 * This is important for lock-free wait paths, where no contended lock
1336 * naturally enforces the correct ordering between the bail-out of the
1337 * waiter and the gpu reset work code.
1339 atomic_t reset_counter;
1341 #define I915_RESET_IN_PROGRESS_FLAG 1
1342 #define I915_WEDGED (1 << 31)
1345 * Waitqueue to signal when the reset has completed. Used by clients
1346 * that wait for dev_priv->mm.wedged to settle.
1348 wait_queue_head_t reset_queue;
1350 /* Userspace knobs for gpu hang simulation;
1351 * combines both a ring mask, and extra flags
1354 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1355 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1357 /* For missed irq/seqno simulation. */
1358 unsigned int test_irq_rings;
1360 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1361 bool reload_in_reset;
1364 enum modeset_restore {
1365 MODESET_ON_LID_OPEN,
1370 #define DP_AUX_A 0x40
1371 #define DP_AUX_B 0x10
1372 #define DP_AUX_C 0x20
1373 #define DP_AUX_D 0x30
1375 #define DDC_PIN_B 0x05
1376 #define DDC_PIN_C 0x04
1377 #define DDC_PIN_D 0x06
1379 struct ddi_vbt_port_info {
1381 * This is an index in the HDMI/DVI DDI buffer translation table.
1382 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1383 * populate this field.
1385 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1386 uint8_t hdmi_level_shift;
1388 uint8_t supports_dvi:1;
1389 uint8_t supports_hdmi:1;
1390 uint8_t supports_dp:1;
1392 uint8_t alternate_aux_channel;
1393 uint8_t alternate_ddc_pin;
1395 uint8_t dp_boost_level;
1396 uint8_t hdmi_boost_level;
1399 enum psr_lines_to_wait {
1400 PSR_0_LINES_TO_WAIT = 0,
1402 PSR_4_LINES_TO_WAIT,
1406 struct intel_vbt_data {
1407 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1408 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1411 unsigned int int_tv_support:1;
1412 unsigned int lvds_dither:1;
1413 unsigned int lvds_vbt:1;
1414 unsigned int int_crt_support:1;
1415 unsigned int lvds_use_ssc:1;
1416 unsigned int display_clock_mode:1;
1417 unsigned int fdi_rx_polarity_inverted:1;
1418 unsigned int has_mipi:1;
1420 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1422 enum drrs_support_type drrs_type;
1427 int edp_preemphasis;
1429 bool edp_initialized;
1432 struct edp_power_seq edp_pps;
1436 bool require_aux_wakeup;
1438 enum psr_lines_to_wait lines_to_wait;
1439 int tp1_wakeup_time;
1440 int tp2_tp3_wakeup_time;
1446 bool active_low_pwm;
1447 u8 min_brightness; /* min_brightness/255 of max */
1454 struct mipi_config *config;
1455 struct mipi_pps_data *pps;
1459 const u8 *sequence[MIPI_SEQ_MAX];
1465 union child_device_config *child_dev;
1467 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1470 enum intel_ddb_partitioning {
1472 INTEL_DDB_PART_5_6, /* IVB+ */
1475 struct intel_wm_level {
1483 struct ilk_wm_values {
1484 uint32_t wm_pipe[3];
1486 uint32_t wm_lp_spr[3];
1487 uint32_t wm_linetime[3];
1489 enum intel_ddb_partitioning partitioning;
1492 struct vlv_pipe_wm {
1503 struct vlv_wm_values {
1504 struct vlv_pipe_wm pipe[3];
1505 struct vlv_sr_wm sr;
1515 struct skl_ddb_entry {
1516 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1519 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1521 return entry->end - entry->start;
1524 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1525 const struct skl_ddb_entry *e2)
1527 if (e1->start == e2->start && e1->end == e2->end)
1533 struct skl_ddb_allocation {
1534 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1535 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1536 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1539 struct skl_wm_values {
1540 bool dirty[I915_MAX_PIPES];
1541 struct skl_ddb_allocation ddb;
1542 uint32_t wm_linetime[I915_MAX_PIPES];
1543 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1544 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1547 struct skl_wm_level {
1548 bool plane_en[I915_MAX_PLANES];
1549 uint16_t plane_res_b[I915_MAX_PLANES];
1550 uint8_t plane_res_l[I915_MAX_PLANES];
1554 * This struct helps tracking the state needed for runtime PM, which puts the
1555 * device in PCI D3 state. Notice that when this happens, nothing on the
1556 * graphics device works, even register access, so we don't get interrupts nor
1559 * Every piece of our code that needs to actually touch the hardware needs to
1560 * either call intel_runtime_pm_get or call intel_display_power_get with the
1561 * appropriate power domain.
1563 * Our driver uses the autosuspend delay feature, which means we'll only really
1564 * suspend if we stay with zero refcount for a certain amount of time. The
1565 * default value is currently very conservative (see intel_runtime_pm_enable), but
1566 * it can be changed with the standard runtime PM files from sysfs.
1568 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1569 * goes back to false exactly before we reenable the IRQs. We use this variable
1570 * to check if someone is trying to enable/disable IRQs while they're supposed
1571 * to be disabled. This shouldn't happen and we'll print some error messages in
1574 * For more, read the Documentation/power/runtime_pm.txt.
1576 struct i915_runtime_pm {
1577 atomic_t wakeref_count;
1578 atomic_t atomic_seq;
1583 enum intel_pipe_crc_source {
1584 INTEL_PIPE_CRC_SOURCE_NONE,
1585 INTEL_PIPE_CRC_SOURCE_PLANE1,
1586 INTEL_PIPE_CRC_SOURCE_PLANE2,
1587 INTEL_PIPE_CRC_SOURCE_PF,
1588 INTEL_PIPE_CRC_SOURCE_PIPE,
1589 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1590 INTEL_PIPE_CRC_SOURCE_TV,
1591 INTEL_PIPE_CRC_SOURCE_DP_B,
1592 INTEL_PIPE_CRC_SOURCE_DP_C,
1593 INTEL_PIPE_CRC_SOURCE_DP_D,
1594 INTEL_PIPE_CRC_SOURCE_AUTO,
1595 INTEL_PIPE_CRC_SOURCE_MAX,
1598 struct intel_pipe_crc_entry {
1603 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1604 struct intel_pipe_crc {
1606 bool opened; /* exclusive access to the result file */
1607 struct intel_pipe_crc_entry *entries;
1608 enum intel_pipe_crc_source source;
1610 wait_queue_head_t wq;
1613 struct i915_frontbuffer_tracking {
1617 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1624 struct i915_wa_reg {
1627 /* bitmask representing WA bits */
1632 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1633 * allowing it for RCS as we don't foresee any requirement of having
1634 * a whitelist for other engines. When it is really required for
1635 * other engines then the limit need to be increased.
1637 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1639 struct i915_workarounds {
1640 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1642 u32 hw_whitelist_count[I915_NUM_RINGS];
1645 struct i915_virtual_gpu {
1649 struct i915_execbuffer_params {
1650 struct drm_device *dev;
1651 struct drm_file *file;
1652 uint32_t dispatch_flags;
1653 uint32_t args_batch_start_offset;
1654 uint64_t batch_obj_vm_offset;
1655 struct intel_engine_cs *engine;
1656 struct drm_i915_gem_object *batch_obj;
1657 struct intel_context *ctx;
1658 struct drm_i915_gem_request *request;
1661 /* used in computing the new watermarks state */
1662 struct intel_wm_config {
1663 unsigned int num_pipes_active;
1664 bool sprites_enabled;
1665 bool sprites_scaled;
1668 struct drm_i915_private {
1669 struct drm_device *dev;
1670 struct kmem_cache *objects;
1671 struct kmem_cache *vmas;
1672 struct kmem_cache *requests;
1674 const struct intel_device_info info;
1676 int relative_constants_mode;
1680 struct intel_uncore uncore;
1682 struct i915_virtual_gpu vgpu;
1684 struct intel_guc guc;
1686 struct intel_csr csr;
1688 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1690 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1691 * controller on different i2c buses. */
1692 struct mutex gmbus_mutex;
1695 * Base address of the gmbus and gpio block.
1697 uint32_t gpio_mmio_base;
1699 /* MMIO base address for MIPI regs */
1700 uint32_t mipi_mmio_base;
1702 uint32_t psr_mmio_base;
1704 wait_queue_head_t gmbus_wait_queue;
1706 struct pci_dev *bridge_dev;
1707 struct intel_engine_cs engine[I915_NUM_RINGS];
1708 struct drm_i915_gem_object *semaphore_obj;
1709 uint32_t last_seqno, next_seqno;
1711 struct drm_dma_handle *status_page_dmah;
1712 struct resource mch_res;
1714 /* protects the irq masks */
1715 spinlock_t irq_lock;
1717 /* protects the mmio flip data */
1718 spinlock_t mmio_flip_lock;
1720 bool display_irqs_enabled;
1722 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1723 struct pm_qos_request pm_qos;
1725 /* Sideband mailbox protection */
1726 struct mutex sb_lock;
1728 /** Cached value of IMR to avoid reads in updating the bitfield */
1731 u32 de_irq_mask[I915_MAX_PIPES];
1736 u32 pipestat_irq_mask[I915_MAX_PIPES];
1738 struct i915_hotplug hotplug;
1739 struct intel_fbc fbc;
1740 struct i915_drrs drrs;
1741 struct intel_opregion opregion;
1742 struct intel_vbt_data vbt;
1744 bool preserve_bios_swizzle;
1747 struct intel_overlay *overlay;
1749 /* backlight registers and fields in struct intel_panel */
1750 struct mutex backlight_lock;
1753 bool no_aux_handshake;
1755 /* protects panel power sequencer state */
1756 struct mutex pps_mutex;
1758 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1759 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1761 unsigned int fsb_freq, mem_freq, is_ddr3;
1762 unsigned int skl_boot_cdclk;
1763 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1764 unsigned int max_dotclk_freq;
1765 unsigned int rawclk_freq;
1766 unsigned int hpll_freq;
1767 unsigned int czclk_freq;
1770 * wq - Driver workqueue for GEM.
1772 * NOTE: Work items scheduled here are not allowed to grab any modeset
1773 * locks, for otherwise the flushing done in the pageflip code will
1774 * result in deadlocks.
1776 struct workqueue_struct *wq;
1778 /* Display functions */
1779 struct drm_i915_display_funcs display;
1781 /* PCH chipset type */
1782 enum intel_pch pch_type;
1783 unsigned short pch_id;
1785 unsigned long quirks;
1787 enum modeset_restore modeset_restore;
1788 struct mutex modeset_restore_lock;
1789 struct drm_atomic_state *modeset_restore_state;
1791 struct list_head vm_list; /* Global list of all address spaces */
1792 struct i915_gtt gtt; /* VM representing the global address space */
1794 struct i915_gem_mm mm;
1795 DECLARE_HASHTABLE(mm_structs, 7);
1796 struct mutex mm_lock;
1798 /* Kernel Modesetting */
1800 struct sdvo_device_mapping sdvo_mappings[2];
1802 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1803 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1804 wait_queue_head_t pending_flip_queue;
1806 #ifdef CONFIG_DEBUG_FS
1807 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1810 /* dpll and cdclk state is protected by connection_mutex */
1811 int num_shared_dpll;
1812 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1813 const struct intel_dpll_mgr *dpll_mgr;
1815 unsigned int active_crtcs;
1816 unsigned int min_pixclk[I915_MAX_PIPES];
1818 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1820 struct i915_workarounds workarounds;
1822 /* Reclocking support */
1823 bool render_reclock_avail;
1825 struct i915_frontbuffer_tracking fb_tracking;
1829 bool mchbar_need_disable;
1831 struct intel_l3_parity l3_parity;
1833 /* Cannot be determined by PCIID. You must always read a register. */
1836 /* gen6+ rps state */
1837 struct intel_gen6_power_mgmt rps;
1839 /* ilk-only ips/rps state. Everything in here is protected by the global
1840 * mchdev_lock in intel_pm.c */
1841 struct intel_ilk_power_mgmt ips;
1843 struct i915_power_domains power_domains;
1845 struct i915_psr psr;
1847 struct i915_gpu_error gpu_error;
1849 struct drm_i915_gem_object *vlv_pctx;
1851 #ifdef CONFIG_DRM_FBDEV_EMULATION
1852 /* list of fbdev register on this device */
1853 struct intel_fbdev *fbdev;
1854 struct work_struct fbdev_suspend_work;
1857 struct drm_property *broadcast_rgb_property;
1858 struct drm_property *force_audio_property;
1860 /* hda/i915 audio component */
1861 struct i915_audio_component *audio_component;
1862 bool audio_component_registered;
1864 * av_mutex - mutex for audio/video sync
1867 struct mutex av_mutex;
1869 uint32_t hw_context_size;
1870 struct list_head context_list;
1874 u32 chv_phy_control;
1877 bool suspended_to_idle;
1878 struct i915_suspend_saved_registers regfile;
1879 struct vlv_s0ix_state vlv_s0ix_state;
1883 * Raw watermark latency values:
1884 * in 0.1us units for WM0,
1885 * in 0.5us units for WM1+.
1888 uint16_t pri_latency[5];
1890 uint16_t spr_latency[5];
1892 uint16_t cur_latency[5];
1894 * Raw watermark memory latency values
1895 * for SKL for all 8 levels
1898 uint16_t skl_latency[8];
1900 /* Committed wm config */
1901 struct intel_wm_config config;
1904 * The skl_wm_values structure is a bit too big for stack
1905 * allocation, so we keep the staging struct where we store
1906 * intermediate results here instead.
1908 struct skl_wm_values skl_results;
1910 /* current hardware state */
1912 struct ilk_wm_values hw;
1913 struct skl_wm_values skl_hw;
1914 struct vlv_wm_values vlv;
1920 * Should be held around atomic WM register writing; also
1921 * protects * intel_crtc->wm.active and
1922 * cstate->wm.need_postvbl_update.
1924 struct mutex wm_mutex;
1927 struct i915_runtime_pm pm;
1929 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1931 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1932 struct drm_i915_gem_execbuffer2 *args,
1933 struct list_head *vmas);
1934 int (*init_rings)(struct drm_device *dev);
1935 void (*cleanup_ring)(struct intel_engine_cs *ring);
1936 void (*stop_ring)(struct intel_engine_cs *ring);
1939 struct intel_context *kernel_context;
1941 bool edp_low_vswing;
1943 /* perform PHY state sanity checks? */
1944 bool chv_phy_assert[2];
1946 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
1949 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1950 * will be rejected. Instead look for a better place.
1954 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1956 return dev->dev_private;
1959 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1961 return to_i915(dev_get_drvdata(dev));
1964 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
1966 return container_of(guc, struct drm_i915_private, guc);
1969 /* Iterate over initialised rings */
1970 #define for_each_ring(ring__, dev_priv__, i__) \
1971 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1972 for_each_if ((((ring__) = &(dev_priv__)->engine[(i__)]), intel_ring_initialized((ring__))))
1974 enum hdmi_force_audio {
1975 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1976 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1977 HDMI_AUDIO_AUTO, /* trust EDID */
1978 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1981 #define I915_GTT_OFFSET_NONE ((u32)-1)
1983 struct drm_i915_gem_object_ops {
1985 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
1987 /* Interface between the GEM object and its backing storage.
1988 * get_pages() is called once prior to the use of the associated set
1989 * of pages before to binding them into the GTT, and put_pages() is
1990 * called after we no longer need them. As we expect there to be
1991 * associated cost with migrating pages between the backing storage
1992 * and making them available for the GPU (e.g. clflush), we may hold
1993 * onto the pages after they are no longer referenced by the GPU
1994 * in case they may be used again shortly (for example migrating the
1995 * pages to a different memory domain within the GTT). put_pages()
1996 * will therefore most likely be called when the object itself is
1997 * being released or under memory pressure (where we attempt to
1998 * reap pages for the shrinker).
2000 int (*get_pages)(struct drm_i915_gem_object *);
2001 void (*put_pages)(struct drm_i915_gem_object *);
2003 int (*dmabuf_export)(struct drm_i915_gem_object *);
2004 void (*release)(struct drm_i915_gem_object *);
2008 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2009 * considered to be the frontbuffer for the given plane interface-wise. This
2010 * doesn't mean that the hw necessarily already scans it out, but that any
2011 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2013 * We have one bit per pipe and per scanout plane type.
2015 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2016 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2017 #define INTEL_FRONTBUFFER_BITS \
2018 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2019 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2020 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2021 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2022 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2023 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2024 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2025 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2026 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2027 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2028 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2030 struct drm_i915_gem_object {
2031 struct drm_gem_object base;
2033 const struct drm_i915_gem_object_ops *ops;
2035 /** List of VMAs backed by this object */
2036 struct list_head vma_list;
2038 /** Stolen memory for this object, instead of being backed by shmem. */
2039 struct drm_mm_node *stolen;
2040 struct list_head global_list;
2042 struct list_head ring_list[I915_NUM_RINGS];
2043 /** Used in execbuf to temporarily hold a ref */
2044 struct list_head obj_exec_link;
2046 struct list_head batch_pool_link;
2049 * This is set if the object is on the active lists (has pending
2050 * rendering and so a non-zero seqno), and is not set if it i s on
2051 * inactive (ready to be unbound) list.
2053 unsigned int active:I915_NUM_RINGS;
2056 * This is set if the object has been written to since last bound
2059 unsigned int dirty:1;
2062 * Fence register bits (if any) for this object. Will be set
2063 * as needed when mapped into the GTT.
2064 * Protected by dev->struct_mutex.
2066 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2069 * Advice: are the backing pages purgeable?
2071 unsigned int madv:2;
2074 * Current tiling mode for the object.
2076 unsigned int tiling_mode:2;
2078 * Whether the tiling parameters for the currently associated fence
2079 * register have changed. Note that for the purposes of tracking
2080 * tiling changes we also treat the unfenced register, the register
2081 * slot that the object occupies whilst it executes a fenced
2082 * command (such as BLT on gen2/3), as a "fence".
2084 unsigned int fence_dirty:1;
2087 * Is the object at the current location in the gtt mappable and
2088 * fenceable? Used to avoid costly recalculations.
2090 unsigned int map_and_fenceable:1;
2093 * Whether the current gtt mapping needs to be mappable (and isn't just
2094 * mappable by accident). Track pin and fault separate for a more
2095 * accurate mappable working set.
2097 unsigned int fault_mappable:1;
2100 * Is the object to be mapped as read-only to the GPU
2101 * Only honoured if hardware has relevant pte bit
2103 unsigned long gt_ro:1;
2104 unsigned int cache_level:3;
2105 unsigned int cache_dirty:1;
2107 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2109 unsigned int pin_display;
2111 struct sg_table *pages;
2112 int pages_pin_count;
2114 struct scatterlist *sg;
2118 /* prime dma-buf support */
2119 void *dma_buf_vmapping;
2122 /** Breadcrumb of last rendering to the buffer.
2123 * There can only be one writer, but we allow for multiple readers.
2124 * If there is a writer that necessarily implies that all other
2125 * read requests are complete - but we may only be lazily clearing
2126 * the read requests. A read request is naturally the most recent
2127 * request on a ring, so we may have two different write and read
2128 * requests on one ring where the write request is older than the
2129 * read request. This allows for the CPU to read from an active
2130 * buffer by only waiting for the write to complete.
2132 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2133 struct drm_i915_gem_request *last_write_req;
2134 /** Breadcrumb of last fenced GPU access to the buffer. */
2135 struct drm_i915_gem_request *last_fenced_req;
2137 /** Current tiling stride for the object, if it's tiled. */
2140 /** References from framebuffers, locks out tiling changes. */
2141 unsigned long framebuffer_references;
2143 /** Record of address bit 17 of each page at last unbind. */
2144 unsigned long *bit_17;
2147 /** for phy allocated objects */
2148 struct drm_dma_handle *phys_handle;
2150 struct i915_gem_userptr {
2152 unsigned read_only :1;
2153 unsigned workers :4;
2154 #define I915_GEM_USERPTR_MAX_WORKERS 15
2156 struct i915_mm_struct *mm;
2157 struct i915_mmu_object *mmu_object;
2158 struct work_struct *work;
2162 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2164 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2165 struct drm_i915_gem_object *new,
2166 unsigned frontbuffer_bits);
2169 * Request queue structure.
2171 * The request queue allows us to note sequence numbers that have been emitted
2172 * and may be associated with active buffers to be retired.
2174 * By keeping this list, we can avoid having to do questionable sequence
2175 * number comparisons on buffer last_read|write_seqno. It also allows an
2176 * emission time to be associated with the request for tracking how far ahead
2177 * of the GPU the submission is.
2179 * The requests are reference counted, so upon creation they should have an
2180 * initial reference taken using kref_init
2182 struct drm_i915_gem_request {
2185 /** On Which ring this request was generated */
2186 struct drm_i915_private *i915;
2187 struct intel_engine_cs *engine;
2189 /** GEM sequence number associated with the previous request,
2190 * when the HWS breadcrumb is equal to this the GPU is processing
2195 /** GEM sequence number associated with this request,
2196 * when the HWS breadcrumb is equal or greater than this the GPU
2197 * has finished processing this request.
2201 /** Position in the ringbuffer of the start of the request */
2205 * Position in the ringbuffer of the start of the postfix.
2206 * This is required to calculate the maximum available ringbuffer
2207 * space without overwriting the postfix.
2211 /** Position in the ringbuffer of the end of the whole request */
2215 * Context and ring buffer related to this request
2216 * Contexts are refcounted, so when this request is associated with a
2217 * context, we must increment the context's refcount, to guarantee that
2218 * it persists while any request is linked to it. Requests themselves
2219 * are also refcounted, so the request will only be freed when the last
2220 * reference to it is dismissed, and the code in
2221 * i915_gem_request_free() will then decrement the refcount on the
2224 struct intel_context *ctx;
2225 struct intel_ringbuffer *ringbuf;
2227 /** Batch buffer related to this request if any (used for
2228 error state dump only) */
2229 struct drm_i915_gem_object *batch_obj;
2231 /** Time at which this request was emitted, in jiffies. */
2232 unsigned long emitted_jiffies;
2234 /** global list entry for this request */
2235 struct list_head list;
2237 struct drm_i915_file_private *file_priv;
2238 /** file_priv list entry for this request */
2239 struct list_head client_list;
2241 /** process identifier submitting this request */
2245 * The ELSP only accepts two elements at a time, so we queue
2246 * context/tail pairs on a given queue (ring->execlist_queue) until the
2247 * hardware is available. The queue serves a double purpose: we also use
2248 * it to keep track of the up to 2 contexts currently in the hardware
2249 * (usually one in execution and the other queued up by the GPU): We
2250 * only remove elements from the head of the queue when the hardware
2251 * informs us that an element has been completed.
2253 * All accesses to the queue are mediated by a spinlock
2254 * (ring->execlist_lock).
2257 /** Execlist link in the submission queue.*/
2258 struct list_head execlist_link;
2260 /** Execlists no. of times this request has been sent to the ELSP */
2265 struct drm_i915_gem_request * __must_check
2266 i915_gem_request_alloc(struct intel_engine_cs *engine,
2267 struct intel_context *ctx);
2268 void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2269 void i915_gem_request_free(struct kref *req_ref);
2270 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2271 struct drm_file *file);
2273 static inline uint32_t
2274 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2276 return req ? req->seqno : 0;
2279 static inline struct intel_engine_cs *
2280 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2282 return req ? req->engine : NULL;
2285 static inline struct drm_i915_gem_request *
2286 i915_gem_request_reference(struct drm_i915_gem_request *req)
2289 kref_get(&req->ref);
2294 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2296 WARN_ON(!mutex_is_locked(&req->engine->dev->struct_mutex));
2297 kref_put(&req->ref, i915_gem_request_free);
2301 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2303 struct drm_device *dev;
2308 dev = req->engine->dev;
2309 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2310 mutex_unlock(&dev->struct_mutex);
2313 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2314 struct drm_i915_gem_request *src)
2317 i915_gem_request_reference(src);
2320 i915_gem_request_unreference(*pdst);
2326 * XXX: i915_gem_request_completed should be here but currently needs the
2327 * definition of i915_seqno_passed() which is below. It will be moved in
2328 * a later patch when the call to i915_seqno_passed() is obsoleted...
2332 * A command that requires special handling by the command parser.
2334 struct drm_i915_cmd_descriptor {
2336 * Flags describing how the command parser processes the command.
2338 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2339 * a length mask if not set
2340 * CMD_DESC_SKIP: The command is allowed but does not follow the
2341 * standard length encoding for the opcode range in
2343 * CMD_DESC_REJECT: The command is never allowed
2344 * CMD_DESC_REGISTER: The command should be checked against the
2345 * register whitelist for the appropriate ring
2346 * CMD_DESC_MASTER: The command is allowed if the submitting process
2350 #define CMD_DESC_FIXED (1<<0)
2351 #define CMD_DESC_SKIP (1<<1)
2352 #define CMD_DESC_REJECT (1<<2)
2353 #define CMD_DESC_REGISTER (1<<3)
2354 #define CMD_DESC_BITMASK (1<<4)
2355 #define CMD_DESC_MASTER (1<<5)
2358 * The command's unique identification bits and the bitmask to get them.
2359 * This isn't strictly the opcode field as defined in the spec and may
2360 * also include type, subtype, and/or subop fields.
2368 * The command's length. The command is either fixed length (i.e. does
2369 * not include a length field) or has a length field mask. The flag
2370 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2371 * a length mask. All command entries in a command table must include
2372 * length information.
2380 * Describes where to find a register address in the command to check
2381 * against the ring's register whitelist. Only valid if flags has the
2382 * CMD_DESC_REGISTER bit set.
2384 * A non-zero step value implies that the command may access multiple
2385 * registers in sequence (e.g. LRI), in that case step gives the
2386 * distance in dwords between individual offset fields.
2394 #define MAX_CMD_DESC_BITMASKS 3
2396 * Describes command checks where a particular dword is masked and
2397 * compared against an expected value. If the command does not match
2398 * the expected value, the parser rejects it. Only valid if flags has
2399 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2402 * If the check specifies a non-zero condition_mask then the parser
2403 * only performs the check when the bits specified by condition_mask
2410 u32 condition_offset;
2412 } bits[MAX_CMD_DESC_BITMASKS];
2416 * A table of commands requiring special handling by the command parser.
2418 * Each ring has an array of tables. Each table consists of an array of command
2419 * descriptors, which must be sorted with command opcodes in ascending order.
2421 struct drm_i915_cmd_table {
2422 const struct drm_i915_cmd_descriptor *table;
2426 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2427 #define __I915__(p) ({ \
2428 struct drm_i915_private *__p; \
2429 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2430 __p = (struct drm_i915_private *)p; \
2431 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2432 __p = to_i915((struct drm_device *)p); \
2437 #define INTEL_INFO(p) (&__I915__(p)->info)
2438 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2439 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2441 #define REVID_FOREVER 0xff
2443 * Return true if revision is in range [since,until] inclusive.
2445 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2447 #define IS_REVID(p, since, until) \
2448 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2450 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2451 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2452 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2453 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2454 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2455 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2456 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2457 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2458 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2459 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2460 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2461 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2462 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2463 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2464 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2465 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2466 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2467 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2468 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2469 INTEL_DEVID(dev) == 0x0152 || \
2470 INTEL_DEVID(dev) == 0x015a)
2471 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2472 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2473 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2474 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2475 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2476 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2477 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2478 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2479 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2480 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2481 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2482 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2483 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2484 (INTEL_DEVID(dev) & 0xf) == 0xe))
2485 /* ULX machines are also considered ULT. */
2486 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2487 (INTEL_DEVID(dev) & 0xf) == 0xe)
2488 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2489 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2490 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2491 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2492 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2493 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2494 /* ULX machines are also considered ULT. */
2495 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2496 INTEL_DEVID(dev) == 0x0A1E)
2497 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2498 INTEL_DEVID(dev) == 0x1913 || \
2499 INTEL_DEVID(dev) == 0x1916 || \
2500 INTEL_DEVID(dev) == 0x1921 || \
2501 INTEL_DEVID(dev) == 0x1926)
2502 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2503 INTEL_DEVID(dev) == 0x1915 || \
2504 INTEL_DEVID(dev) == 0x191E)
2505 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2506 INTEL_DEVID(dev) == 0x5913 || \
2507 INTEL_DEVID(dev) == 0x5916 || \
2508 INTEL_DEVID(dev) == 0x5921 || \
2509 INTEL_DEVID(dev) == 0x5926)
2510 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2511 INTEL_DEVID(dev) == 0x5915 || \
2512 INTEL_DEVID(dev) == 0x591E)
2513 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2514 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2515 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2516 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2518 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2520 #define SKL_REVID_A0 0x0
2521 #define SKL_REVID_B0 0x1
2522 #define SKL_REVID_C0 0x2
2523 #define SKL_REVID_D0 0x3
2524 #define SKL_REVID_E0 0x4
2525 #define SKL_REVID_F0 0x5
2527 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2529 #define BXT_REVID_A0 0x0
2530 #define BXT_REVID_A1 0x1
2531 #define BXT_REVID_B0 0x3
2532 #define BXT_REVID_C0 0x9
2534 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2537 * The genX designation typically refers to the render engine, so render
2538 * capability related checks should use IS_GEN, while display and other checks
2539 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2542 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2543 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2544 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2545 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2546 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2547 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2548 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2549 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2551 #define RENDER_RING (1<<RCS)
2552 #define BSD_RING (1<<VCS)
2553 #define BLT_RING (1<<BCS)
2554 #define VEBOX_RING (1<<VECS)
2555 #define BSD2_RING (1<<VCS2)
2556 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2557 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2558 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2559 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2560 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2561 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2562 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2563 __I915__(dev)->ellc_size)
2564 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2566 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2567 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2568 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2569 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2570 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2572 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2573 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2575 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2576 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2578 /* WaRsDisableCoarsePowerGating:skl,bxt */
2579 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2580 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
2581 IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
2583 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2584 * even when in MSI mode. This results in spurious interrupt warnings if the
2585 * legacy irq no. is shared with another device. The kernel then disables that
2586 * interrupt source and so prevents the other device from working properly.
2588 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2589 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2591 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2592 * rows, which changed the alignment requirements and fence programming.
2594 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2596 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2597 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2599 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2600 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2601 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2603 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2605 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2606 INTEL_INFO(dev)->gen >= 9)
2608 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2609 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2610 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2611 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2612 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2613 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2614 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2615 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2617 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2618 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2620 #define HAS_CSR(dev) (IS_GEN9(dev))
2622 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2623 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2625 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2626 INTEL_INFO(dev)->gen >= 8)
2628 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2629 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2632 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2633 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2634 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2635 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2636 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2637 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2638 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2639 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2640 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2641 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2643 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2644 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2645 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2646 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2647 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2648 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2649 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2650 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2651 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2653 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2654 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2656 /* DPF == dynamic parity feature */
2657 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2658 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2660 #define GT_FREQUENCY_MULTIPLIER 50
2661 #define GEN9_FREQ_SCALER 3
2663 #include "i915_trace.h"
2665 extern const struct drm_ioctl_desc i915_ioctls[];
2666 extern int i915_max_ioctl;
2668 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2669 extern int i915_resume_switcheroo(struct drm_device *dev);
2672 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2673 extern int i915_driver_unload(struct drm_device *);
2674 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2675 extern void i915_driver_lastclose(struct drm_device * dev);
2676 extern void i915_driver_preclose(struct drm_device *dev,
2677 struct drm_file *file);
2678 extern void i915_driver_postclose(struct drm_device *dev,
2679 struct drm_file *file);
2680 #ifdef CONFIG_COMPAT
2681 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2684 extern int intel_gpu_reset(struct drm_device *dev);
2685 extern bool intel_has_gpu_reset(struct drm_device *dev);
2686 extern int i915_reset(struct drm_device *dev);
2687 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2688 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2689 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2690 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2691 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2693 /* intel_hotplug.c */
2694 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2695 void intel_hpd_init(struct drm_i915_private *dev_priv);
2696 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2697 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2698 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2701 void i915_queue_hangcheck(struct drm_device *dev);
2703 void i915_handle_error(struct drm_device *dev, bool wedged,
2704 const char *fmt, ...);
2706 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2707 int intel_irq_install(struct drm_i915_private *dev_priv);
2708 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2710 extern void intel_uncore_sanitize(struct drm_device *dev);
2711 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2712 bool restore_forcewake);
2713 extern void intel_uncore_init(struct drm_device *dev);
2714 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2715 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2716 extern void intel_uncore_fini(struct drm_device *dev);
2717 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2718 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2719 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2720 enum forcewake_domains domains);
2721 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2722 enum forcewake_domains domains);
2723 /* Like above but the caller must manage the uncore.lock itself.
2724 * Must be used with I915_READ_FW and friends.
2726 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2727 enum forcewake_domains domains);
2728 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2729 enum forcewake_domains domains);
2730 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2731 static inline bool intel_vgpu_active(struct drm_device *dev)
2733 return to_i915(dev)->vgpu.active;
2737 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2741 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2744 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2745 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2746 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2749 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2750 uint32_t interrupt_mask,
2751 uint32_t enabled_irq_mask);
2753 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2755 ilk_update_display_irq(dev_priv, bits, bits);
2758 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2760 ilk_update_display_irq(dev_priv, bits, 0);
2762 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2764 uint32_t interrupt_mask,
2765 uint32_t enabled_irq_mask);
2766 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2767 enum pipe pipe, uint32_t bits)
2769 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2771 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2772 enum pipe pipe, uint32_t bits)
2774 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2776 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2777 uint32_t interrupt_mask,
2778 uint32_t enabled_irq_mask);
2780 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2782 ibx_display_interrupt_update(dev_priv, bits, bits);
2785 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2787 ibx_display_interrupt_update(dev_priv, bits, 0);
2792 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2793 struct drm_file *file_priv);
2794 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2795 struct drm_file *file_priv);
2796 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2797 struct drm_file *file_priv);
2798 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2799 struct drm_file *file_priv);
2800 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2801 struct drm_file *file_priv);
2802 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2803 struct drm_file *file_priv);
2804 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2805 struct drm_file *file_priv);
2806 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2807 struct drm_i915_gem_request *req);
2808 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2809 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2810 struct drm_i915_gem_execbuffer2 *args,
2811 struct list_head *vmas);
2812 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2813 struct drm_file *file_priv);
2814 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2815 struct drm_file *file_priv);
2816 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2817 struct drm_file *file_priv);
2818 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2819 struct drm_file *file);
2820 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2821 struct drm_file *file);
2822 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2823 struct drm_file *file_priv);
2824 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2825 struct drm_file *file_priv);
2826 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2827 struct drm_file *file_priv);
2828 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2829 struct drm_file *file_priv);
2830 int i915_gem_init_userptr(struct drm_device *dev);
2831 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2832 struct drm_file *file);
2833 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2834 struct drm_file *file_priv);
2835 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2836 struct drm_file *file_priv);
2837 void i915_gem_load_init(struct drm_device *dev);
2838 void i915_gem_load_cleanup(struct drm_device *dev);
2839 void *i915_gem_object_alloc(struct drm_device *dev);
2840 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2841 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2842 const struct drm_i915_gem_object_ops *ops);
2843 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2845 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2846 struct drm_device *dev, const void *data, size_t size);
2847 void i915_gem_free_object(struct drm_gem_object *obj);
2848 void i915_gem_vma_destroy(struct i915_vma *vma);
2850 /* Flags used by pin/bind&friends. */
2851 #define PIN_MAPPABLE (1<<0)
2852 #define PIN_NONBLOCK (1<<1)
2853 #define PIN_GLOBAL (1<<2)
2854 #define PIN_OFFSET_BIAS (1<<3)
2855 #define PIN_USER (1<<4)
2856 #define PIN_UPDATE (1<<5)
2857 #define PIN_ZONE_4G (1<<6)
2858 #define PIN_HIGH (1<<7)
2859 #define PIN_OFFSET_FIXED (1<<8)
2860 #define PIN_OFFSET_MASK (~4095)
2862 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2863 struct i915_address_space *vm,
2867 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2868 const struct i915_ggtt_view *view,
2872 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2874 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2875 int __must_check i915_vma_unbind(struct i915_vma *vma);
2877 * BEWARE: Do not use the function below unless you can _absolutely_
2878 * _guarantee_ VMA in question is _not in use_ anywhere.
2880 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2881 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2882 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2883 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2885 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2886 int *needs_clflush);
2888 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2890 static inline int __sg_page_count(struct scatterlist *sg)
2892 return sg->length >> PAGE_SHIFT;
2896 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
2898 static inline struct page *
2899 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2901 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2904 if (n < obj->get_page.last) {
2905 obj->get_page.sg = obj->pages->sgl;
2906 obj->get_page.last = 0;
2909 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2910 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2911 if (unlikely(sg_is_chain(obj->get_page.sg)))
2912 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2915 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2918 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2920 BUG_ON(obj->pages == NULL);
2921 obj->pages_pin_count++;
2923 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2925 BUG_ON(obj->pages_pin_count == 0);
2926 obj->pages_pin_count--;
2929 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2930 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2931 struct intel_engine_cs *to,
2932 struct drm_i915_gem_request **to_req);
2933 void i915_vma_move_to_active(struct i915_vma *vma,
2934 struct drm_i915_gem_request *req);
2935 int i915_gem_dumb_create(struct drm_file *file_priv,
2936 struct drm_device *dev,
2937 struct drm_mode_create_dumb *args);
2938 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2939 uint32_t handle, uint64_t *offset);
2941 * Returns true if seq1 is later than seq2.
2944 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2946 return (int32_t)(seq1 - seq2) >= 0;
2949 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
2950 bool lazy_coherency)
2952 u32 seqno = req->engine->get_seqno(req->engine, lazy_coherency);
2953 return i915_seqno_passed(seqno, req->previous_seqno);
2956 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2957 bool lazy_coherency)
2959 u32 seqno = req->engine->get_seqno(req->engine, lazy_coherency);
2960 return i915_seqno_passed(seqno, req->seqno);
2963 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2964 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2966 struct drm_i915_gem_request *
2967 i915_gem_find_active_request(struct intel_engine_cs *engine);
2969 bool i915_gem_retire_requests(struct drm_device *dev);
2970 void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
2971 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2972 bool interruptible);
2974 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2976 return unlikely(atomic_read(&error->reset_counter)
2977 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2980 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2982 return atomic_read(&error->reset_counter) & I915_WEDGED;
2985 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2987 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2990 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2992 return dev_priv->gpu_error.stop_rings == 0 ||
2993 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2996 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2998 return dev_priv->gpu_error.stop_rings == 0 ||
2999 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3002 void i915_gem_reset(struct drm_device *dev);
3003 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3004 int __must_check i915_gem_init(struct drm_device *dev);
3005 int i915_gem_init_rings(struct drm_device *dev);
3006 int __must_check i915_gem_init_hw(struct drm_device *dev);
3007 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3008 void i915_gem_init_swizzling(struct drm_device *dev);
3009 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
3010 int __must_check i915_gpu_idle(struct drm_device *dev);
3011 int __must_check i915_gem_suspend(struct drm_device *dev);
3012 void __i915_add_request(struct drm_i915_gem_request *req,
3013 struct drm_i915_gem_object *batch_obj,
3015 #define i915_add_request(req) \
3016 __i915_add_request(req, NULL, true)
3017 #define i915_add_request_no_flush(req) \
3018 __i915_add_request(req, NULL, false)
3019 int __i915_wait_request(struct drm_i915_gem_request *req,
3020 unsigned reset_counter,
3023 struct intel_rps_client *rps);
3024 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3025 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3027 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3030 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3033 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3035 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3037 const struct i915_ggtt_view *view);
3038 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3039 const struct i915_ggtt_view *view);
3040 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3042 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3043 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3046 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3048 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3049 int tiling_mode, bool fenced);
3051 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3052 enum i915_cache_level cache_level);
3054 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3055 struct dma_buf *dma_buf);
3057 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3058 struct drm_gem_object *gem_obj, int flags);
3060 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3061 const struct i915_ggtt_view *view);
3062 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3063 struct i915_address_space *vm);
3065 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3067 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3070 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3071 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3072 const struct i915_ggtt_view *view);
3073 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3074 struct i915_address_space *vm);
3076 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3077 struct i915_address_space *vm);
3079 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3080 struct i915_address_space *vm);
3082 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3083 const struct i915_ggtt_view *view);
3086 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3087 struct i915_address_space *vm);
3089 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3090 const struct i915_ggtt_view *view);
3092 static inline struct i915_vma *
3093 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3095 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3097 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3099 /* Some GGTT VM helpers */
3100 #define i915_obj_to_ggtt(obj) \
3101 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3103 static inline struct i915_hw_ppgtt *
3104 i915_vm_to_ppgtt(struct i915_address_space *vm)
3106 WARN_ON(i915_is_ggtt(vm));
3107 return container_of(vm, struct i915_hw_ppgtt, base);
3111 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3113 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3116 static inline unsigned long
3117 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3119 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3122 static inline int __must_check
3123 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3127 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3128 alignment, flags | PIN_GLOBAL);
3132 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3134 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3137 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3138 const struct i915_ggtt_view *view);
3140 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3142 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3145 /* i915_gem_fence.c */
3146 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3147 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3149 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3150 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3152 void i915_gem_restore_fences(struct drm_device *dev);
3154 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3155 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3156 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3158 /* i915_gem_context.c */
3159 int __must_check i915_gem_context_init(struct drm_device *dev);
3160 void i915_gem_context_fini(struct drm_device *dev);
3161 void i915_gem_context_reset(struct drm_device *dev);
3162 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3163 int i915_gem_context_enable(struct drm_i915_gem_request *req);
3164 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3165 int i915_switch_context(struct drm_i915_gem_request *req);
3166 struct intel_context *
3167 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3168 void i915_gem_context_free(struct kref *ctx_ref);
3169 struct drm_i915_gem_object *
3170 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3171 static inline void i915_gem_context_reference(struct intel_context *ctx)
3173 kref_get(&ctx->ref);
3176 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3178 kref_put(&ctx->ref, i915_gem_context_free);
3181 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3183 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3186 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3187 struct drm_file *file);
3188 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3189 struct drm_file *file);
3190 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3191 struct drm_file *file_priv);
3192 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3193 struct drm_file *file_priv);
3195 /* i915_gem_evict.c */
3196 int __must_check i915_gem_evict_something(struct drm_device *dev,
3197 struct i915_address_space *vm,
3200 unsigned cache_level,
3201 unsigned long start,
3204 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3205 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3207 /* belongs in i915_gem_gtt.h */
3208 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3210 if (INTEL_INFO(dev)->gen < 6)
3211 intel_gtt_chipset_flush();
3214 /* i915_gem_stolen.c */
3215 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3216 struct drm_mm_node *node, u64 size,
3217 unsigned alignment);
3218 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3219 struct drm_mm_node *node, u64 size,
3220 unsigned alignment, u64 start,
3222 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3223 struct drm_mm_node *node);
3224 int i915_gem_init_stolen(struct drm_device *dev);
3225 void i915_gem_cleanup_stolen(struct drm_device *dev);
3226 struct drm_i915_gem_object *
3227 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3228 struct drm_i915_gem_object *
3229 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3234 /* i915_gem_shrinker.c */
3235 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3236 unsigned long target,
3238 #define I915_SHRINK_PURGEABLE 0x1
3239 #define I915_SHRINK_UNBOUND 0x2
3240 #define I915_SHRINK_BOUND 0x4
3241 #define I915_SHRINK_ACTIVE 0x8
3242 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3243 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3244 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3247 /* i915_gem_tiling.c */
3248 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3250 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3252 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3253 obj->tiling_mode != I915_TILING_NONE;
3256 /* i915_gem_debug.c */
3258 int i915_verify_lists(struct drm_device *dev);
3260 #define i915_verify_lists(dev) 0
3263 /* i915_debugfs.c */
3264 int i915_debugfs_init(struct drm_minor *minor);
3265 void i915_debugfs_cleanup(struct drm_minor *minor);
3266 #ifdef CONFIG_DEBUG_FS
3267 int i915_debugfs_connector_add(struct drm_connector *connector);
3268 void intel_display_crc_init(struct drm_device *dev);
3270 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3272 static inline void intel_display_crc_init(struct drm_device *dev) {}
3275 /* i915_gpu_error.c */
3277 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3278 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3279 const struct i915_error_state_file_priv *error);
3280 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3281 struct drm_i915_private *i915,
3282 size_t count, loff_t pos);
3283 static inline void i915_error_state_buf_release(
3284 struct drm_i915_error_state_buf *eb)
3288 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3289 const char *error_msg);
3290 void i915_error_state_get(struct drm_device *dev,
3291 struct i915_error_state_file_priv *error_priv);
3292 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3293 void i915_destroy_error_state(struct drm_device *dev);
3295 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3296 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3298 /* i915_cmd_parser.c */
3299 int i915_cmd_parser_get_version(void);
3300 int i915_cmd_parser_init_ring(struct intel_engine_cs *engine);
3301 void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine);
3302 bool i915_needs_cmd_parser(struct intel_engine_cs *engine);
3303 int i915_parse_cmds(struct intel_engine_cs *engine,
3304 struct drm_i915_gem_object *batch_obj,
3305 struct drm_i915_gem_object *shadow_batch_obj,
3306 u32 batch_start_offset,
3310 /* i915_suspend.c */
3311 extern int i915_save_state(struct drm_device *dev);
3312 extern int i915_restore_state(struct drm_device *dev);
3315 void i915_setup_sysfs(struct drm_device *dev_priv);
3316 void i915_teardown_sysfs(struct drm_device *dev_priv);
3319 extern int intel_setup_gmbus(struct drm_device *dev);
3320 extern void intel_teardown_gmbus(struct drm_device *dev);
3321 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3324 extern struct i2c_adapter *
3325 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3326 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3327 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3328 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3330 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3332 extern void intel_i2c_reset(struct drm_device *dev);
3335 int intel_bios_init(struct drm_i915_private *dev_priv);
3336 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3338 /* intel_opregion.c */
3340 extern int intel_opregion_setup(struct drm_device *dev);
3341 extern void intel_opregion_init(struct drm_device *dev);
3342 extern void intel_opregion_fini(struct drm_device *dev);
3343 extern void intel_opregion_asle_intr(struct drm_device *dev);
3344 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3346 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3349 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3350 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3351 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3352 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3354 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3359 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3367 extern void intel_register_dsm_handler(void);
3368 extern void intel_unregister_dsm_handler(void);
3370 static inline void intel_register_dsm_handler(void) { return; }
3371 static inline void intel_unregister_dsm_handler(void) { return; }
3372 #endif /* CONFIG_ACPI */
3375 extern void intel_modeset_init_hw(struct drm_device *dev);
3376 extern void intel_modeset_init(struct drm_device *dev);
3377 extern void intel_modeset_gem_init(struct drm_device *dev);
3378 extern void intel_modeset_cleanup(struct drm_device *dev);
3379 extern void intel_connector_unregister(struct intel_connector *);
3380 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3381 extern void intel_display_resume(struct drm_device *dev);
3382 extern void i915_redisable_vga(struct drm_device *dev);
3383 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3384 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3385 extern void intel_init_pch_refclk(struct drm_device *dev);
3386 extern void intel_set_rps(struct drm_device *dev, u8 val);
3387 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3389 extern void intel_detect_pch(struct drm_device *dev);
3390 extern int intel_enable_rc6(const struct drm_device *dev);
3392 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3393 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3394 struct drm_file *file);
3395 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3396 struct drm_file *file);
3399 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3400 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3401 struct intel_overlay_error_state *error);
3403 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3404 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3405 struct drm_device *dev,
3406 struct intel_display_error_state *error);
3408 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3409 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3411 /* intel_sideband.c */
3412 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3413 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3414 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3415 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3416 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3417 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3418 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3419 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3420 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3421 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3422 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3423 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3424 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3425 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3426 enum intel_sbi_destination destination);
3427 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3428 enum intel_sbi_destination destination);
3429 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3430 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3432 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3433 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3435 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3436 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3438 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3439 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3440 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3441 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3443 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3444 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3445 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3446 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3448 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3449 * will be implemented using 2 32-bit writes in an arbitrary order with
3450 * an arbitrary delay between them. This can cause the hardware to
3451 * act upon the intermediate value, possibly leading to corruption and
3452 * machine death. You have been warned.
3454 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3455 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3457 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3458 u32 upper, lower, old_upper, loop = 0; \
3459 upper = I915_READ(upper_reg); \
3461 old_upper = upper; \
3462 lower = I915_READ(lower_reg); \
3463 upper = I915_READ(upper_reg); \
3464 } while (upper != old_upper && loop++ < 2); \
3465 (u64)upper << 32 | lower; })
3467 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3468 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3470 #define __raw_read(x, s) \
3471 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3474 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3477 #define __raw_write(x, s) \
3478 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3479 i915_reg_t reg, uint##x##_t val) \
3481 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3496 /* These are untraced mmio-accessors that are only valid to be used inside
3497 * criticial sections inside IRQ handlers where forcewake is explicitly
3499 * Think twice, and think again, before using these.
3500 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3501 * intel_uncore_forcewake_irqunlock().
3503 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3504 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3505 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3507 /* "Broadcast RGB" property */
3508 #define INTEL_BROADCAST_RGB_AUTO 0
3509 #define INTEL_BROADCAST_RGB_FULL 1
3510 #define INTEL_BROADCAST_RGB_LIMITED 2
3512 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3514 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3515 return VLV_VGACNTRL;
3516 else if (INTEL_INFO(dev)->gen >= 5)
3517 return CPU_VGACNTRL;
3522 static inline void __user *to_user_ptr(u64 address)
3524 return (void __user *)(uintptr_t)address;
3527 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3529 unsigned long j = msecs_to_jiffies(m);
3531 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3534 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3536 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3539 static inline unsigned long
3540 timespec_to_jiffies_timeout(const struct timespec *value)
3542 unsigned long j = timespec_to_jiffies(value);
3544 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3548 * If you need to wait X milliseconds between events A and B, but event B
3549 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3550 * when event A happened, then just before event B you call this function and
3551 * pass the timestamp as the first argument, and X as the second argument.
3554 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3556 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3559 * Don't re-read the value of "jiffies" every time since it may change
3560 * behind our back and break the math.
3562 tmp_jiffies = jiffies;
3563 target_jiffies = timestamp_jiffies +
3564 msecs_to_jiffies_timeout(to_wait_ms);
3566 if (time_after(target_jiffies, tmp_jiffies)) {
3567 remaining_jiffies = target_jiffies - tmp_jiffies;
3568 while (remaining_jiffies)
3570 schedule_timeout_uninterruptible(remaining_jiffies);
3574 static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
3575 struct drm_i915_gem_request *req)
3577 if (engine->trace_irq_req == NULL && engine->irq_get(engine))
3578 i915_gem_request_assign(&engine->trace_irq_req, req);