1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
54 /* General customization:
57 #define DRIVER_NAME "i915"
58 #define DRIVER_DESC "Intel Graphics"
59 #define DRIVER_DATE "20150410"
62 /* Many gcc seem to no see through this and fall over :( */
64 #define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
74 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
76 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
77 (long) (x), __func__);
79 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
80 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
81 * which may not necessarily be a user visible problem. This will either
82 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
83 * enable distros and users to tailor their preferred amount of i915 abrt
86 #define I915_STATE_WARN(condition, format...) ({ \
87 int __ret_warn_on = !!(condition); \
88 if (unlikely(__ret_warn_on)) { \
89 if (i915.verbose_state_checks) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) { \
100 if (i915.verbose_state_checks) \
101 WARN(1, "WARN_ON(" #condition ")\n"); \
103 DRM_ERROR("WARN_ON(" #condition ")\n"); \
105 unlikely(__ret_warn_on); \
114 I915_MAX_PIPES = _PIPE_EDP
116 #define pipe_name(p) ((p) + 'A')
125 #define transcoder_name(t) ((t) + 'A')
128 * This is the maximum (across all platforms) number of planes (primary +
129 * sprites) that can be active at the same time on one pipe.
131 * This value doesn't count the cursor plane.
133 #define I915_MAX_PLANES 4
140 #define plane_name(p) ((p) + 'A')
142 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
152 #define port_name(p) ((p) + 'A')
154 #define I915_NUM_PHYS_VLV 2
166 enum intel_display_power_domain {
170 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
171 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
172 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
173 POWER_DOMAIN_TRANSCODER_A,
174 POWER_DOMAIN_TRANSCODER_B,
175 POWER_DOMAIN_TRANSCODER_C,
176 POWER_DOMAIN_TRANSCODER_EDP,
177 POWER_DOMAIN_PORT_DDI_A_2_LANES,
178 POWER_DOMAIN_PORT_DDI_A_4_LANES,
179 POWER_DOMAIN_PORT_DDI_B_2_LANES,
180 POWER_DOMAIN_PORT_DDI_B_4_LANES,
181 POWER_DOMAIN_PORT_DDI_C_2_LANES,
182 POWER_DOMAIN_PORT_DDI_C_4_LANES,
183 POWER_DOMAIN_PORT_DDI_D_2_LANES,
184 POWER_DOMAIN_PORT_DDI_D_4_LANES,
185 POWER_DOMAIN_PORT_DSI,
186 POWER_DOMAIN_PORT_CRT,
187 POWER_DOMAIN_PORT_OTHER,
200 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
201 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
202 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
203 #define POWER_DOMAIN_TRANSCODER(tran) \
204 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
205 (tran) + POWER_DOMAIN_TRANSCODER_A)
209 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
210 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
220 #define I915_GEM_GPU_DOMAINS \
221 (I915_GEM_DOMAIN_RENDER | \
222 I915_GEM_DOMAIN_SAMPLER | \
223 I915_GEM_DOMAIN_COMMAND | \
224 I915_GEM_DOMAIN_INSTRUCTION | \
225 I915_GEM_DOMAIN_VERTEX)
227 #define for_each_pipe(__dev_priv, __p) \
228 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
229 #define for_each_plane(__dev_priv, __pipe, __p) \
231 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
233 #define for_each_sprite(__dev_priv, __p, __s) \
235 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
238 #define for_each_crtc(dev, crtc) \
239 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
241 #define for_each_intel_crtc(dev, intel_crtc) \
242 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
244 #define for_each_intel_encoder(dev, intel_encoder) \
245 list_for_each_entry(intel_encoder, \
246 &(dev)->mode_config.encoder_list, \
249 #define for_each_intel_connector(dev, intel_connector) \
250 list_for_each_entry(intel_connector, \
251 &dev->mode_config.connector_list, \
254 #define for_each_digital_port(dev, digital_port) \
255 list_for_each_entry(digital_port, \
256 &dev->mode_config.encoder_list, \
259 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
260 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
261 if ((intel_encoder)->base.crtc == (__crtc))
263 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
264 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
265 if ((intel_connector)->base.encoder == (__encoder))
267 #define for_each_power_domain(domain, mask) \
268 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
269 if ((1 << (domain)) & (mask))
271 struct drm_i915_private;
272 struct i915_mm_struct;
273 struct i915_mmu_object;
276 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
277 /* real shared dpll ids must be >= 0 */
278 DPLL_ID_PCH_PLL_A = 0,
279 DPLL_ID_PCH_PLL_B = 1,
284 DPLL_ID_SKL_DPLL1 = 0,
285 DPLL_ID_SKL_DPLL2 = 1,
286 DPLL_ID_SKL_DPLL3 = 2,
288 #define I915_NUM_PLLS 3
290 struct intel_dpll_hw_state {
302 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
303 * lower part of crtl1 and they get shifted into position when writing
304 * the register. This allows us to easily compare the state to share
308 /* HDMI only, 0 when used for DP */
309 uint32_t cfgcr1, cfgcr2;
312 uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pcsdw12;
315 struct intel_shared_dpll_config {
316 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
317 struct intel_dpll_hw_state hw_state;
320 struct intel_shared_dpll {
321 struct intel_shared_dpll_config config;
322 struct intel_shared_dpll_config *new_config;
324 int active; /* count of number of active CRTCs (i.e. DPMS on) */
325 bool on; /* is the PLL actually active? Disabled during modeset */
327 /* should match the index in the dev_priv->shared_dplls array */
328 enum intel_dpll_id id;
329 /* The mode_set hook is optional and should be used together with the
330 * intel_prepare_shared_dpll function. */
331 void (*mode_set)(struct drm_i915_private *dev_priv,
332 struct intel_shared_dpll *pll);
333 void (*enable)(struct drm_i915_private *dev_priv,
334 struct intel_shared_dpll *pll);
335 void (*disable)(struct drm_i915_private *dev_priv,
336 struct intel_shared_dpll *pll);
337 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
338 struct intel_shared_dpll *pll,
339 struct intel_dpll_hw_state *hw_state);
347 /* Used by dp and fdi links */
348 struct intel_link_m_n {
356 void intel_link_compute_m_n(int bpp, int nlanes,
357 int pixel_clock, int link_clock,
358 struct intel_link_m_n *m_n);
360 /* Interface history:
363 * 1.2: Add Power Management
364 * 1.3: Add vblank support
365 * 1.4: Fix cmdbuffer path, add heap destroy
366 * 1.5: Add vblank pipe configuration
367 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
368 * - Support vertical blank on secondary display pipe
370 #define DRIVER_MAJOR 1
371 #define DRIVER_MINOR 6
372 #define DRIVER_PATCHLEVEL 0
374 #define WATCH_LISTS 0
376 struct opregion_header;
377 struct opregion_acpi;
378 struct opregion_swsci;
379 struct opregion_asle;
381 struct intel_opregion {
382 struct opregion_header __iomem *header;
383 struct opregion_acpi __iomem *acpi;
384 struct opregion_swsci __iomem *swsci;
385 u32 swsci_gbda_sub_functions;
386 u32 swsci_sbcb_sub_functions;
387 struct opregion_asle __iomem *asle;
389 u32 __iomem *lid_state;
390 struct work_struct asle_work;
392 #define OPREGION_SIZE (8*1024)
394 struct intel_overlay;
395 struct intel_overlay_error_state;
397 #define I915_FENCE_REG_NONE -1
398 #define I915_MAX_NUM_FENCES 32
399 /* 32 fences + sign bit for FENCE_REG_NONE */
400 #define I915_MAX_NUM_FENCE_BITS 6
402 struct drm_i915_fence_reg {
403 struct list_head lru_list;
404 struct drm_i915_gem_object *obj;
408 struct sdvo_device_mapping {
417 struct intel_display_error_state;
419 struct drm_i915_error_state {
427 /* Generic register state */
435 u32 error; /* gen6+ */
436 u32 err_int; /* gen7 */
437 u32 fault_data0; /* gen8, gen9 */
438 u32 fault_data1; /* gen8, gen9 */
444 u32 extra_instdone[I915_NUM_INSTDONE_REG];
445 u64 fence[I915_MAX_NUM_FENCES];
446 struct intel_overlay_error_state *overlay;
447 struct intel_display_error_state *display;
448 struct drm_i915_error_object *semaphore_obj;
450 struct drm_i915_error_ring {
452 /* Software tracked state */
455 enum intel_ring_hangcheck_action hangcheck_action;
458 /* our own tracking of ring head and tail */
462 u32 semaphore_seqno[I915_NUM_RINGS - 1];
481 u32 rc_psmi; /* sleep state */
482 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
484 struct drm_i915_error_object {
488 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
490 struct drm_i915_error_request {
505 char comm[TASK_COMM_LEN];
506 } ring[I915_NUM_RINGS];
508 struct drm_i915_error_buffer {
515 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
523 } **active_bo, **pinned_bo;
525 u32 *active_bo_count, *pinned_bo_count;
529 struct intel_connector;
530 struct intel_encoder;
531 struct intel_crtc_state;
532 struct intel_initial_plane_config;
537 struct drm_i915_display_funcs {
538 bool (*fbc_enabled)(struct drm_device *dev);
539 void (*enable_fbc)(struct drm_crtc *crtc);
540 void (*disable_fbc)(struct drm_device *dev);
541 int (*get_display_clock_speed)(struct drm_device *dev);
542 int (*get_fifo_size)(struct drm_device *dev, int plane);
544 * find_dpll() - Find the best values for the PLL
545 * @limit: limits for the PLL
546 * @crtc: current CRTC
547 * @target: target frequency in kHz
548 * @refclk: reference clock frequency in kHz
549 * @match_clock: if provided, @best_clock P divider must
550 * match the P divider from @match_clock
551 * used for LVDS downclocking
552 * @best_clock: best PLL values found
554 * Returns true on success, false on failure.
556 bool (*find_dpll)(const struct intel_limit *limit,
557 struct intel_crtc_state *crtc_state,
558 int target, int refclk,
559 struct dpll *match_clock,
560 struct dpll *best_clock);
561 void (*update_wm)(struct drm_crtc *crtc);
562 void (*update_sprite_wm)(struct drm_plane *plane,
563 struct drm_crtc *crtc,
564 uint32_t sprite_width, uint32_t sprite_height,
565 int pixel_size, bool enable, bool scaled);
566 void (*modeset_global_resources)(struct drm_atomic_state *state);
567 /* Returns the active state of the crtc, and if the crtc is active,
568 * fills out the pipe-config with the hw state. */
569 bool (*get_pipe_config)(struct intel_crtc *,
570 struct intel_crtc_state *);
571 void (*get_initial_plane_config)(struct intel_crtc *,
572 struct intel_initial_plane_config *);
573 int (*crtc_compute_clock)(struct intel_crtc *crtc,
574 struct intel_crtc_state *crtc_state);
575 void (*crtc_enable)(struct drm_crtc *crtc);
576 void (*crtc_disable)(struct drm_crtc *crtc);
577 void (*off)(struct drm_crtc *crtc);
578 void (*audio_codec_enable)(struct drm_connector *connector,
579 struct intel_encoder *encoder,
580 struct drm_display_mode *mode);
581 void (*audio_codec_disable)(struct intel_encoder *encoder);
582 void (*fdi_link_train)(struct drm_crtc *crtc);
583 void (*init_clock_gating)(struct drm_device *dev);
584 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
585 struct drm_framebuffer *fb,
586 struct drm_i915_gem_object *obj,
587 struct intel_engine_cs *ring,
589 void (*update_primary_plane)(struct drm_crtc *crtc,
590 struct drm_framebuffer *fb,
592 void (*hpd_irq_setup)(struct drm_device *dev);
593 /* clock updates for mode set */
595 /* render clock increase/decrease */
596 /* display clock increase/decrease */
597 /* pll clock increase/decrease */
599 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
600 uint32_t (*get_backlight)(struct intel_connector *connector);
601 void (*set_backlight)(struct intel_connector *connector,
603 void (*disable_backlight)(struct intel_connector *connector);
604 void (*enable_backlight)(struct intel_connector *connector);
607 enum forcewake_domain_id {
608 FW_DOMAIN_ID_RENDER = 0,
609 FW_DOMAIN_ID_BLITTER,
615 enum forcewake_domains {
616 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
617 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
618 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
619 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
624 struct intel_uncore_funcs {
625 void (*force_wake_get)(struct drm_i915_private *dev_priv,
626 enum forcewake_domains domains);
627 void (*force_wake_put)(struct drm_i915_private *dev_priv,
628 enum forcewake_domains domains);
630 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
631 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
632 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
633 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
635 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
636 uint8_t val, bool trace);
637 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
638 uint16_t val, bool trace);
639 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
640 uint32_t val, bool trace);
641 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
642 uint64_t val, bool trace);
645 struct intel_uncore {
646 spinlock_t lock; /** lock is also taken in irq contexts. */
648 struct intel_uncore_funcs funcs;
651 enum forcewake_domains fw_domains;
653 struct intel_uncore_forcewake_domain {
654 struct drm_i915_private *i915;
655 enum forcewake_domain_id id;
657 struct timer_list timer;
664 } fw_domain[FW_DOMAIN_ID_COUNT];
667 /* Iterate over initialised fw domains */
668 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
669 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
670 (i__) < FW_DOMAIN_ID_COUNT; \
671 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
672 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
674 #define for_each_fw_domain(domain__, dev_priv__, i__) \
675 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
677 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
678 func(is_mobile) sep \
681 func(is_i945gm) sep \
683 func(need_gfx_hws) sep \
685 func(is_pineview) sep \
686 func(is_broadwater) sep \
687 func(is_crestline) sep \
688 func(is_ivybridge) sep \
689 func(is_valleyview) sep \
690 func(is_haswell) sep \
691 func(is_skylake) sep \
692 func(is_preliminary) sep \
694 func(has_pipe_cxsr) sep \
695 func(has_hotplug) sep \
696 func(cursor_needs_physical) sep \
697 func(has_overlay) sep \
698 func(overlay_needs_physical) sep \
699 func(supports_tv) sep \
704 #define DEFINE_FLAG(name) u8 name:1
705 #define SEP_SEMICOLON ;
707 struct intel_device_info {
708 u32 display_mmio_offset;
711 u8 num_sprites[I915_MAX_PIPES];
713 u8 ring_mask; /* Rings supported by the HW */
714 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
715 /* Register offsets for the various display pipes and transcoders */
716 int pipe_offsets[I915_MAX_TRANSCODERS];
717 int trans_offsets[I915_MAX_TRANSCODERS];
718 int palette_offsets[I915_MAX_PIPES];
719 int cursor_offsets[I915_MAX_PIPES];
721 /* Slice/subslice/EU info */
724 u8 subslice_per_slice;
727 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
730 u8 has_subslice_pg:1;
737 enum i915_cache_level {
739 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
740 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
741 caches, eg sampler/render caches, and the
742 large Last-Level-Cache. LLC is coherent with
743 the CPU, but L3 is only visible to the GPU. */
744 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
747 struct i915_ctx_hang_stats {
748 /* This context had batch pending when hang was declared */
749 unsigned batch_pending;
751 /* This context had batch active when hang was declared */
752 unsigned batch_active;
754 /* Time when this context was last blamed for a GPU reset */
755 unsigned long guilty_ts;
757 /* If the contexts causes a second GPU hang within this time,
758 * it is permanently banned from submitting any more work.
760 unsigned long ban_period_seconds;
762 /* This context is banned to submit more work */
766 /* This must match up with the value previously used for execbuf2.rsvd1. */
767 #define DEFAULT_CONTEXT_HANDLE 0
769 * struct intel_context - as the name implies, represents a context.
770 * @ref: reference count.
771 * @user_handle: userspace tracking identity for this context.
772 * @remap_slice: l3 row remapping information.
773 * @file_priv: filp associated with this context (NULL for global default
775 * @hang_stats: information about the role of this context in possible GPU
777 * @ppgtt: virtual memory space used by this context.
778 * @legacy_hw_ctx: render context backing object and whether it is correctly
779 * initialized (legacy ring submission mechanism only).
780 * @link: link in the global list of contexts.
782 * Contexts are memory images used by the hardware to store copies of their
785 struct intel_context {
789 struct drm_i915_file_private *file_priv;
790 struct i915_ctx_hang_stats hang_stats;
791 struct i915_hw_ppgtt *ppgtt;
793 /* Legacy ring buffer submission */
795 struct drm_i915_gem_object *rcs_state;
800 bool rcs_initialized;
802 struct drm_i915_gem_object *state;
803 struct intel_ringbuffer *ringbuf;
805 } engine[I915_NUM_RINGS];
807 struct list_head link;
818 unsigned long uncompressed_size;
821 unsigned int possible_framebuffer_bits;
822 unsigned int busy_bits;
823 struct intel_crtc *crtc;
826 struct drm_mm_node compressed_fb;
827 struct drm_mm_node *compressed_llb;
831 /* Tracks whether the HW is actually enabled, not whether the feature is
835 struct intel_fbc_work {
836 struct delayed_work work;
837 struct drm_crtc *crtc;
838 struct drm_framebuffer *fb;
842 FBC_OK, /* FBC is enabled */
843 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
844 FBC_NO_OUTPUT, /* no outputs enabled to compress */
845 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
846 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
847 FBC_MODE_TOO_LARGE, /* mode too large for compression */
848 FBC_BAD_PLANE, /* fbc not supported on plane */
849 FBC_NOT_TILED, /* buffer not tiled */
850 FBC_MULTIPLE_PIPES, /* more than one pipe active */
852 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
857 * HIGH_RR is the highest eDP panel refresh rate read from EDID
858 * LOW_RR is the lowest eDP panel refresh rate found from EDID
859 * parsing for same resolution.
861 enum drrs_refresh_rate_type {
864 DRRS_MAX_RR, /* RR count */
867 enum drrs_support_type {
868 DRRS_NOT_SUPPORTED = 0,
869 STATIC_DRRS_SUPPORT = 1,
870 SEAMLESS_DRRS_SUPPORT = 2
876 struct delayed_work work;
878 unsigned busy_frontbuffer_bits;
879 enum drrs_refresh_rate_type refresh_rate_type;
880 enum drrs_support_type type;
887 struct intel_dp *enabled;
889 struct delayed_work work;
890 unsigned busy_frontbuffer_bits;
896 PCH_NONE = 0, /* No PCH present */
897 PCH_IBX, /* Ibexpeak PCH */
898 PCH_CPT, /* Cougarpoint PCH */
899 PCH_LPT, /* Lynxpoint PCH */
900 PCH_SPT, /* Sunrisepoint PCH */
904 enum intel_sbi_destination {
909 #define QUIRK_PIPEA_FORCE (1<<0)
910 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
911 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
912 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
913 #define QUIRK_PIPEB_FORCE (1<<4)
914 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
917 struct intel_fbc_work;
920 struct i2c_adapter adapter;
924 struct i2c_algo_bit_data bit_algo;
925 struct drm_i915_private *dev_priv;
928 struct i915_suspend_saved_registers {
931 u32 savePP_ON_DELAYS;
932 u32 savePP_OFF_DELAYS;
938 u32 saveCACHE_MODE_0;
939 u32 saveMI_ARB_STATE;
943 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
944 u32 savePCH_PORT_HOTPLUG;
948 struct vlv_s0ix_state {
955 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
956 u32 media_max_req_count;
957 u32 gfx_max_req_count;
989 /* Display 1 CZ domain */
994 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
996 /* GT SA CZ domain */
1003 /* Display 2 CZ domain */
1006 u32 clock_gate_dis2;
1009 struct intel_rps_ei {
1015 struct intel_gen6_power_mgmt {
1017 * work, interrupts_enabled and pm_iir are protected by
1018 * dev_priv->irq_lock
1020 struct work_struct work;
1021 bool interrupts_enabled;
1024 /* Frequencies are stored in potentially platform dependent multiples.
1025 * In other words, *_freq needs to be multiplied by X to be interesting.
1026 * Soft limits are those which are used for the dynamic reclocking done
1027 * by the driver (raise frequencies under heavy loads, and lower for
1028 * lighter loads). Hard limits are those imposed by the hardware.
1030 * A distinction is made for overclocking, which is never enabled by
1031 * default, and is considered to be above the hard limit if it's
1034 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1035 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1036 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1037 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1038 u8 min_freq; /* AKA RPn. Minimum frequency */
1039 u8 idle_freq; /* Frequency to request when we are idle */
1040 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1041 u8 rp1_freq; /* "less than" RP0 power/freqency */
1042 u8 rp0_freq; /* Non-overclocked max frequency. */
1045 u8 up_threshold; /* Current %busy required to uplock */
1046 u8 down_threshold; /* Current %busy required to downclock */
1049 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1052 struct delayed_work delayed_resume_work;
1053 struct list_head clients;
1056 /* manual wa residency calculations */
1057 struct intel_rps_ei up_ei, down_ei;
1060 * Protects RPS/RC6 register access and PCU communication.
1061 * Must be taken after struct_mutex if nested.
1063 struct mutex hw_lock;
1066 /* defined intel_pm.c */
1067 extern spinlock_t mchdev_lock;
1069 struct intel_ilk_power_mgmt {
1077 unsigned long last_time1;
1078 unsigned long chipset_power;
1081 unsigned long gfx_power;
1088 struct drm_i915_private;
1089 struct i915_power_well;
1091 struct i915_power_well_ops {
1093 * Synchronize the well's hw state to match the current sw state, for
1094 * example enable/disable it based on the current refcount. Called
1095 * during driver init and resume time, possibly after first calling
1096 * the enable/disable handlers.
1098 void (*sync_hw)(struct drm_i915_private *dev_priv,
1099 struct i915_power_well *power_well);
1101 * Enable the well and resources that depend on it (for example
1102 * interrupts located on the well). Called after the 0->1 refcount
1105 void (*enable)(struct drm_i915_private *dev_priv,
1106 struct i915_power_well *power_well);
1108 * Disable the well and resources that depend on it. Called after
1109 * the 1->0 refcount transition.
1111 void (*disable)(struct drm_i915_private *dev_priv,
1112 struct i915_power_well *power_well);
1113 /* Returns the hw enabled state. */
1114 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1115 struct i915_power_well *power_well);
1118 /* Power well structure for haswell */
1119 struct i915_power_well {
1122 /* power well enable/disable usage count */
1124 /* cached hw enabled state */
1126 unsigned long domains;
1128 const struct i915_power_well_ops *ops;
1131 struct i915_power_domains {
1133 * Power wells needed for initialization at driver init and suspend
1134 * time are on. They are kept on until after the first modeset.
1138 int power_well_count;
1141 int domain_use_count[POWER_DOMAIN_NUM];
1142 struct i915_power_well *power_wells;
1145 #define MAX_L3_SLICES 2
1146 struct intel_l3_parity {
1147 u32 *remap_info[MAX_L3_SLICES];
1148 struct work_struct error_work;
1152 struct i915_gem_mm {
1153 /** Memory allocator for GTT stolen memory */
1154 struct drm_mm stolen;
1155 /** List of all objects in gtt_space. Used to restore gtt
1156 * mappings on resume */
1157 struct list_head bound_list;
1159 * List of objects which are not bound to the GTT (thus
1160 * are idle and not used by the GPU) but still have
1161 * (presumably uncached) pages still attached.
1163 struct list_head unbound_list;
1165 /** Usable portion of the GTT for GEM */
1166 unsigned long stolen_base; /* limited to low memory (32-bit) */
1168 /** PPGTT used for aliasing the PPGTT with the GTT */
1169 struct i915_hw_ppgtt *aliasing_ppgtt;
1171 struct notifier_block oom_notifier;
1172 struct shrinker shrinker;
1173 bool shrinker_no_lock_stealing;
1175 /** LRU list of objects with fence regs on them. */
1176 struct list_head fence_list;
1179 * We leave the user IRQ off as much as possible,
1180 * but this means that requests will finish and never
1181 * be retired once the system goes idle. Set a timer to
1182 * fire periodically while the ring is running. When it
1183 * fires, go retire requests.
1185 struct delayed_work retire_work;
1188 * When we detect an idle GPU, we want to turn on
1189 * powersaving features. So once we see that there
1190 * are no more requests outstanding and no more
1191 * arrive within a small period of time, we fire
1192 * off the idle_work.
1194 struct delayed_work idle_work;
1197 * Are we in a non-interruptible section of code like
1203 * Is the GPU currently considered idle, or busy executing userspace
1204 * requests? Whilst idle, we attempt to power down the hardware and
1205 * display clocks. In order to reduce the effect on performance, there
1206 * is a slight delay before we do so.
1210 /* the indicator for dispatch video commands on two BSD rings */
1211 int bsd_ring_dispatch_index;
1213 /** Bit 6 swizzling required for X tiling */
1214 uint32_t bit_6_swizzle_x;
1215 /** Bit 6 swizzling required for Y tiling */
1216 uint32_t bit_6_swizzle_y;
1218 /* accounting, useful for userland debugging */
1219 spinlock_t object_stat_lock;
1220 size_t object_memory;
1224 struct drm_i915_error_state_buf {
1225 struct drm_i915_private *i915;
1234 struct i915_error_state_file_priv {
1235 struct drm_device *dev;
1236 struct drm_i915_error_state *error;
1239 struct i915_gpu_error {
1240 /* For hangcheck timer */
1241 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1242 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1243 /* Hang gpu twice in this window and your context gets banned */
1244 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1246 struct workqueue_struct *hangcheck_wq;
1247 struct delayed_work hangcheck_work;
1249 /* For reset and error_state handling. */
1251 /* Protected by the above dev->gpu_error.lock. */
1252 struct drm_i915_error_state *first_error;
1254 unsigned long missed_irq_rings;
1257 * State variable controlling the reset flow and count
1259 * This is a counter which gets incremented when reset is triggered,
1260 * and again when reset has been handled. So odd values (lowest bit set)
1261 * means that reset is in progress and even values that
1262 * (reset_counter >> 1):th reset was successfully completed.
1264 * If reset is not completed succesfully, the I915_WEDGE bit is
1265 * set meaning that hardware is terminally sour and there is no
1266 * recovery. All waiters on the reset_queue will be woken when
1269 * This counter is used by the wait_seqno code to notice that reset
1270 * event happened and it needs to restart the entire ioctl (since most
1271 * likely the seqno it waited for won't ever signal anytime soon).
1273 * This is important for lock-free wait paths, where no contended lock
1274 * naturally enforces the correct ordering between the bail-out of the
1275 * waiter and the gpu reset work code.
1277 atomic_t reset_counter;
1279 #define I915_RESET_IN_PROGRESS_FLAG 1
1280 #define I915_WEDGED (1 << 31)
1283 * Waitqueue to signal when the reset has completed. Used by clients
1284 * that wait for dev_priv->mm.wedged to settle.
1286 wait_queue_head_t reset_queue;
1288 /* Userspace knobs for gpu hang simulation;
1289 * combines both a ring mask, and extra flags
1292 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1293 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1295 /* For missed irq/seqno simulation. */
1296 unsigned int test_irq_rings;
1298 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1299 bool reload_in_reset;
1302 enum modeset_restore {
1303 MODESET_ON_LID_OPEN,
1308 struct ddi_vbt_port_info {
1310 * This is an index in the HDMI/DVI DDI buffer translation table.
1311 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1312 * populate this field.
1314 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1315 uint8_t hdmi_level_shift;
1317 uint8_t supports_dvi:1;
1318 uint8_t supports_hdmi:1;
1319 uint8_t supports_dp:1;
1322 enum psr_lines_to_wait {
1323 PSR_0_LINES_TO_WAIT = 0,
1325 PSR_4_LINES_TO_WAIT,
1329 struct intel_vbt_data {
1330 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1331 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1334 unsigned int int_tv_support:1;
1335 unsigned int lvds_dither:1;
1336 unsigned int lvds_vbt:1;
1337 unsigned int int_crt_support:1;
1338 unsigned int lvds_use_ssc:1;
1339 unsigned int display_clock_mode:1;
1340 unsigned int fdi_rx_polarity_inverted:1;
1341 unsigned int has_mipi:1;
1343 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1345 enum drrs_support_type drrs_type;
1350 int edp_preemphasis;
1352 bool edp_initialized;
1355 bool edp_low_vswing;
1356 struct edp_power_seq edp_pps;
1360 bool require_aux_wakeup;
1362 enum psr_lines_to_wait lines_to_wait;
1363 int tp1_wakeup_time;
1364 int tp2_tp3_wakeup_time;
1370 bool active_low_pwm;
1371 u8 min_brightness; /* min_brightness/255 of max */
1378 struct mipi_config *config;
1379 struct mipi_pps_data *pps;
1383 u8 *sequence[MIPI_SEQ_MAX];
1389 union child_device_config *child_dev;
1391 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1394 enum intel_ddb_partitioning {
1396 INTEL_DDB_PART_5_6, /* IVB+ */
1399 struct intel_wm_level {
1407 struct ilk_wm_values {
1408 uint32_t wm_pipe[3];
1410 uint32_t wm_lp_spr[3];
1411 uint32_t wm_linetime[3];
1413 enum intel_ddb_partitioning partitioning;
1416 struct vlv_wm_values {
1435 struct skl_ddb_entry {
1436 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1439 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1441 return entry->end - entry->start;
1444 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1445 const struct skl_ddb_entry *e2)
1447 if (e1->start == e2->start && e1->end == e2->end)
1453 struct skl_ddb_allocation {
1454 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1455 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1456 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1459 struct skl_wm_values {
1460 bool dirty[I915_MAX_PIPES];
1461 struct skl_ddb_allocation ddb;
1462 uint32_t wm_linetime[I915_MAX_PIPES];
1463 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1464 uint32_t cursor[I915_MAX_PIPES][8];
1465 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1466 uint32_t cursor_trans[I915_MAX_PIPES];
1469 struct skl_wm_level {
1470 bool plane_en[I915_MAX_PLANES];
1472 uint16_t plane_res_b[I915_MAX_PLANES];
1473 uint8_t plane_res_l[I915_MAX_PLANES];
1474 uint16_t cursor_res_b;
1475 uint8_t cursor_res_l;
1479 * This struct helps tracking the state needed for runtime PM, which puts the
1480 * device in PCI D3 state. Notice that when this happens, nothing on the
1481 * graphics device works, even register access, so we don't get interrupts nor
1484 * Every piece of our code that needs to actually touch the hardware needs to
1485 * either call intel_runtime_pm_get or call intel_display_power_get with the
1486 * appropriate power domain.
1488 * Our driver uses the autosuspend delay feature, which means we'll only really
1489 * suspend if we stay with zero refcount for a certain amount of time. The
1490 * default value is currently very conservative (see intel_runtime_pm_enable), but
1491 * it can be changed with the standard runtime PM files from sysfs.
1493 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1494 * goes back to false exactly before we reenable the IRQs. We use this variable
1495 * to check if someone is trying to enable/disable IRQs while they're supposed
1496 * to be disabled. This shouldn't happen and we'll print some error messages in
1499 * For more, read the Documentation/power/runtime_pm.txt.
1501 struct i915_runtime_pm {
1506 enum intel_pipe_crc_source {
1507 INTEL_PIPE_CRC_SOURCE_NONE,
1508 INTEL_PIPE_CRC_SOURCE_PLANE1,
1509 INTEL_PIPE_CRC_SOURCE_PLANE2,
1510 INTEL_PIPE_CRC_SOURCE_PF,
1511 INTEL_PIPE_CRC_SOURCE_PIPE,
1512 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1513 INTEL_PIPE_CRC_SOURCE_TV,
1514 INTEL_PIPE_CRC_SOURCE_DP_B,
1515 INTEL_PIPE_CRC_SOURCE_DP_C,
1516 INTEL_PIPE_CRC_SOURCE_DP_D,
1517 INTEL_PIPE_CRC_SOURCE_AUTO,
1518 INTEL_PIPE_CRC_SOURCE_MAX,
1521 struct intel_pipe_crc_entry {
1526 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1527 struct intel_pipe_crc {
1529 bool opened; /* exclusive access to the result file */
1530 struct intel_pipe_crc_entry *entries;
1531 enum intel_pipe_crc_source source;
1533 wait_queue_head_t wq;
1536 struct i915_frontbuffer_tracking {
1540 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1547 struct i915_wa_reg {
1550 /* bitmask representing WA bits */
1554 #define I915_MAX_WA_REGS 16
1556 struct i915_workarounds {
1557 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1561 struct i915_virtual_gpu {
1565 struct drm_i915_private {
1566 struct drm_device *dev;
1567 struct kmem_cache *objects;
1568 struct kmem_cache *vmas;
1569 struct kmem_cache *requests;
1571 const struct intel_device_info info;
1573 int relative_constants_mode;
1577 struct intel_uncore uncore;
1579 struct i915_virtual_gpu vgpu;
1581 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1583 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1584 * controller on different i2c buses. */
1585 struct mutex gmbus_mutex;
1588 * Base address of the gmbus and gpio block.
1590 uint32_t gpio_mmio_base;
1592 /* MMIO base address for MIPI regs */
1593 uint32_t mipi_mmio_base;
1595 wait_queue_head_t gmbus_wait_queue;
1597 struct pci_dev *bridge_dev;
1598 struct intel_engine_cs ring[I915_NUM_RINGS];
1599 struct drm_i915_gem_object *semaphore_obj;
1600 uint32_t last_seqno, next_seqno;
1602 struct drm_dma_handle *status_page_dmah;
1603 struct resource mch_res;
1605 /* protects the irq masks */
1606 spinlock_t irq_lock;
1608 /* protects the mmio flip data */
1609 spinlock_t mmio_flip_lock;
1611 bool display_irqs_enabled;
1613 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1614 struct pm_qos_request pm_qos;
1616 /* DPIO indirect register protection */
1617 struct mutex dpio_lock;
1619 /** Cached value of IMR to avoid reads in updating the bitfield */
1622 u32 de_irq_mask[I915_MAX_PIPES];
1627 u32 pipestat_irq_mask[I915_MAX_PIPES];
1629 struct work_struct hotplug_work;
1631 unsigned long hpd_last_jiffies;
1636 HPD_MARK_DISABLED = 2
1638 } hpd_stats[HPD_NUM_PINS];
1640 struct delayed_work hotplug_reenable_work;
1642 struct i915_fbc fbc;
1643 struct i915_drrs drrs;
1644 struct intel_opregion opregion;
1645 struct intel_vbt_data vbt;
1647 bool preserve_bios_swizzle;
1650 struct intel_overlay *overlay;
1652 /* backlight registers and fields in struct intel_panel */
1653 struct mutex backlight_lock;
1656 bool no_aux_handshake;
1658 /* protects panel power sequencer state */
1659 struct mutex pps_mutex;
1661 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1662 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1663 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1665 unsigned int fsb_freq, mem_freq, is_ddr3;
1666 unsigned int cdclk_freq;
1667 unsigned int hpll_freq;
1670 * wq - Driver workqueue for GEM.
1672 * NOTE: Work items scheduled here are not allowed to grab any modeset
1673 * locks, for otherwise the flushing done in the pageflip code will
1674 * result in deadlocks.
1676 struct workqueue_struct *wq;
1678 /* Display functions */
1679 struct drm_i915_display_funcs display;
1681 /* PCH chipset type */
1682 enum intel_pch pch_type;
1683 unsigned short pch_id;
1685 unsigned long quirks;
1687 enum modeset_restore modeset_restore;
1688 struct mutex modeset_restore_lock;
1690 struct list_head vm_list; /* Global list of all address spaces */
1691 struct i915_gtt gtt; /* VM representing the global address space */
1693 struct i915_gem_mm mm;
1694 DECLARE_HASHTABLE(mm_structs, 7);
1695 struct mutex mm_lock;
1697 /* Kernel Modesetting */
1699 struct sdvo_device_mapping sdvo_mappings[2];
1701 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1702 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1703 wait_queue_head_t pending_flip_queue;
1705 #ifdef CONFIG_DEBUG_FS
1706 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1709 int num_shared_dpll;
1710 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1711 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1713 struct i915_workarounds workarounds;
1715 /* Reclocking support */
1716 bool render_reclock_avail;
1717 bool lvds_downclock_avail;
1718 /* indicates the reduced downclock for LVDS*/
1721 struct i915_frontbuffer_tracking fb_tracking;
1725 bool mchbar_need_disable;
1727 struct intel_l3_parity l3_parity;
1729 /* Cannot be determined by PCIID. You must always read a register. */
1732 /* gen6+ rps state */
1733 struct intel_gen6_power_mgmt rps;
1735 /* ilk-only ips/rps state. Everything in here is protected by the global
1736 * mchdev_lock in intel_pm.c */
1737 struct intel_ilk_power_mgmt ips;
1739 struct i915_power_domains power_domains;
1741 struct i915_psr psr;
1743 struct i915_gpu_error gpu_error;
1745 struct drm_i915_gem_object *vlv_pctx;
1747 #ifdef CONFIG_DRM_I915_FBDEV
1748 /* list of fbdev register on this device */
1749 struct intel_fbdev *fbdev;
1750 struct work_struct fbdev_suspend_work;
1753 struct drm_property *broadcast_rgb_property;
1754 struct drm_property *force_audio_property;
1756 /* hda/i915 audio component */
1757 bool audio_component_registered;
1759 uint32_t hw_context_size;
1760 struct list_head context_list;
1765 struct i915_suspend_saved_registers regfile;
1766 struct vlv_s0ix_state vlv_s0ix_state;
1770 * Raw watermark latency values:
1771 * in 0.1us units for WM0,
1772 * in 0.5us units for WM1+.
1775 uint16_t pri_latency[5];
1777 uint16_t spr_latency[5];
1779 uint16_t cur_latency[5];
1781 * Raw watermark memory latency values
1782 * for SKL for all 8 levels
1785 uint16_t skl_latency[8];
1788 * The skl_wm_values structure is a bit too big for stack
1789 * allocation, so we keep the staging struct where we store
1790 * intermediate results here instead.
1792 struct skl_wm_values skl_results;
1794 /* current hardware state */
1796 struct ilk_wm_values hw;
1797 struct skl_wm_values skl_hw;
1798 struct vlv_wm_values vlv;
1802 struct i915_runtime_pm pm;
1804 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1805 u32 long_hpd_port_mask;
1806 u32 short_hpd_port_mask;
1807 struct work_struct dig_port_work;
1810 * if we get a HPD irq from DP and a HPD irq from non-DP
1811 * the non-DP HPD could block the workqueue on a mode config
1812 * mutex getting, that userspace may have taken. However
1813 * userspace is waiting on the DP workqueue to run which is
1814 * blocked behind the non-DP one.
1816 struct workqueue_struct *dp_wq;
1818 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1820 int (*execbuf_submit)(struct drm_device *dev, struct drm_file *file,
1821 struct intel_engine_cs *ring,
1822 struct intel_context *ctx,
1823 struct drm_i915_gem_execbuffer2 *args,
1824 struct list_head *vmas,
1825 struct drm_i915_gem_object *batch_obj,
1826 u64 exec_start, u32 flags);
1827 int (*init_rings)(struct drm_device *dev);
1828 void (*cleanup_ring)(struct intel_engine_cs *ring);
1829 void (*stop_ring)(struct intel_engine_cs *ring);
1833 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1834 * will be rejected. Instead look for a better place.
1838 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1840 return dev->dev_private;
1843 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1845 return to_i915(dev_get_drvdata(dev));
1848 /* Iterate over initialised rings */
1849 #define for_each_ring(ring__, dev_priv__, i__) \
1850 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1851 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1853 enum hdmi_force_audio {
1854 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1855 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1856 HDMI_AUDIO_AUTO, /* trust EDID */
1857 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1860 #define I915_GTT_OFFSET_NONE ((u32)-1)
1862 struct drm_i915_gem_object_ops {
1863 /* Interface between the GEM object and its backing storage.
1864 * get_pages() is called once prior to the use of the associated set
1865 * of pages before to binding them into the GTT, and put_pages() is
1866 * called after we no longer need them. As we expect there to be
1867 * associated cost with migrating pages between the backing storage
1868 * and making them available for the GPU (e.g. clflush), we may hold
1869 * onto the pages after they are no longer referenced by the GPU
1870 * in case they may be used again shortly (for example migrating the
1871 * pages to a different memory domain within the GTT). put_pages()
1872 * will therefore most likely be called when the object itself is
1873 * being released or under memory pressure (where we attempt to
1874 * reap pages for the shrinker).
1876 int (*get_pages)(struct drm_i915_gem_object *);
1877 void (*put_pages)(struct drm_i915_gem_object *);
1878 int (*dmabuf_export)(struct drm_i915_gem_object *);
1879 void (*release)(struct drm_i915_gem_object *);
1883 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1884 * considered to be the frontbuffer for the given plane interface-vise. This
1885 * doesn't mean that the hw necessarily already scans it out, but that any
1886 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1888 * We have one bit per pipe and per scanout plane type.
1890 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1891 #define INTEL_FRONTBUFFER_BITS \
1892 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1893 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1894 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1895 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1896 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1897 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1898 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1899 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1900 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1901 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1902 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1904 struct drm_i915_gem_object {
1905 struct drm_gem_object base;
1907 const struct drm_i915_gem_object_ops *ops;
1909 /** List of VMAs backed by this object */
1910 struct list_head vma_list;
1912 /** Stolen memory for this object, instead of being backed by shmem. */
1913 struct drm_mm_node *stolen;
1914 struct list_head global_list;
1916 struct list_head ring_list;
1917 /** Used in execbuf to temporarily hold a ref */
1918 struct list_head obj_exec_link;
1920 struct list_head batch_pool_link;
1923 * This is set if the object is on the active lists (has pending
1924 * rendering and so a non-zero seqno), and is not set if it i s on
1925 * inactive (ready to be unbound) list.
1927 unsigned int active:1;
1930 * This is set if the object has been written to since last bound
1933 unsigned int dirty:1;
1936 * Fence register bits (if any) for this object. Will be set
1937 * as needed when mapped into the GTT.
1938 * Protected by dev->struct_mutex.
1940 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1943 * Advice: are the backing pages purgeable?
1945 unsigned int madv:2;
1948 * Current tiling mode for the object.
1950 unsigned int tiling_mode:2;
1952 * Whether the tiling parameters for the currently associated fence
1953 * register have changed. Note that for the purposes of tracking
1954 * tiling changes we also treat the unfenced register, the register
1955 * slot that the object occupies whilst it executes a fenced
1956 * command (such as BLT on gen2/3), as a "fence".
1958 unsigned int fence_dirty:1;
1961 * Is the object at the current location in the gtt mappable and
1962 * fenceable? Used to avoid costly recalculations.
1964 unsigned int map_and_fenceable:1;
1967 * Whether the current gtt mapping needs to be mappable (and isn't just
1968 * mappable by accident). Track pin and fault separate for a more
1969 * accurate mappable working set.
1971 unsigned int fault_mappable:1;
1974 * Is the object to be mapped as read-only to the GPU
1975 * Only honoured if hardware has relevant pte bit
1977 unsigned long gt_ro:1;
1978 unsigned int cache_level:3;
1979 unsigned int cache_dirty:1;
1981 unsigned int has_dma_mapping:1;
1983 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1985 unsigned int pin_display;
1987 struct sg_table *pages;
1988 int pages_pin_count;
1990 struct scatterlist *sg;
1994 /* prime dma-buf support */
1995 void *dma_buf_vmapping;
1998 /** Breadcrumb of last rendering to the buffer. */
1999 struct drm_i915_gem_request *last_read_req;
2000 struct drm_i915_gem_request *last_write_req;
2001 /** Breadcrumb of last fenced GPU access to the buffer. */
2002 struct drm_i915_gem_request *last_fenced_req;
2004 /** Current tiling stride for the object, if it's tiled. */
2007 /** References from framebuffers, locks out tiling changes. */
2008 unsigned long framebuffer_references;
2010 /** Record of address bit 17 of each page at last unbind. */
2011 unsigned long *bit_17;
2014 /** for phy allocated objects */
2015 struct drm_dma_handle *phys_handle;
2017 struct i915_gem_userptr {
2019 unsigned read_only :1;
2020 unsigned workers :4;
2021 #define I915_GEM_USERPTR_MAX_WORKERS 15
2023 struct i915_mm_struct *mm;
2024 struct i915_mmu_object *mmu_object;
2025 struct work_struct *work;
2029 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2031 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2032 struct drm_i915_gem_object *new,
2033 unsigned frontbuffer_bits);
2036 * Request queue structure.
2038 * The request queue allows us to note sequence numbers that have been emitted
2039 * and may be associated with active buffers to be retired.
2041 * By keeping this list, we can avoid having to do questionable sequence
2042 * number comparisons on buffer last_read|write_seqno. It also allows an
2043 * emission time to be associated with the request for tracking how far ahead
2044 * of the GPU the submission is.
2046 * The requests are reference counted, so upon creation they should have an
2047 * initial reference taken using kref_init
2049 struct drm_i915_gem_request {
2052 /** On Which ring this request was generated */
2053 struct drm_i915_private *i915;
2054 struct intel_engine_cs *ring;
2056 /** GEM sequence number associated with this request. */
2059 /** Position in the ringbuffer of the start of the request */
2063 * Position in the ringbuffer of the start of the postfix.
2064 * This is required to calculate the maximum available ringbuffer
2065 * space without overwriting the postfix.
2069 /** Position in the ringbuffer of the end of the whole request */
2073 * Context and ring buffer related to this request
2074 * Contexts are refcounted, so when this request is associated with a
2075 * context, we must increment the context's refcount, to guarantee that
2076 * it persists while any request is linked to it. Requests themselves
2077 * are also refcounted, so the request will only be freed when the last
2078 * reference to it is dismissed, and the code in
2079 * i915_gem_request_free() will then decrement the refcount on the
2082 struct intel_context *ctx;
2083 struct intel_ringbuffer *ringbuf;
2085 /** Batch buffer related to this request if any */
2086 struct drm_i915_gem_object *batch_obj;
2088 /** Time at which this request was emitted, in jiffies. */
2089 unsigned long emitted_jiffies;
2091 /** global list entry for this request */
2092 struct list_head list;
2094 struct drm_i915_file_private *file_priv;
2095 /** file_priv list entry for this request */
2096 struct list_head client_list;
2098 /** process identifier submitting this request */
2102 * The ELSP only accepts two elements at a time, so we queue
2103 * context/tail pairs on a given queue (ring->execlist_queue) until the
2104 * hardware is available. The queue serves a double purpose: we also use
2105 * it to keep track of the up to 2 contexts currently in the hardware
2106 * (usually one in execution and the other queued up by the GPU): We
2107 * only remove elements from the head of the queue when the hardware
2108 * informs us that an element has been completed.
2110 * All accesses to the queue are mediated by a spinlock
2111 * (ring->execlist_lock).
2114 /** Execlist link in the submission queue.*/
2115 struct list_head execlist_link;
2117 /** Execlists no. of times this request has been sent to the ELSP */
2122 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2123 struct intel_context *ctx);
2124 void i915_gem_request_free(struct kref *req_ref);
2126 static inline uint32_t
2127 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2129 return req ? req->seqno : 0;
2132 static inline struct intel_engine_cs *
2133 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2135 return req ? req->ring : NULL;
2139 i915_gem_request_reference(struct drm_i915_gem_request *req)
2141 kref_get(&req->ref);
2145 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2147 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2148 kref_put(&req->ref, i915_gem_request_free);
2152 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2154 struct drm_device *dev;
2159 dev = req->ring->dev;
2160 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2161 mutex_unlock(&dev->struct_mutex);
2164 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2165 struct drm_i915_gem_request *src)
2168 i915_gem_request_reference(src);
2171 i915_gem_request_unreference(*pdst);
2177 * XXX: i915_gem_request_completed should be here but currently needs the
2178 * definition of i915_seqno_passed() which is below. It will be moved in
2179 * a later patch when the call to i915_seqno_passed() is obsoleted...
2182 struct drm_i915_file_private {
2183 struct drm_i915_private *dev_priv;
2184 struct drm_file *file;
2188 struct list_head request_list;
2190 struct idr context_idr;
2192 struct list_head rps_boost;
2193 struct intel_engine_cs *bsd_ring;
2195 unsigned rps_boosts;
2199 * A command that requires special handling by the command parser.
2201 struct drm_i915_cmd_descriptor {
2203 * Flags describing how the command parser processes the command.
2205 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2206 * a length mask if not set
2207 * CMD_DESC_SKIP: The command is allowed but does not follow the
2208 * standard length encoding for the opcode range in
2210 * CMD_DESC_REJECT: The command is never allowed
2211 * CMD_DESC_REGISTER: The command should be checked against the
2212 * register whitelist for the appropriate ring
2213 * CMD_DESC_MASTER: The command is allowed if the submitting process
2217 #define CMD_DESC_FIXED (1<<0)
2218 #define CMD_DESC_SKIP (1<<1)
2219 #define CMD_DESC_REJECT (1<<2)
2220 #define CMD_DESC_REGISTER (1<<3)
2221 #define CMD_DESC_BITMASK (1<<4)
2222 #define CMD_DESC_MASTER (1<<5)
2225 * The command's unique identification bits and the bitmask to get them.
2226 * This isn't strictly the opcode field as defined in the spec and may
2227 * also include type, subtype, and/or subop fields.
2235 * The command's length. The command is either fixed length (i.e. does
2236 * not include a length field) or has a length field mask. The flag
2237 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2238 * a length mask. All command entries in a command table must include
2239 * length information.
2247 * Describes where to find a register address in the command to check
2248 * against the ring's register whitelist. Only valid if flags has the
2249 * CMD_DESC_REGISTER bit set.
2256 #define MAX_CMD_DESC_BITMASKS 3
2258 * Describes command checks where a particular dword is masked and
2259 * compared against an expected value. If the command does not match
2260 * the expected value, the parser rejects it. Only valid if flags has
2261 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2264 * If the check specifies a non-zero condition_mask then the parser
2265 * only performs the check when the bits specified by condition_mask
2272 u32 condition_offset;
2274 } bits[MAX_CMD_DESC_BITMASKS];
2278 * A table of commands requiring special handling by the command parser.
2280 * Each ring has an array of tables. Each table consists of an array of command
2281 * descriptors, which must be sorted with command opcodes in ascending order.
2283 struct drm_i915_cmd_table {
2284 const struct drm_i915_cmd_descriptor *table;
2288 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2289 #define __I915__(p) ({ \
2290 struct drm_i915_private *__p; \
2291 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2292 __p = (struct drm_i915_private *)p; \
2293 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2294 __p = to_i915((struct drm_device *)p); \
2299 #define INTEL_INFO(p) (&__I915__(p)->info)
2300 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2301 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2303 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2304 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2305 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2306 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2307 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2308 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2309 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2310 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2311 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2312 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2313 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2314 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2315 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2316 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2317 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2318 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2319 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2320 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2321 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2322 INTEL_DEVID(dev) == 0x0152 || \
2323 INTEL_DEVID(dev) == 0x015a)
2324 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2325 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2326 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2327 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2328 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2329 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2330 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2331 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2332 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2333 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2334 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2335 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2336 (INTEL_DEVID(dev) & 0xf) == 0xe))
2337 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2338 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2339 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2340 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2341 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2342 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2343 /* ULX machines are also considered ULT. */
2344 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2345 INTEL_DEVID(dev) == 0x0A1E)
2346 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2348 #define SKL_REVID_A0 (0x0)
2349 #define SKL_REVID_B0 (0x1)
2350 #define SKL_REVID_C0 (0x2)
2351 #define SKL_REVID_D0 (0x3)
2352 #define SKL_REVID_E0 (0x4)
2354 #define BXT_REVID_A0 (0x0)
2355 #define BXT_REVID_B0 (0x3)
2356 #define BXT_REVID_C0 (0x6)
2359 * The genX designation typically refers to the render engine, so render
2360 * capability related checks should use IS_GEN, while display and other checks
2361 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2364 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2365 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2366 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2367 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2368 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2369 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2370 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2371 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2373 #define RENDER_RING (1<<RCS)
2374 #define BSD_RING (1<<VCS)
2375 #define BLT_RING (1<<BCS)
2376 #define VEBOX_RING (1<<VECS)
2377 #define BSD2_RING (1<<VCS2)
2378 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2379 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2380 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2381 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2382 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2383 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2384 __I915__(dev)->ellc_size)
2385 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2387 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2388 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2389 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2390 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2392 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2393 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2395 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2396 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2398 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2399 * even when in MSI mode. This results in spurious interrupt warnings if the
2400 * legacy irq no. is shared with another device. The kernel then disables that
2401 * interrupt source and so prevents the other device from working properly.
2403 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2404 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2406 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2407 * rows, which changed the alignment requirements and fence programming.
2409 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2411 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2412 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2413 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2414 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2415 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2417 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2418 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2419 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2421 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2423 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2424 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2425 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2426 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2428 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2429 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2430 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2431 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2433 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2434 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2435 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2436 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2437 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2438 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2439 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2440 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2442 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2443 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2444 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2445 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2446 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2447 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2448 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2450 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2452 /* DPF == dynamic parity feature */
2453 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2454 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2456 #define GT_FREQUENCY_MULTIPLIER 50
2457 #define GEN9_FREQ_SCALER 3
2459 #include "i915_trace.h"
2461 extern const struct drm_ioctl_desc i915_ioctls[];
2462 extern int i915_max_ioctl;
2464 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2465 extern int i915_resume_legacy(struct drm_device *dev);
2468 struct i915_params {
2470 int panel_ignore_lid;
2472 unsigned int lvds_downclock;
2473 int lvds_channel_mode;
2475 int vbt_sdvo_panel_type;
2479 int enable_execlists;
2481 unsigned int preliminary_hw_support;
2482 int disable_power_well;
2484 int invert_brightness;
2485 int enable_cmd_parser;
2486 /* leave bools at the end to not create holes */
2487 bool enable_hangcheck;
2489 bool prefault_disable;
2490 bool load_detect_test;
2492 bool disable_display;
2493 bool disable_vtd_wa;
2496 bool verbose_state_checks;
2497 bool nuclear_pageflip;
2499 extern struct i915_params i915 __read_mostly;
2502 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2503 extern int i915_driver_unload(struct drm_device *);
2504 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2505 extern void i915_driver_lastclose(struct drm_device * dev);
2506 extern void i915_driver_preclose(struct drm_device *dev,
2507 struct drm_file *file);
2508 extern void i915_driver_postclose(struct drm_device *dev,
2509 struct drm_file *file);
2510 extern int i915_driver_device_is_agp(struct drm_device * dev);
2511 #ifdef CONFIG_COMPAT
2512 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2515 extern int intel_gpu_reset(struct drm_device *dev);
2516 extern int i915_reset(struct drm_device *dev);
2517 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2518 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2519 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2520 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2521 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2522 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2525 void i915_queue_hangcheck(struct drm_device *dev);
2527 void i915_handle_error(struct drm_device *dev, bool wedged,
2528 const char *fmt, ...);
2530 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2531 extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2532 int intel_irq_install(struct drm_i915_private *dev_priv);
2533 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2535 extern void intel_uncore_sanitize(struct drm_device *dev);
2536 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2537 bool restore_forcewake);
2538 extern void intel_uncore_init(struct drm_device *dev);
2539 extern void intel_uncore_check_errors(struct drm_device *dev);
2540 extern void intel_uncore_fini(struct drm_device *dev);
2541 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2542 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2543 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2544 enum forcewake_domains domains);
2545 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2546 enum forcewake_domains domains);
2547 /* Like above but the caller must manage the uncore.lock itself.
2548 * Must be used with I915_READ_FW and friends.
2550 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2551 enum forcewake_domains domains);
2552 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2553 enum forcewake_domains domains);
2554 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2555 static inline bool intel_vgpu_active(struct drm_device *dev)
2557 return to_i915(dev)->vgpu.active;
2561 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2565 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2568 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2569 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2571 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2573 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2574 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2575 uint32_t interrupt_mask,
2576 uint32_t enabled_irq_mask);
2577 #define ibx_enable_display_interrupt(dev_priv, bits) \
2578 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2579 #define ibx_disable_display_interrupt(dev_priv, bits) \
2580 ibx_display_interrupt_update((dev_priv), (bits), 0)
2583 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2584 struct drm_file *file_priv);
2585 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2586 struct drm_file *file_priv);
2587 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2588 struct drm_file *file_priv);
2589 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2590 struct drm_file *file_priv);
2591 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2592 struct drm_file *file_priv);
2593 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2594 struct drm_file *file_priv);
2595 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2596 struct drm_file *file_priv);
2597 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2598 struct intel_engine_cs *ring);
2599 void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2600 struct drm_file *file,
2601 struct intel_engine_cs *ring,
2602 struct drm_i915_gem_object *obj);
2603 int i915_gem_ringbuffer_submission(struct drm_device *dev,
2604 struct drm_file *file,
2605 struct intel_engine_cs *ring,
2606 struct intel_context *ctx,
2607 struct drm_i915_gem_execbuffer2 *args,
2608 struct list_head *vmas,
2609 struct drm_i915_gem_object *batch_obj,
2610 u64 exec_start, u32 flags);
2611 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2612 struct drm_file *file_priv);
2613 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2614 struct drm_file *file_priv);
2615 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2616 struct drm_file *file_priv);
2617 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2618 struct drm_file *file);
2619 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2620 struct drm_file *file);
2621 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2622 struct drm_file *file_priv);
2623 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2624 struct drm_file *file_priv);
2625 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2626 struct drm_file *file_priv);
2627 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2628 struct drm_file *file_priv);
2629 int i915_gem_init_userptr(struct drm_device *dev);
2630 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2631 struct drm_file *file);
2632 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2633 struct drm_file *file_priv);
2634 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2635 struct drm_file *file_priv);
2636 void i915_gem_load(struct drm_device *dev);
2637 void *i915_gem_object_alloc(struct drm_device *dev);
2638 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2639 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2640 const struct drm_i915_gem_object_ops *ops);
2641 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2643 void i915_init_vm(struct drm_i915_private *dev_priv,
2644 struct i915_address_space *vm);
2645 void i915_gem_free_object(struct drm_gem_object *obj);
2646 void i915_gem_vma_destroy(struct i915_vma *vma);
2648 #define PIN_MAPPABLE 0x1
2649 #define PIN_NONBLOCK 0x2
2650 #define PIN_GLOBAL 0x4
2651 #define PIN_OFFSET_BIAS 0x8
2652 #define PIN_OFFSET_MASK (~4095)
2654 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2655 struct i915_address_space *vm,
2659 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2660 const struct i915_ggtt_view *view,
2664 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2666 int __must_check i915_vma_unbind(struct i915_vma *vma);
2667 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2668 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2669 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2671 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2672 int *needs_clflush);
2674 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2676 static inline int __sg_page_count(struct scatterlist *sg)
2678 return sg->length >> PAGE_SHIFT;
2681 static inline struct page *
2682 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2684 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2687 if (n < obj->get_page.last) {
2688 obj->get_page.sg = obj->pages->sgl;
2689 obj->get_page.last = 0;
2692 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2693 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2694 if (unlikely(sg_is_chain(obj->get_page.sg)))
2695 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2698 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2701 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2703 BUG_ON(obj->pages == NULL);
2704 obj->pages_pin_count++;
2706 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2708 BUG_ON(obj->pages_pin_count == 0);
2709 obj->pages_pin_count--;
2712 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2713 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2714 struct intel_engine_cs *to);
2715 void i915_vma_move_to_active(struct i915_vma *vma,
2716 struct intel_engine_cs *ring);
2717 int i915_gem_dumb_create(struct drm_file *file_priv,
2718 struct drm_device *dev,
2719 struct drm_mode_create_dumb *args);
2720 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2721 uint32_t handle, uint64_t *offset);
2723 * Returns true if seq1 is later than seq2.
2726 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2728 return (int32_t)(seq1 - seq2) >= 0;
2731 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2732 bool lazy_coherency)
2736 BUG_ON(req == NULL);
2738 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2740 return i915_seqno_passed(seqno, req->seqno);
2743 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2744 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2745 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2746 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2748 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2749 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2751 struct drm_i915_gem_request *
2752 i915_gem_find_active_request(struct intel_engine_cs *ring);
2754 bool i915_gem_retire_requests(struct drm_device *dev);
2755 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2756 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2757 bool interruptible);
2758 int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req);
2760 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2762 return unlikely(atomic_read(&error->reset_counter)
2763 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2766 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2768 return atomic_read(&error->reset_counter) & I915_WEDGED;
2771 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2773 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2776 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2778 return dev_priv->gpu_error.stop_rings == 0 ||
2779 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2782 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2784 return dev_priv->gpu_error.stop_rings == 0 ||
2785 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2788 void i915_gem_reset(struct drm_device *dev);
2789 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2790 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2791 int __must_check i915_gem_init(struct drm_device *dev);
2792 int i915_gem_init_rings(struct drm_device *dev);
2793 int __must_check i915_gem_init_hw(struct drm_device *dev);
2794 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2795 void i915_gem_init_swizzling(struct drm_device *dev);
2796 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2797 int __must_check i915_gpu_idle(struct drm_device *dev);
2798 int __must_check i915_gem_suspend(struct drm_device *dev);
2799 int __i915_add_request(struct intel_engine_cs *ring,
2800 struct drm_file *file,
2801 struct drm_i915_gem_object *batch_obj);
2802 #define i915_add_request(ring) \
2803 __i915_add_request(ring, NULL, NULL)
2804 int __i915_wait_request(struct drm_i915_gem_request *req,
2805 unsigned reset_counter,
2808 struct drm_i915_file_private *file_priv);
2809 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2810 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2812 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2815 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2817 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2819 struct intel_engine_cs *pipelined,
2820 const struct i915_ggtt_view *view);
2821 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
2822 const struct i915_ggtt_view *view);
2823 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2825 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2826 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2829 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2831 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2832 int tiling_mode, bool fenced);
2834 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2835 enum i915_cache_level cache_level);
2837 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2838 struct dma_buf *dma_buf);
2840 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2841 struct drm_gem_object *gem_obj, int flags);
2843 void i915_gem_restore_fences(struct drm_device *dev);
2846 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
2847 const struct i915_ggtt_view *view);
2849 i915_gem_obj_offset(struct drm_i915_gem_object *o,
2850 struct i915_address_space *vm);
2851 static inline unsigned long
2852 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
2854 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
2857 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2858 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
2859 const struct i915_ggtt_view *view);
2860 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2861 struct i915_address_space *vm);
2863 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2864 struct i915_address_space *vm);
2866 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2867 struct i915_address_space *vm);
2869 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
2870 const struct i915_ggtt_view *view);
2873 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2874 struct i915_address_space *vm);
2876 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2877 const struct i915_ggtt_view *view);
2879 static inline struct i915_vma *
2880 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
2882 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
2884 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
2886 /* Some GGTT VM helpers */
2887 #define i915_obj_to_ggtt(obj) \
2888 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2889 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2891 struct i915_address_space *ggtt =
2892 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2896 static inline struct i915_hw_ppgtt *
2897 i915_vm_to_ppgtt(struct i915_address_space *vm)
2899 WARN_ON(i915_is_ggtt(vm));
2901 return container_of(vm, struct i915_hw_ppgtt, base);
2905 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2907 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
2910 static inline unsigned long
2911 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2913 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2916 static inline int __must_check
2917 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2921 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2922 alignment, flags | PIN_GLOBAL);
2926 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2928 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2931 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
2932 const struct i915_ggtt_view *view);
2934 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
2936 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
2939 /* i915_gem_context.c */
2940 int __must_check i915_gem_context_init(struct drm_device *dev);
2941 void i915_gem_context_fini(struct drm_device *dev);
2942 void i915_gem_context_reset(struct drm_device *dev);
2943 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2944 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2945 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2946 int i915_switch_context(struct intel_engine_cs *ring,
2947 struct intel_context *to);
2948 struct intel_context *
2949 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2950 void i915_gem_context_free(struct kref *ctx_ref);
2951 struct drm_i915_gem_object *
2952 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
2953 static inline void i915_gem_context_reference(struct intel_context *ctx)
2955 kref_get(&ctx->ref);
2958 static inline void i915_gem_context_unreference(struct intel_context *ctx)
2960 kref_put(&ctx->ref, i915_gem_context_free);
2963 static inline bool i915_gem_context_is_default(const struct intel_context *c)
2965 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
2968 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2969 struct drm_file *file);
2970 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2971 struct drm_file *file);
2972 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
2973 struct drm_file *file_priv);
2974 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
2975 struct drm_file *file_priv);
2977 /* i915_gem_evict.c */
2978 int __must_check i915_gem_evict_something(struct drm_device *dev,
2979 struct i915_address_space *vm,
2982 unsigned cache_level,
2983 unsigned long start,
2986 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2987 int i915_gem_evict_everything(struct drm_device *dev);
2989 /* belongs in i915_gem_gtt.h */
2990 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2992 if (INTEL_INFO(dev)->gen < 6)
2993 intel_gtt_chipset_flush();
2996 /* i915_gem_stolen.c */
2997 int i915_gem_init_stolen(struct drm_device *dev);
2998 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
2999 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
3000 void i915_gem_cleanup_stolen(struct drm_device *dev);
3001 struct drm_i915_gem_object *
3002 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3003 struct drm_i915_gem_object *
3004 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3009 /* i915_gem_shrinker.c */
3010 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3013 #define I915_SHRINK_PURGEABLE 0x1
3014 #define I915_SHRINK_UNBOUND 0x2
3015 #define I915_SHRINK_BOUND 0x4
3016 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3017 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3020 /* i915_gem_tiling.c */
3021 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3023 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3025 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3026 obj->tiling_mode != I915_TILING_NONE;
3029 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3030 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3031 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3033 /* i915_gem_debug.c */
3035 int i915_verify_lists(struct drm_device *dev);
3037 #define i915_verify_lists(dev) 0
3040 /* i915_debugfs.c */
3041 int i915_debugfs_init(struct drm_minor *minor);
3042 void i915_debugfs_cleanup(struct drm_minor *minor);
3043 #ifdef CONFIG_DEBUG_FS
3044 int i915_debugfs_connector_add(struct drm_connector *connector);
3045 void intel_display_crc_init(struct drm_device *dev);
3047 static inline int i915_debugfs_connector_add(struct drm_connector *connector) {}
3048 static inline void intel_display_crc_init(struct drm_device *dev) {}
3051 /* i915_gpu_error.c */
3053 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3054 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3055 const struct i915_error_state_file_priv *error);
3056 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3057 struct drm_i915_private *i915,
3058 size_t count, loff_t pos);
3059 static inline void i915_error_state_buf_release(
3060 struct drm_i915_error_state_buf *eb)
3064 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3065 const char *error_msg);
3066 void i915_error_state_get(struct drm_device *dev,
3067 struct i915_error_state_file_priv *error_priv);
3068 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3069 void i915_destroy_error_state(struct drm_device *dev);
3071 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3072 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3074 /* i915_cmd_parser.c */
3075 int i915_cmd_parser_get_version(void);
3076 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3077 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3078 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3079 int i915_parse_cmds(struct intel_engine_cs *ring,
3080 struct drm_i915_gem_object *batch_obj,
3081 struct drm_i915_gem_object *shadow_batch_obj,
3082 u32 batch_start_offset,
3086 /* i915_suspend.c */
3087 extern int i915_save_state(struct drm_device *dev);
3088 extern int i915_restore_state(struct drm_device *dev);
3091 void i915_setup_sysfs(struct drm_device *dev_priv);
3092 void i915_teardown_sysfs(struct drm_device *dev_priv);
3095 extern int intel_setup_gmbus(struct drm_device *dev);
3096 extern void intel_teardown_gmbus(struct drm_device *dev);
3097 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3100 extern struct i2c_adapter *
3101 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3102 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3103 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3104 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3106 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3108 extern void intel_i2c_reset(struct drm_device *dev);
3110 /* intel_opregion.c */
3112 extern int intel_opregion_setup(struct drm_device *dev);
3113 extern void intel_opregion_init(struct drm_device *dev);
3114 extern void intel_opregion_fini(struct drm_device *dev);
3115 extern void intel_opregion_asle_intr(struct drm_device *dev);
3116 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3118 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3121 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3122 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3123 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3124 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3126 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3131 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3139 extern void intel_register_dsm_handler(void);
3140 extern void intel_unregister_dsm_handler(void);
3142 static inline void intel_register_dsm_handler(void) { return; }
3143 static inline void intel_unregister_dsm_handler(void) { return; }
3144 #endif /* CONFIG_ACPI */
3147 extern void intel_modeset_init_hw(struct drm_device *dev);
3148 extern void intel_modeset_init(struct drm_device *dev);
3149 extern void intel_modeset_gem_init(struct drm_device *dev);
3150 extern void intel_modeset_cleanup(struct drm_device *dev);
3151 extern void intel_connector_unregister(struct intel_connector *);
3152 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3153 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
3154 bool force_restore);
3155 extern void i915_redisable_vga(struct drm_device *dev);
3156 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3157 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3158 extern void intel_init_pch_refclk(struct drm_device *dev);
3159 extern void intel_set_rps(struct drm_device *dev, u8 val);
3160 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3162 extern void intel_detect_pch(struct drm_device *dev);
3163 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3164 extern int intel_enable_rc6(const struct drm_device *dev);
3166 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3167 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3168 struct drm_file *file);
3169 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3170 struct drm_file *file);
3173 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3174 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3175 struct intel_overlay_error_state *error);
3177 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3178 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3179 struct drm_device *dev,
3180 struct intel_display_error_state *error);
3182 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3183 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3185 /* intel_sideband.c */
3186 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3187 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3188 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3189 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3190 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3191 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3192 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3193 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3194 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3195 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3196 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3197 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3198 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3199 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3200 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3201 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3202 enum intel_sbi_destination destination);
3203 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3204 enum intel_sbi_destination destination);
3205 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3206 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3208 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3209 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3211 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3212 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3214 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3215 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3216 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3217 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3219 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3220 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3221 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3222 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3224 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3225 * will be implemented using 2 32-bit writes in an arbitrary order with
3226 * an arbitrary delay between them. This can cause the hardware to
3227 * act upon the intermediate value, possibly leading to corruption and
3228 * machine death. You have been warned.
3230 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3231 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3233 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3234 u32 upper = I915_READ(upper_reg); \
3235 u32 lower = I915_READ(lower_reg); \
3236 u32 tmp = I915_READ(upper_reg); \
3237 if (upper != tmp) { \
3239 lower = I915_READ(lower_reg); \
3240 WARN_ON(I915_READ(upper_reg) != upper); \
3242 (u64)upper << 32 | lower; })
3244 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3245 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3247 /* These are untraced mmio-accessors that are only valid to be used inside
3248 * criticial sections inside IRQ handlers where forcewake is explicitly
3250 * Think twice, and think again, before using these.
3251 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3252 * intel_uncore_forcewake_irqunlock().
3254 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3255 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3256 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3258 /* "Broadcast RGB" property */
3259 #define INTEL_BROADCAST_RGB_AUTO 0
3260 #define INTEL_BROADCAST_RGB_FULL 1
3261 #define INTEL_BROADCAST_RGB_LIMITED 2
3263 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3265 if (IS_VALLEYVIEW(dev))
3266 return VLV_VGACNTRL;
3267 else if (INTEL_INFO(dev)->gen >= 5)
3268 return CPU_VGACNTRL;
3273 static inline void __user *to_user_ptr(u64 address)
3275 return (void __user *)(uintptr_t)address;
3278 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3280 unsigned long j = msecs_to_jiffies(m);
3282 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3285 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3287 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3290 static inline unsigned long
3291 timespec_to_jiffies_timeout(const struct timespec *value)
3293 unsigned long j = timespec_to_jiffies(value);
3295 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3299 * If you need to wait X milliseconds between events A and B, but event B
3300 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3301 * when event A happened, then just before event B you call this function and
3302 * pass the timestamp as the first argument, and X as the second argument.
3305 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3307 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3310 * Don't re-read the value of "jiffies" every time since it may change
3311 * behind our back and break the math.
3313 tmp_jiffies = jiffies;
3314 target_jiffies = timestamp_jiffies +
3315 msecs_to_jiffies_timeout(to_wait_ms);
3317 if (time_after(target_jiffies, tmp_jiffies)) {
3318 remaining_jiffies = target_jiffies - tmp_jiffies;
3319 while (remaining_jiffies)
3321 schedule_timeout_uninterruptible(remaining_jiffies);
3325 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3326 struct drm_i915_gem_request *req)
3328 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3329 i915_gem_request_assign(&ring->trace_irq_req, req);