1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <drm/drm_auth.h>
52 #include "i915_params.h"
55 #include "intel_bios.h"
56 #include "intel_dpll_mgr.h"
57 #include "intel_guc.h"
58 #include "intel_lrc.h"
59 #include "intel_ringbuffer.h"
62 #include "i915_gem_gtt.h"
63 #include "i915_gem_render_state.h"
64 #include "i915_gem_request.h"
66 #include "intel_gvt.h"
68 /* General customization:
71 #define DRIVER_NAME "i915"
72 #define DRIVER_DESC "Intel Graphics"
73 #define DRIVER_DATE "20160902"
76 /* Many gcc seem to no see through this and fall over :( */
78 #define WARN_ON(x) ({ \
79 bool __i915_warn_cond = (x); \
80 if (__builtin_constant_p(__i915_warn_cond)) \
81 BUILD_BUG_ON(__i915_warn_cond); \
82 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
84 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
88 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
90 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
91 (long) (x), __func__);
93 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
94 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
95 * which may not necessarily be a user visible problem. This will either
96 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
97 * enable distros and users to tailor their preferred amount of i915 abrt
100 #define I915_STATE_WARN(condition, format...) ({ \
101 int __ret_warn_on = !!(condition); \
102 if (unlikely(__ret_warn_on)) \
103 if (!WARN(i915.verbose_state_checks, format)) \
105 unlikely(__ret_warn_on); \
108 #define I915_STATE_WARN_ON(x) \
109 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
111 bool __i915_inject_load_failure(const char *func, int line);
112 #define i915_inject_load_failure() \
113 __i915_inject_load_failure(__func__, __LINE__)
115 static inline const char *yesno(bool v)
117 return v ? "yes" : "no";
120 static inline const char *onoff(bool v)
122 return v ? "on" : "off";
131 I915_MAX_PIPES = _PIPE_EDP
133 #define pipe_name(p) ((p) + 'A')
145 static inline const char *transcoder_name(enum transcoder transcoder)
147 switch (transcoder) {
156 case TRANSCODER_DSI_A:
158 case TRANSCODER_DSI_C:
165 static inline bool transcoder_is_dsi(enum transcoder transcoder)
167 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
171 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
172 * number of planes per CRTC. Not all platforms really have this many planes,
173 * which means some arrays of size I915_MAX_PLANES may have unused entries
174 * between the topmost sprite plane and the cursor plane.
183 #define plane_name(p) ((p) + 'A')
185 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
195 #define port_name(p) ((p) + 'A')
197 #define I915_NUM_PHYS_VLV 2
209 enum intel_display_power_domain {
213 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
214 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
215 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
216 POWER_DOMAIN_TRANSCODER_A,
217 POWER_DOMAIN_TRANSCODER_B,
218 POWER_DOMAIN_TRANSCODER_C,
219 POWER_DOMAIN_TRANSCODER_EDP,
220 POWER_DOMAIN_TRANSCODER_DSI_A,
221 POWER_DOMAIN_TRANSCODER_DSI_C,
222 POWER_DOMAIN_PORT_DDI_A_LANES,
223 POWER_DOMAIN_PORT_DDI_B_LANES,
224 POWER_DOMAIN_PORT_DDI_C_LANES,
225 POWER_DOMAIN_PORT_DDI_D_LANES,
226 POWER_DOMAIN_PORT_DDI_E_LANES,
227 POWER_DOMAIN_PORT_DSI,
228 POWER_DOMAIN_PORT_CRT,
229 POWER_DOMAIN_PORT_OTHER,
238 POWER_DOMAIN_MODESET,
244 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
245 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
246 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
247 #define POWER_DOMAIN_TRANSCODER(tran) \
248 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
249 (tran) + POWER_DOMAIN_TRANSCODER_A)
253 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
265 #define for_each_hpd_pin(__pin) \
266 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
268 struct i915_hotplug {
269 struct work_struct hotplug_work;
272 unsigned long last_jiffies;
277 HPD_MARK_DISABLED = 2
279 } stats[HPD_NUM_PINS];
281 struct delayed_work reenable_work;
283 struct intel_digital_port *irq_port[I915_MAX_PORTS];
286 struct work_struct dig_port_work;
288 struct work_struct poll_init_work;
292 * if we get a HPD irq from DP and a HPD irq from non-DP
293 * the non-DP HPD could block the workqueue on a mode config
294 * mutex getting, that userspace may have taken. However
295 * userspace is waiting on the DP workqueue to run which is
296 * blocked behind the non-DP one.
298 struct workqueue_struct *dp_wq;
301 #define I915_GEM_GPU_DOMAINS \
302 (I915_GEM_DOMAIN_RENDER | \
303 I915_GEM_DOMAIN_SAMPLER | \
304 I915_GEM_DOMAIN_COMMAND | \
305 I915_GEM_DOMAIN_INSTRUCTION | \
306 I915_GEM_DOMAIN_VERTEX)
308 #define for_each_pipe(__dev_priv, __p) \
309 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
310 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
311 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
312 for_each_if ((__mask) & (1 << (__p)))
313 #define for_each_plane(__dev_priv, __pipe, __p) \
315 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
317 #define for_each_sprite(__dev_priv, __p, __s) \
319 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
322 #define for_each_port_masked(__port, __ports_mask) \
323 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
324 for_each_if ((__ports_mask) & (1 << (__port)))
326 #define for_each_crtc(dev, crtc) \
327 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
329 #define for_each_intel_plane(dev, intel_plane) \
330 list_for_each_entry(intel_plane, \
331 &(dev)->mode_config.plane_list, \
334 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
335 list_for_each_entry(intel_plane, \
336 &(dev)->mode_config.plane_list, \
338 for_each_if ((plane_mask) & \
339 (1 << drm_plane_index(&intel_plane->base)))
341 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
342 list_for_each_entry(intel_plane, \
343 &(dev)->mode_config.plane_list, \
345 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
347 #define for_each_intel_crtc(dev, intel_crtc) \
348 list_for_each_entry(intel_crtc, \
349 &(dev)->mode_config.crtc_list, \
352 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
353 list_for_each_entry(intel_crtc, \
354 &(dev)->mode_config.crtc_list, \
356 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
358 #define for_each_intel_encoder(dev, intel_encoder) \
359 list_for_each_entry(intel_encoder, \
360 &(dev)->mode_config.encoder_list, \
363 #define for_each_intel_connector(dev, intel_connector) \
364 list_for_each_entry(intel_connector, \
365 &(dev)->mode_config.connector_list, \
368 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
369 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
370 for_each_if ((intel_encoder)->base.crtc == (__crtc))
372 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
373 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
374 for_each_if ((intel_connector)->base.encoder == (__encoder))
376 #define for_each_power_domain(domain, mask) \
377 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
378 for_each_if ((1 << (domain)) & (mask))
380 struct drm_i915_private;
381 struct i915_mm_struct;
382 struct i915_mmu_object;
384 struct drm_i915_file_private {
385 struct drm_i915_private *dev_priv;
386 struct drm_file *file;
390 struct list_head request_list;
391 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
392 * chosen to prevent the CPU getting more than a frame ahead of the GPU
393 * (when using lax throttling for the frontbuffer). We also use it to
394 * offer free GPU waitboosts for severely congested workloads.
396 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
398 struct idr context_idr;
400 struct intel_rps_client {
401 struct list_head link;
405 unsigned int bsd_engine;
408 /* Used by dp and fdi links */
409 struct intel_link_m_n {
417 void intel_link_compute_m_n(int bpp, int nlanes,
418 int pixel_clock, int link_clock,
419 struct intel_link_m_n *m_n);
421 /* Interface history:
424 * 1.2: Add Power Management
425 * 1.3: Add vblank support
426 * 1.4: Fix cmdbuffer path, add heap destroy
427 * 1.5: Add vblank pipe configuration
428 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
429 * - Support vertical blank on secondary display pipe
431 #define DRIVER_MAJOR 1
432 #define DRIVER_MINOR 6
433 #define DRIVER_PATCHLEVEL 0
435 struct opregion_header;
436 struct opregion_acpi;
437 struct opregion_swsci;
438 struct opregion_asle;
440 struct intel_opregion {
441 struct opregion_header *header;
442 struct opregion_acpi *acpi;
443 struct opregion_swsci *swsci;
444 u32 swsci_gbda_sub_functions;
445 u32 swsci_sbcb_sub_functions;
446 struct opregion_asle *asle;
451 struct work_struct asle_work;
453 #define OPREGION_SIZE (8*1024)
455 struct intel_overlay;
456 struct intel_overlay_error_state;
458 struct drm_i915_fence_reg {
459 struct list_head link;
460 struct drm_i915_private *i915;
461 struct i915_vma *vma;
465 * Whether the tiling parameters for the currently
466 * associated fence register have changed. Note that
467 * for the purposes of tracking tiling changes we also
468 * treat the unfenced register, the register slot that
469 * the object occupies whilst it executes a fenced
470 * command (such as BLT on gen2/3), as a "fence".
475 struct sdvo_device_mapping {
484 struct intel_connector;
485 struct intel_encoder;
486 struct intel_crtc_state;
487 struct intel_initial_plane_config;
492 struct drm_i915_display_funcs {
493 int (*get_display_clock_speed)(struct drm_device *dev);
494 int (*get_fifo_size)(struct drm_device *dev, int plane);
495 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
496 int (*compute_intermediate_wm)(struct drm_device *dev,
497 struct intel_crtc *intel_crtc,
498 struct intel_crtc_state *newstate);
499 void (*initial_watermarks)(struct intel_crtc_state *cstate);
500 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
501 int (*compute_global_watermarks)(struct drm_atomic_state *state);
502 void (*update_wm)(struct drm_crtc *crtc);
503 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
504 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
505 /* Returns the active state of the crtc, and if the crtc is active,
506 * fills out the pipe-config with the hw state. */
507 bool (*get_pipe_config)(struct intel_crtc *,
508 struct intel_crtc_state *);
509 void (*get_initial_plane_config)(struct intel_crtc *,
510 struct intel_initial_plane_config *);
511 int (*crtc_compute_clock)(struct intel_crtc *crtc,
512 struct intel_crtc_state *crtc_state);
513 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
514 struct drm_atomic_state *old_state);
515 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
516 struct drm_atomic_state *old_state);
517 void (*update_crtcs)(struct drm_atomic_state *state,
518 unsigned int *crtc_vblank_mask);
519 void (*audio_codec_enable)(struct drm_connector *connector,
520 struct intel_encoder *encoder,
521 const struct drm_display_mode *adjusted_mode);
522 void (*audio_codec_disable)(struct intel_encoder *encoder);
523 void (*fdi_link_train)(struct drm_crtc *crtc);
524 void (*init_clock_gating)(struct drm_device *dev);
525 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
526 struct drm_framebuffer *fb,
527 struct drm_i915_gem_object *obj,
528 struct drm_i915_gem_request *req,
530 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
531 /* clock updates for mode set */
533 /* render clock increase/decrease */
534 /* display clock increase/decrease */
535 /* pll clock increase/decrease */
537 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
538 void (*load_luts)(struct drm_crtc_state *crtc_state);
541 enum forcewake_domain_id {
542 FW_DOMAIN_ID_RENDER = 0,
543 FW_DOMAIN_ID_BLITTER,
549 enum forcewake_domains {
550 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
551 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
552 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
553 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
558 #define FW_REG_READ (1)
559 #define FW_REG_WRITE (2)
561 enum forcewake_domains
562 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
563 i915_reg_t reg, unsigned int op);
565 struct intel_uncore_funcs {
566 void (*force_wake_get)(struct drm_i915_private *dev_priv,
567 enum forcewake_domains domains);
568 void (*force_wake_put)(struct drm_i915_private *dev_priv,
569 enum forcewake_domains domains);
571 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
572 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
573 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
574 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
576 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
577 uint8_t val, bool trace);
578 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
579 uint16_t val, bool trace);
580 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
581 uint32_t val, bool trace);
582 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
583 uint64_t val, bool trace);
586 struct intel_uncore {
587 spinlock_t lock; /** lock is also taken in irq contexts. */
589 struct intel_uncore_funcs funcs;
592 enum forcewake_domains fw_domains;
594 struct intel_uncore_forcewake_domain {
595 struct drm_i915_private *i915;
596 enum forcewake_domain_id id;
597 enum forcewake_domains mask;
599 struct hrtimer timer;
606 } fw_domain[FW_DOMAIN_ID_COUNT];
608 int unclaimed_mmio_check;
611 /* Iterate over initialised fw domains */
612 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
613 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
614 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
616 for_each_if ((mask__) & (domain__)->mask)
618 #define for_each_fw_domain(domain__, dev_priv__) \
619 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
621 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
622 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
623 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
626 struct work_struct work;
628 uint32_t *dmc_payload;
629 uint32_t dmc_fw_size;
632 i915_reg_t mmioaddr[8];
633 uint32_t mmiodata[8];
635 uint32_t allowed_dc_mask;
638 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
639 func(is_mobile) sep \
642 func(is_i945gm) sep \
644 func(need_gfx_hws) sep \
646 func(is_pineview) sep \
647 func(is_broadwater) sep \
648 func(is_crestline) sep \
649 func(is_ivybridge) sep \
650 func(is_valleyview) sep \
651 func(is_cherryview) sep \
652 func(is_haswell) sep \
653 func(is_broadwell) sep \
654 func(is_skylake) sep \
655 func(is_broxton) sep \
656 func(is_kabylake) sep \
657 func(is_preliminary) sep \
659 func(has_pipe_cxsr) sep \
660 func(has_hotplug) sep \
661 func(cursor_needs_physical) sep \
662 func(has_overlay) sep \
663 func(overlay_needs_physical) sep \
664 func(supports_tv) sep \
666 func(has_snoop) sep \
668 func(has_fpga_dbg) sep \
671 #define DEFINE_FLAG(name) u8 name:1
672 #define SEP_SEMICOLON ;
674 struct sseu_dev_info {
677 u8 subslice_per_slice;
681 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
684 u8 has_subslice_pg:1;
688 struct intel_device_info {
689 u32 display_mmio_offset;
692 u8 num_sprites[I915_MAX_PIPES];
695 u8 ring_mask; /* Rings supported by the HW */
697 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
698 /* Register offsets for the various display pipes and transcoders */
699 int pipe_offsets[I915_MAX_TRANSCODERS];
700 int trans_offsets[I915_MAX_TRANSCODERS];
701 int palette_offsets[I915_MAX_PIPES];
702 int cursor_offsets[I915_MAX_PIPES];
704 /* Slice/subslice/EU info */
705 struct sseu_dev_info sseu;
708 u16 degamma_lut_size;
716 struct intel_display_error_state;
718 struct drm_i915_error_state {
727 struct intel_device_info device_info;
729 /* Generic register state */
737 u32 error; /* gen6+ */
738 u32 err_int; /* gen7 */
739 u32 fault_data0; /* gen8, gen9 */
740 u32 fault_data1; /* gen8, gen9 */
746 u32 extra_instdone[I915_NUM_INSTDONE_REG];
747 u64 fence[I915_MAX_NUM_FENCES];
748 struct intel_overlay_error_state *overlay;
749 struct intel_display_error_state *display;
750 struct drm_i915_error_object *semaphore;
752 struct drm_i915_error_engine {
754 /* Software tracked state */
758 enum intel_engine_hangcheck_action hangcheck_action;
759 struct i915_address_space *vm;
762 /* our own tracking of ring head and tail */
767 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
787 u32 rc_psmi; /* sleep state */
788 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
790 struct drm_i915_error_object {
795 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
797 struct drm_i915_error_object *wa_ctx;
799 struct drm_i915_error_request {
807 struct drm_i915_error_waiter {
808 char comm[TASK_COMM_LEN];
822 char comm[TASK_COMM_LEN];
823 } engine[I915_NUM_ENGINES];
825 struct drm_i915_error_buffer {
828 u32 rseqno[I915_NUM_ENGINES], wseqno;
832 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
839 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
840 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
841 struct i915_address_space *active_vm[I915_NUM_ENGINES];
844 enum i915_cache_level {
846 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
847 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
848 caches, eg sampler/render caches, and the
849 large Last-Level-Cache. LLC is coherent with
850 the CPU, but L3 is only visible to the GPU. */
851 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
854 struct i915_ctx_hang_stats {
855 /* This context had batch pending when hang was declared */
856 unsigned batch_pending;
858 /* This context had batch active when hang was declared */
859 unsigned batch_active;
861 /* Time when this context was last blamed for a GPU reset */
862 unsigned long guilty_ts;
864 /* If the contexts causes a second GPU hang within this time,
865 * it is permanently banned from submitting any more work.
867 unsigned long ban_period_seconds;
869 /* This context is banned to submit more work */
873 /* This must match up with the value previously used for execbuf2.rsvd1. */
874 #define DEFAULT_CONTEXT_HANDLE 0
877 * struct i915_gem_context - as the name implies, represents a context.
878 * @ref: reference count.
879 * @user_handle: userspace tracking identity for this context.
880 * @remap_slice: l3 row remapping information.
881 * @flags: context specific flags:
882 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
883 * @file_priv: filp associated with this context (NULL for global default
885 * @hang_stats: information about the role of this context in possible GPU
887 * @ppgtt: virtual memory space used by this context.
888 * @legacy_hw_ctx: render context backing object and whether it is correctly
889 * initialized (legacy ring submission mechanism only).
890 * @link: link in the global list of contexts.
892 * Contexts are memory images used by the hardware to store copies of their
895 struct i915_gem_context {
897 struct drm_i915_private *i915;
898 struct drm_i915_file_private *file_priv;
899 struct i915_hw_ppgtt *ppgtt;
902 struct i915_ctx_hang_stats hang_stats;
905 #define CONTEXT_NO_ZEROMAP BIT(0)
906 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
908 /* Unique identifier for this context, used by the hw for tracking */
914 struct intel_context {
915 struct i915_vma *state;
916 struct intel_ring *ring;
917 uint32_t *lrc_reg_state;
921 } engine[I915_NUM_ENGINES];
924 struct atomic_notifier_head status_notifier;
925 bool execlists_force_single_submission;
927 struct list_head link;
942 /* This is always the inner lock when overlapping with struct_mutex and
943 * it's the outer lock when overlapping with stolen_lock. */
946 unsigned int possible_framebuffer_bits;
947 unsigned int busy_bits;
948 unsigned int visible_pipes_mask;
949 struct intel_crtc *crtc;
951 struct drm_mm_node compressed_fb;
952 struct drm_mm_node *compressed_llb;
959 struct intel_fbc_state_cache {
961 unsigned int mode_flags;
962 uint32_t hsw_bdw_pixel_rate;
966 unsigned int rotation;
974 uint32_t pixel_format;
977 unsigned int tiling_mode;
981 struct intel_fbc_reg_params {
985 unsigned int fence_y_offset;
990 uint32_t pixel_format;
998 struct intel_fbc_work {
1000 u32 scheduled_vblank;
1001 struct work_struct work;
1004 const char *no_fbc_reason;
1008 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1009 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1010 * parsing for same resolution.
1012 enum drrs_refresh_rate_type {
1015 DRRS_MAX_RR, /* RR count */
1018 enum drrs_support_type {
1019 DRRS_NOT_SUPPORTED = 0,
1020 STATIC_DRRS_SUPPORT = 1,
1021 SEAMLESS_DRRS_SUPPORT = 2
1027 struct delayed_work work;
1028 struct intel_dp *dp;
1029 unsigned busy_frontbuffer_bits;
1030 enum drrs_refresh_rate_type refresh_rate_type;
1031 enum drrs_support_type type;
1038 struct intel_dp *enabled;
1040 struct delayed_work work;
1041 unsigned busy_frontbuffer_bits;
1043 bool aux_frame_sync;
1048 PCH_NONE = 0, /* No PCH present */
1049 PCH_IBX, /* Ibexpeak PCH */
1050 PCH_CPT, /* Cougarpoint PCH */
1051 PCH_LPT, /* Lynxpoint PCH */
1052 PCH_SPT, /* Sunrisepoint PCH */
1053 PCH_KBP, /* Kabypoint PCH */
1057 enum intel_sbi_destination {
1062 #define QUIRK_PIPEA_FORCE (1<<0)
1063 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1064 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1065 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1066 #define QUIRK_PIPEB_FORCE (1<<4)
1067 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1070 struct intel_fbc_work;
1072 struct intel_gmbus {
1073 struct i2c_adapter adapter;
1074 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1077 i915_reg_t gpio_reg;
1078 struct i2c_algo_bit_data bit_algo;
1079 struct drm_i915_private *dev_priv;
1082 struct i915_suspend_saved_registers {
1084 u32 saveFBC_CONTROL;
1085 u32 saveCACHE_MODE_0;
1086 u32 saveMI_ARB_STATE;
1090 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1091 u32 savePCH_PORT_HOTPLUG;
1095 struct vlv_s0ix_state {
1102 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1103 u32 media_max_req_count;
1104 u32 gfx_max_req_count;
1130 u32 rp_down_timeout;
1136 /* Display 1 CZ domain */
1141 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1143 /* GT SA CZ domain */
1150 /* Display 2 CZ domain */
1154 u32 clock_gate_dis2;
1157 struct intel_rps_ei {
1163 struct intel_gen6_power_mgmt {
1165 * work, interrupts_enabled and pm_iir are protected by
1166 * dev_priv->irq_lock
1168 struct work_struct work;
1169 bool interrupts_enabled;
1174 /* Frequencies are stored in potentially platform dependent multiples.
1175 * In other words, *_freq needs to be multiplied by X to be interesting.
1176 * Soft limits are those which are used for the dynamic reclocking done
1177 * by the driver (raise frequencies under heavy loads, and lower for
1178 * lighter loads). Hard limits are those imposed by the hardware.
1180 * A distinction is made for overclocking, which is never enabled by
1181 * default, and is considered to be above the hard limit if it's
1184 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1185 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1186 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1187 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1188 u8 min_freq; /* AKA RPn. Minimum frequency */
1189 u8 boost_freq; /* Frequency to request when wait boosting */
1190 u8 idle_freq; /* Frequency to request when we are idle */
1191 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1192 u8 rp1_freq; /* "less than" RP0 power/freqency */
1193 u8 rp0_freq; /* Non-overclocked max frequency. */
1194 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1196 u8 up_threshold; /* Current %busy required to uplock */
1197 u8 down_threshold; /* Current %busy required to downclock */
1200 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1202 spinlock_t client_lock;
1203 struct list_head clients;
1207 struct delayed_work autoenable_work;
1210 /* manual wa residency calculations */
1211 struct intel_rps_ei up_ei, down_ei;
1214 * Protects RPS/RC6 register access and PCU communication.
1215 * Must be taken after struct_mutex if nested. Note that
1216 * this lock may be held for long periods of time when
1217 * talking to hw - so only take it when talking to hw!
1219 struct mutex hw_lock;
1222 /* defined intel_pm.c */
1223 extern spinlock_t mchdev_lock;
1225 struct intel_ilk_power_mgmt {
1233 unsigned long last_time1;
1234 unsigned long chipset_power;
1237 unsigned long gfx_power;
1244 struct drm_i915_private;
1245 struct i915_power_well;
1247 struct i915_power_well_ops {
1249 * Synchronize the well's hw state to match the current sw state, for
1250 * example enable/disable it based on the current refcount. Called
1251 * during driver init and resume time, possibly after first calling
1252 * the enable/disable handlers.
1254 void (*sync_hw)(struct drm_i915_private *dev_priv,
1255 struct i915_power_well *power_well);
1257 * Enable the well and resources that depend on it (for example
1258 * interrupts located on the well). Called after the 0->1 refcount
1261 void (*enable)(struct drm_i915_private *dev_priv,
1262 struct i915_power_well *power_well);
1264 * Disable the well and resources that depend on it. Called after
1265 * the 1->0 refcount transition.
1267 void (*disable)(struct drm_i915_private *dev_priv,
1268 struct i915_power_well *power_well);
1269 /* Returns the hw enabled state. */
1270 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1271 struct i915_power_well *power_well);
1274 /* Power well structure for haswell */
1275 struct i915_power_well {
1278 /* power well enable/disable usage count */
1280 /* cached hw enabled state */
1282 unsigned long domains;
1284 const struct i915_power_well_ops *ops;
1287 struct i915_power_domains {
1289 * Power wells needed for initialization at driver init and suspend
1290 * time are on. They are kept on until after the first modeset.
1294 int power_well_count;
1297 int domain_use_count[POWER_DOMAIN_NUM];
1298 struct i915_power_well *power_wells;
1301 #define MAX_L3_SLICES 2
1302 struct intel_l3_parity {
1303 u32 *remap_info[MAX_L3_SLICES];
1304 struct work_struct error_work;
1308 struct i915_gem_mm {
1309 /** Memory allocator for GTT stolen memory */
1310 struct drm_mm stolen;
1311 /** Protects the usage of the GTT stolen memory allocator. This is
1312 * always the inner lock when overlapping with struct_mutex. */
1313 struct mutex stolen_lock;
1315 /** List of all objects in gtt_space. Used to restore gtt
1316 * mappings on resume */
1317 struct list_head bound_list;
1319 * List of objects which are not bound to the GTT (thus
1320 * are idle and not used by the GPU) but still have
1321 * (presumably uncached) pages still attached.
1323 struct list_head unbound_list;
1325 /** Usable portion of the GTT for GEM */
1326 unsigned long stolen_base; /* limited to low memory (32-bit) */
1328 /** PPGTT used for aliasing the PPGTT with the GTT */
1329 struct i915_hw_ppgtt *aliasing_ppgtt;
1331 struct notifier_block oom_notifier;
1332 struct notifier_block vmap_notifier;
1333 struct shrinker shrinker;
1335 /** LRU list of objects with fence regs on them. */
1336 struct list_head fence_list;
1339 * Are we in a non-interruptible section of code like
1344 /* the indicator for dispatch video commands on two BSD rings */
1345 atomic_t bsd_engine_dispatch_index;
1347 /** Bit 6 swizzling required for X tiling */
1348 uint32_t bit_6_swizzle_x;
1349 /** Bit 6 swizzling required for Y tiling */
1350 uint32_t bit_6_swizzle_y;
1352 /* accounting, useful for userland debugging */
1353 spinlock_t object_stat_lock;
1354 size_t object_memory;
1358 struct drm_i915_error_state_buf {
1359 struct drm_i915_private *i915;
1368 struct i915_error_state_file_priv {
1369 struct drm_device *dev;
1370 struct drm_i915_error_state *error;
1373 struct i915_gpu_error {
1374 /* For hangcheck timer */
1375 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1376 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1377 /* Hang gpu twice in this window and your context gets banned */
1378 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1380 struct delayed_work hangcheck_work;
1382 /* For reset and error_state handling. */
1384 /* Protected by the above dev->gpu_error.lock. */
1385 struct drm_i915_error_state *first_error;
1387 unsigned long missed_irq_rings;
1390 * State variable controlling the reset flow and count
1392 * This is a counter which gets incremented when reset is triggered,
1393 * and again when reset has been handled. So odd values (lowest bit set)
1394 * means that reset is in progress and even values that
1395 * (reset_counter >> 1):th reset was successfully completed.
1397 * If reset is not completed succesfully, the I915_WEDGE bit is
1398 * set meaning that hardware is terminally sour and there is no
1399 * recovery. All waiters on the reset_queue will be woken when
1402 * This counter is used by the wait_seqno code to notice that reset
1403 * event happened and it needs to restart the entire ioctl (since most
1404 * likely the seqno it waited for won't ever signal anytime soon).
1406 * This is important for lock-free wait paths, where no contended lock
1407 * naturally enforces the correct ordering between the bail-out of the
1408 * waiter and the gpu reset work code.
1410 atomic_t reset_counter;
1412 #define I915_RESET_IN_PROGRESS_FLAG 1
1413 #define I915_WEDGED (1 << 31)
1416 * Waitqueue to signal when a hang is detected. Used to for waiters
1417 * to release the struct_mutex for the reset to procede.
1419 wait_queue_head_t wait_queue;
1422 * Waitqueue to signal when the reset has completed. Used by clients
1423 * that wait for dev_priv->mm.wedged to settle.
1425 wait_queue_head_t reset_queue;
1427 /* For missed irq/seqno simulation. */
1428 unsigned long test_irq_rings;
1431 enum modeset_restore {
1432 MODESET_ON_LID_OPEN,
1437 #define DP_AUX_A 0x40
1438 #define DP_AUX_B 0x10
1439 #define DP_AUX_C 0x20
1440 #define DP_AUX_D 0x30
1442 #define DDC_PIN_B 0x05
1443 #define DDC_PIN_C 0x04
1444 #define DDC_PIN_D 0x06
1446 struct ddi_vbt_port_info {
1448 * This is an index in the HDMI/DVI DDI buffer translation table.
1449 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1450 * populate this field.
1452 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1453 uint8_t hdmi_level_shift;
1455 uint8_t supports_dvi:1;
1456 uint8_t supports_hdmi:1;
1457 uint8_t supports_dp:1;
1459 uint8_t alternate_aux_channel;
1460 uint8_t alternate_ddc_pin;
1462 uint8_t dp_boost_level;
1463 uint8_t hdmi_boost_level;
1466 enum psr_lines_to_wait {
1467 PSR_0_LINES_TO_WAIT = 0,
1469 PSR_4_LINES_TO_WAIT,
1473 struct intel_vbt_data {
1474 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1475 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1478 unsigned int int_tv_support:1;
1479 unsigned int lvds_dither:1;
1480 unsigned int lvds_vbt:1;
1481 unsigned int int_crt_support:1;
1482 unsigned int lvds_use_ssc:1;
1483 unsigned int display_clock_mode:1;
1484 unsigned int fdi_rx_polarity_inverted:1;
1485 unsigned int panel_type:4;
1487 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1489 enum drrs_support_type drrs_type;
1500 struct edp_power_seq pps;
1505 bool require_aux_wakeup;
1507 enum psr_lines_to_wait lines_to_wait;
1508 int tp1_wakeup_time;
1509 int tp2_tp3_wakeup_time;
1515 bool active_low_pwm;
1516 u8 min_brightness; /* min_brightness/255 of max */
1517 enum intel_backlight_type type;
1523 struct mipi_config *config;
1524 struct mipi_pps_data *pps;
1528 const u8 *sequence[MIPI_SEQ_MAX];
1534 union child_device_config *child_dev;
1536 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1537 struct sdvo_device_mapping sdvo_mappings[2];
1540 enum intel_ddb_partitioning {
1542 INTEL_DDB_PART_5_6, /* IVB+ */
1545 struct intel_wm_level {
1553 struct ilk_wm_values {
1554 uint32_t wm_pipe[3];
1556 uint32_t wm_lp_spr[3];
1557 uint32_t wm_linetime[3];
1559 enum intel_ddb_partitioning partitioning;
1562 struct vlv_pipe_wm {
1573 struct vlv_wm_values {
1574 struct vlv_pipe_wm pipe[3];
1575 struct vlv_sr_wm sr;
1585 struct skl_ddb_entry {
1586 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1589 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1591 return entry->end - entry->start;
1594 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1595 const struct skl_ddb_entry *e2)
1597 if (e1->start == e2->start && e1->end == e2->end)
1603 struct skl_ddb_allocation {
1604 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1605 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1606 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1609 struct skl_wm_values {
1610 unsigned dirty_pipes;
1611 struct skl_ddb_allocation ddb;
1612 uint32_t wm_linetime[I915_MAX_PIPES];
1613 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1614 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1617 struct skl_wm_level {
1618 bool plane_en[I915_MAX_PLANES];
1619 uint16_t plane_res_b[I915_MAX_PLANES];
1620 uint8_t plane_res_l[I915_MAX_PLANES];
1624 * This struct helps tracking the state needed for runtime PM, which puts the
1625 * device in PCI D3 state. Notice that when this happens, nothing on the
1626 * graphics device works, even register access, so we don't get interrupts nor
1629 * Every piece of our code that needs to actually touch the hardware needs to
1630 * either call intel_runtime_pm_get or call intel_display_power_get with the
1631 * appropriate power domain.
1633 * Our driver uses the autosuspend delay feature, which means we'll only really
1634 * suspend if we stay with zero refcount for a certain amount of time. The
1635 * default value is currently very conservative (see intel_runtime_pm_enable), but
1636 * it can be changed with the standard runtime PM files from sysfs.
1638 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1639 * goes back to false exactly before we reenable the IRQs. We use this variable
1640 * to check if someone is trying to enable/disable IRQs while they're supposed
1641 * to be disabled. This shouldn't happen and we'll print some error messages in
1644 * For more, read the Documentation/power/runtime_pm.txt.
1646 struct i915_runtime_pm {
1647 atomic_t wakeref_count;
1648 atomic_t atomic_seq;
1653 enum intel_pipe_crc_source {
1654 INTEL_PIPE_CRC_SOURCE_NONE,
1655 INTEL_PIPE_CRC_SOURCE_PLANE1,
1656 INTEL_PIPE_CRC_SOURCE_PLANE2,
1657 INTEL_PIPE_CRC_SOURCE_PF,
1658 INTEL_PIPE_CRC_SOURCE_PIPE,
1659 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1660 INTEL_PIPE_CRC_SOURCE_TV,
1661 INTEL_PIPE_CRC_SOURCE_DP_B,
1662 INTEL_PIPE_CRC_SOURCE_DP_C,
1663 INTEL_PIPE_CRC_SOURCE_DP_D,
1664 INTEL_PIPE_CRC_SOURCE_AUTO,
1665 INTEL_PIPE_CRC_SOURCE_MAX,
1668 struct intel_pipe_crc_entry {
1673 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1674 struct intel_pipe_crc {
1676 bool opened; /* exclusive access to the result file */
1677 struct intel_pipe_crc_entry *entries;
1678 enum intel_pipe_crc_source source;
1680 wait_queue_head_t wq;
1683 struct i915_frontbuffer_tracking {
1687 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1694 struct i915_wa_reg {
1697 /* bitmask representing WA bits */
1702 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1703 * allowing it for RCS as we don't foresee any requirement of having
1704 * a whitelist for other engines. When it is really required for
1705 * other engines then the limit need to be increased.
1707 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1709 struct i915_workarounds {
1710 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1712 u32 hw_whitelist_count[I915_NUM_ENGINES];
1715 struct i915_virtual_gpu {
1719 /* used in computing the new watermarks state */
1720 struct intel_wm_config {
1721 unsigned int num_pipes_active;
1722 bool sprites_enabled;
1723 bool sprites_scaled;
1726 struct drm_i915_private {
1727 struct drm_device drm;
1729 struct kmem_cache *objects;
1730 struct kmem_cache *vmas;
1731 struct kmem_cache *requests;
1733 const struct intel_device_info info;
1735 int relative_constants_mode;
1739 struct intel_uncore uncore;
1741 struct i915_virtual_gpu vgpu;
1743 struct intel_gvt gvt;
1745 struct intel_guc guc;
1747 struct intel_csr csr;
1749 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1751 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1752 * controller on different i2c buses. */
1753 struct mutex gmbus_mutex;
1756 * Base address of the gmbus and gpio block.
1758 uint32_t gpio_mmio_base;
1760 /* MMIO base address for MIPI regs */
1761 uint32_t mipi_mmio_base;
1763 uint32_t psr_mmio_base;
1765 uint32_t pps_mmio_base;
1767 wait_queue_head_t gmbus_wait_queue;
1769 struct pci_dev *bridge_dev;
1770 struct i915_gem_context *kernel_context;
1771 struct intel_engine_cs engine[I915_NUM_ENGINES];
1772 struct i915_vma *semaphore;
1775 struct drm_dma_handle *status_page_dmah;
1776 struct resource mch_res;
1778 /* protects the irq masks */
1779 spinlock_t irq_lock;
1781 /* protects the mmio flip data */
1782 spinlock_t mmio_flip_lock;
1784 bool display_irqs_enabled;
1786 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1787 struct pm_qos_request pm_qos;
1789 /* Sideband mailbox protection */
1790 struct mutex sb_lock;
1792 /** Cached value of IMR to avoid reads in updating the bitfield */
1795 u32 de_irq_mask[I915_MAX_PIPES];
1800 u32 pipestat_irq_mask[I915_MAX_PIPES];
1802 struct i915_hotplug hotplug;
1803 struct intel_fbc fbc;
1804 struct i915_drrs drrs;
1805 struct intel_opregion opregion;
1806 struct intel_vbt_data vbt;
1808 bool preserve_bios_swizzle;
1811 struct intel_overlay *overlay;
1813 /* backlight registers and fields in struct intel_panel */
1814 struct mutex backlight_lock;
1817 bool no_aux_handshake;
1819 /* protects panel power sequencer state */
1820 struct mutex pps_mutex;
1822 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1823 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1825 unsigned int fsb_freq, mem_freq, is_ddr3;
1826 unsigned int skl_preferred_vco_freq;
1827 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1828 unsigned int max_dotclk_freq;
1829 unsigned int rawclk_freq;
1830 unsigned int hpll_freq;
1831 unsigned int czclk_freq;
1834 unsigned int vco, ref;
1838 * wq - Driver workqueue for GEM.
1840 * NOTE: Work items scheduled here are not allowed to grab any modeset
1841 * locks, for otherwise the flushing done in the pageflip code will
1842 * result in deadlocks.
1844 struct workqueue_struct *wq;
1846 /* Display functions */
1847 struct drm_i915_display_funcs display;
1849 /* PCH chipset type */
1850 enum intel_pch pch_type;
1851 unsigned short pch_id;
1853 unsigned long quirks;
1855 enum modeset_restore modeset_restore;
1856 struct mutex modeset_restore_lock;
1857 struct drm_atomic_state *modeset_restore_state;
1858 struct drm_modeset_acquire_ctx reset_ctx;
1860 struct list_head vm_list; /* Global list of all address spaces */
1861 struct i915_ggtt ggtt; /* VM representing the global address space */
1863 struct i915_gem_mm mm;
1864 DECLARE_HASHTABLE(mm_structs, 7);
1865 struct mutex mm_lock;
1867 /* The hw wants to have a stable context identifier for the lifetime
1868 * of the context (for OA, PASID, faults, etc). This is limited
1869 * in execlists to 21 bits.
1871 struct ida context_hw_ida;
1872 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1874 /* Kernel Modesetting */
1876 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1877 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1878 wait_queue_head_t pending_flip_queue;
1880 #ifdef CONFIG_DEBUG_FS
1881 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1884 /* dpll and cdclk state is protected by connection_mutex */
1885 int num_shared_dpll;
1886 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1887 const struct intel_dpll_mgr *dpll_mgr;
1890 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1891 * Must be global rather than per dpll, because on some platforms
1892 * plls share registers.
1894 struct mutex dpll_lock;
1896 unsigned int active_crtcs;
1897 unsigned int min_pixclk[I915_MAX_PIPES];
1899 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1901 struct i915_workarounds workarounds;
1903 struct i915_frontbuffer_tracking fb_tracking;
1907 bool mchbar_need_disable;
1909 struct intel_l3_parity l3_parity;
1911 /* Cannot be determined by PCIID. You must always read a register. */
1914 /* gen6+ rps state */
1915 struct intel_gen6_power_mgmt rps;
1917 /* ilk-only ips/rps state. Everything in here is protected by the global
1918 * mchdev_lock in intel_pm.c */
1919 struct intel_ilk_power_mgmt ips;
1921 struct i915_power_domains power_domains;
1923 struct i915_psr psr;
1925 struct i915_gpu_error gpu_error;
1927 struct drm_i915_gem_object *vlv_pctx;
1929 #ifdef CONFIG_DRM_FBDEV_EMULATION
1930 /* list of fbdev register on this device */
1931 struct intel_fbdev *fbdev;
1932 struct work_struct fbdev_suspend_work;
1935 struct drm_property *broadcast_rgb_property;
1936 struct drm_property *force_audio_property;
1938 /* hda/i915 audio component */
1939 struct i915_audio_component *audio_component;
1940 bool audio_component_registered;
1942 * av_mutex - mutex for audio/video sync
1945 struct mutex av_mutex;
1947 uint32_t hw_context_size;
1948 struct list_head context_list;
1952 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1953 u32 chv_phy_control;
1955 * Shadows for CHV DPLL_MD regs to keep the state
1956 * checker somewhat working in the presence hardware
1957 * crappiness (can't read out DPLL_MD for pipes B & C).
1959 u32 chv_dpll_md[I915_MAX_PIPES];
1963 bool suspended_to_idle;
1964 struct i915_suspend_saved_registers regfile;
1965 struct vlv_s0ix_state vlv_s0ix_state;
1968 I915_SKL_SAGV_UNKNOWN = 0,
1969 I915_SKL_SAGV_DISABLED,
1970 I915_SKL_SAGV_ENABLED,
1971 I915_SKL_SAGV_NOT_CONTROLLED
1976 * Raw watermark latency values:
1977 * in 0.1us units for WM0,
1978 * in 0.5us units for WM1+.
1981 uint16_t pri_latency[5];
1983 uint16_t spr_latency[5];
1985 uint16_t cur_latency[5];
1987 * Raw watermark memory latency values
1988 * for SKL for all 8 levels
1991 uint16_t skl_latency[8];
1994 * The skl_wm_values structure is a bit too big for stack
1995 * allocation, so we keep the staging struct where we store
1996 * intermediate results here instead.
1998 struct skl_wm_values skl_results;
2000 /* current hardware state */
2002 struct ilk_wm_values hw;
2003 struct skl_wm_values skl_hw;
2004 struct vlv_wm_values vlv;
2010 * Should be held around atomic WM register writing; also
2011 * protects * intel_crtc->wm.active and
2012 * cstate->wm.need_postvbl_update.
2014 struct mutex wm_mutex;
2017 * Set during HW readout of watermarks/DDB. Some platforms
2018 * need to know when we're still using BIOS-provided values
2019 * (which we don't fully trust).
2021 bool distrust_bios_wm;
2024 struct i915_runtime_pm pm;
2026 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2028 void (*cleanup_engine)(struct intel_engine_cs *engine);
2031 * Is the GPU currently considered idle, or busy executing
2032 * userspace requests? Whilst idle, we allow runtime power
2033 * management to power down the hardware and display clocks.
2034 * In order to reduce the effect on performance, there
2035 * is a slight delay before we do so.
2037 unsigned int active_engines;
2041 * We leave the user IRQ off as much as possible,
2042 * but this means that requests will finish and never
2043 * be retired once the system goes idle. Set a timer to
2044 * fire periodically while the ring is running. When it
2045 * fires, go retire requests.
2047 struct delayed_work retire_work;
2050 * When we detect an idle GPU, we want to turn on
2051 * powersaving features. So once we see that there
2052 * are no more requests outstanding and no more
2053 * arrive within a small period of time, we fire
2054 * off the idle_work.
2056 struct delayed_work idle_work;
2059 /* perform PHY state sanity checks? */
2060 bool chv_phy_assert[2];
2062 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
2065 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2066 * will be rejected. Instead look for a better place.
2070 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2072 return container_of(dev, struct drm_i915_private, drm);
2075 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2077 return to_i915(dev_get_drvdata(kdev));
2080 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2082 return container_of(guc, struct drm_i915_private, guc);
2085 /* Simple iterator over all initialised engines */
2086 #define for_each_engine(engine__, dev_priv__) \
2087 for ((engine__) = &(dev_priv__)->engine[0]; \
2088 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2090 for_each_if (intel_engine_initialized(engine__))
2092 /* Iterator with engine_id */
2093 #define for_each_engine_id(engine__, dev_priv__, id__) \
2094 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2095 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2097 for_each_if (((id__) = (engine__)->id, \
2098 intel_engine_initialized(engine__)))
2100 #define __mask_next_bit(mask) ({ \
2101 int __idx = ffs(mask) - 1; \
2102 mask &= ~BIT(__idx); \
2106 /* Iterator over subset of engines selected by mask */
2107 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2108 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2109 tmp__ ? (engine__ = &(dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2111 enum hdmi_force_audio {
2112 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2113 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2114 HDMI_AUDIO_AUTO, /* trust EDID */
2115 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2118 #define I915_GTT_OFFSET_NONE ((u32)-1)
2120 struct drm_i915_gem_object_ops {
2122 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2124 /* Interface between the GEM object and its backing storage.
2125 * get_pages() is called once prior to the use of the associated set
2126 * of pages before to binding them into the GTT, and put_pages() is
2127 * called after we no longer need them. As we expect there to be
2128 * associated cost with migrating pages between the backing storage
2129 * and making them available for the GPU (e.g. clflush), we may hold
2130 * onto the pages after they are no longer referenced by the GPU
2131 * in case they may be used again shortly (for example migrating the
2132 * pages to a different memory domain within the GTT). put_pages()
2133 * will therefore most likely be called when the object itself is
2134 * being released or under memory pressure (where we attempt to
2135 * reap pages for the shrinker).
2137 int (*get_pages)(struct drm_i915_gem_object *);
2138 void (*put_pages)(struct drm_i915_gem_object *);
2140 int (*dmabuf_export)(struct drm_i915_gem_object *);
2141 void (*release)(struct drm_i915_gem_object *);
2145 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2146 * considered to be the frontbuffer for the given plane interface-wise. This
2147 * doesn't mean that the hw necessarily already scans it out, but that any
2148 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2150 * We have one bit per pipe and per scanout plane type.
2152 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2153 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2154 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2155 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2156 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2157 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2158 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2159 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2160 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2161 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2162 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2163 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2165 struct drm_i915_gem_object {
2166 struct drm_gem_object base;
2168 const struct drm_i915_gem_object_ops *ops;
2170 /** List of VMAs backed by this object */
2171 struct list_head vma_list;
2173 /** Stolen memory for this object, instead of being backed by shmem. */
2174 struct drm_mm_node *stolen;
2175 struct list_head global_list;
2177 /** Used in execbuf to temporarily hold a ref */
2178 struct list_head obj_exec_link;
2180 struct list_head batch_pool_link;
2182 unsigned long flags;
2184 * This is set if the object is on the active lists (has pending
2185 * rendering and so a non-zero seqno), and is not set if it i s on
2186 * inactive (ready to be unbound) list.
2188 #define I915_BO_ACTIVE_SHIFT 0
2189 #define I915_BO_ACTIVE_MASK ((1 << I915_NUM_ENGINES) - 1)
2190 #define __I915_BO_ACTIVE(bo) \
2191 ((READ_ONCE((bo)->flags) >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK)
2194 * This is set if the object has been written to since last bound
2197 unsigned int dirty:1;
2200 * Advice: are the backing pages purgeable?
2202 unsigned int madv:2;
2205 * Whether the current gtt mapping needs to be mappable (and isn't just
2206 * mappable by accident). Track pin and fault separate for a more
2207 * accurate mappable working set.
2209 unsigned int fault_mappable:1;
2212 * Is the object to be mapped as read-only to the GPU
2213 * Only honoured if hardware has relevant pte bit
2215 unsigned long gt_ro:1;
2216 unsigned int cache_level:3;
2217 unsigned int cache_dirty:1;
2219 atomic_t frontbuffer_bits;
2220 unsigned int frontbuffer_ggtt_origin; /* write once */
2222 /** Current tiling stride for the object, if it's tiled. */
2223 unsigned int tiling_and_stride;
2224 #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
2225 #define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
2226 #define STRIDE_MASK (~TILING_MASK)
2228 /** Count of VMA actually bound by this object */
2229 unsigned int bind_count;
2230 unsigned int pin_display;
2232 struct sg_table *pages;
2233 int pages_pin_count;
2235 struct scatterlist *sg;
2240 /** Breadcrumb of last rendering to the buffer.
2241 * There can only be one writer, but we allow for multiple readers.
2242 * If there is a writer that necessarily implies that all other
2243 * read requests are complete - but we may only be lazily clearing
2244 * the read requests. A read request is naturally the most recent
2245 * request on a ring, so we may have two different write and read
2246 * requests on one ring where the write request is older than the
2247 * read request. This allows for the CPU to read from an active
2248 * buffer by only waiting for the write to complete.
2250 struct i915_gem_active last_read[I915_NUM_ENGINES];
2251 struct i915_gem_active last_write;
2253 /** References from framebuffers, locks out tiling changes. */
2254 unsigned long framebuffer_references;
2256 /** Record of address bit 17 of each page at last unbind. */
2257 unsigned long *bit_17;
2260 /** for phy allocated objects */
2261 struct drm_dma_handle *phys_handle;
2263 struct i915_gem_userptr {
2265 unsigned read_only :1;
2266 unsigned workers :4;
2267 #define I915_GEM_USERPTR_MAX_WORKERS 15
2269 struct i915_mm_struct *mm;
2270 struct i915_mmu_object *mmu_object;
2271 struct work_struct *work;
2276 static inline struct drm_i915_gem_object *
2277 to_intel_bo(struct drm_gem_object *gem)
2279 /* Assert that to_intel_bo(NULL) == NULL */
2280 BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));
2282 return container_of(gem, struct drm_i915_gem_object, base);
2285 static inline struct drm_i915_gem_object *
2286 i915_gem_object_lookup(struct drm_file *file, u32 handle)
2288 return to_intel_bo(drm_gem_object_lookup(file, handle));
2292 extern struct drm_gem_object *
2293 drm_gem_object_lookup(struct drm_file *file, u32 handle);
2295 __attribute__((nonnull))
2296 static inline struct drm_i915_gem_object *
2297 i915_gem_object_get(struct drm_i915_gem_object *obj)
2299 drm_gem_object_reference(&obj->base);
2304 extern void drm_gem_object_reference(struct drm_gem_object *);
2306 __attribute__((nonnull))
2308 i915_gem_object_put(struct drm_i915_gem_object *obj)
2310 drm_gem_object_unreference(&obj->base);
2314 extern void drm_gem_object_unreference(struct drm_gem_object *);
2316 __attribute__((nonnull))
2318 i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj)
2320 drm_gem_object_unreference_unlocked(&obj->base);
2324 extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *);
2327 i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
2329 return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
2332 static inline unsigned long
2333 i915_gem_object_get_active(const struct drm_i915_gem_object *obj)
2335 return (obj->flags >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK;
2339 i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
2341 return i915_gem_object_get_active(obj);
2345 i915_gem_object_set_active(struct drm_i915_gem_object *obj, int engine)
2347 obj->flags |= BIT(engine + I915_BO_ACTIVE_SHIFT);
2351 i915_gem_object_clear_active(struct drm_i915_gem_object *obj, int engine)
2353 obj->flags &= ~BIT(engine + I915_BO_ACTIVE_SHIFT);
2357 i915_gem_object_has_active_engine(const struct drm_i915_gem_object *obj,
2360 return obj->flags & BIT(engine + I915_BO_ACTIVE_SHIFT);
2363 static inline unsigned int
2364 i915_gem_object_get_tiling(struct drm_i915_gem_object *obj)
2366 return obj->tiling_and_stride & TILING_MASK;
2370 i915_gem_object_is_tiled(struct drm_i915_gem_object *obj)
2372 return i915_gem_object_get_tiling(obj) != I915_TILING_NONE;
2375 static inline unsigned int
2376 i915_gem_object_get_stride(struct drm_i915_gem_object *obj)
2378 return obj->tiling_and_stride & STRIDE_MASK;
2381 static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
2383 i915_gem_object_get(vma->obj);
2387 static inline void i915_vma_put(struct i915_vma *vma)
2389 lockdep_assert_held(&vma->vm->dev->struct_mutex);
2390 i915_gem_object_put(vma->obj);
2394 * Optimised SGL iterator for GEM objects
2396 static __always_inline struct sgt_iter {
2397 struct scatterlist *sgp;
2404 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2405 struct sgt_iter s = { .sgp = sgl };
2408 s.max = s.curr = s.sgp->offset;
2409 s.max += s.sgp->length;
2411 s.dma = sg_dma_address(s.sgp);
2413 s.pfn = page_to_pfn(sg_page(s.sgp));
2420 * __sg_next - return the next scatterlist entry in a list
2421 * @sg: The current sg entry
2424 * If the entry is the last, return NULL; otherwise, step to the next
2425 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2426 * otherwise just return the pointer to the current element.
2428 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2430 #ifdef CONFIG_DEBUG_SG
2431 BUG_ON(sg->sg_magic != SG_MAGIC);
2433 return sg_is_last(sg) ? NULL :
2434 likely(!sg_is_chain(++sg)) ? sg :
2439 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2440 * @__dmap: DMA address (output)
2441 * @__iter: 'struct sgt_iter' (iterator state, internal)
2442 * @__sgt: sg_table to iterate over (input)
2444 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2445 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2446 ((__dmap) = (__iter).dma + (__iter).curr); \
2447 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2448 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2451 * for_each_sgt_page - iterate over the pages of the given sg_table
2452 * @__pp: page pointer (output)
2453 * @__iter: 'struct sgt_iter' (iterator state, internal)
2454 * @__sgt: sg_table to iterate over (input)
2456 #define for_each_sgt_page(__pp, __iter, __sgt) \
2457 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2458 ((__pp) = (__iter).pfn == 0 ? NULL : \
2459 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2460 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2461 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2464 * A command that requires special handling by the command parser.
2466 struct drm_i915_cmd_descriptor {
2468 * Flags describing how the command parser processes the command.
2470 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2471 * a length mask if not set
2472 * CMD_DESC_SKIP: The command is allowed but does not follow the
2473 * standard length encoding for the opcode range in
2475 * CMD_DESC_REJECT: The command is never allowed
2476 * CMD_DESC_REGISTER: The command should be checked against the
2477 * register whitelist for the appropriate ring
2478 * CMD_DESC_MASTER: The command is allowed if the submitting process
2482 #define CMD_DESC_FIXED (1<<0)
2483 #define CMD_DESC_SKIP (1<<1)
2484 #define CMD_DESC_REJECT (1<<2)
2485 #define CMD_DESC_REGISTER (1<<3)
2486 #define CMD_DESC_BITMASK (1<<4)
2487 #define CMD_DESC_MASTER (1<<5)
2490 * The command's unique identification bits and the bitmask to get them.
2491 * This isn't strictly the opcode field as defined in the spec and may
2492 * also include type, subtype, and/or subop fields.
2500 * The command's length. The command is either fixed length (i.e. does
2501 * not include a length field) or has a length field mask. The flag
2502 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2503 * a length mask. All command entries in a command table must include
2504 * length information.
2512 * Describes where to find a register address in the command to check
2513 * against the ring's register whitelist. Only valid if flags has the
2514 * CMD_DESC_REGISTER bit set.
2516 * A non-zero step value implies that the command may access multiple
2517 * registers in sequence (e.g. LRI), in that case step gives the
2518 * distance in dwords between individual offset fields.
2526 #define MAX_CMD_DESC_BITMASKS 3
2528 * Describes command checks where a particular dword is masked and
2529 * compared against an expected value. If the command does not match
2530 * the expected value, the parser rejects it. Only valid if flags has
2531 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2534 * If the check specifies a non-zero condition_mask then the parser
2535 * only performs the check when the bits specified by condition_mask
2542 u32 condition_offset;
2544 } bits[MAX_CMD_DESC_BITMASKS];
2548 * A table of commands requiring special handling by the command parser.
2550 * Each engine has an array of tables. Each table consists of an array of
2551 * command descriptors, which must be sorted with command opcodes in
2554 struct drm_i915_cmd_table {
2555 const struct drm_i915_cmd_descriptor *table;
2559 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2560 #define __I915__(p) ({ \
2561 struct drm_i915_private *__p; \
2562 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2563 __p = (struct drm_i915_private *)p; \
2564 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2565 __p = to_i915((struct drm_device *)p); \
2570 #define INTEL_INFO(p) (&__I915__(p)->info)
2571 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2572 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2574 #define REVID_FOREVER 0xff
2575 #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
2577 #define GEN_FOREVER (0)
2579 * Returns true if Gen is in inclusive range [Start, End].
2581 * Use GEN_FOREVER for unbound start and or end.
2583 #define IS_GEN(p, s, e) ({ \
2584 unsigned int __s = (s), __e = (e); \
2585 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2586 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2587 if ((__s) != GEN_FOREVER) \
2589 if ((__e) == GEN_FOREVER) \
2590 __e = BITS_PER_LONG - 1; \
2593 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2597 * Return true if revision is in range [since,until] inclusive.
2599 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2601 #define IS_REVID(p, since, until) \
2602 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2604 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2605 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2606 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2607 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2608 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2609 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2610 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2611 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2612 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2613 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2614 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2615 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2616 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2617 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2618 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2619 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2620 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2621 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2622 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2623 INTEL_DEVID(dev) == 0x0152 || \
2624 INTEL_DEVID(dev) == 0x015a)
2625 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2626 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2627 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2628 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
2629 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2630 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2631 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2632 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2633 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2634 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2635 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2636 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2637 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2638 (INTEL_DEVID(dev) & 0xf) == 0xe))
2639 /* ULX machines are also considered ULT. */
2640 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2641 (INTEL_DEVID(dev) & 0xf) == 0xe)
2642 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2643 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2644 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2645 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2646 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2647 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2648 /* ULX machines are also considered ULT. */
2649 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2650 INTEL_DEVID(dev) == 0x0A1E)
2651 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2652 INTEL_DEVID(dev) == 0x1913 || \
2653 INTEL_DEVID(dev) == 0x1916 || \
2654 INTEL_DEVID(dev) == 0x1921 || \
2655 INTEL_DEVID(dev) == 0x1926)
2656 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2657 INTEL_DEVID(dev) == 0x1915 || \
2658 INTEL_DEVID(dev) == 0x191E)
2659 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2660 INTEL_DEVID(dev) == 0x5913 || \
2661 INTEL_DEVID(dev) == 0x5916 || \
2662 INTEL_DEVID(dev) == 0x5921 || \
2663 INTEL_DEVID(dev) == 0x5926)
2664 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2665 INTEL_DEVID(dev) == 0x5915 || \
2666 INTEL_DEVID(dev) == 0x591E)
2667 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2668 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2669 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2670 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2672 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2674 #define SKL_REVID_A0 0x0
2675 #define SKL_REVID_B0 0x1
2676 #define SKL_REVID_C0 0x2
2677 #define SKL_REVID_D0 0x3
2678 #define SKL_REVID_E0 0x4
2679 #define SKL_REVID_F0 0x5
2680 #define SKL_REVID_G0 0x6
2681 #define SKL_REVID_H0 0x7
2683 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2685 #define BXT_REVID_A0 0x0
2686 #define BXT_REVID_A1 0x1
2687 #define BXT_REVID_B0 0x3
2688 #define BXT_REVID_C0 0x9
2690 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2692 #define KBL_REVID_A0 0x0
2693 #define KBL_REVID_B0 0x1
2694 #define KBL_REVID_C0 0x2
2695 #define KBL_REVID_D0 0x3
2696 #define KBL_REVID_E0 0x4
2698 #define IS_KBL_REVID(p, since, until) \
2699 (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2702 * The genX designation typically refers to the render engine, so render
2703 * capability related checks should use IS_GEN, while display and other checks
2704 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2707 #define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
2708 #define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
2709 #define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
2710 #define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
2711 #define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
2712 #define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
2713 #define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
2714 #define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
2716 #define ENGINE_MASK(id) BIT(id)
2717 #define RENDER_RING ENGINE_MASK(RCS)
2718 #define BSD_RING ENGINE_MASK(VCS)
2719 #define BLT_RING ENGINE_MASK(BCS)
2720 #define VEBOX_RING ENGINE_MASK(VECS)
2721 #define BSD2_RING ENGINE_MASK(VCS2)
2722 #define ALL_ENGINES (~0)
2724 #define HAS_ENGINE(dev_priv, id) \
2725 (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2727 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2728 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2729 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2730 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2732 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2733 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2734 #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2735 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2737 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2739 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2740 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2741 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2742 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2743 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2745 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2746 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2748 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2749 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2751 /* WaRsDisableCoarsePowerGating:skl,bxt */
2752 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2753 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2754 IS_SKL_GT3(dev_priv) || \
2755 IS_SKL_GT4(dev_priv))
2758 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2759 * even when in MSI mode. This results in spurious interrupt warnings if the
2760 * legacy irq no. is shared with another device. The kernel then disables that
2761 * interrupt source and so prevents the other device from working properly.
2763 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2764 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2766 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2767 * rows, which changed the alignment requirements and fence programming.
2769 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2771 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2772 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2774 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2775 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2776 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2778 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2780 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2781 INTEL_INFO(dev)->gen >= 9)
2783 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2784 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2785 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2786 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2787 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2788 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2789 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2790 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2791 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2792 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2793 #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
2795 #define HAS_CSR(dev) (IS_GEN9(dev))
2798 * For now, anything with a GuC requires uCode loading, and then supports
2799 * command submission once loaded. But these are logically independent
2800 * properties, so we have separate macros to test them.
2802 #define HAS_GUC(dev) (IS_GEN9(dev))
2803 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2804 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2806 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2807 INTEL_INFO(dev)->gen >= 8)
2809 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2810 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2813 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2815 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2816 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2817 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2818 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2819 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2820 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2821 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2822 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2823 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2824 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2825 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2826 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2828 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2829 #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2830 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2831 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2832 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2833 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2834 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2835 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2836 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2837 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2839 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2840 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2842 /* DPF == dynamic parity feature */
2843 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2844 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2846 #define GT_FREQUENCY_MULTIPLIER 50
2847 #define GEN9_FREQ_SCALER 3
2849 #include "i915_trace.h"
2851 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2853 #ifdef CONFIG_INTEL_IOMMU
2854 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2860 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2861 extern int i915_resume_switcheroo(struct drm_device *dev);
2863 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2866 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2870 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2871 const char *fmt, ...);
2873 #define i915_report_error(dev_priv, fmt, ...) \
2874 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2876 #ifdef CONFIG_COMPAT
2877 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2880 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2881 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2882 extern int i915_reset(struct drm_i915_private *dev_priv);
2883 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2884 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2885 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2886 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2887 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2888 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2889 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2891 /* intel_hotplug.c */
2892 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2893 u32 pin_mask, u32 long_mask);
2894 void intel_hpd_init(struct drm_i915_private *dev_priv);
2895 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2896 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2897 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2898 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2899 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2902 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2904 unsigned long delay;
2906 if (unlikely(!i915.enable_hangcheck))
2909 /* Don't continually defer the hangcheck so that it is always run at
2910 * least once after work has been scheduled on any ring. Otherwise,
2911 * we will ignore a hung ring if a second ring is kept busy.
2914 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2915 queue_delayed_work(system_long_wq,
2916 &dev_priv->gpu_error.hangcheck_work, delay);
2920 void i915_handle_error(struct drm_i915_private *dev_priv,
2922 const char *fmt, ...);
2924 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2925 int intel_irq_install(struct drm_i915_private *dev_priv);
2926 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2928 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
2929 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2930 bool restore_forcewake);
2931 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2932 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2933 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2934 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
2935 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
2937 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2938 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2939 enum forcewake_domains domains);
2940 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2941 enum forcewake_domains domains);
2942 /* Like above but the caller must manage the uncore.lock itself.
2943 * Must be used with I915_READ_FW and friends.
2945 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2946 enum forcewake_domains domains);
2947 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2948 enum forcewake_domains domains);
2949 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
2951 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2953 int intel_wait_for_register(struct drm_i915_private *dev_priv,
2957 const unsigned long timeout_ms);
2958 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
2962 const unsigned long timeout_ms);
2964 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2966 return dev_priv->gvt.initialized;
2969 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2971 return dev_priv->vgpu.active;
2975 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2979 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2982 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2983 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2984 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2987 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2988 uint32_t interrupt_mask,
2989 uint32_t enabled_irq_mask);
2991 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2993 ilk_update_display_irq(dev_priv, bits, bits);
2996 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2998 ilk_update_display_irq(dev_priv, bits, 0);
3000 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3002 uint32_t interrupt_mask,
3003 uint32_t enabled_irq_mask);
3004 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3005 enum pipe pipe, uint32_t bits)
3007 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3009 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3010 enum pipe pipe, uint32_t bits)
3012 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3014 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3015 uint32_t interrupt_mask,
3016 uint32_t enabled_irq_mask);
3018 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3020 ibx_display_interrupt_update(dev_priv, bits, bits);
3023 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3025 ibx_display_interrupt_update(dev_priv, bits, 0);
3029 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3030 struct drm_file *file_priv);
3031 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3032 struct drm_file *file_priv);
3033 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3034 struct drm_file *file_priv);
3035 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3036 struct drm_file *file_priv);
3037 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3038 struct drm_file *file_priv);
3039 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3040 struct drm_file *file_priv);
3041 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3042 struct drm_file *file_priv);
3043 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3044 struct drm_file *file_priv);
3045 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3046 struct drm_file *file_priv);
3047 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3048 struct drm_file *file_priv);
3049 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3050 struct drm_file *file);
3051 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3052 struct drm_file *file);
3053 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3054 struct drm_file *file_priv);
3055 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3056 struct drm_file *file_priv);
3057 int i915_gem_set_tiling(struct drm_device *dev, void *data,
3058 struct drm_file *file_priv);
3059 int i915_gem_get_tiling(struct drm_device *dev, void *data,
3060 struct drm_file *file_priv);
3061 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3062 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3063 struct drm_file *file);
3064 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3065 struct drm_file *file_priv);
3066 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3067 struct drm_file *file_priv);
3068 void i915_gem_load_init(struct drm_device *dev);
3069 void i915_gem_load_cleanup(struct drm_device *dev);
3070 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3071 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3073 void *i915_gem_object_alloc(struct drm_device *dev);
3074 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3075 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3076 const struct drm_i915_gem_object_ops *ops);
3077 struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
3079 struct drm_i915_gem_object *i915_gem_object_create_from_data(
3080 struct drm_device *dev, const void *data, size_t size);
3081 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3082 void i915_gem_free_object(struct drm_gem_object *obj);
3084 struct i915_vma * __must_check
3085 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3086 const struct i915_ggtt_view *view,
3091 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3093 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
3094 int __must_check i915_vma_unbind(struct i915_vma *vma);
3095 void i915_vma_close(struct i915_vma *vma);
3096 void i915_vma_destroy(struct i915_vma *vma);
3098 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3099 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
3100 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
3101 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3103 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3105 static inline int __sg_page_count(struct scatterlist *sg)
3107 return sg->length >> PAGE_SHIFT;
3111 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
3113 static inline dma_addr_t
3114 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n)
3116 if (n < obj->get_page.last) {
3117 obj->get_page.sg = obj->pages->sgl;
3118 obj->get_page.last = 0;
3121 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3122 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3123 if (unlikely(sg_is_chain(obj->get_page.sg)))
3124 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3127 return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT);
3130 static inline struct page *
3131 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3133 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
3136 if (n < obj->get_page.last) {
3137 obj->get_page.sg = obj->pages->sgl;
3138 obj->get_page.last = 0;
3141 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3142 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3143 if (unlikely(sg_is_chain(obj->get_page.sg)))
3144 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3147 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3150 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3152 BUG_ON(obj->pages == NULL);
3153 obj->pages_pin_count++;
3156 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3158 BUG_ON(obj->pages_pin_count == 0);
3159 obj->pages_pin_count--;
3162 enum i915_map_type {
3168 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3169 * @obj - the object to map into kernel address space
3170 * @type - the type of mapping, used to select pgprot_t
3172 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3173 * pages and then returns a contiguous mapping of the backing storage into
3174 * the kernel address space. Based on the @type of mapping, the PTE will be
3175 * set to either WriteBack or WriteCombine (via pgprot_t).
3177 * The caller must hold the struct_mutex, and is responsible for calling
3178 * i915_gem_object_unpin_map() when the mapping is no longer required.
3180 * Returns the pointer through which to access the mapped object, or an
3181 * ERR_PTR() on error.
3183 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3184 enum i915_map_type type);
3187 * i915_gem_object_unpin_map - releases an earlier mapping
3188 * @obj - the object to unmap
3190 * After pinning the object and mapping its pages, once you are finished
3191 * with your access, call i915_gem_object_unpin_map() to release the pin
3192 * upon the mapping. Once the pin count reaches zero, that mapping may be
3195 * The caller must hold the struct_mutex.
3197 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3199 lockdep_assert_held(&obj->base.dev->struct_mutex);
3200 i915_gem_object_unpin_pages(obj);
3203 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3204 unsigned int *needs_clflush);
3205 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3206 unsigned int *needs_clflush);
3207 #define CLFLUSH_BEFORE 0x1
3208 #define CLFLUSH_AFTER 0x2
3209 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3212 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3214 i915_gem_object_unpin_pages(obj);
3217 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3218 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3219 struct drm_i915_gem_request *to);
3220 void i915_vma_move_to_active(struct i915_vma *vma,
3221 struct drm_i915_gem_request *req,
3222 unsigned int flags);
3223 int i915_gem_dumb_create(struct drm_file *file_priv,
3224 struct drm_device *dev,
3225 struct drm_mode_create_dumb *args);
3226 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3227 uint32_t handle, uint64_t *offset);
3228 int i915_gem_mmap_gtt_version(void);
3230 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3231 struct drm_i915_gem_object *new,
3232 unsigned frontbuffer_bits);
3234 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3236 struct drm_i915_gem_request *
3237 i915_gem_find_active_request(struct intel_engine_cs *engine);
3239 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3241 static inline u32 i915_reset_counter(struct i915_gpu_error *error)
3243 return atomic_read(&error->reset_counter);
3246 static inline bool __i915_reset_in_progress(u32 reset)
3248 return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
3251 static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
3253 return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3256 static inline bool __i915_terminally_wedged(u32 reset)
3258 return unlikely(reset & I915_WEDGED);
3261 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3263 return __i915_reset_in_progress(i915_reset_counter(error));
3266 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3268 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
3271 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3273 return __i915_terminally_wedged(i915_reset_counter(error));
3276 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3278 return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
3281 void i915_gem_reset(struct drm_device *dev);
3282 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3283 int __must_check i915_gem_init(struct drm_device *dev);
3284 int __must_check i915_gem_init_hw(struct drm_device *dev);
3285 void i915_gem_init_swizzling(struct drm_device *dev);
3286 void i915_gem_cleanup_engines(struct drm_device *dev);
3287 int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3288 bool interruptible);
3289 int __must_check i915_gem_suspend(struct drm_device *dev);
3290 void i915_gem_resume(struct drm_device *dev);
3291 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3293 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3296 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3299 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3300 struct i915_vma * __must_check
3301 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3303 const struct i915_ggtt_view *view);
3304 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3305 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3307 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3308 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3310 u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
3312 u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
3313 int tiling_mode, bool fenced);
3315 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3316 enum i915_cache_level cache_level);
3318 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3319 struct dma_buf *dma_buf);
3321 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3322 struct drm_gem_object *gem_obj, int flags);
3325 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3326 struct i915_address_space *vm,
3327 const struct i915_ggtt_view *view);
3330 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3331 struct i915_address_space *vm,
3332 const struct i915_ggtt_view *view);
3334 static inline struct i915_hw_ppgtt *
3335 i915_vm_to_ppgtt(struct i915_address_space *vm)
3337 return container_of(vm, struct i915_hw_ppgtt, base);
3340 static inline struct i915_vma *
3341 i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj,
3342 const struct i915_ggtt_view *view)
3344 return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view);
3347 static inline unsigned long
3348 i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o,
3349 const struct i915_ggtt_view *view)
3351 return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view));
3354 /* i915_gem_fence.c */
3355 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3356 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3359 * i915_vma_pin_fence - pin fencing state
3360 * @vma: vma to pin fencing for
3362 * This pins the fencing state (whether tiled or untiled) to make sure the
3363 * vma (and its object) is ready to be used as a scanout target. Fencing
3364 * status must be synchronize first by calling i915_vma_get_fence():
3366 * The resulting fence pin reference must be released again with
3367 * i915_vma_unpin_fence().
3371 * True if the vma has a fence, false otherwise.
3374 i915_vma_pin_fence(struct i915_vma *vma)
3377 vma->fence->pin_count++;
3384 * i915_vma_unpin_fence - unpin fencing state
3385 * @vma: vma to unpin fencing for
3387 * This releases the fence pin reference acquired through
3388 * i915_vma_pin_fence. It will handle both objects with and without an
3389 * attached fence correctly, callers do not need to distinguish this.
3392 i915_vma_unpin_fence(struct i915_vma *vma)
3395 GEM_BUG_ON(vma->fence->pin_count <= 0);
3396 vma->fence->pin_count--;
3400 void i915_gem_restore_fences(struct drm_device *dev);
3402 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3403 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3404 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3406 /* i915_gem_context.c */
3407 int __must_check i915_gem_context_init(struct drm_device *dev);
3408 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3409 void i915_gem_context_fini(struct drm_device *dev);
3410 void i915_gem_context_reset(struct drm_device *dev);
3411 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3412 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3413 int i915_switch_context(struct drm_i915_gem_request *req);
3414 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3415 void i915_gem_context_free(struct kref *ctx_ref);
3416 struct drm_i915_gem_object *
3417 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3418 struct i915_gem_context *
3419 i915_gem_context_create_gvt(struct drm_device *dev);
3421 static inline struct i915_gem_context *
3422 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3424 struct i915_gem_context *ctx;
3426 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3428 ctx = idr_find(&file_priv->context_idr, id);
3430 return ERR_PTR(-ENOENT);
3435 static inline struct i915_gem_context *
3436 i915_gem_context_get(struct i915_gem_context *ctx)
3438 kref_get(&ctx->ref);
3442 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3444 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3445 kref_put(&ctx->ref, i915_gem_context_free);
3448 static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3450 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3453 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3454 struct drm_file *file);
3455 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3456 struct drm_file *file);
3457 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3458 struct drm_file *file_priv);
3459 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3460 struct drm_file *file_priv);
3461 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
3462 struct drm_file *file);
3464 /* i915_gem_evict.c */
3465 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3466 u64 min_size, u64 alignment,
3467 unsigned cache_level,
3470 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3471 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3473 /* belongs in i915_gem_gtt.h */
3474 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3477 if (INTEL_GEN(dev_priv) < 6)
3478 intel_gtt_chipset_flush();
3481 /* i915_gem_stolen.c */
3482 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3483 struct drm_mm_node *node, u64 size,
3484 unsigned alignment);
3485 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3486 struct drm_mm_node *node, u64 size,
3487 unsigned alignment, u64 start,
3489 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3490 struct drm_mm_node *node);
3491 int i915_gem_init_stolen(struct drm_device *dev);
3492 void i915_gem_cleanup_stolen(struct drm_device *dev);
3493 struct drm_i915_gem_object *
3494 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3495 struct drm_i915_gem_object *
3496 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3501 /* i915_gem_shrinker.c */
3502 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3503 unsigned long target,
3505 #define I915_SHRINK_PURGEABLE 0x1
3506 #define I915_SHRINK_UNBOUND 0x2
3507 #define I915_SHRINK_BOUND 0x4
3508 #define I915_SHRINK_ACTIVE 0x8
3509 #define I915_SHRINK_VMAPS 0x10
3510 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3511 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3512 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3515 /* i915_gem_tiling.c */
3516 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3518 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3520 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3521 i915_gem_object_is_tiled(obj);
3524 /* i915_debugfs.c */
3525 #ifdef CONFIG_DEBUG_FS
3526 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3527 void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3528 int i915_debugfs_connector_add(struct drm_connector *connector);
3529 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3531 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3532 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3533 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3535 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3538 /* i915_gpu_error.c */
3540 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3541 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3542 const struct i915_error_state_file_priv *error);
3543 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3544 struct drm_i915_private *i915,
3545 size_t count, loff_t pos);
3546 static inline void i915_error_state_buf_release(
3547 struct drm_i915_error_state_buf *eb)
3551 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3553 const char *error_msg);
3554 void i915_error_state_get(struct drm_device *dev,
3555 struct i915_error_state_file_priv *error_priv);
3556 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3557 void i915_destroy_error_state(struct drm_device *dev);
3559 void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
3560 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3562 /* i915_cmd_parser.c */
3563 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3564 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3565 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3566 bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine);
3567 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3568 struct drm_i915_gem_object *batch_obj,
3569 struct drm_i915_gem_object *shadow_batch_obj,
3570 u32 batch_start_offset,
3574 /* i915_suspend.c */
3575 extern int i915_save_state(struct drm_device *dev);
3576 extern int i915_restore_state(struct drm_device *dev);
3579 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3580 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3583 extern int intel_setup_gmbus(struct drm_device *dev);
3584 extern void intel_teardown_gmbus(struct drm_device *dev);
3585 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3588 extern struct i2c_adapter *
3589 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3590 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3591 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3592 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3594 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3596 extern void intel_i2c_reset(struct drm_device *dev);
3599 int intel_bios_init(struct drm_i915_private *dev_priv);
3600 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3601 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3602 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3603 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3604 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3605 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3606 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3607 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3610 /* intel_opregion.c */
3612 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3613 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3614 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3615 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3616 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3618 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3620 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3622 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3623 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3624 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3625 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3629 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3634 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3638 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3646 extern void intel_register_dsm_handler(void);
3647 extern void intel_unregister_dsm_handler(void);
3649 static inline void intel_register_dsm_handler(void) { return; }
3650 static inline void intel_unregister_dsm_handler(void) { return; }
3651 #endif /* CONFIG_ACPI */
3653 /* intel_device_info.c */
3654 static inline struct intel_device_info *
3655 mkwrite_device_info(struct drm_i915_private *dev_priv)
3657 return (struct intel_device_info *)&dev_priv->info;
3660 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3661 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3664 extern void intel_modeset_init_hw(struct drm_device *dev);
3665 extern void intel_modeset_init(struct drm_device *dev);
3666 extern void intel_modeset_gem_init(struct drm_device *dev);
3667 extern void intel_modeset_cleanup(struct drm_device *dev);
3668 extern int intel_connector_register(struct drm_connector *);
3669 extern void intel_connector_unregister(struct drm_connector *);
3670 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3671 extern void intel_display_resume(struct drm_device *dev);
3672 extern void i915_redisable_vga(struct drm_device *dev);
3673 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3674 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3675 extern void intel_init_pch_refclk(struct drm_device *dev);
3676 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3677 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3680 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3681 struct drm_file *file);
3684 extern struct intel_overlay_error_state *
3685 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3686 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3687 struct intel_overlay_error_state *error);
3689 extern struct intel_display_error_state *
3690 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3691 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3692 struct drm_device *dev,
3693 struct intel_display_error_state *error);
3695 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3696 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3698 /* intel_sideband.c */
3699 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3700 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3701 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3702 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3703 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3704 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3705 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3706 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3707 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3708 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3709 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3710 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3711 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3712 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3713 enum intel_sbi_destination destination);
3714 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3715 enum intel_sbi_destination destination);
3716 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3717 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3719 /* intel_dpio_phy.c */
3720 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3721 u32 deemph_reg_value, u32 margin_reg_value,
3722 bool uniq_trans_scale);
3723 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3725 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3726 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3727 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3728 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3730 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3731 u32 demph_reg_value, u32 preemph_reg_value,
3732 u32 uniqtranscale_reg_value, u32 tx3_demph);
3733 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3734 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3735 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3737 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3738 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3740 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3741 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3743 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3744 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3745 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3746 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3748 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3749 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3750 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3751 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3753 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3754 * will be implemented using 2 32-bit writes in an arbitrary order with
3755 * an arbitrary delay between them. This can cause the hardware to
3756 * act upon the intermediate value, possibly leading to corruption and
3757 * machine death. You have been warned.
3759 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3760 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3762 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3763 u32 upper, lower, old_upper, loop = 0; \
3764 upper = I915_READ(upper_reg); \
3766 old_upper = upper; \
3767 lower = I915_READ(lower_reg); \
3768 upper = I915_READ(upper_reg); \
3769 } while (upper != old_upper && loop++ < 2); \
3770 (u64)upper << 32 | lower; })
3772 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3773 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3775 #define __raw_read(x, s) \
3776 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3779 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3782 #define __raw_write(x, s) \
3783 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3784 i915_reg_t reg, uint##x##_t val) \
3786 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3801 /* These are untraced mmio-accessors that are only valid to be used inside
3802 * critical sections inside IRQ handlers where forcewake is explicitly
3804 * Think twice, and think again, before using these.
3805 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3806 * intel_uncore_forcewake_irqunlock().
3808 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3809 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3810 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3811 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3813 /* "Broadcast RGB" property */
3814 #define INTEL_BROADCAST_RGB_AUTO 0
3815 #define INTEL_BROADCAST_RGB_FULL 1
3816 #define INTEL_BROADCAST_RGB_LIMITED 2
3818 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3820 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3821 return VLV_VGACNTRL;
3822 else if (INTEL_INFO(dev)->gen >= 5)
3823 return CPU_VGACNTRL;
3828 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3830 unsigned long j = msecs_to_jiffies(m);
3832 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3835 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3837 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3840 static inline unsigned long
3841 timespec_to_jiffies_timeout(const struct timespec *value)
3843 unsigned long j = timespec_to_jiffies(value);
3845 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3849 * If you need to wait X milliseconds between events A and B, but event B
3850 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3851 * when event A happened, then just before event B you call this function and
3852 * pass the timestamp as the first argument, and X as the second argument.
3855 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3857 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3860 * Don't re-read the value of "jiffies" every time since it may change
3861 * behind our back and break the math.
3863 tmp_jiffies = jiffies;
3864 target_jiffies = timestamp_jiffies +
3865 msecs_to_jiffies_timeout(to_wait_ms);
3867 if (time_after(target_jiffies, tmp_jiffies)) {
3868 remaining_jiffies = target_jiffies - tmp_jiffies;
3869 while (remaining_jiffies)
3871 schedule_timeout_uninterruptible(remaining_jiffies);
3874 static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
3876 struct intel_engine_cs *engine = req->engine;
3878 /* Before we do the heavier coherent read of the seqno,
3879 * check the value (hopefully) in the CPU cacheline.
3881 if (i915_gem_request_completed(req))
3884 /* Ensure our read of the seqno is coherent so that we
3885 * do not "miss an interrupt" (i.e. if this is the last
3886 * request and the seqno write from the GPU is not visible
3887 * by the time the interrupt fires, we will see that the
3888 * request is incomplete and go back to sleep awaiting
3889 * another interrupt that will never come.)
3891 * Strictly, we only need to do this once after an interrupt,
3892 * but it is easier and safer to do it every time the waiter
3895 if (engine->irq_seqno_barrier &&
3896 rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
3897 cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
3898 struct task_struct *tsk;
3900 /* The ordering of irq_posted versus applying the barrier
3901 * is crucial. The clearing of the current irq_posted must
3902 * be visible before we perform the barrier operation,
3903 * such that if a subsequent interrupt arrives, irq_posted
3904 * is reasserted and our task rewoken (which causes us to
3905 * do another __i915_request_irq_complete() immediately
3906 * and reapply the barrier). Conversely, if the clear
3907 * occurs after the barrier, then an interrupt that arrived
3908 * whilst we waited on the barrier would not trigger a
3909 * barrier on the next pass, and the read may not see the
3912 engine->irq_seqno_barrier(engine);
3914 /* If we consume the irq, but we are no longer the bottom-half,
3915 * the real bottom-half may not have serialised their own
3916 * seqno check with the irq-barrier (i.e. may have inspected
3917 * the seqno before we believe it coherent since they see
3918 * irq_posted == false but we are still running).
3921 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
3922 if (tsk && tsk != current)
3923 /* Note that if the bottom-half is changed as we
3924 * are sending the wake-up, the new bottom-half will
3925 * be woken by whomever made the change. We only have
3926 * to worry about when we steal the irq-posted for
3929 wake_up_process(tsk);
3932 if (i915_gem_request_completed(req))
3936 /* We need to check whether any gpu reset happened in between
3937 * the request being submitted and now. If a reset has occurred,
3938 * the seqno will have been advance past ours and our request
3939 * is complete. If we are in the process of handling a reset,
3940 * the request is effectively complete as the rendering will
3941 * be discarded, but we need to return in order to drop the
3944 if (i915_reset_in_progress(&req->i915->gpu_error))
3950 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3951 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3954 int remap_io_mapping(struct vm_area_struct *vma,
3955 unsigned long addr, unsigned long pfn, unsigned long size,
3956 struct io_mapping *iomap);
3958 #define ptr_mask_bits(ptr) ({ \
3959 unsigned long __v = (unsigned long)(ptr); \
3960 (typeof(ptr))(__v & PAGE_MASK); \
3963 #define ptr_unpack_bits(ptr, bits) ({ \
3964 unsigned long __v = (unsigned long)(ptr); \
3965 (bits) = __v & ~PAGE_MASK; \
3966 (typeof(ptr))(__v & PAGE_MASK); \
3969 #define ptr_pack_bits(ptr, bits) \
3970 ((typeof(ptr))((unsigned long)(ptr) | (bits)))
3972 #define fetch_and_zero(ptr) ({ \
3973 typeof(*ptr) __T = *(ptr); \
3974 *(ptr) = (typeof(*ptr))0; \