1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
53 #include "i915_params.h"
56 #include "intel_bios.h"
57 #include "intel_dpll_mgr.h"
59 #include "intel_lrc.h"
60 #include "intel_ringbuffer.h"
63 #include "i915_gem_fence_reg.h"
64 #include "i915_gem_object.h"
65 #include "i915_gem_gtt.h"
66 #include "i915_gem_render_state.h"
67 #include "i915_gem_request.h"
68 #include "i915_gem_timeline.h"
72 #include "intel_gvt.h"
74 /* General customization:
77 #define DRIVER_NAME "i915"
78 #define DRIVER_DESC "Intel Graphics"
79 #define DRIVER_DATE "20161205"
80 #define DRIVER_TIMESTAMP 1480926326
83 /* Many gcc seem to no see through this and fall over :( */
85 #define WARN_ON(x) ({ \
86 bool __i915_warn_cond = (x); \
87 if (__builtin_constant_p(__i915_warn_cond)) \
88 BUILD_BUG_ON(__i915_warn_cond); \
89 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
91 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
95 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
97 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
98 (long) (x), __func__);
100 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
101 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
102 * which may not necessarily be a user visible problem. This will either
103 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
104 * enable distros and users to tailor their preferred amount of i915 abrt
107 #define I915_STATE_WARN(condition, format...) ({ \
108 int __ret_warn_on = !!(condition); \
109 if (unlikely(__ret_warn_on)) \
110 if (!WARN(i915.verbose_state_checks, format)) \
112 unlikely(__ret_warn_on); \
115 #define I915_STATE_WARN_ON(x) \
116 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
118 bool __i915_inject_load_failure(const char *func, int line);
119 #define i915_inject_load_failure() \
120 __i915_inject_load_failure(__func__, __LINE__)
124 } uint_fixed_16_16_t;
126 #define FP_16_16_MAX ({ \
127 uint_fixed_16_16_t fp; \
132 static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
134 uint_fixed_16_16_t fp;
142 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
144 return DIV_ROUND_UP(fp.val, 1 << 16);
147 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
152 static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
153 uint_fixed_16_16_t min2)
155 uint_fixed_16_16_t min;
157 min.val = min(min1.val, min2.val);
161 static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
162 uint_fixed_16_16_t max2)
164 uint_fixed_16_16_t max;
166 max.val = max(max1.val, max2.val);
170 static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
173 uint_fixed_16_16_t fp, res;
175 fp = u32_to_fixed_16_16(val);
176 res.val = DIV_ROUND_UP(fp.val, d);
180 static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
183 uint_fixed_16_16_t res;
186 interm_val = (uint64_t)val << 16;
187 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
188 WARN_ON(interm_val >> 32);
189 res.val = (uint32_t) interm_val;
194 static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
195 uint_fixed_16_16_t mul)
197 uint64_t intermediate_val;
198 uint_fixed_16_16_t fp;
200 intermediate_val = (uint64_t) val * mul.val;
201 WARN_ON(intermediate_val >> 32);
202 fp.val = (uint32_t) intermediate_val;
206 static inline const char *yesno(bool v)
208 return v ? "yes" : "no";
211 static inline const char *onoff(bool v)
213 return v ? "on" : "off";
216 static inline const char *enableddisabled(bool v)
218 return v ? "enabled" : "disabled";
221 #define range_overflows(start, size, max) ({ \
222 typeof(start) start__ = (start); \
223 typeof(size) size__ = (size); \
224 typeof(max) max__ = (max); \
225 (void)(&start__ == &size__); \
226 (void)(&start__ == &max__); \
227 start__ > max__ || size__ > max__ - start__; \
230 #define range_overflows_t(type, start, size, max) \
231 range_overflows((type)(start), (type)(size), (type)(max))
239 I915_MAX_PIPES = _PIPE_EDP
241 #define pipe_name(p) ((p) + 'A')
253 static inline const char *transcoder_name(enum transcoder transcoder)
255 switch (transcoder) {
264 case TRANSCODER_DSI_A:
266 case TRANSCODER_DSI_C:
273 static inline bool transcoder_is_dsi(enum transcoder transcoder)
275 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
279 * Global legacy plane identifier. Valid only for primary/sprite
280 * planes on pre-g4x, and only for primary planes on g4x+.
287 #define plane_name(p) ((p) + 'A')
289 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
292 * Per-pipe plane identifier.
293 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
294 * number of planes per CRTC. Not all platforms really have this many planes,
295 * which means some arrays of size I915_MAX_PLANES may have unused entries
296 * between the topmost sprite plane and the cursor plane.
298 * This is expected to be passed to various register macros
299 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
309 #define for_each_plane_id_on_crtc(__crtc, __p) \
310 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
311 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
322 #define port_name(p) ((p) + 'A')
324 #define I915_NUM_PHYS_VLV 2
337 enum intel_display_power_domain {
341 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
342 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
343 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
344 POWER_DOMAIN_TRANSCODER_A,
345 POWER_DOMAIN_TRANSCODER_B,
346 POWER_DOMAIN_TRANSCODER_C,
347 POWER_DOMAIN_TRANSCODER_EDP,
348 POWER_DOMAIN_TRANSCODER_DSI_A,
349 POWER_DOMAIN_TRANSCODER_DSI_C,
350 POWER_DOMAIN_PORT_DDI_A_LANES,
351 POWER_DOMAIN_PORT_DDI_B_LANES,
352 POWER_DOMAIN_PORT_DDI_C_LANES,
353 POWER_DOMAIN_PORT_DDI_D_LANES,
354 POWER_DOMAIN_PORT_DDI_E_LANES,
355 POWER_DOMAIN_PORT_DSI,
356 POWER_DOMAIN_PORT_CRT,
357 POWER_DOMAIN_PORT_OTHER,
366 POWER_DOMAIN_MODESET,
372 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
373 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
374 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
375 #define POWER_DOMAIN_TRANSCODER(tran) \
376 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
377 (tran) + POWER_DOMAIN_TRANSCODER_A)
381 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
393 #define for_each_hpd_pin(__pin) \
394 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
396 struct i915_hotplug {
397 struct work_struct hotplug_work;
400 unsigned long last_jiffies;
405 HPD_MARK_DISABLED = 2
407 } stats[HPD_NUM_PINS];
409 struct delayed_work reenable_work;
411 struct intel_digital_port *irq_port[I915_MAX_PORTS];
414 struct work_struct dig_port_work;
416 struct work_struct poll_init_work;
420 * if we get a HPD irq from DP and a HPD irq from non-DP
421 * the non-DP HPD could block the workqueue on a mode config
422 * mutex getting, that userspace may have taken. However
423 * userspace is waiting on the DP workqueue to run which is
424 * blocked behind the non-DP one.
426 struct workqueue_struct *dp_wq;
429 #define I915_GEM_GPU_DOMAINS \
430 (I915_GEM_DOMAIN_RENDER | \
431 I915_GEM_DOMAIN_SAMPLER | \
432 I915_GEM_DOMAIN_COMMAND | \
433 I915_GEM_DOMAIN_INSTRUCTION | \
434 I915_GEM_DOMAIN_VERTEX)
436 #define for_each_pipe(__dev_priv, __p) \
437 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
438 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
439 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
440 for_each_if ((__mask) & (1 << (__p)))
441 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
443 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
445 #define for_each_sprite(__dev_priv, __p, __s) \
447 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
450 #define for_each_port_masked(__port, __ports_mask) \
451 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
452 for_each_if ((__ports_mask) & (1 << (__port)))
454 #define for_each_crtc(dev, crtc) \
455 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
457 #define for_each_intel_plane(dev, intel_plane) \
458 list_for_each_entry(intel_plane, \
459 &(dev)->mode_config.plane_list, \
462 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
463 list_for_each_entry(intel_plane, \
464 &(dev)->mode_config.plane_list, \
466 for_each_if ((plane_mask) & \
467 (1 << drm_plane_index(&intel_plane->base)))
469 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
470 list_for_each_entry(intel_plane, \
471 &(dev)->mode_config.plane_list, \
473 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
475 #define for_each_intel_crtc(dev, intel_crtc) \
476 list_for_each_entry(intel_crtc, \
477 &(dev)->mode_config.crtc_list, \
480 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
481 list_for_each_entry(intel_crtc, \
482 &(dev)->mode_config.crtc_list, \
484 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
486 #define for_each_intel_encoder(dev, intel_encoder) \
487 list_for_each_entry(intel_encoder, \
488 &(dev)->mode_config.encoder_list, \
491 #define for_each_intel_connector(dev, intel_connector) \
492 list_for_each_entry(intel_connector, \
493 &(dev)->mode_config.connector_list, \
496 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
497 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
498 for_each_if ((intel_encoder)->base.crtc == (__crtc))
500 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
501 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
502 for_each_if ((intel_connector)->base.encoder == (__encoder))
504 #define for_each_power_domain(domain, mask) \
505 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
506 for_each_if ((1 << (domain)) & (mask))
508 struct drm_i915_private;
509 struct i915_mm_struct;
510 struct i915_mmu_object;
512 struct drm_i915_file_private {
513 struct drm_i915_private *dev_priv;
514 struct drm_file *file;
518 struct list_head request_list;
519 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
520 * chosen to prevent the CPU getting more than a frame ahead of the GPU
521 * (when using lax throttling for the frontbuffer). We also use it to
522 * offer free GPU waitboosts for severely congested workloads.
524 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
526 struct idr context_idr;
528 struct intel_rps_client {
529 struct list_head link;
533 unsigned int bsd_engine;
535 /* Client can have a maximum of 3 contexts banned before
536 * it is denied of creating new contexts. As one context
537 * ban needs 4 consecutive hangs, and more if there is
538 * progress in between, this is a last resort stop gap measure
539 * to limit the badly behaving clients access to gpu.
541 #define I915_MAX_CLIENT_CONTEXT_BANS 3
545 /* Used by dp and fdi links */
546 struct intel_link_m_n {
554 void intel_link_compute_m_n(int bpp, int nlanes,
555 int pixel_clock, int link_clock,
556 struct intel_link_m_n *m_n);
558 /* Interface history:
561 * 1.2: Add Power Management
562 * 1.3: Add vblank support
563 * 1.4: Fix cmdbuffer path, add heap destroy
564 * 1.5: Add vblank pipe configuration
565 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
566 * - Support vertical blank on secondary display pipe
568 #define DRIVER_MAJOR 1
569 #define DRIVER_MINOR 6
570 #define DRIVER_PATCHLEVEL 0
572 struct opregion_header;
573 struct opregion_acpi;
574 struct opregion_swsci;
575 struct opregion_asle;
577 struct intel_opregion {
578 struct opregion_header *header;
579 struct opregion_acpi *acpi;
580 struct opregion_swsci *swsci;
581 u32 swsci_gbda_sub_functions;
582 u32 swsci_sbcb_sub_functions;
583 struct opregion_asle *asle;
588 struct work_struct asle_work;
590 #define OPREGION_SIZE (8*1024)
592 struct intel_overlay;
593 struct intel_overlay_error_state;
595 struct sdvo_device_mapping {
604 struct intel_connector;
605 struct intel_encoder;
606 struct intel_atomic_state;
607 struct intel_crtc_state;
608 struct intel_initial_plane_config;
613 struct drm_i915_display_funcs {
614 int (*get_display_clock_speed)(struct drm_i915_private *dev_priv);
615 int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
616 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
617 int (*compute_intermediate_wm)(struct drm_device *dev,
618 struct intel_crtc *intel_crtc,
619 struct intel_crtc_state *newstate);
620 void (*initial_watermarks)(struct intel_atomic_state *state,
621 struct intel_crtc_state *cstate);
622 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
623 struct intel_crtc_state *cstate);
624 void (*optimize_watermarks)(struct intel_atomic_state *state,
625 struct intel_crtc_state *cstate);
626 int (*compute_global_watermarks)(struct drm_atomic_state *state);
627 void (*update_wm)(struct intel_crtc *crtc);
628 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
629 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
630 /* Returns the active state of the crtc, and if the crtc is active,
631 * fills out the pipe-config with the hw state. */
632 bool (*get_pipe_config)(struct intel_crtc *,
633 struct intel_crtc_state *);
634 void (*get_initial_plane_config)(struct intel_crtc *,
635 struct intel_initial_plane_config *);
636 int (*crtc_compute_clock)(struct intel_crtc *crtc,
637 struct intel_crtc_state *crtc_state);
638 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
639 struct drm_atomic_state *old_state);
640 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
641 struct drm_atomic_state *old_state);
642 void (*update_crtcs)(struct drm_atomic_state *state,
643 unsigned int *crtc_vblank_mask);
644 void (*audio_codec_enable)(struct drm_connector *connector,
645 struct intel_encoder *encoder,
646 const struct drm_display_mode *adjusted_mode);
647 void (*audio_codec_disable)(struct intel_encoder *encoder);
648 void (*fdi_link_train)(struct drm_crtc *crtc);
649 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
650 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
651 struct drm_framebuffer *fb,
652 struct drm_i915_gem_object *obj,
653 struct drm_i915_gem_request *req,
655 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
656 /* clock updates for mode set */
658 /* render clock increase/decrease */
659 /* display clock increase/decrease */
660 /* pll clock increase/decrease */
662 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
663 void (*load_luts)(struct drm_crtc_state *crtc_state);
666 enum forcewake_domain_id {
667 FW_DOMAIN_ID_RENDER = 0,
668 FW_DOMAIN_ID_BLITTER,
674 enum forcewake_domains {
675 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
676 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
677 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
678 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
683 #define FW_REG_READ (1)
684 #define FW_REG_WRITE (2)
686 enum decoupled_power_domain {
687 GEN9_DECOUPLED_PD_BLITTER = 0,
688 GEN9_DECOUPLED_PD_RENDER,
689 GEN9_DECOUPLED_PD_MEDIA,
690 GEN9_DECOUPLED_PD_ALL
694 GEN9_DECOUPLED_OP_WRITE = 0,
695 GEN9_DECOUPLED_OP_READ
698 enum forcewake_domains
699 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
700 i915_reg_t reg, unsigned int op);
702 struct intel_uncore_funcs {
703 void (*force_wake_get)(struct drm_i915_private *dev_priv,
704 enum forcewake_domains domains);
705 void (*force_wake_put)(struct drm_i915_private *dev_priv,
706 enum forcewake_domains domains);
708 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
709 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
710 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
711 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
713 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
714 uint8_t val, bool trace);
715 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
716 uint16_t val, bool trace);
717 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
718 uint32_t val, bool trace);
721 struct intel_forcewake_range {
725 enum forcewake_domains domains;
728 struct intel_uncore {
729 spinlock_t lock; /** lock is also taken in irq contexts. */
731 const struct intel_forcewake_range *fw_domains_table;
732 unsigned int fw_domains_table_entries;
734 struct intel_uncore_funcs funcs;
738 enum forcewake_domains fw_domains;
739 enum forcewake_domains fw_domains_active;
741 struct intel_uncore_forcewake_domain {
742 struct drm_i915_private *i915;
743 enum forcewake_domain_id id;
744 enum forcewake_domains mask;
746 struct hrtimer timer;
753 } fw_domain[FW_DOMAIN_ID_COUNT];
755 int unclaimed_mmio_check;
758 /* Iterate over initialised fw domains */
759 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
760 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
761 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
763 for_each_if ((mask__) & (domain__)->mask)
765 #define for_each_fw_domain(domain__, dev_priv__) \
766 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
768 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
769 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
770 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
773 struct work_struct work;
775 uint32_t *dmc_payload;
776 uint32_t dmc_fw_size;
779 i915_reg_t mmioaddr[8];
780 uint32_t mmiodata[8];
782 uint32_t allowed_dc_mask;
785 #define DEV_INFO_FOR_EACH_FLAG(func) \
788 func(is_alpha_support); \
789 /* Keep has_* in alphabetical order */ \
790 func(has_64bit_reloc); \
791 func(has_aliasing_ppgtt); \
794 func(has_decoupled_mmio); \
797 func(has_fpga_dbg); \
798 func(has_full_ppgtt); \
799 func(has_full_48bit_ppgtt); \
800 func(has_gmbus_irq); \
801 func(has_gmch_display); \
804 func(has_hw_contexts); \
807 func(has_logical_ring_contexts); \
809 func(has_pipe_cxsr); \
810 func(has_pooled_eu); \
814 func(has_resource_streamer); \
815 func(has_runtime_pm); \
817 func(cursor_needs_physical); \
818 func(hws_needs_physical); \
819 func(overlay_needs_physical); \
822 struct sseu_dev_info {
828 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
831 u8 has_subslice_pg:1;
835 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
837 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
840 /* Keep in gen based order, and chronological order within a gen */
841 enum intel_platform {
842 INTEL_PLATFORM_UNINITIALIZED = 0,
870 struct intel_device_info {
871 u32 display_mmio_offset;
874 u8 num_sprites[I915_MAX_PIPES];
877 enum intel_platform platform;
878 u8 ring_mask; /* Rings supported by the HW */
880 #define DEFINE_FLAG(name) u8 name:1
881 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
883 u16 ddb_size; /* in blocks */
884 /* Register offsets for the various display pipes and transcoders */
885 int pipe_offsets[I915_MAX_TRANSCODERS];
886 int trans_offsets[I915_MAX_TRANSCODERS];
887 int palette_offsets[I915_MAX_PIPES];
888 int cursor_offsets[I915_MAX_PIPES];
890 /* Slice/subslice/EU info */
891 struct sseu_dev_info sseu;
894 u16 degamma_lut_size;
899 struct intel_display_error_state;
901 struct drm_i915_error_state {
904 struct timeval boottime;
905 struct timeval uptime;
907 struct drm_i915_private *i915;
914 struct intel_device_info device_info;
916 /* Generic register state */
924 u32 error; /* gen6+ */
925 u32 err_int; /* gen7 */
926 u32 fault_data0; /* gen8, gen9 */
927 u32 fault_data1; /* gen8, gen9 */
934 u64 fence[I915_MAX_NUM_FENCES];
935 struct intel_overlay_error_state *overlay;
936 struct intel_display_error_state *display;
937 struct drm_i915_error_object *semaphore;
938 struct drm_i915_error_object *guc_log;
940 struct drm_i915_error_engine {
942 /* Software tracked state */
945 unsigned long hangcheck_timestamp;
946 bool hangcheck_stalled;
947 enum intel_engine_hangcheck_action hangcheck_action;
948 struct i915_address_space *vm;
951 /* position of active request inside the ring */
952 u32 rq_head, rq_post, rq_tail;
954 /* our own tracking of ring head and tail */
977 u32 rc_psmi; /* sleep state */
978 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
979 struct intel_instdone instdone;
981 struct drm_i915_error_object {
987 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
989 struct drm_i915_error_object *wa_ctx;
991 struct drm_i915_error_request {
999 } *requests, execlist[2];
1001 struct drm_i915_error_waiter {
1002 char comm[TASK_COMM_LEN];
1016 char comm[TASK_COMM_LEN];
1018 } engine[I915_NUM_ENGINES];
1020 struct drm_i915_error_buffer {
1023 u32 rseqno[I915_NUM_ENGINES], wseqno;
1027 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
1034 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
1035 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
1036 struct i915_address_space *active_vm[I915_NUM_ENGINES];
1039 enum i915_cache_level {
1040 I915_CACHE_NONE = 0,
1041 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
1042 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
1043 caches, eg sampler/render caches, and the
1044 large Last-Level-Cache. LLC is coherent with
1045 the CPU, but L3 is only visible to the GPU. */
1046 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1049 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1051 #define DEFAULT_CONTEXT_HANDLE 0
1054 * struct i915_gem_context - as the name implies, represents a context.
1055 * @ref: reference count.
1056 * @user_handle: userspace tracking identity for this context.
1057 * @remap_slice: l3 row remapping information.
1058 * @flags: context specific flags:
1059 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
1060 * @file_priv: filp associated with this context (NULL for global default
1062 * @hang_stats: information about the role of this context in possible GPU
1064 * @ppgtt: virtual memory space used by this context.
1065 * @legacy_hw_ctx: render context backing object and whether it is correctly
1066 * initialized (legacy ring submission mechanism only).
1067 * @link: link in the global list of contexts.
1069 * Contexts are memory images used by the hardware to store copies of their
1072 struct i915_gem_context {
1074 struct drm_i915_private *i915;
1075 struct drm_i915_file_private *file_priv;
1076 struct i915_hw_ppgtt *ppgtt;
1080 unsigned long flags;
1081 #define CONTEXT_NO_ZEROMAP BIT(0)
1082 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
1084 /* Unique identifier for this context, used by the hw for tracking */
1087 int priority; /* greater priorities are serviced first */
1091 struct intel_context {
1092 struct i915_vma *state;
1093 struct intel_ring *ring;
1094 uint32_t *lrc_reg_state;
1098 } engine[I915_NUM_ENGINES];
1101 struct atomic_notifier_head status_notifier;
1102 bool execlists_force_single_submission;
1104 struct list_head link;
1111 unsigned int guilty_count; /* guilty of a hang */
1112 unsigned int active_count; /* active during hang */
1114 #define CONTEXT_SCORE_GUILTY 10
1115 #define CONTEXT_SCORE_BAN_THRESHOLD 40
1116 /* Accumulated score of hangs caused by this context */
1129 /* This is always the inner lock when overlapping with struct_mutex and
1130 * it's the outer lock when overlapping with stolen_lock. */
1133 unsigned int possible_framebuffer_bits;
1134 unsigned int busy_bits;
1135 unsigned int visible_pipes_mask;
1136 struct intel_crtc *crtc;
1138 struct drm_mm_node compressed_fb;
1139 struct drm_mm_node *compressed_llb;
1146 bool underrun_detected;
1147 struct work_struct underrun_work;
1149 struct intel_fbc_state_cache {
1151 unsigned int mode_flags;
1152 uint32_t hsw_bdw_pixel_rate;
1156 unsigned int rotation;
1163 u64 ilk_ggtt_offset;
1164 uint32_t pixel_format;
1165 unsigned int stride;
1167 unsigned int tiling_mode;
1171 struct intel_fbc_reg_params {
1175 unsigned int fence_y_offset;
1180 uint32_t pixel_format;
1181 unsigned int stride;
1188 struct intel_fbc_work {
1190 u32 scheduled_vblank;
1191 struct work_struct work;
1194 const char *no_fbc_reason;
1198 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1199 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1200 * parsing for same resolution.
1202 enum drrs_refresh_rate_type {
1205 DRRS_MAX_RR, /* RR count */
1208 enum drrs_support_type {
1209 DRRS_NOT_SUPPORTED = 0,
1210 STATIC_DRRS_SUPPORT = 1,
1211 SEAMLESS_DRRS_SUPPORT = 2
1217 struct delayed_work work;
1218 struct intel_dp *dp;
1219 unsigned busy_frontbuffer_bits;
1220 enum drrs_refresh_rate_type refresh_rate_type;
1221 enum drrs_support_type type;
1228 struct intel_dp *enabled;
1230 struct delayed_work work;
1231 unsigned busy_frontbuffer_bits;
1233 bool aux_frame_sync;
1238 PCH_NONE = 0, /* No PCH present */
1239 PCH_IBX, /* Ibexpeak PCH */
1240 PCH_CPT, /* Cougarpoint PCH */
1241 PCH_LPT, /* Lynxpoint PCH */
1242 PCH_SPT, /* Sunrisepoint PCH */
1243 PCH_KBP, /* Kabypoint PCH */
1247 enum intel_sbi_destination {
1252 #define QUIRK_PIPEA_FORCE (1<<0)
1253 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1254 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1255 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1256 #define QUIRK_PIPEB_FORCE (1<<4)
1257 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1260 struct intel_fbc_work;
1262 struct intel_gmbus {
1263 struct i2c_adapter adapter;
1264 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1267 i915_reg_t gpio_reg;
1268 struct i2c_algo_bit_data bit_algo;
1269 struct drm_i915_private *dev_priv;
1272 struct i915_suspend_saved_registers {
1274 u32 saveFBC_CONTROL;
1275 u32 saveCACHE_MODE_0;
1276 u32 saveMI_ARB_STATE;
1280 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1281 u32 savePCH_PORT_HOTPLUG;
1285 struct vlv_s0ix_state {
1292 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1293 u32 media_max_req_count;
1294 u32 gfx_max_req_count;
1320 u32 rp_down_timeout;
1326 /* Display 1 CZ domain */
1331 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1333 /* GT SA CZ domain */
1340 /* Display 2 CZ domain */
1344 u32 clock_gate_dis2;
1347 struct intel_rps_ei {
1353 struct intel_gen6_power_mgmt {
1355 * work, interrupts_enabled and pm_iir are protected by
1356 * dev_priv->irq_lock
1358 struct work_struct work;
1359 bool interrupts_enabled;
1362 /* PM interrupt bits that should never be masked */
1365 /* Frequencies are stored in potentially platform dependent multiples.
1366 * In other words, *_freq needs to be multiplied by X to be interesting.
1367 * Soft limits are those which are used for the dynamic reclocking done
1368 * by the driver (raise frequencies under heavy loads, and lower for
1369 * lighter loads). Hard limits are those imposed by the hardware.
1371 * A distinction is made for overclocking, which is never enabled by
1372 * default, and is considered to be above the hard limit if it's
1375 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1376 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1377 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1378 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1379 u8 min_freq; /* AKA RPn. Minimum frequency */
1380 u8 boost_freq; /* Frequency to request when wait boosting */
1381 u8 idle_freq; /* Frequency to request when we are idle */
1382 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1383 u8 rp1_freq; /* "less than" RP0 power/freqency */
1384 u8 rp0_freq; /* Non-overclocked max frequency. */
1385 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1387 u8 up_threshold; /* Current %busy required to uplock */
1388 u8 down_threshold; /* Current %busy required to downclock */
1391 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1393 spinlock_t client_lock;
1394 struct list_head clients;
1398 struct delayed_work autoenable_work;
1401 /* manual wa residency calculations */
1402 struct intel_rps_ei up_ei, down_ei;
1405 * Protects RPS/RC6 register access and PCU communication.
1406 * Must be taken after struct_mutex if nested. Note that
1407 * this lock may be held for long periods of time when
1408 * talking to hw - so only take it when talking to hw!
1410 struct mutex hw_lock;
1413 /* defined intel_pm.c */
1414 extern spinlock_t mchdev_lock;
1416 struct intel_ilk_power_mgmt {
1424 unsigned long last_time1;
1425 unsigned long chipset_power;
1428 unsigned long gfx_power;
1435 struct drm_i915_private;
1436 struct i915_power_well;
1438 struct i915_power_well_ops {
1440 * Synchronize the well's hw state to match the current sw state, for
1441 * example enable/disable it based on the current refcount. Called
1442 * during driver init and resume time, possibly after first calling
1443 * the enable/disable handlers.
1445 void (*sync_hw)(struct drm_i915_private *dev_priv,
1446 struct i915_power_well *power_well);
1448 * Enable the well and resources that depend on it (for example
1449 * interrupts located on the well). Called after the 0->1 refcount
1452 void (*enable)(struct drm_i915_private *dev_priv,
1453 struct i915_power_well *power_well);
1455 * Disable the well and resources that depend on it. Called after
1456 * the 1->0 refcount transition.
1458 void (*disable)(struct drm_i915_private *dev_priv,
1459 struct i915_power_well *power_well);
1460 /* Returns the hw enabled state. */
1461 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1462 struct i915_power_well *power_well);
1465 /* Power well structure for haswell */
1466 struct i915_power_well {
1469 /* power well enable/disable usage count */
1471 /* cached hw enabled state */
1473 unsigned long domains;
1474 /* unique identifier for this power well */
1477 * Arbitraty data associated with this power well. Platform and power
1481 const struct i915_power_well_ops *ops;
1484 struct i915_power_domains {
1486 * Power wells needed for initialization at driver init and suspend
1487 * time are on. They are kept on until after the first modeset.
1491 int power_well_count;
1494 int domain_use_count[POWER_DOMAIN_NUM];
1495 struct i915_power_well *power_wells;
1498 #define MAX_L3_SLICES 2
1499 struct intel_l3_parity {
1500 u32 *remap_info[MAX_L3_SLICES];
1501 struct work_struct error_work;
1505 struct i915_gem_mm {
1506 /** Memory allocator for GTT stolen memory */
1507 struct drm_mm stolen;
1508 /** Protects the usage of the GTT stolen memory allocator. This is
1509 * always the inner lock when overlapping with struct_mutex. */
1510 struct mutex stolen_lock;
1512 /** List of all objects in gtt_space. Used to restore gtt
1513 * mappings on resume */
1514 struct list_head bound_list;
1516 * List of objects which are not bound to the GTT (thus
1517 * are idle and not used by the GPU). These objects may or may
1518 * not actually have any pages attached.
1520 struct list_head unbound_list;
1522 /** List of all objects in gtt_space, currently mmaped by userspace.
1523 * All objects within this list must also be on bound_list.
1525 struct list_head userfault_list;
1528 * List of objects which are pending destruction.
1530 struct llist_head free_list;
1531 struct work_struct free_work;
1533 /** Usable portion of the GTT for GEM */
1534 unsigned long stolen_base; /* limited to low memory (32-bit) */
1536 /** PPGTT used for aliasing the PPGTT with the GTT */
1537 struct i915_hw_ppgtt *aliasing_ppgtt;
1539 struct notifier_block oom_notifier;
1540 struct notifier_block vmap_notifier;
1541 struct shrinker shrinker;
1543 /** LRU list of objects with fence regs on them. */
1544 struct list_head fence_list;
1547 * Are we in a non-interruptible section of code like
1552 /* the indicator for dispatch video commands on two BSD rings */
1553 atomic_t bsd_engine_dispatch_index;
1555 /** Bit 6 swizzling required for X tiling */
1556 uint32_t bit_6_swizzle_x;
1557 /** Bit 6 swizzling required for Y tiling */
1558 uint32_t bit_6_swizzle_y;
1560 /* accounting, useful for userland debugging */
1561 spinlock_t object_stat_lock;
1566 struct drm_i915_error_state_buf {
1567 struct drm_i915_private *i915;
1576 struct i915_error_state_file_priv {
1577 struct drm_i915_private *i915;
1578 struct drm_i915_error_state *error;
1581 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1582 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1584 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1585 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1587 struct i915_gpu_error {
1588 /* For hangcheck timer */
1589 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1590 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1592 struct delayed_work hangcheck_work;
1594 /* For reset and error_state handling. */
1596 /* Protected by the above dev->gpu_error.lock. */
1597 struct drm_i915_error_state *first_error;
1599 unsigned long missed_irq_rings;
1602 * State variable controlling the reset flow and count
1604 * This is a counter which gets incremented when reset is triggered,
1606 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1607 * meaning that any waiters holding onto the struct_mutex should
1608 * relinquish the lock immediately in order for the reset to start.
1610 * If reset is not completed succesfully, the I915_WEDGE bit is
1611 * set meaning that hardware is terminally sour and there is no
1612 * recovery. All waiters on the reset_queue will be woken when
1615 * This counter is used by the wait_seqno code to notice that reset
1616 * event happened and it needs to restart the entire ioctl (since most
1617 * likely the seqno it waited for won't ever signal anytime soon).
1619 * This is important for lock-free wait paths, where no contended lock
1620 * naturally enforces the correct ordering between the bail-out of the
1621 * waiter and the gpu reset work code.
1623 unsigned long reset_count;
1625 unsigned long flags;
1626 #define I915_RESET_IN_PROGRESS 0
1627 #define I915_WEDGED (BITS_PER_LONG - 1)
1630 * Waitqueue to signal when a hang is detected. Used to for waiters
1631 * to release the struct_mutex for the reset to procede.
1633 wait_queue_head_t wait_queue;
1636 * Waitqueue to signal when the reset has completed. Used by clients
1637 * that wait for dev_priv->mm.wedged to settle.
1639 wait_queue_head_t reset_queue;
1641 /* For missed irq/seqno simulation. */
1642 unsigned long test_irq_rings;
1645 enum modeset_restore {
1646 MODESET_ON_LID_OPEN,
1651 #define DP_AUX_A 0x40
1652 #define DP_AUX_B 0x10
1653 #define DP_AUX_C 0x20
1654 #define DP_AUX_D 0x30
1656 #define DDC_PIN_B 0x05
1657 #define DDC_PIN_C 0x04
1658 #define DDC_PIN_D 0x06
1660 struct ddi_vbt_port_info {
1662 * This is an index in the HDMI/DVI DDI buffer translation table.
1663 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1664 * populate this field.
1666 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1667 uint8_t hdmi_level_shift;
1669 uint8_t supports_dvi:1;
1670 uint8_t supports_hdmi:1;
1671 uint8_t supports_dp:1;
1673 uint8_t alternate_aux_channel;
1674 uint8_t alternate_ddc_pin;
1676 uint8_t dp_boost_level;
1677 uint8_t hdmi_boost_level;
1680 enum psr_lines_to_wait {
1681 PSR_0_LINES_TO_WAIT = 0,
1683 PSR_4_LINES_TO_WAIT,
1687 struct intel_vbt_data {
1688 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1689 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1692 unsigned int int_tv_support:1;
1693 unsigned int lvds_dither:1;
1694 unsigned int lvds_vbt:1;
1695 unsigned int int_crt_support:1;
1696 unsigned int lvds_use_ssc:1;
1697 unsigned int display_clock_mode:1;
1698 unsigned int fdi_rx_polarity_inverted:1;
1699 unsigned int panel_type:4;
1701 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1703 enum drrs_support_type drrs_type;
1714 struct edp_power_seq pps;
1719 bool require_aux_wakeup;
1721 enum psr_lines_to_wait lines_to_wait;
1722 int tp1_wakeup_time;
1723 int tp2_tp3_wakeup_time;
1729 bool active_low_pwm;
1730 u8 min_brightness; /* min_brightness/255 of max */
1731 u8 controller; /* brightness controller number */
1732 enum intel_backlight_type type;
1738 struct mipi_config *config;
1739 struct mipi_pps_data *pps;
1743 const u8 *sequence[MIPI_SEQ_MAX];
1749 union child_device_config *child_dev;
1751 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1752 struct sdvo_device_mapping sdvo_mappings[2];
1755 enum intel_ddb_partitioning {
1757 INTEL_DDB_PART_5_6, /* IVB+ */
1760 struct intel_wm_level {
1768 struct ilk_wm_values {
1769 uint32_t wm_pipe[3];
1771 uint32_t wm_lp_spr[3];
1772 uint32_t wm_linetime[3];
1774 enum intel_ddb_partitioning partitioning;
1777 struct vlv_pipe_wm {
1778 uint16_t plane[I915_MAX_PLANES];
1786 struct vlv_wm_ddl_values {
1787 uint8_t plane[I915_MAX_PLANES];
1790 struct vlv_wm_values {
1791 struct vlv_pipe_wm pipe[3];
1792 struct vlv_sr_wm sr;
1793 struct vlv_wm_ddl_values ddl[3];
1798 struct skl_ddb_entry {
1799 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1802 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1804 return entry->end - entry->start;
1807 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1808 const struct skl_ddb_entry *e2)
1810 if (e1->start == e2->start && e1->end == e2->end)
1816 struct skl_ddb_allocation {
1817 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1818 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1821 struct skl_wm_values {
1822 unsigned dirty_pipes;
1823 struct skl_ddb_allocation ddb;
1826 struct skl_wm_level {
1828 uint16_t plane_res_b;
1829 uint8_t plane_res_l;
1833 * This struct helps tracking the state needed for runtime PM, which puts the
1834 * device in PCI D3 state. Notice that when this happens, nothing on the
1835 * graphics device works, even register access, so we don't get interrupts nor
1838 * Every piece of our code that needs to actually touch the hardware needs to
1839 * either call intel_runtime_pm_get or call intel_display_power_get with the
1840 * appropriate power domain.
1842 * Our driver uses the autosuspend delay feature, which means we'll only really
1843 * suspend if we stay with zero refcount for a certain amount of time. The
1844 * default value is currently very conservative (see intel_runtime_pm_enable), but
1845 * it can be changed with the standard runtime PM files from sysfs.
1847 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1848 * goes back to false exactly before we reenable the IRQs. We use this variable
1849 * to check if someone is trying to enable/disable IRQs while they're supposed
1850 * to be disabled. This shouldn't happen and we'll print some error messages in
1853 * For more, read the Documentation/power/runtime_pm.txt.
1855 struct i915_runtime_pm {
1856 atomic_t wakeref_count;
1861 enum intel_pipe_crc_source {
1862 INTEL_PIPE_CRC_SOURCE_NONE,
1863 INTEL_PIPE_CRC_SOURCE_PLANE1,
1864 INTEL_PIPE_CRC_SOURCE_PLANE2,
1865 INTEL_PIPE_CRC_SOURCE_PF,
1866 INTEL_PIPE_CRC_SOURCE_PIPE,
1867 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1868 INTEL_PIPE_CRC_SOURCE_TV,
1869 INTEL_PIPE_CRC_SOURCE_DP_B,
1870 INTEL_PIPE_CRC_SOURCE_DP_C,
1871 INTEL_PIPE_CRC_SOURCE_DP_D,
1872 INTEL_PIPE_CRC_SOURCE_AUTO,
1873 INTEL_PIPE_CRC_SOURCE_MAX,
1876 struct intel_pipe_crc_entry {
1881 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1882 struct intel_pipe_crc {
1884 bool opened; /* exclusive access to the result file */
1885 struct intel_pipe_crc_entry *entries;
1886 enum intel_pipe_crc_source source;
1888 wait_queue_head_t wq;
1891 struct i915_frontbuffer_tracking {
1895 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1902 struct i915_wa_reg {
1905 /* bitmask representing WA bits */
1910 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1911 * allowing it for RCS as we don't foresee any requirement of having
1912 * a whitelist for other engines. When it is really required for
1913 * other engines then the limit need to be increased.
1915 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1917 struct i915_workarounds {
1918 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1920 u32 hw_whitelist_count[I915_NUM_ENGINES];
1923 struct i915_virtual_gpu {
1927 /* used in computing the new watermarks state */
1928 struct intel_wm_config {
1929 unsigned int num_pipes_active;
1930 bool sprites_enabled;
1931 bool sprites_scaled;
1934 struct i915_oa_format {
1939 struct i915_oa_reg {
1944 struct i915_perf_stream;
1947 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1949 struct i915_perf_stream_ops {
1951 * @enable: Enables the collection of HW samples, either in response to
1952 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1953 * without `I915_PERF_FLAG_DISABLED`.
1955 void (*enable)(struct i915_perf_stream *stream);
1958 * @disable: Disables the collection of HW samples, either in response
1959 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1962 void (*disable)(struct i915_perf_stream *stream);
1965 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1966 * once there is something ready to read() for the stream
1968 void (*poll_wait)(struct i915_perf_stream *stream,
1973 * @wait_unlocked: For handling a blocking read, wait until there is
1974 * something to ready to read() for the stream. E.g. wait on the same
1975 * wait queue that would be passed to poll_wait().
1977 int (*wait_unlocked)(struct i915_perf_stream *stream);
1980 * @read: Copy buffered metrics as records to userspace
1981 * **buf**: the userspace, destination buffer
1982 * **count**: the number of bytes to copy, requested by userspace
1983 * **offset**: zero at the start of the read, updated as the read
1984 * proceeds, it represents how many bytes have been copied so far and
1985 * the buffer offset for copying the next record.
1987 * Copy as many buffered i915 perf samples and records for this stream
1988 * to userspace as will fit in the given buffer.
1990 * Only write complete records; returning -%ENOSPC if there isn't room
1991 * for a complete record.
1993 * Return any error condition that results in a short read such as
1994 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1995 * returning to userspace.
1997 int (*read)(struct i915_perf_stream *stream,
2003 * @destroy: Cleanup any stream specific resources.
2005 * The stream will always be disabled before this is called.
2007 void (*destroy)(struct i915_perf_stream *stream);
2011 * struct i915_perf_stream - state for a single open stream FD
2013 struct i915_perf_stream {
2015 * @dev_priv: i915 drm device
2017 struct drm_i915_private *dev_priv;
2020 * @link: Links the stream into ``&drm_i915_private->streams``
2022 struct list_head link;
2025 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
2026 * properties given when opening a stream, representing the contents
2027 * of a single sample as read() by userspace.
2032 * @sample_size: Considering the configured contents of a sample
2033 * combined with the required header size, this is the total size
2034 * of a single sample record.
2039 * @ctx: %NULL if measuring system-wide across all contexts or a
2040 * specific context that is being monitored.
2042 struct i915_gem_context *ctx;
2045 * @enabled: Whether the stream is currently enabled, considering
2046 * whether the stream was opened in a disabled state and based
2047 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
2052 * @ops: The callbacks providing the implementation of this specific
2053 * type of configured stream.
2055 const struct i915_perf_stream_ops *ops;
2059 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2061 struct i915_oa_ops {
2063 * @init_oa_buffer: Resets the head and tail pointers of the
2064 * circular buffer for periodic OA reports.
2066 * Called when first opening a stream for OA metrics, but also may be
2067 * called in response to an OA buffer overflow or other error
2070 * Note it may be necessary to clear the full OA buffer here as part of
2071 * maintaining the invariable that new reports must be written to
2072 * zeroed memory for us to be able to reliable detect if an expected
2073 * report has not yet landed in memory. (At least on Haswell the OA
2074 * buffer tail pointer is not synchronized with reports being visible
2077 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2080 * @enable_metric_set: Applies any MUX configuration to set up the
2081 * Boolean and Custom (B/C) counters that are part of the counter
2082 * reports being sampled. May apply system constraints such as
2083 * disabling EU clock gating as required.
2085 int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2088 * @disable_metric_set: Remove system constraints associated with using
2091 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2094 * @oa_enable: Enable periodic sampling
2096 void (*oa_enable)(struct drm_i915_private *dev_priv);
2099 * @oa_disable: Disable periodic sampling
2101 void (*oa_disable)(struct drm_i915_private *dev_priv);
2104 * @read: Copy data from the circular OA buffer into a given userspace
2107 int (*read)(struct i915_perf_stream *stream,
2113 * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
2115 * This is either called via fops or the poll check hrtimer (atomic
2116 * ctx) without any locks taken.
2118 * It's safe to read OA config state here unlocked, assuming that this
2119 * is only called while the stream is enabled, while the global OA
2120 * configuration can't be modified.
2122 * Efficiency is more important than avoiding some false positives
2123 * here, which will be handled gracefully - likely resulting in an
2124 * %EAGAIN error for userspace.
2126 bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
2129 struct drm_i915_private {
2130 struct drm_device drm;
2132 struct kmem_cache *objects;
2133 struct kmem_cache *vmas;
2134 struct kmem_cache *requests;
2135 struct kmem_cache *dependencies;
2137 const struct intel_device_info info;
2139 int relative_constants_mode;
2143 struct intel_uncore uncore;
2145 struct i915_virtual_gpu vgpu;
2147 struct intel_gvt *gvt;
2149 struct intel_guc guc;
2151 struct intel_csr csr;
2153 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2155 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2156 * controller on different i2c buses. */
2157 struct mutex gmbus_mutex;
2160 * Base address of the gmbus and gpio block.
2162 uint32_t gpio_mmio_base;
2164 /* MMIO base address for MIPI regs */
2165 uint32_t mipi_mmio_base;
2167 uint32_t psr_mmio_base;
2169 uint32_t pps_mmio_base;
2171 wait_queue_head_t gmbus_wait_queue;
2173 struct pci_dev *bridge_dev;
2174 struct i915_gem_context *kernel_context;
2175 struct intel_engine_cs *engine[I915_NUM_ENGINES];
2176 struct i915_vma *semaphore;
2178 struct drm_dma_handle *status_page_dmah;
2179 struct resource mch_res;
2181 /* protects the irq masks */
2182 spinlock_t irq_lock;
2184 /* protects the mmio flip data */
2185 spinlock_t mmio_flip_lock;
2187 bool display_irqs_enabled;
2189 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2190 struct pm_qos_request pm_qos;
2192 /* Sideband mailbox protection */
2193 struct mutex sb_lock;
2195 /** Cached value of IMR to avoid reads in updating the bitfield */
2198 u32 de_irq_mask[I915_MAX_PIPES];
2205 u32 pipestat_irq_mask[I915_MAX_PIPES];
2207 struct i915_hotplug hotplug;
2208 struct intel_fbc fbc;
2209 struct i915_drrs drrs;
2210 struct intel_opregion opregion;
2211 struct intel_vbt_data vbt;
2213 bool preserve_bios_swizzle;
2216 struct intel_overlay *overlay;
2218 /* backlight registers and fields in struct intel_panel */
2219 struct mutex backlight_lock;
2222 bool no_aux_handshake;
2224 /* protects panel power sequencer state */
2225 struct mutex pps_mutex;
2227 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
2228 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2230 unsigned int fsb_freq, mem_freq, is_ddr3;
2231 unsigned int skl_preferred_vco_freq;
2232 unsigned int cdclk_freq, max_cdclk_freq;
2235 * For reading holding any crtc lock is sufficient,
2236 * for writing must hold all of them.
2238 unsigned int atomic_cdclk_freq;
2240 unsigned int max_dotclk_freq;
2241 unsigned int rawclk_freq;
2242 unsigned int hpll_freq;
2243 unsigned int czclk_freq;
2246 unsigned int vco, ref;
2250 * wq - Driver workqueue for GEM.
2252 * NOTE: Work items scheduled here are not allowed to grab any modeset
2253 * locks, for otherwise the flushing done in the pageflip code will
2254 * result in deadlocks.
2256 struct workqueue_struct *wq;
2258 /* Display functions */
2259 struct drm_i915_display_funcs display;
2261 /* PCH chipset type */
2262 enum intel_pch pch_type;
2263 unsigned short pch_id;
2265 unsigned long quirks;
2267 enum modeset_restore modeset_restore;
2268 struct mutex modeset_restore_lock;
2269 struct drm_atomic_state *modeset_restore_state;
2270 struct drm_modeset_acquire_ctx reset_ctx;
2272 struct list_head vm_list; /* Global list of all address spaces */
2273 struct i915_ggtt ggtt; /* VM representing the global address space */
2275 struct i915_gem_mm mm;
2276 DECLARE_HASHTABLE(mm_structs, 7);
2277 struct mutex mm_lock;
2279 /* The hw wants to have a stable context identifier for the lifetime
2280 * of the context (for OA, PASID, faults, etc). This is limited
2281 * in execlists to 21 bits.
2283 struct ida context_hw_ida;
2284 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2286 /* Kernel Modesetting */
2288 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2289 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2290 wait_queue_head_t pending_flip_queue;
2292 #ifdef CONFIG_DEBUG_FS
2293 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2296 /* dpll and cdclk state is protected by connection_mutex */
2297 int num_shared_dpll;
2298 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2299 const struct intel_dpll_mgr *dpll_mgr;
2302 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2303 * Must be global rather than per dpll, because on some platforms
2304 * plls share registers.
2306 struct mutex dpll_lock;
2308 unsigned int active_crtcs;
2309 unsigned int min_pixclk[I915_MAX_PIPES];
2311 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2313 struct i915_workarounds workarounds;
2315 struct i915_frontbuffer_tracking fb_tracking;
2319 bool mchbar_need_disable;
2321 struct intel_l3_parity l3_parity;
2323 /* Cannot be determined by PCIID. You must always read a register. */
2326 /* gen6+ rps state */
2327 struct intel_gen6_power_mgmt rps;
2329 /* ilk-only ips/rps state. Everything in here is protected by the global
2330 * mchdev_lock in intel_pm.c */
2331 struct intel_ilk_power_mgmt ips;
2333 struct i915_power_domains power_domains;
2335 struct i915_psr psr;
2337 struct i915_gpu_error gpu_error;
2339 struct drm_i915_gem_object *vlv_pctx;
2341 #ifdef CONFIG_DRM_FBDEV_EMULATION
2342 /* list of fbdev register on this device */
2343 struct intel_fbdev *fbdev;
2344 struct work_struct fbdev_suspend_work;
2347 struct drm_property *broadcast_rgb_property;
2348 struct drm_property *force_audio_property;
2350 /* hda/i915 audio component */
2351 struct i915_audio_component *audio_component;
2352 bool audio_component_registered;
2354 * av_mutex - mutex for audio/video sync
2357 struct mutex av_mutex;
2359 uint32_t hw_context_size;
2360 struct list_head context_list;
2364 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2365 u32 chv_phy_control;
2367 * Shadows for CHV DPLL_MD regs to keep the state
2368 * checker somewhat working in the presence hardware
2369 * crappiness (can't read out DPLL_MD for pipes B & C).
2371 u32 chv_dpll_md[I915_MAX_PIPES];
2375 bool suspended_to_idle;
2376 struct i915_suspend_saved_registers regfile;
2377 struct vlv_s0ix_state vlv_s0ix_state;
2380 I915_SAGV_UNKNOWN = 0,
2383 I915_SAGV_NOT_CONTROLLED
2387 /* protects DSPARB registers on pre-g4x/vlv/chv */
2388 spinlock_t dsparb_lock;
2391 * Raw watermark latency values:
2392 * in 0.1us units for WM0,
2393 * in 0.5us units for WM1+.
2396 uint16_t pri_latency[5];
2398 uint16_t spr_latency[5];
2400 uint16_t cur_latency[5];
2402 * Raw watermark memory latency values
2403 * for SKL for all 8 levels
2406 uint16_t skl_latency[8];
2408 /* current hardware state */
2410 struct ilk_wm_values hw;
2411 struct skl_wm_values skl_hw;
2412 struct vlv_wm_values vlv;
2418 * Should be held around atomic WM register writing; also
2419 * protects * intel_crtc->wm.active and
2420 * cstate->wm.need_postvbl_update.
2422 struct mutex wm_mutex;
2425 * Set during HW readout of watermarks/DDB. Some platforms
2426 * need to know when we're still using BIOS-provided values
2427 * (which we don't fully trust).
2429 bool distrust_bios_wm;
2432 struct i915_runtime_pm pm;
2437 struct kobject *metrics_kobj;
2438 struct ctl_table_header *sysctl_header;
2441 struct list_head streams;
2443 spinlock_t hook_lock;
2446 struct i915_perf_stream *exclusive_stream;
2448 u32 specific_ctx_id;
2450 struct hrtimer poll_check_timer;
2451 wait_queue_head_t poll_wq;
2455 int period_exponent;
2456 int timestamp_frequency;
2462 const struct i915_oa_reg *mux_regs;
2464 const struct i915_oa_reg *b_counter_regs;
2465 int b_counter_regs_len;
2468 struct i915_vma *vma;
2474 u32 gen7_latched_oastatus1;
2476 struct i915_oa_ops ops;
2477 const struct i915_oa_format *oa_formats;
2482 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2484 void (*resume)(struct drm_i915_private *);
2485 void (*cleanup_engine)(struct intel_engine_cs *engine);
2487 struct list_head timelines;
2488 struct i915_gem_timeline global_timeline;
2489 u32 active_requests;
2492 * Is the GPU currently considered idle, or busy executing
2493 * userspace requests? Whilst idle, we allow runtime power
2494 * management to power down the hardware and display clocks.
2495 * In order to reduce the effect on performance, there
2496 * is a slight delay before we do so.
2501 * We leave the user IRQ off as much as possible,
2502 * but this means that requests will finish and never
2503 * be retired once the system goes idle. Set a timer to
2504 * fire periodically while the ring is running. When it
2505 * fires, go retire requests.
2507 struct delayed_work retire_work;
2510 * When we detect an idle GPU, we want to turn on
2511 * powersaving features. So once we see that there
2512 * are no more requests outstanding and no more
2513 * arrive within a small period of time, we fire
2514 * off the idle_work.
2516 struct delayed_work idle_work;
2518 ktime_t last_init_time;
2521 /* perform PHY state sanity checks? */
2522 bool chv_phy_assert[2];
2526 /* Used to save the pipe-to-encoder mapping for audio */
2527 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2530 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2531 * will be rejected. Instead look for a better place.
2535 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2537 return container_of(dev, struct drm_i915_private, drm);
2540 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2542 return to_i915(dev_get_drvdata(kdev));
2545 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2547 return container_of(guc, struct drm_i915_private, guc);
2550 /* Simple iterator over all initialised engines */
2551 #define for_each_engine(engine__, dev_priv__, id__) \
2553 (id__) < I915_NUM_ENGINES; \
2555 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2557 #define __mask_next_bit(mask) ({ \
2558 int __idx = ffs(mask) - 1; \
2559 mask &= ~BIT(__idx); \
2563 /* Iterator over subset of engines selected by mask */
2564 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2565 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2566 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2568 enum hdmi_force_audio {
2569 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2570 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2571 HDMI_AUDIO_AUTO, /* trust EDID */
2572 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2575 #define I915_GTT_OFFSET_NONE ((u32)-1)
2578 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2579 * considered to be the frontbuffer for the given plane interface-wise. This
2580 * doesn't mean that the hw necessarily already scans it out, but that any
2581 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2583 * We have one bit per pipe and per scanout plane type.
2585 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2586 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2587 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2588 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2589 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2590 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2591 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2592 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2593 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2594 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2595 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2596 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2599 * Optimised SGL iterator for GEM objects
2601 static __always_inline struct sgt_iter {
2602 struct scatterlist *sgp;
2609 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2610 struct sgt_iter s = { .sgp = sgl };
2613 s.max = s.curr = s.sgp->offset;
2614 s.max += s.sgp->length;
2616 s.dma = sg_dma_address(s.sgp);
2618 s.pfn = page_to_pfn(sg_page(s.sgp));
2624 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2627 if (unlikely(sg_is_chain(sg)))
2628 sg = sg_chain_ptr(sg);
2633 * __sg_next - return the next scatterlist entry in a list
2634 * @sg: The current sg entry
2637 * If the entry is the last, return NULL; otherwise, step to the next
2638 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2639 * otherwise just return the pointer to the current element.
2641 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2643 #ifdef CONFIG_DEBUG_SG
2644 BUG_ON(sg->sg_magic != SG_MAGIC);
2646 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2650 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2651 * @__dmap: DMA address (output)
2652 * @__iter: 'struct sgt_iter' (iterator state, internal)
2653 * @__sgt: sg_table to iterate over (input)
2655 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2656 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2657 ((__dmap) = (__iter).dma + (__iter).curr); \
2658 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2659 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2662 * for_each_sgt_page - iterate over the pages of the given sg_table
2663 * @__pp: page pointer (output)
2664 * @__iter: 'struct sgt_iter' (iterator state, internal)
2665 * @__sgt: sg_table to iterate over (input)
2667 #define for_each_sgt_page(__pp, __iter, __sgt) \
2668 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2669 ((__pp) = (__iter).pfn == 0 ? NULL : \
2670 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2671 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2672 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2674 static inline const struct intel_device_info *
2675 intel_info(const struct drm_i915_private *dev_priv)
2677 return &dev_priv->info;
2680 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2682 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2683 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2685 #define REVID_FOREVER 0xff
2686 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2688 #define GEN_FOREVER (0)
2690 * Returns true if Gen is in inclusive range [Start, End].
2692 * Use GEN_FOREVER for unbound start and or end.
2694 #define IS_GEN(dev_priv, s, e) ({ \
2695 unsigned int __s = (s), __e = (e); \
2696 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2697 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2698 if ((__s) != GEN_FOREVER) \
2700 if ((__e) == GEN_FOREVER) \
2701 __e = BITS_PER_LONG - 1; \
2704 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2708 * Return true if revision is in range [since,until] inclusive.
2710 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2712 #define IS_REVID(p, since, until) \
2713 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2715 #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830)
2716 #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G)
2717 #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
2718 #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G)
2719 #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
2720 #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM)
2721 #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G)
2722 #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
2723 #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G)
2724 #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM)
2725 #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45)
2726 #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45)
2727 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2728 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2729 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2730 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW)
2731 #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2732 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2733 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2734 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2735 INTEL_DEVID(dev_priv) == 0x0152 || \
2736 INTEL_DEVID(dev_priv) == 0x015a)
2737 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2738 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2739 #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
2740 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
2741 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
2742 #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
2743 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
2744 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2745 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2746 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2747 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2748 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2749 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2750 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2751 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2752 /* ULX machines are also considered ULT. */
2753 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2754 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2755 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2756 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2757 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2758 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2759 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2760 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2761 /* ULX machines are also considered ULT. */
2762 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2763 INTEL_DEVID(dev_priv) == 0x0A1E)
2764 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2765 INTEL_DEVID(dev_priv) == 0x1913 || \
2766 INTEL_DEVID(dev_priv) == 0x1916 || \
2767 INTEL_DEVID(dev_priv) == 0x1921 || \
2768 INTEL_DEVID(dev_priv) == 0x1926)
2769 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2770 INTEL_DEVID(dev_priv) == 0x1915 || \
2771 INTEL_DEVID(dev_priv) == 0x191E)
2772 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2773 INTEL_DEVID(dev_priv) == 0x5913 || \
2774 INTEL_DEVID(dev_priv) == 0x5916 || \
2775 INTEL_DEVID(dev_priv) == 0x5921 || \
2776 INTEL_DEVID(dev_priv) == 0x5926)
2777 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2778 INTEL_DEVID(dev_priv) == 0x5915 || \
2779 INTEL_DEVID(dev_priv) == 0x591E)
2780 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2781 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2782 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2783 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2785 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2787 #define SKL_REVID_A0 0x0
2788 #define SKL_REVID_B0 0x1
2789 #define SKL_REVID_C0 0x2
2790 #define SKL_REVID_D0 0x3
2791 #define SKL_REVID_E0 0x4
2792 #define SKL_REVID_F0 0x5
2793 #define SKL_REVID_G0 0x6
2794 #define SKL_REVID_H0 0x7
2796 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2798 #define BXT_REVID_A0 0x0
2799 #define BXT_REVID_A1 0x1
2800 #define BXT_REVID_B0 0x3
2801 #define BXT_REVID_B_LAST 0x8
2802 #define BXT_REVID_C0 0x9
2804 #define IS_BXT_REVID(dev_priv, since, until) \
2805 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2807 #define KBL_REVID_A0 0x0
2808 #define KBL_REVID_B0 0x1
2809 #define KBL_REVID_C0 0x2
2810 #define KBL_REVID_D0 0x3
2811 #define KBL_REVID_E0 0x4
2813 #define IS_KBL_REVID(dev_priv, since, until) \
2814 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2817 * The genX designation typically refers to the render engine, so render
2818 * capability related checks should use IS_GEN, while display and other checks
2819 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2822 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2823 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2824 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2825 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2826 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2827 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2828 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2829 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2831 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && INTEL_INFO(dev_priv)->is_lp)
2833 #define ENGINE_MASK(id) BIT(id)
2834 #define RENDER_RING ENGINE_MASK(RCS)
2835 #define BSD_RING ENGINE_MASK(VCS)
2836 #define BLT_RING ENGINE_MASK(BCS)
2837 #define VEBOX_RING ENGINE_MASK(VECS)
2838 #define BSD2_RING ENGINE_MASK(VCS2)
2839 #define ALL_ENGINES (~0)
2841 #define HAS_ENGINE(dev_priv, id) \
2842 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2844 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2845 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2846 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2847 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2849 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2850 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2851 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2852 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2853 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2855 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2857 #define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts)
2858 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2859 ((dev_priv)->info.has_logical_ring_contexts)
2860 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2861 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2862 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2864 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2865 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2866 ((dev_priv)->info.overlay_needs_physical)
2868 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2869 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2871 /* WaRsDisableCoarsePowerGating:skl,bxt */
2872 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2873 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2874 IS_SKL_GT3(dev_priv) || \
2875 IS_SKL_GT4(dev_priv))
2878 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2879 * even when in MSI mode. This results in spurious interrupt warnings if the
2880 * legacy irq no. is shared with another device. The kernel then disables that
2881 * interrupt source and so prevents the other device from working properly.
2883 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2884 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2886 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2887 * rows, which changed the alignment requirements and fence programming.
2889 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2890 !(IS_I915G(dev_priv) || \
2891 IS_I915GM(dev_priv)))
2892 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2893 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2895 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2896 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2897 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2899 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2901 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2903 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2904 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2905 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2906 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2907 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2909 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2911 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2912 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2915 * For now, anything with a GuC requires uCode loading, and then supports
2916 * command submission once loaded. But these are logically independent
2917 * properties, so we have separate macros to test them.
2919 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2920 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2921 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2923 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2925 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2927 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2928 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2929 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2930 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2931 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2932 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2933 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2934 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2935 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2936 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2937 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2938 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2940 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2941 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2942 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2943 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2944 #define HAS_PCH_LPT_LP(dev_priv) \
2945 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2946 #define HAS_PCH_LPT_H(dev_priv) \
2947 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2948 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2949 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2950 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2951 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2953 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2955 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2957 /* DPF == dynamic parity feature */
2958 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2959 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2960 2 : HAS_L3_DPF(dev_priv))
2962 #define GT_FREQUENCY_MULTIPLIER 50
2963 #define GEN9_FREQ_SCALER 3
2965 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2967 #include "i915_trace.h"
2969 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2971 #ifdef CONFIG_INTEL_IOMMU
2972 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2978 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2981 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2985 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2986 const char *fmt, ...);
2988 #define i915_report_error(dev_priv, fmt, ...) \
2989 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2991 #ifdef CONFIG_COMPAT
2992 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2995 #define i915_compat_ioctl NULL
2997 extern const struct dev_pm_ops i915_pm_ops;
2999 extern int i915_driver_load(struct pci_dev *pdev,
3000 const struct pci_device_id *ent);
3001 extern void i915_driver_unload(struct drm_device *dev);
3002 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
3003 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
3004 extern void i915_reset(struct drm_i915_private *dev_priv);
3005 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
3006 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
3007 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
3008 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
3009 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
3010 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
3011 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
3012 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3014 /* intel_hotplug.c */
3015 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
3016 u32 pin_mask, u32 long_mask);
3017 void intel_hpd_init(struct drm_i915_private *dev_priv);
3018 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
3019 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3020 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3021 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3022 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3025 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3027 unsigned long delay;
3029 if (unlikely(!i915.enable_hangcheck))
3032 /* Don't continually defer the hangcheck so that it is always run at
3033 * least once after work has been scheduled on any ring. Otherwise,
3034 * we will ignore a hung ring if a second ring is kept busy.
3037 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
3038 queue_delayed_work(system_long_wq,
3039 &dev_priv->gpu_error.hangcheck_work, delay);
3043 void i915_handle_error(struct drm_i915_private *dev_priv,
3045 const char *fmt, ...);
3047 extern void intel_irq_init(struct drm_i915_private *dev_priv);
3048 int intel_irq_install(struct drm_i915_private *dev_priv);
3049 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3051 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
3052 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
3053 bool restore_forcewake);
3054 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
3055 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
3056 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
3057 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
3058 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
3060 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
3061 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
3062 enum forcewake_domains domains);
3063 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
3064 enum forcewake_domains domains);
3065 /* Like above but the caller must manage the uncore.lock itself.
3066 * Must be used with I915_READ_FW and friends.
3068 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
3069 enum forcewake_domains domains);
3070 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
3071 enum forcewake_domains domains);
3072 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
3074 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
3076 int intel_wait_for_register(struct drm_i915_private *dev_priv,
3080 const unsigned long timeout_ms);
3081 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
3085 const unsigned long timeout_ms);
3087 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3089 return dev_priv->gvt;
3092 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3094 return dev_priv->vgpu.active;
3098 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3102 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3105 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3106 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3107 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3110 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3111 uint32_t interrupt_mask,
3112 uint32_t enabled_irq_mask);
3114 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3116 ilk_update_display_irq(dev_priv, bits, bits);
3119 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3121 ilk_update_display_irq(dev_priv, bits, 0);
3123 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3125 uint32_t interrupt_mask,
3126 uint32_t enabled_irq_mask);
3127 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3128 enum pipe pipe, uint32_t bits)
3130 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3132 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3133 enum pipe pipe, uint32_t bits)
3135 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3137 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3138 uint32_t interrupt_mask,
3139 uint32_t enabled_irq_mask);
3141 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3143 ibx_display_interrupt_update(dev_priv, bits, bits);
3146 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3148 ibx_display_interrupt_update(dev_priv, bits, 0);
3152 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3153 struct drm_file *file_priv);
3154 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3155 struct drm_file *file_priv);
3156 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3157 struct drm_file *file_priv);
3158 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3159 struct drm_file *file_priv);
3160 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3161 struct drm_file *file_priv);
3162 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3163 struct drm_file *file_priv);
3164 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3165 struct drm_file *file_priv);
3166 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3167 struct drm_file *file_priv);
3168 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3169 struct drm_file *file_priv);
3170 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3171 struct drm_file *file_priv);
3172 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3173 struct drm_file *file);
3174 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3175 struct drm_file *file);
3176 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3177 struct drm_file *file_priv);
3178 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3179 struct drm_file *file_priv);
3180 int i915_gem_set_tiling(struct drm_device *dev, void *data,
3181 struct drm_file *file_priv);
3182 int i915_gem_get_tiling(struct drm_device *dev, void *data,
3183 struct drm_file *file_priv);
3184 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3185 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3186 struct drm_file *file);
3187 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3188 struct drm_file *file_priv);
3189 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3190 struct drm_file *file_priv);
3191 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3192 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3193 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3194 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3195 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3197 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3198 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3199 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3200 const struct drm_i915_gem_object_ops *ops);
3201 struct drm_i915_gem_object *
3202 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3203 struct drm_i915_gem_object *
3204 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3205 const void *data, size_t size);
3206 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3207 void i915_gem_free_object(struct drm_gem_object *obj);
3209 struct i915_vma * __must_check
3210 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3211 const struct i915_ggtt_view *view,
3216 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3217 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3219 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3221 static inline int __sg_page_count(const struct scatterlist *sg)
3223 return sg->length >> PAGE_SHIFT;
3226 struct scatterlist *
3227 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3228 unsigned int n, unsigned int *offset);
3231 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3235 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3239 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3242 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3243 struct sg_table *pages);
3244 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3246 static inline int __must_check
3247 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3249 might_lock(&obj->mm.lock);
3251 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3254 return __i915_gem_object_get_pages(obj);
3258 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3260 GEM_BUG_ON(!obj->mm.pages);
3262 atomic_inc(&obj->mm.pages_pin_count);
3266 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3268 return atomic_read(&obj->mm.pages_pin_count);
3272 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3274 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3275 GEM_BUG_ON(!obj->mm.pages);
3277 atomic_dec(&obj->mm.pages_pin_count);
3278 GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count) < obj->bind_count);
3282 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3284 __i915_gem_object_unpin_pages(obj);
3287 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3292 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3293 enum i915_mm_subclass subclass);
3294 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3296 enum i915_map_type {
3302 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3303 * @obj - the object to map into kernel address space
3304 * @type - the type of mapping, used to select pgprot_t
3306 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3307 * pages and then returns a contiguous mapping of the backing storage into
3308 * the kernel address space. Based on the @type of mapping, the PTE will be
3309 * set to either WriteBack or WriteCombine (via pgprot_t).
3311 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3312 * mapping is no longer required.
3314 * Returns the pointer through which to access the mapped object, or an
3315 * ERR_PTR() on error.
3317 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3318 enum i915_map_type type);
3321 * i915_gem_object_unpin_map - releases an earlier mapping
3322 * @obj - the object to unmap
3324 * After pinning the object and mapping its pages, once you are finished
3325 * with your access, call i915_gem_object_unpin_map() to release the pin
3326 * upon the mapping. Once the pin count reaches zero, that mapping may be
3329 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3331 i915_gem_object_unpin_pages(obj);
3334 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3335 unsigned int *needs_clflush);
3336 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3337 unsigned int *needs_clflush);
3338 #define CLFLUSH_BEFORE 0x1
3339 #define CLFLUSH_AFTER 0x2
3340 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3343 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3345 i915_gem_object_unpin_pages(obj);
3348 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3349 void i915_vma_move_to_active(struct i915_vma *vma,
3350 struct drm_i915_gem_request *req,
3351 unsigned int flags);
3352 int i915_gem_dumb_create(struct drm_file *file_priv,
3353 struct drm_device *dev,
3354 struct drm_mode_create_dumb *args);
3355 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3356 uint32_t handle, uint64_t *offset);
3357 int i915_gem_mmap_gtt_version(void);
3359 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3360 struct drm_i915_gem_object *new,
3361 unsigned frontbuffer_bits);
3363 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3365 struct drm_i915_gem_request *
3366 i915_gem_find_active_request(struct intel_engine_cs *engine);
3368 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3370 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3372 return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3375 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3377 return unlikely(test_bit(I915_WEDGED, &error->flags));
3380 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3382 return i915_reset_in_progress(error) | i915_terminally_wedged(error);
3385 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3387 return READ_ONCE(error->reset_count);
3390 void i915_gem_reset(struct drm_i915_private *dev_priv);
3391 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3392 void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3393 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3394 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3395 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3396 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3397 int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3398 unsigned int flags);
3399 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3400 void i915_gem_resume(struct drm_i915_private *dev_priv);
3401 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3402 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3405 struct intel_rps_client *rps);
3406 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3409 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3412 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3415 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3416 struct i915_vma * __must_check
3417 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3419 const struct i915_ggtt_view *view);
3420 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3421 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3423 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3424 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3426 u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
3428 u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
3429 int tiling_mode, bool fenced);
3431 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3432 enum i915_cache_level cache_level);
3434 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3435 struct dma_buf *dma_buf);
3437 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3438 struct drm_gem_object *gem_obj, int flags);
3441 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3442 struct i915_address_space *vm,
3443 const struct i915_ggtt_view *view);
3446 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3447 struct i915_address_space *vm,
3448 const struct i915_ggtt_view *view);
3450 static inline struct i915_hw_ppgtt *
3451 i915_vm_to_ppgtt(struct i915_address_space *vm)
3453 return container_of(vm, struct i915_hw_ppgtt, base);
3456 static inline struct i915_vma *
3457 i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj,
3458 const struct i915_ggtt_view *view)
3460 return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view);
3463 static inline unsigned long
3464 i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o,
3465 const struct i915_ggtt_view *view)
3467 return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view));
3470 /* i915_gem_fence_reg.c */
3471 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3472 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3474 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3476 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3477 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3478 struct sg_table *pages);
3479 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3480 struct sg_table *pages);
3482 /* i915_gem_context.c */
3483 int __must_check i915_gem_context_init(struct drm_i915_private *dev_priv);
3484 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3485 void i915_gem_context_fini(struct drm_i915_private *dev_priv);
3486 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3487 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3488 int i915_switch_context(struct drm_i915_gem_request *req);
3489 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3490 void i915_gem_context_free(struct kref *ctx_ref);
3491 struct i915_gem_context *
3492 i915_gem_context_create_gvt(struct drm_device *dev);
3494 static inline struct i915_gem_context *
3495 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3497 struct i915_gem_context *ctx;
3499 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3501 ctx = idr_find(&file_priv->context_idr, id);
3503 return ERR_PTR(-ENOENT);
3508 static inline struct i915_gem_context *
3509 i915_gem_context_get(struct i915_gem_context *ctx)
3511 kref_get(&ctx->ref);
3515 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3517 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3518 kref_put(&ctx->ref, i915_gem_context_free);
3521 static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
3523 kref_put_mutex(&ctx->ref,
3524 i915_gem_context_free,
3525 &ctx->i915->drm.struct_mutex);
3528 static inline struct intel_timeline *
3529 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3530 struct intel_engine_cs *engine)
3532 struct i915_address_space *vm;
3534 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3535 return &vm->timeline.engine[engine->id];
3538 static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3540 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3543 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3544 struct drm_file *file);
3545 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3546 struct drm_file *file);
3547 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3548 struct drm_file *file_priv);
3549 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3550 struct drm_file *file_priv);
3551 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
3552 struct drm_file *file);
3554 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3555 struct drm_file *file);
3557 /* i915_gem_evict.c */
3558 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3559 u64 min_size, u64 alignment,
3560 unsigned cache_level,
3563 int __must_check i915_gem_evict_for_vma(struct i915_vma *vma,
3564 unsigned int flags);
3565 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3567 /* belongs in i915_gem_gtt.h */
3568 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3571 if (INTEL_GEN(dev_priv) < 6)
3572 intel_gtt_chipset_flush();
3575 /* i915_gem_stolen.c */
3576 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3577 struct drm_mm_node *node, u64 size,
3578 unsigned alignment);
3579 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3580 struct drm_mm_node *node, u64 size,
3581 unsigned alignment, u64 start,
3583 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3584 struct drm_mm_node *node);
3585 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3586 void i915_gem_cleanup_stolen(struct drm_device *dev);
3587 struct drm_i915_gem_object *
3588 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3589 struct drm_i915_gem_object *
3590 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3595 /* i915_gem_internal.c */
3596 struct drm_i915_gem_object *
3597 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3600 /* i915_gem_shrinker.c */
3601 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3602 unsigned long target,
3604 #define I915_SHRINK_PURGEABLE 0x1
3605 #define I915_SHRINK_UNBOUND 0x2
3606 #define I915_SHRINK_BOUND 0x4
3607 #define I915_SHRINK_ACTIVE 0x8
3608 #define I915_SHRINK_VMAPS 0x10
3609 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3610 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3611 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3614 /* i915_gem_tiling.c */
3615 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3617 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3619 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3620 i915_gem_object_is_tiled(obj);
3623 /* i915_debugfs.c */
3624 #ifdef CONFIG_DEBUG_FS
3625 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3626 void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3627 int i915_debugfs_connector_add(struct drm_connector *connector);
3628 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3630 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3631 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3632 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3634 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3637 /* i915_gpu_error.c */
3638 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3641 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3642 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3643 const struct i915_error_state_file_priv *error);
3644 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3645 struct drm_i915_private *i915,
3646 size_t count, loff_t pos);
3647 static inline void i915_error_state_buf_release(
3648 struct drm_i915_error_state_buf *eb)
3652 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3654 const char *error_msg);
3655 void i915_error_state_get(struct drm_device *dev,
3656 struct i915_error_state_file_priv *error_priv);
3657 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3658 void i915_destroy_error_state(struct drm_i915_private *dev_priv);
3662 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3664 const char *error_msg)
3668 static inline void i915_destroy_error_state(struct drm_i915_private *dev_priv)
3674 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3676 /* i915_cmd_parser.c */
3677 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3678 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3679 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3680 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3681 struct drm_i915_gem_object *batch_obj,
3682 struct drm_i915_gem_object *shadow_batch_obj,
3683 u32 batch_start_offset,
3688 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3689 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3690 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3691 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3693 /* i915_suspend.c */
3694 extern int i915_save_state(struct drm_i915_private *dev_priv);
3695 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3698 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3699 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3702 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3703 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3704 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3707 extern struct i2c_adapter *
3708 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3709 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3710 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3711 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3713 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3715 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3718 int intel_bios_init(struct drm_i915_private *dev_priv);
3719 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3720 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3721 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3722 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3723 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3724 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3725 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3726 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3728 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3732 /* intel_opregion.c */
3734 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3735 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3736 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3737 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3738 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3740 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3742 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3744 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3745 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3746 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3747 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3751 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3756 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3760 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3768 extern void intel_register_dsm_handler(void);
3769 extern void intel_unregister_dsm_handler(void);
3771 static inline void intel_register_dsm_handler(void) { return; }
3772 static inline void intel_unregister_dsm_handler(void) { return; }
3773 #endif /* CONFIG_ACPI */
3775 /* intel_device_info.c */
3776 static inline struct intel_device_info *
3777 mkwrite_device_info(struct drm_i915_private *dev_priv)
3779 return (struct intel_device_info *)&dev_priv->info;
3782 const char *intel_platform_name(enum intel_platform platform);
3783 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3784 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3787 extern void intel_modeset_init_hw(struct drm_device *dev);
3788 extern int intel_modeset_init(struct drm_device *dev);
3789 extern void intel_modeset_gem_init(struct drm_device *dev);
3790 extern void intel_modeset_cleanup(struct drm_device *dev);
3791 extern int intel_connector_register(struct drm_connector *);
3792 extern void intel_connector_unregister(struct drm_connector *);
3793 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3795 extern void intel_display_resume(struct drm_device *dev);
3796 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3797 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3798 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3799 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3800 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3801 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3804 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3805 struct drm_file *file);
3808 extern struct intel_overlay_error_state *
3809 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3810 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3811 struct intel_overlay_error_state *error);
3813 extern struct intel_display_error_state *
3814 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3815 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3816 struct drm_i915_private *dev_priv,
3817 struct intel_display_error_state *error);
3819 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3820 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3821 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3822 u32 reply_mask, u32 reply, int timeout_base_ms);
3824 /* intel_sideband.c */
3825 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3826 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3827 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3828 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3829 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3830 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3831 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3832 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3833 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3834 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3835 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3836 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3837 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3838 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3839 enum intel_sbi_destination destination);
3840 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3841 enum intel_sbi_destination destination);
3842 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3843 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3845 /* intel_dpio_phy.c */
3846 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3847 enum dpio_phy *phy, enum dpio_channel *ch);
3848 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3849 enum port port, u32 margin, u32 scale,
3850 u32 enable, u32 deemphasis);
3851 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3852 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3853 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3855 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3857 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3858 uint8_t lane_count);
3859 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3860 uint8_t lane_lat_optim_mask);
3861 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3863 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3864 u32 deemph_reg_value, u32 margin_reg_value,
3865 bool uniq_trans_scale);
3866 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3868 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3869 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3870 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3871 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3873 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3874 u32 demph_reg_value, u32 preemph_reg_value,
3875 u32 uniqtranscale_reg_value, u32 tx3_demph);
3876 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3877 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3878 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3880 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3881 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3883 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3884 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3886 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3887 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3888 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3889 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3891 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3892 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3893 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3894 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3896 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3897 * will be implemented using 2 32-bit writes in an arbitrary order with
3898 * an arbitrary delay between them. This can cause the hardware to
3899 * act upon the intermediate value, possibly leading to corruption and
3900 * machine death. For this reason we do not support I915_WRITE64, or
3901 * dev_priv->uncore.funcs.mmio_writeq.
3903 * When reading a 64-bit value as two 32-bit values, the delay may cause
3904 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3905 * occasionally a 64-bit register does not actualy support a full readq
3906 * and must be read using two 32-bit reads.
3908 * You have been warned.
3910 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3912 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3913 u32 upper, lower, old_upper, loop = 0; \
3914 upper = I915_READ(upper_reg); \
3916 old_upper = upper; \
3917 lower = I915_READ(lower_reg); \
3918 upper = I915_READ(upper_reg); \
3919 } while (upper != old_upper && loop++ < 2); \
3920 (u64)upper << 32 | lower; })
3922 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3923 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3925 #define __raw_read(x, s) \
3926 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3929 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3932 #define __raw_write(x, s) \
3933 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3934 i915_reg_t reg, uint##x##_t val) \
3936 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3951 /* These are untraced mmio-accessors that are only valid to be used inside
3952 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3955 * Think twice, and think again, before using these.
3957 * As an example, these accessors can possibly be used between:
3959 * spin_lock_irq(&dev_priv->uncore.lock);
3960 * intel_uncore_forcewake_get__locked();
3964 * intel_uncore_forcewake_put__locked();
3965 * spin_unlock_irq(&dev_priv->uncore.lock);
3968 * Note: some registers may not need forcewake held, so
3969 * intel_uncore_forcewake_{get,put} can be omitted, see
3970 * intel_uncore_forcewake_for_reg().
3972 * Certain architectures will die if the same cacheline is concurrently accessed
3973 * by different clients (e.g. on Ivybridge). Access to registers should
3974 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3975 * a more localised lock guarding all access to that bank of registers.
3977 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3978 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3979 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3980 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3982 /* "Broadcast RGB" property */
3983 #define INTEL_BROADCAST_RGB_AUTO 0
3984 #define INTEL_BROADCAST_RGB_FULL 1
3985 #define INTEL_BROADCAST_RGB_LIMITED 2
3987 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3989 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3990 return VLV_VGACNTRL;
3991 else if (INTEL_GEN(dev_priv) >= 5)
3992 return CPU_VGACNTRL;
3997 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3999 unsigned long j = msecs_to_jiffies(m);
4001 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4004 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
4006 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
4009 static inline unsigned long
4010 timespec_to_jiffies_timeout(const struct timespec *value)
4012 unsigned long j = timespec_to_jiffies(value);
4014 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4018 * If you need to wait X milliseconds between events A and B, but event B
4019 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4020 * when event A happened, then just before event B you call this function and
4021 * pass the timestamp as the first argument, and X as the second argument.
4024 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4026 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4029 * Don't re-read the value of "jiffies" every time since it may change
4030 * behind our back and break the math.
4032 tmp_jiffies = jiffies;
4033 target_jiffies = timestamp_jiffies +
4034 msecs_to_jiffies_timeout(to_wait_ms);
4036 if (time_after(target_jiffies, tmp_jiffies)) {
4037 remaining_jiffies = target_jiffies - tmp_jiffies;
4038 while (remaining_jiffies)
4040 schedule_timeout_uninterruptible(remaining_jiffies);
4045 __i915_request_irq_complete(struct drm_i915_gem_request *req)
4047 struct intel_engine_cs *engine = req->engine;
4049 /* Before we do the heavier coherent read of the seqno,
4050 * check the value (hopefully) in the CPU cacheline.
4052 if (__i915_gem_request_completed(req))
4055 /* Ensure our read of the seqno is coherent so that we
4056 * do not "miss an interrupt" (i.e. if this is the last
4057 * request and the seqno write from the GPU is not visible
4058 * by the time the interrupt fires, we will see that the
4059 * request is incomplete and go back to sleep awaiting
4060 * another interrupt that will never come.)
4062 * Strictly, we only need to do this once after an interrupt,
4063 * but it is easier and safer to do it every time the waiter
4066 if (engine->irq_seqno_barrier &&
4067 rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
4068 cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
4069 struct task_struct *tsk;
4071 /* The ordering of irq_posted versus applying the barrier
4072 * is crucial. The clearing of the current irq_posted must
4073 * be visible before we perform the barrier operation,
4074 * such that if a subsequent interrupt arrives, irq_posted
4075 * is reasserted and our task rewoken (which causes us to
4076 * do another __i915_request_irq_complete() immediately
4077 * and reapply the barrier). Conversely, if the clear
4078 * occurs after the barrier, then an interrupt that arrived
4079 * whilst we waited on the barrier would not trigger a
4080 * barrier on the next pass, and the read may not see the
4083 engine->irq_seqno_barrier(engine);
4085 /* If we consume the irq, but we are no longer the bottom-half,
4086 * the real bottom-half may not have serialised their own
4087 * seqno check with the irq-barrier (i.e. may have inspected
4088 * the seqno before we believe it coherent since they see
4089 * irq_posted == false but we are still running).
4092 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
4093 if (tsk && tsk != current)
4094 /* Note that if the bottom-half is changed as we
4095 * are sending the wake-up, the new bottom-half will
4096 * be woken by whomever made the change. We only have
4097 * to worry about when we steal the irq-posted for
4100 wake_up_process(tsk);
4103 if (__i915_gem_request_completed(req))
4110 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4111 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4114 int remap_io_mapping(struct vm_area_struct *vma,
4115 unsigned long addr, unsigned long pfn, unsigned long size,
4116 struct io_mapping *iomap);
4118 #define ptr_mask_bits(ptr) ({ \
4119 unsigned long __v = (unsigned long)(ptr); \
4120 (typeof(ptr))(__v & PAGE_MASK); \
4123 #define ptr_unpack_bits(ptr, bits) ({ \
4124 unsigned long __v = (unsigned long)(ptr); \
4125 (bits) = __v & ~PAGE_MASK; \
4126 (typeof(ptr))(__v & PAGE_MASK); \
4129 #define ptr_pack_bits(ptr, bits) \
4130 ((typeof(ptr))((unsigned long)(ptr) | (bits)))
4132 #define fetch_and_zero(ptr) ({ \
4133 typeof(*ptr) __T = *(ptr); \
4134 *(ptr) = (typeof(*ptr))0; \