1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
37 /* General customization:
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
56 #define I915_NUM_PIPE 2
61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
63 * 1.4: Fix cmdbuffer path, add heap destroy
64 * 1.5: Add vblank pipe configuration
65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
68 #define DRIVER_MAJOR 1
69 #define DRIVER_MINOR 6
70 #define DRIVER_PATCHLEVEL 0
72 #define WATCH_COHERENCY 0
77 #define WATCH_INACTIVE 0
78 #define WATCH_PWRITE 0
80 #define I915_GEM_PHYS_CURSOR_0 1
81 #define I915_GEM_PHYS_CURSOR_1 2
82 #define I915_GEM_PHYS_OVERLAY_REGS 3
83 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
85 struct drm_i915_gem_phys_object {
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
92 typedef struct _drm_i915_ring_buffer {
99 struct drm_gem_object *ring_obj;
100 } drm_i915_ring_buffer_t;
103 struct mem_block *next;
104 struct mem_block *prev;
107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
110 struct opregion_header;
111 struct opregion_acpi;
112 struct opregion_swsci;
113 struct opregion_asle;
115 struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
123 struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
127 #define I915_FENCE_REG_NONE -1
129 struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
133 struct sdvo_device_mapping {
140 struct drm_i915_error_state {
155 struct drm_i915_error_object {
159 } *ringbuffer, *batchbuffer[2];
160 struct drm_i915_error_buffer {
176 struct drm_i915_display_funcs {
177 void (*dpms)(struct drm_crtc *crtc, int mode);
178 bool (*fbc_enabled)(struct drm_crtc *crtc);
179 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
180 void (*disable_fbc)(struct drm_device *dev);
181 int (*get_display_clock_speed)(struct drm_device *dev);
182 int (*get_fifo_size)(struct drm_device *dev, int plane);
183 void (*update_wm)(struct drm_device *dev, int planea_clock,
184 int planeb_clock, int sr_hdisplay, int pixel_size);
185 /* clock updates for mode set */
187 /* render clock increase/decrease */
188 /* display clock increase/decrease */
189 /* pll clock increase/decrease */
190 /* clock gating init */
193 struct intel_overlay;
195 struct intel_device_info {
211 u8 has_pipe_cxsr : 1;
213 u8 cursor_needs_physical : 1;
217 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
218 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
219 FBC_MODE_TOO_LARGE, /* mode too large for compression */
220 FBC_BAD_PLANE, /* fbc not supported on plane */
221 FBC_NOT_TILED, /* buffer not tiled */
225 PCH_IBX, /* Ibexpeak PCH */
226 PCH_CPT, /* Cougarpoint PCH */
231 typedef struct drm_i915_private {
232 struct drm_device *dev;
234 const struct intel_device_info *info;
240 struct pci_dev *bridge_dev;
241 drm_i915_ring_buffer_t ring;
243 drm_dma_handle_t *status_page_dmah;
244 void *hw_status_page;
245 dma_addr_t dma_status_page;
247 unsigned int status_gfx_addr;
248 drm_local_map_t hws_map;
249 struct drm_gem_object *hws_obj;
250 struct drm_gem_object *pwrctx;
252 struct resource mch_res;
260 wait_queue_head_t irq_queue;
261 atomic_t irq_received;
262 /** Protects user_irq_refcount and irq_mask_reg */
263 spinlock_t user_irq_lock;
264 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
265 int user_irq_refcount;
267 /** Cached value of IMR to avoid reads in updating the bitfield */
270 /** splitted irq regs for graphics and display engine on Ironlake,
271 irq_mask_reg is still used for display irq. */
273 u32 gt_irq_enable_reg;
274 u32 de_irq_enable_reg;
275 u32 pch_irq_mask_reg;
276 u32 pch_irq_enable_reg;
278 u32 hotplug_supported_mask;
279 struct work_struct hotplug_work;
281 int tex_lru_log_granularity;
282 int allow_batchbuffer;
283 struct mem_block *agp_heap;
284 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
287 /* For hangcheck timer */
288 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
289 struct timer_list hangcheck_timer;
295 unsigned long cfb_size;
296 unsigned long cfb_pitch;
302 struct intel_opregion opregion;
305 struct intel_overlay *overlay;
308 int backlight_duty_cycle; /* restore backlight to this value */
309 bool panel_wants_dither;
310 struct drm_display_mode *panel_fixed_mode;
311 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
312 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
314 /* Feature bits from the VBIOS */
315 unsigned int int_tv_support:1;
316 unsigned int lvds_dither:1;
317 unsigned int lvds_vbt:1;
318 unsigned int int_crt_support:1;
319 unsigned int lvds_use_ssc:1;
320 unsigned int edp_support:1;
324 struct notifier_block lid_notifier;
326 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */
327 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
328 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
329 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
331 unsigned int fsb_freq, mem_freq;
333 spinlock_t error_lock;
334 struct drm_i915_error_state *first_error;
335 struct work_struct error_work;
336 struct workqueue_struct *wq;
338 /* Display functions */
339 struct drm_i915_display_funcs display;
341 /* PCH chipset type */
342 enum intel_pch pch_type;
367 u32 saveTRANS_HTOTAL_A;
368 u32 saveTRANS_HBLANK_A;
369 u32 saveTRANS_HSYNC_A;
370 u32 saveTRANS_VTOTAL_A;
371 u32 saveTRANS_VBLANK_A;
372 u32 saveTRANS_VSYNC_A;
380 u32 savePFIT_PGM_RATIOS;
381 u32 saveBLC_HIST_CTL;
383 u32 saveBLC_PWM_CTL2;
384 u32 saveBLC_CPU_PWM_CTL;
385 u32 saveBLC_CPU_PWM_CTL2;
398 u32 saveTRANS_HTOTAL_B;
399 u32 saveTRANS_HBLANK_B;
400 u32 saveTRANS_HSYNC_B;
401 u32 saveTRANS_VTOTAL_B;
402 u32 saveTRANS_VBLANK_B;
403 u32 saveTRANS_VSYNC_B;
417 u32 savePP_ON_DELAYS;
418 u32 savePP_OFF_DELAYS;
426 u32 savePFIT_CONTROL;
427 u32 save_palette_a[256];
428 u32 save_palette_b[256];
429 u32 saveDPFC_CB_BASE;
430 u32 saveFBC_CFB_BASE;
433 u32 saveFBC_CONTROL2;
443 u32 saveCACHE_MODE_0;
444 u32 saveMI_ARB_STATE;
455 uint64_t saveFENCE[16];
466 u32 savePIPEA_GMCH_DATA_M;
467 u32 savePIPEB_GMCH_DATA_M;
468 u32 savePIPEA_GMCH_DATA_N;
469 u32 savePIPEB_GMCH_DATA_N;
470 u32 savePIPEA_DP_LINK_M;
471 u32 savePIPEB_DP_LINK_M;
472 u32 savePIPEA_DP_LINK_N;
473 u32 savePIPEB_DP_LINK_N;
484 u32 savePCH_DREF_CONTROL;
485 u32 saveDISP_ARB_CTL;
486 u32 savePIPEA_DATA_M1;
487 u32 savePIPEA_DATA_N1;
488 u32 savePIPEA_LINK_M1;
489 u32 savePIPEA_LINK_N1;
490 u32 savePIPEB_DATA_M1;
491 u32 savePIPEB_DATA_N1;
492 u32 savePIPEB_LINK_M1;
493 u32 savePIPEB_LINK_N1;
494 u32 saveMCHBAR_RENDER_STANDBY;
497 struct drm_mm gtt_space;
499 struct io_mapping *gtt_mapping;
503 * Membership on list of all loaded devices, used to evict
504 * inactive buffers under memory pressure.
506 * Modifications should only be done whilst holding the
507 * shrink_list_lock spinlock.
509 struct list_head shrink_list;
512 * List of objects currently involved in rendering from the
515 * Includes buffers having the contents of their GPU caches
516 * flushed, not necessarily primitives. last_rendering_seqno
517 * represents when the rendering involved will be completed.
519 * A reference is held on the buffer while on this list.
521 spinlock_t active_list_lock;
522 struct list_head active_list;
525 * List of objects which are not in the ringbuffer but which
526 * still have a write_domain which needs to be flushed before
529 * last_rendering_seqno is 0 while an object is in this list.
531 * A reference is held on the buffer while on this list.
533 struct list_head flushing_list;
536 * List of objects currently pending a GPU write flush.
538 * All elements on this list will belong to either the
539 * active_list or flushing_list, last_rendering_seqno can
540 * be used to differentiate between the two elements.
542 struct list_head gpu_write_list;
545 * LRU list of objects which are not in the ringbuffer and
546 * are ready to unbind, but are still in the GTT.
548 * last_rendering_seqno is 0 while an object is in this list.
550 * A reference is not held on the buffer while on this list,
551 * as merely being GTT-bound shouldn't prevent its being
552 * freed, and we'll pull it off the list in the free path.
554 struct list_head inactive_list;
556 /** LRU list of objects with fence regs on them. */
557 struct list_head fence_list;
560 * List of breadcrumbs associated with GPU requests currently
563 struct list_head request_list;
566 * We leave the user IRQ off as much as possible,
567 * but this means that requests will finish and never
568 * be retired once the system goes idle. Set a timer to
569 * fire periodically while the ring is running. When it
570 * fires, go retire requests.
572 struct delayed_work retire_work;
574 uint32_t next_gem_seqno;
577 * Waiting sequence number, if any
579 uint32_t waiting_gem_seqno;
582 * Last seq seen at irq time
584 uint32_t irq_gem_seqno;
587 * Flag if the X Server, and thus DRM, is not currently in
588 * control of the device.
590 * This is set between LeaveVT and EnterVT. It needs to be
591 * replaced with a semaphore. It also needs to be
592 * transitioned away from for kernel modesetting.
597 * Flag if the hardware appears to be wedged.
599 * This is set when attempts to idle the device timeout.
600 * It prevents command submission from occuring and makes
601 * every pending request fail
605 /** Bit 6 swizzling required for X tiling */
606 uint32_t bit_6_swizzle_x;
607 /** Bit 6 swizzling required for Y tiling */
608 uint32_t bit_6_swizzle_y;
610 /* storage for physical objects */
611 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
613 struct sdvo_device_mapping sdvo_mappings[2];
614 /* indicate whether the LVDS_BORDER should be enabled or not */
615 unsigned int lvds_border_bits;
617 struct drm_crtc *plane_to_crtc_mapping[2];
618 struct drm_crtc *pipe_to_crtc_mapping[2];
619 wait_queue_head_t pending_flip_queue;
621 /* Reclocking support */
622 bool render_reclock_avail;
623 bool lvds_downclock_avail;
624 /* indicate whether the LVDS EDID is OK */
626 /* indicates the reduced downclock for LVDS*/
628 struct work_struct idle_work;
629 struct timer_list idle_timer;
633 struct child_device_config *child_dev;
634 struct drm_connector *int_lvds_connector;
636 bool mchbar_need_disable;
642 enum no_fbc_reason no_fbc_reason;
644 /* list of fbdev register on this device */
645 struct intel_fbdev *fbdev;
646 } drm_i915_private_t;
648 /** driver private structure attached to each drm_gem_object */
649 struct drm_i915_gem_object {
650 struct drm_gem_object base;
652 /** Current space allocated to this object in the GTT, if any. */
653 struct drm_mm_node *gtt_space;
655 /** This object's place on the active/flushing/inactive lists */
656 struct list_head list;
657 /** This object's place on GPU write list */
658 struct list_head gpu_write_list;
660 /** This object's place on the fenced object LRU */
661 struct list_head fence_list;
664 * This is set if the object is on the active or flushing lists
665 * (has pending rendering), and is not set if it's on inactive (ready
671 * This is set if the object has been written to since last bound
676 /** AGP memory structure for our GTT binding. */
677 DRM_AGP_MEM *agp_mem;
683 * Current offset of the object in GTT space.
685 * This is the same as gtt_space->start
690 * Fake offset for use by mmap(2)
692 uint64_t mmap_offset;
695 * Fence register bits (if any) for this object. Will be set
696 * as needed when mapped into the GTT.
697 * Protected by dev->struct_mutex.
701 /** How many users have pinned this object in GTT space */
704 /** Breadcrumb of last rendering to the buffer. */
705 uint32_t last_rendering_seqno;
707 /** Current tiling mode for the object. */
708 uint32_t tiling_mode;
711 /** Record of address bit 17 of each page at last unbind. */
714 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
718 * If present, while GEM_DOMAIN_CPU is in the read domain this array
719 * flags which individual pages are valid.
721 uint8_t *page_cpu_valid;
723 /** User space pin count and filp owning the pin */
724 uint32_t user_pin_count;
725 struct drm_file *pin_filp;
727 /** for phy allocated objects */
728 struct drm_i915_gem_phys_object *phys_obj;
731 * Used for checking the object doesn't appear more than once
732 * in an execbuffer object list.
737 * Advice: are the backing pages purgeable?
742 * Number of crtcs where this object is currently the fb, but
743 * will be page flipped away on the next vblank. When it
744 * reaches 0, dev_priv->pending_flip_queue will be woken up.
746 atomic_t pending_flip;
749 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
752 * Request queue structure.
754 * The request queue allows us to note sequence numbers that have been emitted
755 * and may be associated with active buffers to be retired.
757 * By keeping this list, we can avoid having to do questionable
758 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
759 * an emission time with seqnos for tracking how far ahead of the GPU we are.
761 struct drm_i915_gem_request {
762 /** GEM sequence number associated with this request. */
765 /** Time at which this request was emitted, in jiffies. */
766 unsigned long emitted_jiffies;
768 /** global list entry for this request */
769 struct list_head list;
771 /** file_priv list entry for this request */
772 struct list_head client_list;
775 struct drm_i915_file_private {
777 struct list_head request_list;
781 enum intel_chip_family {
788 extern struct drm_ioctl_desc i915_ioctls[];
789 extern int i915_max_ioctl;
790 extern unsigned int i915_fbpercrtc;
791 extern unsigned int i915_powersave;
792 extern unsigned int i915_lvds_downclock;
794 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
795 extern int i915_resume(struct drm_device *dev);
796 extern void i915_save_display(struct drm_device *dev);
797 extern void i915_restore_display(struct drm_device *dev);
798 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
799 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
802 extern void i915_kernel_lost_context(struct drm_device * dev);
803 extern int i915_driver_load(struct drm_device *, unsigned long flags);
804 extern int i915_driver_unload(struct drm_device *);
805 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
806 extern void i915_driver_lastclose(struct drm_device * dev);
807 extern void i915_driver_preclose(struct drm_device *dev,
808 struct drm_file *file_priv);
809 extern void i915_driver_postclose(struct drm_device *dev,
810 struct drm_file *file_priv);
811 extern int i915_driver_device_is_agp(struct drm_device * dev);
812 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
814 extern int i915_emit_box(struct drm_device *dev,
815 struct drm_clip_rect *boxes,
816 int i, int DR1, int DR4);
817 extern int i965_reset(struct drm_device *dev, u8 flags);
820 void i915_hangcheck_elapsed(unsigned long data);
821 void i915_destroy_error_state(struct drm_device *dev);
822 extern int i915_irq_emit(struct drm_device *dev, void *data,
823 struct drm_file *file_priv);
824 extern int i915_irq_wait(struct drm_device *dev, void *data,
825 struct drm_file *file_priv);
826 void i915_user_irq_get(struct drm_device *dev);
827 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
828 void i915_user_irq_put(struct drm_device *dev);
829 extern void i915_enable_interrupt (struct drm_device *dev);
831 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
832 extern void i915_driver_irq_preinstall(struct drm_device * dev);
833 extern int i915_driver_irq_postinstall(struct drm_device *dev);
834 extern void i915_driver_irq_uninstall(struct drm_device * dev);
835 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
836 struct drm_file *file_priv);
837 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
838 struct drm_file *file_priv);
839 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
840 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
841 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
842 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
843 extern int i915_vblank_swap(struct drm_device *dev, void *data,
844 struct drm_file *file_priv);
845 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
848 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
851 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
853 void intel_enable_asle (struct drm_device *dev);
857 extern int i915_mem_alloc(struct drm_device *dev, void *data,
858 struct drm_file *file_priv);
859 extern int i915_mem_free(struct drm_device *dev, void *data,
860 struct drm_file *file_priv);
861 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
862 struct drm_file *file_priv);
863 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
864 struct drm_file *file_priv);
865 extern void i915_mem_takedown(struct mem_block **heap);
866 extern void i915_mem_release(struct drm_device * dev,
867 struct drm_file *file_priv, struct mem_block *heap);
869 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
870 struct drm_file *file_priv);
871 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
872 struct drm_file *file_priv);
873 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
874 struct drm_file *file_priv);
875 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
876 struct drm_file *file_priv);
877 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
878 struct drm_file *file_priv);
879 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
880 struct drm_file *file_priv);
881 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
882 struct drm_file *file_priv);
883 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
884 struct drm_file *file_priv);
885 int i915_gem_execbuffer(struct drm_device *dev, void *data,
886 struct drm_file *file_priv);
887 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
888 struct drm_file *file_priv);
889 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
890 struct drm_file *file_priv);
891 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
892 struct drm_file *file_priv);
893 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
894 struct drm_file *file_priv);
895 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
896 struct drm_file *file_priv);
897 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
898 struct drm_file *file_priv);
899 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
900 struct drm_file *file_priv);
901 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
902 struct drm_file *file_priv);
903 int i915_gem_set_tiling(struct drm_device *dev, void *data,
904 struct drm_file *file_priv);
905 int i915_gem_get_tiling(struct drm_device *dev, void *data,
906 struct drm_file *file_priv);
907 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
908 struct drm_file *file_priv);
909 void i915_gem_load(struct drm_device *dev);
910 int i915_gem_init_object(struct drm_gem_object *obj);
911 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
913 void i915_gem_free_object(struct drm_gem_object *obj);
914 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
915 void i915_gem_object_unpin(struct drm_gem_object *obj);
916 int i915_gem_object_unbind(struct drm_gem_object *obj);
917 void i915_gem_release_mmap(struct drm_gem_object *obj);
918 void i915_gem_lastclose(struct drm_device *dev);
919 uint32_t i915_get_gem_seqno(struct drm_device *dev);
920 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
921 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
922 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
923 void i915_gem_retire_requests(struct drm_device *dev);
924 void i915_gem_retire_work_handler(struct work_struct *work);
925 void i915_gem_clflush_object(struct drm_gem_object *obj);
926 int i915_gem_object_set_domain(struct drm_gem_object *obj,
927 uint32_t read_domains,
928 uint32_t write_domain);
929 int i915_gem_init_ringbuffer(struct drm_device *dev);
930 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
931 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
933 int i915_gem_idle(struct drm_device *dev);
934 uint32_t i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
935 uint32_t flush_domains);
936 int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible);
937 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
938 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
940 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
941 int i915_gem_attach_phys_object(struct drm_device *dev,
942 struct drm_gem_object *obj, int id);
943 void i915_gem_detach_phys_object(struct drm_device *dev,
944 struct drm_gem_object *obj);
945 void i915_gem_free_all_phys_object(struct drm_device *dev);
946 int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
947 void i915_gem_object_put_pages(struct drm_gem_object *obj);
948 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
949 void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
951 void i915_gem_shrinker_init(void);
952 void i915_gem_shrinker_exit(void);
954 /* i915_gem_tiling.c */
955 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
956 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
957 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
958 bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
960 bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
963 /* i915_gem_debug.c */
964 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
965 const char *where, uint32_t mark);
967 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
969 #define i915_verify_inactive(dev, file, line)
971 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
972 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
973 const char *where, uint32_t mark);
974 void i915_dump_lru(struct drm_device *dev, const char *where);
977 int i915_debugfs_init(struct drm_minor *minor);
978 void i915_debugfs_cleanup(struct drm_minor *minor);
981 extern int i915_save_state(struct drm_device *dev);
982 extern int i915_restore_state(struct drm_device *dev);
985 extern int i915_save_state(struct drm_device *dev);
986 extern int i915_restore_state(struct drm_device *dev);
989 /* i915_opregion.c */
990 extern int intel_opregion_init(struct drm_device *dev, int resume);
991 extern void intel_opregion_free(struct drm_device *dev, int suspend);
992 extern void opregion_asle_intr(struct drm_device *dev);
993 extern void ironlake_opregion_gse_intr(struct drm_device *dev);
994 extern void opregion_enable_asle(struct drm_device *dev);
996 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
997 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
998 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
999 static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; }
1000 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
1004 extern void intel_modeset_init(struct drm_device *dev);
1005 extern void intel_modeset_cleanup(struct drm_device *dev);
1006 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1007 extern void i8xx_disable_fbc(struct drm_device *dev);
1008 extern void g4x_disable_fbc(struct drm_device *dev);
1010 extern void intel_detect_pch (struct drm_device *dev);
1011 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1014 * Lock test for when it's just for synchronization of ring access.
1016 * In that case, we don't need to do it when GEM is initialized as nobody else
1017 * has access to the ring.
1019 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1020 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
1021 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1024 #define I915_READ(reg) readl(dev_priv->regs + (reg))
1025 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
1026 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1027 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1028 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1029 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1030 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1031 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1032 #define POSTING_READ(reg) (void)I915_READ(reg)
1034 #define I915_VERBOSE 0
1036 #define RING_LOCALS volatile unsigned int *ring_virt__;
1038 #define BEGIN_LP_RING(n) do { \
1039 int bytes__ = 4*(n); \
1040 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
1041 /* a wrap must occur between instructions so pad beforehand */ \
1042 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
1043 i915_wrap_ring(dev); \
1044 if (unlikely (dev_priv->ring.space < bytes__)) \
1045 i915_wait_ring(dev, bytes__, __func__); \
1046 ring_virt__ = (unsigned int *) \
1047 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
1048 dev_priv->ring.tail += bytes__; \
1049 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
1050 dev_priv->ring.space -= bytes__; \
1053 #define OUT_RING(n) do { \
1054 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
1055 *ring_virt__++ = (n); \
1058 #define ADVANCE_LP_RING() do { \
1060 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
1061 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
1065 * Reads a dword out of the status page, which is written to from the command
1066 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1067 * MI_STORE_DATA_IMM.
1069 * The following dwords have a reserved meaning:
1070 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1071 * 0x04: ring 0 head pointer
1072 * 0x05: ring 1 head pointer (915-class)
1073 * 0x06: ring 2 head pointer (915-class)
1074 * 0x10-0x1b: Context status DWords (GM45)
1075 * 0x1f: Last written status offset. (GM45)
1077 * The area from dword 0x20 to 0x3ff is available for driver usage.
1079 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
1080 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1081 #define I915_GEM_HWS_INDEX 0x20
1082 #define I915_BREADCRUMB_INDEX 0x21
1084 extern int i915_wrap_ring(struct drm_device * dev);
1085 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1087 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1089 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1090 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1091 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
1092 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1093 #define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
1094 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1095 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1096 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1097 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1098 #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
1099 #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
1100 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1101 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1102 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1103 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1104 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1105 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1106 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1107 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1108 #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1109 #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1110 #define IS_GEN6(dev) (INTEL_INFO(dev)->is_gen6)
1111 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1113 #define IS_GEN3(dev) (IS_I915G(dev) || \
1119 #define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \
1120 (dev)->pci_device == 0x2982 || \
1121 (dev)->pci_device == 0x2992 || \
1122 (dev)->pci_device == 0x29A2 || \
1123 (dev)->pci_device == 0x2A02 || \
1124 (dev)->pci_device == 0x2A12 || \
1125 (dev)->pci_device == 0x2E02 || \
1126 (dev)->pci_device == 0x2E12 || \
1127 (dev)->pci_device == 0x2E22 || \
1128 (dev)->pci_device == 0x2E32 || \
1129 (dev)->pci_device == 0x2A42 || \
1130 (dev)->pci_device == 0x2E42)
1132 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1134 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1135 * rows, which changed the alignment requirements and fence programming.
1137 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1139 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1140 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1141 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1142 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1143 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1144 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \
1146 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1147 /* dsparb controlled by hw only */
1148 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1150 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1151 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1152 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1153 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1155 #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
1158 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1159 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1161 #define PRIMARY_RINGBUFFER_SIZE (128*1024)