1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
40 /* General customization:
43 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45 #define DRIVER_NAME "i915"
46 #define DRIVER_DESC "Intel Graphics"
47 #define DRIVER_DATE "20080730"
59 #define I915_NUM_PIPE 2
61 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66 * 1.2: Add Power Management
67 * 1.3: Add vblank support
68 * 1.4: Fix cmdbuffer path, add heap destroy
69 * 1.5: Add vblank pipe configuration
70 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
71 * - Support vertical blank on secondary display pipe
73 #define DRIVER_MAJOR 1
74 #define DRIVER_MINOR 6
75 #define DRIVER_PATCHLEVEL 0
77 #define WATCH_COHERENCY 0
81 #define WATCH_PWRITE 0
83 #define I915_GEM_PHYS_CURSOR_0 1
84 #define I915_GEM_PHYS_CURSOR_1 2
85 #define I915_GEM_PHYS_OVERLAY_REGS 3
86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
88 struct drm_i915_gem_phys_object {
90 struct page **page_list;
91 drm_dma_handle_t *handle;
92 struct drm_gem_object *cur_obj;
96 struct mem_block *next;
97 struct mem_block *prev;
100 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
103 struct opregion_header;
104 struct opregion_acpi;
105 struct opregion_swsci;
106 struct opregion_asle;
108 struct intel_opregion {
109 struct opregion_header *header;
110 struct opregion_acpi *acpi;
111 struct opregion_swsci *swsci;
112 struct opregion_asle *asle;
115 #define OPREGION_SIZE (8*1024)
117 struct intel_overlay;
118 struct intel_overlay_error_state;
120 struct drm_i915_master_private {
121 drm_local_map_t *sarea;
122 struct _drm_i915_sarea *sarea_priv;
124 #define I915_FENCE_REG_NONE -1
126 struct drm_i915_fence_reg {
127 struct drm_gem_object *obj;
128 struct list_head lru_list;
132 struct sdvo_device_mapping {
142 struct drm_i915_error_state {
157 struct drm_i915_error_object {
161 } *ringbuffer, *batchbuffer[2];
162 struct drm_i915_error_buffer {
176 struct intel_overlay_error_state *overlay;
179 struct drm_i915_display_funcs {
180 void (*dpms)(struct drm_crtc *crtc, int mode);
181 bool (*fbc_enabled)(struct drm_device *dev);
182 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
183 void (*disable_fbc)(struct drm_device *dev);
184 int (*get_display_clock_speed)(struct drm_device *dev);
185 int (*get_fifo_size)(struct drm_device *dev, int plane);
186 void (*update_wm)(struct drm_device *dev, int planea_clock,
187 int planeb_clock, int sr_hdisplay, int sr_htotal,
189 /* clock updates for mode set */
191 /* render clock increase/decrease */
192 /* display clock increase/decrease */
193 /* pll clock increase/decrease */
194 /* clock gating init */
197 struct intel_device_info {
207 u8 is_broadwater : 1;
211 u8 has_pipe_cxsr : 1;
213 u8 cursor_needs_physical : 1;
215 u8 overlay_needs_physical : 1;
222 FBC_NO_OUTPUT, /* no outputs enabled to compress */
223 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
224 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
225 FBC_MODE_TOO_LARGE, /* mode too large for compression */
226 FBC_BAD_PLANE, /* fbc not supported on plane */
227 FBC_NOT_TILED, /* buffer not tiled */
228 FBC_MULTIPLE_PIPES, /* more than one pipe active */
232 PCH_IBX, /* Ibexpeak PCH */
233 PCH_CPT, /* Cougarpoint PCH */
236 #define QUIRK_PIPEA_FORCE (1<<0)
240 typedef struct drm_i915_private {
241 struct drm_device *dev;
243 const struct intel_device_info *info;
250 struct i2c_adapter adapter;
251 struct i2c_adapter *force_bit;
255 struct pci_dev *bridge_dev;
256 struct intel_ring_buffer render_ring;
257 struct intel_ring_buffer bsd_ring;
258 struct intel_ring_buffer blt_ring;
261 drm_dma_handle_t *status_page_dmah;
263 dma_addr_t dma_status_page;
265 unsigned int seqno_gfx_addr;
266 drm_local_map_t hws_map;
267 struct drm_gem_object *seqno_obj;
268 struct drm_gem_object *pwrctx;
269 struct drm_gem_object *renderctx;
271 struct resource mch_res;
278 #define I915_DEBUG_READ (1<<0)
279 #define I915_DEBUG_WRITE (1<<1)
280 unsigned long debug_flags;
282 wait_queue_head_t irq_queue;
283 atomic_t irq_received;
284 /** Protects user_irq_refcount and irq_mask_reg */
285 spinlock_t user_irq_lock;
287 /** Cached value of IMR to avoid reads in updating the bitfield */
290 /** splitted irq regs for graphics and display engine on Ironlake,
291 irq_mask_reg is still used for display irq. */
293 u32 gt_irq_enable_reg;
294 u32 de_irq_enable_reg;
295 u32 pch_irq_mask_reg;
296 u32 pch_irq_enable_reg;
298 u32 hotplug_supported_mask;
299 struct work_struct hotplug_work;
301 int tex_lru_log_granularity;
302 int allow_batchbuffer;
303 struct mem_block *agp_heap;
304 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
308 /* For hangcheck timer */
309 #define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */
310 struct timer_list hangcheck_timer;
313 uint32_t last_instdone;
314 uint32_t last_instdone1;
316 unsigned long cfb_size;
317 unsigned long cfb_pitch;
318 unsigned long cfb_offset;
325 struct intel_opregion opregion;
328 struct intel_overlay *overlay;
331 int backlight_level; /* restore backlight to this value */
332 struct drm_display_mode *panel_fixed_mode;
333 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
334 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
336 /* Feature bits from the VBIOS */
337 unsigned int int_tv_support:1;
338 unsigned int lvds_dither:1;
339 unsigned int lvds_vbt:1;
340 unsigned int int_crt_support:1;
341 unsigned int lvds_use_ssc:1;
352 struct edp_power_seq pps;
354 bool no_aux_handshake;
356 struct notifier_block lid_notifier;
359 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
360 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
361 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
363 unsigned int fsb_freq, mem_freq, is_ddr3;
365 spinlock_t error_lock;
366 struct drm_i915_error_state *first_error;
367 struct work_struct error_work;
368 struct completion error_completion;
369 struct workqueue_struct *wq;
371 /* Display functions */
372 struct drm_i915_display_funcs display;
374 /* PCH chipset type */
375 enum intel_pch pch_type;
377 unsigned long quirks;
402 u32 saveTRANS_HTOTAL_A;
403 u32 saveTRANS_HBLANK_A;
404 u32 saveTRANS_HSYNC_A;
405 u32 saveTRANS_VTOTAL_A;
406 u32 saveTRANS_VBLANK_A;
407 u32 saveTRANS_VSYNC_A;
415 u32 savePFIT_PGM_RATIOS;
416 u32 saveBLC_HIST_CTL;
418 u32 saveBLC_PWM_CTL2;
419 u32 saveBLC_CPU_PWM_CTL;
420 u32 saveBLC_CPU_PWM_CTL2;
433 u32 saveTRANS_HTOTAL_B;
434 u32 saveTRANS_HBLANK_B;
435 u32 saveTRANS_HSYNC_B;
436 u32 saveTRANS_VTOTAL_B;
437 u32 saveTRANS_VBLANK_B;
438 u32 saveTRANS_VSYNC_B;
452 u32 savePP_ON_DELAYS;
453 u32 savePP_OFF_DELAYS;
461 u32 savePFIT_CONTROL;
462 u32 save_palette_a[256];
463 u32 save_palette_b[256];
464 u32 saveDPFC_CB_BASE;
465 u32 saveFBC_CFB_BASE;
468 u32 saveFBC_CONTROL2;
478 u32 saveCACHE_MODE_0;
479 u32 saveMI_ARB_STATE;
490 uint64_t saveFENCE[16];
501 u32 savePIPEA_GMCH_DATA_M;
502 u32 savePIPEB_GMCH_DATA_M;
503 u32 savePIPEA_GMCH_DATA_N;
504 u32 savePIPEB_GMCH_DATA_N;
505 u32 savePIPEA_DP_LINK_M;
506 u32 savePIPEB_DP_LINK_M;
507 u32 savePIPEA_DP_LINK_N;
508 u32 savePIPEB_DP_LINK_N;
519 u32 savePCH_DREF_CONTROL;
520 u32 saveDISP_ARB_CTL;
521 u32 savePIPEA_DATA_M1;
522 u32 savePIPEA_DATA_N1;
523 u32 savePIPEA_LINK_M1;
524 u32 savePIPEA_LINK_N1;
525 u32 savePIPEB_DATA_M1;
526 u32 savePIPEB_DATA_N1;
527 u32 savePIPEB_LINK_M1;
528 u32 savePIPEB_LINK_N1;
529 u32 saveMCHBAR_RENDER_STANDBY;
532 /** Bridge to intel-gtt-ko */
533 struct intel_gtt *gtt;
534 /** Memory allocator for GTT stolen memory */
536 /** Memory allocator for GTT */
537 struct drm_mm gtt_space;
539 struct io_mapping *gtt_mapping;
543 * Membership on list of all loaded devices, used to evict
544 * inactive buffers under memory pressure.
546 * Modifications should only be done whilst holding the
547 * shrink_list_lock spinlock.
549 struct list_head shrink_list;
552 * List of objects currently involved in rendering.
554 * Includes buffers having the contents of their GPU caches
555 * flushed, not necessarily primitives. last_rendering_seqno
556 * represents when the rendering involved will be completed.
558 * A reference is held on the buffer while on this list.
560 struct list_head active_list;
563 * List of objects which are not in the ringbuffer but which
564 * still have a write_domain which needs to be flushed before
567 * last_rendering_seqno is 0 while an object is in this list.
569 * A reference is held on the buffer while on this list.
571 struct list_head flushing_list;
574 * LRU list of objects which are not in the ringbuffer and
575 * are ready to unbind, but are still in the GTT.
577 * last_rendering_seqno is 0 while an object is in this list.
579 * A reference is not held on the buffer while on this list,
580 * as merely being GTT-bound shouldn't prevent its being
581 * freed, and we'll pull it off the list in the free path.
583 struct list_head inactive_list;
586 * LRU list of objects which are not in the ringbuffer but
587 * are still pinned in the GTT.
589 struct list_head pinned_list;
591 /** LRU list of objects with fence regs on them. */
592 struct list_head fence_list;
595 * List of objects currently pending being freed.
597 * These objects are no longer in use, but due to a signal
598 * we were prevented from freeing them at the appointed time.
600 struct list_head deferred_free_list;
603 * We leave the user IRQ off as much as possible,
604 * but this means that requests will finish and never
605 * be retired once the system goes idle. Set a timer to
606 * fire periodically while the ring is running. When it
607 * fires, go retire requests.
609 struct delayed_work retire_work;
612 * Waiting sequence number, if any
614 uint32_t waiting_gem_seqno;
617 * Last seq seen at irq time
619 uint32_t irq_gem_seqno;
622 * Flag if the X Server, and thus DRM, is not currently in
623 * control of the device.
625 * This is set between LeaveVT and EnterVT. It needs to be
626 * replaced with a semaphore. It also needs to be
627 * transitioned away from for kernel modesetting.
632 * Flag if the hardware appears to be wedged.
634 * This is set when attempts to idle the device timeout.
635 * It prevents command submission from occuring and makes
636 * every pending request fail
640 /** Bit 6 swizzling required for X tiling */
641 uint32_t bit_6_swizzle_x;
642 /** Bit 6 swizzling required for Y tiling */
643 uint32_t bit_6_swizzle_y;
645 /* storage for physical objects */
646 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
648 uint32_t flush_rings;
650 /* accounting, useful for userland debugging */
651 size_t object_memory;
659 struct sdvo_device_mapping sdvo_mappings[2];
660 /* indicate whether the LVDS_BORDER should be enabled or not */
661 unsigned int lvds_border_bits;
662 /* Panel fitter placement and size for Ironlake+ */
663 u32 pch_pf_pos, pch_pf_size;
665 struct drm_crtc *plane_to_crtc_mapping[2];
666 struct drm_crtc *pipe_to_crtc_mapping[2];
667 wait_queue_head_t pending_flip_queue;
668 bool flip_pending_is_done;
670 /* Reclocking support */
671 bool render_reclock_avail;
672 bool lvds_downclock_avail;
673 /* indicates the reduced downclock for LVDS*/
675 struct work_struct idle_work;
676 struct timer_list idle_timer;
680 struct child_device_config *child_dev;
681 struct drm_connector *int_lvds_connector;
683 bool mchbar_need_disable;
692 unsigned long last_time1;
694 struct timespec last_time2;
695 unsigned long gfx_power;
699 spinlock_t *mchdev_lock;
701 enum no_fbc_reason no_fbc_reason;
703 struct drm_mm_node *compressed_fb;
704 struct drm_mm_node *compressed_llb;
706 unsigned long last_gpu_reset;
708 /* list of fbdev register on this device */
709 struct intel_fbdev *fbdev;
710 } drm_i915_private_t;
712 /** driver private structure attached to each drm_gem_object */
713 struct drm_i915_gem_object {
714 struct drm_gem_object base;
716 /** Current space allocated to this object in the GTT, if any. */
717 struct drm_mm_node *gtt_space;
719 /** This object's place on the active/flushing/inactive lists */
720 struct list_head ring_list;
721 struct list_head mm_list;
722 /** This object's place on GPU write list */
723 struct list_head gpu_write_list;
724 /** This object's place on eviction list */
725 struct list_head evict_list;
728 * This is set if the object is on the active or flushing lists
729 * (has pending rendering), and is not set if it's on inactive (ready
732 unsigned int active : 1;
735 * This is set if the object has been written to since last bound
738 unsigned int dirty : 1;
741 * Fence register bits (if any) for this object. Will be set
742 * as needed when mapped into the GTT.
743 * Protected by dev->struct_mutex.
745 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
747 signed int fence_reg : 5;
750 * Used for checking the object doesn't appear more than once
751 * in an execbuffer object list.
753 unsigned int in_execbuffer : 1;
756 * Advice: are the backing pages purgeable?
758 unsigned int madv : 2;
761 * Refcount for the pages array. With the current locking scheme, there
762 * are at most two concurrent users: Binding a bo to the gtt and
763 * pwrite/pread using physical addresses. So two bits for a maximum
764 * of two users are enough.
766 unsigned int pages_refcount : 2;
767 #define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3
770 * Current tiling mode for the object.
772 unsigned int tiling_mode : 2;
774 /** How many users have pinned this object in GTT space. The following
775 * users can each hold at most one reference: pwrite/pread, pin_ioctl
776 * (via user_pin_count), execbuffer (objects are not allowed multiple
777 * times for the same batchbuffer), and the framebuffer code. When
778 * switching/pageflipping, the framebuffer code has at most two buffers
781 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
782 * bits with absolutely no headroom. So use 4 bits. */
783 unsigned int pin_count : 4;
784 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
786 /** AGP memory structure for our GTT binding. */
787 DRM_AGP_MEM *agp_mem;
792 * Current offset of the object in GTT space.
794 * This is the same as gtt_space->start
798 /* Which ring is refering to is this object */
799 struct intel_ring_buffer *ring;
802 * Fake offset for use by mmap(2)
804 uint64_t mmap_offset;
806 /** Breadcrumb of last rendering to the buffer. */
807 uint32_t last_rendering_seqno;
809 /** Current tiling stride for the object, if it's tiled. */
812 /** Record of address bit 17 of each page at last unbind. */
813 unsigned long *bit_17;
815 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
819 * If present, while GEM_DOMAIN_CPU is in the read domain this array
820 * flags which individual pages are valid.
822 uint8_t *page_cpu_valid;
824 /** User space pin count and filp owning the pin */
825 uint32_t user_pin_count;
826 struct drm_file *pin_filp;
828 /** for phy allocated objects */
829 struct drm_i915_gem_phys_object *phys_obj;
832 * Number of crtcs where this object is currently the fb, but
833 * will be page flipped away on the next vblank. When it
834 * reaches 0, dev_priv->pending_flip_queue will be woken up.
836 atomic_t pending_flip;
839 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
842 * Request queue structure.
844 * The request queue allows us to note sequence numbers that have been emitted
845 * and may be associated with active buffers to be retired.
847 * By keeping this list, we can avoid having to do questionable
848 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
849 * an emission time with seqnos for tracking how far ahead of the GPU we are.
851 struct drm_i915_gem_request {
852 /** On Which ring this request was generated */
853 struct intel_ring_buffer *ring;
855 /** GEM sequence number associated with this request. */
858 /** Time at which this request was emitted, in jiffies. */
859 unsigned long emitted_jiffies;
861 /** global list entry for this request */
862 struct list_head list;
864 struct drm_i915_file_private *file_priv;
865 /** file_priv list entry for this request */
866 struct list_head client_list;
869 struct drm_i915_file_private {
871 struct spinlock lock;
872 struct list_head request_list;
876 enum intel_chip_family {
883 extern struct drm_ioctl_desc i915_ioctls[];
884 extern int i915_max_ioctl;
885 extern unsigned int i915_fbpercrtc;
886 extern unsigned int i915_powersave;
887 extern unsigned int i915_lvds_downclock;
889 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
890 extern int i915_resume(struct drm_device *dev);
891 extern void i915_save_display(struct drm_device *dev);
892 extern void i915_restore_display(struct drm_device *dev);
893 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
894 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
897 extern void i915_kernel_lost_context(struct drm_device * dev);
898 extern int i915_driver_load(struct drm_device *, unsigned long flags);
899 extern int i915_driver_unload(struct drm_device *);
900 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
901 extern void i915_driver_lastclose(struct drm_device * dev);
902 extern void i915_driver_preclose(struct drm_device *dev,
903 struct drm_file *file_priv);
904 extern void i915_driver_postclose(struct drm_device *dev,
905 struct drm_file *file_priv);
906 extern int i915_driver_device_is_agp(struct drm_device * dev);
907 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
909 extern int i915_emit_box(struct drm_device *dev,
910 struct drm_clip_rect *boxes,
911 int i, int DR1, int DR4);
912 extern int i915_reset(struct drm_device *dev, u8 flags);
913 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
914 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
915 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
916 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
920 void i915_hangcheck_elapsed(unsigned long data);
921 extern int i915_irq_emit(struct drm_device *dev, void *data,
922 struct drm_file *file_priv);
923 extern int i915_irq_wait(struct drm_device *dev, void *data,
924 struct drm_file *file_priv);
925 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
926 extern void i915_enable_interrupt (struct drm_device *dev);
928 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
929 extern void i915_driver_irq_preinstall(struct drm_device * dev);
930 extern int i915_driver_irq_postinstall(struct drm_device *dev);
931 extern void i915_driver_irq_uninstall(struct drm_device * dev);
932 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
933 struct drm_file *file_priv);
934 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
935 struct drm_file *file_priv);
936 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
937 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
938 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
939 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
940 extern int i915_vblank_swap(struct drm_device *dev, void *data,
941 struct drm_file *file_priv);
942 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
943 extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
944 extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
946 extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
950 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
953 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
955 void intel_enable_asle (struct drm_device *dev);
957 #ifdef CONFIG_DEBUG_FS
958 extern void i915_destroy_error_state(struct drm_device *dev);
960 #define i915_destroy_error_state(x)
965 extern int i915_mem_alloc(struct drm_device *dev, void *data,
966 struct drm_file *file_priv);
967 extern int i915_mem_free(struct drm_device *dev, void *data,
968 struct drm_file *file_priv);
969 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
970 struct drm_file *file_priv);
971 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
972 struct drm_file *file_priv);
973 extern void i915_mem_takedown(struct mem_block **heap);
974 extern void i915_mem_release(struct drm_device * dev,
975 struct drm_file *file_priv, struct mem_block *heap);
977 int i915_gem_check_is_wedged(struct drm_device *dev);
978 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
979 struct drm_file *file_priv);
980 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
981 struct drm_file *file_priv);
982 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
983 struct drm_file *file_priv);
984 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
985 struct drm_file *file_priv);
986 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
987 struct drm_file *file_priv);
988 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
989 struct drm_file *file_priv);
990 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
991 struct drm_file *file_priv);
992 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
993 struct drm_file *file_priv);
994 int i915_gem_execbuffer(struct drm_device *dev, void *data,
995 struct drm_file *file_priv);
996 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
997 struct drm_file *file_priv);
998 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
999 struct drm_file *file_priv);
1000 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1001 struct drm_file *file_priv);
1002 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1003 struct drm_file *file_priv);
1004 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1005 struct drm_file *file_priv);
1006 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1007 struct drm_file *file_priv);
1008 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1009 struct drm_file *file_priv);
1010 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1011 struct drm_file *file_priv);
1012 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1013 struct drm_file *file_priv);
1014 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1015 struct drm_file *file_priv);
1016 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1017 struct drm_file *file_priv);
1018 void i915_gem_load(struct drm_device *dev);
1019 int i915_gem_init_object(struct drm_gem_object *obj);
1020 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
1022 void i915_gem_free_object(struct drm_gem_object *obj);
1023 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
1024 void i915_gem_object_unpin(struct drm_gem_object *obj);
1025 int i915_gem_object_unbind(struct drm_gem_object *obj);
1026 void i915_gem_release_mmap(struct drm_gem_object *obj);
1027 void i915_gem_lastclose(struct drm_device *dev);
1030 * Returns true if seq1 is later than seq2.
1033 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1035 return (int32_t)(seq1 - seq2) >= 0;
1038 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
1039 bool interruptible);
1040 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
1041 bool interruptible);
1042 void i915_gem_retire_requests(struct drm_device *dev);
1043 void i915_gem_reset(struct drm_device *dev);
1044 void i915_gem_clflush_object(struct drm_gem_object *obj);
1045 int i915_gem_object_set_domain(struct drm_gem_object *obj,
1046 uint32_t read_domains,
1047 uint32_t write_domain);
1048 int i915_gem_init_ringbuffer(struct drm_device *dev);
1049 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1050 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
1052 int i915_gpu_idle(struct drm_device *dev);
1053 int i915_gem_idle(struct drm_device *dev);
1054 uint32_t i915_add_request(struct drm_device *dev,
1055 struct drm_file *file_priv,
1056 struct drm_i915_gem_request *request,
1057 struct intel_ring_buffer *ring);
1058 int i915_do_wait_request(struct drm_device *dev,
1061 struct intel_ring_buffer *ring);
1062 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1063 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
1065 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
1067 int i915_gem_attach_phys_object(struct drm_device *dev,
1068 struct drm_gem_object *obj,
1071 void i915_gem_detach_phys_object(struct drm_device *dev,
1072 struct drm_gem_object *obj);
1073 void i915_gem_free_all_phys_object(struct drm_device *dev);
1074 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
1076 void i915_gem_shrinker_init(void);
1077 void i915_gem_shrinker_exit(void);
1079 /* i915_gem_evict.c */
1080 int i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignment);
1081 int i915_gem_evict_everything(struct drm_device *dev);
1082 int i915_gem_evict_inactive(struct drm_device *dev);
1084 /* i915_gem_tiling.c */
1085 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1086 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
1087 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
1088 bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
1090 bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
1093 /* i915_gem_debug.c */
1094 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
1095 const char *where, uint32_t mark);
1097 int i915_verify_lists(struct drm_device *dev);
1099 #define i915_verify_lists(dev) 0
1101 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
1102 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
1103 const char *where, uint32_t mark);
1105 /* i915_debugfs.c */
1106 int i915_debugfs_init(struct drm_minor *minor);
1107 void i915_debugfs_cleanup(struct drm_minor *minor);
1109 /* i915_suspend.c */
1110 extern int i915_save_state(struct drm_device *dev);
1111 extern int i915_restore_state(struct drm_device *dev);
1113 /* i915_suspend.c */
1114 extern int i915_save_state(struct drm_device *dev);
1115 extern int i915_restore_state(struct drm_device *dev);
1118 extern int intel_setup_gmbus(struct drm_device *dev);
1119 extern void intel_teardown_gmbus(struct drm_device *dev);
1120 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1121 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1122 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1124 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1126 extern void intel_i2c_reset(struct drm_device *dev);
1128 /* intel_opregion.c */
1129 extern int intel_opregion_setup(struct drm_device *dev);
1131 extern void intel_opregion_init(struct drm_device *dev);
1132 extern void intel_opregion_fini(struct drm_device *dev);
1133 extern void intel_opregion_asle_intr(struct drm_device *dev);
1134 extern void intel_opregion_gse_intr(struct drm_device *dev);
1135 extern void intel_opregion_enable_asle(struct drm_device *dev);
1137 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1138 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1139 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1140 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1141 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1146 extern void intel_register_dsm_handler(void);
1147 extern void intel_unregister_dsm_handler(void);
1149 static inline void intel_register_dsm_handler(void) { return; }
1150 static inline void intel_unregister_dsm_handler(void) { return; }
1151 #endif /* CONFIG_ACPI */
1154 extern void intel_modeset_init(struct drm_device *dev);
1155 extern void intel_modeset_cleanup(struct drm_device *dev);
1156 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1157 extern void i8xx_disable_fbc(struct drm_device *dev);
1158 extern void g4x_disable_fbc(struct drm_device *dev);
1159 extern void ironlake_disable_fbc(struct drm_device *dev);
1160 extern void intel_disable_fbc(struct drm_device *dev);
1161 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1162 extern bool intel_fbc_enabled(struct drm_device *dev);
1163 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1164 extern void intel_detect_pch (struct drm_device *dev);
1165 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1168 #ifdef CONFIG_DEBUG_FS
1169 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1170 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1174 * Lock test for when it's just for synchronization of ring access.
1176 * In that case, we don't need to do it when GEM is initialized as nobody else
1177 * has access to the ring.
1179 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1180 if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
1182 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1185 static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg)
1189 val = readl(dev_priv->regs + reg);
1190 if (dev_priv->debug_flags & I915_DEBUG_READ)
1191 printk(KERN_ERR "read 0x%08x from 0x%08x\n", val, reg);
1195 static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg,
1198 writel(val, dev_priv->regs + reg);
1199 if (dev_priv->debug_flags & I915_DEBUG_WRITE)
1200 printk(KERN_ERR "wrote 0x%08x to 0x%08x\n", val, reg);
1203 #define I915_READ(reg) i915_read(dev_priv, (reg))
1204 #define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val))
1205 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1206 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1207 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1208 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1209 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1210 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1211 #define POSTING_READ(reg) (void)I915_READ(reg)
1212 #define POSTING_READ16(reg) (void)I915_READ16(reg)
1214 #define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \
1216 #define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \
1219 #define I915_VERBOSE 0
1221 #define BEGIN_LP_RING(n) do { \
1222 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1224 DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \
1225 intel_ring_begin(dev, &dev_priv__->render_ring, (n)); \
1229 #define OUT_RING(x) do { \
1230 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1232 DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \
1233 intel_ring_emit(dev, &dev_priv__->render_ring, x); \
1236 #define ADVANCE_LP_RING() do { \
1237 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1239 DRM_DEBUG("ADVANCE_LP_RING %x\n", \
1240 dev_priv__->render_ring.tail); \
1241 intel_ring_advance(dev, &dev_priv__->render_ring); \
1245 * Reads a dword out of the status page, which is written to from the command
1246 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1247 * MI_STORE_DATA_IMM.
1249 * The following dwords have a reserved meaning:
1250 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1251 * 0x04: ring 0 head pointer
1252 * 0x05: ring 1 head pointer (915-class)
1253 * 0x06: ring 2 head pointer (915-class)
1254 * 0x10-0x1b: Context status DWords (GM45)
1255 * 0x1f: Last written status offset. (GM45)
1257 * The area from dword 0x20 to 0x3ff is available for driver usage.
1259 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1260 (dev_priv->render_ring.status_page.page_addr))[reg])
1261 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1262 #define I915_GEM_HWS_INDEX 0x20
1263 #define I915_BREADCRUMB_INDEX 0x21
1265 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1267 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1268 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1269 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1270 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1271 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1272 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1273 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1274 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1275 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1276 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1277 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1278 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1279 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1280 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1281 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1282 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1283 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1284 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1285 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1287 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1288 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1289 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1290 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1291 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1293 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1294 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1295 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1297 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1298 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1300 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1301 * rows, which changed the alignment requirements and fence programming.
1303 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1305 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1306 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1307 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1308 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1309 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1310 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1311 /* dsparb controlled by hw only */
1312 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1314 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1315 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1316 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1317 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1319 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
1320 #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
1322 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1323 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1325 #define PRIMARY_RINGBUFFER_SIZE (128*1024)