1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
51 #include "i915_params.h"
54 #include "intel_bios.h"
55 #include "intel_dpll_mgr.h"
56 #include "intel_guc.h"
57 #include "intel_lrc.h"
58 #include "intel_ringbuffer.h"
61 #include "i915_gem_gtt.h"
62 #include "i915_gem_render_state.h"
64 /* General customization:
67 #define DRIVER_NAME "i915"
68 #define DRIVER_DESC "Intel Graphics"
69 #define DRIVER_DATE "20160508"
72 /* Many gcc seem to no see through this and fall over :( */
74 #define WARN_ON(x) ({ \
75 bool __i915_warn_cond = (x); \
76 if (__builtin_constant_p(__i915_warn_cond)) \
77 BUILD_BUG_ON(__i915_warn_cond); \
78 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
80 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
84 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
86 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
87 (long) (x), __func__);
89 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
90 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
91 * which may not necessarily be a user visible problem. This will either
92 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
93 * enable distros and users to tailor their preferred amount of i915 abrt
96 #define I915_STATE_WARN(condition, format...) ({ \
97 int __ret_warn_on = !!(condition); \
98 if (unlikely(__ret_warn_on)) \
99 if (!WARN(i915.verbose_state_checks, format)) \
101 unlikely(__ret_warn_on); \
104 #define I915_STATE_WARN_ON(x) \
105 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
107 bool __i915_inject_load_failure(const char *func, int line);
108 #define i915_inject_load_failure() \
109 __i915_inject_load_failure(__func__, __LINE__)
111 static inline const char *yesno(bool v)
113 return v ? "yes" : "no";
116 static inline const char *onoff(bool v)
118 return v ? "on" : "off";
127 I915_MAX_PIPES = _PIPE_EDP
129 #define pipe_name(p) ((p) + 'A')
141 static inline const char *transcoder_name(enum transcoder transcoder)
143 switch (transcoder) {
152 case TRANSCODER_DSI_A:
154 case TRANSCODER_DSI_C:
161 static inline bool transcoder_is_dsi(enum transcoder transcoder)
163 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
167 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
168 * number of planes per CRTC. Not all platforms really have this many planes,
169 * which means some arrays of size I915_MAX_PLANES may have unused entries
170 * between the topmost sprite plane and the cursor plane.
179 #define plane_name(p) ((p) + 'A')
181 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
191 #define port_name(p) ((p) + 'A')
193 #define I915_NUM_PHYS_VLV 2
205 enum intel_display_power_domain {
209 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
210 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
211 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
212 POWER_DOMAIN_TRANSCODER_A,
213 POWER_DOMAIN_TRANSCODER_B,
214 POWER_DOMAIN_TRANSCODER_C,
215 POWER_DOMAIN_TRANSCODER_EDP,
216 POWER_DOMAIN_TRANSCODER_DSI_A,
217 POWER_DOMAIN_TRANSCODER_DSI_C,
218 POWER_DOMAIN_PORT_DDI_A_LANES,
219 POWER_DOMAIN_PORT_DDI_B_LANES,
220 POWER_DOMAIN_PORT_DDI_C_LANES,
221 POWER_DOMAIN_PORT_DDI_D_LANES,
222 POWER_DOMAIN_PORT_DDI_E_LANES,
223 POWER_DOMAIN_PORT_DSI,
224 POWER_DOMAIN_PORT_CRT,
225 POWER_DOMAIN_PORT_OTHER,
234 POWER_DOMAIN_MODESET,
240 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
241 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
242 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
243 #define POWER_DOMAIN_TRANSCODER(tran) \
244 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
245 (tran) + POWER_DOMAIN_TRANSCODER_A)
249 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
261 #define for_each_hpd_pin(__pin) \
262 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
264 struct i915_hotplug {
265 struct work_struct hotplug_work;
268 unsigned long last_jiffies;
273 HPD_MARK_DISABLED = 2
275 } stats[HPD_NUM_PINS];
277 struct delayed_work reenable_work;
279 struct intel_digital_port *irq_port[I915_MAX_PORTS];
282 struct work_struct dig_port_work;
285 * if we get a HPD irq from DP and a HPD irq from non-DP
286 * the non-DP HPD could block the workqueue on a mode config
287 * mutex getting, that userspace may have taken. However
288 * userspace is waiting on the DP workqueue to run which is
289 * blocked behind the non-DP one.
291 struct workqueue_struct *dp_wq;
294 #define I915_GEM_GPU_DOMAINS \
295 (I915_GEM_DOMAIN_RENDER | \
296 I915_GEM_DOMAIN_SAMPLER | \
297 I915_GEM_DOMAIN_COMMAND | \
298 I915_GEM_DOMAIN_INSTRUCTION | \
299 I915_GEM_DOMAIN_VERTEX)
301 #define for_each_pipe(__dev_priv, __p) \
302 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
303 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
304 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
305 for_each_if ((__mask) & (1 << (__p)))
306 #define for_each_plane(__dev_priv, __pipe, __p) \
308 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
310 #define for_each_sprite(__dev_priv, __p, __s) \
312 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
315 #define for_each_port_masked(__port, __ports_mask) \
316 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
317 for_each_if ((__ports_mask) & (1 << (__port)))
319 #define for_each_crtc(dev, crtc) \
320 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
322 #define for_each_intel_plane(dev, intel_plane) \
323 list_for_each_entry(intel_plane, \
324 &dev->mode_config.plane_list, \
327 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
328 list_for_each_entry(intel_plane, \
329 &(dev)->mode_config.plane_list, \
331 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
333 #define for_each_intel_crtc(dev, intel_crtc) \
334 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
336 #define for_each_intel_encoder(dev, intel_encoder) \
337 list_for_each_entry(intel_encoder, \
338 &(dev)->mode_config.encoder_list, \
341 #define for_each_intel_connector(dev, intel_connector) \
342 list_for_each_entry(intel_connector, \
343 &dev->mode_config.connector_list, \
346 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
347 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
348 for_each_if ((intel_encoder)->base.crtc == (__crtc))
350 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
351 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
352 for_each_if ((intel_connector)->base.encoder == (__encoder))
354 #define for_each_power_domain(domain, mask) \
355 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
356 for_each_if ((1 << (domain)) & (mask))
358 struct drm_i915_private;
359 struct i915_mm_struct;
360 struct i915_mmu_object;
362 struct drm_i915_file_private {
363 struct drm_i915_private *dev_priv;
364 struct drm_file *file;
368 struct list_head request_list;
369 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
370 * chosen to prevent the CPU getting more than a frame ahead of the GPU
371 * (when using lax throttling for the frontbuffer). We also use it to
372 * offer free GPU waitboosts for severely congested workloads.
374 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
376 struct idr context_idr;
378 struct intel_rps_client {
379 struct list_head link;
383 unsigned int bsd_ring;
386 /* Used by dp and fdi links */
387 struct intel_link_m_n {
395 void intel_link_compute_m_n(int bpp, int nlanes,
396 int pixel_clock, int link_clock,
397 struct intel_link_m_n *m_n);
399 /* Interface history:
402 * 1.2: Add Power Management
403 * 1.3: Add vblank support
404 * 1.4: Fix cmdbuffer path, add heap destroy
405 * 1.5: Add vblank pipe configuration
406 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
407 * - Support vertical blank on secondary display pipe
409 #define DRIVER_MAJOR 1
410 #define DRIVER_MINOR 6
411 #define DRIVER_PATCHLEVEL 0
413 #define WATCH_LISTS 0
415 struct opregion_header;
416 struct opregion_acpi;
417 struct opregion_swsci;
418 struct opregion_asle;
420 struct intel_opregion {
421 struct opregion_header *header;
422 struct opregion_acpi *acpi;
423 struct opregion_swsci *swsci;
424 u32 swsci_gbda_sub_functions;
425 u32 swsci_sbcb_sub_functions;
426 struct opregion_asle *asle;
431 struct work_struct asle_work;
433 #define OPREGION_SIZE (8*1024)
435 struct intel_overlay;
436 struct intel_overlay_error_state;
438 #define I915_FENCE_REG_NONE -1
439 #define I915_MAX_NUM_FENCES 32
440 /* 32 fences + sign bit for FENCE_REG_NONE */
441 #define I915_MAX_NUM_FENCE_BITS 6
443 struct drm_i915_fence_reg {
444 struct list_head lru_list;
445 struct drm_i915_gem_object *obj;
449 struct sdvo_device_mapping {
458 struct intel_display_error_state;
460 struct drm_i915_error_state {
469 /* Generic register state */
477 u32 error; /* gen6+ */
478 u32 err_int; /* gen7 */
479 u32 fault_data0; /* gen8, gen9 */
480 u32 fault_data1; /* gen8, gen9 */
486 u32 extra_instdone[I915_NUM_INSTDONE_REG];
487 u64 fence[I915_MAX_NUM_FENCES];
488 struct intel_overlay_error_state *overlay;
489 struct intel_display_error_state *display;
490 struct drm_i915_error_object *semaphore_obj;
492 struct drm_i915_error_ring {
494 /* Software tracked state */
497 enum intel_ring_hangcheck_action hangcheck_action;
500 /* our own tracking of ring head and tail */
505 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
524 u32 rc_psmi; /* sleep state */
525 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
527 struct drm_i915_error_object {
531 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
533 struct drm_i915_error_object *wa_ctx;
535 struct drm_i915_error_request {
550 char comm[TASK_COMM_LEN];
551 } ring[I915_NUM_ENGINES];
553 struct drm_i915_error_buffer {
556 u32 rseqno[I915_NUM_ENGINES], wseqno;
560 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
568 } **active_bo, **pinned_bo;
570 u32 *active_bo_count, *pinned_bo_count;
574 struct intel_connector;
575 struct intel_encoder;
576 struct intel_crtc_state;
577 struct intel_initial_plane_config;
582 struct drm_i915_display_funcs {
583 int (*get_display_clock_speed)(struct drm_device *dev);
584 int (*get_fifo_size)(struct drm_device *dev, int plane);
585 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
586 int (*compute_intermediate_wm)(struct drm_device *dev,
587 struct intel_crtc *intel_crtc,
588 struct intel_crtc_state *newstate);
589 void (*initial_watermarks)(struct intel_crtc_state *cstate);
590 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
591 void (*update_wm)(struct drm_crtc *crtc);
592 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
593 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
594 /* Returns the active state of the crtc, and if the crtc is active,
595 * fills out the pipe-config with the hw state. */
596 bool (*get_pipe_config)(struct intel_crtc *,
597 struct intel_crtc_state *);
598 void (*get_initial_plane_config)(struct intel_crtc *,
599 struct intel_initial_plane_config *);
600 int (*crtc_compute_clock)(struct intel_crtc *crtc,
601 struct intel_crtc_state *crtc_state);
602 void (*crtc_enable)(struct drm_crtc *crtc);
603 void (*crtc_disable)(struct drm_crtc *crtc);
604 void (*audio_codec_enable)(struct drm_connector *connector,
605 struct intel_encoder *encoder,
606 const struct drm_display_mode *adjusted_mode);
607 void (*audio_codec_disable)(struct intel_encoder *encoder);
608 void (*fdi_link_train)(struct drm_crtc *crtc);
609 void (*init_clock_gating)(struct drm_device *dev);
610 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
611 struct drm_framebuffer *fb,
612 struct drm_i915_gem_object *obj,
613 struct drm_i915_gem_request *req,
615 void (*hpd_irq_setup)(struct drm_device *dev);
616 /* clock updates for mode set */
618 /* render clock increase/decrease */
619 /* display clock increase/decrease */
620 /* pll clock increase/decrease */
622 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
623 void (*load_luts)(struct drm_crtc_state *crtc_state);
626 enum forcewake_domain_id {
627 FW_DOMAIN_ID_RENDER = 0,
628 FW_DOMAIN_ID_BLITTER,
634 enum forcewake_domains {
635 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
636 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
637 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
638 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
643 #define FW_REG_READ (1)
644 #define FW_REG_WRITE (2)
646 enum forcewake_domains
647 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
648 i915_reg_t reg, unsigned int op);
650 struct intel_uncore_funcs {
651 void (*force_wake_get)(struct drm_i915_private *dev_priv,
652 enum forcewake_domains domains);
653 void (*force_wake_put)(struct drm_i915_private *dev_priv,
654 enum forcewake_domains domains);
656 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
657 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
658 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
659 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
661 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
662 uint8_t val, bool trace);
663 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
664 uint16_t val, bool trace);
665 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
666 uint32_t val, bool trace);
667 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
668 uint64_t val, bool trace);
671 struct intel_uncore {
672 spinlock_t lock; /** lock is also taken in irq contexts. */
674 struct intel_uncore_funcs funcs;
677 enum forcewake_domains fw_domains;
679 struct intel_uncore_forcewake_domain {
680 struct drm_i915_private *i915;
681 enum forcewake_domain_id id;
682 enum forcewake_domains mask;
684 struct hrtimer timer;
691 } fw_domain[FW_DOMAIN_ID_COUNT];
693 int unclaimed_mmio_check;
696 /* Iterate over initialised fw domains */
697 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
698 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
699 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
701 for_each_if ((mask__) & (domain__)->mask)
703 #define for_each_fw_domain(domain__, dev_priv__) \
704 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
706 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
707 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
708 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
711 struct work_struct work;
713 uint32_t *dmc_payload;
714 uint32_t dmc_fw_size;
717 i915_reg_t mmioaddr[8];
718 uint32_t mmiodata[8];
720 uint32_t allowed_dc_mask;
723 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
724 func(is_mobile) sep \
727 func(is_i945gm) sep \
729 func(need_gfx_hws) sep \
731 func(is_pineview) sep \
732 func(is_broadwater) sep \
733 func(is_crestline) sep \
734 func(is_ivybridge) sep \
735 func(is_valleyview) sep \
736 func(is_cherryview) sep \
737 func(is_haswell) sep \
738 func(is_skylake) sep \
739 func(is_broxton) sep \
740 func(is_kabylake) sep \
741 func(is_preliminary) sep \
743 func(has_pipe_cxsr) sep \
744 func(has_hotplug) sep \
745 func(cursor_needs_physical) sep \
746 func(has_overlay) sep \
747 func(overlay_needs_physical) sep \
748 func(supports_tv) sep \
750 func(has_snoop) sep \
754 #define DEFINE_FLAG(name) u8 name:1
755 #define SEP_SEMICOLON ;
757 struct intel_device_info {
758 u32 display_mmio_offset;
761 u8 num_sprites[I915_MAX_PIPES];
763 u8 ring_mask; /* Rings supported by the HW */
764 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
765 /* Register offsets for the various display pipes and transcoders */
766 int pipe_offsets[I915_MAX_TRANSCODERS];
767 int trans_offsets[I915_MAX_TRANSCODERS];
768 int palette_offsets[I915_MAX_PIPES];
769 int cursor_offsets[I915_MAX_PIPES];
771 /* Slice/subslice/EU info */
774 u8 subslice_per_slice;
777 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
780 u8 has_subslice_pg:1;
784 u16 degamma_lut_size;
792 enum i915_cache_level {
794 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
795 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
796 caches, eg sampler/render caches, and the
797 large Last-Level-Cache. LLC is coherent with
798 the CPU, but L3 is only visible to the GPU. */
799 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
802 struct i915_ctx_hang_stats {
803 /* This context had batch pending when hang was declared */
804 unsigned batch_pending;
806 /* This context had batch active when hang was declared */
807 unsigned batch_active;
809 /* Time when this context was last blamed for a GPU reset */
810 unsigned long guilty_ts;
812 /* If the contexts causes a second GPU hang within this time,
813 * it is permanently banned from submitting any more work.
815 unsigned long ban_period_seconds;
817 /* This context is banned to submit more work */
821 /* This must match up with the value previously used for execbuf2.rsvd1. */
822 #define DEFAULT_CONTEXT_HANDLE 0
824 #define CONTEXT_NO_ZEROMAP (1<<0)
826 * struct intel_context - as the name implies, represents a context.
827 * @ref: reference count.
828 * @user_handle: userspace tracking identity for this context.
829 * @remap_slice: l3 row remapping information.
830 * @flags: context specific flags:
831 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
832 * @file_priv: filp associated with this context (NULL for global default
834 * @hang_stats: information about the role of this context in possible GPU
836 * @ppgtt: virtual memory space used by this context.
837 * @legacy_hw_ctx: render context backing object and whether it is correctly
838 * initialized (legacy ring submission mechanism only).
839 * @link: link in the global list of contexts.
841 * Contexts are memory images used by the hardware to store copies of their
844 struct intel_context {
848 struct drm_i915_private *i915;
850 struct drm_i915_file_private *file_priv;
851 struct i915_ctx_hang_stats hang_stats;
852 struct i915_hw_ppgtt *ppgtt;
854 /* Unique identifier for this context, used by the hw for tracking */
857 /* Legacy ring buffer submission */
859 struct drm_i915_gem_object *rcs_state;
865 struct drm_i915_gem_object *state;
866 struct intel_ringbuffer *ringbuf;
868 struct i915_vma *lrc_vma;
870 uint32_t *lrc_reg_state;
872 } engine[I915_NUM_ENGINES];
874 struct list_head link;
886 /* This is always the inner lock when overlapping with struct_mutex and
887 * it's the outer lock when overlapping with stolen_lock. */
890 unsigned int possible_framebuffer_bits;
891 unsigned int busy_bits;
892 unsigned int visible_pipes_mask;
893 struct intel_crtc *crtc;
895 struct drm_mm_node compressed_fb;
896 struct drm_mm_node *compressed_llb;
903 struct intel_fbc_state_cache {
905 unsigned int mode_flags;
906 uint32_t hsw_bdw_pixel_rate;
910 unsigned int rotation;
918 uint32_t pixel_format;
921 unsigned int tiling_mode;
925 struct intel_fbc_reg_params {
929 unsigned int fence_y_offset;
934 uint32_t pixel_format;
942 struct intel_fbc_work {
944 u32 scheduled_vblank;
945 struct work_struct work;
948 const char *no_fbc_reason;
952 * HIGH_RR is the highest eDP panel refresh rate read from EDID
953 * LOW_RR is the lowest eDP panel refresh rate found from EDID
954 * parsing for same resolution.
956 enum drrs_refresh_rate_type {
959 DRRS_MAX_RR, /* RR count */
962 enum drrs_support_type {
963 DRRS_NOT_SUPPORTED = 0,
964 STATIC_DRRS_SUPPORT = 1,
965 SEAMLESS_DRRS_SUPPORT = 2
971 struct delayed_work work;
973 unsigned busy_frontbuffer_bits;
974 enum drrs_refresh_rate_type refresh_rate_type;
975 enum drrs_support_type type;
982 struct intel_dp *enabled;
984 struct delayed_work work;
985 unsigned busy_frontbuffer_bits;
992 PCH_NONE = 0, /* No PCH present */
993 PCH_IBX, /* Ibexpeak PCH */
994 PCH_CPT, /* Cougarpoint PCH */
995 PCH_LPT, /* Lynxpoint PCH */
996 PCH_SPT, /* Sunrisepoint PCH */
1000 enum intel_sbi_destination {
1005 #define QUIRK_PIPEA_FORCE (1<<0)
1006 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1007 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1008 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1009 #define QUIRK_PIPEB_FORCE (1<<4)
1010 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1013 struct intel_fbc_work;
1015 struct intel_gmbus {
1016 struct i2c_adapter adapter;
1017 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1020 i915_reg_t gpio_reg;
1021 struct i2c_algo_bit_data bit_algo;
1022 struct drm_i915_private *dev_priv;
1025 struct i915_suspend_saved_registers {
1028 u32 savePP_ON_DELAYS;
1029 u32 savePP_OFF_DELAYS;
1034 u32 saveFBC_CONTROL;
1035 u32 saveCACHE_MODE_0;
1036 u32 saveMI_ARB_STATE;
1040 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1041 u32 savePCH_PORT_HOTPLUG;
1045 struct vlv_s0ix_state {
1052 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1053 u32 media_max_req_count;
1054 u32 gfx_max_req_count;
1080 u32 rp_down_timeout;
1086 /* Display 1 CZ domain */
1091 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1093 /* GT SA CZ domain */
1100 /* Display 2 CZ domain */
1104 u32 clock_gate_dis2;
1107 struct intel_rps_ei {
1113 struct intel_gen6_power_mgmt {
1115 * work, interrupts_enabled and pm_iir are protected by
1116 * dev_priv->irq_lock
1118 struct work_struct work;
1119 bool interrupts_enabled;
1122 /* Frequencies are stored in potentially platform dependent multiples.
1123 * In other words, *_freq needs to be multiplied by X to be interesting.
1124 * Soft limits are those which are used for the dynamic reclocking done
1125 * by the driver (raise frequencies under heavy loads, and lower for
1126 * lighter loads). Hard limits are those imposed by the hardware.
1128 * A distinction is made for overclocking, which is never enabled by
1129 * default, and is considered to be above the hard limit if it's
1132 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1133 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1134 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1135 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1136 u8 min_freq; /* AKA RPn. Minimum frequency */
1137 u8 idle_freq; /* Frequency to request when we are idle */
1138 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1139 u8 rp1_freq; /* "less than" RP0 power/freqency */
1140 u8 rp0_freq; /* Non-overclocked max frequency. */
1141 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1143 u8 up_threshold; /* Current %busy required to uplock */
1144 u8 down_threshold; /* Current %busy required to downclock */
1147 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1149 spinlock_t client_lock;
1150 struct list_head clients;
1154 struct delayed_work delayed_resume_work;
1157 struct intel_rps_client semaphores, mmioflips;
1159 /* manual wa residency calculations */
1160 struct intel_rps_ei up_ei, down_ei;
1163 * Protects RPS/RC6 register access and PCU communication.
1164 * Must be taken after struct_mutex if nested. Note that
1165 * this lock may be held for long periods of time when
1166 * talking to hw - so only take it when talking to hw!
1168 struct mutex hw_lock;
1171 /* defined intel_pm.c */
1172 extern spinlock_t mchdev_lock;
1174 struct intel_ilk_power_mgmt {
1182 unsigned long last_time1;
1183 unsigned long chipset_power;
1186 unsigned long gfx_power;
1193 struct drm_i915_private;
1194 struct i915_power_well;
1196 struct i915_power_well_ops {
1198 * Synchronize the well's hw state to match the current sw state, for
1199 * example enable/disable it based on the current refcount. Called
1200 * during driver init and resume time, possibly after first calling
1201 * the enable/disable handlers.
1203 void (*sync_hw)(struct drm_i915_private *dev_priv,
1204 struct i915_power_well *power_well);
1206 * Enable the well and resources that depend on it (for example
1207 * interrupts located on the well). Called after the 0->1 refcount
1210 void (*enable)(struct drm_i915_private *dev_priv,
1211 struct i915_power_well *power_well);
1213 * Disable the well and resources that depend on it. Called after
1214 * the 1->0 refcount transition.
1216 void (*disable)(struct drm_i915_private *dev_priv,
1217 struct i915_power_well *power_well);
1218 /* Returns the hw enabled state. */
1219 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1220 struct i915_power_well *power_well);
1223 /* Power well structure for haswell */
1224 struct i915_power_well {
1227 /* power well enable/disable usage count */
1229 /* cached hw enabled state */
1231 unsigned long domains;
1233 const struct i915_power_well_ops *ops;
1236 struct i915_power_domains {
1238 * Power wells needed for initialization at driver init and suspend
1239 * time are on. They are kept on until after the first modeset.
1243 int power_well_count;
1246 int domain_use_count[POWER_DOMAIN_NUM];
1247 struct i915_power_well *power_wells;
1250 #define MAX_L3_SLICES 2
1251 struct intel_l3_parity {
1252 u32 *remap_info[MAX_L3_SLICES];
1253 struct work_struct error_work;
1257 struct i915_gem_mm {
1258 /** Memory allocator for GTT stolen memory */
1259 struct drm_mm stolen;
1260 /** Protects the usage of the GTT stolen memory allocator. This is
1261 * always the inner lock when overlapping with struct_mutex. */
1262 struct mutex stolen_lock;
1264 /** List of all objects in gtt_space. Used to restore gtt
1265 * mappings on resume */
1266 struct list_head bound_list;
1268 * List of objects which are not bound to the GTT (thus
1269 * are idle and not used by the GPU) but still have
1270 * (presumably uncached) pages still attached.
1272 struct list_head unbound_list;
1274 /** Usable portion of the GTT for GEM */
1275 unsigned long stolen_base; /* limited to low memory (32-bit) */
1277 /** PPGTT used for aliasing the PPGTT with the GTT */
1278 struct i915_hw_ppgtt *aliasing_ppgtt;
1280 struct notifier_block oom_notifier;
1281 struct notifier_block vmap_notifier;
1282 struct shrinker shrinker;
1283 bool shrinker_no_lock_stealing;
1285 /** LRU list of objects with fence regs on them. */
1286 struct list_head fence_list;
1289 * We leave the user IRQ off as much as possible,
1290 * but this means that requests will finish and never
1291 * be retired once the system goes idle. Set a timer to
1292 * fire periodically while the ring is running. When it
1293 * fires, go retire requests.
1295 struct delayed_work retire_work;
1298 * When we detect an idle GPU, we want to turn on
1299 * powersaving features. So once we see that there
1300 * are no more requests outstanding and no more
1301 * arrive within a small period of time, we fire
1302 * off the idle_work.
1304 struct delayed_work idle_work;
1307 * Are we in a non-interruptible section of code like
1313 * Is the GPU currently considered idle, or busy executing userspace
1314 * requests? Whilst idle, we attempt to power down the hardware and
1315 * display clocks. In order to reduce the effect on performance, there
1316 * is a slight delay before we do so.
1320 /* the indicator for dispatch video commands on two BSD rings */
1321 unsigned int bsd_ring_dispatch_index;
1323 /** Bit 6 swizzling required for X tiling */
1324 uint32_t bit_6_swizzle_x;
1325 /** Bit 6 swizzling required for Y tiling */
1326 uint32_t bit_6_swizzle_y;
1328 /* accounting, useful for userland debugging */
1329 spinlock_t object_stat_lock;
1330 size_t object_memory;
1334 struct drm_i915_error_state_buf {
1335 struct drm_i915_private *i915;
1344 struct i915_error_state_file_priv {
1345 struct drm_device *dev;
1346 struct drm_i915_error_state *error;
1349 struct i915_gpu_error {
1350 /* For hangcheck timer */
1351 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1352 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1353 /* Hang gpu twice in this window and your context gets banned */
1354 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1356 struct workqueue_struct *hangcheck_wq;
1357 struct delayed_work hangcheck_work;
1359 /* For reset and error_state handling. */
1361 /* Protected by the above dev->gpu_error.lock. */
1362 struct drm_i915_error_state *first_error;
1364 unsigned long missed_irq_rings;
1367 * State variable controlling the reset flow and count
1369 * This is a counter which gets incremented when reset is triggered,
1370 * and again when reset has been handled. So odd values (lowest bit set)
1371 * means that reset is in progress and even values that
1372 * (reset_counter >> 1):th reset was successfully completed.
1374 * If reset is not completed succesfully, the I915_WEDGE bit is
1375 * set meaning that hardware is terminally sour and there is no
1376 * recovery. All waiters on the reset_queue will be woken when
1379 * This counter is used by the wait_seqno code to notice that reset
1380 * event happened and it needs to restart the entire ioctl (since most
1381 * likely the seqno it waited for won't ever signal anytime soon).
1383 * This is important for lock-free wait paths, where no contended lock
1384 * naturally enforces the correct ordering between the bail-out of the
1385 * waiter and the gpu reset work code.
1387 atomic_t reset_counter;
1389 #define I915_RESET_IN_PROGRESS_FLAG 1
1390 #define I915_WEDGED (1 << 31)
1393 * Waitqueue to signal when the reset has completed. Used by clients
1394 * that wait for dev_priv->mm.wedged to settle.
1396 wait_queue_head_t reset_queue;
1398 /* Userspace knobs for gpu hang simulation;
1399 * combines both a ring mask, and extra flags
1402 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1403 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1405 /* For missed irq/seqno simulation. */
1406 unsigned int test_irq_rings;
1409 enum modeset_restore {
1410 MODESET_ON_LID_OPEN,
1415 #define DP_AUX_A 0x40
1416 #define DP_AUX_B 0x10
1417 #define DP_AUX_C 0x20
1418 #define DP_AUX_D 0x30
1420 #define DDC_PIN_B 0x05
1421 #define DDC_PIN_C 0x04
1422 #define DDC_PIN_D 0x06
1424 struct ddi_vbt_port_info {
1426 * This is an index in the HDMI/DVI DDI buffer translation table.
1427 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1428 * populate this field.
1430 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1431 uint8_t hdmi_level_shift;
1433 uint8_t supports_dvi:1;
1434 uint8_t supports_hdmi:1;
1435 uint8_t supports_dp:1;
1437 uint8_t alternate_aux_channel;
1438 uint8_t alternate_ddc_pin;
1440 uint8_t dp_boost_level;
1441 uint8_t hdmi_boost_level;
1444 enum psr_lines_to_wait {
1445 PSR_0_LINES_TO_WAIT = 0,
1447 PSR_4_LINES_TO_WAIT,
1451 struct intel_vbt_data {
1452 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1453 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1456 unsigned int int_tv_support:1;
1457 unsigned int lvds_dither:1;
1458 unsigned int lvds_vbt:1;
1459 unsigned int int_crt_support:1;
1460 unsigned int lvds_use_ssc:1;
1461 unsigned int display_clock_mode:1;
1462 unsigned int fdi_rx_polarity_inverted:1;
1463 unsigned int panel_type:4;
1465 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1467 enum drrs_support_type drrs_type;
1478 struct edp_power_seq pps;
1483 bool require_aux_wakeup;
1485 enum psr_lines_to_wait lines_to_wait;
1486 int tp1_wakeup_time;
1487 int tp2_tp3_wakeup_time;
1493 bool active_low_pwm;
1494 u8 min_brightness; /* min_brightness/255 of max */
1495 enum intel_backlight_type type;
1501 struct mipi_config *config;
1502 struct mipi_pps_data *pps;
1506 const u8 *sequence[MIPI_SEQ_MAX];
1512 union child_device_config *child_dev;
1514 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1515 struct sdvo_device_mapping sdvo_mappings[2];
1518 enum intel_ddb_partitioning {
1520 INTEL_DDB_PART_5_6, /* IVB+ */
1523 struct intel_wm_level {
1531 struct ilk_wm_values {
1532 uint32_t wm_pipe[3];
1534 uint32_t wm_lp_spr[3];
1535 uint32_t wm_linetime[3];
1537 enum intel_ddb_partitioning partitioning;
1540 struct vlv_pipe_wm {
1551 struct vlv_wm_values {
1552 struct vlv_pipe_wm pipe[3];
1553 struct vlv_sr_wm sr;
1563 struct skl_ddb_entry {
1564 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1567 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1569 return entry->end - entry->start;
1572 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1573 const struct skl_ddb_entry *e2)
1575 if (e1->start == e2->start && e1->end == e2->end)
1581 struct skl_ddb_allocation {
1582 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1583 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1584 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1587 struct skl_wm_values {
1588 bool dirty[I915_MAX_PIPES];
1589 struct skl_ddb_allocation ddb;
1590 uint32_t wm_linetime[I915_MAX_PIPES];
1591 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1592 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1595 struct skl_wm_level {
1596 bool plane_en[I915_MAX_PLANES];
1597 uint16_t plane_res_b[I915_MAX_PLANES];
1598 uint8_t plane_res_l[I915_MAX_PLANES];
1602 * This struct helps tracking the state needed for runtime PM, which puts the
1603 * device in PCI D3 state. Notice that when this happens, nothing on the
1604 * graphics device works, even register access, so we don't get interrupts nor
1607 * Every piece of our code that needs to actually touch the hardware needs to
1608 * either call intel_runtime_pm_get or call intel_display_power_get with the
1609 * appropriate power domain.
1611 * Our driver uses the autosuspend delay feature, which means we'll only really
1612 * suspend if we stay with zero refcount for a certain amount of time. The
1613 * default value is currently very conservative (see intel_runtime_pm_enable), but
1614 * it can be changed with the standard runtime PM files from sysfs.
1616 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1617 * goes back to false exactly before we reenable the IRQs. We use this variable
1618 * to check if someone is trying to enable/disable IRQs while they're supposed
1619 * to be disabled. This shouldn't happen and we'll print some error messages in
1622 * For more, read the Documentation/power/runtime_pm.txt.
1624 struct i915_runtime_pm {
1625 atomic_t wakeref_count;
1626 atomic_t atomic_seq;
1631 enum intel_pipe_crc_source {
1632 INTEL_PIPE_CRC_SOURCE_NONE,
1633 INTEL_PIPE_CRC_SOURCE_PLANE1,
1634 INTEL_PIPE_CRC_SOURCE_PLANE2,
1635 INTEL_PIPE_CRC_SOURCE_PF,
1636 INTEL_PIPE_CRC_SOURCE_PIPE,
1637 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1638 INTEL_PIPE_CRC_SOURCE_TV,
1639 INTEL_PIPE_CRC_SOURCE_DP_B,
1640 INTEL_PIPE_CRC_SOURCE_DP_C,
1641 INTEL_PIPE_CRC_SOURCE_DP_D,
1642 INTEL_PIPE_CRC_SOURCE_AUTO,
1643 INTEL_PIPE_CRC_SOURCE_MAX,
1646 struct intel_pipe_crc_entry {
1651 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1652 struct intel_pipe_crc {
1654 bool opened; /* exclusive access to the result file */
1655 struct intel_pipe_crc_entry *entries;
1656 enum intel_pipe_crc_source source;
1658 wait_queue_head_t wq;
1661 struct i915_frontbuffer_tracking {
1665 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1672 struct i915_wa_reg {
1675 /* bitmask representing WA bits */
1680 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1681 * allowing it for RCS as we don't foresee any requirement of having
1682 * a whitelist for other engines. When it is really required for
1683 * other engines then the limit need to be increased.
1685 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1687 struct i915_workarounds {
1688 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1690 u32 hw_whitelist_count[I915_NUM_ENGINES];
1693 struct i915_virtual_gpu {
1697 struct i915_execbuffer_params {
1698 struct drm_device *dev;
1699 struct drm_file *file;
1700 uint32_t dispatch_flags;
1701 uint32_t args_batch_start_offset;
1702 uint64_t batch_obj_vm_offset;
1703 struct intel_engine_cs *engine;
1704 struct drm_i915_gem_object *batch_obj;
1705 struct intel_context *ctx;
1706 struct drm_i915_gem_request *request;
1709 /* used in computing the new watermarks state */
1710 struct intel_wm_config {
1711 unsigned int num_pipes_active;
1712 bool sprites_enabled;
1713 bool sprites_scaled;
1716 struct drm_i915_private {
1717 struct drm_device *dev;
1718 struct kmem_cache *objects;
1719 struct kmem_cache *vmas;
1720 struct kmem_cache *requests;
1722 const struct intel_device_info info;
1724 int relative_constants_mode;
1728 struct intel_uncore uncore;
1730 struct i915_virtual_gpu vgpu;
1732 struct intel_guc guc;
1734 struct intel_csr csr;
1736 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1738 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1739 * controller on different i2c buses. */
1740 struct mutex gmbus_mutex;
1743 * Base address of the gmbus and gpio block.
1745 uint32_t gpio_mmio_base;
1747 /* MMIO base address for MIPI regs */
1748 uint32_t mipi_mmio_base;
1750 uint32_t psr_mmio_base;
1752 wait_queue_head_t gmbus_wait_queue;
1754 struct pci_dev *bridge_dev;
1755 struct intel_engine_cs engine[I915_NUM_ENGINES];
1756 struct drm_i915_gem_object *semaphore_obj;
1757 uint32_t last_seqno, next_seqno;
1759 struct drm_dma_handle *status_page_dmah;
1760 struct resource mch_res;
1762 /* protects the irq masks */
1763 spinlock_t irq_lock;
1765 /* protects the mmio flip data */
1766 spinlock_t mmio_flip_lock;
1768 bool display_irqs_enabled;
1770 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1771 struct pm_qos_request pm_qos;
1773 /* Sideband mailbox protection */
1774 struct mutex sb_lock;
1776 /** Cached value of IMR to avoid reads in updating the bitfield */
1779 u32 de_irq_mask[I915_MAX_PIPES];
1784 u32 pipestat_irq_mask[I915_MAX_PIPES];
1786 struct i915_hotplug hotplug;
1787 struct intel_fbc fbc;
1788 struct i915_drrs drrs;
1789 struct intel_opregion opregion;
1790 struct intel_vbt_data vbt;
1792 bool preserve_bios_swizzle;
1795 struct intel_overlay *overlay;
1797 /* backlight registers and fields in struct intel_panel */
1798 struct mutex backlight_lock;
1801 bool no_aux_handshake;
1803 /* protects panel power sequencer state */
1804 struct mutex pps_mutex;
1806 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1807 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1809 unsigned int fsb_freq, mem_freq, is_ddr3;
1810 unsigned int skl_boot_cdclk;
1811 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1812 unsigned int max_dotclk_freq;
1813 unsigned int rawclk_freq;
1814 unsigned int hpll_freq;
1815 unsigned int czclk_freq;
1818 * wq - Driver workqueue for GEM.
1820 * NOTE: Work items scheduled here are not allowed to grab any modeset
1821 * locks, for otherwise the flushing done in the pageflip code will
1822 * result in deadlocks.
1824 struct workqueue_struct *wq;
1826 /* Display functions */
1827 struct drm_i915_display_funcs display;
1829 /* PCH chipset type */
1830 enum intel_pch pch_type;
1831 unsigned short pch_id;
1833 unsigned long quirks;
1835 enum modeset_restore modeset_restore;
1836 struct mutex modeset_restore_lock;
1837 struct drm_atomic_state *modeset_restore_state;
1839 struct list_head vm_list; /* Global list of all address spaces */
1840 struct i915_ggtt ggtt; /* VM representing the global address space */
1842 struct i915_gem_mm mm;
1843 DECLARE_HASHTABLE(mm_structs, 7);
1844 struct mutex mm_lock;
1846 /* The hw wants to have a stable context identifier for the lifetime
1847 * of the context (for OA, PASID, faults, etc). This is limited
1848 * in execlists to 21 bits.
1850 struct ida context_hw_ida;
1851 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1853 /* Kernel Modesetting */
1855 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1856 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1857 wait_queue_head_t pending_flip_queue;
1859 #ifdef CONFIG_DEBUG_FS
1860 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1863 /* dpll and cdclk state is protected by connection_mutex */
1864 int num_shared_dpll;
1865 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1866 const struct intel_dpll_mgr *dpll_mgr;
1869 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1870 * Must be global rather than per dpll, because on some platforms
1871 * plls share registers.
1873 struct mutex dpll_lock;
1875 unsigned int active_crtcs;
1876 unsigned int min_pixclk[I915_MAX_PIPES];
1878 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1880 struct i915_workarounds workarounds;
1882 struct i915_frontbuffer_tracking fb_tracking;
1886 bool mchbar_need_disable;
1888 struct intel_l3_parity l3_parity;
1890 /* Cannot be determined by PCIID. You must always read a register. */
1893 /* gen6+ rps state */
1894 struct intel_gen6_power_mgmt rps;
1896 /* ilk-only ips/rps state. Everything in here is protected by the global
1897 * mchdev_lock in intel_pm.c */
1898 struct intel_ilk_power_mgmt ips;
1900 struct i915_power_domains power_domains;
1902 struct i915_psr psr;
1904 struct i915_gpu_error gpu_error;
1906 struct drm_i915_gem_object *vlv_pctx;
1908 #ifdef CONFIG_DRM_FBDEV_EMULATION
1909 /* list of fbdev register on this device */
1910 struct intel_fbdev *fbdev;
1911 struct work_struct fbdev_suspend_work;
1914 struct drm_property *broadcast_rgb_property;
1915 struct drm_property *force_audio_property;
1917 /* hda/i915 audio component */
1918 struct i915_audio_component *audio_component;
1919 bool audio_component_registered;
1921 * av_mutex - mutex for audio/video sync
1924 struct mutex av_mutex;
1926 uint32_t hw_context_size;
1927 struct list_head context_list;
1931 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1932 u32 chv_phy_control;
1934 * Shadows for CHV DPLL_MD regs to keep the state
1935 * checker somewhat working in the presence hardware
1936 * crappiness (can't read out DPLL_MD for pipes B & C).
1938 u32 chv_dpll_md[I915_MAX_PIPES];
1942 bool suspended_to_idle;
1943 struct i915_suspend_saved_registers regfile;
1944 struct vlv_s0ix_state vlv_s0ix_state;
1948 * Raw watermark latency values:
1949 * in 0.1us units for WM0,
1950 * in 0.5us units for WM1+.
1953 uint16_t pri_latency[5];
1955 uint16_t spr_latency[5];
1957 uint16_t cur_latency[5];
1959 * Raw watermark memory latency values
1960 * for SKL for all 8 levels
1963 uint16_t skl_latency[8];
1965 /* Committed wm config */
1966 struct intel_wm_config config;
1969 * The skl_wm_values structure is a bit too big for stack
1970 * allocation, so we keep the staging struct where we store
1971 * intermediate results here instead.
1973 struct skl_wm_values skl_results;
1975 /* current hardware state */
1977 struct ilk_wm_values hw;
1978 struct skl_wm_values skl_hw;
1979 struct vlv_wm_values vlv;
1985 * Should be held around atomic WM register writing; also
1986 * protects * intel_crtc->wm.active and
1987 * cstate->wm.need_postvbl_update.
1989 struct mutex wm_mutex;
1992 struct i915_runtime_pm pm;
1994 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1996 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1997 struct drm_i915_gem_execbuffer2 *args,
1998 struct list_head *vmas);
1999 int (*init_engines)(struct drm_device *dev);
2000 void (*cleanup_engine)(struct intel_engine_cs *engine);
2001 void (*stop_engine)(struct intel_engine_cs *engine);
2004 struct intel_context *kernel_context;
2006 /* perform PHY state sanity checks? */
2007 bool chv_phy_assert[2];
2009 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
2012 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2013 * will be rejected. Instead look for a better place.
2017 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2019 return dev->dev_private;
2022 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
2024 return to_i915(dev_get_drvdata(dev));
2027 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2029 return container_of(guc, struct drm_i915_private, guc);
2032 /* Simple iterator over all initialised engines */
2033 #define for_each_engine(engine__, dev_priv__) \
2034 for ((engine__) = &(dev_priv__)->engine[0]; \
2035 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2037 for_each_if (intel_engine_initialized(engine__))
2039 /* Iterator with engine_id */
2040 #define for_each_engine_id(engine__, dev_priv__, id__) \
2041 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2042 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2044 for_each_if (((id__) = (engine__)->id, \
2045 intel_engine_initialized(engine__)))
2047 /* Iterator over subset of engines selected by mask */
2048 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2049 for ((engine__) = &(dev_priv__)->engine[0]; \
2050 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2052 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2053 intel_engine_initialized(engine__))
2055 enum hdmi_force_audio {
2056 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2057 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2058 HDMI_AUDIO_AUTO, /* trust EDID */
2059 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2062 #define I915_GTT_OFFSET_NONE ((u32)-1)
2064 struct drm_i915_gem_object_ops {
2066 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2068 /* Interface between the GEM object and its backing storage.
2069 * get_pages() is called once prior to the use of the associated set
2070 * of pages before to binding them into the GTT, and put_pages() is
2071 * called after we no longer need them. As we expect there to be
2072 * associated cost with migrating pages between the backing storage
2073 * and making them available for the GPU (e.g. clflush), we may hold
2074 * onto the pages after they are no longer referenced by the GPU
2075 * in case they may be used again shortly (for example migrating the
2076 * pages to a different memory domain within the GTT). put_pages()
2077 * will therefore most likely be called when the object itself is
2078 * being released or under memory pressure (where we attempt to
2079 * reap pages for the shrinker).
2081 int (*get_pages)(struct drm_i915_gem_object *);
2082 void (*put_pages)(struct drm_i915_gem_object *);
2084 int (*dmabuf_export)(struct drm_i915_gem_object *);
2085 void (*release)(struct drm_i915_gem_object *);
2089 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2090 * considered to be the frontbuffer for the given plane interface-wise. This
2091 * doesn't mean that the hw necessarily already scans it out, but that any
2092 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2094 * We have one bit per pipe and per scanout plane type.
2096 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2097 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2098 #define INTEL_FRONTBUFFER_BITS \
2099 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2100 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2101 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2102 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2103 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2104 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2105 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2106 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2107 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2108 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2109 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2111 struct drm_i915_gem_object {
2112 struct drm_gem_object base;
2114 const struct drm_i915_gem_object_ops *ops;
2116 /** List of VMAs backed by this object */
2117 struct list_head vma_list;
2119 /** Stolen memory for this object, instead of being backed by shmem. */
2120 struct drm_mm_node *stolen;
2121 struct list_head global_list;
2123 struct list_head engine_list[I915_NUM_ENGINES];
2124 /** Used in execbuf to temporarily hold a ref */
2125 struct list_head obj_exec_link;
2127 struct list_head batch_pool_link;
2130 * This is set if the object is on the active lists (has pending
2131 * rendering and so a non-zero seqno), and is not set if it i s on
2132 * inactive (ready to be unbound) list.
2134 unsigned int active:I915_NUM_ENGINES;
2137 * This is set if the object has been written to since last bound
2140 unsigned int dirty:1;
2143 * Fence register bits (if any) for this object. Will be set
2144 * as needed when mapped into the GTT.
2145 * Protected by dev->struct_mutex.
2147 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2150 * Advice: are the backing pages purgeable?
2152 unsigned int madv:2;
2155 * Current tiling mode for the object.
2157 unsigned int tiling_mode:2;
2159 * Whether the tiling parameters for the currently associated fence
2160 * register have changed. Note that for the purposes of tracking
2161 * tiling changes we also treat the unfenced register, the register
2162 * slot that the object occupies whilst it executes a fenced
2163 * command (such as BLT on gen2/3), as a "fence".
2165 unsigned int fence_dirty:1;
2168 * Is the object at the current location in the gtt mappable and
2169 * fenceable? Used to avoid costly recalculations.
2171 unsigned int map_and_fenceable:1;
2174 * Whether the current gtt mapping needs to be mappable (and isn't just
2175 * mappable by accident). Track pin and fault separate for a more
2176 * accurate mappable working set.
2178 unsigned int fault_mappable:1;
2181 * Is the object to be mapped as read-only to the GPU
2182 * Only honoured if hardware has relevant pte bit
2184 unsigned long gt_ro:1;
2185 unsigned int cache_level:3;
2186 unsigned int cache_dirty:1;
2188 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2190 unsigned int pin_display;
2192 struct sg_table *pages;
2193 int pages_pin_count;
2195 struct scatterlist *sg;
2200 /** Breadcrumb of last rendering to the buffer.
2201 * There can only be one writer, but we allow for multiple readers.
2202 * If there is a writer that necessarily implies that all other
2203 * read requests are complete - but we may only be lazily clearing
2204 * the read requests. A read request is naturally the most recent
2205 * request on a ring, so we may have two different write and read
2206 * requests on one ring where the write request is older than the
2207 * read request. This allows for the CPU to read from an active
2208 * buffer by only waiting for the write to complete.
2210 struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES];
2211 struct drm_i915_gem_request *last_write_req;
2212 /** Breadcrumb of last fenced GPU access to the buffer. */
2213 struct drm_i915_gem_request *last_fenced_req;
2215 /** Current tiling stride for the object, if it's tiled. */
2218 /** References from framebuffers, locks out tiling changes. */
2219 unsigned long framebuffer_references;
2221 /** Record of address bit 17 of each page at last unbind. */
2222 unsigned long *bit_17;
2225 /** for phy allocated objects */
2226 struct drm_dma_handle *phys_handle;
2228 struct i915_gem_userptr {
2230 unsigned read_only :1;
2231 unsigned workers :4;
2232 #define I915_GEM_USERPTR_MAX_WORKERS 15
2234 struct i915_mm_struct *mm;
2235 struct i915_mmu_object *mmu_object;
2236 struct work_struct *work;
2240 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2242 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2243 struct drm_i915_gem_object *new,
2244 unsigned frontbuffer_bits);
2247 * Request queue structure.
2249 * The request queue allows us to note sequence numbers that have been emitted
2250 * and may be associated with active buffers to be retired.
2252 * By keeping this list, we can avoid having to do questionable sequence
2253 * number comparisons on buffer last_read|write_seqno. It also allows an
2254 * emission time to be associated with the request for tracking how far ahead
2255 * of the GPU the submission is.
2257 * The requests are reference counted, so upon creation they should have an
2258 * initial reference taken using kref_init
2260 struct drm_i915_gem_request {
2263 /** On Which ring this request was generated */
2264 struct drm_i915_private *i915;
2265 struct intel_engine_cs *engine;
2266 unsigned reset_counter;
2268 /** GEM sequence number associated with the previous request,
2269 * when the HWS breadcrumb is equal to this the GPU is processing
2274 /** GEM sequence number associated with this request,
2275 * when the HWS breadcrumb is equal or greater than this the GPU
2276 * has finished processing this request.
2280 /** Position in the ringbuffer of the start of the request */
2284 * Position in the ringbuffer of the start of the postfix.
2285 * This is required to calculate the maximum available ringbuffer
2286 * space without overwriting the postfix.
2290 /** Position in the ringbuffer of the end of the whole request */
2293 /** Preallocate space in the ringbuffer for the emitting the request */
2297 * Context and ring buffer related to this request
2298 * Contexts are refcounted, so when this request is associated with a
2299 * context, we must increment the context's refcount, to guarantee that
2300 * it persists while any request is linked to it. Requests themselves
2301 * are also refcounted, so the request will only be freed when the last
2302 * reference to it is dismissed, and the code in
2303 * i915_gem_request_free() will then decrement the refcount on the
2306 struct intel_context *ctx;
2307 struct intel_ringbuffer *ringbuf;
2310 * Context related to the previous request.
2311 * As the contexts are accessed by the hardware until the switch is
2312 * completed to a new context, the hardware may still be writing
2313 * to the context object after the breadcrumb is visible. We must
2314 * not unpin/unbind/prune that object whilst still active and so
2315 * we keep the previous context pinned until the following (this)
2316 * request is retired.
2318 struct intel_context *previous_context;
2320 /** Batch buffer related to this request if any (used for
2321 error state dump only) */
2322 struct drm_i915_gem_object *batch_obj;
2324 /** Time at which this request was emitted, in jiffies. */
2325 unsigned long emitted_jiffies;
2327 /** global list entry for this request */
2328 struct list_head list;
2330 struct drm_i915_file_private *file_priv;
2331 /** file_priv list entry for this request */
2332 struct list_head client_list;
2334 /** process identifier submitting this request */
2338 * The ELSP only accepts two elements at a time, so we queue
2339 * context/tail pairs on a given queue (ring->execlist_queue) until the
2340 * hardware is available. The queue serves a double purpose: we also use
2341 * it to keep track of the up to 2 contexts currently in the hardware
2342 * (usually one in execution and the other queued up by the GPU): We
2343 * only remove elements from the head of the queue when the hardware
2344 * informs us that an element has been completed.
2346 * All accesses to the queue are mediated by a spinlock
2347 * (ring->execlist_lock).
2350 /** Execlist link in the submission queue.*/
2351 struct list_head execlist_link;
2353 /** Execlists no. of times this request has been sent to the ELSP */
2356 /** Execlists context hardware id. */
2360 struct drm_i915_gem_request * __must_check
2361 i915_gem_request_alloc(struct intel_engine_cs *engine,
2362 struct intel_context *ctx);
2363 void i915_gem_request_free(struct kref *req_ref);
2364 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2365 struct drm_file *file);
2367 static inline uint32_t
2368 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2370 return req ? req->seqno : 0;
2373 static inline struct intel_engine_cs *
2374 i915_gem_request_get_engine(struct drm_i915_gem_request *req)
2376 return req ? req->engine : NULL;
2379 static inline struct drm_i915_gem_request *
2380 i915_gem_request_reference(struct drm_i915_gem_request *req)
2383 kref_get(&req->ref);
2388 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2390 kref_put(&req->ref, i915_gem_request_free);
2393 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2394 struct drm_i915_gem_request *src)
2397 i915_gem_request_reference(src);
2400 i915_gem_request_unreference(*pdst);
2406 * XXX: i915_gem_request_completed should be here but currently needs the
2407 * definition of i915_seqno_passed() which is below. It will be moved in
2408 * a later patch when the call to i915_seqno_passed() is obsoleted...
2412 * A command that requires special handling by the command parser.
2414 struct drm_i915_cmd_descriptor {
2416 * Flags describing how the command parser processes the command.
2418 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2419 * a length mask if not set
2420 * CMD_DESC_SKIP: The command is allowed but does not follow the
2421 * standard length encoding for the opcode range in
2423 * CMD_DESC_REJECT: The command is never allowed
2424 * CMD_DESC_REGISTER: The command should be checked against the
2425 * register whitelist for the appropriate ring
2426 * CMD_DESC_MASTER: The command is allowed if the submitting process
2430 #define CMD_DESC_FIXED (1<<0)
2431 #define CMD_DESC_SKIP (1<<1)
2432 #define CMD_DESC_REJECT (1<<2)
2433 #define CMD_DESC_REGISTER (1<<3)
2434 #define CMD_DESC_BITMASK (1<<4)
2435 #define CMD_DESC_MASTER (1<<5)
2438 * The command's unique identification bits and the bitmask to get them.
2439 * This isn't strictly the opcode field as defined in the spec and may
2440 * also include type, subtype, and/or subop fields.
2448 * The command's length. The command is either fixed length (i.e. does
2449 * not include a length field) or has a length field mask. The flag
2450 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2451 * a length mask. All command entries in a command table must include
2452 * length information.
2460 * Describes where to find a register address in the command to check
2461 * against the ring's register whitelist. Only valid if flags has the
2462 * CMD_DESC_REGISTER bit set.
2464 * A non-zero step value implies that the command may access multiple
2465 * registers in sequence (e.g. LRI), in that case step gives the
2466 * distance in dwords between individual offset fields.
2474 #define MAX_CMD_DESC_BITMASKS 3
2476 * Describes command checks where a particular dword is masked and
2477 * compared against an expected value. If the command does not match
2478 * the expected value, the parser rejects it. Only valid if flags has
2479 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2482 * If the check specifies a non-zero condition_mask then the parser
2483 * only performs the check when the bits specified by condition_mask
2490 u32 condition_offset;
2492 } bits[MAX_CMD_DESC_BITMASKS];
2496 * A table of commands requiring special handling by the command parser.
2498 * Each ring has an array of tables. Each table consists of an array of command
2499 * descriptors, which must be sorted with command opcodes in ascending order.
2501 struct drm_i915_cmd_table {
2502 const struct drm_i915_cmd_descriptor *table;
2506 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2507 #define __I915__(p) ({ \
2508 struct drm_i915_private *__p; \
2509 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2510 __p = (struct drm_i915_private *)p; \
2511 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2512 __p = to_i915((struct drm_device *)p); \
2517 #define INTEL_INFO(p) (&__I915__(p)->info)
2518 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2519 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2520 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2522 #define REVID_FOREVER 0xff
2524 * Return true if revision is in range [since,until] inclusive.
2526 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2528 #define IS_REVID(p, since, until) \
2529 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2531 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2532 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2533 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2534 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2535 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2536 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2537 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2538 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2539 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2540 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2541 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2542 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2543 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2544 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2545 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2546 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2547 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2548 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2549 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2550 INTEL_DEVID(dev) == 0x0152 || \
2551 INTEL_DEVID(dev) == 0x015a)
2552 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2553 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2554 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2555 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2556 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2557 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2558 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2559 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2560 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2561 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2562 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2563 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2564 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2565 (INTEL_DEVID(dev) & 0xf) == 0xe))
2566 /* ULX machines are also considered ULT. */
2567 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2568 (INTEL_DEVID(dev) & 0xf) == 0xe)
2569 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2570 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2571 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2572 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2573 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2574 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2575 /* ULX machines are also considered ULT. */
2576 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2577 INTEL_DEVID(dev) == 0x0A1E)
2578 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2579 INTEL_DEVID(dev) == 0x1913 || \
2580 INTEL_DEVID(dev) == 0x1916 || \
2581 INTEL_DEVID(dev) == 0x1921 || \
2582 INTEL_DEVID(dev) == 0x1926)
2583 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2584 INTEL_DEVID(dev) == 0x1915 || \
2585 INTEL_DEVID(dev) == 0x191E)
2586 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2587 INTEL_DEVID(dev) == 0x5913 || \
2588 INTEL_DEVID(dev) == 0x5916 || \
2589 INTEL_DEVID(dev) == 0x5921 || \
2590 INTEL_DEVID(dev) == 0x5926)
2591 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2592 INTEL_DEVID(dev) == 0x5915 || \
2593 INTEL_DEVID(dev) == 0x591E)
2594 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2595 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2596 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2597 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2599 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2601 #define SKL_REVID_A0 0x0
2602 #define SKL_REVID_B0 0x1
2603 #define SKL_REVID_C0 0x2
2604 #define SKL_REVID_D0 0x3
2605 #define SKL_REVID_E0 0x4
2606 #define SKL_REVID_F0 0x5
2608 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2610 #define BXT_REVID_A0 0x0
2611 #define BXT_REVID_A1 0x1
2612 #define BXT_REVID_B0 0x3
2613 #define BXT_REVID_C0 0x9
2615 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2618 * The genX designation typically refers to the render engine, so render
2619 * capability related checks should use IS_GEN, while display and other checks
2620 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2623 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2624 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2625 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2626 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2627 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2628 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2629 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2630 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2632 #define RENDER_RING (1<<RCS)
2633 #define BSD_RING (1<<VCS)
2634 #define BLT_RING (1<<BCS)
2635 #define VEBOX_RING (1<<VECS)
2636 #define BSD2_RING (1<<VCS2)
2637 #define ALL_ENGINES (~0)
2639 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2640 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2641 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2642 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2643 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2644 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2645 #define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED)
2646 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2648 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2650 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2651 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2652 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2653 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2654 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2656 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2657 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2659 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2660 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2662 /* WaRsDisableCoarsePowerGating:skl,bxt */
2663 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2664 IS_SKL_GT3(dev) || \
2668 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2669 * even when in MSI mode. This results in spurious interrupt warnings if the
2670 * legacy irq no. is shared with another device. The kernel then disables that
2671 * interrupt source and so prevents the other device from working properly.
2673 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2674 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2676 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2677 * rows, which changed the alignment requirements and fence programming.
2679 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2681 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2682 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2684 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2685 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2686 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2688 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2690 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2691 INTEL_INFO(dev)->gen >= 9)
2693 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2694 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2695 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2696 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2697 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2698 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2699 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2700 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2701 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2702 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2703 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2705 #define HAS_CSR(dev) (IS_GEN9(dev))
2707 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2708 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2710 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2711 INTEL_INFO(dev)->gen >= 8)
2713 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2714 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2717 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2718 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2719 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2720 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2721 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2722 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2723 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2724 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2725 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2726 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2727 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2729 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2730 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2731 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2732 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2733 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2734 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2735 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2736 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2737 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2739 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2740 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2742 /* DPF == dynamic parity feature */
2743 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2744 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2746 #define GT_FREQUENCY_MULTIPLIER 50
2747 #define GEN9_FREQ_SCALER 3
2749 #include "i915_trace.h"
2751 extern const struct drm_ioctl_desc i915_ioctls[];
2752 extern int i915_max_ioctl;
2754 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2755 extern int i915_resume_switcheroo(struct drm_device *dev);
2757 int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt);
2761 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2762 const char *fmt, ...);
2764 #define i915_report_error(dev_priv, fmt, ...) \
2765 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2767 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2768 extern int i915_driver_unload(struct drm_device *);
2769 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2770 extern void i915_driver_lastclose(struct drm_device * dev);
2771 extern void i915_driver_preclose(struct drm_device *dev,
2772 struct drm_file *file);
2773 extern void i915_driver_postclose(struct drm_device *dev,
2774 struct drm_file *file);
2775 #ifdef CONFIG_COMPAT
2776 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2779 extern int intel_gpu_reset(struct drm_device *dev, u32 engine_mask);
2780 extern bool intel_has_gpu_reset(struct drm_device *dev);
2781 extern int i915_reset(struct drm_device *dev);
2782 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2783 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2784 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2785 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2786 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2787 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2788 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2790 /* intel_hotplug.c */
2791 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2792 void intel_hpd_init(struct drm_i915_private *dev_priv);
2793 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2794 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2795 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2798 void i915_queue_hangcheck(struct drm_device *dev);
2800 void i915_handle_error(struct drm_device *dev, u32 engine_mask,
2801 const char *fmt, ...);
2803 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2804 int intel_irq_install(struct drm_i915_private *dev_priv);
2805 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2807 extern void intel_uncore_sanitize(struct drm_device *dev);
2808 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2809 bool restore_forcewake);
2810 extern void intel_uncore_init(struct drm_device *dev);
2811 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2812 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2813 extern void intel_uncore_fini(struct drm_device *dev);
2814 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2815 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2816 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2817 enum forcewake_domains domains);
2818 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2819 enum forcewake_domains domains);
2820 /* Like above but the caller must manage the uncore.lock itself.
2821 * Must be used with I915_READ_FW and friends.
2823 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2824 enum forcewake_domains domains);
2825 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2826 enum forcewake_domains domains);
2827 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
2829 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2830 static inline bool intel_vgpu_active(struct drm_device *dev)
2832 return to_i915(dev)->vgpu.active;
2836 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2840 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2843 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2844 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2845 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2848 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2849 uint32_t interrupt_mask,
2850 uint32_t enabled_irq_mask);
2852 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2854 ilk_update_display_irq(dev_priv, bits, bits);
2857 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2859 ilk_update_display_irq(dev_priv, bits, 0);
2861 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2863 uint32_t interrupt_mask,
2864 uint32_t enabled_irq_mask);
2865 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2866 enum pipe pipe, uint32_t bits)
2868 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2870 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2871 enum pipe pipe, uint32_t bits)
2873 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2875 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2876 uint32_t interrupt_mask,
2877 uint32_t enabled_irq_mask);
2879 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2881 ibx_display_interrupt_update(dev_priv, bits, bits);
2884 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2886 ibx_display_interrupt_update(dev_priv, bits, 0);
2891 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2892 struct drm_file *file_priv);
2893 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2894 struct drm_file *file_priv);
2895 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2896 struct drm_file *file_priv);
2897 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2898 struct drm_file *file_priv);
2899 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2900 struct drm_file *file_priv);
2901 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2902 struct drm_file *file_priv);
2903 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2904 struct drm_file *file_priv);
2905 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2906 struct drm_i915_gem_request *req);
2907 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2908 struct drm_i915_gem_execbuffer2 *args,
2909 struct list_head *vmas);
2910 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2911 struct drm_file *file_priv);
2912 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2913 struct drm_file *file_priv);
2914 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2915 struct drm_file *file_priv);
2916 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2917 struct drm_file *file);
2918 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2919 struct drm_file *file);
2920 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2921 struct drm_file *file_priv);
2922 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2923 struct drm_file *file_priv);
2924 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2925 struct drm_file *file_priv);
2926 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2927 struct drm_file *file_priv);
2928 int i915_gem_init_userptr(struct drm_device *dev);
2929 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2930 struct drm_file *file);
2931 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2932 struct drm_file *file_priv);
2933 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2934 struct drm_file *file_priv);
2935 void i915_gem_load_init(struct drm_device *dev);
2936 void i915_gem_load_cleanup(struct drm_device *dev);
2937 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2938 void *i915_gem_object_alloc(struct drm_device *dev);
2939 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2940 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2941 const struct drm_i915_gem_object_ops *ops);
2942 struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
2944 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2945 struct drm_device *dev, const void *data, size_t size);
2946 void i915_gem_free_object(struct drm_gem_object *obj);
2947 void i915_gem_vma_destroy(struct i915_vma *vma);
2949 /* Flags used by pin/bind&friends. */
2950 #define PIN_MAPPABLE (1<<0)
2951 #define PIN_NONBLOCK (1<<1)
2952 #define PIN_GLOBAL (1<<2)
2953 #define PIN_OFFSET_BIAS (1<<3)
2954 #define PIN_USER (1<<4)
2955 #define PIN_UPDATE (1<<5)
2956 #define PIN_ZONE_4G (1<<6)
2957 #define PIN_HIGH (1<<7)
2958 #define PIN_OFFSET_FIXED (1<<8)
2959 #define PIN_OFFSET_MASK (~4095)
2961 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2962 struct i915_address_space *vm,
2966 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2967 const struct i915_ggtt_view *view,
2971 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2973 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2974 int __must_check i915_vma_unbind(struct i915_vma *vma);
2976 * BEWARE: Do not use the function below unless you can _absolutely_
2977 * _guarantee_ VMA in question is _not in use_ anywhere.
2979 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2980 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2981 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2982 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2984 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2985 int *needs_clflush);
2987 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2989 static inline int __sg_page_count(struct scatterlist *sg)
2991 return sg->length >> PAGE_SHIFT;
2995 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
2997 static inline struct page *
2998 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3000 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
3003 if (n < obj->get_page.last) {
3004 obj->get_page.sg = obj->pages->sgl;
3005 obj->get_page.last = 0;
3008 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3009 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3010 if (unlikely(sg_is_chain(obj->get_page.sg)))
3011 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3014 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3017 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3019 BUG_ON(obj->pages == NULL);
3020 obj->pages_pin_count++;
3023 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3025 BUG_ON(obj->pages_pin_count == 0);
3026 obj->pages_pin_count--;
3030 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3031 * @obj - the object to map into kernel address space
3033 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3034 * pages and then returns a contiguous mapping of the backing storage into
3035 * the kernel address space.
3037 * The caller must hold the struct_mutex, and is responsible for calling
3038 * i915_gem_object_unpin_map() when the mapping is no longer required.
3040 * Returns the pointer through which to access the mapped object, or an
3041 * ERR_PTR() on error.
3043 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj);
3046 * i915_gem_object_unpin_map - releases an earlier mapping
3047 * @obj - the object to unmap
3049 * After pinning the object and mapping its pages, once you are finished
3050 * with your access, call i915_gem_object_unpin_map() to release the pin
3051 * upon the mapping. Once the pin count reaches zero, that mapping may be
3054 * The caller must hold the struct_mutex.
3056 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3058 lockdep_assert_held(&obj->base.dev->struct_mutex);
3059 i915_gem_object_unpin_pages(obj);
3062 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3063 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3064 struct intel_engine_cs *to,
3065 struct drm_i915_gem_request **to_req);
3066 void i915_vma_move_to_active(struct i915_vma *vma,
3067 struct drm_i915_gem_request *req);
3068 int i915_gem_dumb_create(struct drm_file *file_priv,
3069 struct drm_device *dev,
3070 struct drm_mode_create_dumb *args);
3071 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3072 uint32_t handle, uint64_t *offset);
3074 * Returns true if seq1 is later than seq2.
3077 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
3079 return (int32_t)(seq1 - seq2) >= 0;
3082 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
3083 bool lazy_coherency)
3085 if (!lazy_coherency && req->engine->irq_seqno_barrier)
3086 req->engine->irq_seqno_barrier(req->engine);
3087 return i915_seqno_passed(req->engine->get_seqno(req->engine),
3088 req->previous_seqno);
3091 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
3092 bool lazy_coherency)
3094 if (!lazy_coherency && req->engine->irq_seqno_barrier)
3095 req->engine->irq_seqno_barrier(req->engine);
3096 return i915_seqno_passed(req->engine->get_seqno(req->engine),
3100 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
3101 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3103 struct drm_i915_gem_request *
3104 i915_gem_find_active_request(struct intel_engine_cs *engine);
3106 bool i915_gem_retire_requests(struct drm_device *dev);
3107 void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
3109 static inline u32 i915_reset_counter(struct i915_gpu_error *error)
3111 return atomic_read(&error->reset_counter);
3114 static inline bool __i915_reset_in_progress(u32 reset)
3116 return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
3119 static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
3121 return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3124 static inline bool __i915_terminally_wedged(u32 reset)
3126 return unlikely(reset & I915_WEDGED);
3129 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3131 return __i915_reset_in_progress(i915_reset_counter(error));
3134 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3136 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
3139 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3141 return __i915_terminally_wedged(i915_reset_counter(error));
3144 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3146 return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
3149 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3151 return dev_priv->gpu_error.stop_rings == 0 ||
3152 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3155 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3157 return dev_priv->gpu_error.stop_rings == 0 ||
3158 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3161 void i915_gem_reset(struct drm_device *dev);
3162 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3163 int __must_check i915_gem_init(struct drm_device *dev);
3164 int i915_gem_init_engines(struct drm_device *dev);
3165 int __must_check i915_gem_init_hw(struct drm_device *dev);
3166 void i915_gem_init_swizzling(struct drm_device *dev);
3167 void i915_gem_cleanup_engines(struct drm_device *dev);
3168 int __must_check i915_gpu_idle(struct drm_device *dev);
3169 int __must_check i915_gem_suspend(struct drm_device *dev);
3170 void __i915_add_request(struct drm_i915_gem_request *req,
3171 struct drm_i915_gem_object *batch_obj,
3173 #define i915_add_request(req) \
3174 __i915_add_request(req, NULL, true)
3175 #define i915_add_request_no_flush(req) \
3176 __i915_add_request(req, NULL, false)
3177 int __i915_wait_request(struct drm_i915_gem_request *req,
3180 struct intel_rps_client *rps);
3181 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3182 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3184 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3187 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3190 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3192 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3194 const struct i915_ggtt_view *view);
3195 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3196 const struct i915_ggtt_view *view);
3197 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3199 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3200 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3203 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3205 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3206 int tiling_mode, bool fenced);
3208 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3209 enum i915_cache_level cache_level);
3211 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3212 struct dma_buf *dma_buf);
3214 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3215 struct drm_gem_object *gem_obj, int flags);
3217 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3218 const struct i915_ggtt_view *view);
3219 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3220 struct i915_address_space *vm);
3222 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3224 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3227 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3228 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3229 const struct i915_ggtt_view *view);
3230 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3231 struct i915_address_space *vm);
3234 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3235 struct i915_address_space *vm);
3237 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3238 const struct i915_ggtt_view *view);
3241 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3242 struct i915_address_space *vm);
3244 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3245 const struct i915_ggtt_view *view);
3247 static inline struct i915_vma *
3248 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3250 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3252 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3254 /* Some GGTT VM helpers */
3255 static inline struct i915_hw_ppgtt *
3256 i915_vm_to_ppgtt(struct i915_address_space *vm)
3258 return container_of(vm, struct i915_hw_ppgtt, base);
3262 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3264 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3268 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj);
3270 static inline int __must_check
3271 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3275 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3276 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3278 return i915_gem_object_pin(obj, &ggtt->base,
3279 alignment, flags | PIN_GLOBAL);
3282 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3283 const struct i915_ggtt_view *view);
3285 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3287 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3290 /* i915_gem_fence.c */
3291 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3292 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3294 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3295 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3297 void i915_gem_restore_fences(struct drm_device *dev);
3299 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3300 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3301 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3303 /* i915_gem_context.c */
3304 int __must_check i915_gem_context_init(struct drm_device *dev);
3305 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3306 void i915_gem_context_fini(struct drm_device *dev);
3307 void i915_gem_context_reset(struct drm_device *dev);
3308 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3309 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3310 int i915_switch_context(struct drm_i915_gem_request *req);
3311 struct intel_context *
3312 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3313 void i915_gem_context_free(struct kref *ctx_ref);
3314 struct drm_i915_gem_object *
3315 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3316 static inline void i915_gem_context_reference(struct intel_context *ctx)
3318 kref_get(&ctx->ref);
3321 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3323 kref_put(&ctx->ref, i915_gem_context_free);
3326 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3328 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3331 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3332 struct drm_file *file);
3333 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3334 struct drm_file *file);
3335 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3336 struct drm_file *file_priv);
3337 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3338 struct drm_file *file_priv);
3340 /* i915_gem_evict.c */
3341 int __must_check i915_gem_evict_something(struct drm_device *dev,
3342 struct i915_address_space *vm,
3345 unsigned cache_level,
3346 unsigned long start,
3349 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3350 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3352 /* belongs in i915_gem_gtt.h */
3353 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3355 if (INTEL_INFO(dev)->gen < 6)
3356 intel_gtt_chipset_flush();
3359 /* i915_gem_stolen.c */
3360 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3361 struct drm_mm_node *node, u64 size,
3362 unsigned alignment);
3363 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3364 struct drm_mm_node *node, u64 size,
3365 unsigned alignment, u64 start,
3367 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3368 struct drm_mm_node *node);
3369 int i915_gem_init_stolen(struct drm_device *dev);
3370 void i915_gem_cleanup_stolen(struct drm_device *dev);
3371 struct drm_i915_gem_object *
3372 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3373 struct drm_i915_gem_object *
3374 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3379 /* i915_gem_shrinker.c */
3380 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3381 unsigned long target,
3383 #define I915_SHRINK_PURGEABLE 0x1
3384 #define I915_SHRINK_UNBOUND 0x2
3385 #define I915_SHRINK_BOUND 0x4
3386 #define I915_SHRINK_ACTIVE 0x8
3387 #define I915_SHRINK_VMAPS 0x10
3388 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3389 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3390 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3393 /* i915_gem_tiling.c */
3394 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3396 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3398 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3399 obj->tiling_mode != I915_TILING_NONE;
3402 /* i915_gem_debug.c */
3404 int i915_verify_lists(struct drm_device *dev);
3406 #define i915_verify_lists(dev) 0
3409 /* i915_debugfs.c */
3410 int i915_debugfs_init(struct drm_minor *minor);
3411 void i915_debugfs_cleanup(struct drm_minor *minor);
3412 #ifdef CONFIG_DEBUG_FS
3413 int i915_debugfs_connector_add(struct drm_connector *connector);
3414 void intel_display_crc_init(struct drm_device *dev);
3416 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3418 static inline void intel_display_crc_init(struct drm_device *dev) {}
3421 /* i915_gpu_error.c */
3423 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3424 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3425 const struct i915_error_state_file_priv *error);
3426 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3427 struct drm_i915_private *i915,
3428 size_t count, loff_t pos);
3429 static inline void i915_error_state_buf_release(
3430 struct drm_i915_error_state_buf *eb)
3434 void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
3435 const char *error_msg);
3436 void i915_error_state_get(struct drm_device *dev,
3437 struct i915_error_state_file_priv *error_priv);
3438 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3439 void i915_destroy_error_state(struct drm_device *dev);
3441 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3442 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3444 /* i915_cmd_parser.c */
3445 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3446 int i915_cmd_parser_init_ring(struct intel_engine_cs *engine);
3447 void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine);
3448 bool i915_needs_cmd_parser(struct intel_engine_cs *engine);
3449 int i915_parse_cmds(struct intel_engine_cs *engine,
3450 struct drm_i915_gem_object *batch_obj,
3451 struct drm_i915_gem_object *shadow_batch_obj,
3452 u32 batch_start_offset,
3456 /* i915_suspend.c */
3457 extern int i915_save_state(struct drm_device *dev);
3458 extern int i915_restore_state(struct drm_device *dev);
3461 void i915_setup_sysfs(struct drm_device *dev_priv);
3462 void i915_teardown_sysfs(struct drm_device *dev_priv);
3465 extern int intel_setup_gmbus(struct drm_device *dev);
3466 extern void intel_teardown_gmbus(struct drm_device *dev);
3467 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3470 extern struct i2c_adapter *
3471 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3472 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3473 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3474 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3476 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3478 extern void intel_i2c_reset(struct drm_device *dev);
3481 int intel_bios_init(struct drm_i915_private *dev_priv);
3482 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3483 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3484 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3485 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3486 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3487 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3488 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3491 /* intel_opregion.c */
3493 extern int intel_opregion_setup(struct drm_device *dev);
3494 extern void intel_opregion_init(struct drm_device *dev);
3495 extern void intel_opregion_fini(struct drm_device *dev);
3496 extern void intel_opregion_asle_intr(struct drm_device *dev);
3497 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3499 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3501 extern int intel_opregion_get_panel_type(struct drm_device *dev);
3503 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3504 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3505 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3506 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3508 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3513 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3517 static inline int intel_opregion_get_panel_type(struct drm_device *dev)
3525 extern void intel_register_dsm_handler(void);
3526 extern void intel_unregister_dsm_handler(void);
3528 static inline void intel_register_dsm_handler(void) { return; }
3529 static inline void intel_unregister_dsm_handler(void) { return; }
3530 #endif /* CONFIG_ACPI */
3533 extern void intel_modeset_init_hw(struct drm_device *dev);
3534 extern void intel_modeset_init(struct drm_device *dev);
3535 extern void intel_modeset_gem_init(struct drm_device *dev);
3536 extern void intel_modeset_cleanup(struct drm_device *dev);
3537 extern void intel_connector_unregister(struct intel_connector *);
3538 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3539 extern void intel_display_resume(struct drm_device *dev);
3540 extern void i915_redisable_vga(struct drm_device *dev);
3541 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3542 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3543 extern void intel_init_pch_refclk(struct drm_device *dev);
3544 extern void intel_set_rps(struct drm_device *dev, u8 val);
3545 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3547 extern void intel_detect_pch(struct drm_device *dev);
3548 extern int intel_enable_rc6(const struct drm_device *dev);
3550 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3551 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3552 struct drm_file *file);
3553 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3554 struct drm_file *file);
3557 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3558 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3559 struct intel_overlay_error_state *error);
3561 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3562 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3563 struct drm_device *dev,
3564 struct intel_display_error_state *error);
3566 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3567 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3569 /* intel_sideband.c */
3570 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3571 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3572 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3573 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3574 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3575 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3576 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3577 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3578 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3579 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3580 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3581 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3582 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3583 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3584 enum intel_sbi_destination destination);
3585 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3586 enum intel_sbi_destination destination);
3587 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3588 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3590 /* intel_dpio_phy.c */
3591 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3592 u32 deemph_reg_value, u32 margin_reg_value,
3593 bool uniq_trans_scale);
3594 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3596 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3597 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3598 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3599 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3601 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3602 u32 demph_reg_value, u32 preemph_reg_value,
3603 u32 uniqtranscale_reg_value, u32 tx3_demph);
3604 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3605 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3606 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3608 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3609 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3611 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3612 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3614 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3615 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3616 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3617 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3619 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3620 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3621 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3622 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3624 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3625 * will be implemented using 2 32-bit writes in an arbitrary order with
3626 * an arbitrary delay between them. This can cause the hardware to
3627 * act upon the intermediate value, possibly leading to corruption and
3628 * machine death. You have been warned.
3630 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3631 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3633 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3634 u32 upper, lower, old_upper, loop = 0; \
3635 upper = I915_READ(upper_reg); \
3637 old_upper = upper; \
3638 lower = I915_READ(lower_reg); \
3639 upper = I915_READ(upper_reg); \
3640 } while (upper != old_upper && loop++ < 2); \
3641 (u64)upper << 32 | lower; })
3643 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3644 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3646 #define __raw_read(x, s) \
3647 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3650 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3653 #define __raw_write(x, s) \
3654 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3655 i915_reg_t reg, uint##x##_t val) \
3657 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3672 /* These are untraced mmio-accessors that are only valid to be used inside
3673 * criticial sections inside IRQ handlers where forcewake is explicitly
3675 * Think twice, and think again, before using these.
3676 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3677 * intel_uncore_forcewake_irqunlock().
3679 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3680 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3681 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3683 /* "Broadcast RGB" property */
3684 #define INTEL_BROADCAST_RGB_AUTO 0
3685 #define INTEL_BROADCAST_RGB_FULL 1
3686 #define INTEL_BROADCAST_RGB_LIMITED 2
3688 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3690 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3691 return VLV_VGACNTRL;
3692 else if (INTEL_INFO(dev)->gen >= 5)
3693 return CPU_VGACNTRL;
3698 static inline void __user *to_user_ptr(u64 address)
3700 return (void __user *)(uintptr_t)address;
3703 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3705 unsigned long j = msecs_to_jiffies(m);
3707 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3710 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3712 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3715 static inline unsigned long
3716 timespec_to_jiffies_timeout(const struct timespec *value)
3718 unsigned long j = timespec_to_jiffies(value);
3720 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3724 * If you need to wait X milliseconds between events A and B, but event B
3725 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3726 * when event A happened, then just before event B you call this function and
3727 * pass the timestamp as the first argument, and X as the second argument.
3730 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3732 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3735 * Don't re-read the value of "jiffies" every time since it may change
3736 * behind our back and break the math.
3738 tmp_jiffies = jiffies;
3739 target_jiffies = timestamp_jiffies +
3740 msecs_to_jiffies_timeout(to_wait_ms);
3742 if (time_after(target_jiffies, tmp_jiffies)) {
3743 remaining_jiffies = target_jiffies - tmp_jiffies;
3744 while (remaining_jiffies)
3746 schedule_timeout_uninterruptible(remaining_jiffies);
3750 static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
3751 struct drm_i915_gem_request *req)
3753 if (engine->trace_irq_req == NULL && engine->irq_get(engine))
3754 i915_gem_request_assign(&engine->trace_irq_req, req);