1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <drm/drm_auth.h>
52 #include "i915_params.h"
55 #include "intel_bios.h"
56 #include "intel_dpll_mgr.h"
57 #include "intel_guc.h"
58 #include "intel_lrc.h"
59 #include "intel_ringbuffer.h"
62 #include "i915_gem_gtt.h"
63 #include "i915_gem_render_state.h"
64 #include "i915_gem_request.h"
66 #include "intel_gvt.h"
68 /* General customization:
71 #define DRIVER_NAME "i915"
72 #define DRIVER_DESC "Intel Graphics"
73 #define DRIVER_DATE "20160808"
76 /* Many gcc seem to no see through this and fall over :( */
78 #define WARN_ON(x) ({ \
79 bool __i915_warn_cond = (x); \
80 if (__builtin_constant_p(__i915_warn_cond)) \
81 BUILD_BUG_ON(__i915_warn_cond); \
82 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
84 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
88 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
90 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
91 (long) (x), __func__);
93 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
94 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
95 * which may not necessarily be a user visible problem. This will either
96 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
97 * enable distros and users to tailor their preferred amount of i915 abrt
100 #define I915_STATE_WARN(condition, format...) ({ \
101 int __ret_warn_on = !!(condition); \
102 if (unlikely(__ret_warn_on)) \
103 if (!WARN(i915.verbose_state_checks, format)) \
105 unlikely(__ret_warn_on); \
108 #define I915_STATE_WARN_ON(x) \
109 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
111 bool __i915_inject_load_failure(const char *func, int line);
112 #define i915_inject_load_failure() \
113 __i915_inject_load_failure(__func__, __LINE__)
115 static inline const char *yesno(bool v)
117 return v ? "yes" : "no";
120 static inline const char *onoff(bool v)
122 return v ? "on" : "off";
131 I915_MAX_PIPES = _PIPE_EDP
133 #define pipe_name(p) ((p) + 'A')
145 static inline const char *transcoder_name(enum transcoder transcoder)
147 switch (transcoder) {
156 case TRANSCODER_DSI_A:
158 case TRANSCODER_DSI_C:
165 static inline bool transcoder_is_dsi(enum transcoder transcoder)
167 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
171 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
172 * number of planes per CRTC. Not all platforms really have this many planes,
173 * which means some arrays of size I915_MAX_PLANES may have unused entries
174 * between the topmost sprite plane and the cursor plane.
183 #define plane_name(p) ((p) + 'A')
185 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
195 #define port_name(p) ((p) + 'A')
197 #define I915_NUM_PHYS_VLV 2
209 enum intel_display_power_domain {
213 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
214 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
215 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
216 POWER_DOMAIN_TRANSCODER_A,
217 POWER_DOMAIN_TRANSCODER_B,
218 POWER_DOMAIN_TRANSCODER_C,
219 POWER_DOMAIN_TRANSCODER_EDP,
220 POWER_DOMAIN_TRANSCODER_DSI_A,
221 POWER_DOMAIN_TRANSCODER_DSI_C,
222 POWER_DOMAIN_PORT_DDI_A_LANES,
223 POWER_DOMAIN_PORT_DDI_B_LANES,
224 POWER_DOMAIN_PORT_DDI_C_LANES,
225 POWER_DOMAIN_PORT_DDI_D_LANES,
226 POWER_DOMAIN_PORT_DDI_E_LANES,
227 POWER_DOMAIN_PORT_DSI,
228 POWER_DOMAIN_PORT_CRT,
229 POWER_DOMAIN_PORT_OTHER,
238 POWER_DOMAIN_MODESET,
244 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
245 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
246 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
247 #define POWER_DOMAIN_TRANSCODER(tran) \
248 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
249 (tran) + POWER_DOMAIN_TRANSCODER_A)
253 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
265 #define for_each_hpd_pin(__pin) \
266 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
268 struct i915_hotplug {
269 struct work_struct hotplug_work;
272 unsigned long last_jiffies;
277 HPD_MARK_DISABLED = 2
279 } stats[HPD_NUM_PINS];
281 struct delayed_work reenable_work;
283 struct intel_digital_port *irq_port[I915_MAX_PORTS];
286 struct work_struct dig_port_work;
288 struct work_struct poll_init_work;
292 * if we get a HPD irq from DP and a HPD irq from non-DP
293 * the non-DP HPD could block the workqueue on a mode config
294 * mutex getting, that userspace may have taken. However
295 * userspace is waiting on the DP workqueue to run which is
296 * blocked behind the non-DP one.
298 struct workqueue_struct *dp_wq;
301 #define I915_GEM_GPU_DOMAINS \
302 (I915_GEM_DOMAIN_RENDER | \
303 I915_GEM_DOMAIN_SAMPLER | \
304 I915_GEM_DOMAIN_COMMAND | \
305 I915_GEM_DOMAIN_INSTRUCTION | \
306 I915_GEM_DOMAIN_VERTEX)
308 #define for_each_pipe(__dev_priv, __p) \
309 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
310 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
311 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
312 for_each_if ((__mask) & (1 << (__p)))
313 #define for_each_plane(__dev_priv, __pipe, __p) \
315 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
317 #define for_each_sprite(__dev_priv, __p, __s) \
319 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
322 #define for_each_port_masked(__port, __ports_mask) \
323 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
324 for_each_if ((__ports_mask) & (1 << (__port)))
326 #define for_each_crtc(dev, crtc) \
327 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
329 #define for_each_intel_plane(dev, intel_plane) \
330 list_for_each_entry(intel_plane, \
331 &(dev)->mode_config.plane_list, \
334 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
335 list_for_each_entry(intel_plane, \
336 &(dev)->mode_config.plane_list, \
338 for_each_if ((plane_mask) & \
339 (1 << drm_plane_index(&intel_plane->base)))
341 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
342 list_for_each_entry(intel_plane, \
343 &(dev)->mode_config.plane_list, \
345 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
347 #define for_each_intel_crtc(dev, intel_crtc) \
348 list_for_each_entry(intel_crtc, \
349 &(dev)->mode_config.crtc_list, \
352 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
353 list_for_each_entry(intel_crtc, \
354 &(dev)->mode_config.crtc_list, \
356 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
358 #define for_each_intel_encoder(dev, intel_encoder) \
359 list_for_each_entry(intel_encoder, \
360 &(dev)->mode_config.encoder_list, \
363 #define for_each_intel_connector(dev, intel_connector) \
364 list_for_each_entry(intel_connector, \
365 &(dev)->mode_config.connector_list, \
368 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
369 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
370 for_each_if ((intel_encoder)->base.crtc == (__crtc))
372 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
373 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
374 for_each_if ((intel_connector)->base.encoder == (__encoder))
376 #define for_each_power_domain(domain, mask) \
377 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
378 for_each_if ((1 << (domain)) & (mask))
380 struct drm_i915_private;
381 struct i915_mm_struct;
382 struct i915_mmu_object;
384 struct drm_i915_file_private {
385 struct drm_i915_private *dev_priv;
386 struct drm_file *file;
390 struct list_head request_list;
391 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
392 * chosen to prevent the CPU getting more than a frame ahead of the GPU
393 * (when using lax throttling for the frontbuffer). We also use it to
394 * offer free GPU waitboosts for severely congested workloads.
396 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
398 struct idr context_idr;
400 struct intel_rps_client {
401 struct list_head link;
405 unsigned int bsd_engine;
408 /* Used by dp and fdi links */
409 struct intel_link_m_n {
417 void intel_link_compute_m_n(int bpp, int nlanes,
418 int pixel_clock, int link_clock,
419 struct intel_link_m_n *m_n);
421 /* Interface history:
424 * 1.2: Add Power Management
425 * 1.3: Add vblank support
426 * 1.4: Fix cmdbuffer path, add heap destroy
427 * 1.5: Add vblank pipe configuration
428 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
429 * - Support vertical blank on secondary display pipe
431 #define DRIVER_MAJOR 1
432 #define DRIVER_MINOR 6
433 #define DRIVER_PATCHLEVEL 0
435 struct opregion_header;
436 struct opregion_acpi;
437 struct opregion_swsci;
438 struct opregion_asle;
440 struct intel_opregion {
441 struct opregion_header *header;
442 struct opregion_acpi *acpi;
443 struct opregion_swsci *swsci;
444 u32 swsci_gbda_sub_functions;
445 u32 swsci_sbcb_sub_functions;
446 struct opregion_asle *asle;
451 struct work_struct asle_work;
453 #define OPREGION_SIZE (8*1024)
455 struct intel_overlay;
456 struct intel_overlay_error_state;
458 #define I915_FENCE_REG_NONE -1
459 #define I915_MAX_NUM_FENCES 32
460 /* 32 fences + sign bit for FENCE_REG_NONE */
461 #define I915_MAX_NUM_FENCE_BITS 6
463 struct drm_i915_fence_reg {
464 struct list_head lru_list;
465 struct drm_i915_gem_object *obj;
469 struct sdvo_device_mapping {
478 struct intel_display_error_state;
480 struct drm_i915_error_state {
490 /* Generic register state */
498 u32 error; /* gen6+ */
499 u32 err_int; /* gen7 */
500 u32 fault_data0; /* gen8, gen9 */
501 u32 fault_data1; /* gen8, gen9 */
507 u32 extra_instdone[I915_NUM_INSTDONE_REG];
508 u64 fence[I915_MAX_NUM_FENCES];
509 struct intel_overlay_error_state *overlay;
510 struct intel_display_error_state *display;
511 struct drm_i915_error_object *semaphore_obj;
513 struct drm_i915_error_engine {
515 /* Software tracked state */
519 enum intel_engine_hangcheck_action hangcheck_action;
522 /* our own tracking of ring head and tail */
527 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
546 u32 rc_psmi; /* sleep state */
547 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
549 struct drm_i915_error_object {
553 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
555 struct drm_i915_error_object *wa_ctx;
557 struct drm_i915_error_request {
563 struct drm_i915_error_waiter {
564 char comm[TASK_COMM_LEN];
578 char comm[TASK_COMM_LEN];
579 } engine[I915_NUM_ENGINES];
581 struct drm_i915_error_buffer {
584 u32 rseqno[I915_NUM_ENGINES], wseqno;
588 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
596 } **active_bo, **pinned_bo;
598 u32 *active_bo_count, *pinned_bo_count;
602 struct intel_connector;
603 struct intel_encoder;
604 struct intel_crtc_state;
605 struct intel_initial_plane_config;
610 struct drm_i915_display_funcs {
611 int (*get_display_clock_speed)(struct drm_device *dev);
612 int (*get_fifo_size)(struct drm_device *dev, int plane);
613 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
614 int (*compute_intermediate_wm)(struct drm_device *dev,
615 struct intel_crtc *intel_crtc,
616 struct intel_crtc_state *newstate);
617 void (*initial_watermarks)(struct intel_crtc_state *cstate);
618 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
619 int (*compute_global_watermarks)(struct drm_atomic_state *state);
620 void (*update_wm)(struct drm_crtc *crtc);
621 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
622 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
623 /* Returns the active state of the crtc, and if the crtc is active,
624 * fills out the pipe-config with the hw state. */
625 bool (*get_pipe_config)(struct intel_crtc *,
626 struct intel_crtc_state *);
627 void (*get_initial_plane_config)(struct intel_crtc *,
628 struct intel_initial_plane_config *);
629 int (*crtc_compute_clock)(struct intel_crtc *crtc,
630 struct intel_crtc_state *crtc_state);
631 void (*crtc_enable)(struct drm_crtc *crtc);
632 void (*crtc_disable)(struct drm_crtc *crtc);
633 void (*audio_codec_enable)(struct drm_connector *connector,
634 struct intel_encoder *encoder,
635 const struct drm_display_mode *adjusted_mode);
636 void (*audio_codec_disable)(struct intel_encoder *encoder);
637 void (*fdi_link_train)(struct drm_crtc *crtc);
638 void (*init_clock_gating)(struct drm_device *dev);
639 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
640 struct drm_framebuffer *fb,
641 struct drm_i915_gem_object *obj,
642 struct drm_i915_gem_request *req,
644 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
645 /* clock updates for mode set */
647 /* render clock increase/decrease */
648 /* display clock increase/decrease */
649 /* pll clock increase/decrease */
651 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
652 void (*load_luts)(struct drm_crtc_state *crtc_state);
655 enum forcewake_domain_id {
656 FW_DOMAIN_ID_RENDER = 0,
657 FW_DOMAIN_ID_BLITTER,
663 enum forcewake_domains {
664 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
665 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
666 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
667 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
672 #define FW_REG_READ (1)
673 #define FW_REG_WRITE (2)
675 enum forcewake_domains
676 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
677 i915_reg_t reg, unsigned int op);
679 struct intel_uncore_funcs {
680 void (*force_wake_get)(struct drm_i915_private *dev_priv,
681 enum forcewake_domains domains);
682 void (*force_wake_put)(struct drm_i915_private *dev_priv,
683 enum forcewake_domains domains);
685 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
686 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
687 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
688 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
690 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
691 uint8_t val, bool trace);
692 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
693 uint16_t val, bool trace);
694 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
695 uint32_t val, bool trace);
696 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
697 uint64_t val, bool trace);
700 struct intel_uncore {
701 spinlock_t lock; /** lock is also taken in irq contexts. */
703 struct intel_uncore_funcs funcs;
706 enum forcewake_domains fw_domains;
708 struct intel_uncore_forcewake_domain {
709 struct drm_i915_private *i915;
710 enum forcewake_domain_id id;
711 enum forcewake_domains mask;
713 struct hrtimer timer;
720 } fw_domain[FW_DOMAIN_ID_COUNT];
722 int unclaimed_mmio_check;
725 /* Iterate over initialised fw domains */
726 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
727 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
728 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
730 for_each_if ((mask__) & (domain__)->mask)
732 #define for_each_fw_domain(domain__, dev_priv__) \
733 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
735 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
736 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
737 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
740 struct work_struct work;
742 uint32_t *dmc_payload;
743 uint32_t dmc_fw_size;
746 i915_reg_t mmioaddr[8];
747 uint32_t mmiodata[8];
749 uint32_t allowed_dc_mask;
752 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
753 func(is_mobile) sep \
756 func(is_i945gm) sep \
758 func(need_gfx_hws) sep \
760 func(is_pineview) sep \
761 func(is_broadwater) sep \
762 func(is_crestline) sep \
763 func(is_ivybridge) sep \
764 func(is_valleyview) sep \
765 func(is_cherryview) sep \
766 func(is_haswell) sep \
767 func(is_broadwell) sep \
768 func(is_skylake) sep \
769 func(is_broxton) sep \
770 func(is_kabylake) sep \
771 func(is_preliminary) sep \
773 func(has_pipe_cxsr) sep \
774 func(has_hotplug) sep \
775 func(cursor_needs_physical) sep \
776 func(has_overlay) sep \
777 func(overlay_needs_physical) sep \
778 func(supports_tv) sep \
780 func(has_snoop) sep \
782 func(has_fpga_dbg) sep \
785 #define DEFINE_FLAG(name) u8 name:1
786 #define SEP_SEMICOLON ;
788 struct intel_device_info {
789 u32 display_mmio_offset;
792 u8 num_sprites[I915_MAX_PIPES];
795 u8 ring_mask; /* Rings supported by the HW */
796 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
797 /* Register offsets for the various display pipes and transcoders */
798 int pipe_offsets[I915_MAX_TRANSCODERS];
799 int trans_offsets[I915_MAX_TRANSCODERS];
800 int palette_offsets[I915_MAX_PIPES];
801 int cursor_offsets[I915_MAX_PIPES];
803 /* Slice/subslice/EU info */
806 u8 subslice_per_slice;
810 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
813 u8 has_subslice_pg:1;
817 u16 degamma_lut_size;
825 enum i915_cache_level {
827 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
828 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
829 caches, eg sampler/render caches, and the
830 large Last-Level-Cache. LLC is coherent with
831 the CPU, but L3 is only visible to the GPU. */
832 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
835 struct i915_ctx_hang_stats {
836 /* This context had batch pending when hang was declared */
837 unsigned batch_pending;
839 /* This context had batch active when hang was declared */
840 unsigned batch_active;
842 /* Time when this context was last blamed for a GPU reset */
843 unsigned long guilty_ts;
845 /* If the contexts causes a second GPU hang within this time,
846 * it is permanently banned from submitting any more work.
848 unsigned long ban_period_seconds;
850 /* This context is banned to submit more work */
854 /* This must match up with the value previously used for execbuf2.rsvd1. */
855 #define DEFAULT_CONTEXT_HANDLE 0
858 * struct i915_gem_context - as the name implies, represents a context.
859 * @ref: reference count.
860 * @user_handle: userspace tracking identity for this context.
861 * @remap_slice: l3 row remapping information.
862 * @flags: context specific flags:
863 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
864 * @file_priv: filp associated with this context (NULL for global default
866 * @hang_stats: information about the role of this context in possible GPU
868 * @ppgtt: virtual memory space used by this context.
869 * @legacy_hw_ctx: render context backing object and whether it is correctly
870 * initialized (legacy ring submission mechanism only).
871 * @link: link in the global list of contexts.
873 * Contexts are memory images used by the hardware to store copies of their
876 struct i915_gem_context {
878 struct drm_i915_private *i915;
879 struct drm_i915_file_private *file_priv;
880 struct i915_hw_ppgtt *ppgtt;
882 struct i915_ctx_hang_stats hang_stats;
884 /* Unique identifier for this context, used by the hw for tracking */
886 #define CONTEXT_NO_ZEROMAP BIT(0)
887 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
893 struct intel_context {
894 struct drm_i915_gem_object *state;
895 struct intel_ring *ring;
896 struct i915_vma *lrc_vma;
897 uint32_t *lrc_reg_state;
901 } engine[I915_NUM_ENGINES];
904 struct atomic_notifier_head status_notifier;
905 bool execlists_force_single_submission;
907 struct list_head link;
922 /* This is always the inner lock when overlapping with struct_mutex and
923 * it's the outer lock when overlapping with stolen_lock. */
926 unsigned int possible_framebuffer_bits;
927 unsigned int busy_bits;
928 unsigned int visible_pipes_mask;
929 struct intel_crtc *crtc;
931 struct drm_mm_node compressed_fb;
932 struct drm_mm_node *compressed_llb;
939 struct intel_fbc_state_cache {
941 unsigned int mode_flags;
942 uint32_t hsw_bdw_pixel_rate;
946 unsigned int rotation;
954 uint32_t pixel_format;
957 unsigned int tiling_mode;
961 struct intel_fbc_reg_params {
965 unsigned int fence_y_offset;
970 uint32_t pixel_format;
978 struct intel_fbc_work {
980 u32 scheduled_vblank;
981 struct work_struct work;
984 const char *no_fbc_reason;
988 * HIGH_RR is the highest eDP panel refresh rate read from EDID
989 * LOW_RR is the lowest eDP panel refresh rate found from EDID
990 * parsing for same resolution.
992 enum drrs_refresh_rate_type {
995 DRRS_MAX_RR, /* RR count */
998 enum drrs_support_type {
999 DRRS_NOT_SUPPORTED = 0,
1000 STATIC_DRRS_SUPPORT = 1,
1001 SEAMLESS_DRRS_SUPPORT = 2
1007 struct delayed_work work;
1008 struct intel_dp *dp;
1009 unsigned busy_frontbuffer_bits;
1010 enum drrs_refresh_rate_type refresh_rate_type;
1011 enum drrs_support_type type;
1018 struct intel_dp *enabled;
1020 struct delayed_work work;
1021 unsigned busy_frontbuffer_bits;
1023 bool aux_frame_sync;
1028 PCH_NONE = 0, /* No PCH present */
1029 PCH_IBX, /* Ibexpeak PCH */
1030 PCH_CPT, /* Cougarpoint PCH */
1031 PCH_LPT, /* Lynxpoint PCH */
1032 PCH_SPT, /* Sunrisepoint PCH */
1033 PCH_KBP, /* Kabypoint PCH */
1037 enum intel_sbi_destination {
1042 #define QUIRK_PIPEA_FORCE (1<<0)
1043 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1044 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1045 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1046 #define QUIRK_PIPEB_FORCE (1<<4)
1047 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1050 struct intel_fbc_work;
1052 struct intel_gmbus {
1053 struct i2c_adapter adapter;
1054 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1057 i915_reg_t gpio_reg;
1058 struct i2c_algo_bit_data bit_algo;
1059 struct drm_i915_private *dev_priv;
1062 struct i915_suspend_saved_registers {
1064 u32 saveFBC_CONTROL;
1065 u32 saveCACHE_MODE_0;
1066 u32 saveMI_ARB_STATE;
1070 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1071 u32 savePCH_PORT_HOTPLUG;
1075 struct vlv_s0ix_state {
1082 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1083 u32 media_max_req_count;
1084 u32 gfx_max_req_count;
1110 u32 rp_down_timeout;
1116 /* Display 1 CZ domain */
1121 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1123 /* GT SA CZ domain */
1130 /* Display 2 CZ domain */
1134 u32 clock_gate_dis2;
1137 struct intel_rps_ei {
1143 struct intel_gen6_power_mgmt {
1145 * work, interrupts_enabled and pm_iir are protected by
1146 * dev_priv->irq_lock
1148 struct work_struct work;
1149 bool interrupts_enabled;
1154 /* Frequencies are stored in potentially platform dependent multiples.
1155 * In other words, *_freq needs to be multiplied by X to be interesting.
1156 * Soft limits are those which are used for the dynamic reclocking done
1157 * by the driver (raise frequencies under heavy loads, and lower for
1158 * lighter loads). Hard limits are those imposed by the hardware.
1160 * A distinction is made for overclocking, which is never enabled by
1161 * default, and is considered to be above the hard limit if it's
1164 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1165 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1166 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1167 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1168 u8 min_freq; /* AKA RPn. Minimum frequency */
1169 u8 boost_freq; /* Frequency to request when wait boosting */
1170 u8 idle_freq; /* Frequency to request when we are idle */
1171 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1172 u8 rp1_freq; /* "less than" RP0 power/freqency */
1173 u8 rp0_freq; /* Non-overclocked max frequency. */
1174 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1176 u8 up_threshold; /* Current %busy required to uplock */
1177 u8 down_threshold; /* Current %busy required to downclock */
1180 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1182 spinlock_t client_lock;
1183 struct list_head clients;
1187 struct delayed_work autoenable_work;
1190 /* manual wa residency calculations */
1191 struct intel_rps_ei up_ei, down_ei;
1194 * Protects RPS/RC6 register access and PCU communication.
1195 * Must be taken after struct_mutex if nested. Note that
1196 * this lock may be held for long periods of time when
1197 * talking to hw - so only take it when talking to hw!
1199 struct mutex hw_lock;
1202 /* defined intel_pm.c */
1203 extern spinlock_t mchdev_lock;
1205 struct intel_ilk_power_mgmt {
1213 unsigned long last_time1;
1214 unsigned long chipset_power;
1217 unsigned long gfx_power;
1224 struct drm_i915_private;
1225 struct i915_power_well;
1227 struct i915_power_well_ops {
1229 * Synchronize the well's hw state to match the current sw state, for
1230 * example enable/disable it based on the current refcount. Called
1231 * during driver init and resume time, possibly after first calling
1232 * the enable/disable handlers.
1234 void (*sync_hw)(struct drm_i915_private *dev_priv,
1235 struct i915_power_well *power_well);
1237 * Enable the well and resources that depend on it (for example
1238 * interrupts located on the well). Called after the 0->1 refcount
1241 void (*enable)(struct drm_i915_private *dev_priv,
1242 struct i915_power_well *power_well);
1244 * Disable the well and resources that depend on it. Called after
1245 * the 1->0 refcount transition.
1247 void (*disable)(struct drm_i915_private *dev_priv,
1248 struct i915_power_well *power_well);
1249 /* Returns the hw enabled state. */
1250 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1251 struct i915_power_well *power_well);
1254 /* Power well structure for haswell */
1255 struct i915_power_well {
1258 /* power well enable/disable usage count */
1260 /* cached hw enabled state */
1262 unsigned long domains;
1264 const struct i915_power_well_ops *ops;
1267 struct i915_power_domains {
1269 * Power wells needed for initialization at driver init and suspend
1270 * time are on. They are kept on until after the first modeset.
1274 int power_well_count;
1277 int domain_use_count[POWER_DOMAIN_NUM];
1278 struct i915_power_well *power_wells;
1281 #define MAX_L3_SLICES 2
1282 struct intel_l3_parity {
1283 u32 *remap_info[MAX_L3_SLICES];
1284 struct work_struct error_work;
1288 struct i915_gem_mm {
1289 /** Memory allocator for GTT stolen memory */
1290 struct drm_mm stolen;
1291 /** Protects the usage of the GTT stolen memory allocator. This is
1292 * always the inner lock when overlapping with struct_mutex. */
1293 struct mutex stolen_lock;
1295 /** List of all objects in gtt_space. Used to restore gtt
1296 * mappings on resume */
1297 struct list_head bound_list;
1299 * List of objects which are not bound to the GTT (thus
1300 * are idle and not used by the GPU) but still have
1301 * (presumably uncached) pages still attached.
1303 struct list_head unbound_list;
1305 /** Usable portion of the GTT for GEM */
1306 unsigned long stolen_base; /* limited to low memory (32-bit) */
1308 /** PPGTT used for aliasing the PPGTT with the GTT */
1309 struct i915_hw_ppgtt *aliasing_ppgtt;
1311 struct notifier_block oom_notifier;
1312 struct notifier_block vmap_notifier;
1313 struct shrinker shrinker;
1315 /** LRU list of objects with fence regs on them. */
1316 struct list_head fence_list;
1319 * Are we in a non-interruptible section of code like
1324 /* the indicator for dispatch video commands on two BSD rings */
1325 unsigned int bsd_engine_dispatch_index;
1327 /** Bit 6 swizzling required for X tiling */
1328 uint32_t bit_6_swizzle_x;
1329 /** Bit 6 swizzling required for Y tiling */
1330 uint32_t bit_6_swizzle_y;
1332 /* accounting, useful for userland debugging */
1333 spinlock_t object_stat_lock;
1334 size_t object_memory;
1338 struct drm_i915_error_state_buf {
1339 struct drm_i915_private *i915;
1348 struct i915_error_state_file_priv {
1349 struct drm_device *dev;
1350 struct drm_i915_error_state *error;
1353 struct i915_gpu_error {
1354 /* For hangcheck timer */
1355 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1356 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1357 /* Hang gpu twice in this window and your context gets banned */
1358 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1360 struct delayed_work hangcheck_work;
1362 /* For reset and error_state handling. */
1364 /* Protected by the above dev->gpu_error.lock. */
1365 struct drm_i915_error_state *first_error;
1367 unsigned long missed_irq_rings;
1370 * State variable controlling the reset flow and count
1372 * This is a counter which gets incremented when reset is triggered,
1373 * and again when reset has been handled. So odd values (lowest bit set)
1374 * means that reset is in progress and even values that
1375 * (reset_counter >> 1):th reset was successfully completed.
1377 * If reset is not completed succesfully, the I915_WEDGE bit is
1378 * set meaning that hardware is terminally sour and there is no
1379 * recovery. All waiters on the reset_queue will be woken when
1382 * This counter is used by the wait_seqno code to notice that reset
1383 * event happened and it needs to restart the entire ioctl (since most
1384 * likely the seqno it waited for won't ever signal anytime soon).
1386 * This is important for lock-free wait paths, where no contended lock
1387 * naturally enforces the correct ordering between the bail-out of the
1388 * waiter and the gpu reset work code.
1390 atomic_t reset_counter;
1392 #define I915_RESET_IN_PROGRESS_FLAG 1
1393 #define I915_WEDGED (1 << 31)
1396 * Waitqueue to signal when a hang is detected. Used to for waiters
1397 * to release the struct_mutex for the reset to procede.
1399 wait_queue_head_t wait_queue;
1402 * Waitqueue to signal when the reset has completed. Used by clients
1403 * that wait for dev_priv->mm.wedged to settle.
1405 wait_queue_head_t reset_queue;
1407 /* For missed irq/seqno simulation. */
1408 unsigned long test_irq_rings;
1411 enum modeset_restore {
1412 MODESET_ON_LID_OPEN,
1417 #define DP_AUX_A 0x40
1418 #define DP_AUX_B 0x10
1419 #define DP_AUX_C 0x20
1420 #define DP_AUX_D 0x30
1422 #define DDC_PIN_B 0x05
1423 #define DDC_PIN_C 0x04
1424 #define DDC_PIN_D 0x06
1426 struct ddi_vbt_port_info {
1428 * This is an index in the HDMI/DVI DDI buffer translation table.
1429 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1430 * populate this field.
1432 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1433 uint8_t hdmi_level_shift;
1435 uint8_t supports_dvi:1;
1436 uint8_t supports_hdmi:1;
1437 uint8_t supports_dp:1;
1439 uint8_t alternate_aux_channel;
1440 uint8_t alternate_ddc_pin;
1442 uint8_t dp_boost_level;
1443 uint8_t hdmi_boost_level;
1446 enum psr_lines_to_wait {
1447 PSR_0_LINES_TO_WAIT = 0,
1449 PSR_4_LINES_TO_WAIT,
1453 struct intel_vbt_data {
1454 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1455 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1458 unsigned int int_tv_support:1;
1459 unsigned int lvds_dither:1;
1460 unsigned int lvds_vbt:1;
1461 unsigned int int_crt_support:1;
1462 unsigned int lvds_use_ssc:1;
1463 unsigned int display_clock_mode:1;
1464 unsigned int fdi_rx_polarity_inverted:1;
1465 unsigned int panel_type:4;
1467 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1469 enum drrs_support_type drrs_type;
1480 struct edp_power_seq pps;
1485 bool require_aux_wakeup;
1487 enum psr_lines_to_wait lines_to_wait;
1488 int tp1_wakeup_time;
1489 int tp2_tp3_wakeup_time;
1495 bool active_low_pwm;
1496 u8 min_brightness; /* min_brightness/255 of max */
1497 enum intel_backlight_type type;
1503 struct mipi_config *config;
1504 struct mipi_pps_data *pps;
1508 const u8 *sequence[MIPI_SEQ_MAX];
1514 union child_device_config *child_dev;
1516 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1517 struct sdvo_device_mapping sdvo_mappings[2];
1520 enum intel_ddb_partitioning {
1522 INTEL_DDB_PART_5_6, /* IVB+ */
1525 struct intel_wm_level {
1533 struct ilk_wm_values {
1534 uint32_t wm_pipe[3];
1536 uint32_t wm_lp_spr[3];
1537 uint32_t wm_linetime[3];
1539 enum intel_ddb_partitioning partitioning;
1542 struct vlv_pipe_wm {
1553 struct vlv_wm_values {
1554 struct vlv_pipe_wm pipe[3];
1555 struct vlv_sr_wm sr;
1565 struct skl_ddb_entry {
1566 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1569 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1571 return entry->end - entry->start;
1574 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1575 const struct skl_ddb_entry *e2)
1577 if (e1->start == e2->start && e1->end == e2->end)
1583 struct skl_ddb_allocation {
1584 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1585 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1586 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1589 struct skl_wm_values {
1590 unsigned dirty_pipes;
1591 struct skl_ddb_allocation ddb;
1592 uint32_t wm_linetime[I915_MAX_PIPES];
1593 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1594 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1597 struct skl_wm_level {
1598 bool plane_en[I915_MAX_PLANES];
1599 uint16_t plane_res_b[I915_MAX_PLANES];
1600 uint8_t plane_res_l[I915_MAX_PLANES];
1604 * This struct helps tracking the state needed for runtime PM, which puts the
1605 * device in PCI D3 state. Notice that when this happens, nothing on the
1606 * graphics device works, even register access, so we don't get interrupts nor
1609 * Every piece of our code that needs to actually touch the hardware needs to
1610 * either call intel_runtime_pm_get or call intel_display_power_get with the
1611 * appropriate power domain.
1613 * Our driver uses the autosuspend delay feature, which means we'll only really
1614 * suspend if we stay with zero refcount for a certain amount of time. The
1615 * default value is currently very conservative (see intel_runtime_pm_enable), but
1616 * it can be changed with the standard runtime PM files from sysfs.
1618 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1619 * goes back to false exactly before we reenable the IRQs. We use this variable
1620 * to check if someone is trying to enable/disable IRQs while they're supposed
1621 * to be disabled. This shouldn't happen and we'll print some error messages in
1624 * For more, read the Documentation/power/runtime_pm.txt.
1626 struct i915_runtime_pm {
1627 atomic_t wakeref_count;
1628 atomic_t atomic_seq;
1633 enum intel_pipe_crc_source {
1634 INTEL_PIPE_CRC_SOURCE_NONE,
1635 INTEL_PIPE_CRC_SOURCE_PLANE1,
1636 INTEL_PIPE_CRC_SOURCE_PLANE2,
1637 INTEL_PIPE_CRC_SOURCE_PF,
1638 INTEL_PIPE_CRC_SOURCE_PIPE,
1639 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1640 INTEL_PIPE_CRC_SOURCE_TV,
1641 INTEL_PIPE_CRC_SOURCE_DP_B,
1642 INTEL_PIPE_CRC_SOURCE_DP_C,
1643 INTEL_PIPE_CRC_SOURCE_DP_D,
1644 INTEL_PIPE_CRC_SOURCE_AUTO,
1645 INTEL_PIPE_CRC_SOURCE_MAX,
1648 struct intel_pipe_crc_entry {
1653 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1654 struct intel_pipe_crc {
1656 bool opened; /* exclusive access to the result file */
1657 struct intel_pipe_crc_entry *entries;
1658 enum intel_pipe_crc_source source;
1660 wait_queue_head_t wq;
1663 struct i915_frontbuffer_tracking {
1667 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1674 struct i915_wa_reg {
1677 /* bitmask representing WA bits */
1682 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1683 * allowing it for RCS as we don't foresee any requirement of having
1684 * a whitelist for other engines. When it is really required for
1685 * other engines then the limit need to be increased.
1687 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1689 struct i915_workarounds {
1690 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1692 u32 hw_whitelist_count[I915_NUM_ENGINES];
1695 struct i915_virtual_gpu {
1699 /* used in computing the new watermarks state */
1700 struct intel_wm_config {
1701 unsigned int num_pipes_active;
1702 bool sprites_enabled;
1703 bool sprites_scaled;
1706 struct drm_i915_private {
1707 struct drm_device drm;
1709 struct kmem_cache *objects;
1710 struct kmem_cache *vmas;
1711 struct kmem_cache *requests;
1713 const struct intel_device_info info;
1715 int relative_constants_mode;
1719 struct intel_uncore uncore;
1721 struct i915_virtual_gpu vgpu;
1723 struct intel_gvt gvt;
1725 struct intel_guc guc;
1727 struct intel_csr csr;
1729 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1731 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1732 * controller on different i2c buses. */
1733 struct mutex gmbus_mutex;
1736 * Base address of the gmbus and gpio block.
1738 uint32_t gpio_mmio_base;
1740 /* MMIO base address for MIPI regs */
1741 uint32_t mipi_mmio_base;
1743 uint32_t psr_mmio_base;
1745 uint32_t pps_mmio_base;
1747 wait_queue_head_t gmbus_wait_queue;
1749 struct pci_dev *bridge_dev;
1750 struct i915_gem_context *kernel_context;
1751 struct intel_engine_cs engine[I915_NUM_ENGINES];
1752 struct drm_i915_gem_object *semaphore_obj;
1755 struct drm_dma_handle *status_page_dmah;
1756 struct resource mch_res;
1758 /* protects the irq masks */
1759 spinlock_t irq_lock;
1761 /* protects the mmio flip data */
1762 spinlock_t mmio_flip_lock;
1764 bool display_irqs_enabled;
1766 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1767 struct pm_qos_request pm_qos;
1769 /* Sideband mailbox protection */
1770 struct mutex sb_lock;
1772 /** Cached value of IMR to avoid reads in updating the bitfield */
1775 u32 de_irq_mask[I915_MAX_PIPES];
1780 u32 pipestat_irq_mask[I915_MAX_PIPES];
1782 struct i915_hotplug hotplug;
1783 struct intel_fbc fbc;
1784 struct i915_drrs drrs;
1785 struct intel_opregion opregion;
1786 struct intel_vbt_data vbt;
1788 bool preserve_bios_swizzle;
1791 struct intel_overlay *overlay;
1793 /* backlight registers and fields in struct intel_panel */
1794 struct mutex backlight_lock;
1797 bool no_aux_handshake;
1799 /* protects panel power sequencer state */
1800 struct mutex pps_mutex;
1802 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1803 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1805 unsigned int fsb_freq, mem_freq, is_ddr3;
1806 unsigned int skl_preferred_vco_freq;
1807 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1808 unsigned int max_dotclk_freq;
1809 unsigned int rawclk_freq;
1810 unsigned int hpll_freq;
1811 unsigned int czclk_freq;
1814 unsigned int vco, ref;
1818 * wq - Driver workqueue for GEM.
1820 * NOTE: Work items scheduled here are not allowed to grab any modeset
1821 * locks, for otherwise the flushing done in the pageflip code will
1822 * result in deadlocks.
1824 struct workqueue_struct *wq;
1826 /* Display functions */
1827 struct drm_i915_display_funcs display;
1829 /* PCH chipset type */
1830 enum intel_pch pch_type;
1831 unsigned short pch_id;
1833 unsigned long quirks;
1835 enum modeset_restore modeset_restore;
1836 struct mutex modeset_restore_lock;
1837 struct drm_atomic_state *modeset_restore_state;
1838 struct drm_modeset_acquire_ctx reset_ctx;
1840 struct list_head vm_list; /* Global list of all address spaces */
1841 struct i915_ggtt ggtt; /* VM representing the global address space */
1843 struct i915_gem_mm mm;
1844 DECLARE_HASHTABLE(mm_structs, 7);
1845 struct mutex mm_lock;
1847 /* The hw wants to have a stable context identifier for the lifetime
1848 * of the context (for OA, PASID, faults, etc). This is limited
1849 * in execlists to 21 bits.
1851 struct ida context_hw_ida;
1852 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1854 /* Kernel Modesetting */
1856 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1857 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1858 wait_queue_head_t pending_flip_queue;
1860 #ifdef CONFIG_DEBUG_FS
1861 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1864 /* dpll and cdclk state is protected by connection_mutex */
1865 int num_shared_dpll;
1866 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1867 const struct intel_dpll_mgr *dpll_mgr;
1870 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1871 * Must be global rather than per dpll, because on some platforms
1872 * plls share registers.
1874 struct mutex dpll_lock;
1876 unsigned int active_crtcs;
1877 unsigned int min_pixclk[I915_MAX_PIPES];
1879 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1881 struct i915_workarounds workarounds;
1883 struct i915_frontbuffer_tracking fb_tracking;
1887 bool mchbar_need_disable;
1889 struct intel_l3_parity l3_parity;
1891 /* Cannot be determined by PCIID. You must always read a register. */
1894 /* gen6+ rps state */
1895 struct intel_gen6_power_mgmt rps;
1897 /* ilk-only ips/rps state. Everything in here is protected by the global
1898 * mchdev_lock in intel_pm.c */
1899 struct intel_ilk_power_mgmt ips;
1901 struct i915_power_domains power_domains;
1903 struct i915_psr psr;
1905 struct i915_gpu_error gpu_error;
1907 struct drm_i915_gem_object *vlv_pctx;
1909 #ifdef CONFIG_DRM_FBDEV_EMULATION
1910 /* list of fbdev register on this device */
1911 struct intel_fbdev *fbdev;
1912 struct work_struct fbdev_suspend_work;
1915 struct drm_property *broadcast_rgb_property;
1916 struct drm_property *force_audio_property;
1918 /* hda/i915 audio component */
1919 struct i915_audio_component *audio_component;
1920 bool audio_component_registered;
1922 * av_mutex - mutex for audio/video sync
1925 struct mutex av_mutex;
1927 uint32_t hw_context_size;
1928 struct list_head context_list;
1932 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1933 u32 chv_phy_control;
1935 * Shadows for CHV DPLL_MD regs to keep the state
1936 * checker somewhat working in the presence hardware
1937 * crappiness (can't read out DPLL_MD for pipes B & C).
1939 u32 chv_dpll_md[I915_MAX_PIPES];
1943 bool suspended_to_idle;
1944 struct i915_suspend_saved_registers regfile;
1945 struct vlv_s0ix_state vlv_s0ix_state;
1949 * Raw watermark latency values:
1950 * in 0.1us units for WM0,
1951 * in 0.5us units for WM1+.
1954 uint16_t pri_latency[5];
1956 uint16_t spr_latency[5];
1958 uint16_t cur_latency[5];
1960 * Raw watermark memory latency values
1961 * for SKL for all 8 levels
1964 uint16_t skl_latency[8];
1967 * The skl_wm_values structure is a bit too big for stack
1968 * allocation, so we keep the staging struct where we store
1969 * intermediate results here instead.
1971 struct skl_wm_values skl_results;
1973 /* current hardware state */
1975 struct ilk_wm_values hw;
1976 struct skl_wm_values skl_hw;
1977 struct vlv_wm_values vlv;
1983 * Should be held around atomic WM register writing; also
1984 * protects * intel_crtc->wm.active and
1985 * cstate->wm.need_postvbl_update.
1987 struct mutex wm_mutex;
1990 * Set during HW readout of watermarks/DDB. Some platforms
1991 * need to know when we're still using BIOS-provided values
1992 * (which we don't fully trust).
1994 bool distrust_bios_wm;
1997 struct i915_runtime_pm pm;
1999 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2001 void (*cleanup_engine)(struct intel_engine_cs *engine);
2004 * Is the GPU currently considered idle, or busy executing
2005 * userspace requests? Whilst idle, we allow runtime power
2006 * management to power down the hardware and display clocks.
2007 * In order to reduce the effect on performance, there
2008 * is a slight delay before we do so.
2010 unsigned int active_engines;
2014 * We leave the user IRQ off as much as possible,
2015 * but this means that requests will finish and never
2016 * be retired once the system goes idle. Set a timer to
2017 * fire periodically while the ring is running. When it
2018 * fires, go retire requests.
2020 struct delayed_work retire_work;
2023 * When we detect an idle GPU, we want to turn on
2024 * powersaving features. So once we see that there
2025 * are no more requests outstanding and no more
2026 * arrive within a small period of time, we fire
2027 * off the idle_work.
2029 struct delayed_work idle_work;
2032 /* perform PHY state sanity checks? */
2033 bool chv_phy_assert[2];
2035 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
2038 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2039 * will be rejected. Instead look for a better place.
2043 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2045 return container_of(dev, struct drm_i915_private, drm);
2048 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
2050 return to_i915(dev_get_drvdata(dev));
2053 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2055 return container_of(guc, struct drm_i915_private, guc);
2058 /* Simple iterator over all initialised engines */
2059 #define for_each_engine(engine__, dev_priv__) \
2060 for ((engine__) = &(dev_priv__)->engine[0]; \
2061 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2063 for_each_if (intel_engine_initialized(engine__))
2065 /* Iterator with engine_id */
2066 #define for_each_engine_id(engine__, dev_priv__, id__) \
2067 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2068 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2070 for_each_if (((id__) = (engine__)->id, \
2071 intel_engine_initialized(engine__)))
2073 /* Iterator over subset of engines selected by mask */
2074 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2075 for ((engine__) = &(dev_priv__)->engine[0]; \
2076 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2078 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2079 intel_engine_initialized(engine__))
2081 enum hdmi_force_audio {
2082 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2083 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2084 HDMI_AUDIO_AUTO, /* trust EDID */
2085 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2088 #define I915_GTT_OFFSET_NONE ((u32)-1)
2090 struct drm_i915_gem_object_ops {
2092 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2094 /* Interface between the GEM object and its backing storage.
2095 * get_pages() is called once prior to the use of the associated set
2096 * of pages before to binding them into the GTT, and put_pages() is
2097 * called after we no longer need them. As we expect there to be
2098 * associated cost with migrating pages between the backing storage
2099 * and making them available for the GPU (e.g. clflush), we may hold
2100 * onto the pages after they are no longer referenced by the GPU
2101 * in case they may be used again shortly (for example migrating the
2102 * pages to a different memory domain within the GTT). put_pages()
2103 * will therefore most likely be called when the object itself is
2104 * being released or under memory pressure (where we attempt to
2105 * reap pages for the shrinker).
2107 int (*get_pages)(struct drm_i915_gem_object *);
2108 void (*put_pages)(struct drm_i915_gem_object *);
2110 int (*dmabuf_export)(struct drm_i915_gem_object *);
2111 void (*release)(struct drm_i915_gem_object *);
2115 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2116 * considered to be the frontbuffer for the given plane interface-wise. This
2117 * doesn't mean that the hw necessarily already scans it out, but that any
2118 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2120 * We have one bit per pipe and per scanout plane type.
2122 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2123 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2124 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2125 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2126 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2127 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2128 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2129 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2130 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2131 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2132 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2133 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2135 struct drm_i915_gem_object {
2136 struct drm_gem_object base;
2138 const struct drm_i915_gem_object_ops *ops;
2140 /** List of VMAs backed by this object */
2141 struct list_head vma_list;
2143 /** Stolen memory for this object, instead of being backed by shmem. */
2144 struct drm_mm_node *stolen;
2145 struct list_head global_list;
2147 /** Used in execbuf to temporarily hold a ref */
2148 struct list_head obj_exec_link;
2150 struct list_head batch_pool_link;
2152 unsigned long flags;
2154 * This is set if the object is on the active lists (has pending
2155 * rendering and so a non-zero seqno), and is not set if it i s on
2156 * inactive (ready to be unbound) list.
2158 #define I915_BO_ACTIVE_SHIFT 0
2159 #define I915_BO_ACTIVE_MASK ((1 << I915_NUM_ENGINES) - 1)
2160 #define __I915_BO_ACTIVE(bo) \
2161 ((READ_ONCE((bo)->flags) >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK)
2164 * This is set if the object has been written to since last bound
2167 unsigned int dirty:1;
2170 * Fence register bits (if any) for this object. Will be set
2171 * as needed when mapped into the GTT.
2172 * Protected by dev->struct_mutex.
2174 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2177 * Advice: are the backing pages purgeable?
2179 unsigned int madv:2;
2182 * Whether the tiling parameters for the currently associated fence
2183 * register have changed. Note that for the purposes of tracking
2184 * tiling changes we also treat the unfenced register, the register
2185 * slot that the object occupies whilst it executes a fenced
2186 * command (such as BLT on gen2/3), as a "fence".
2188 unsigned int fence_dirty:1;
2191 * Is the object at the current location in the gtt mappable and
2192 * fenceable? Used to avoid costly recalculations.
2194 unsigned int map_and_fenceable:1;
2197 * Whether the current gtt mapping needs to be mappable (and isn't just
2198 * mappable by accident). Track pin and fault separate for a more
2199 * accurate mappable working set.
2201 unsigned int fault_mappable:1;
2204 * Is the object to be mapped as read-only to the GPU
2205 * Only honoured if hardware has relevant pte bit
2207 unsigned long gt_ro:1;
2208 unsigned int cache_level:3;
2209 unsigned int cache_dirty:1;
2211 atomic_t frontbuffer_bits;
2213 /** Current tiling stride for the object, if it's tiled. */
2214 unsigned int tiling_and_stride;
2215 #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
2216 #define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
2217 #define STRIDE_MASK (~TILING_MASK)
2219 unsigned int has_wc_mmap;
2220 /** Count of VMA actually bound by this object */
2221 unsigned int bind_count;
2222 unsigned int pin_display;
2224 struct sg_table *pages;
2225 int pages_pin_count;
2227 struct scatterlist *sg;
2232 /** Breadcrumb of last rendering to the buffer.
2233 * There can only be one writer, but we allow for multiple readers.
2234 * If there is a writer that necessarily implies that all other
2235 * read requests are complete - but we may only be lazily clearing
2236 * the read requests. A read request is naturally the most recent
2237 * request on a ring, so we may have two different write and read
2238 * requests on one ring where the write request is older than the
2239 * read request. This allows for the CPU to read from an active
2240 * buffer by only waiting for the write to complete.
2242 struct i915_gem_active last_read[I915_NUM_ENGINES];
2243 struct i915_gem_active last_write;
2244 struct i915_gem_active last_fence;
2246 /** References from framebuffers, locks out tiling changes. */
2247 unsigned long framebuffer_references;
2249 /** Record of address bit 17 of each page at last unbind. */
2250 unsigned long *bit_17;
2253 /** for phy allocated objects */
2254 struct drm_dma_handle *phys_handle;
2256 struct i915_gem_userptr {
2258 unsigned read_only :1;
2259 unsigned workers :4;
2260 #define I915_GEM_USERPTR_MAX_WORKERS 15
2262 struct i915_mm_struct *mm;
2263 struct i915_mmu_object *mmu_object;
2264 struct work_struct *work;
2269 static inline struct drm_i915_gem_object *
2270 to_intel_bo(struct drm_gem_object *gem)
2272 /* Assert that to_intel_bo(NULL) == NULL */
2273 BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));
2275 return container_of(gem, struct drm_i915_gem_object, base);
2278 static inline struct drm_i915_gem_object *
2279 i915_gem_object_lookup(struct drm_file *file, u32 handle)
2281 return to_intel_bo(drm_gem_object_lookup(file, handle));
2285 extern struct drm_gem_object *
2286 drm_gem_object_lookup(struct drm_file *file, u32 handle);
2288 __attribute__((nonnull))
2289 static inline struct drm_i915_gem_object *
2290 i915_gem_object_get(struct drm_i915_gem_object *obj)
2292 drm_gem_object_reference(&obj->base);
2297 extern void drm_gem_object_reference(struct drm_gem_object *);
2299 __attribute__((nonnull))
2301 i915_gem_object_put(struct drm_i915_gem_object *obj)
2303 drm_gem_object_unreference(&obj->base);
2307 extern void drm_gem_object_unreference(struct drm_gem_object *);
2309 __attribute__((nonnull))
2311 i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj)
2313 drm_gem_object_unreference_unlocked(&obj->base);
2317 extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *);
2320 i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
2322 return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
2325 static inline unsigned long
2326 i915_gem_object_get_active(const struct drm_i915_gem_object *obj)
2328 return (obj->flags >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK;
2332 i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
2334 return i915_gem_object_get_active(obj);
2338 i915_gem_object_set_active(struct drm_i915_gem_object *obj, int engine)
2340 obj->flags |= BIT(engine + I915_BO_ACTIVE_SHIFT);
2344 i915_gem_object_clear_active(struct drm_i915_gem_object *obj, int engine)
2346 obj->flags &= ~BIT(engine + I915_BO_ACTIVE_SHIFT);
2350 i915_gem_object_has_active_engine(const struct drm_i915_gem_object *obj,
2353 return obj->flags & BIT(engine + I915_BO_ACTIVE_SHIFT);
2356 static inline unsigned int
2357 i915_gem_object_get_tiling(struct drm_i915_gem_object *obj)
2359 return obj->tiling_and_stride & TILING_MASK;
2363 i915_gem_object_is_tiled(struct drm_i915_gem_object *obj)
2365 return i915_gem_object_get_tiling(obj) != I915_TILING_NONE;
2368 static inline unsigned int
2369 i915_gem_object_get_stride(struct drm_i915_gem_object *obj)
2371 return obj->tiling_and_stride & STRIDE_MASK;
2375 * Optimised SGL iterator for GEM objects
2377 static __always_inline struct sgt_iter {
2378 struct scatterlist *sgp;
2385 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2386 struct sgt_iter s = { .sgp = sgl };
2389 s.max = s.curr = s.sgp->offset;
2390 s.max += s.sgp->length;
2392 s.dma = sg_dma_address(s.sgp);
2394 s.pfn = page_to_pfn(sg_page(s.sgp));
2401 * __sg_next - return the next scatterlist entry in a list
2402 * @sg: The current sg entry
2405 * If the entry is the last, return NULL; otherwise, step to the next
2406 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2407 * otherwise just return the pointer to the current element.
2409 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2411 #ifdef CONFIG_DEBUG_SG
2412 BUG_ON(sg->sg_magic != SG_MAGIC);
2414 return sg_is_last(sg) ? NULL :
2415 likely(!sg_is_chain(++sg)) ? sg :
2420 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2421 * @__dmap: DMA address (output)
2422 * @__iter: 'struct sgt_iter' (iterator state, internal)
2423 * @__sgt: sg_table to iterate over (input)
2425 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2426 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2427 ((__dmap) = (__iter).dma + (__iter).curr); \
2428 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2429 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2432 * for_each_sgt_page - iterate over the pages of the given sg_table
2433 * @__pp: page pointer (output)
2434 * @__iter: 'struct sgt_iter' (iterator state, internal)
2435 * @__sgt: sg_table to iterate over (input)
2437 #define for_each_sgt_page(__pp, __iter, __sgt) \
2438 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2439 ((__pp) = (__iter).pfn == 0 ? NULL : \
2440 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2441 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2442 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2445 * A command that requires special handling by the command parser.
2447 struct drm_i915_cmd_descriptor {
2449 * Flags describing how the command parser processes the command.
2451 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2452 * a length mask if not set
2453 * CMD_DESC_SKIP: The command is allowed but does not follow the
2454 * standard length encoding for the opcode range in
2456 * CMD_DESC_REJECT: The command is never allowed
2457 * CMD_DESC_REGISTER: The command should be checked against the
2458 * register whitelist for the appropriate ring
2459 * CMD_DESC_MASTER: The command is allowed if the submitting process
2463 #define CMD_DESC_FIXED (1<<0)
2464 #define CMD_DESC_SKIP (1<<1)
2465 #define CMD_DESC_REJECT (1<<2)
2466 #define CMD_DESC_REGISTER (1<<3)
2467 #define CMD_DESC_BITMASK (1<<4)
2468 #define CMD_DESC_MASTER (1<<5)
2471 * The command's unique identification bits and the bitmask to get them.
2472 * This isn't strictly the opcode field as defined in the spec and may
2473 * also include type, subtype, and/or subop fields.
2481 * The command's length. The command is either fixed length (i.e. does
2482 * not include a length field) or has a length field mask. The flag
2483 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2484 * a length mask. All command entries in a command table must include
2485 * length information.
2493 * Describes where to find a register address in the command to check
2494 * against the ring's register whitelist. Only valid if flags has the
2495 * CMD_DESC_REGISTER bit set.
2497 * A non-zero step value implies that the command may access multiple
2498 * registers in sequence (e.g. LRI), in that case step gives the
2499 * distance in dwords between individual offset fields.
2507 #define MAX_CMD_DESC_BITMASKS 3
2509 * Describes command checks where a particular dword is masked and
2510 * compared against an expected value. If the command does not match
2511 * the expected value, the parser rejects it. Only valid if flags has
2512 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2515 * If the check specifies a non-zero condition_mask then the parser
2516 * only performs the check when the bits specified by condition_mask
2523 u32 condition_offset;
2525 } bits[MAX_CMD_DESC_BITMASKS];
2529 * A table of commands requiring special handling by the command parser.
2531 * Each engine has an array of tables. Each table consists of an array of
2532 * command descriptors, which must be sorted with command opcodes in
2535 struct drm_i915_cmd_table {
2536 const struct drm_i915_cmd_descriptor *table;
2540 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2541 #define __I915__(p) ({ \
2542 struct drm_i915_private *__p; \
2543 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2544 __p = (struct drm_i915_private *)p; \
2545 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2546 __p = to_i915((struct drm_device *)p); \
2551 #define INTEL_INFO(p) (&__I915__(p)->info)
2552 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2553 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2555 #define REVID_FOREVER 0xff
2556 #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
2558 #define GEN_FOREVER (0)
2560 * Returns true if Gen is in inclusive range [Start, End].
2562 * Use GEN_FOREVER for unbound start and or end.
2564 #define IS_GEN(p, s, e) ({ \
2565 unsigned int __s = (s), __e = (e); \
2566 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2567 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2568 if ((__s) != GEN_FOREVER) \
2570 if ((__e) == GEN_FOREVER) \
2571 __e = BITS_PER_LONG - 1; \
2574 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2578 * Return true if revision is in range [since,until] inclusive.
2580 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2582 #define IS_REVID(p, since, until) \
2583 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2585 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2586 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2587 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2588 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2589 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2590 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2591 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2592 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2593 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2594 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2595 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2596 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2597 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2598 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2599 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2600 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2601 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2602 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2603 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2604 INTEL_DEVID(dev) == 0x0152 || \
2605 INTEL_DEVID(dev) == 0x015a)
2606 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2607 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2608 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2609 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
2610 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2611 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2612 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2613 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2614 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2615 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2616 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2617 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2618 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2619 (INTEL_DEVID(dev) & 0xf) == 0xe))
2620 /* ULX machines are also considered ULT. */
2621 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2622 (INTEL_DEVID(dev) & 0xf) == 0xe)
2623 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2624 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2625 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2626 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2627 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2628 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2629 /* ULX machines are also considered ULT. */
2630 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2631 INTEL_DEVID(dev) == 0x0A1E)
2632 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2633 INTEL_DEVID(dev) == 0x1913 || \
2634 INTEL_DEVID(dev) == 0x1916 || \
2635 INTEL_DEVID(dev) == 0x1921 || \
2636 INTEL_DEVID(dev) == 0x1926)
2637 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2638 INTEL_DEVID(dev) == 0x1915 || \
2639 INTEL_DEVID(dev) == 0x191E)
2640 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2641 INTEL_DEVID(dev) == 0x5913 || \
2642 INTEL_DEVID(dev) == 0x5916 || \
2643 INTEL_DEVID(dev) == 0x5921 || \
2644 INTEL_DEVID(dev) == 0x5926)
2645 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2646 INTEL_DEVID(dev) == 0x5915 || \
2647 INTEL_DEVID(dev) == 0x591E)
2648 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2649 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2650 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2651 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2653 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2655 #define SKL_REVID_A0 0x0
2656 #define SKL_REVID_B0 0x1
2657 #define SKL_REVID_C0 0x2
2658 #define SKL_REVID_D0 0x3
2659 #define SKL_REVID_E0 0x4
2660 #define SKL_REVID_F0 0x5
2661 #define SKL_REVID_G0 0x6
2662 #define SKL_REVID_H0 0x7
2664 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2666 #define BXT_REVID_A0 0x0
2667 #define BXT_REVID_A1 0x1
2668 #define BXT_REVID_B0 0x3
2669 #define BXT_REVID_C0 0x9
2671 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2673 #define KBL_REVID_A0 0x0
2674 #define KBL_REVID_B0 0x1
2675 #define KBL_REVID_C0 0x2
2676 #define KBL_REVID_D0 0x3
2677 #define KBL_REVID_E0 0x4
2679 #define IS_KBL_REVID(p, since, until) \
2680 (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2683 * The genX designation typically refers to the render engine, so render
2684 * capability related checks should use IS_GEN, while display and other checks
2685 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2688 #define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
2689 #define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
2690 #define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
2691 #define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
2692 #define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
2693 #define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
2694 #define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
2695 #define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
2697 #define ENGINE_MASK(id) BIT(id)
2698 #define RENDER_RING ENGINE_MASK(RCS)
2699 #define BSD_RING ENGINE_MASK(VCS)
2700 #define BLT_RING ENGINE_MASK(BCS)
2701 #define VEBOX_RING ENGINE_MASK(VECS)
2702 #define BSD2_RING ENGINE_MASK(VCS2)
2703 #define ALL_ENGINES (~0)
2705 #define HAS_ENGINE(dev_priv, id) \
2706 (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2708 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2709 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2710 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2711 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2713 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2714 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2715 #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2716 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2718 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2720 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2721 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2722 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2723 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2724 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2726 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2727 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2729 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2730 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2732 /* WaRsDisableCoarsePowerGating:skl,bxt */
2733 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2734 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2735 IS_SKL_GT3(dev_priv) || \
2736 IS_SKL_GT4(dev_priv))
2739 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2740 * even when in MSI mode. This results in spurious interrupt warnings if the
2741 * legacy irq no. is shared with another device. The kernel then disables that
2742 * interrupt source and so prevents the other device from working properly.
2744 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2745 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2747 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2748 * rows, which changed the alignment requirements and fence programming.
2750 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2752 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2753 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2755 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2756 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2757 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2759 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2761 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2762 INTEL_INFO(dev)->gen >= 9)
2764 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2765 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2766 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2767 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2768 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2769 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2770 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2771 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2772 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2773 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2774 #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
2776 #define HAS_CSR(dev) (IS_GEN9(dev))
2779 * For now, anything with a GuC requires uCode loading, and then supports
2780 * command submission once loaded. But these are logically independent
2781 * properties, so we have separate macros to test them.
2783 #define HAS_GUC(dev) (IS_GEN9(dev))
2784 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2785 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2787 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2788 INTEL_INFO(dev)->gen >= 8)
2790 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2791 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2794 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2796 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2797 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2798 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2799 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2800 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2801 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2802 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2803 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2804 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2805 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2806 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2807 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2809 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2810 #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2811 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2812 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2813 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2814 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2815 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2816 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2817 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2818 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2820 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2821 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2823 /* DPF == dynamic parity feature */
2824 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2825 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2827 #define GT_FREQUENCY_MULTIPLIER 50
2828 #define GEN9_FREQ_SCALER 3
2830 #include "i915_trace.h"
2832 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2834 #ifdef CONFIG_INTEL_IOMMU
2835 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2841 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2842 extern int i915_resume_switcheroo(struct drm_device *dev);
2844 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2847 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2851 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2852 const char *fmt, ...);
2854 #define i915_report_error(dev_priv, fmt, ...) \
2855 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2857 #ifdef CONFIG_COMPAT
2858 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2861 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2862 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2863 extern int i915_reset(struct drm_i915_private *dev_priv);
2864 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2865 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2866 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2867 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2868 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2869 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2870 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2872 /* intel_hotplug.c */
2873 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2874 u32 pin_mask, u32 long_mask);
2875 void intel_hpd_init(struct drm_i915_private *dev_priv);
2876 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2877 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2878 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2879 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2880 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2883 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2885 unsigned long delay;
2887 if (unlikely(!i915.enable_hangcheck))
2890 /* Don't continually defer the hangcheck so that it is always run at
2891 * least once after work has been scheduled on any ring. Otherwise,
2892 * we will ignore a hung ring if a second ring is kept busy.
2895 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2896 queue_delayed_work(system_long_wq,
2897 &dev_priv->gpu_error.hangcheck_work, delay);
2901 void i915_handle_error(struct drm_i915_private *dev_priv,
2903 const char *fmt, ...);
2905 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2906 int intel_irq_install(struct drm_i915_private *dev_priv);
2907 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2909 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
2910 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2911 bool restore_forcewake);
2912 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2913 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2914 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2915 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
2916 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
2918 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2919 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2920 enum forcewake_domains domains);
2921 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2922 enum forcewake_domains domains);
2923 /* Like above but the caller must manage the uncore.lock itself.
2924 * Must be used with I915_READ_FW and friends.
2926 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2927 enum forcewake_domains domains);
2928 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2929 enum forcewake_domains domains);
2930 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
2932 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2934 int intel_wait_for_register(struct drm_i915_private *dev_priv,
2938 const unsigned long timeout_ms);
2939 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
2943 const unsigned long timeout_ms);
2945 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2947 return dev_priv->gvt.initialized;
2950 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2952 return dev_priv->vgpu.active;
2956 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2960 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2963 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2964 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2965 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2968 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2969 uint32_t interrupt_mask,
2970 uint32_t enabled_irq_mask);
2972 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2974 ilk_update_display_irq(dev_priv, bits, bits);
2977 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2979 ilk_update_display_irq(dev_priv, bits, 0);
2981 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2983 uint32_t interrupt_mask,
2984 uint32_t enabled_irq_mask);
2985 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2986 enum pipe pipe, uint32_t bits)
2988 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2990 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2991 enum pipe pipe, uint32_t bits)
2993 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2995 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2996 uint32_t interrupt_mask,
2997 uint32_t enabled_irq_mask);
2999 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3001 ibx_display_interrupt_update(dev_priv, bits, bits);
3004 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3006 ibx_display_interrupt_update(dev_priv, bits, 0);
3010 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3011 struct drm_file *file_priv);
3012 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3013 struct drm_file *file_priv);
3014 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3015 struct drm_file *file_priv);
3016 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3017 struct drm_file *file_priv);
3018 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3019 struct drm_file *file_priv);
3020 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3021 struct drm_file *file_priv);
3022 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3023 struct drm_file *file_priv);
3024 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3025 struct drm_file *file_priv);
3026 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3027 struct drm_file *file_priv);
3028 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3029 struct drm_file *file_priv);
3030 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3031 struct drm_file *file);
3032 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3033 struct drm_file *file);
3034 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3035 struct drm_file *file_priv);
3036 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3037 struct drm_file *file_priv);
3038 int i915_gem_set_tiling(struct drm_device *dev, void *data,
3039 struct drm_file *file_priv);
3040 int i915_gem_get_tiling(struct drm_device *dev, void *data,
3041 struct drm_file *file_priv);
3042 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3043 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3044 struct drm_file *file);
3045 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3046 struct drm_file *file_priv);
3047 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3048 struct drm_file *file_priv);
3049 void i915_gem_load_init(struct drm_device *dev);
3050 void i915_gem_load_cleanup(struct drm_device *dev);
3051 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3052 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3054 void *i915_gem_object_alloc(struct drm_device *dev);
3055 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3056 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3057 const struct drm_i915_gem_object_ops *ops);
3058 struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
3060 struct drm_i915_gem_object *i915_gem_object_create_from_data(
3061 struct drm_device *dev, const void *data, size_t size);
3062 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3063 void i915_gem_free_object(struct drm_gem_object *obj);
3066 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3067 const struct i915_ggtt_view *view,
3072 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3074 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
3075 int __must_check i915_vma_unbind(struct i915_vma *vma);
3076 void i915_vma_close(struct i915_vma *vma);
3077 void i915_vma_destroy(struct i915_vma *vma);
3079 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3080 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
3081 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
3082 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3084 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3085 int *needs_clflush);
3087 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3089 static inline int __sg_page_count(struct scatterlist *sg)
3091 return sg->length >> PAGE_SHIFT;
3095 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
3097 static inline dma_addr_t
3098 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n)
3100 if (n < obj->get_page.last) {
3101 obj->get_page.sg = obj->pages->sgl;
3102 obj->get_page.last = 0;
3105 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3106 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3107 if (unlikely(sg_is_chain(obj->get_page.sg)))
3108 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3111 return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT);
3114 static inline struct page *
3115 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3117 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
3120 if (n < obj->get_page.last) {
3121 obj->get_page.sg = obj->pages->sgl;
3122 obj->get_page.last = 0;
3125 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3126 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3127 if (unlikely(sg_is_chain(obj->get_page.sg)))
3128 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3131 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3134 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3136 BUG_ON(obj->pages == NULL);
3137 obj->pages_pin_count++;
3140 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3142 BUG_ON(obj->pages_pin_count == 0);
3143 obj->pages_pin_count--;
3147 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3148 * @obj - the object to map into kernel address space
3150 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3151 * pages and then returns a contiguous mapping of the backing storage into
3152 * the kernel address space.
3154 * The caller must hold the struct_mutex, and is responsible for calling
3155 * i915_gem_object_unpin_map() when the mapping is no longer required.
3157 * Returns the pointer through which to access the mapped object, or an
3158 * ERR_PTR() on error.
3160 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj);
3163 * i915_gem_object_unpin_map - releases an earlier mapping
3164 * @obj - the object to unmap
3166 * After pinning the object and mapping its pages, once you are finished
3167 * with your access, call i915_gem_object_unpin_map() to release the pin
3168 * upon the mapping. Once the pin count reaches zero, that mapping may be
3171 * The caller must hold the struct_mutex.
3173 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3175 lockdep_assert_held(&obj->base.dev->struct_mutex);
3176 i915_gem_object_unpin_pages(obj);
3179 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3180 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3181 struct drm_i915_gem_request *to);
3182 void i915_vma_move_to_active(struct i915_vma *vma,
3183 struct drm_i915_gem_request *req,
3184 unsigned int flags);
3185 int i915_gem_dumb_create(struct drm_file *file_priv,
3186 struct drm_device *dev,
3187 struct drm_mode_create_dumb *args);
3188 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3189 uint32_t handle, uint64_t *offset);
3191 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3192 struct drm_i915_gem_object *new,
3193 unsigned frontbuffer_bits);
3195 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3197 struct drm_i915_gem_request *
3198 i915_gem_find_active_request(struct intel_engine_cs *engine);
3200 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3202 static inline u32 i915_reset_counter(struct i915_gpu_error *error)
3204 return atomic_read(&error->reset_counter);
3207 static inline bool __i915_reset_in_progress(u32 reset)
3209 return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
3212 static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
3214 return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3217 static inline bool __i915_terminally_wedged(u32 reset)
3219 return unlikely(reset & I915_WEDGED);
3222 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3224 return __i915_reset_in_progress(i915_reset_counter(error));
3227 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3229 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
3232 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3234 return __i915_terminally_wedged(i915_reset_counter(error));
3237 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3239 return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
3242 void i915_gem_reset(struct drm_device *dev);
3243 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3244 int __must_check i915_gem_init(struct drm_device *dev);
3245 int __must_check i915_gem_init_hw(struct drm_device *dev);
3246 void i915_gem_init_swizzling(struct drm_device *dev);
3247 void i915_gem_cleanup_engines(struct drm_device *dev);
3248 int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3249 bool interruptible);
3250 int __must_check i915_gem_suspend(struct drm_device *dev);
3251 void i915_gem_resume(struct drm_device *dev);
3252 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3254 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3257 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3260 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3262 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3264 const struct i915_ggtt_view *view);
3265 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3266 const struct i915_ggtt_view *view);
3267 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3269 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3270 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3272 u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
3274 u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
3275 int tiling_mode, bool fenced);
3277 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3278 enum i915_cache_level cache_level);
3280 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3281 struct dma_buf *dma_buf);
3283 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3284 struct drm_gem_object *gem_obj, int flags);
3286 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3287 const struct i915_ggtt_view *view);
3288 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3289 struct i915_address_space *vm);
3291 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3293 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3296 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3297 const struct i915_ggtt_view *view);
3298 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3299 struct i915_address_space *vm);
3302 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3303 struct i915_address_space *vm);
3305 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3306 const struct i915_ggtt_view *view);
3309 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3310 struct i915_address_space *vm);
3312 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3313 const struct i915_ggtt_view *view);
3315 static inline struct i915_vma *
3316 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3318 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3320 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3322 /* Some GGTT VM helpers */
3323 static inline struct i915_hw_ppgtt *
3324 i915_vm_to_ppgtt(struct i915_address_space *vm)
3326 return container_of(vm, struct i915_hw_ppgtt, base);
3329 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3331 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3335 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj);
3337 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3338 const struct i915_ggtt_view *view);
3340 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3342 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3345 /* i915_gem_fence.c */
3346 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3347 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3349 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3350 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3352 void i915_gem_restore_fences(struct drm_device *dev);
3354 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3355 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3356 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3358 /* i915_gem_context.c */
3359 int __must_check i915_gem_context_init(struct drm_device *dev);
3360 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3361 void i915_gem_context_fini(struct drm_device *dev);
3362 void i915_gem_context_reset(struct drm_device *dev);
3363 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3364 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3365 int i915_switch_context(struct drm_i915_gem_request *req);
3366 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3367 void i915_gem_context_free(struct kref *ctx_ref);
3368 struct drm_i915_gem_object *
3369 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3370 struct i915_gem_context *
3371 i915_gem_context_create_gvt(struct drm_device *dev);
3373 static inline struct i915_gem_context *
3374 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3376 struct i915_gem_context *ctx;
3378 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3380 ctx = idr_find(&file_priv->context_idr, id);
3382 return ERR_PTR(-ENOENT);
3387 static inline struct i915_gem_context *
3388 i915_gem_context_get(struct i915_gem_context *ctx)
3390 kref_get(&ctx->ref);
3394 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3396 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3397 kref_put(&ctx->ref, i915_gem_context_free);
3400 static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3402 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3405 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3406 struct drm_file *file);
3407 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3408 struct drm_file *file);
3409 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3410 struct drm_file *file_priv);
3411 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3412 struct drm_file *file_priv);
3413 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
3414 struct drm_file *file);
3416 /* i915_gem_evict.c */
3417 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3418 u64 min_size, u64 alignment,
3419 unsigned cache_level,
3422 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3423 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3425 /* belongs in i915_gem_gtt.h */
3426 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3428 if (INTEL_GEN(dev_priv) < 6)
3429 intel_gtt_chipset_flush();
3432 /* i915_gem_stolen.c */
3433 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3434 struct drm_mm_node *node, u64 size,
3435 unsigned alignment);
3436 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3437 struct drm_mm_node *node, u64 size,
3438 unsigned alignment, u64 start,
3440 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3441 struct drm_mm_node *node);
3442 int i915_gem_init_stolen(struct drm_device *dev);
3443 void i915_gem_cleanup_stolen(struct drm_device *dev);
3444 struct drm_i915_gem_object *
3445 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3446 struct drm_i915_gem_object *
3447 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3452 /* i915_gem_shrinker.c */
3453 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3454 unsigned long target,
3456 #define I915_SHRINK_PURGEABLE 0x1
3457 #define I915_SHRINK_UNBOUND 0x2
3458 #define I915_SHRINK_BOUND 0x4
3459 #define I915_SHRINK_ACTIVE 0x8
3460 #define I915_SHRINK_VMAPS 0x10
3461 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3462 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3463 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3466 /* i915_gem_tiling.c */
3467 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3469 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3471 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3472 i915_gem_object_is_tiled(obj);
3475 /* i915_debugfs.c */
3476 #ifdef CONFIG_DEBUG_FS
3477 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3478 void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3479 int i915_debugfs_connector_add(struct drm_connector *connector);
3480 void intel_display_crc_init(struct drm_device *dev);
3482 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3483 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3484 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3486 static inline void intel_display_crc_init(struct drm_device *dev) {}
3489 /* i915_gpu_error.c */
3491 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3492 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3493 const struct i915_error_state_file_priv *error);
3494 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3495 struct drm_i915_private *i915,
3496 size_t count, loff_t pos);
3497 static inline void i915_error_state_buf_release(
3498 struct drm_i915_error_state_buf *eb)
3502 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3504 const char *error_msg);
3505 void i915_error_state_get(struct drm_device *dev,
3506 struct i915_error_state_file_priv *error_priv);
3507 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3508 void i915_destroy_error_state(struct drm_device *dev);
3510 void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
3511 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3513 /* i915_cmd_parser.c */
3514 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3515 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3516 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3517 bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine);
3518 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3519 struct drm_i915_gem_object *batch_obj,
3520 struct drm_i915_gem_object *shadow_batch_obj,
3521 u32 batch_start_offset,
3525 /* i915_suspend.c */
3526 extern int i915_save_state(struct drm_device *dev);
3527 extern int i915_restore_state(struct drm_device *dev);
3530 void i915_setup_sysfs(struct drm_device *dev_priv);
3531 void i915_teardown_sysfs(struct drm_device *dev_priv);
3534 extern int intel_setup_gmbus(struct drm_device *dev);
3535 extern void intel_teardown_gmbus(struct drm_device *dev);
3536 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3539 extern struct i2c_adapter *
3540 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3541 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3542 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3543 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3545 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3547 extern void intel_i2c_reset(struct drm_device *dev);
3550 int intel_bios_init(struct drm_i915_private *dev_priv);
3551 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3552 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3553 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3554 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3555 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3556 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3557 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3558 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3561 /* intel_opregion.c */
3563 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3564 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3565 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3566 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3567 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3569 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3571 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3573 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3574 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3575 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3576 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3580 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3585 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3589 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3597 extern void intel_register_dsm_handler(void);
3598 extern void intel_unregister_dsm_handler(void);
3600 static inline void intel_register_dsm_handler(void) { return; }
3601 static inline void intel_unregister_dsm_handler(void) { return; }
3602 #endif /* CONFIG_ACPI */
3604 /* intel_device_info.c */
3605 static inline struct intel_device_info *
3606 mkwrite_device_info(struct drm_i915_private *dev_priv)
3608 return (struct intel_device_info *)&dev_priv->info;
3611 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3612 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3615 extern void intel_modeset_init_hw(struct drm_device *dev);
3616 extern void intel_modeset_init(struct drm_device *dev);
3617 extern void intel_modeset_gem_init(struct drm_device *dev);
3618 extern void intel_modeset_cleanup(struct drm_device *dev);
3619 extern int intel_connector_register(struct drm_connector *);
3620 extern void intel_connector_unregister(struct drm_connector *);
3621 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3622 extern void intel_display_resume(struct drm_device *dev);
3623 extern void i915_redisable_vga(struct drm_device *dev);
3624 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3625 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3626 extern void intel_init_pch_refclk(struct drm_device *dev);
3627 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3628 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3631 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3632 struct drm_file *file);
3635 extern struct intel_overlay_error_state *
3636 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3637 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3638 struct intel_overlay_error_state *error);
3640 extern struct intel_display_error_state *
3641 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3642 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3643 struct drm_device *dev,
3644 struct intel_display_error_state *error);
3646 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3647 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3649 /* intel_sideband.c */
3650 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3651 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3652 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3653 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3654 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3655 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3656 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3657 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3658 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3659 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3660 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3661 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3662 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3663 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3664 enum intel_sbi_destination destination);
3665 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3666 enum intel_sbi_destination destination);
3667 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3668 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3670 /* intel_dpio_phy.c */
3671 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3672 u32 deemph_reg_value, u32 margin_reg_value,
3673 bool uniq_trans_scale);
3674 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3676 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3677 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3678 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3679 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3681 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3682 u32 demph_reg_value, u32 preemph_reg_value,
3683 u32 uniqtranscale_reg_value, u32 tx3_demph);
3684 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3685 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3686 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3688 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3689 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3691 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3692 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3694 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3695 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3696 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3697 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3699 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3700 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3701 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3702 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3704 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3705 * will be implemented using 2 32-bit writes in an arbitrary order with
3706 * an arbitrary delay between them. This can cause the hardware to
3707 * act upon the intermediate value, possibly leading to corruption and
3708 * machine death. You have been warned.
3710 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3711 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3713 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3714 u32 upper, lower, old_upper, loop = 0; \
3715 upper = I915_READ(upper_reg); \
3717 old_upper = upper; \
3718 lower = I915_READ(lower_reg); \
3719 upper = I915_READ(upper_reg); \
3720 } while (upper != old_upper && loop++ < 2); \
3721 (u64)upper << 32 | lower; })
3723 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3724 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3726 #define __raw_read(x, s) \
3727 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3730 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3733 #define __raw_write(x, s) \
3734 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3735 i915_reg_t reg, uint##x##_t val) \
3737 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3752 /* These are untraced mmio-accessors that are only valid to be used inside
3753 * criticial sections inside IRQ handlers where forcewake is explicitly
3755 * Think twice, and think again, before using these.
3756 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3757 * intel_uncore_forcewake_irqunlock().
3759 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3760 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3761 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3762 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3764 /* "Broadcast RGB" property */
3765 #define INTEL_BROADCAST_RGB_AUTO 0
3766 #define INTEL_BROADCAST_RGB_FULL 1
3767 #define INTEL_BROADCAST_RGB_LIMITED 2
3769 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3771 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3772 return VLV_VGACNTRL;
3773 else if (INTEL_INFO(dev)->gen >= 5)
3774 return CPU_VGACNTRL;
3779 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3781 unsigned long j = msecs_to_jiffies(m);
3783 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3786 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3788 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3791 static inline unsigned long
3792 timespec_to_jiffies_timeout(const struct timespec *value)
3794 unsigned long j = timespec_to_jiffies(value);
3796 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3800 * If you need to wait X milliseconds between events A and B, but event B
3801 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3802 * when event A happened, then just before event B you call this function and
3803 * pass the timestamp as the first argument, and X as the second argument.
3806 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3808 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3811 * Don't re-read the value of "jiffies" every time since it may change
3812 * behind our back and break the math.
3814 tmp_jiffies = jiffies;
3815 target_jiffies = timestamp_jiffies +
3816 msecs_to_jiffies_timeout(to_wait_ms);
3818 if (time_after(target_jiffies, tmp_jiffies)) {
3819 remaining_jiffies = target_jiffies - tmp_jiffies;
3820 while (remaining_jiffies)
3822 schedule_timeout_uninterruptible(remaining_jiffies);
3825 static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
3827 struct intel_engine_cs *engine = req->engine;
3829 /* Before we do the heavier coherent read of the seqno,
3830 * check the value (hopefully) in the CPU cacheline.
3832 if (i915_gem_request_completed(req))
3835 /* Ensure our read of the seqno is coherent so that we
3836 * do not "miss an interrupt" (i.e. if this is the last
3837 * request and the seqno write from the GPU is not visible
3838 * by the time the interrupt fires, we will see that the
3839 * request is incomplete and go back to sleep awaiting
3840 * another interrupt that will never come.)
3842 * Strictly, we only need to do this once after an interrupt,
3843 * but it is easier and safer to do it every time the waiter
3846 if (engine->irq_seqno_barrier &&
3847 rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
3848 cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
3849 struct task_struct *tsk;
3851 /* The ordering of irq_posted versus applying the barrier
3852 * is crucial. The clearing of the current irq_posted must
3853 * be visible before we perform the barrier operation,
3854 * such that if a subsequent interrupt arrives, irq_posted
3855 * is reasserted and our task rewoken (which causes us to
3856 * do another __i915_request_irq_complete() immediately
3857 * and reapply the barrier). Conversely, if the clear
3858 * occurs after the barrier, then an interrupt that arrived
3859 * whilst we waited on the barrier would not trigger a
3860 * barrier on the next pass, and the read may not see the
3863 engine->irq_seqno_barrier(engine);
3865 /* If we consume the irq, but we are no longer the bottom-half,
3866 * the real bottom-half may not have serialised their own
3867 * seqno check with the irq-barrier (i.e. may have inspected
3868 * the seqno before we believe it coherent since they see
3869 * irq_posted == false but we are still running).
3872 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
3873 if (tsk && tsk != current)
3874 /* Note that if the bottom-half is changed as we
3875 * are sending the wake-up, the new bottom-half will
3876 * be woken by whomever made the change. We only have
3877 * to worry about when we steal the irq-posted for
3880 wake_up_process(tsk);
3883 if (i915_gem_request_completed(req))
3887 /* We need to check whether any gpu reset happened in between
3888 * the request being submitted and now. If a reset has occurred,
3889 * the seqno will have been advance past ours and our request
3890 * is complete. If we are in the process of handling a reset,
3891 * the request is effectively complete as the rendering will
3892 * be discarded, but we need to return in order to drop the
3895 if (i915_reset_in_progress(&req->i915->gpu_error))