1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include <linux/io-mapping.h>
36 /* General customization:
39 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41 #define DRIVER_NAME "i915"
42 #define DRIVER_DESC "Intel Graphics"
43 #define DRIVER_DATE "20080730"
50 #define I915_NUM_PIPE 2
55 * 1.2: Add Power Management
56 * 1.3: Add vblank support
57 * 1.4: Fix cmdbuffer path, add heap destroy
58 * 1.5: Add vblank pipe configuration
59 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
60 * - Support vertical blank on secondary display pipe
62 #define DRIVER_MAJOR 1
63 #define DRIVER_MINOR 6
64 #define DRIVER_PATCHLEVEL 0
66 #define WATCH_COHERENCY 0
71 #define WATCH_INACTIVE 0
72 #define WATCH_PWRITE 0
74 typedef struct _drm_i915_ring_buffer {
82 struct drm_gem_object *ring_obj;
83 } drm_i915_ring_buffer_t;
86 struct mem_block *next;
87 struct mem_block *prev;
90 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
93 struct opregion_header;
95 struct opregion_swsci;
98 struct intel_opregion {
99 struct opregion_header *header;
100 struct opregion_acpi *acpi;
101 struct opregion_swsci *swsci;
102 struct opregion_asle *asle;
106 struct drm_i915_master_private {
107 drm_local_map_t *sarea;
108 struct _drm_i915_sarea *sarea_priv;
110 #define I915_FENCE_REG_NONE -1
112 struct drm_i915_fence_reg {
113 struct drm_gem_object *obj;
116 typedef struct drm_i915_private {
117 struct drm_device *dev;
123 drm_i915_ring_buffer_t ring;
125 drm_dma_handle_t *status_page_dmah;
126 void *hw_status_page;
127 dma_addr_t dma_status_page;
129 unsigned int status_gfx_addr;
130 drm_local_map_t hws_map;
131 struct drm_gem_object *hws_obj;
139 wait_queue_head_t irq_queue;
140 atomic_t irq_received;
141 /** Protects user_irq_refcount and irq_mask_reg */
142 spinlock_t user_irq_lock;
143 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
144 int user_irq_refcount;
145 /** Cached value of IMR to avoid reads in updating the bitfield */
149 int tex_lru_log_granularity;
150 int allow_batchbuffer;
151 struct mem_block *agp_heap;
152 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
155 struct intel_opregion opregion;
157 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
158 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
159 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
166 u32 saveRENDERSTANDBY;
190 u32 savePFIT_PGM_RATIOS;
192 u32 saveBLC_PWM_CTL2;
217 u32 savePP_ON_DELAYS;
218 u32 savePP_OFF_DELAYS;
226 u32 savePFIT_CONTROL;
227 u32 save_palette_a[256];
228 u32 save_palette_b[256];
229 u32 saveFBC_CFB_BASE;
232 u32 saveFBC_CONTROL2;
236 u32 saveCACHE_MODE_0;
239 u32 saveMI_ARB_STATE;
249 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
253 struct drm_mm gtt_space;
255 struct io_mapping *gtt_mapping;
258 * List of objects currently involved in rendering from the
261 * Includes buffers having the contents of their GPU caches
262 * flushed, not necessarily primitives. last_rendering_seqno
263 * represents when the rendering involved will be completed.
265 * A reference is held on the buffer while on this list.
267 struct list_head active_list;
270 * List of objects which are not in the ringbuffer but which
271 * still have a write_domain which needs to be flushed before
274 * last_rendering_seqno is 0 while an object is in this list.
276 * A reference is held on the buffer while on this list.
278 struct list_head flushing_list;
281 * LRU list of objects which are not in the ringbuffer and
282 * are ready to unbind, but are still in the GTT.
284 * last_rendering_seqno is 0 while an object is in this list.
286 * A reference is not held on the buffer while on this list,
287 * as merely being GTT-bound shouldn't prevent its being
288 * freed, and we'll pull it off the list in the free path.
290 struct list_head inactive_list;
293 * List of breadcrumbs associated with GPU requests currently
296 struct list_head request_list;
299 * We leave the user IRQ off as much as possible,
300 * but this means that requests will finish and never
301 * be retired once the system goes idle. Set a timer to
302 * fire periodically while the ring is running. When it
303 * fires, go retire requests.
305 struct delayed_work retire_work;
307 uint32_t next_gem_seqno;
310 * Waiting sequence number, if any
312 uint32_t waiting_gem_seqno;
315 * Last seq seen at irq time
317 uint32_t irq_gem_seqno;
320 * Flag if the X Server, and thus DRM, is not currently in
321 * control of the device.
323 * This is set between LeaveVT and EnterVT. It needs to be
324 * replaced with a semaphore. It also needs to be
325 * transitioned away from for kernel modesetting.
330 * Flag if the hardware appears to be wedged.
332 * This is set when attempts to idle the device timeout.
333 * It prevents command submission from occuring and makes
334 * every pending request fail
338 /** Bit 6 swizzling required for X tiling */
339 uint32_t bit_6_swizzle_x;
340 /** Bit 6 swizzling required for Y tiling */
341 uint32_t bit_6_swizzle_y;
343 } drm_i915_private_t;
345 /** driver private structure attached to each drm_gem_object */
346 struct drm_i915_gem_object {
347 struct drm_gem_object *obj;
349 /** Current space allocated to this object in the GTT, if any. */
350 struct drm_mm_node *gtt_space;
352 /** This object's place on the active/flushing/inactive lists */
353 struct list_head list;
356 * This is set if the object is on the active or flushing lists
357 * (has pending rendering), and is not set if it's on inactive (ready
363 * This is set if the object has been written to since last bound
368 /** AGP memory structure for our GTT binding. */
369 DRM_AGP_MEM *agp_mem;
371 struct page **page_list;
374 * Current offset of the object in GTT space.
376 * This is the same as gtt_space->start
380 * Required alignment for the object
382 uint32_t gtt_alignment;
384 * Fake offset for use by mmap(2)
386 uint64_t mmap_offset;
389 * Fence register bits (if any) for this object. Will be set
390 * as needed when mapped into the GTT.
391 * Protected by dev->struct_mutex.
395 /** Boolean whether this object has a valid gtt offset. */
398 /** How many users have pinned this object in GTT space */
401 /** Breadcrumb of last rendering to the buffer. */
402 uint32_t last_rendering_seqno;
404 /** Current tiling mode for the object. */
405 uint32_t tiling_mode;
408 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
412 * If present, while GEM_DOMAIN_CPU is in the read domain this array
413 * flags which individual pages are valid.
415 uint8_t *page_cpu_valid;
419 * Request queue structure.
421 * The request queue allows us to note sequence numbers that have been emitted
422 * and may be associated with active buffers to be retired.
424 * By keeping this list, we can avoid having to do questionable
425 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
426 * an emission time with seqnos for tracking how far ahead of the GPU we are.
428 struct drm_i915_gem_request {
429 /** GEM sequence number associated with this request. */
432 /** Time at which this request was emitted, in jiffies. */
433 unsigned long emitted_jiffies;
435 struct list_head list;
438 struct drm_i915_file_private {
440 uint32_t last_gem_seqno;
441 uint32_t last_gem_throttle_seqno;
445 extern struct drm_ioctl_desc i915_ioctls[];
446 extern int i915_max_ioctl;
448 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
449 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
452 extern void i915_kernel_lost_context(struct drm_device * dev);
453 extern int i915_driver_load(struct drm_device *, unsigned long flags);
454 extern int i915_driver_unload(struct drm_device *);
455 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
456 extern void i915_driver_lastclose(struct drm_device * dev);
457 extern void i915_driver_preclose(struct drm_device *dev,
458 struct drm_file *file_priv);
459 extern void i915_driver_postclose(struct drm_device *dev,
460 struct drm_file *file_priv);
461 extern int i915_driver_device_is_agp(struct drm_device * dev);
462 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
464 extern int i915_emit_box(struct drm_device *dev,
465 struct drm_clip_rect __user *boxes,
466 int i, int DR1, int DR4);
469 extern int i915_irq_emit(struct drm_device *dev, void *data,
470 struct drm_file *file_priv);
471 extern int i915_irq_wait(struct drm_device *dev, void *data,
472 struct drm_file *file_priv);
473 void i915_user_irq_get(struct drm_device *dev);
474 void i915_user_irq_put(struct drm_device *dev);
476 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
477 extern void i915_driver_irq_preinstall(struct drm_device * dev);
478 extern int i915_driver_irq_postinstall(struct drm_device *dev);
479 extern void i915_driver_irq_uninstall(struct drm_device * dev);
480 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
481 struct drm_file *file_priv);
482 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
483 struct drm_file *file_priv);
484 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
485 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
486 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
487 extern int i915_vblank_swap(struct drm_device *dev, void *data,
488 struct drm_file *file_priv);
489 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
492 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
495 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
499 extern int i915_mem_alloc(struct drm_device *dev, void *data,
500 struct drm_file *file_priv);
501 extern int i915_mem_free(struct drm_device *dev, void *data,
502 struct drm_file *file_priv);
503 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
504 struct drm_file *file_priv);
505 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
506 struct drm_file *file_priv);
507 extern void i915_mem_takedown(struct mem_block **heap);
508 extern void i915_mem_release(struct drm_device * dev,
509 struct drm_file *file_priv, struct mem_block *heap);
511 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
512 struct drm_file *file_priv);
513 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
514 struct drm_file *file_priv);
515 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
516 struct drm_file *file_priv);
517 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
518 struct drm_file *file_priv);
519 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
520 struct drm_file *file_priv);
521 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
522 struct drm_file *file_priv);
523 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
524 struct drm_file *file_priv);
525 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
526 struct drm_file *file_priv);
527 int i915_gem_execbuffer(struct drm_device *dev, void *data,
528 struct drm_file *file_priv);
529 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
530 struct drm_file *file_priv);
531 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
532 struct drm_file *file_priv);
533 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
534 struct drm_file *file_priv);
535 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
536 struct drm_file *file_priv);
537 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
538 struct drm_file *file_priv);
539 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
540 struct drm_file *file_priv);
541 int i915_gem_set_tiling(struct drm_device *dev, void *data,
542 struct drm_file *file_priv);
543 int i915_gem_get_tiling(struct drm_device *dev, void *data,
544 struct drm_file *file_priv);
545 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
546 struct drm_file *file_priv);
547 void i915_gem_load(struct drm_device *dev);
548 int i915_gem_proc_init(struct drm_minor *minor);
549 void i915_gem_proc_cleanup(struct drm_minor *minor);
550 int i915_gem_init_object(struct drm_gem_object *obj);
551 void i915_gem_free_object(struct drm_gem_object *obj);
552 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
553 void i915_gem_object_unpin(struct drm_gem_object *obj);
554 void i915_gem_lastclose(struct drm_device *dev);
555 uint32_t i915_get_gem_seqno(struct drm_device *dev);
556 void i915_gem_retire_requests(struct drm_device *dev);
557 void i915_gem_retire_work_handler(struct work_struct *work);
558 void i915_gem_clflush_object(struct drm_gem_object *obj);
559 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
561 /* i915_gem_tiling.c */
562 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
564 /* i915_gem_debug.c */
565 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
566 const char *where, uint32_t mark);
568 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
570 #define i915_verify_inactive(dev, file, line)
572 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
573 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
574 const char *where, uint32_t mark);
575 void i915_dump_lru(struct drm_device *dev, const char *where);
578 extern int i915_save_state(struct drm_device *dev);
579 extern int i915_restore_state(struct drm_device *dev);
582 extern int i915_save_state(struct drm_device *dev);
583 extern int i915_restore_state(struct drm_device *dev);
586 /* i915_opregion.c */
587 extern int intel_opregion_init(struct drm_device *dev);
588 extern void intel_opregion_free(struct drm_device *dev);
589 extern void opregion_asle_intr(struct drm_device *dev);
590 extern void opregion_enable_asle(struct drm_device *dev);
592 static inline int intel_opregion_init(struct drm_device *dev) { return 0; }
593 static inline void intel_opregion_free(struct drm_device *dev) { return; }
594 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
595 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
599 * Lock test for when it's just for synchronization of ring access.
601 * In that case, we don't need to do it when GEM is initialized as nobody else
602 * has access to the ring.
604 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
605 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
606 LOCK_TEST_WITH_RETURN(dev, file_priv); \
609 #define I915_READ(reg) readl(dev_priv->regs + (reg))
610 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
611 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
612 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
613 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
614 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
616 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
618 #define I915_WRITE64(reg, val) (writel(val, dev_priv->regs + (reg)), \
619 writel(upper_32_bits(val), dev_priv->regs + \
623 #define I915_VERBOSE 0
625 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
628 #define BEGIN_LP_RING(n) do { \
630 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
631 if (dev_priv->ring.space < (n)*4) \
632 i915_wait_ring(dev, (n)*4, __func__); \
634 outring = dev_priv->ring.tail; \
635 ringmask = dev_priv->ring.tail_mask; \
636 virt = dev_priv->ring.virtual_start; \
639 #define OUT_RING(n) do { \
640 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
641 *(volatile unsigned int *)(virt + outring) = (n); \
644 outring &= ringmask; \
647 #define ADVANCE_LP_RING() do { \
648 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
649 dev_priv->ring.tail = outring; \
650 dev_priv->ring.space -= outcount * 4; \
651 I915_WRITE(PRB0_TAIL, outring); \
655 * Reads a dword out of the status page, which is written to from the command
656 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
659 * The following dwords have a reserved meaning:
660 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
661 * 0x04: ring 0 head pointer
662 * 0x05: ring 1 head pointer (915-class)
663 * 0x06: ring 2 head pointer (915-class)
664 * 0x10-0x1b: Context status DWords (GM45)
665 * 0x1f: Last written status offset. (GM45)
667 * The area from dword 0x20 to 0x3ff is available for driver usage.
669 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
670 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
671 #define I915_GEM_HWS_INDEX 0x20
672 #define I915_BREADCRUMB_INDEX 0x21
674 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
676 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
677 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
678 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
679 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
680 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
682 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
683 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
684 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
685 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
686 (dev)->pci_device == 0x27AE)
687 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
688 (dev)->pci_device == 0x2982 || \
689 (dev)->pci_device == 0x2992 || \
690 (dev)->pci_device == 0x29A2 || \
691 (dev)->pci_device == 0x2A02 || \
692 (dev)->pci_device == 0x2A12 || \
693 (dev)->pci_device == 0x2A42 || \
694 (dev)->pci_device == 0x2E02 || \
695 (dev)->pci_device == 0x2E12 || \
696 (dev)->pci_device == 0x2E22)
698 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
700 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
702 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
703 (dev)->pci_device == 0x2E12 || \
704 (dev)->pci_device == 0x2E22)
706 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
707 (dev)->pci_device == 0x29B2 || \
708 (dev)->pci_device == 0x29D2)
710 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
711 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
713 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
714 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
716 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
718 #define PRIMARY_RINGBUFFER_SIZE (128*1024)