1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "i915_params.h"
39 #include "intel_bios.h"
40 #include "intel_ringbuffer.h"
41 #include "intel_lrc.h"
42 #include "i915_gem_gtt.h"
43 #include "i915_gem_render_state.h"
44 #include <linux/io-mapping.h>
45 #include <linux/i2c.h>
46 #include <linux/i2c-algo-bit.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <linux/backlight.h>
51 #include <linux/hashtable.h>
52 #include <linux/intel-iommu.h>
53 #include <linux/kref.h>
54 #include <linux/pm_qos.h>
55 #include "intel_guc.h"
57 /* General customization:
60 #define DRIVER_NAME "i915"
61 #define DRIVER_DESC "Intel Graphics"
62 #define DRIVER_DATE "20151218"
65 /* Many gcc seem to no see through this and fall over :( */
67 #define WARN_ON(x) ({ \
68 bool __i915_warn_cond = (x); \
69 if (__builtin_constant_p(__i915_warn_cond)) \
70 BUILD_BUG_ON(__i915_warn_cond); \
71 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
73 #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
77 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
79 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
80 (long) (x), __func__);
82 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
83 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
84 * which may not necessarily be a user visible problem. This will either
85 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
86 * enable distros and users to tailor their preferred amount of i915 abrt
89 #define I915_STATE_WARN(condition, format...) ({ \
90 int __ret_warn_on = !!(condition); \
91 if (unlikely(__ret_warn_on)) { \
92 if (i915.verbose_state_checks) \
97 unlikely(__ret_warn_on); \
100 #define I915_STATE_WARN_ON(condition) ({ \
101 int __ret_warn_on = !!(condition); \
102 if (unlikely(__ret_warn_on)) { \
103 if (i915.verbose_state_checks) \
104 WARN(1, "WARN_ON(" #condition ")\n"); \
106 DRM_ERROR("WARN_ON(" #condition ")\n"); \
108 unlikely(__ret_warn_on); \
111 static inline const char *yesno(bool v)
113 return v ? "yes" : "no";
122 I915_MAX_PIPES = _PIPE_EDP
124 #define pipe_name(p) ((p) + 'A')
133 #define transcoder_name(t) ((t) + 'A')
136 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
137 * number of planes per CRTC. Not all platforms really have this many planes,
138 * which means some arrays of size I915_MAX_PLANES may have unused entries
139 * between the topmost sprite plane and the cursor plane.
148 #define plane_name(p) ((p) + 'A')
150 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
160 #define port_name(p) ((p) + 'A')
162 #define I915_NUM_PHYS_VLV 2
174 enum intel_display_power_domain {
178 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
179 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
180 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
181 POWER_DOMAIN_TRANSCODER_A,
182 POWER_DOMAIN_TRANSCODER_B,
183 POWER_DOMAIN_TRANSCODER_C,
184 POWER_DOMAIN_TRANSCODER_EDP,
185 POWER_DOMAIN_PORT_DDI_A_LANES,
186 POWER_DOMAIN_PORT_DDI_B_LANES,
187 POWER_DOMAIN_PORT_DDI_C_LANES,
188 POWER_DOMAIN_PORT_DDI_D_LANES,
189 POWER_DOMAIN_PORT_DDI_E_LANES,
190 POWER_DOMAIN_PORT_DSI,
191 POWER_DOMAIN_PORT_CRT,
192 POWER_DOMAIN_PORT_OTHER,
201 POWER_DOMAIN_MODESET,
207 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
208 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
209 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
210 #define POWER_DOMAIN_TRANSCODER(tran) \
211 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
212 (tran) + POWER_DOMAIN_TRANSCODER_A)
216 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
228 #define for_each_hpd_pin(__pin) \
229 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
231 struct i915_hotplug {
232 struct work_struct hotplug_work;
235 unsigned long last_jiffies;
240 HPD_MARK_DISABLED = 2
242 } stats[HPD_NUM_PINS];
244 struct delayed_work reenable_work;
246 struct intel_digital_port *irq_port[I915_MAX_PORTS];
249 struct work_struct dig_port_work;
252 * if we get a HPD irq from DP and a HPD irq from non-DP
253 * the non-DP HPD could block the workqueue on a mode config
254 * mutex getting, that userspace may have taken. However
255 * userspace is waiting on the DP workqueue to run which is
256 * blocked behind the non-DP one.
258 struct workqueue_struct *dp_wq;
261 #define I915_GEM_GPU_DOMAINS \
262 (I915_GEM_DOMAIN_RENDER | \
263 I915_GEM_DOMAIN_SAMPLER | \
264 I915_GEM_DOMAIN_COMMAND | \
265 I915_GEM_DOMAIN_INSTRUCTION | \
266 I915_GEM_DOMAIN_VERTEX)
268 #define for_each_pipe(__dev_priv, __p) \
269 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
270 #define for_each_plane(__dev_priv, __pipe, __p) \
272 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
274 #define for_each_sprite(__dev_priv, __p, __s) \
276 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
279 #define for_each_crtc(dev, crtc) \
280 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
282 #define for_each_intel_plane(dev, intel_plane) \
283 list_for_each_entry(intel_plane, \
284 &dev->mode_config.plane_list, \
287 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
288 list_for_each_entry(intel_plane, \
289 &(dev)->mode_config.plane_list, \
291 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
293 #define for_each_intel_crtc(dev, intel_crtc) \
294 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
296 #define for_each_intel_encoder(dev, intel_encoder) \
297 list_for_each_entry(intel_encoder, \
298 &(dev)->mode_config.encoder_list, \
301 #define for_each_intel_connector(dev, intel_connector) \
302 list_for_each_entry(intel_connector, \
303 &dev->mode_config.connector_list, \
306 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
307 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
308 for_each_if ((intel_encoder)->base.crtc == (__crtc))
310 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
311 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
312 for_each_if ((intel_connector)->base.encoder == (__encoder))
314 #define for_each_power_domain(domain, mask) \
315 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
316 for_each_if ((1 << (domain)) & (mask))
318 struct drm_i915_private;
319 struct i915_mm_struct;
320 struct i915_mmu_object;
322 struct drm_i915_file_private {
323 struct drm_i915_private *dev_priv;
324 struct drm_file *file;
328 struct list_head request_list;
329 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
330 * chosen to prevent the CPU getting more than a frame ahead of the GPU
331 * (when using lax throttling for the frontbuffer). We also use it to
332 * offer free GPU waitboosts for severely congested workloads.
334 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
336 struct idr context_idr;
338 struct intel_rps_client {
339 struct list_head link;
343 struct intel_engine_cs *bsd_ring;
347 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
348 /* real shared dpll ids must be >= 0 */
349 DPLL_ID_PCH_PLL_A = 0,
350 DPLL_ID_PCH_PLL_B = 1,
357 DPLL_ID_SKL_DPLL1 = 0,
358 DPLL_ID_SKL_DPLL2 = 1,
359 DPLL_ID_SKL_DPLL3 = 2,
361 #define I915_NUM_PLLS 3
363 struct intel_dpll_hw_state {
376 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
377 * lower part of ctrl1 and they get shifted into position when writing
378 * the register. This allows us to easily compare the state to share
382 /* HDMI only, 0 when used for DP */
383 uint32_t cfgcr1, cfgcr2;
386 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
390 struct intel_shared_dpll_config {
391 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
392 struct intel_dpll_hw_state hw_state;
395 struct intel_shared_dpll {
396 struct intel_shared_dpll_config config;
398 int active; /* count of number of active CRTCs (i.e. DPMS on) */
399 bool on; /* is the PLL actually active? Disabled during modeset */
401 /* should match the index in the dev_priv->shared_dplls array */
402 enum intel_dpll_id id;
403 /* The mode_set hook is optional and should be used together with the
404 * intel_prepare_shared_dpll function. */
405 void (*mode_set)(struct drm_i915_private *dev_priv,
406 struct intel_shared_dpll *pll);
407 void (*enable)(struct drm_i915_private *dev_priv,
408 struct intel_shared_dpll *pll);
409 void (*disable)(struct drm_i915_private *dev_priv,
410 struct intel_shared_dpll *pll);
411 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
412 struct intel_shared_dpll *pll,
413 struct intel_dpll_hw_state *hw_state);
421 /* Used by dp and fdi links */
422 struct intel_link_m_n {
430 void intel_link_compute_m_n(int bpp, int nlanes,
431 int pixel_clock, int link_clock,
432 struct intel_link_m_n *m_n);
434 /* Interface history:
437 * 1.2: Add Power Management
438 * 1.3: Add vblank support
439 * 1.4: Fix cmdbuffer path, add heap destroy
440 * 1.5: Add vblank pipe configuration
441 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
442 * - Support vertical blank on secondary display pipe
444 #define DRIVER_MAJOR 1
445 #define DRIVER_MINOR 6
446 #define DRIVER_PATCHLEVEL 0
448 #define WATCH_LISTS 0
450 struct opregion_header;
451 struct opregion_acpi;
452 struct opregion_swsci;
453 struct opregion_asle;
455 struct intel_opregion {
456 struct opregion_header *header;
457 struct opregion_acpi *acpi;
458 struct opregion_swsci *swsci;
459 u32 swsci_gbda_sub_functions;
460 u32 swsci_sbcb_sub_functions;
461 struct opregion_asle *asle;
466 struct work_struct asle_work;
468 #define OPREGION_SIZE (8*1024)
470 struct intel_overlay;
471 struct intel_overlay_error_state;
473 #define I915_FENCE_REG_NONE -1
474 #define I915_MAX_NUM_FENCES 32
475 /* 32 fences + sign bit for FENCE_REG_NONE */
476 #define I915_MAX_NUM_FENCE_BITS 6
478 struct drm_i915_fence_reg {
479 struct list_head lru_list;
480 struct drm_i915_gem_object *obj;
484 struct sdvo_device_mapping {
493 struct intel_display_error_state;
495 struct drm_i915_error_state {
504 /* Generic register state */
512 u32 error; /* gen6+ */
513 u32 err_int; /* gen7 */
514 u32 fault_data0; /* gen8, gen9 */
515 u32 fault_data1; /* gen8, gen9 */
521 u32 extra_instdone[I915_NUM_INSTDONE_REG];
522 u64 fence[I915_MAX_NUM_FENCES];
523 struct intel_overlay_error_state *overlay;
524 struct intel_display_error_state *display;
525 struct drm_i915_error_object *semaphore_obj;
527 struct drm_i915_error_ring {
529 /* Software tracked state */
532 enum intel_ring_hangcheck_action hangcheck_action;
535 /* our own tracking of ring head and tail */
539 u32 semaphore_seqno[I915_NUM_RINGS - 1];
558 u32 rc_psmi; /* sleep state */
559 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
561 struct drm_i915_error_object {
565 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
567 struct drm_i915_error_request {
582 char comm[TASK_COMM_LEN];
583 } ring[I915_NUM_RINGS];
585 struct drm_i915_error_buffer {
588 u32 rseqno[I915_NUM_RINGS], wseqno;
592 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
600 } **active_bo, **pinned_bo;
602 u32 *active_bo_count, *pinned_bo_count;
606 struct intel_connector;
607 struct intel_encoder;
608 struct intel_crtc_state;
609 struct intel_initial_plane_config;
614 struct drm_i915_display_funcs {
615 int (*get_display_clock_speed)(struct drm_device *dev);
616 int (*get_fifo_size)(struct drm_device *dev, int plane);
618 * find_dpll() - Find the best values for the PLL
619 * @limit: limits for the PLL
620 * @crtc: current CRTC
621 * @target: target frequency in kHz
622 * @refclk: reference clock frequency in kHz
623 * @match_clock: if provided, @best_clock P divider must
624 * match the P divider from @match_clock
625 * used for LVDS downclocking
626 * @best_clock: best PLL values found
628 * Returns true on success, false on failure.
630 bool (*find_dpll)(const struct intel_limit *limit,
631 struct intel_crtc_state *crtc_state,
632 int target, int refclk,
633 struct dpll *match_clock,
634 struct dpll *best_clock);
635 int (*compute_pipe_wm)(struct intel_crtc *crtc,
636 struct drm_atomic_state *state);
637 void (*update_wm)(struct drm_crtc *crtc);
638 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
639 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
640 /* Returns the active state of the crtc, and if the crtc is active,
641 * fills out the pipe-config with the hw state. */
642 bool (*get_pipe_config)(struct intel_crtc *,
643 struct intel_crtc_state *);
644 void (*get_initial_plane_config)(struct intel_crtc *,
645 struct intel_initial_plane_config *);
646 int (*crtc_compute_clock)(struct intel_crtc *crtc,
647 struct intel_crtc_state *crtc_state);
648 void (*crtc_enable)(struct drm_crtc *crtc);
649 void (*crtc_disable)(struct drm_crtc *crtc);
650 void (*audio_codec_enable)(struct drm_connector *connector,
651 struct intel_encoder *encoder,
652 const struct drm_display_mode *adjusted_mode);
653 void (*audio_codec_disable)(struct intel_encoder *encoder);
654 void (*fdi_link_train)(struct drm_crtc *crtc);
655 void (*init_clock_gating)(struct drm_device *dev);
656 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
657 struct drm_framebuffer *fb,
658 struct drm_i915_gem_object *obj,
659 struct drm_i915_gem_request *req,
661 void (*update_primary_plane)(struct drm_crtc *crtc,
662 struct drm_framebuffer *fb,
664 void (*hpd_irq_setup)(struct drm_device *dev);
665 /* clock updates for mode set */
667 /* render clock increase/decrease */
668 /* display clock increase/decrease */
669 /* pll clock increase/decrease */
672 enum forcewake_domain_id {
673 FW_DOMAIN_ID_RENDER = 0,
674 FW_DOMAIN_ID_BLITTER,
680 enum forcewake_domains {
681 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
682 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
683 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
684 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
689 struct intel_uncore_funcs {
690 void (*force_wake_get)(struct drm_i915_private *dev_priv,
691 enum forcewake_domains domains);
692 void (*force_wake_put)(struct drm_i915_private *dev_priv,
693 enum forcewake_domains domains);
695 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
696 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
697 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
698 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
700 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
701 uint8_t val, bool trace);
702 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
703 uint16_t val, bool trace);
704 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
705 uint32_t val, bool trace);
706 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
707 uint64_t val, bool trace);
710 struct intel_uncore {
711 spinlock_t lock; /** lock is also taken in irq contexts. */
713 struct intel_uncore_funcs funcs;
716 enum forcewake_domains fw_domains;
718 struct intel_uncore_forcewake_domain {
719 struct drm_i915_private *i915;
720 enum forcewake_domain_id id;
722 struct timer_list timer;
729 } fw_domain[FW_DOMAIN_ID_COUNT];
732 /* Iterate over initialised fw domains */
733 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
734 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
735 (i__) < FW_DOMAIN_ID_COUNT; \
736 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
737 for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
739 #define for_each_fw_domain(domain__, dev_priv__, i__) \
740 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
742 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
743 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
744 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
747 struct work_struct work;
749 uint32_t *dmc_payload;
750 uint32_t dmc_fw_size;
753 i915_reg_t mmioaddr[8];
754 uint32_t mmiodata[8];
757 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
758 func(is_mobile) sep \
761 func(is_i945gm) sep \
763 func(need_gfx_hws) sep \
765 func(is_pineview) sep \
766 func(is_broadwater) sep \
767 func(is_crestline) sep \
768 func(is_ivybridge) sep \
769 func(is_valleyview) sep \
770 func(is_cherryview) sep \
771 func(is_haswell) sep \
772 func(is_skylake) sep \
773 func(is_broxton) sep \
774 func(is_kabylake) sep \
775 func(is_preliminary) sep \
777 func(has_pipe_cxsr) sep \
778 func(has_hotplug) sep \
779 func(cursor_needs_physical) sep \
780 func(has_overlay) sep \
781 func(overlay_needs_physical) sep \
782 func(supports_tv) sep \
787 #define DEFINE_FLAG(name) u8 name:1
788 #define SEP_SEMICOLON ;
790 struct intel_device_info {
791 u32 display_mmio_offset;
794 u8 num_sprites[I915_MAX_PIPES];
796 u8 ring_mask; /* Rings supported by the HW */
797 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
798 /* Register offsets for the various display pipes and transcoders */
799 int pipe_offsets[I915_MAX_TRANSCODERS];
800 int trans_offsets[I915_MAX_TRANSCODERS];
801 int palette_offsets[I915_MAX_PIPES];
802 int cursor_offsets[I915_MAX_PIPES];
804 /* Slice/subslice/EU info */
807 u8 subslice_per_slice;
810 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
813 u8 has_subslice_pg:1;
820 enum i915_cache_level {
822 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
823 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
824 caches, eg sampler/render caches, and the
825 large Last-Level-Cache. LLC is coherent with
826 the CPU, but L3 is only visible to the GPU. */
827 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
830 struct i915_ctx_hang_stats {
831 /* This context had batch pending when hang was declared */
832 unsigned batch_pending;
834 /* This context had batch active when hang was declared */
835 unsigned batch_active;
837 /* Time when this context was last blamed for a GPU reset */
838 unsigned long guilty_ts;
840 /* If the contexts causes a second GPU hang within this time,
841 * it is permanently banned from submitting any more work.
843 unsigned long ban_period_seconds;
845 /* This context is banned to submit more work */
849 /* This must match up with the value previously used for execbuf2.rsvd1. */
850 #define DEFAULT_CONTEXT_HANDLE 0
852 #define CONTEXT_NO_ZEROMAP (1<<0)
854 * struct intel_context - as the name implies, represents a context.
855 * @ref: reference count.
856 * @user_handle: userspace tracking identity for this context.
857 * @remap_slice: l3 row remapping information.
858 * @flags: context specific flags:
859 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
860 * @file_priv: filp associated with this context (NULL for global default
862 * @hang_stats: information about the role of this context in possible GPU
864 * @ppgtt: virtual memory space used by this context.
865 * @legacy_hw_ctx: render context backing object and whether it is correctly
866 * initialized (legacy ring submission mechanism only).
867 * @link: link in the global list of contexts.
869 * Contexts are memory images used by the hardware to store copies of their
872 struct intel_context {
876 struct drm_i915_private *i915;
878 struct drm_i915_file_private *file_priv;
879 struct i915_ctx_hang_stats hang_stats;
880 struct i915_hw_ppgtt *ppgtt;
882 /* Legacy ring buffer submission */
884 struct drm_i915_gem_object *rcs_state;
890 struct drm_i915_gem_object *state;
891 struct intel_ringbuffer *ringbuf;
893 } engine[I915_NUM_RINGS];
895 struct list_head link;
907 /* This is always the inner lock when overlapping with struct_mutex and
908 * it's the outer lock when overlapping with stolen_lock. */
912 unsigned int possible_framebuffer_bits;
913 unsigned int busy_bits;
914 struct intel_crtc *crtc;
917 struct drm_mm_node compressed_fb;
918 struct drm_mm_node *compressed_llb;
925 struct intel_fbc_work {
927 struct work_struct work;
928 struct drm_framebuffer *fb;
929 unsigned long enable_jiffies;
932 const char *no_fbc_reason;
934 bool (*is_active)(struct drm_i915_private *dev_priv);
935 void (*activate)(struct intel_crtc *crtc);
936 void (*deactivate)(struct drm_i915_private *dev_priv);
940 * HIGH_RR is the highest eDP panel refresh rate read from EDID
941 * LOW_RR is the lowest eDP panel refresh rate found from EDID
942 * parsing for same resolution.
944 enum drrs_refresh_rate_type {
947 DRRS_MAX_RR, /* RR count */
950 enum drrs_support_type {
951 DRRS_NOT_SUPPORTED = 0,
952 STATIC_DRRS_SUPPORT = 1,
953 SEAMLESS_DRRS_SUPPORT = 2
959 struct delayed_work work;
961 unsigned busy_frontbuffer_bits;
962 enum drrs_refresh_rate_type refresh_rate_type;
963 enum drrs_support_type type;
970 struct intel_dp *enabled;
972 struct delayed_work work;
973 unsigned busy_frontbuffer_bits;
979 PCH_NONE = 0, /* No PCH present */
980 PCH_IBX, /* Ibexpeak PCH */
981 PCH_CPT, /* Cougarpoint PCH */
982 PCH_LPT, /* Lynxpoint PCH */
983 PCH_SPT, /* Sunrisepoint PCH */
987 enum intel_sbi_destination {
992 #define QUIRK_PIPEA_FORCE (1<<0)
993 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
994 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
995 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
996 #define QUIRK_PIPEB_FORCE (1<<4)
997 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1000 struct intel_fbc_work;
1002 struct intel_gmbus {
1003 struct i2c_adapter adapter;
1006 i915_reg_t gpio_reg;
1007 struct i2c_algo_bit_data bit_algo;
1008 struct drm_i915_private *dev_priv;
1011 struct i915_suspend_saved_registers {
1014 u32 savePP_ON_DELAYS;
1015 u32 savePP_OFF_DELAYS;
1020 u32 saveFBC_CONTROL;
1021 u32 saveCACHE_MODE_0;
1022 u32 saveMI_ARB_STATE;
1026 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1027 u32 savePCH_PORT_HOTPLUG;
1031 struct vlv_s0ix_state {
1038 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1039 u32 media_max_req_count;
1040 u32 gfx_max_req_count;
1066 u32 rp_down_timeout;
1072 /* Display 1 CZ domain */
1077 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1079 /* GT SA CZ domain */
1086 /* Display 2 CZ domain */
1090 u32 clock_gate_dis2;
1093 struct intel_rps_ei {
1099 struct intel_gen6_power_mgmt {
1101 * work, interrupts_enabled and pm_iir are protected by
1102 * dev_priv->irq_lock
1104 struct work_struct work;
1105 bool interrupts_enabled;
1108 /* Frequencies are stored in potentially platform dependent multiples.
1109 * In other words, *_freq needs to be multiplied by X to be interesting.
1110 * Soft limits are those which are used for the dynamic reclocking done
1111 * by the driver (raise frequencies under heavy loads, and lower for
1112 * lighter loads). Hard limits are those imposed by the hardware.
1114 * A distinction is made for overclocking, which is never enabled by
1115 * default, and is considered to be above the hard limit if it's
1118 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1119 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1120 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1121 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1122 u8 min_freq; /* AKA RPn. Minimum frequency */
1123 u8 idle_freq; /* Frequency to request when we are idle */
1124 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1125 u8 rp1_freq; /* "less than" RP0 power/freqency */
1126 u8 rp0_freq; /* Non-overclocked max frequency. */
1128 u8 up_threshold; /* Current %busy required to uplock */
1129 u8 down_threshold; /* Current %busy required to downclock */
1132 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1134 spinlock_t client_lock;
1135 struct list_head clients;
1139 struct delayed_work delayed_resume_work;
1142 struct intel_rps_client semaphores, mmioflips;
1144 /* manual wa residency calculations */
1145 struct intel_rps_ei up_ei, down_ei;
1148 * Protects RPS/RC6 register access and PCU communication.
1149 * Must be taken after struct_mutex if nested. Note that
1150 * this lock may be held for long periods of time when
1151 * talking to hw - so only take it when talking to hw!
1153 struct mutex hw_lock;
1156 /* defined intel_pm.c */
1157 extern spinlock_t mchdev_lock;
1159 struct intel_ilk_power_mgmt {
1167 unsigned long last_time1;
1168 unsigned long chipset_power;
1171 unsigned long gfx_power;
1178 struct drm_i915_private;
1179 struct i915_power_well;
1181 struct i915_power_well_ops {
1183 * Synchronize the well's hw state to match the current sw state, for
1184 * example enable/disable it based on the current refcount. Called
1185 * during driver init and resume time, possibly after first calling
1186 * the enable/disable handlers.
1188 void (*sync_hw)(struct drm_i915_private *dev_priv,
1189 struct i915_power_well *power_well);
1191 * Enable the well and resources that depend on it (for example
1192 * interrupts located on the well). Called after the 0->1 refcount
1195 void (*enable)(struct drm_i915_private *dev_priv,
1196 struct i915_power_well *power_well);
1198 * Disable the well and resources that depend on it. Called after
1199 * the 1->0 refcount transition.
1201 void (*disable)(struct drm_i915_private *dev_priv,
1202 struct i915_power_well *power_well);
1203 /* Returns the hw enabled state. */
1204 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1205 struct i915_power_well *power_well);
1208 /* Power well structure for haswell */
1209 struct i915_power_well {
1212 /* power well enable/disable usage count */
1214 /* cached hw enabled state */
1216 unsigned long domains;
1218 const struct i915_power_well_ops *ops;
1221 struct i915_power_domains {
1223 * Power wells needed for initialization at driver init and suspend
1224 * time are on. They are kept on until after the first modeset.
1228 int power_well_count;
1231 int domain_use_count[POWER_DOMAIN_NUM];
1232 struct i915_power_well *power_wells;
1235 #define MAX_L3_SLICES 2
1236 struct intel_l3_parity {
1237 u32 *remap_info[MAX_L3_SLICES];
1238 struct work_struct error_work;
1242 struct i915_gem_mm {
1243 /** Memory allocator for GTT stolen memory */
1244 struct drm_mm stolen;
1245 /** Protects the usage of the GTT stolen memory allocator. This is
1246 * always the inner lock when overlapping with struct_mutex. */
1247 struct mutex stolen_lock;
1249 /** List of all objects in gtt_space. Used to restore gtt
1250 * mappings on resume */
1251 struct list_head bound_list;
1253 * List of objects which are not bound to the GTT (thus
1254 * are idle and not used by the GPU) but still have
1255 * (presumably uncached) pages still attached.
1257 struct list_head unbound_list;
1259 /** Usable portion of the GTT for GEM */
1260 unsigned long stolen_base; /* limited to low memory (32-bit) */
1262 /** PPGTT used for aliasing the PPGTT with the GTT */
1263 struct i915_hw_ppgtt *aliasing_ppgtt;
1265 struct notifier_block oom_notifier;
1266 struct shrinker shrinker;
1267 bool shrinker_no_lock_stealing;
1269 /** LRU list of objects with fence regs on them. */
1270 struct list_head fence_list;
1273 * We leave the user IRQ off as much as possible,
1274 * but this means that requests will finish and never
1275 * be retired once the system goes idle. Set a timer to
1276 * fire periodically while the ring is running. When it
1277 * fires, go retire requests.
1279 struct delayed_work retire_work;
1282 * When we detect an idle GPU, we want to turn on
1283 * powersaving features. So once we see that there
1284 * are no more requests outstanding and no more
1285 * arrive within a small period of time, we fire
1286 * off the idle_work.
1288 struct delayed_work idle_work;
1291 * Are we in a non-interruptible section of code like
1297 * Is the GPU currently considered idle, or busy executing userspace
1298 * requests? Whilst idle, we attempt to power down the hardware and
1299 * display clocks. In order to reduce the effect on performance, there
1300 * is a slight delay before we do so.
1304 /* the indicator for dispatch video commands on two BSD rings */
1305 int bsd_ring_dispatch_index;
1307 /** Bit 6 swizzling required for X tiling */
1308 uint32_t bit_6_swizzle_x;
1309 /** Bit 6 swizzling required for Y tiling */
1310 uint32_t bit_6_swizzle_y;
1312 /* accounting, useful for userland debugging */
1313 spinlock_t object_stat_lock;
1314 size_t object_memory;
1318 struct drm_i915_error_state_buf {
1319 struct drm_i915_private *i915;
1328 struct i915_error_state_file_priv {
1329 struct drm_device *dev;
1330 struct drm_i915_error_state *error;
1333 struct i915_gpu_error {
1334 /* For hangcheck timer */
1335 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1336 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1337 /* Hang gpu twice in this window and your context gets banned */
1338 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1340 struct workqueue_struct *hangcheck_wq;
1341 struct delayed_work hangcheck_work;
1343 /* For reset and error_state handling. */
1345 /* Protected by the above dev->gpu_error.lock. */
1346 struct drm_i915_error_state *first_error;
1348 unsigned long missed_irq_rings;
1351 * State variable controlling the reset flow and count
1353 * This is a counter which gets incremented when reset is triggered,
1354 * and again when reset has been handled. So odd values (lowest bit set)
1355 * means that reset is in progress and even values that
1356 * (reset_counter >> 1):th reset was successfully completed.
1358 * If reset is not completed succesfully, the I915_WEDGE bit is
1359 * set meaning that hardware is terminally sour and there is no
1360 * recovery. All waiters on the reset_queue will be woken when
1363 * This counter is used by the wait_seqno code to notice that reset
1364 * event happened and it needs to restart the entire ioctl (since most
1365 * likely the seqno it waited for won't ever signal anytime soon).
1367 * This is important for lock-free wait paths, where no contended lock
1368 * naturally enforces the correct ordering between the bail-out of the
1369 * waiter and the gpu reset work code.
1371 atomic_t reset_counter;
1373 #define I915_RESET_IN_PROGRESS_FLAG 1
1374 #define I915_WEDGED (1 << 31)
1377 * Waitqueue to signal when the reset has completed. Used by clients
1378 * that wait for dev_priv->mm.wedged to settle.
1380 wait_queue_head_t reset_queue;
1382 /* Userspace knobs for gpu hang simulation;
1383 * combines both a ring mask, and extra flags
1386 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1387 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1389 /* For missed irq/seqno simulation. */
1390 unsigned int test_irq_rings;
1392 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1393 bool reload_in_reset;
1396 enum modeset_restore {
1397 MODESET_ON_LID_OPEN,
1402 #define DP_AUX_A 0x40
1403 #define DP_AUX_B 0x10
1404 #define DP_AUX_C 0x20
1405 #define DP_AUX_D 0x30
1407 #define DDC_PIN_B 0x05
1408 #define DDC_PIN_C 0x04
1409 #define DDC_PIN_D 0x06
1411 struct ddi_vbt_port_info {
1413 * This is an index in the HDMI/DVI DDI buffer translation table.
1414 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1415 * populate this field.
1417 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1418 uint8_t hdmi_level_shift;
1420 uint8_t supports_dvi:1;
1421 uint8_t supports_hdmi:1;
1422 uint8_t supports_dp:1;
1424 uint8_t alternate_aux_channel;
1425 uint8_t alternate_ddc_pin;
1427 uint8_t dp_boost_level;
1428 uint8_t hdmi_boost_level;
1431 enum psr_lines_to_wait {
1432 PSR_0_LINES_TO_WAIT = 0,
1434 PSR_4_LINES_TO_WAIT,
1438 struct intel_vbt_data {
1439 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1440 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1443 unsigned int int_tv_support:1;
1444 unsigned int lvds_dither:1;
1445 unsigned int lvds_vbt:1;
1446 unsigned int int_crt_support:1;
1447 unsigned int lvds_use_ssc:1;
1448 unsigned int display_clock_mode:1;
1449 unsigned int fdi_rx_polarity_inverted:1;
1450 unsigned int has_mipi:1;
1452 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1454 enum drrs_support_type drrs_type;
1459 int edp_preemphasis;
1461 bool edp_initialized;
1464 struct edp_power_seq edp_pps;
1468 bool require_aux_wakeup;
1470 enum psr_lines_to_wait lines_to_wait;
1471 int tp1_wakeup_time;
1472 int tp2_tp3_wakeup_time;
1478 bool active_low_pwm;
1479 u8 min_brightness; /* min_brightness/255 of max */
1486 struct mipi_config *config;
1487 struct mipi_pps_data *pps;
1491 u8 *sequence[MIPI_SEQ_MAX];
1497 union child_device_config *child_dev;
1499 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1502 enum intel_ddb_partitioning {
1504 INTEL_DDB_PART_5_6, /* IVB+ */
1507 struct intel_wm_level {
1515 struct ilk_wm_values {
1516 uint32_t wm_pipe[3];
1518 uint32_t wm_lp_spr[3];
1519 uint32_t wm_linetime[3];
1521 enum intel_ddb_partitioning partitioning;
1524 struct vlv_pipe_wm {
1535 struct vlv_wm_values {
1536 struct vlv_pipe_wm pipe[3];
1537 struct vlv_sr_wm sr;
1547 struct skl_ddb_entry {
1548 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1551 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1553 return entry->end - entry->start;
1556 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1557 const struct skl_ddb_entry *e2)
1559 if (e1->start == e2->start && e1->end == e2->end)
1565 struct skl_ddb_allocation {
1566 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1567 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1568 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1571 struct skl_wm_values {
1572 bool dirty[I915_MAX_PIPES];
1573 struct skl_ddb_allocation ddb;
1574 uint32_t wm_linetime[I915_MAX_PIPES];
1575 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1576 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1579 struct skl_wm_level {
1580 bool plane_en[I915_MAX_PLANES];
1581 uint16_t plane_res_b[I915_MAX_PLANES];
1582 uint8_t plane_res_l[I915_MAX_PLANES];
1586 * This struct helps tracking the state needed for runtime PM, which puts the
1587 * device in PCI D3 state. Notice that when this happens, nothing on the
1588 * graphics device works, even register access, so we don't get interrupts nor
1591 * Every piece of our code that needs to actually touch the hardware needs to
1592 * either call intel_runtime_pm_get or call intel_display_power_get with the
1593 * appropriate power domain.
1595 * Our driver uses the autosuspend delay feature, which means we'll only really
1596 * suspend if we stay with zero refcount for a certain amount of time. The
1597 * default value is currently very conservative (see intel_runtime_pm_enable), but
1598 * it can be changed with the standard runtime PM files from sysfs.
1600 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1601 * goes back to false exactly before we reenable the IRQs. We use this variable
1602 * to check if someone is trying to enable/disable IRQs while they're supposed
1603 * to be disabled. This shouldn't happen and we'll print some error messages in
1606 * For more, read the Documentation/power/runtime_pm.txt.
1608 struct i915_runtime_pm {
1609 atomic_t wakeref_count;
1610 atomic_t atomic_seq;
1615 enum intel_pipe_crc_source {
1616 INTEL_PIPE_CRC_SOURCE_NONE,
1617 INTEL_PIPE_CRC_SOURCE_PLANE1,
1618 INTEL_PIPE_CRC_SOURCE_PLANE2,
1619 INTEL_PIPE_CRC_SOURCE_PF,
1620 INTEL_PIPE_CRC_SOURCE_PIPE,
1621 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1622 INTEL_PIPE_CRC_SOURCE_TV,
1623 INTEL_PIPE_CRC_SOURCE_DP_B,
1624 INTEL_PIPE_CRC_SOURCE_DP_C,
1625 INTEL_PIPE_CRC_SOURCE_DP_D,
1626 INTEL_PIPE_CRC_SOURCE_AUTO,
1627 INTEL_PIPE_CRC_SOURCE_MAX,
1630 struct intel_pipe_crc_entry {
1635 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1636 struct intel_pipe_crc {
1638 bool opened; /* exclusive access to the result file */
1639 struct intel_pipe_crc_entry *entries;
1640 enum intel_pipe_crc_source source;
1642 wait_queue_head_t wq;
1645 struct i915_frontbuffer_tracking {
1649 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1656 struct i915_wa_reg {
1659 /* bitmask representing WA bits */
1663 #define I915_MAX_WA_REGS 16
1665 struct i915_workarounds {
1666 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1670 struct i915_virtual_gpu {
1674 struct i915_execbuffer_params {
1675 struct drm_device *dev;
1676 struct drm_file *file;
1677 uint32_t dispatch_flags;
1678 uint32_t args_batch_start_offset;
1679 uint64_t batch_obj_vm_offset;
1680 struct intel_engine_cs *ring;
1681 struct drm_i915_gem_object *batch_obj;
1682 struct intel_context *ctx;
1683 struct drm_i915_gem_request *request;
1686 /* used in computing the new watermarks state */
1687 struct intel_wm_config {
1688 unsigned int num_pipes_active;
1689 bool sprites_enabled;
1690 bool sprites_scaled;
1693 struct drm_i915_private {
1694 struct drm_device *dev;
1695 struct kmem_cache *objects;
1696 struct kmem_cache *vmas;
1697 struct kmem_cache *requests;
1699 const struct intel_device_info info;
1701 int relative_constants_mode;
1705 struct intel_uncore uncore;
1707 struct i915_virtual_gpu vgpu;
1709 struct intel_guc guc;
1711 struct intel_csr csr;
1713 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1715 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1716 * controller on different i2c buses. */
1717 struct mutex gmbus_mutex;
1720 * Base address of the gmbus and gpio block.
1722 uint32_t gpio_mmio_base;
1724 /* MMIO base address for MIPI regs */
1725 uint32_t mipi_mmio_base;
1727 uint32_t psr_mmio_base;
1729 wait_queue_head_t gmbus_wait_queue;
1731 struct pci_dev *bridge_dev;
1732 struct intel_engine_cs ring[I915_NUM_RINGS];
1733 struct drm_i915_gem_object *semaphore_obj;
1734 uint32_t last_seqno, next_seqno;
1736 struct drm_dma_handle *status_page_dmah;
1737 struct resource mch_res;
1739 /* protects the irq masks */
1740 spinlock_t irq_lock;
1742 /* protects the mmio flip data */
1743 spinlock_t mmio_flip_lock;
1745 bool display_irqs_enabled;
1747 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1748 struct pm_qos_request pm_qos;
1750 /* Sideband mailbox protection */
1751 struct mutex sb_lock;
1753 /** Cached value of IMR to avoid reads in updating the bitfield */
1756 u32 de_irq_mask[I915_MAX_PIPES];
1761 u32 pipestat_irq_mask[I915_MAX_PIPES];
1763 struct i915_hotplug hotplug;
1764 struct i915_fbc fbc;
1765 struct i915_drrs drrs;
1766 struct intel_opregion opregion;
1767 struct intel_vbt_data vbt;
1769 bool preserve_bios_swizzle;
1772 struct intel_overlay *overlay;
1774 /* backlight registers and fields in struct intel_panel */
1775 struct mutex backlight_lock;
1778 bool no_aux_handshake;
1780 /* protects panel power sequencer state */
1781 struct mutex pps_mutex;
1783 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1784 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1786 unsigned int fsb_freq, mem_freq, is_ddr3;
1787 unsigned int skl_boot_cdclk;
1788 unsigned int cdclk_freq, max_cdclk_freq;
1789 unsigned int max_dotclk_freq;
1790 unsigned int hpll_freq;
1791 unsigned int czclk_freq;
1794 * wq - Driver workqueue for GEM.
1796 * NOTE: Work items scheduled here are not allowed to grab any modeset
1797 * locks, for otherwise the flushing done in the pageflip code will
1798 * result in deadlocks.
1800 struct workqueue_struct *wq;
1802 /* Display functions */
1803 struct drm_i915_display_funcs display;
1805 /* PCH chipset type */
1806 enum intel_pch pch_type;
1807 unsigned short pch_id;
1809 unsigned long quirks;
1811 enum modeset_restore modeset_restore;
1812 struct mutex modeset_restore_lock;
1814 struct list_head vm_list; /* Global list of all address spaces */
1815 struct i915_gtt gtt; /* VM representing the global address space */
1817 struct i915_gem_mm mm;
1818 DECLARE_HASHTABLE(mm_structs, 7);
1819 struct mutex mm_lock;
1821 /* Kernel Modesetting */
1823 struct sdvo_device_mapping sdvo_mappings[2];
1825 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1826 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1827 wait_queue_head_t pending_flip_queue;
1829 #ifdef CONFIG_DEBUG_FS
1830 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1833 int num_shared_dpll;
1834 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1835 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1837 struct i915_workarounds workarounds;
1839 /* Reclocking support */
1840 bool render_reclock_avail;
1842 struct i915_frontbuffer_tracking fb_tracking;
1846 bool mchbar_need_disable;
1848 struct intel_l3_parity l3_parity;
1850 /* Cannot be determined by PCIID. You must always read a register. */
1853 /* gen6+ rps state */
1854 struct intel_gen6_power_mgmt rps;
1856 /* ilk-only ips/rps state. Everything in here is protected by the global
1857 * mchdev_lock in intel_pm.c */
1858 struct intel_ilk_power_mgmt ips;
1860 struct i915_power_domains power_domains;
1862 struct i915_psr psr;
1864 struct i915_gpu_error gpu_error;
1866 struct drm_i915_gem_object *vlv_pctx;
1868 #ifdef CONFIG_DRM_FBDEV_EMULATION
1869 /* list of fbdev register on this device */
1870 struct intel_fbdev *fbdev;
1871 struct work_struct fbdev_suspend_work;
1874 struct drm_property *broadcast_rgb_property;
1875 struct drm_property *force_audio_property;
1877 /* hda/i915 audio component */
1878 struct i915_audio_component *audio_component;
1879 bool audio_component_registered;
1881 * av_mutex - mutex for audio/video sync
1884 struct mutex av_mutex;
1886 uint32_t hw_context_size;
1887 struct list_head context_list;
1891 u32 chv_phy_control;
1894 bool suspended_to_idle;
1895 struct i915_suspend_saved_registers regfile;
1896 struct vlv_s0ix_state vlv_s0ix_state;
1900 * Raw watermark latency values:
1901 * in 0.1us units for WM0,
1902 * in 0.5us units for WM1+.
1905 uint16_t pri_latency[5];
1907 uint16_t spr_latency[5];
1909 uint16_t cur_latency[5];
1911 * Raw watermark memory latency values
1912 * for SKL for all 8 levels
1915 uint16_t skl_latency[8];
1917 /* Committed wm config */
1918 struct intel_wm_config config;
1921 * The skl_wm_values structure is a bit too big for stack
1922 * allocation, so we keep the staging struct where we store
1923 * intermediate results here instead.
1925 struct skl_wm_values skl_results;
1927 /* current hardware state */
1929 struct ilk_wm_values hw;
1930 struct skl_wm_values skl_hw;
1931 struct vlv_wm_values vlv;
1937 struct i915_runtime_pm pm;
1939 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1941 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1942 struct drm_i915_gem_execbuffer2 *args,
1943 struct list_head *vmas);
1944 int (*init_rings)(struct drm_device *dev);
1945 void (*cleanup_ring)(struct intel_engine_cs *ring);
1946 void (*stop_ring)(struct intel_engine_cs *ring);
1949 bool edp_low_vswing;
1951 /* perform PHY state sanity checks? */
1952 bool chv_phy_assert[2];
1954 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
1957 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1958 * will be rejected. Instead look for a better place.
1962 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1964 return dev->dev_private;
1967 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1969 return to_i915(dev_get_drvdata(dev));
1972 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
1974 return container_of(guc, struct drm_i915_private, guc);
1977 /* Iterate over initialised rings */
1978 #define for_each_ring(ring__, dev_priv__, i__) \
1979 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1980 for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))))
1982 enum hdmi_force_audio {
1983 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1984 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1985 HDMI_AUDIO_AUTO, /* trust EDID */
1986 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1989 #define I915_GTT_OFFSET_NONE ((u32)-1)
1991 struct drm_i915_gem_object_ops {
1992 /* Interface between the GEM object and its backing storage.
1993 * get_pages() is called once prior to the use of the associated set
1994 * of pages before to binding them into the GTT, and put_pages() is
1995 * called after we no longer need them. As we expect there to be
1996 * associated cost with migrating pages between the backing storage
1997 * and making them available for the GPU (e.g. clflush), we may hold
1998 * onto the pages after they are no longer referenced by the GPU
1999 * in case they may be used again shortly (for example migrating the
2000 * pages to a different memory domain within the GTT). put_pages()
2001 * will therefore most likely be called when the object itself is
2002 * being released or under memory pressure (where we attempt to
2003 * reap pages for the shrinker).
2005 int (*get_pages)(struct drm_i915_gem_object *);
2006 void (*put_pages)(struct drm_i915_gem_object *);
2007 int (*dmabuf_export)(struct drm_i915_gem_object *);
2008 void (*release)(struct drm_i915_gem_object *);
2012 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2013 * considered to be the frontbuffer for the given plane interface-wise. This
2014 * doesn't mean that the hw necessarily already scans it out, but that any
2015 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2017 * We have one bit per pipe and per scanout plane type.
2019 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2020 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2021 #define INTEL_FRONTBUFFER_BITS \
2022 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2023 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2024 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2025 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2026 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2027 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2028 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2029 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2030 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2031 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2032 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2034 struct drm_i915_gem_object {
2035 struct drm_gem_object base;
2037 const struct drm_i915_gem_object_ops *ops;
2039 /** List of VMAs backed by this object */
2040 struct list_head vma_list;
2042 /** Stolen memory for this object, instead of being backed by shmem. */
2043 struct drm_mm_node *stolen;
2044 struct list_head global_list;
2046 struct list_head ring_list[I915_NUM_RINGS];
2047 /** Used in execbuf to temporarily hold a ref */
2048 struct list_head obj_exec_link;
2050 struct list_head batch_pool_link;
2053 * This is set if the object is on the active lists (has pending
2054 * rendering and so a non-zero seqno), and is not set if it i s on
2055 * inactive (ready to be unbound) list.
2057 unsigned int active:I915_NUM_RINGS;
2060 * This is set if the object has been written to since last bound
2063 unsigned int dirty:1;
2066 * Fence register bits (if any) for this object. Will be set
2067 * as needed when mapped into the GTT.
2068 * Protected by dev->struct_mutex.
2070 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2073 * Advice: are the backing pages purgeable?
2075 unsigned int madv:2;
2078 * Current tiling mode for the object.
2080 unsigned int tiling_mode:2;
2082 * Whether the tiling parameters for the currently associated fence
2083 * register have changed. Note that for the purposes of tracking
2084 * tiling changes we also treat the unfenced register, the register
2085 * slot that the object occupies whilst it executes a fenced
2086 * command (such as BLT on gen2/3), as a "fence".
2088 unsigned int fence_dirty:1;
2091 * Is the object at the current location in the gtt mappable and
2092 * fenceable? Used to avoid costly recalculations.
2094 unsigned int map_and_fenceable:1;
2097 * Whether the current gtt mapping needs to be mappable (and isn't just
2098 * mappable by accident). Track pin and fault separate for a more
2099 * accurate mappable working set.
2101 unsigned int fault_mappable:1;
2104 * Is the object to be mapped as read-only to the GPU
2105 * Only honoured if hardware has relevant pte bit
2107 unsigned long gt_ro:1;
2108 unsigned int cache_level:3;
2109 unsigned int cache_dirty:1;
2111 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2113 unsigned int pin_display;
2115 struct sg_table *pages;
2116 int pages_pin_count;
2118 struct scatterlist *sg;
2122 /* prime dma-buf support */
2123 void *dma_buf_vmapping;
2126 /** Breadcrumb of last rendering to the buffer.
2127 * There can only be one writer, but we allow for multiple readers.
2128 * If there is a writer that necessarily implies that all other
2129 * read requests are complete - but we may only be lazily clearing
2130 * the read requests. A read request is naturally the most recent
2131 * request on a ring, so we may have two different write and read
2132 * requests on one ring where the write request is older than the
2133 * read request. This allows for the CPU to read from an active
2134 * buffer by only waiting for the write to complete.
2136 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2137 struct drm_i915_gem_request *last_write_req;
2138 /** Breadcrumb of last fenced GPU access to the buffer. */
2139 struct drm_i915_gem_request *last_fenced_req;
2141 /** Current tiling stride for the object, if it's tiled. */
2144 /** References from framebuffers, locks out tiling changes. */
2145 unsigned long framebuffer_references;
2147 /** Record of address bit 17 of each page at last unbind. */
2148 unsigned long *bit_17;
2151 /** for phy allocated objects */
2152 struct drm_dma_handle *phys_handle;
2154 struct i915_gem_userptr {
2156 unsigned read_only :1;
2157 unsigned workers :4;
2158 #define I915_GEM_USERPTR_MAX_WORKERS 15
2160 struct i915_mm_struct *mm;
2161 struct i915_mmu_object *mmu_object;
2162 struct work_struct *work;
2166 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2168 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2169 struct drm_i915_gem_object *new,
2170 unsigned frontbuffer_bits);
2173 * Request queue structure.
2175 * The request queue allows us to note sequence numbers that have been emitted
2176 * and may be associated with active buffers to be retired.
2178 * By keeping this list, we can avoid having to do questionable sequence
2179 * number comparisons on buffer last_read|write_seqno. It also allows an
2180 * emission time to be associated with the request for tracking how far ahead
2181 * of the GPU the submission is.
2183 * The requests are reference counted, so upon creation they should have an
2184 * initial reference taken using kref_init
2186 struct drm_i915_gem_request {
2189 /** On Which ring this request was generated */
2190 struct drm_i915_private *i915;
2191 struct intel_engine_cs *ring;
2193 /** GEM sequence number associated with the previous request,
2194 * when the HWS breadcrumb is equal to this the GPU is processing
2199 /** GEM sequence number associated with this request,
2200 * when the HWS breadcrumb is equal or greater than this the GPU
2201 * has finished processing this request.
2205 /** Position in the ringbuffer of the start of the request */
2209 * Position in the ringbuffer of the start of the postfix.
2210 * This is required to calculate the maximum available ringbuffer
2211 * space without overwriting the postfix.
2215 /** Position in the ringbuffer of the end of the whole request */
2219 * Context and ring buffer related to this request
2220 * Contexts are refcounted, so when this request is associated with a
2221 * context, we must increment the context's refcount, to guarantee that
2222 * it persists while any request is linked to it. Requests themselves
2223 * are also refcounted, so the request will only be freed when the last
2224 * reference to it is dismissed, and the code in
2225 * i915_gem_request_free() will then decrement the refcount on the
2228 struct intel_context *ctx;
2229 struct intel_ringbuffer *ringbuf;
2231 /** Batch buffer related to this request if any (used for
2232 error state dump only) */
2233 struct drm_i915_gem_object *batch_obj;
2235 /** Time at which this request was emitted, in jiffies. */
2236 unsigned long emitted_jiffies;
2238 /** global list entry for this request */
2239 struct list_head list;
2241 struct drm_i915_file_private *file_priv;
2242 /** file_priv list entry for this request */
2243 struct list_head client_list;
2245 /** process identifier submitting this request */
2249 * The ELSP only accepts two elements at a time, so we queue
2250 * context/tail pairs on a given queue (ring->execlist_queue) until the
2251 * hardware is available. The queue serves a double purpose: we also use
2252 * it to keep track of the up to 2 contexts currently in the hardware
2253 * (usually one in execution and the other queued up by the GPU): We
2254 * only remove elements from the head of the queue when the hardware
2255 * informs us that an element has been completed.
2257 * All accesses to the queue are mediated by a spinlock
2258 * (ring->execlist_lock).
2261 /** Execlist link in the submission queue.*/
2262 struct list_head execlist_link;
2264 /** Execlists no. of times this request has been sent to the ELSP */
2269 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2270 struct intel_context *ctx,
2271 struct drm_i915_gem_request **req_out);
2272 void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2273 void i915_gem_request_free(struct kref *req_ref);
2274 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2275 struct drm_file *file);
2277 static inline uint32_t
2278 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2280 return req ? req->seqno : 0;
2283 static inline struct intel_engine_cs *
2284 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2286 return req ? req->ring : NULL;
2289 static inline struct drm_i915_gem_request *
2290 i915_gem_request_reference(struct drm_i915_gem_request *req)
2293 kref_get(&req->ref);
2298 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2300 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2301 kref_put(&req->ref, i915_gem_request_free);
2305 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2307 struct drm_device *dev;
2312 dev = req->ring->dev;
2313 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2314 mutex_unlock(&dev->struct_mutex);
2317 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2318 struct drm_i915_gem_request *src)
2321 i915_gem_request_reference(src);
2324 i915_gem_request_unreference(*pdst);
2330 * XXX: i915_gem_request_completed should be here but currently needs the
2331 * definition of i915_seqno_passed() which is below. It will be moved in
2332 * a later patch when the call to i915_seqno_passed() is obsoleted...
2336 * A command that requires special handling by the command parser.
2338 struct drm_i915_cmd_descriptor {
2340 * Flags describing how the command parser processes the command.
2342 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2343 * a length mask if not set
2344 * CMD_DESC_SKIP: The command is allowed but does not follow the
2345 * standard length encoding for the opcode range in
2347 * CMD_DESC_REJECT: The command is never allowed
2348 * CMD_DESC_REGISTER: The command should be checked against the
2349 * register whitelist for the appropriate ring
2350 * CMD_DESC_MASTER: The command is allowed if the submitting process
2354 #define CMD_DESC_FIXED (1<<0)
2355 #define CMD_DESC_SKIP (1<<1)
2356 #define CMD_DESC_REJECT (1<<2)
2357 #define CMD_DESC_REGISTER (1<<3)
2358 #define CMD_DESC_BITMASK (1<<4)
2359 #define CMD_DESC_MASTER (1<<5)
2362 * The command's unique identification bits and the bitmask to get them.
2363 * This isn't strictly the opcode field as defined in the spec and may
2364 * also include type, subtype, and/or subop fields.
2372 * The command's length. The command is either fixed length (i.e. does
2373 * not include a length field) or has a length field mask. The flag
2374 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2375 * a length mask. All command entries in a command table must include
2376 * length information.
2384 * Describes where to find a register address in the command to check
2385 * against the ring's register whitelist. Only valid if flags has the
2386 * CMD_DESC_REGISTER bit set.
2388 * A non-zero step value implies that the command may access multiple
2389 * registers in sequence (e.g. LRI), in that case step gives the
2390 * distance in dwords between individual offset fields.
2398 #define MAX_CMD_DESC_BITMASKS 3
2400 * Describes command checks where a particular dword is masked and
2401 * compared against an expected value. If the command does not match
2402 * the expected value, the parser rejects it. Only valid if flags has
2403 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2406 * If the check specifies a non-zero condition_mask then the parser
2407 * only performs the check when the bits specified by condition_mask
2414 u32 condition_offset;
2416 } bits[MAX_CMD_DESC_BITMASKS];
2420 * A table of commands requiring special handling by the command parser.
2422 * Each ring has an array of tables. Each table consists of an array of command
2423 * descriptors, which must be sorted with command opcodes in ascending order.
2425 struct drm_i915_cmd_table {
2426 const struct drm_i915_cmd_descriptor *table;
2430 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2431 #define __I915__(p) ({ \
2432 struct drm_i915_private *__p; \
2433 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2434 __p = (struct drm_i915_private *)p; \
2435 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2436 __p = to_i915((struct drm_device *)p); \
2441 #define INTEL_INFO(p) (&__I915__(p)->info)
2442 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2443 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2445 #define REVID_FOREVER 0xff
2447 * Return true if revision is in range [since,until] inclusive.
2449 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2451 #define IS_REVID(p, since, until) \
2452 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2454 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2455 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2456 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2457 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2458 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2459 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2460 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2461 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2462 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2463 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2464 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2465 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2466 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2467 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2468 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2469 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2470 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2471 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2472 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2473 INTEL_DEVID(dev) == 0x0152 || \
2474 INTEL_DEVID(dev) == 0x015a)
2475 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2476 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2477 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2478 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2479 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2480 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2481 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2482 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2483 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2484 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2485 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2486 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2487 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2488 (INTEL_DEVID(dev) & 0xf) == 0xe))
2489 /* ULX machines are also considered ULT. */
2490 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2491 (INTEL_DEVID(dev) & 0xf) == 0xe)
2492 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2493 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2494 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2495 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2496 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2497 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2498 /* ULX machines are also considered ULT. */
2499 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2500 INTEL_DEVID(dev) == 0x0A1E)
2501 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2502 INTEL_DEVID(dev) == 0x1913 || \
2503 INTEL_DEVID(dev) == 0x1916 || \
2504 INTEL_DEVID(dev) == 0x1921 || \
2505 INTEL_DEVID(dev) == 0x1926)
2506 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2507 INTEL_DEVID(dev) == 0x1915 || \
2508 INTEL_DEVID(dev) == 0x191E)
2509 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2510 INTEL_DEVID(dev) == 0x5913 || \
2511 INTEL_DEVID(dev) == 0x5916 || \
2512 INTEL_DEVID(dev) == 0x5921 || \
2513 INTEL_DEVID(dev) == 0x5926)
2514 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2515 INTEL_DEVID(dev) == 0x5915 || \
2516 INTEL_DEVID(dev) == 0x591E)
2517 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2518 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2519 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2520 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2522 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2524 #define SKL_REVID_A0 0x0
2525 #define SKL_REVID_B0 0x1
2526 #define SKL_REVID_C0 0x2
2527 #define SKL_REVID_D0 0x3
2528 #define SKL_REVID_E0 0x4
2529 #define SKL_REVID_F0 0x5
2531 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2533 #define BXT_REVID_A0 0x0
2534 #define BXT_REVID_A1 0x1
2535 #define BXT_REVID_B0 0x3
2536 #define BXT_REVID_C0 0x9
2538 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2541 * The genX designation typically refers to the render engine, so render
2542 * capability related checks should use IS_GEN, while display and other checks
2543 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2546 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2547 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2548 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2549 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2550 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2551 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2552 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2553 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2555 #define RENDER_RING (1<<RCS)
2556 #define BSD_RING (1<<VCS)
2557 #define BLT_RING (1<<BCS)
2558 #define VEBOX_RING (1<<VECS)
2559 #define BSD2_RING (1<<VCS2)
2560 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2561 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2562 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2563 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2564 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2565 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2566 __I915__(dev)->ellc_size)
2567 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2569 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2570 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2571 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2572 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2573 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2575 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2576 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2578 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2579 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2581 /* WaRsDisableCoarsePowerGating:skl,bxt */
2582 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2583 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
2584 IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
2586 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2587 * even when in MSI mode. This results in spurious interrupt warnings if the
2588 * legacy irq no. is shared with another device. The kernel then disables that
2589 * interrupt source and so prevents the other device from working properly.
2591 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2592 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2594 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2595 * rows, which changed the alignment requirements and fence programming.
2597 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2599 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2600 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2602 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2603 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2604 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2606 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2608 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2609 INTEL_INFO(dev)->gen >= 9)
2611 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2612 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2613 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2614 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2615 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2616 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2617 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2618 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2620 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2621 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2623 #define HAS_CSR(dev) (IS_GEN9(dev))
2625 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2626 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2628 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2629 INTEL_INFO(dev)->gen >= 8)
2631 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2632 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2635 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2636 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2637 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2638 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2639 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2640 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2641 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2642 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2643 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2644 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2646 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2647 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2648 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2649 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2650 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2651 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2652 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2653 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2654 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2656 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2657 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2659 /* DPF == dynamic parity feature */
2660 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2661 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2663 #define GT_FREQUENCY_MULTIPLIER 50
2664 #define GEN9_FREQ_SCALER 3
2666 #include "i915_trace.h"
2668 extern const struct drm_ioctl_desc i915_ioctls[];
2669 extern int i915_max_ioctl;
2671 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2672 extern int i915_resume_switcheroo(struct drm_device *dev);
2675 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2676 extern int i915_driver_unload(struct drm_device *);
2677 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2678 extern void i915_driver_lastclose(struct drm_device * dev);
2679 extern void i915_driver_preclose(struct drm_device *dev,
2680 struct drm_file *file);
2681 extern void i915_driver_postclose(struct drm_device *dev,
2682 struct drm_file *file);
2683 #ifdef CONFIG_COMPAT
2684 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2687 extern int intel_gpu_reset(struct drm_device *dev);
2688 extern bool intel_has_gpu_reset(struct drm_device *dev);
2689 extern int i915_reset(struct drm_device *dev);
2690 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2691 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2692 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2693 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2694 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2696 /* intel_hotplug.c */
2697 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2698 void intel_hpd_init(struct drm_i915_private *dev_priv);
2699 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2700 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2701 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2704 void i915_queue_hangcheck(struct drm_device *dev);
2706 void i915_handle_error(struct drm_device *dev, bool wedged,
2707 const char *fmt, ...);
2709 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2710 int intel_irq_install(struct drm_i915_private *dev_priv);
2711 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2713 extern void intel_uncore_sanitize(struct drm_device *dev);
2714 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2715 bool restore_forcewake);
2716 extern void intel_uncore_init(struct drm_device *dev);
2717 extern void intel_uncore_check_errors(struct drm_device *dev);
2718 extern void intel_uncore_fini(struct drm_device *dev);
2719 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2720 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2721 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2722 enum forcewake_domains domains);
2723 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2724 enum forcewake_domains domains);
2725 /* Like above but the caller must manage the uncore.lock itself.
2726 * Must be used with I915_READ_FW and friends.
2728 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2729 enum forcewake_domains domains);
2730 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2731 enum forcewake_domains domains);
2732 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2733 static inline bool intel_vgpu_active(struct drm_device *dev)
2735 return to_i915(dev)->vgpu.active;
2739 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2743 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2746 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2747 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2748 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2751 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2752 uint32_t interrupt_mask,
2753 uint32_t enabled_irq_mask);
2755 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2757 ilk_update_display_irq(dev_priv, bits, bits);
2760 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2762 ilk_update_display_irq(dev_priv, bits, 0);
2764 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2766 uint32_t interrupt_mask,
2767 uint32_t enabled_irq_mask);
2768 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2769 enum pipe pipe, uint32_t bits)
2771 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2773 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2774 enum pipe pipe, uint32_t bits)
2776 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2778 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2779 uint32_t interrupt_mask,
2780 uint32_t enabled_irq_mask);
2782 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2784 ibx_display_interrupt_update(dev_priv, bits, bits);
2787 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2789 ibx_display_interrupt_update(dev_priv, bits, 0);
2794 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2795 struct drm_file *file_priv);
2796 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2797 struct drm_file *file_priv);
2798 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2799 struct drm_file *file_priv);
2800 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2801 struct drm_file *file_priv);
2802 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2803 struct drm_file *file_priv);
2804 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2805 struct drm_file *file_priv);
2806 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2807 struct drm_file *file_priv);
2808 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2809 struct drm_i915_gem_request *req);
2810 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2811 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2812 struct drm_i915_gem_execbuffer2 *args,
2813 struct list_head *vmas);
2814 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2815 struct drm_file *file_priv);
2816 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2817 struct drm_file *file_priv);
2818 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2819 struct drm_file *file_priv);
2820 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2821 struct drm_file *file);
2822 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2823 struct drm_file *file);
2824 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2825 struct drm_file *file_priv);
2826 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2827 struct drm_file *file_priv);
2828 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2829 struct drm_file *file_priv);
2830 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2831 struct drm_file *file_priv);
2832 int i915_gem_init_userptr(struct drm_device *dev);
2833 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2834 struct drm_file *file);
2835 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2836 struct drm_file *file_priv);
2837 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2838 struct drm_file *file_priv);
2839 void i915_gem_load(struct drm_device *dev);
2840 void *i915_gem_object_alloc(struct drm_device *dev);
2841 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2842 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2843 const struct drm_i915_gem_object_ops *ops);
2844 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2846 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2847 struct drm_device *dev, const void *data, size_t size);
2848 void i915_gem_free_object(struct drm_gem_object *obj);
2849 void i915_gem_vma_destroy(struct i915_vma *vma);
2851 /* Flags used by pin/bind&friends. */
2852 #define PIN_MAPPABLE (1<<0)
2853 #define PIN_NONBLOCK (1<<1)
2854 #define PIN_GLOBAL (1<<2)
2855 #define PIN_OFFSET_BIAS (1<<3)
2856 #define PIN_USER (1<<4)
2857 #define PIN_UPDATE (1<<5)
2858 #define PIN_ZONE_4G (1<<6)
2859 #define PIN_HIGH (1<<7)
2860 #define PIN_OFFSET_FIXED (1<<8)
2861 #define PIN_OFFSET_MASK (~4095)
2863 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2864 struct i915_address_space *vm,
2868 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2869 const struct i915_ggtt_view *view,
2873 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2875 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2876 int __must_check i915_vma_unbind(struct i915_vma *vma);
2878 * BEWARE: Do not use the function below unless you can _absolutely_
2879 * _guarantee_ VMA in question is _not in use_ anywhere.
2881 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2882 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2883 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2884 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2886 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2887 int *needs_clflush);
2889 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2891 static inline int __sg_page_count(struct scatterlist *sg)
2893 return sg->length >> PAGE_SHIFT;
2897 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
2899 static inline struct page *
2900 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2902 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2905 if (n < obj->get_page.last) {
2906 obj->get_page.sg = obj->pages->sgl;
2907 obj->get_page.last = 0;
2910 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2911 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2912 if (unlikely(sg_is_chain(obj->get_page.sg)))
2913 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2916 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2919 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2921 BUG_ON(obj->pages == NULL);
2922 obj->pages_pin_count++;
2924 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2926 BUG_ON(obj->pages_pin_count == 0);
2927 obj->pages_pin_count--;
2930 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2931 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2932 struct intel_engine_cs *to,
2933 struct drm_i915_gem_request **to_req);
2934 void i915_vma_move_to_active(struct i915_vma *vma,
2935 struct drm_i915_gem_request *req);
2936 int i915_gem_dumb_create(struct drm_file *file_priv,
2937 struct drm_device *dev,
2938 struct drm_mode_create_dumb *args);
2939 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2940 uint32_t handle, uint64_t *offset);
2942 * Returns true if seq1 is later than seq2.
2945 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2947 return (int32_t)(seq1 - seq2) >= 0;
2950 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
2951 bool lazy_coherency)
2953 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2954 return i915_seqno_passed(seqno, req->previous_seqno);
2957 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2958 bool lazy_coherency)
2960 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2961 return i915_seqno_passed(seqno, req->seqno);
2964 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2965 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2967 struct drm_i915_gem_request *
2968 i915_gem_find_active_request(struct intel_engine_cs *ring);
2970 bool i915_gem_retire_requests(struct drm_device *dev);
2971 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2972 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2973 bool interruptible);
2975 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2977 return unlikely(atomic_read(&error->reset_counter)
2978 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2981 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2983 return atomic_read(&error->reset_counter) & I915_WEDGED;
2986 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2988 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2991 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2993 return dev_priv->gpu_error.stop_rings == 0 ||
2994 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2997 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2999 return dev_priv->gpu_error.stop_rings == 0 ||
3000 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3003 void i915_gem_reset(struct drm_device *dev);
3004 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3005 int __must_check i915_gem_init(struct drm_device *dev);
3006 int i915_gem_init_rings(struct drm_device *dev);
3007 int __must_check i915_gem_init_hw(struct drm_device *dev);
3008 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3009 void i915_gem_init_swizzling(struct drm_device *dev);
3010 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
3011 int __must_check i915_gpu_idle(struct drm_device *dev);
3012 int __must_check i915_gem_suspend(struct drm_device *dev);
3013 void __i915_add_request(struct drm_i915_gem_request *req,
3014 struct drm_i915_gem_object *batch_obj,
3016 #define i915_add_request(req) \
3017 __i915_add_request(req, NULL, true)
3018 #define i915_add_request_no_flush(req) \
3019 __i915_add_request(req, NULL, false)
3020 int __i915_wait_request(struct drm_i915_gem_request *req,
3021 unsigned reset_counter,
3024 struct intel_rps_client *rps);
3025 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3026 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3028 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3031 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3034 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3036 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3038 const struct i915_ggtt_view *view);
3039 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3040 const struct i915_ggtt_view *view);
3041 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3043 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3044 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3047 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3049 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3050 int tiling_mode, bool fenced);
3052 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3053 enum i915_cache_level cache_level);
3055 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3056 struct dma_buf *dma_buf);
3058 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3059 struct drm_gem_object *gem_obj, int flags);
3061 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3062 const struct i915_ggtt_view *view);
3063 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3064 struct i915_address_space *vm);
3066 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3068 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3071 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3072 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3073 const struct i915_ggtt_view *view);
3074 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3075 struct i915_address_space *vm);
3077 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3078 struct i915_address_space *vm);
3080 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3081 struct i915_address_space *vm);
3083 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3084 const struct i915_ggtt_view *view);
3087 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3088 struct i915_address_space *vm);
3090 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3091 const struct i915_ggtt_view *view);
3093 static inline struct i915_vma *
3094 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3096 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3098 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3100 /* Some GGTT VM helpers */
3101 #define i915_obj_to_ggtt(obj) \
3102 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3103 static inline bool i915_is_ggtt(struct i915_address_space *vm)
3105 struct i915_address_space *ggtt =
3106 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
3110 static inline struct i915_hw_ppgtt *
3111 i915_vm_to_ppgtt(struct i915_address_space *vm)
3113 WARN_ON(i915_is_ggtt(vm));
3115 return container_of(vm, struct i915_hw_ppgtt, base);
3119 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3121 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3124 static inline unsigned long
3125 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3127 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3130 static inline int __must_check
3131 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3135 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3136 alignment, flags | PIN_GLOBAL);
3140 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3142 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3145 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3146 const struct i915_ggtt_view *view);
3148 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3150 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3153 /* i915_gem_fence.c */
3154 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3155 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3157 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3158 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3160 void i915_gem_restore_fences(struct drm_device *dev);
3162 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3163 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3164 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3166 /* i915_gem_context.c */
3167 int __must_check i915_gem_context_init(struct drm_device *dev);
3168 void i915_gem_context_fini(struct drm_device *dev);
3169 void i915_gem_context_reset(struct drm_device *dev);
3170 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3171 int i915_gem_context_enable(struct drm_i915_gem_request *req);
3172 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3173 int i915_switch_context(struct drm_i915_gem_request *req);
3174 struct intel_context *
3175 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3176 void i915_gem_context_free(struct kref *ctx_ref);
3177 struct drm_i915_gem_object *
3178 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3179 static inline void i915_gem_context_reference(struct intel_context *ctx)
3181 kref_get(&ctx->ref);
3184 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3186 kref_put(&ctx->ref, i915_gem_context_free);
3189 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3191 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3194 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3195 struct drm_file *file);
3196 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3197 struct drm_file *file);
3198 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3199 struct drm_file *file_priv);
3200 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3201 struct drm_file *file_priv);
3203 /* i915_gem_evict.c */
3204 int __must_check i915_gem_evict_something(struct drm_device *dev,
3205 struct i915_address_space *vm,
3208 unsigned cache_level,
3209 unsigned long start,
3212 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3213 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3215 /* belongs in i915_gem_gtt.h */
3216 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3218 if (INTEL_INFO(dev)->gen < 6)
3219 intel_gtt_chipset_flush();
3222 /* i915_gem_stolen.c */
3223 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3224 struct drm_mm_node *node, u64 size,
3225 unsigned alignment);
3226 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3227 struct drm_mm_node *node, u64 size,
3228 unsigned alignment, u64 start,
3230 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3231 struct drm_mm_node *node);
3232 int i915_gem_init_stolen(struct drm_device *dev);
3233 void i915_gem_cleanup_stolen(struct drm_device *dev);
3234 struct drm_i915_gem_object *
3235 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3236 struct drm_i915_gem_object *
3237 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3242 /* i915_gem_shrinker.c */
3243 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3244 unsigned long target,
3246 #define I915_SHRINK_PURGEABLE 0x1
3247 #define I915_SHRINK_UNBOUND 0x2
3248 #define I915_SHRINK_BOUND 0x4
3249 #define I915_SHRINK_ACTIVE 0x8
3250 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3251 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3254 /* i915_gem_tiling.c */
3255 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3257 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3259 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3260 obj->tiling_mode != I915_TILING_NONE;
3263 /* i915_gem_debug.c */
3265 int i915_verify_lists(struct drm_device *dev);
3267 #define i915_verify_lists(dev) 0
3270 /* i915_debugfs.c */
3271 int i915_debugfs_init(struct drm_minor *minor);
3272 void i915_debugfs_cleanup(struct drm_minor *minor);
3273 #ifdef CONFIG_DEBUG_FS
3274 int i915_debugfs_connector_add(struct drm_connector *connector);
3275 void intel_display_crc_init(struct drm_device *dev);
3277 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3279 static inline void intel_display_crc_init(struct drm_device *dev) {}
3282 /* i915_gpu_error.c */
3284 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3285 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3286 const struct i915_error_state_file_priv *error);
3287 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3288 struct drm_i915_private *i915,
3289 size_t count, loff_t pos);
3290 static inline void i915_error_state_buf_release(
3291 struct drm_i915_error_state_buf *eb)
3295 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3296 const char *error_msg);
3297 void i915_error_state_get(struct drm_device *dev,
3298 struct i915_error_state_file_priv *error_priv);
3299 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3300 void i915_destroy_error_state(struct drm_device *dev);
3302 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3303 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3305 /* i915_cmd_parser.c */
3306 int i915_cmd_parser_get_version(void);
3307 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3308 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3309 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3310 int i915_parse_cmds(struct intel_engine_cs *ring,
3311 struct drm_i915_gem_object *batch_obj,
3312 struct drm_i915_gem_object *shadow_batch_obj,
3313 u32 batch_start_offset,
3317 /* i915_suspend.c */
3318 extern int i915_save_state(struct drm_device *dev);
3319 extern int i915_restore_state(struct drm_device *dev);
3322 void i915_setup_sysfs(struct drm_device *dev_priv);
3323 void i915_teardown_sysfs(struct drm_device *dev_priv);
3326 extern int intel_setup_gmbus(struct drm_device *dev);
3327 extern void intel_teardown_gmbus(struct drm_device *dev);
3328 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3331 extern struct i2c_adapter *
3332 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3333 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3334 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3335 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3337 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3339 extern void intel_i2c_reset(struct drm_device *dev);
3342 int intel_bios_init(struct drm_i915_private *dev_priv);
3343 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3345 /* intel_opregion.c */
3347 extern int intel_opregion_setup(struct drm_device *dev);
3348 extern void intel_opregion_init(struct drm_device *dev);
3349 extern void intel_opregion_fini(struct drm_device *dev);
3350 extern void intel_opregion_asle_intr(struct drm_device *dev);
3351 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3353 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3356 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3357 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3358 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3359 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3361 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3366 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3374 extern void intel_register_dsm_handler(void);
3375 extern void intel_unregister_dsm_handler(void);
3377 static inline void intel_register_dsm_handler(void) { return; }
3378 static inline void intel_unregister_dsm_handler(void) { return; }
3379 #endif /* CONFIG_ACPI */
3382 extern void intel_modeset_init_hw(struct drm_device *dev);
3383 extern void intel_modeset_init(struct drm_device *dev);
3384 extern void intel_modeset_gem_init(struct drm_device *dev);
3385 extern void intel_modeset_cleanup(struct drm_device *dev);
3386 extern void intel_connector_unregister(struct intel_connector *);
3387 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3388 extern void intel_display_resume(struct drm_device *dev);
3389 extern void i915_redisable_vga(struct drm_device *dev);
3390 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3391 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3392 extern void intel_init_pch_refclk(struct drm_device *dev);
3393 extern void intel_set_rps(struct drm_device *dev, u8 val);
3394 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3396 extern void intel_detect_pch(struct drm_device *dev);
3397 extern int intel_enable_rc6(const struct drm_device *dev);
3399 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3400 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3401 struct drm_file *file);
3402 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3403 struct drm_file *file);
3406 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3407 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3408 struct intel_overlay_error_state *error);
3410 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3411 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3412 struct drm_device *dev,
3413 struct intel_display_error_state *error);
3415 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3416 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3418 /* intel_sideband.c */
3419 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3420 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3421 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3422 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3423 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3424 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3425 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3426 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3427 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3428 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3429 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3430 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3431 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3432 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3433 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3434 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3435 enum intel_sbi_destination destination);
3436 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3437 enum intel_sbi_destination destination);
3438 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3439 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3441 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3442 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3444 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3445 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3447 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3448 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3449 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3450 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3452 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3453 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3454 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3455 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3457 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3458 * will be implemented using 2 32-bit writes in an arbitrary order with
3459 * an arbitrary delay between them. This can cause the hardware to
3460 * act upon the intermediate value, possibly leading to corruption and
3461 * machine death. You have been warned.
3463 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3464 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3466 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3467 u32 upper, lower, old_upper, loop = 0; \
3468 upper = I915_READ(upper_reg); \
3470 old_upper = upper; \
3471 lower = I915_READ(lower_reg); \
3472 upper = I915_READ(upper_reg); \
3473 } while (upper != old_upper && loop++ < 2); \
3474 (u64)upper << 32 | lower; })
3476 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3477 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3479 #define __raw_read(x, s) \
3480 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3483 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3486 #define __raw_write(x, s) \
3487 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3488 i915_reg_t reg, uint##x##_t val) \
3490 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3505 /* These are untraced mmio-accessors that are only valid to be used inside
3506 * criticial sections inside IRQ handlers where forcewake is explicitly
3508 * Think twice, and think again, before using these.
3509 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3510 * intel_uncore_forcewake_irqunlock().
3512 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3513 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3514 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3516 /* "Broadcast RGB" property */
3517 #define INTEL_BROADCAST_RGB_AUTO 0
3518 #define INTEL_BROADCAST_RGB_FULL 1
3519 #define INTEL_BROADCAST_RGB_LIMITED 2
3521 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3523 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3524 return VLV_VGACNTRL;
3525 else if (INTEL_INFO(dev)->gen >= 5)
3526 return CPU_VGACNTRL;
3531 static inline void __user *to_user_ptr(u64 address)
3533 return (void __user *)(uintptr_t)address;
3536 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3538 unsigned long j = msecs_to_jiffies(m);
3540 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3543 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3545 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3548 static inline unsigned long
3549 timespec_to_jiffies_timeout(const struct timespec *value)
3551 unsigned long j = timespec_to_jiffies(value);
3553 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3557 * If you need to wait X milliseconds between events A and B, but event B
3558 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3559 * when event A happened, then just before event B you call this function and
3560 * pass the timestamp as the first argument, and X as the second argument.
3563 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3565 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3568 * Don't re-read the value of "jiffies" every time since it may change
3569 * behind our back and break the math.
3571 tmp_jiffies = jiffies;
3572 target_jiffies = timestamp_jiffies +
3573 msecs_to_jiffies_timeout(to_wait_ms);
3575 if (time_after(target_jiffies, tmp_jiffies)) {
3576 remaining_jiffies = target_jiffies - tmp_jiffies;
3577 while (remaining_jiffies)
3579 schedule_timeout_uninterruptible(remaining_jiffies);
3583 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3584 struct drm_i915_gem_request *req)
3586 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3587 i915_gem_request_assign(&ring->trace_irq_req, req);