1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "i915_params.h"
39 #include "intel_bios.h"
40 #include "intel_ringbuffer.h"
41 #include "intel_lrc.h"
42 #include "i915_gem_gtt.h"
43 #include "i915_gem_render_state.h"
44 #include <linux/io-mapping.h>
45 #include <linux/i2c.h>
46 #include <linux/i2c-algo-bit.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <linux/backlight.h>
51 #include <linux/hashtable.h>
52 #include <linux/intel-iommu.h>
53 #include <linux/kref.h>
54 #include <linux/pm_qos.h>
55 #include "intel_guc.h"
56 #include "intel_dpll_mgr.h"
58 /* General customization:
61 #define DRIVER_NAME "i915"
62 #define DRIVER_DESC "Intel Graphics"
63 #define DRIVER_DATE "20160314"
66 /* Many gcc seem to no see through this and fall over :( */
68 #define WARN_ON(x) ({ \
69 bool __i915_warn_cond = (x); \
70 if (__builtin_constant_p(__i915_warn_cond)) \
71 BUILD_BUG_ON(__i915_warn_cond); \
72 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
74 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
78 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
80 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
81 (long) (x), __func__);
83 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
84 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
85 * which may not necessarily be a user visible problem. This will either
86 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
87 * enable distros and users to tailor their preferred amount of i915 abrt
90 #define I915_STATE_WARN(condition, format...) ({ \
91 int __ret_warn_on = !!(condition); \
92 if (unlikely(__ret_warn_on)) \
93 if (!WARN(i915.verbose_state_checks, format)) \
95 unlikely(__ret_warn_on); \
98 #define I915_STATE_WARN_ON(x) \
99 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
101 static inline const char *yesno(bool v)
103 return v ? "yes" : "no";
106 static inline const char *onoff(bool v)
108 return v ? "on" : "off";
117 I915_MAX_PIPES = _PIPE_EDP
119 #define pipe_name(p) ((p) + 'A')
129 static inline const char *transcoder_name(enum transcoder transcoder)
131 switch (transcoder) {
146 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
147 * number of planes per CRTC. Not all platforms really have this many planes,
148 * which means some arrays of size I915_MAX_PLANES may have unused entries
149 * between the topmost sprite plane and the cursor plane.
158 #define plane_name(p) ((p) + 'A')
160 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
170 #define port_name(p) ((p) + 'A')
172 #define I915_NUM_PHYS_VLV 2
184 enum intel_display_power_domain {
188 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
189 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
190 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
191 POWER_DOMAIN_TRANSCODER_A,
192 POWER_DOMAIN_TRANSCODER_B,
193 POWER_DOMAIN_TRANSCODER_C,
194 POWER_DOMAIN_TRANSCODER_EDP,
195 POWER_DOMAIN_PORT_DDI_A_LANES,
196 POWER_DOMAIN_PORT_DDI_B_LANES,
197 POWER_DOMAIN_PORT_DDI_C_LANES,
198 POWER_DOMAIN_PORT_DDI_D_LANES,
199 POWER_DOMAIN_PORT_DDI_E_LANES,
200 POWER_DOMAIN_PORT_DSI,
201 POWER_DOMAIN_PORT_CRT,
202 POWER_DOMAIN_PORT_OTHER,
211 POWER_DOMAIN_MODESET,
217 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
218 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
219 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
220 #define POWER_DOMAIN_TRANSCODER(tran) \
221 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
222 (tran) + POWER_DOMAIN_TRANSCODER_A)
226 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
238 #define for_each_hpd_pin(__pin) \
239 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
241 struct i915_hotplug {
242 struct work_struct hotplug_work;
245 unsigned long last_jiffies;
250 HPD_MARK_DISABLED = 2
252 } stats[HPD_NUM_PINS];
254 struct delayed_work reenable_work;
256 struct intel_digital_port *irq_port[I915_MAX_PORTS];
259 struct work_struct dig_port_work;
262 * if we get a HPD irq from DP and a HPD irq from non-DP
263 * the non-DP HPD could block the workqueue on a mode config
264 * mutex getting, that userspace may have taken. However
265 * userspace is waiting on the DP workqueue to run which is
266 * blocked behind the non-DP one.
268 struct workqueue_struct *dp_wq;
271 #define I915_GEM_GPU_DOMAINS \
272 (I915_GEM_DOMAIN_RENDER | \
273 I915_GEM_DOMAIN_SAMPLER | \
274 I915_GEM_DOMAIN_COMMAND | \
275 I915_GEM_DOMAIN_INSTRUCTION | \
276 I915_GEM_DOMAIN_VERTEX)
278 #define for_each_pipe(__dev_priv, __p) \
279 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
280 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
281 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
282 for_each_if ((__mask) & (1 << (__p)))
283 #define for_each_plane(__dev_priv, __pipe, __p) \
285 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
287 #define for_each_sprite(__dev_priv, __p, __s) \
289 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
292 #define for_each_port_masked(__port, __ports_mask) \
293 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
294 for_each_if ((__ports_mask) & (1 << (__port)))
296 #define for_each_crtc(dev, crtc) \
297 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
299 #define for_each_intel_plane(dev, intel_plane) \
300 list_for_each_entry(intel_plane, \
301 &dev->mode_config.plane_list, \
304 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
305 list_for_each_entry(intel_plane, \
306 &(dev)->mode_config.plane_list, \
308 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
310 #define for_each_intel_crtc(dev, intel_crtc) \
311 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
313 #define for_each_intel_encoder(dev, intel_encoder) \
314 list_for_each_entry(intel_encoder, \
315 &(dev)->mode_config.encoder_list, \
318 #define for_each_intel_connector(dev, intel_connector) \
319 list_for_each_entry(intel_connector, \
320 &dev->mode_config.connector_list, \
323 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
324 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
325 for_each_if ((intel_encoder)->base.crtc == (__crtc))
327 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
328 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
329 for_each_if ((intel_connector)->base.encoder == (__encoder))
331 #define for_each_power_domain(domain, mask) \
332 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
333 for_each_if ((1 << (domain)) & (mask))
335 struct drm_i915_private;
336 struct i915_mm_struct;
337 struct i915_mmu_object;
339 struct drm_i915_file_private {
340 struct drm_i915_private *dev_priv;
341 struct drm_file *file;
345 struct list_head request_list;
346 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
347 * chosen to prevent the CPU getting more than a frame ahead of the GPU
348 * (when using lax throttling for the frontbuffer). We also use it to
349 * offer free GPU waitboosts for severely congested workloads.
351 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
353 struct idr context_idr;
355 struct intel_rps_client {
356 struct list_head link;
360 unsigned int bsd_ring;
363 /* Used by dp and fdi links */
364 struct intel_link_m_n {
372 void intel_link_compute_m_n(int bpp, int nlanes,
373 int pixel_clock, int link_clock,
374 struct intel_link_m_n *m_n);
376 /* Interface history:
379 * 1.2: Add Power Management
380 * 1.3: Add vblank support
381 * 1.4: Fix cmdbuffer path, add heap destroy
382 * 1.5: Add vblank pipe configuration
383 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
384 * - Support vertical blank on secondary display pipe
386 #define DRIVER_MAJOR 1
387 #define DRIVER_MINOR 6
388 #define DRIVER_PATCHLEVEL 0
390 #define WATCH_LISTS 0
392 struct opregion_header;
393 struct opregion_acpi;
394 struct opregion_swsci;
395 struct opregion_asle;
397 struct intel_opregion {
398 struct opregion_header *header;
399 struct opregion_acpi *acpi;
400 struct opregion_swsci *swsci;
401 u32 swsci_gbda_sub_functions;
402 u32 swsci_sbcb_sub_functions;
403 struct opregion_asle *asle;
408 struct work_struct asle_work;
410 #define OPREGION_SIZE (8*1024)
412 struct intel_overlay;
413 struct intel_overlay_error_state;
415 #define I915_FENCE_REG_NONE -1
416 #define I915_MAX_NUM_FENCES 32
417 /* 32 fences + sign bit for FENCE_REG_NONE */
418 #define I915_MAX_NUM_FENCE_BITS 6
420 struct drm_i915_fence_reg {
421 struct list_head lru_list;
422 struct drm_i915_gem_object *obj;
426 struct sdvo_device_mapping {
435 struct intel_display_error_state;
437 struct drm_i915_error_state {
446 /* Generic register state */
454 u32 error; /* gen6+ */
455 u32 err_int; /* gen7 */
456 u32 fault_data0; /* gen8, gen9 */
457 u32 fault_data1; /* gen8, gen9 */
463 u32 extra_instdone[I915_NUM_INSTDONE_REG];
464 u64 fence[I915_MAX_NUM_FENCES];
465 struct intel_overlay_error_state *overlay;
466 struct intel_display_error_state *display;
467 struct drm_i915_error_object *semaphore_obj;
469 struct drm_i915_error_ring {
471 /* Software tracked state */
474 enum intel_ring_hangcheck_action hangcheck_action;
477 /* our own tracking of ring head and tail */
481 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
500 u32 rc_psmi; /* sleep state */
501 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
503 struct drm_i915_error_object {
507 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
509 struct drm_i915_error_object *wa_ctx;
511 struct drm_i915_error_request {
526 char comm[TASK_COMM_LEN];
527 } ring[I915_NUM_ENGINES];
529 struct drm_i915_error_buffer {
532 u32 rseqno[I915_NUM_ENGINES], wseqno;
536 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
544 } **active_bo, **pinned_bo;
546 u32 *active_bo_count, *pinned_bo_count;
550 struct intel_connector;
551 struct intel_encoder;
552 struct intel_crtc_state;
553 struct intel_initial_plane_config;
558 struct drm_i915_display_funcs {
559 int (*get_display_clock_speed)(struct drm_device *dev);
560 int (*get_fifo_size)(struct drm_device *dev, int plane);
562 * find_dpll() - Find the best values for the PLL
563 * @limit: limits for the PLL
564 * @crtc: current CRTC
565 * @target: target frequency in kHz
566 * @refclk: reference clock frequency in kHz
567 * @match_clock: if provided, @best_clock P divider must
568 * match the P divider from @match_clock
569 * used for LVDS downclocking
570 * @best_clock: best PLL values found
572 * Returns true on success, false on failure.
574 bool (*find_dpll)(const struct intel_limit *limit,
575 struct intel_crtc_state *crtc_state,
576 int target, int refclk,
577 struct dpll *match_clock,
578 struct dpll *best_clock);
579 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
580 int (*compute_intermediate_wm)(struct drm_device *dev,
581 struct intel_crtc *intel_crtc,
582 struct intel_crtc_state *newstate);
583 void (*initial_watermarks)(struct intel_crtc_state *cstate);
584 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
585 void (*update_wm)(struct drm_crtc *crtc);
586 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
587 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
588 /* Returns the active state of the crtc, and if the crtc is active,
589 * fills out the pipe-config with the hw state. */
590 bool (*get_pipe_config)(struct intel_crtc *,
591 struct intel_crtc_state *);
592 void (*get_initial_plane_config)(struct intel_crtc *,
593 struct intel_initial_plane_config *);
594 int (*crtc_compute_clock)(struct intel_crtc *crtc,
595 struct intel_crtc_state *crtc_state);
596 void (*crtc_enable)(struct drm_crtc *crtc);
597 void (*crtc_disable)(struct drm_crtc *crtc);
598 void (*audio_codec_enable)(struct drm_connector *connector,
599 struct intel_encoder *encoder,
600 const struct drm_display_mode *adjusted_mode);
601 void (*audio_codec_disable)(struct intel_encoder *encoder);
602 void (*fdi_link_train)(struct drm_crtc *crtc);
603 void (*init_clock_gating)(struct drm_device *dev);
604 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
605 struct drm_framebuffer *fb,
606 struct drm_i915_gem_object *obj,
607 struct drm_i915_gem_request *req,
609 void (*hpd_irq_setup)(struct drm_device *dev);
610 /* clock updates for mode set */
612 /* render clock increase/decrease */
613 /* display clock increase/decrease */
614 /* pll clock increase/decrease */
617 enum forcewake_domain_id {
618 FW_DOMAIN_ID_RENDER = 0,
619 FW_DOMAIN_ID_BLITTER,
625 enum forcewake_domains {
626 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
627 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
628 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
629 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
634 struct intel_uncore_funcs {
635 void (*force_wake_get)(struct drm_i915_private *dev_priv,
636 enum forcewake_domains domains);
637 void (*force_wake_put)(struct drm_i915_private *dev_priv,
638 enum forcewake_domains domains);
640 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
641 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
642 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
643 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
645 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
646 uint8_t val, bool trace);
647 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
648 uint16_t val, bool trace);
649 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
650 uint32_t val, bool trace);
651 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
652 uint64_t val, bool trace);
655 struct intel_uncore {
656 spinlock_t lock; /** lock is also taken in irq contexts. */
658 struct intel_uncore_funcs funcs;
661 enum forcewake_domains fw_domains;
663 struct intel_uncore_forcewake_domain {
664 struct drm_i915_private *i915;
665 enum forcewake_domain_id id;
667 struct timer_list timer;
674 } fw_domain[FW_DOMAIN_ID_COUNT];
676 int unclaimed_mmio_check;
679 /* Iterate over initialised fw domains */
680 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
681 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
682 (i__) < FW_DOMAIN_ID_COUNT; \
683 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
684 for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
686 #define for_each_fw_domain(domain__, dev_priv__, i__) \
687 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
689 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
690 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
691 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
694 struct work_struct work;
696 uint32_t *dmc_payload;
697 uint32_t dmc_fw_size;
700 i915_reg_t mmioaddr[8];
701 uint32_t mmiodata[8];
703 uint32_t allowed_dc_mask;
706 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
707 func(is_mobile) sep \
710 func(is_i945gm) sep \
712 func(need_gfx_hws) sep \
714 func(is_pineview) sep \
715 func(is_broadwater) sep \
716 func(is_crestline) sep \
717 func(is_ivybridge) sep \
718 func(is_valleyview) sep \
719 func(is_cherryview) sep \
720 func(is_haswell) sep \
721 func(is_skylake) sep \
722 func(is_broxton) sep \
723 func(is_kabylake) sep \
724 func(is_preliminary) sep \
726 func(has_pipe_cxsr) sep \
727 func(has_hotplug) sep \
728 func(cursor_needs_physical) sep \
729 func(has_overlay) sep \
730 func(overlay_needs_physical) sep \
731 func(supports_tv) sep \
733 func(has_snoop) sep \
737 #define DEFINE_FLAG(name) u8 name:1
738 #define SEP_SEMICOLON ;
740 struct intel_device_info {
741 u32 display_mmio_offset;
744 u8 num_sprites[I915_MAX_PIPES];
746 u8 ring_mask; /* Rings supported by the HW */
747 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
748 /* Register offsets for the various display pipes and transcoders */
749 int pipe_offsets[I915_MAX_TRANSCODERS];
750 int trans_offsets[I915_MAX_TRANSCODERS];
751 int palette_offsets[I915_MAX_PIPES];
752 int cursor_offsets[I915_MAX_PIPES];
754 /* Slice/subslice/EU info */
757 u8 subslice_per_slice;
760 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
763 u8 has_subslice_pg:1;
770 enum i915_cache_level {
772 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
773 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
774 caches, eg sampler/render caches, and the
775 large Last-Level-Cache. LLC is coherent with
776 the CPU, but L3 is only visible to the GPU. */
777 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
780 struct i915_ctx_hang_stats {
781 /* This context had batch pending when hang was declared */
782 unsigned batch_pending;
784 /* This context had batch active when hang was declared */
785 unsigned batch_active;
787 /* Time when this context was last blamed for a GPU reset */
788 unsigned long guilty_ts;
790 /* If the contexts causes a second GPU hang within this time,
791 * it is permanently banned from submitting any more work.
793 unsigned long ban_period_seconds;
795 /* This context is banned to submit more work */
799 /* This must match up with the value previously used for execbuf2.rsvd1. */
800 #define DEFAULT_CONTEXT_HANDLE 0
802 #define CONTEXT_NO_ZEROMAP (1<<0)
804 * struct intel_context - as the name implies, represents a context.
805 * @ref: reference count.
806 * @user_handle: userspace tracking identity for this context.
807 * @remap_slice: l3 row remapping information.
808 * @flags: context specific flags:
809 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
810 * @file_priv: filp associated with this context (NULL for global default
812 * @hang_stats: information about the role of this context in possible GPU
814 * @ppgtt: virtual memory space used by this context.
815 * @legacy_hw_ctx: render context backing object and whether it is correctly
816 * initialized (legacy ring submission mechanism only).
817 * @link: link in the global list of contexts.
819 * Contexts are memory images used by the hardware to store copies of their
822 struct intel_context {
826 struct drm_i915_private *i915;
828 struct drm_i915_file_private *file_priv;
829 struct i915_ctx_hang_stats hang_stats;
830 struct i915_hw_ppgtt *ppgtt;
832 /* Legacy ring buffer submission */
834 struct drm_i915_gem_object *rcs_state;
840 struct drm_i915_gem_object *state;
841 struct intel_ringbuffer *ringbuf;
843 struct i915_vma *lrc_vma;
845 uint32_t *lrc_reg_state;
846 } engine[I915_NUM_ENGINES];
848 struct list_head link;
860 /* This is always the inner lock when overlapping with struct_mutex and
861 * it's the outer lock when overlapping with stolen_lock. */
864 unsigned int possible_framebuffer_bits;
865 unsigned int busy_bits;
866 unsigned int visible_pipes_mask;
867 struct intel_crtc *crtc;
869 struct drm_mm_node compressed_fb;
870 struct drm_mm_node *compressed_llb;
877 struct intel_fbc_state_cache {
879 unsigned int mode_flags;
880 uint32_t hsw_bdw_pixel_rate;
884 unsigned int rotation;
892 uint32_t pixel_format;
895 unsigned int tiling_mode;
899 struct intel_fbc_reg_params {
903 unsigned int fence_y_offset;
908 uint32_t pixel_format;
916 struct intel_fbc_work {
918 u32 scheduled_vblank;
919 struct work_struct work;
922 const char *no_fbc_reason;
926 * HIGH_RR is the highest eDP panel refresh rate read from EDID
927 * LOW_RR is the lowest eDP panel refresh rate found from EDID
928 * parsing for same resolution.
930 enum drrs_refresh_rate_type {
933 DRRS_MAX_RR, /* RR count */
936 enum drrs_support_type {
937 DRRS_NOT_SUPPORTED = 0,
938 STATIC_DRRS_SUPPORT = 1,
939 SEAMLESS_DRRS_SUPPORT = 2
945 struct delayed_work work;
947 unsigned busy_frontbuffer_bits;
948 enum drrs_refresh_rate_type refresh_rate_type;
949 enum drrs_support_type type;
956 struct intel_dp *enabled;
958 struct delayed_work work;
959 unsigned busy_frontbuffer_bits;
966 PCH_NONE = 0, /* No PCH present */
967 PCH_IBX, /* Ibexpeak PCH */
968 PCH_CPT, /* Cougarpoint PCH */
969 PCH_LPT, /* Lynxpoint PCH */
970 PCH_SPT, /* Sunrisepoint PCH */
974 enum intel_sbi_destination {
979 #define QUIRK_PIPEA_FORCE (1<<0)
980 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
981 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
982 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
983 #define QUIRK_PIPEB_FORCE (1<<4)
984 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
987 struct intel_fbc_work;
990 struct i2c_adapter adapter;
994 struct i2c_algo_bit_data bit_algo;
995 struct drm_i915_private *dev_priv;
998 struct i915_suspend_saved_registers {
1001 u32 savePP_ON_DELAYS;
1002 u32 savePP_OFF_DELAYS;
1007 u32 saveFBC_CONTROL;
1008 u32 saveCACHE_MODE_0;
1009 u32 saveMI_ARB_STATE;
1013 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1014 u32 savePCH_PORT_HOTPLUG;
1018 struct vlv_s0ix_state {
1025 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1026 u32 media_max_req_count;
1027 u32 gfx_max_req_count;
1053 u32 rp_down_timeout;
1059 /* Display 1 CZ domain */
1064 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1066 /* GT SA CZ domain */
1073 /* Display 2 CZ domain */
1077 u32 clock_gate_dis2;
1080 struct intel_rps_ei {
1086 struct intel_gen6_power_mgmt {
1088 * work, interrupts_enabled and pm_iir are protected by
1089 * dev_priv->irq_lock
1091 struct work_struct work;
1092 bool interrupts_enabled;
1095 /* Frequencies are stored in potentially platform dependent multiples.
1096 * In other words, *_freq needs to be multiplied by X to be interesting.
1097 * Soft limits are those which are used for the dynamic reclocking done
1098 * by the driver (raise frequencies under heavy loads, and lower for
1099 * lighter loads). Hard limits are those imposed by the hardware.
1101 * A distinction is made for overclocking, which is never enabled by
1102 * default, and is considered to be above the hard limit if it's
1105 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1106 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1107 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1108 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1109 u8 min_freq; /* AKA RPn. Minimum frequency */
1110 u8 idle_freq; /* Frequency to request when we are idle */
1111 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1112 u8 rp1_freq; /* "less than" RP0 power/freqency */
1113 u8 rp0_freq; /* Non-overclocked max frequency. */
1115 u8 up_threshold; /* Current %busy required to uplock */
1116 u8 down_threshold; /* Current %busy required to downclock */
1119 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1121 spinlock_t client_lock;
1122 struct list_head clients;
1126 struct delayed_work delayed_resume_work;
1129 struct intel_rps_client semaphores, mmioflips;
1131 /* manual wa residency calculations */
1132 struct intel_rps_ei up_ei, down_ei;
1135 * Protects RPS/RC6 register access and PCU communication.
1136 * Must be taken after struct_mutex if nested. Note that
1137 * this lock may be held for long periods of time when
1138 * talking to hw - so only take it when talking to hw!
1140 struct mutex hw_lock;
1143 /* defined intel_pm.c */
1144 extern spinlock_t mchdev_lock;
1146 struct intel_ilk_power_mgmt {
1154 unsigned long last_time1;
1155 unsigned long chipset_power;
1158 unsigned long gfx_power;
1165 struct drm_i915_private;
1166 struct i915_power_well;
1168 struct i915_power_well_ops {
1170 * Synchronize the well's hw state to match the current sw state, for
1171 * example enable/disable it based on the current refcount. Called
1172 * during driver init and resume time, possibly after first calling
1173 * the enable/disable handlers.
1175 void (*sync_hw)(struct drm_i915_private *dev_priv,
1176 struct i915_power_well *power_well);
1178 * Enable the well and resources that depend on it (for example
1179 * interrupts located on the well). Called after the 0->1 refcount
1182 void (*enable)(struct drm_i915_private *dev_priv,
1183 struct i915_power_well *power_well);
1185 * Disable the well and resources that depend on it. Called after
1186 * the 1->0 refcount transition.
1188 void (*disable)(struct drm_i915_private *dev_priv,
1189 struct i915_power_well *power_well);
1190 /* Returns the hw enabled state. */
1191 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1192 struct i915_power_well *power_well);
1195 /* Power well structure for haswell */
1196 struct i915_power_well {
1199 /* power well enable/disable usage count */
1201 /* cached hw enabled state */
1203 unsigned long domains;
1205 const struct i915_power_well_ops *ops;
1208 struct i915_power_domains {
1210 * Power wells needed for initialization at driver init and suspend
1211 * time are on. They are kept on until after the first modeset.
1215 int power_well_count;
1218 int domain_use_count[POWER_DOMAIN_NUM];
1219 struct i915_power_well *power_wells;
1222 #define MAX_L3_SLICES 2
1223 struct intel_l3_parity {
1224 u32 *remap_info[MAX_L3_SLICES];
1225 struct work_struct error_work;
1229 struct i915_gem_mm {
1230 /** Memory allocator for GTT stolen memory */
1231 struct drm_mm stolen;
1232 /** Protects the usage of the GTT stolen memory allocator. This is
1233 * always the inner lock when overlapping with struct_mutex. */
1234 struct mutex stolen_lock;
1236 /** List of all objects in gtt_space. Used to restore gtt
1237 * mappings on resume */
1238 struct list_head bound_list;
1240 * List of objects which are not bound to the GTT (thus
1241 * are idle and not used by the GPU) but still have
1242 * (presumably uncached) pages still attached.
1244 struct list_head unbound_list;
1246 /** Usable portion of the GTT for GEM */
1247 unsigned long stolen_base; /* limited to low memory (32-bit) */
1249 /** PPGTT used for aliasing the PPGTT with the GTT */
1250 struct i915_hw_ppgtt *aliasing_ppgtt;
1252 struct notifier_block oom_notifier;
1253 struct shrinker shrinker;
1254 bool shrinker_no_lock_stealing;
1256 /** LRU list of objects with fence regs on them. */
1257 struct list_head fence_list;
1260 * We leave the user IRQ off as much as possible,
1261 * but this means that requests will finish and never
1262 * be retired once the system goes idle. Set a timer to
1263 * fire periodically while the ring is running. When it
1264 * fires, go retire requests.
1266 struct delayed_work retire_work;
1269 * When we detect an idle GPU, we want to turn on
1270 * powersaving features. So once we see that there
1271 * are no more requests outstanding and no more
1272 * arrive within a small period of time, we fire
1273 * off the idle_work.
1275 struct delayed_work idle_work;
1278 * Are we in a non-interruptible section of code like
1284 * Is the GPU currently considered idle, or busy executing userspace
1285 * requests? Whilst idle, we attempt to power down the hardware and
1286 * display clocks. In order to reduce the effect on performance, there
1287 * is a slight delay before we do so.
1291 /* the indicator for dispatch video commands on two BSD rings */
1292 unsigned int bsd_ring_dispatch_index;
1294 /** Bit 6 swizzling required for X tiling */
1295 uint32_t bit_6_swizzle_x;
1296 /** Bit 6 swizzling required for Y tiling */
1297 uint32_t bit_6_swizzle_y;
1299 /* accounting, useful for userland debugging */
1300 spinlock_t object_stat_lock;
1301 size_t object_memory;
1305 struct drm_i915_error_state_buf {
1306 struct drm_i915_private *i915;
1315 struct i915_error_state_file_priv {
1316 struct drm_device *dev;
1317 struct drm_i915_error_state *error;
1320 struct i915_gpu_error {
1321 /* For hangcheck timer */
1322 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1323 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1324 /* Hang gpu twice in this window and your context gets banned */
1325 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1327 struct workqueue_struct *hangcheck_wq;
1328 struct delayed_work hangcheck_work;
1330 /* For reset and error_state handling. */
1332 /* Protected by the above dev->gpu_error.lock. */
1333 struct drm_i915_error_state *first_error;
1335 unsigned long missed_irq_rings;
1338 * State variable controlling the reset flow and count
1340 * This is a counter which gets incremented when reset is triggered,
1341 * and again when reset has been handled. So odd values (lowest bit set)
1342 * means that reset is in progress and even values that
1343 * (reset_counter >> 1):th reset was successfully completed.
1345 * If reset is not completed succesfully, the I915_WEDGE bit is
1346 * set meaning that hardware is terminally sour and there is no
1347 * recovery. All waiters on the reset_queue will be woken when
1350 * This counter is used by the wait_seqno code to notice that reset
1351 * event happened and it needs to restart the entire ioctl (since most
1352 * likely the seqno it waited for won't ever signal anytime soon).
1354 * This is important for lock-free wait paths, where no contended lock
1355 * naturally enforces the correct ordering between the bail-out of the
1356 * waiter and the gpu reset work code.
1358 atomic_t reset_counter;
1360 #define I915_RESET_IN_PROGRESS_FLAG 1
1361 #define I915_WEDGED (1 << 31)
1364 * Waitqueue to signal when the reset has completed. Used by clients
1365 * that wait for dev_priv->mm.wedged to settle.
1367 wait_queue_head_t reset_queue;
1369 /* Userspace knobs for gpu hang simulation;
1370 * combines both a ring mask, and extra flags
1373 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1374 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1376 /* For missed irq/seqno simulation. */
1377 unsigned int test_irq_rings;
1379 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1380 bool reload_in_reset;
1383 enum modeset_restore {
1384 MODESET_ON_LID_OPEN,
1389 #define DP_AUX_A 0x40
1390 #define DP_AUX_B 0x10
1391 #define DP_AUX_C 0x20
1392 #define DP_AUX_D 0x30
1394 #define DDC_PIN_B 0x05
1395 #define DDC_PIN_C 0x04
1396 #define DDC_PIN_D 0x06
1398 struct ddi_vbt_port_info {
1400 * This is an index in the HDMI/DVI DDI buffer translation table.
1401 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1402 * populate this field.
1404 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1405 uint8_t hdmi_level_shift;
1407 uint8_t supports_dvi:1;
1408 uint8_t supports_hdmi:1;
1409 uint8_t supports_dp:1;
1411 uint8_t alternate_aux_channel;
1412 uint8_t alternate_ddc_pin;
1414 uint8_t dp_boost_level;
1415 uint8_t hdmi_boost_level;
1418 enum psr_lines_to_wait {
1419 PSR_0_LINES_TO_WAIT = 0,
1421 PSR_4_LINES_TO_WAIT,
1425 struct intel_vbt_data {
1426 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1427 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1430 unsigned int int_tv_support:1;
1431 unsigned int lvds_dither:1;
1432 unsigned int lvds_vbt:1;
1433 unsigned int int_crt_support:1;
1434 unsigned int lvds_use_ssc:1;
1435 unsigned int display_clock_mode:1;
1436 unsigned int fdi_rx_polarity_inverted:1;
1438 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1440 enum drrs_support_type drrs_type;
1445 int edp_preemphasis;
1447 bool edp_initialized;
1450 struct edp_power_seq edp_pps;
1454 bool require_aux_wakeup;
1456 enum psr_lines_to_wait lines_to_wait;
1457 int tp1_wakeup_time;
1458 int tp2_tp3_wakeup_time;
1464 bool active_low_pwm;
1465 u8 min_brightness; /* min_brightness/255 of max */
1471 struct mipi_config *config;
1472 struct mipi_pps_data *pps;
1476 const u8 *sequence[MIPI_SEQ_MAX];
1482 union child_device_config *child_dev;
1484 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1487 enum intel_ddb_partitioning {
1489 INTEL_DDB_PART_5_6, /* IVB+ */
1492 struct intel_wm_level {
1500 struct ilk_wm_values {
1501 uint32_t wm_pipe[3];
1503 uint32_t wm_lp_spr[3];
1504 uint32_t wm_linetime[3];
1506 enum intel_ddb_partitioning partitioning;
1509 struct vlv_pipe_wm {
1520 struct vlv_wm_values {
1521 struct vlv_pipe_wm pipe[3];
1522 struct vlv_sr_wm sr;
1532 struct skl_ddb_entry {
1533 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1536 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1538 return entry->end - entry->start;
1541 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1542 const struct skl_ddb_entry *e2)
1544 if (e1->start == e2->start && e1->end == e2->end)
1550 struct skl_ddb_allocation {
1551 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1552 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1553 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1556 struct skl_wm_values {
1557 bool dirty[I915_MAX_PIPES];
1558 struct skl_ddb_allocation ddb;
1559 uint32_t wm_linetime[I915_MAX_PIPES];
1560 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1561 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1564 struct skl_wm_level {
1565 bool plane_en[I915_MAX_PLANES];
1566 uint16_t plane_res_b[I915_MAX_PLANES];
1567 uint8_t plane_res_l[I915_MAX_PLANES];
1571 * This struct helps tracking the state needed for runtime PM, which puts the
1572 * device in PCI D3 state. Notice that when this happens, nothing on the
1573 * graphics device works, even register access, so we don't get interrupts nor
1576 * Every piece of our code that needs to actually touch the hardware needs to
1577 * either call intel_runtime_pm_get or call intel_display_power_get with the
1578 * appropriate power domain.
1580 * Our driver uses the autosuspend delay feature, which means we'll only really
1581 * suspend if we stay with zero refcount for a certain amount of time. The
1582 * default value is currently very conservative (see intel_runtime_pm_enable), but
1583 * it can be changed with the standard runtime PM files from sysfs.
1585 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1586 * goes back to false exactly before we reenable the IRQs. We use this variable
1587 * to check if someone is trying to enable/disable IRQs while they're supposed
1588 * to be disabled. This shouldn't happen and we'll print some error messages in
1591 * For more, read the Documentation/power/runtime_pm.txt.
1593 struct i915_runtime_pm {
1594 atomic_t wakeref_count;
1595 atomic_t atomic_seq;
1600 enum intel_pipe_crc_source {
1601 INTEL_PIPE_CRC_SOURCE_NONE,
1602 INTEL_PIPE_CRC_SOURCE_PLANE1,
1603 INTEL_PIPE_CRC_SOURCE_PLANE2,
1604 INTEL_PIPE_CRC_SOURCE_PF,
1605 INTEL_PIPE_CRC_SOURCE_PIPE,
1606 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1607 INTEL_PIPE_CRC_SOURCE_TV,
1608 INTEL_PIPE_CRC_SOURCE_DP_B,
1609 INTEL_PIPE_CRC_SOURCE_DP_C,
1610 INTEL_PIPE_CRC_SOURCE_DP_D,
1611 INTEL_PIPE_CRC_SOURCE_AUTO,
1612 INTEL_PIPE_CRC_SOURCE_MAX,
1615 struct intel_pipe_crc_entry {
1620 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1621 struct intel_pipe_crc {
1623 bool opened; /* exclusive access to the result file */
1624 struct intel_pipe_crc_entry *entries;
1625 enum intel_pipe_crc_source source;
1627 wait_queue_head_t wq;
1630 struct i915_frontbuffer_tracking {
1634 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1641 struct i915_wa_reg {
1644 /* bitmask representing WA bits */
1649 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1650 * allowing it for RCS as we don't foresee any requirement of having
1651 * a whitelist for other engines. When it is really required for
1652 * other engines then the limit need to be increased.
1654 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1656 struct i915_workarounds {
1657 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1659 u32 hw_whitelist_count[I915_NUM_ENGINES];
1662 struct i915_virtual_gpu {
1666 struct i915_execbuffer_params {
1667 struct drm_device *dev;
1668 struct drm_file *file;
1669 uint32_t dispatch_flags;
1670 uint32_t args_batch_start_offset;
1671 uint64_t batch_obj_vm_offset;
1672 struct intel_engine_cs *engine;
1673 struct drm_i915_gem_object *batch_obj;
1674 struct intel_context *ctx;
1675 struct drm_i915_gem_request *request;
1678 /* used in computing the new watermarks state */
1679 struct intel_wm_config {
1680 unsigned int num_pipes_active;
1681 bool sprites_enabled;
1682 bool sprites_scaled;
1685 struct drm_i915_private {
1686 struct drm_device *dev;
1687 struct kmem_cache *objects;
1688 struct kmem_cache *vmas;
1689 struct kmem_cache *requests;
1691 const struct intel_device_info info;
1693 int relative_constants_mode;
1697 struct intel_uncore uncore;
1699 struct i915_virtual_gpu vgpu;
1701 struct intel_guc guc;
1703 struct intel_csr csr;
1705 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1707 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1708 * controller on different i2c buses. */
1709 struct mutex gmbus_mutex;
1712 * Base address of the gmbus and gpio block.
1714 uint32_t gpio_mmio_base;
1716 /* MMIO base address for MIPI regs */
1717 uint32_t mipi_mmio_base;
1719 uint32_t psr_mmio_base;
1721 wait_queue_head_t gmbus_wait_queue;
1723 struct pci_dev *bridge_dev;
1724 struct intel_engine_cs engine[I915_NUM_ENGINES];
1725 struct drm_i915_gem_object *semaphore_obj;
1726 uint32_t last_seqno, next_seqno;
1728 struct drm_dma_handle *status_page_dmah;
1729 struct resource mch_res;
1731 /* protects the irq masks */
1732 spinlock_t irq_lock;
1734 /* protects the mmio flip data */
1735 spinlock_t mmio_flip_lock;
1737 bool display_irqs_enabled;
1739 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1740 struct pm_qos_request pm_qos;
1742 /* Sideband mailbox protection */
1743 struct mutex sb_lock;
1745 /** Cached value of IMR to avoid reads in updating the bitfield */
1748 u32 de_irq_mask[I915_MAX_PIPES];
1753 u32 pipestat_irq_mask[I915_MAX_PIPES];
1755 struct i915_hotplug hotplug;
1756 struct intel_fbc fbc;
1757 struct i915_drrs drrs;
1758 struct intel_opregion opregion;
1759 struct intel_vbt_data vbt;
1761 bool preserve_bios_swizzle;
1764 struct intel_overlay *overlay;
1766 /* backlight registers and fields in struct intel_panel */
1767 struct mutex backlight_lock;
1770 bool no_aux_handshake;
1772 /* protects panel power sequencer state */
1773 struct mutex pps_mutex;
1775 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1776 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1778 unsigned int fsb_freq, mem_freq, is_ddr3;
1779 unsigned int skl_boot_cdclk;
1780 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1781 unsigned int max_dotclk_freq;
1782 unsigned int rawclk_freq;
1783 unsigned int hpll_freq;
1784 unsigned int czclk_freq;
1787 * wq - Driver workqueue for GEM.
1789 * NOTE: Work items scheduled here are not allowed to grab any modeset
1790 * locks, for otherwise the flushing done in the pageflip code will
1791 * result in deadlocks.
1793 struct workqueue_struct *wq;
1795 /* Display functions */
1796 struct drm_i915_display_funcs display;
1798 /* PCH chipset type */
1799 enum intel_pch pch_type;
1800 unsigned short pch_id;
1802 unsigned long quirks;
1804 enum modeset_restore modeset_restore;
1805 struct mutex modeset_restore_lock;
1806 struct drm_atomic_state *modeset_restore_state;
1808 struct list_head vm_list; /* Global list of all address spaces */
1809 struct i915_gtt gtt; /* VM representing the global address space */
1811 struct i915_gem_mm mm;
1812 DECLARE_HASHTABLE(mm_structs, 7);
1813 struct mutex mm_lock;
1815 /* Kernel Modesetting */
1817 struct sdvo_device_mapping sdvo_mappings[2];
1819 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1820 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1821 wait_queue_head_t pending_flip_queue;
1823 #ifdef CONFIG_DEBUG_FS
1824 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1827 /* dpll and cdclk state is protected by connection_mutex */
1828 int num_shared_dpll;
1829 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1830 const struct intel_dpll_mgr *dpll_mgr;
1832 unsigned int active_crtcs;
1833 unsigned int min_pixclk[I915_MAX_PIPES];
1835 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1837 struct i915_workarounds workarounds;
1839 /* Reclocking support */
1840 bool render_reclock_avail;
1842 struct i915_frontbuffer_tracking fb_tracking;
1846 bool mchbar_need_disable;
1848 struct intel_l3_parity l3_parity;
1850 /* Cannot be determined by PCIID. You must always read a register. */
1853 /* gen6+ rps state */
1854 struct intel_gen6_power_mgmt rps;
1856 /* ilk-only ips/rps state. Everything in here is protected by the global
1857 * mchdev_lock in intel_pm.c */
1858 struct intel_ilk_power_mgmt ips;
1860 struct i915_power_domains power_domains;
1862 struct i915_psr psr;
1864 struct i915_gpu_error gpu_error;
1866 struct drm_i915_gem_object *vlv_pctx;
1868 #ifdef CONFIG_DRM_FBDEV_EMULATION
1869 /* list of fbdev register on this device */
1870 struct intel_fbdev *fbdev;
1871 struct work_struct fbdev_suspend_work;
1874 struct drm_property *broadcast_rgb_property;
1875 struct drm_property *force_audio_property;
1877 /* hda/i915 audio component */
1878 struct i915_audio_component *audio_component;
1879 bool audio_component_registered;
1881 * av_mutex - mutex for audio/video sync
1884 struct mutex av_mutex;
1886 uint32_t hw_context_size;
1887 struct list_head context_list;
1891 u32 chv_phy_control;
1894 bool suspended_to_idle;
1895 struct i915_suspend_saved_registers regfile;
1896 struct vlv_s0ix_state vlv_s0ix_state;
1900 * Raw watermark latency values:
1901 * in 0.1us units for WM0,
1902 * in 0.5us units for WM1+.
1905 uint16_t pri_latency[5];
1907 uint16_t spr_latency[5];
1909 uint16_t cur_latency[5];
1911 * Raw watermark memory latency values
1912 * for SKL for all 8 levels
1915 uint16_t skl_latency[8];
1917 /* Committed wm config */
1918 struct intel_wm_config config;
1921 * The skl_wm_values structure is a bit too big for stack
1922 * allocation, so we keep the staging struct where we store
1923 * intermediate results here instead.
1925 struct skl_wm_values skl_results;
1927 /* current hardware state */
1929 struct ilk_wm_values hw;
1930 struct skl_wm_values skl_hw;
1931 struct vlv_wm_values vlv;
1937 * Should be held around atomic WM register writing; also
1938 * protects * intel_crtc->wm.active and
1939 * cstate->wm.need_postvbl_update.
1941 struct mutex wm_mutex;
1944 struct i915_runtime_pm pm;
1946 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1948 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1949 struct drm_i915_gem_execbuffer2 *args,
1950 struct list_head *vmas);
1951 int (*init_engines)(struct drm_device *dev);
1952 void (*cleanup_engine)(struct intel_engine_cs *engine);
1953 void (*stop_engine)(struct intel_engine_cs *engine);
1956 struct intel_context *kernel_context;
1958 bool edp_low_vswing;
1960 /* perform PHY state sanity checks? */
1961 bool chv_phy_assert[2];
1963 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
1966 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1967 * will be rejected. Instead look for a better place.
1971 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1973 return dev->dev_private;
1976 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1978 return to_i915(dev_get_drvdata(dev));
1981 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
1983 return container_of(guc, struct drm_i915_private, guc);
1986 /* Iterate over initialised rings */
1987 #define for_each_engine(ring__, dev_priv__, i__) \
1988 for ((i__) = 0; (i__) < I915_NUM_ENGINES; (i__)++) \
1989 for_each_if ((((ring__) = &(dev_priv__)->engine[(i__)]), intel_engine_initialized((ring__))))
1991 enum hdmi_force_audio {
1992 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1993 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1994 HDMI_AUDIO_AUTO, /* trust EDID */
1995 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1998 #define I915_GTT_OFFSET_NONE ((u32)-1)
2000 struct drm_i915_gem_object_ops {
2002 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2004 /* Interface between the GEM object and its backing storage.
2005 * get_pages() is called once prior to the use of the associated set
2006 * of pages before to binding them into the GTT, and put_pages() is
2007 * called after we no longer need them. As we expect there to be
2008 * associated cost with migrating pages between the backing storage
2009 * and making them available for the GPU (e.g. clflush), we may hold
2010 * onto the pages after they are no longer referenced by the GPU
2011 * in case they may be used again shortly (for example migrating the
2012 * pages to a different memory domain within the GTT). put_pages()
2013 * will therefore most likely be called when the object itself is
2014 * being released or under memory pressure (where we attempt to
2015 * reap pages for the shrinker).
2017 int (*get_pages)(struct drm_i915_gem_object *);
2018 void (*put_pages)(struct drm_i915_gem_object *);
2020 int (*dmabuf_export)(struct drm_i915_gem_object *);
2021 void (*release)(struct drm_i915_gem_object *);
2025 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2026 * considered to be the frontbuffer for the given plane interface-wise. This
2027 * doesn't mean that the hw necessarily already scans it out, but that any
2028 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2030 * We have one bit per pipe and per scanout plane type.
2032 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2033 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2034 #define INTEL_FRONTBUFFER_BITS \
2035 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2036 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2037 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2038 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2039 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2040 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2041 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2042 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2043 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2044 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2045 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2047 struct drm_i915_gem_object {
2048 struct drm_gem_object base;
2050 const struct drm_i915_gem_object_ops *ops;
2052 /** List of VMAs backed by this object */
2053 struct list_head vma_list;
2055 /** Stolen memory for this object, instead of being backed by shmem. */
2056 struct drm_mm_node *stolen;
2057 struct list_head global_list;
2059 struct list_head engine_list[I915_NUM_ENGINES];
2060 /** Used in execbuf to temporarily hold a ref */
2061 struct list_head obj_exec_link;
2063 struct list_head batch_pool_link;
2066 * This is set if the object is on the active lists (has pending
2067 * rendering and so a non-zero seqno), and is not set if it i s on
2068 * inactive (ready to be unbound) list.
2070 unsigned int active:I915_NUM_ENGINES;
2073 * This is set if the object has been written to since last bound
2076 unsigned int dirty:1;
2079 * Fence register bits (if any) for this object. Will be set
2080 * as needed when mapped into the GTT.
2081 * Protected by dev->struct_mutex.
2083 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2086 * Advice: are the backing pages purgeable?
2088 unsigned int madv:2;
2091 * Current tiling mode for the object.
2093 unsigned int tiling_mode:2;
2095 * Whether the tiling parameters for the currently associated fence
2096 * register have changed. Note that for the purposes of tracking
2097 * tiling changes we also treat the unfenced register, the register
2098 * slot that the object occupies whilst it executes a fenced
2099 * command (such as BLT on gen2/3), as a "fence".
2101 unsigned int fence_dirty:1;
2104 * Is the object at the current location in the gtt mappable and
2105 * fenceable? Used to avoid costly recalculations.
2107 unsigned int map_and_fenceable:1;
2110 * Whether the current gtt mapping needs to be mappable (and isn't just
2111 * mappable by accident). Track pin and fault separate for a more
2112 * accurate mappable working set.
2114 unsigned int fault_mappable:1;
2117 * Is the object to be mapped as read-only to the GPU
2118 * Only honoured if hardware has relevant pte bit
2120 unsigned long gt_ro:1;
2121 unsigned int cache_level:3;
2122 unsigned int cache_dirty:1;
2124 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2126 unsigned int pin_display;
2128 struct sg_table *pages;
2129 int pages_pin_count;
2131 struct scatterlist *sg;
2135 /* prime dma-buf support */
2136 void *dma_buf_vmapping;
2139 /** Breadcrumb of last rendering to the buffer.
2140 * There can only be one writer, but we allow for multiple readers.
2141 * If there is a writer that necessarily implies that all other
2142 * read requests are complete - but we may only be lazily clearing
2143 * the read requests. A read request is naturally the most recent
2144 * request on a ring, so we may have two different write and read
2145 * requests on one ring where the write request is older than the
2146 * read request. This allows for the CPU to read from an active
2147 * buffer by only waiting for the write to complete.
2149 struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES];
2150 struct drm_i915_gem_request *last_write_req;
2151 /** Breadcrumb of last fenced GPU access to the buffer. */
2152 struct drm_i915_gem_request *last_fenced_req;
2154 /** Current tiling stride for the object, if it's tiled. */
2157 /** References from framebuffers, locks out tiling changes. */
2158 unsigned long framebuffer_references;
2160 /** Record of address bit 17 of each page at last unbind. */
2161 unsigned long *bit_17;
2164 /** for phy allocated objects */
2165 struct drm_dma_handle *phys_handle;
2167 struct i915_gem_userptr {
2169 unsigned read_only :1;
2170 unsigned workers :4;
2171 #define I915_GEM_USERPTR_MAX_WORKERS 15
2173 struct i915_mm_struct *mm;
2174 struct i915_mmu_object *mmu_object;
2175 struct work_struct *work;
2179 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2181 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2182 struct drm_i915_gem_object *new,
2183 unsigned frontbuffer_bits);
2186 * Request queue structure.
2188 * The request queue allows us to note sequence numbers that have been emitted
2189 * and may be associated with active buffers to be retired.
2191 * By keeping this list, we can avoid having to do questionable sequence
2192 * number comparisons on buffer last_read|write_seqno. It also allows an
2193 * emission time to be associated with the request for tracking how far ahead
2194 * of the GPU the submission is.
2196 * The requests are reference counted, so upon creation they should have an
2197 * initial reference taken using kref_init
2199 struct drm_i915_gem_request {
2202 /** On Which ring this request was generated */
2203 struct drm_i915_private *i915;
2204 struct intel_engine_cs *engine;
2206 /** GEM sequence number associated with the previous request,
2207 * when the HWS breadcrumb is equal to this the GPU is processing
2212 /** GEM sequence number associated with this request,
2213 * when the HWS breadcrumb is equal or greater than this the GPU
2214 * has finished processing this request.
2218 /** Position in the ringbuffer of the start of the request */
2222 * Position in the ringbuffer of the start of the postfix.
2223 * This is required to calculate the maximum available ringbuffer
2224 * space without overwriting the postfix.
2228 /** Position in the ringbuffer of the end of the whole request */
2232 * Context and ring buffer related to this request
2233 * Contexts are refcounted, so when this request is associated with a
2234 * context, we must increment the context's refcount, to guarantee that
2235 * it persists while any request is linked to it. Requests themselves
2236 * are also refcounted, so the request will only be freed when the last
2237 * reference to it is dismissed, and the code in
2238 * i915_gem_request_free() will then decrement the refcount on the
2241 struct intel_context *ctx;
2242 struct intel_ringbuffer *ringbuf;
2244 /** Batch buffer related to this request if any (used for
2245 error state dump only) */
2246 struct drm_i915_gem_object *batch_obj;
2248 /** Time at which this request was emitted, in jiffies. */
2249 unsigned long emitted_jiffies;
2251 /** global list entry for this request */
2252 struct list_head list;
2254 struct drm_i915_file_private *file_priv;
2255 /** file_priv list entry for this request */
2256 struct list_head client_list;
2258 /** process identifier submitting this request */
2262 * The ELSP only accepts two elements at a time, so we queue
2263 * context/tail pairs on a given queue (ring->execlist_queue) until the
2264 * hardware is available. The queue serves a double purpose: we also use
2265 * it to keep track of the up to 2 contexts currently in the hardware
2266 * (usually one in execution and the other queued up by the GPU): We
2267 * only remove elements from the head of the queue when the hardware
2268 * informs us that an element has been completed.
2270 * All accesses to the queue are mediated by a spinlock
2271 * (ring->execlist_lock).
2274 /** Execlist link in the submission queue.*/
2275 struct list_head execlist_link;
2277 /** Execlists no. of times this request has been sent to the ELSP */
2282 struct drm_i915_gem_request * __must_check
2283 i915_gem_request_alloc(struct intel_engine_cs *engine,
2284 struct intel_context *ctx);
2285 void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2286 void i915_gem_request_free(struct kref *req_ref);
2287 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2288 struct drm_file *file);
2290 static inline uint32_t
2291 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2293 return req ? req->seqno : 0;
2296 static inline struct intel_engine_cs *
2297 i915_gem_request_get_engine(struct drm_i915_gem_request *req)
2299 return req ? req->engine : NULL;
2302 static inline struct drm_i915_gem_request *
2303 i915_gem_request_reference(struct drm_i915_gem_request *req)
2306 kref_get(&req->ref);
2311 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2313 WARN_ON(!mutex_is_locked(&req->engine->dev->struct_mutex));
2314 kref_put(&req->ref, i915_gem_request_free);
2318 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2320 struct drm_device *dev;
2325 dev = req->engine->dev;
2326 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2327 mutex_unlock(&dev->struct_mutex);
2330 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2331 struct drm_i915_gem_request *src)
2334 i915_gem_request_reference(src);
2337 i915_gem_request_unreference(*pdst);
2343 * XXX: i915_gem_request_completed should be here but currently needs the
2344 * definition of i915_seqno_passed() which is below. It will be moved in
2345 * a later patch when the call to i915_seqno_passed() is obsoleted...
2349 * A command that requires special handling by the command parser.
2351 struct drm_i915_cmd_descriptor {
2353 * Flags describing how the command parser processes the command.
2355 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2356 * a length mask if not set
2357 * CMD_DESC_SKIP: The command is allowed but does not follow the
2358 * standard length encoding for the opcode range in
2360 * CMD_DESC_REJECT: The command is never allowed
2361 * CMD_DESC_REGISTER: The command should be checked against the
2362 * register whitelist for the appropriate ring
2363 * CMD_DESC_MASTER: The command is allowed if the submitting process
2367 #define CMD_DESC_FIXED (1<<0)
2368 #define CMD_DESC_SKIP (1<<1)
2369 #define CMD_DESC_REJECT (1<<2)
2370 #define CMD_DESC_REGISTER (1<<3)
2371 #define CMD_DESC_BITMASK (1<<4)
2372 #define CMD_DESC_MASTER (1<<5)
2375 * The command's unique identification bits and the bitmask to get them.
2376 * This isn't strictly the opcode field as defined in the spec and may
2377 * also include type, subtype, and/or subop fields.
2385 * The command's length. The command is either fixed length (i.e. does
2386 * not include a length field) or has a length field mask. The flag
2387 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2388 * a length mask. All command entries in a command table must include
2389 * length information.
2397 * Describes where to find a register address in the command to check
2398 * against the ring's register whitelist. Only valid if flags has the
2399 * CMD_DESC_REGISTER bit set.
2401 * A non-zero step value implies that the command may access multiple
2402 * registers in sequence (e.g. LRI), in that case step gives the
2403 * distance in dwords between individual offset fields.
2411 #define MAX_CMD_DESC_BITMASKS 3
2413 * Describes command checks where a particular dword is masked and
2414 * compared against an expected value. If the command does not match
2415 * the expected value, the parser rejects it. Only valid if flags has
2416 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2419 * If the check specifies a non-zero condition_mask then the parser
2420 * only performs the check when the bits specified by condition_mask
2427 u32 condition_offset;
2429 } bits[MAX_CMD_DESC_BITMASKS];
2433 * A table of commands requiring special handling by the command parser.
2435 * Each ring has an array of tables. Each table consists of an array of command
2436 * descriptors, which must be sorted with command opcodes in ascending order.
2438 struct drm_i915_cmd_table {
2439 const struct drm_i915_cmd_descriptor *table;
2443 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2444 #define __I915__(p) ({ \
2445 struct drm_i915_private *__p; \
2446 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2447 __p = (struct drm_i915_private *)p; \
2448 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2449 __p = to_i915((struct drm_device *)p); \
2454 #define INTEL_INFO(p) (&__I915__(p)->info)
2455 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2456 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2458 #define REVID_FOREVER 0xff
2460 * Return true if revision is in range [since,until] inclusive.
2462 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2464 #define IS_REVID(p, since, until) \
2465 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2467 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2468 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2469 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2470 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2471 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2472 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2473 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2474 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2475 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2476 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2477 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2478 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2479 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2480 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2481 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2482 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2483 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2484 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2485 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2486 INTEL_DEVID(dev) == 0x0152 || \
2487 INTEL_DEVID(dev) == 0x015a)
2488 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2489 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2490 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2491 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2492 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2493 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2494 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2495 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2496 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2497 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2498 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2499 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2500 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2501 (INTEL_DEVID(dev) & 0xf) == 0xe))
2502 /* ULX machines are also considered ULT. */
2503 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2504 (INTEL_DEVID(dev) & 0xf) == 0xe)
2505 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2506 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2507 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2508 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2509 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2510 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2511 /* ULX machines are also considered ULT. */
2512 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2513 INTEL_DEVID(dev) == 0x0A1E)
2514 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2515 INTEL_DEVID(dev) == 0x1913 || \
2516 INTEL_DEVID(dev) == 0x1916 || \
2517 INTEL_DEVID(dev) == 0x1921 || \
2518 INTEL_DEVID(dev) == 0x1926)
2519 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2520 INTEL_DEVID(dev) == 0x1915 || \
2521 INTEL_DEVID(dev) == 0x191E)
2522 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2523 INTEL_DEVID(dev) == 0x5913 || \
2524 INTEL_DEVID(dev) == 0x5916 || \
2525 INTEL_DEVID(dev) == 0x5921 || \
2526 INTEL_DEVID(dev) == 0x5926)
2527 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2528 INTEL_DEVID(dev) == 0x5915 || \
2529 INTEL_DEVID(dev) == 0x591E)
2530 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2531 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2532 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2533 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2535 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2537 #define SKL_REVID_A0 0x0
2538 #define SKL_REVID_B0 0x1
2539 #define SKL_REVID_C0 0x2
2540 #define SKL_REVID_D0 0x3
2541 #define SKL_REVID_E0 0x4
2542 #define SKL_REVID_F0 0x5
2544 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2546 #define BXT_REVID_A0 0x0
2547 #define BXT_REVID_A1 0x1
2548 #define BXT_REVID_B0 0x3
2549 #define BXT_REVID_C0 0x9
2551 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2554 * The genX designation typically refers to the render engine, so render
2555 * capability related checks should use IS_GEN, while display and other checks
2556 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2559 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2560 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2561 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2562 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2563 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2564 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2565 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2566 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2568 #define RENDER_RING (1<<RCS)
2569 #define BSD_RING (1<<VCS)
2570 #define BLT_RING (1<<BCS)
2571 #define VEBOX_RING (1<<VECS)
2572 #define BSD2_RING (1<<VCS2)
2573 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2574 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2575 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2576 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2577 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2578 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2579 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2580 __I915__(dev)->ellc_size)
2581 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2583 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2584 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2585 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2586 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2587 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2589 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2590 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2592 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2593 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2595 /* WaRsDisableCoarsePowerGating:skl,bxt */
2596 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2597 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
2598 IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
2600 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2601 * even when in MSI mode. This results in spurious interrupt warnings if the
2602 * legacy irq no. is shared with another device. The kernel then disables that
2603 * interrupt source and so prevents the other device from working properly.
2605 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2606 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2608 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2609 * rows, which changed the alignment requirements and fence programming.
2611 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2613 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2614 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2616 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2617 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2618 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2620 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2622 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2623 INTEL_INFO(dev)->gen >= 9)
2625 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2626 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2627 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2628 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2629 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2630 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2631 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2632 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2634 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2635 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2637 #define HAS_CSR(dev) (IS_GEN9(dev))
2639 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2640 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2642 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2643 INTEL_INFO(dev)->gen >= 8)
2645 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2646 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2649 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2650 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2651 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2652 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2653 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2654 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2655 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2656 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2657 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2658 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2660 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2661 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2662 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2663 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2664 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2665 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2666 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2667 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2668 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2670 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2671 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2673 /* DPF == dynamic parity feature */
2674 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2675 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2677 #define GT_FREQUENCY_MULTIPLIER 50
2678 #define GEN9_FREQ_SCALER 3
2680 #include "i915_trace.h"
2682 extern const struct drm_ioctl_desc i915_ioctls[];
2683 extern int i915_max_ioctl;
2685 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2686 extern int i915_resume_switcheroo(struct drm_device *dev);
2689 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2690 extern int i915_driver_unload(struct drm_device *);
2691 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2692 extern void i915_driver_lastclose(struct drm_device * dev);
2693 extern void i915_driver_preclose(struct drm_device *dev,
2694 struct drm_file *file);
2695 extern void i915_driver_postclose(struct drm_device *dev,
2696 struct drm_file *file);
2697 #ifdef CONFIG_COMPAT
2698 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2701 extern int intel_gpu_reset(struct drm_device *dev);
2702 extern bool intel_has_gpu_reset(struct drm_device *dev);
2703 extern int i915_reset(struct drm_device *dev);
2704 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2705 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2706 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2707 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2708 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2710 /* intel_hotplug.c */
2711 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2712 void intel_hpd_init(struct drm_i915_private *dev_priv);
2713 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2714 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2715 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2718 void i915_queue_hangcheck(struct drm_device *dev);
2720 void i915_handle_error(struct drm_device *dev, bool wedged,
2721 const char *fmt, ...);
2723 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2724 int intel_irq_install(struct drm_i915_private *dev_priv);
2725 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2727 extern void intel_uncore_sanitize(struct drm_device *dev);
2728 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2729 bool restore_forcewake);
2730 extern void intel_uncore_init(struct drm_device *dev);
2731 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2732 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2733 extern void intel_uncore_fini(struct drm_device *dev);
2734 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2735 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2736 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2737 enum forcewake_domains domains);
2738 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2739 enum forcewake_domains domains);
2740 /* Like above but the caller must manage the uncore.lock itself.
2741 * Must be used with I915_READ_FW and friends.
2743 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2744 enum forcewake_domains domains);
2745 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2746 enum forcewake_domains domains);
2747 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2748 static inline bool intel_vgpu_active(struct drm_device *dev)
2750 return to_i915(dev)->vgpu.active;
2754 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2758 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2761 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2762 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2763 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2766 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2767 uint32_t interrupt_mask,
2768 uint32_t enabled_irq_mask);
2770 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2772 ilk_update_display_irq(dev_priv, bits, bits);
2775 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2777 ilk_update_display_irq(dev_priv, bits, 0);
2779 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2781 uint32_t interrupt_mask,
2782 uint32_t enabled_irq_mask);
2783 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2784 enum pipe pipe, uint32_t bits)
2786 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2788 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2789 enum pipe pipe, uint32_t bits)
2791 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2793 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2794 uint32_t interrupt_mask,
2795 uint32_t enabled_irq_mask);
2797 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2799 ibx_display_interrupt_update(dev_priv, bits, bits);
2802 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2804 ibx_display_interrupt_update(dev_priv, bits, 0);
2809 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2810 struct drm_file *file_priv);
2811 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2812 struct drm_file *file_priv);
2813 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2814 struct drm_file *file_priv);
2815 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2816 struct drm_file *file_priv);
2817 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2818 struct drm_file *file_priv);
2819 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2820 struct drm_file *file_priv);
2821 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2822 struct drm_file *file_priv);
2823 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2824 struct drm_i915_gem_request *req);
2825 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2826 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2827 struct drm_i915_gem_execbuffer2 *args,
2828 struct list_head *vmas);
2829 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2830 struct drm_file *file_priv);
2831 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2832 struct drm_file *file_priv);
2833 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2834 struct drm_file *file_priv);
2835 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2836 struct drm_file *file);
2837 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2838 struct drm_file *file);
2839 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2840 struct drm_file *file_priv);
2841 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2842 struct drm_file *file_priv);
2843 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2844 struct drm_file *file_priv);
2845 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2846 struct drm_file *file_priv);
2847 int i915_gem_init_userptr(struct drm_device *dev);
2848 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2849 struct drm_file *file);
2850 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2851 struct drm_file *file_priv);
2852 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2853 struct drm_file *file_priv);
2854 void i915_gem_load_init(struct drm_device *dev);
2855 void i915_gem_load_cleanup(struct drm_device *dev);
2856 void *i915_gem_object_alloc(struct drm_device *dev);
2857 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2858 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2859 const struct drm_i915_gem_object_ops *ops);
2860 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2862 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2863 struct drm_device *dev, const void *data, size_t size);
2864 void i915_gem_free_object(struct drm_gem_object *obj);
2865 void i915_gem_vma_destroy(struct i915_vma *vma);
2867 /* Flags used by pin/bind&friends. */
2868 #define PIN_MAPPABLE (1<<0)
2869 #define PIN_NONBLOCK (1<<1)
2870 #define PIN_GLOBAL (1<<2)
2871 #define PIN_OFFSET_BIAS (1<<3)
2872 #define PIN_USER (1<<4)
2873 #define PIN_UPDATE (1<<5)
2874 #define PIN_ZONE_4G (1<<6)
2875 #define PIN_HIGH (1<<7)
2876 #define PIN_OFFSET_FIXED (1<<8)
2877 #define PIN_OFFSET_MASK (~4095)
2879 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2880 struct i915_address_space *vm,
2884 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2885 const struct i915_ggtt_view *view,
2889 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2891 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2892 int __must_check i915_vma_unbind(struct i915_vma *vma);
2894 * BEWARE: Do not use the function below unless you can _absolutely_
2895 * _guarantee_ VMA in question is _not in use_ anywhere.
2897 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2898 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2899 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2900 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2902 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2903 int *needs_clflush);
2905 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2907 static inline int __sg_page_count(struct scatterlist *sg)
2909 return sg->length >> PAGE_SHIFT;
2913 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
2915 static inline struct page *
2916 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2918 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2921 if (n < obj->get_page.last) {
2922 obj->get_page.sg = obj->pages->sgl;
2923 obj->get_page.last = 0;
2926 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2927 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2928 if (unlikely(sg_is_chain(obj->get_page.sg)))
2929 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2932 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2935 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2937 BUG_ON(obj->pages == NULL);
2938 obj->pages_pin_count++;
2940 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2942 BUG_ON(obj->pages_pin_count == 0);
2943 obj->pages_pin_count--;
2946 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2947 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2948 struct intel_engine_cs *to,
2949 struct drm_i915_gem_request **to_req);
2950 void i915_vma_move_to_active(struct i915_vma *vma,
2951 struct drm_i915_gem_request *req);
2952 int i915_gem_dumb_create(struct drm_file *file_priv,
2953 struct drm_device *dev,
2954 struct drm_mode_create_dumb *args);
2955 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2956 uint32_t handle, uint64_t *offset);
2958 * Returns true if seq1 is later than seq2.
2961 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2963 return (int32_t)(seq1 - seq2) >= 0;
2966 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
2967 bool lazy_coherency)
2969 u32 seqno = req->engine->get_seqno(req->engine, lazy_coherency);
2970 return i915_seqno_passed(seqno, req->previous_seqno);
2973 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2974 bool lazy_coherency)
2976 u32 seqno = req->engine->get_seqno(req->engine, lazy_coherency);
2977 return i915_seqno_passed(seqno, req->seqno);
2980 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2981 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2983 struct drm_i915_gem_request *
2984 i915_gem_find_active_request(struct intel_engine_cs *engine);
2986 bool i915_gem_retire_requests(struct drm_device *dev);
2987 void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
2988 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2989 bool interruptible);
2991 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2993 return unlikely(atomic_read(&error->reset_counter)
2994 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2997 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2999 return atomic_read(&error->reset_counter) & I915_WEDGED;
3002 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3004 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
3007 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3009 return dev_priv->gpu_error.stop_rings == 0 ||
3010 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3013 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3015 return dev_priv->gpu_error.stop_rings == 0 ||
3016 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3019 void i915_gem_reset(struct drm_device *dev);
3020 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3021 int __must_check i915_gem_init(struct drm_device *dev);
3022 int i915_gem_init_engines(struct drm_device *dev);
3023 int __must_check i915_gem_init_hw(struct drm_device *dev);
3024 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3025 void i915_gem_init_swizzling(struct drm_device *dev);
3026 void i915_gem_cleanup_engines(struct drm_device *dev);
3027 int __must_check i915_gpu_idle(struct drm_device *dev);
3028 int __must_check i915_gem_suspend(struct drm_device *dev);
3029 void __i915_add_request(struct drm_i915_gem_request *req,
3030 struct drm_i915_gem_object *batch_obj,
3032 #define i915_add_request(req) \
3033 __i915_add_request(req, NULL, true)
3034 #define i915_add_request_no_flush(req) \
3035 __i915_add_request(req, NULL, false)
3036 int __i915_wait_request(struct drm_i915_gem_request *req,
3037 unsigned reset_counter,
3040 struct intel_rps_client *rps);
3041 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3042 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3044 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3047 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3050 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3052 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3054 const struct i915_ggtt_view *view);
3055 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3056 const struct i915_ggtt_view *view);
3057 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3059 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3060 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3063 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3065 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3066 int tiling_mode, bool fenced);
3068 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3069 enum i915_cache_level cache_level);
3071 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3072 struct dma_buf *dma_buf);
3074 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3075 struct drm_gem_object *gem_obj, int flags);
3077 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3078 const struct i915_ggtt_view *view);
3079 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3080 struct i915_address_space *vm);
3082 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3084 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3087 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3088 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3089 const struct i915_ggtt_view *view);
3090 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3091 struct i915_address_space *vm);
3093 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3094 struct i915_address_space *vm);
3096 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3097 struct i915_address_space *vm);
3099 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3100 const struct i915_ggtt_view *view);
3103 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3104 struct i915_address_space *vm);
3106 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3107 const struct i915_ggtt_view *view);
3109 static inline struct i915_vma *
3110 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3112 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3114 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3116 /* Some GGTT VM helpers */
3117 #define i915_obj_to_ggtt(obj) \
3118 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3120 static inline struct i915_hw_ppgtt *
3121 i915_vm_to_ppgtt(struct i915_address_space *vm)
3123 WARN_ON(i915_is_ggtt(vm));
3124 return container_of(vm, struct i915_hw_ppgtt, base);
3128 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3130 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3133 static inline unsigned long
3134 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3136 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3139 static inline int __must_check
3140 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3144 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3145 alignment, flags | PIN_GLOBAL);
3149 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3151 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3154 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3155 const struct i915_ggtt_view *view);
3157 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3159 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3162 /* i915_gem_fence.c */
3163 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3164 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3166 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3167 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3169 void i915_gem_restore_fences(struct drm_device *dev);
3171 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3172 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3173 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3175 /* i915_gem_context.c */
3176 int __must_check i915_gem_context_init(struct drm_device *dev);
3177 void i915_gem_context_fini(struct drm_device *dev);
3178 void i915_gem_context_reset(struct drm_device *dev);
3179 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3180 int i915_gem_context_enable(struct drm_i915_gem_request *req);
3181 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3182 int i915_switch_context(struct drm_i915_gem_request *req);
3183 struct intel_context *
3184 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3185 void i915_gem_context_free(struct kref *ctx_ref);
3186 struct drm_i915_gem_object *
3187 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3188 static inline void i915_gem_context_reference(struct intel_context *ctx)
3190 kref_get(&ctx->ref);
3193 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3195 kref_put(&ctx->ref, i915_gem_context_free);
3198 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3200 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3203 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3204 struct drm_file *file);
3205 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3206 struct drm_file *file);
3207 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3208 struct drm_file *file_priv);
3209 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3210 struct drm_file *file_priv);
3212 /* i915_gem_evict.c */
3213 int __must_check i915_gem_evict_something(struct drm_device *dev,
3214 struct i915_address_space *vm,
3217 unsigned cache_level,
3218 unsigned long start,
3221 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3222 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3224 /* belongs in i915_gem_gtt.h */
3225 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3227 if (INTEL_INFO(dev)->gen < 6)
3228 intel_gtt_chipset_flush();
3231 /* i915_gem_stolen.c */
3232 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3233 struct drm_mm_node *node, u64 size,
3234 unsigned alignment);
3235 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3236 struct drm_mm_node *node, u64 size,
3237 unsigned alignment, u64 start,
3239 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3240 struct drm_mm_node *node);
3241 int i915_gem_init_stolen(struct drm_device *dev);
3242 void i915_gem_cleanup_stolen(struct drm_device *dev);
3243 struct drm_i915_gem_object *
3244 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3245 struct drm_i915_gem_object *
3246 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3251 /* i915_gem_shrinker.c */
3252 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3253 unsigned long target,
3255 #define I915_SHRINK_PURGEABLE 0x1
3256 #define I915_SHRINK_UNBOUND 0x2
3257 #define I915_SHRINK_BOUND 0x4
3258 #define I915_SHRINK_ACTIVE 0x8
3259 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3260 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3261 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3264 /* i915_gem_tiling.c */
3265 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3267 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3269 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3270 obj->tiling_mode != I915_TILING_NONE;
3273 /* i915_gem_debug.c */
3275 int i915_verify_lists(struct drm_device *dev);
3277 #define i915_verify_lists(dev) 0
3280 /* i915_debugfs.c */
3281 int i915_debugfs_init(struct drm_minor *minor);
3282 void i915_debugfs_cleanup(struct drm_minor *minor);
3283 #ifdef CONFIG_DEBUG_FS
3284 int i915_debugfs_connector_add(struct drm_connector *connector);
3285 void intel_display_crc_init(struct drm_device *dev);
3287 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3289 static inline void intel_display_crc_init(struct drm_device *dev) {}
3292 /* i915_gpu_error.c */
3294 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3295 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3296 const struct i915_error_state_file_priv *error);
3297 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3298 struct drm_i915_private *i915,
3299 size_t count, loff_t pos);
3300 static inline void i915_error_state_buf_release(
3301 struct drm_i915_error_state_buf *eb)
3305 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3306 const char *error_msg);
3307 void i915_error_state_get(struct drm_device *dev,
3308 struct i915_error_state_file_priv *error_priv);
3309 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3310 void i915_destroy_error_state(struct drm_device *dev);
3312 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3313 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3315 /* i915_cmd_parser.c */
3316 int i915_cmd_parser_get_version(void);
3317 int i915_cmd_parser_init_ring(struct intel_engine_cs *engine);
3318 void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine);
3319 bool i915_needs_cmd_parser(struct intel_engine_cs *engine);
3320 int i915_parse_cmds(struct intel_engine_cs *engine,
3321 struct drm_i915_gem_object *batch_obj,
3322 struct drm_i915_gem_object *shadow_batch_obj,
3323 u32 batch_start_offset,
3327 /* i915_suspend.c */
3328 extern int i915_save_state(struct drm_device *dev);
3329 extern int i915_restore_state(struct drm_device *dev);
3332 void i915_setup_sysfs(struct drm_device *dev_priv);
3333 void i915_teardown_sysfs(struct drm_device *dev_priv);
3336 extern int intel_setup_gmbus(struct drm_device *dev);
3337 extern void intel_teardown_gmbus(struct drm_device *dev);
3338 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3341 extern struct i2c_adapter *
3342 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3343 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3344 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3345 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3347 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3349 extern void intel_i2c_reset(struct drm_device *dev);
3352 int intel_bios_init(struct drm_i915_private *dev_priv);
3353 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3354 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3355 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3356 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3357 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3359 /* intel_opregion.c */
3361 extern int intel_opregion_setup(struct drm_device *dev);
3362 extern void intel_opregion_init(struct drm_device *dev);
3363 extern void intel_opregion_fini(struct drm_device *dev);
3364 extern void intel_opregion_asle_intr(struct drm_device *dev);
3365 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3367 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3370 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3371 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3372 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3373 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3375 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3380 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3388 extern void intel_register_dsm_handler(void);
3389 extern void intel_unregister_dsm_handler(void);
3391 static inline void intel_register_dsm_handler(void) { return; }
3392 static inline void intel_unregister_dsm_handler(void) { return; }
3393 #endif /* CONFIG_ACPI */
3396 extern void intel_modeset_init_hw(struct drm_device *dev);
3397 extern void intel_modeset_init(struct drm_device *dev);
3398 extern void intel_modeset_gem_init(struct drm_device *dev);
3399 extern void intel_modeset_cleanup(struct drm_device *dev);
3400 extern void intel_connector_unregister(struct intel_connector *);
3401 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3402 extern void intel_display_resume(struct drm_device *dev);
3403 extern void i915_redisable_vga(struct drm_device *dev);
3404 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3405 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3406 extern void intel_init_pch_refclk(struct drm_device *dev);
3407 extern void intel_set_rps(struct drm_device *dev, u8 val);
3408 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3410 extern void intel_detect_pch(struct drm_device *dev);
3411 extern int intel_enable_rc6(const struct drm_device *dev);
3413 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3414 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3415 struct drm_file *file);
3416 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3417 struct drm_file *file);
3420 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3421 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3422 struct intel_overlay_error_state *error);
3424 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3425 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3426 struct drm_device *dev,
3427 struct intel_display_error_state *error);
3429 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3430 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3432 /* intel_sideband.c */
3433 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3434 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3435 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3436 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3437 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3438 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3439 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3440 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3441 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3442 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3443 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3444 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3445 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3446 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3447 enum intel_sbi_destination destination);
3448 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3449 enum intel_sbi_destination destination);
3450 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3451 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3453 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3454 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3456 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3457 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3459 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3460 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3461 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3462 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3464 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3465 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3466 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3467 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3469 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3470 * will be implemented using 2 32-bit writes in an arbitrary order with
3471 * an arbitrary delay between them. This can cause the hardware to
3472 * act upon the intermediate value, possibly leading to corruption and
3473 * machine death. You have been warned.
3475 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3476 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3478 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3479 u32 upper, lower, old_upper, loop = 0; \
3480 upper = I915_READ(upper_reg); \
3482 old_upper = upper; \
3483 lower = I915_READ(lower_reg); \
3484 upper = I915_READ(upper_reg); \
3485 } while (upper != old_upper && loop++ < 2); \
3486 (u64)upper << 32 | lower; })
3488 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3489 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3491 #define __raw_read(x, s) \
3492 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3495 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3498 #define __raw_write(x, s) \
3499 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3500 i915_reg_t reg, uint##x##_t val) \
3502 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3517 /* These are untraced mmio-accessors that are only valid to be used inside
3518 * criticial sections inside IRQ handlers where forcewake is explicitly
3520 * Think twice, and think again, before using these.
3521 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3522 * intel_uncore_forcewake_irqunlock().
3524 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3525 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3526 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3528 /* "Broadcast RGB" property */
3529 #define INTEL_BROADCAST_RGB_AUTO 0
3530 #define INTEL_BROADCAST_RGB_FULL 1
3531 #define INTEL_BROADCAST_RGB_LIMITED 2
3533 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3535 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3536 return VLV_VGACNTRL;
3537 else if (INTEL_INFO(dev)->gen >= 5)
3538 return CPU_VGACNTRL;
3543 static inline void __user *to_user_ptr(u64 address)
3545 return (void __user *)(uintptr_t)address;
3548 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3550 unsigned long j = msecs_to_jiffies(m);
3552 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3555 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3557 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3560 static inline unsigned long
3561 timespec_to_jiffies_timeout(const struct timespec *value)
3563 unsigned long j = timespec_to_jiffies(value);
3565 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3569 * If you need to wait X milliseconds between events A and B, but event B
3570 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3571 * when event A happened, then just before event B you call this function and
3572 * pass the timestamp as the first argument, and X as the second argument.
3575 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3577 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3580 * Don't re-read the value of "jiffies" every time since it may change
3581 * behind our back and break the math.
3583 tmp_jiffies = jiffies;
3584 target_jiffies = timestamp_jiffies +
3585 msecs_to_jiffies_timeout(to_wait_ms);
3587 if (time_after(target_jiffies, tmp_jiffies)) {
3588 remaining_jiffies = target_jiffies - tmp_jiffies;
3589 while (remaining_jiffies)
3591 schedule_timeout_uninterruptible(remaining_jiffies);
3595 static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
3596 struct drm_i915_gem_request *req)
3598 if (engine->trace_irq_req == NULL && engine->irq_get(engine))
3599 i915_gem_request_assign(&engine->trace_irq_req, req);