1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
38 /* General customization:
41 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
43 #define DRIVER_NAME "i915"
44 #define DRIVER_DESC "Intel Graphics"
45 #define DRIVER_DATE "20080730"
57 #define I915_NUM_PIPE 2
59 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
64 * 1.2: Add Power Management
65 * 1.3: Add vblank support
66 * 1.4: Fix cmdbuffer path, add heap destroy
67 * 1.5: Add vblank pipe configuration
68 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
69 * - Support vertical blank on secondary display pipe
71 #define DRIVER_MAJOR 1
72 #define DRIVER_MINOR 6
73 #define DRIVER_PATCHLEVEL 0
75 #define WATCH_COHERENCY 0
80 #define WATCH_INACTIVE 0
81 #define WATCH_PWRITE 0
83 #define I915_GEM_PHYS_CURSOR_0 1
84 #define I915_GEM_PHYS_CURSOR_1 2
85 #define I915_GEM_PHYS_OVERLAY_REGS 3
86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
88 struct drm_i915_gem_phys_object {
90 struct page **page_list;
91 drm_dma_handle_t *handle;
92 struct drm_gem_object *cur_obj;
96 struct mem_block *next;
97 struct mem_block *prev;
100 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
103 struct opregion_header;
104 struct opregion_acpi;
105 struct opregion_swsci;
106 struct opregion_asle;
108 struct intel_opregion {
109 struct opregion_header *header;
110 struct opregion_acpi *acpi;
111 struct opregion_swsci *swsci;
112 struct opregion_asle *asle;
116 struct drm_i915_master_private {
117 drm_local_map_t *sarea;
118 struct _drm_i915_sarea *sarea_priv;
120 #define I915_FENCE_REG_NONE -1
122 struct drm_i915_fence_reg {
123 struct drm_gem_object *obj;
124 struct list_head lru_list;
127 struct sdvo_device_mapping {
135 struct drm_i915_error_state {
150 struct drm_i915_error_object {
154 } *ringbuffer, *batchbuffer[2];
155 struct drm_i915_error_buffer {
171 struct drm_i915_display_funcs {
172 void (*dpms)(struct drm_crtc *crtc, int mode);
173 bool (*fbc_enabled)(struct drm_device *dev);
174 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
175 void (*disable_fbc)(struct drm_device *dev);
176 int (*get_display_clock_speed)(struct drm_device *dev);
177 int (*get_fifo_size)(struct drm_device *dev, int plane);
178 void (*update_wm)(struct drm_device *dev, int planea_clock,
179 int planeb_clock, int sr_hdisplay, int pixel_size);
180 /* clock updates for mode set */
182 /* render clock increase/decrease */
183 /* display clock increase/decrease */
184 /* pll clock increase/decrease */
185 /* clock gating init */
188 struct intel_overlay;
190 struct intel_device_info {
207 u8 has_pipe_cxsr : 1;
209 u8 cursor_needs_physical : 1;
213 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
214 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
215 FBC_MODE_TOO_LARGE, /* mode too large for compression */
216 FBC_BAD_PLANE, /* fbc not supported on plane */
217 FBC_NOT_TILED, /* buffer not tiled */
221 PCH_IBX, /* Ibexpeak PCH */
222 PCH_CPT, /* Cougarpoint PCH */
227 typedef struct drm_i915_private {
228 struct drm_device *dev;
230 const struct intel_device_info *info;
236 struct pci_dev *bridge_dev;
237 struct intel_ring_buffer render_ring;
238 struct intel_ring_buffer bsd_ring;
240 drm_dma_handle_t *status_page_dmah;
242 dma_addr_t dma_status_page;
244 unsigned int seqno_gfx_addr;
245 drm_local_map_t hws_map;
246 struct drm_gem_object *seqno_obj;
247 struct drm_gem_object *pwrctx;
249 struct resource mch_res;
257 wait_queue_head_t irq_queue;
258 atomic_t irq_received;
259 /** Protects user_irq_refcount and irq_mask_reg */
260 spinlock_t user_irq_lock;
262 /** Cached value of IMR to avoid reads in updating the bitfield */
265 /** splitted irq regs for graphics and display engine on Ironlake,
266 irq_mask_reg is still used for display irq. */
268 u32 gt_irq_enable_reg;
269 u32 de_irq_enable_reg;
270 u32 pch_irq_mask_reg;
271 u32 pch_irq_enable_reg;
273 u32 hotplug_supported_mask;
274 struct work_struct hotplug_work;
276 int tex_lru_log_granularity;
277 int allow_batchbuffer;
278 struct mem_block *agp_heap;
279 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
282 /* For hangcheck timer */
283 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
284 struct timer_list hangcheck_timer;
290 unsigned long cfb_size;
291 unsigned long cfb_pitch;
297 struct intel_opregion opregion;
300 struct intel_overlay *overlay;
303 int backlight_duty_cycle; /* restore backlight to this value */
304 bool panel_wants_dither;
305 struct drm_display_mode *panel_fixed_mode;
306 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
307 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
309 /* Feature bits from the VBIOS */
310 unsigned int int_tv_support:1;
311 unsigned int lvds_dither:1;
312 unsigned int lvds_vbt:1;
313 unsigned int int_crt_support:1;
314 unsigned int lvds_use_ssc:1;
315 unsigned int edp_support:1;
319 struct notifier_block lid_notifier;
321 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */
322 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
323 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
324 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
326 unsigned int fsb_freq, mem_freq, is_ddr3;
328 spinlock_t error_lock;
329 struct drm_i915_error_state *first_error;
330 struct work_struct error_work;
331 struct workqueue_struct *wq;
333 /* Display functions */
334 struct drm_i915_display_funcs display;
336 /* PCH chipset type */
337 enum intel_pch pch_type;
362 u32 saveTRANS_HTOTAL_A;
363 u32 saveTRANS_HBLANK_A;
364 u32 saveTRANS_HSYNC_A;
365 u32 saveTRANS_VTOTAL_A;
366 u32 saveTRANS_VBLANK_A;
367 u32 saveTRANS_VSYNC_A;
375 u32 savePFIT_PGM_RATIOS;
376 u32 saveBLC_HIST_CTL;
378 u32 saveBLC_PWM_CTL2;
379 u32 saveBLC_CPU_PWM_CTL;
380 u32 saveBLC_CPU_PWM_CTL2;
393 u32 saveTRANS_HTOTAL_B;
394 u32 saveTRANS_HBLANK_B;
395 u32 saveTRANS_HSYNC_B;
396 u32 saveTRANS_VTOTAL_B;
397 u32 saveTRANS_VBLANK_B;
398 u32 saveTRANS_VSYNC_B;
412 u32 savePP_ON_DELAYS;
413 u32 savePP_OFF_DELAYS;
421 u32 savePFIT_CONTROL;
422 u32 save_palette_a[256];
423 u32 save_palette_b[256];
424 u32 saveDPFC_CB_BASE;
425 u32 saveFBC_CFB_BASE;
428 u32 saveFBC_CONTROL2;
438 u32 saveCACHE_MODE_0;
439 u32 saveMI_ARB_STATE;
450 uint64_t saveFENCE[16];
461 u32 savePIPEA_GMCH_DATA_M;
462 u32 savePIPEB_GMCH_DATA_M;
463 u32 savePIPEA_GMCH_DATA_N;
464 u32 savePIPEB_GMCH_DATA_N;
465 u32 savePIPEA_DP_LINK_M;
466 u32 savePIPEB_DP_LINK_M;
467 u32 savePIPEA_DP_LINK_N;
468 u32 savePIPEB_DP_LINK_N;
479 u32 savePCH_DREF_CONTROL;
480 u32 saveDISP_ARB_CTL;
481 u32 savePIPEA_DATA_M1;
482 u32 savePIPEA_DATA_N1;
483 u32 savePIPEA_LINK_M1;
484 u32 savePIPEA_LINK_N1;
485 u32 savePIPEB_DATA_M1;
486 u32 savePIPEB_DATA_N1;
487 u32 savePIPEB_LINK_M1;
488 u32 savePIPEB_LINK_N1;
489 u32 saveMCHBAR_RENDER_STANDBY;
492 struct drm_mm gtt_space;
494 struct io_mapping *gtt_mapping;
498 * Membership on list of all loaded devices, used to evict
499 * inactive buffers under memory pressure.
501 * Modifications should only be done whilst holding the
502 * shrink_list_lock spinlock.
504 struct list_head shrink_list;
506 spinlock_t active_list_lock;
509 * List of objects which are not in the ringbuffer but which
510 * still have a write_domain which needs to be flushed before
513 * last_rendering_seqno is 0 while an object is in this list.
515 * A reference is held on the buffer while on this list.
517 struct list_head flushing_list;
520 * List of objects currently pending a GPU write flush.
522 * All elements on this list will belong to either the
523 * active_list or flushing_list, last_rendering_seqno can
524 * be used to differentiate between the two elements.
526 struct list_head gpu_write_list;
529 * LRU list of objects which are not in the ringbuffer and
530 * are ready to unbind, but are still in the GTT.
532 * last_rendering_seqno is 0 while an object is in this list.
534 * A reference is not held on the buffer while on this list,
535 * as merely being GTT-bound shouldn't prevent its being
536 * freed, and we'll pull it off the list in the free path.
538 struct list_head inactive_list;
540 /** LRU list of objects with fence regs on them. */
541 struct list_head fence_list;
544 * We leave the user IRQ off as much as possible,
545 * but this means that requests will finish and never
546 * be retired once the system goes idle. Set a timer to
547 * fire periodically while the ring is running. When it
548 * fires, go retire requests.
550 struct delayed_work retire_work;
552 uint32_t next_gem_seqno;
555 * Waiting sequence number, if any
557 uint32_t waiting_gem_seqno;
560 * Last seq seen at irq time
562 uint32_t irq_gem_seqno;
565 * Flag if the X Server, and thus DRM, is not currently in
566 * control of the device.
568 * This is set between LeaveVT and EnterVT. It needs to be
569 * replaced with a semaphore. It also needs to be
570 * transitioned away from for kernel modesetting.
575 * Flag if the hardware appears to be wedged.
577 * This is set when attempts to idle the device timeout.
578 * It prevents command submission from occuring and makes
579 * every pending request fail
583 /** Bit 6 swizzling required for X tiling */
584 uint32_t bit_6_swizzle_x;
585 /** Bit 6 swizzling required for Y tiling */
586 uint32_t bit_6_swizzle_y;
588 /* storage for physical objects */
589 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
591 struct sdvo_device_mapping sdvo_mappings[2];
592 /* indicate whether the LVDS_BORDER should be enabled or not */
593 unsigned int lvds_border_bits;
595 struct drm_crtc *plane_to_crtc_mapping[2];
596 struct drm_crtc *pipe_to_crtc_mapping[2];
597 wait_queue_head_t pending_flip_queue;
599 /* Reclocking support */
600 bool render_reclock_avail;
601 bool lvds_downclock_avail;
602 /* indicate whether the LVDS EDID is OK */
604 /* indicates the reduced downclock for LVDS*/
606 struct work_struct idle_work;
607 struct timer_list idle_timer;
611 struct child_device_config *child_dev;
612 struct drm_connector *int_lvds_connector;
614 bool mchbar_need_disable;
623 unsigned long last_time1;
625 struct timespec last_time2;
626 unsigned long gfx_power;
630 spinlock_t *mchdev_lock;
632 enum no_fbc_reason no_fbc_reason;
634 struct drm_mm_node *compressed_fb;
635 struct drm_mm_node *compressed_llb;
637 /* list of fbdev register on this device */
638 struct intel_fbdev *fbdev;
639 } drm_i915_private_t;
641 /** driver private structure attached to each drm_gem_object */
642 struct drm_i915_gem_object {
643 struct drm_gem_object base;
645 /** Current space allocated to this object in the GTT, if any. */
646 struct drm_mm_node *gtt_space;
648 /** This object's place on the active/flushing/inactive lists */
649 struct list_head list;
650 /** This object's place on GPU write list */
651 struct list_head gpu_write_list;
654 * This is set if the object is on the active or flushing lists
655 * (has pending rendering), and is not set if it's on inactive (ready
658 unsigned int active : 1;
661 * This is set if the object has been written to since last bound
664 unsigned int dirty : 1;
667 * Fence register bits (if any) for this object. Will be set
668 * as needed when mapped into the GTT.
669 * Protected by dev->struct_mutex.
671 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
676 * Used for checking the object doesn't appear more than once
677 * in an execbuffer object list.
679 unsigned int in_execbuffer : 1;
682 * Advice: are the backing pages purgeable?
684 unsigned int madv : 2;
687 * Refcount for the pages array. With the current locking scheme, there
688 * are at most two concurrent users: Binding a bo to the gtt and
689 * pwrite/pread using physical addresses. So two bits for a maximum
690 * of two users are enough.
692 unsigned int pages_refcount : 2;
693 #define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3
696 * Current tiling mode for the object.
698 unsigned int tiling_mode : 2;
700 /** How many users have pinned this object in GTT space. The following
701 * users can each hold at most one reference: pwrite/pread, pin_ioctl
702 * (via user_pin_count), execbuffer (objects are not allowed multiple
703 * times for the same batchbuffer), and the framebuffer code. When
704 * switching/pageflipping, the framebuffer code has at most two buffers
707 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
708 * bits with absolutely no headroom. So use 4 bits. */
710 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
712 /** AGP memory structure for our GTT binding. */
713 DRM_AGP_MEM *agp_mem;
718 * Current offset of the object in GTT space.
720 * This is the same as gtt_space->start
724 /* Which ring is refering to is this object */
725 struct intel_ring_buffer *ring;
728 * Fake offset for use by mmap(2)
730 uint64_t mmap_offset;
732 /** Breadcrumb of last rendering to the buffer. */
733 uint32_t last_rendering_seqno;
735 /** Current tiling stride for the object, if it's tiled. */
738 /** Record of address bit 17 of each page at last unbind. */
741 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
745 * If present, while GEM_DOMAIN_CPU is in the read domain this array
746 * flags which individual pages are valid.
748 uint8_t *page_cpu_valid;
750 /** User space pin count and filp owning the pin */
751 uint32_t user_pin_count;
752 struct drm_file *pin_filp;
754 /** for phy allocated objects */
755 struct drm_i915_gem_phys_object *phys_obj;
758 * Number of crtcs where this object is currently the fb, but
759 * will be page flipped away on the next vblank. When it
760 * reaches 0, dev_priv->pending_flip_queue will be woken up.
762 atomic_t pending_flip;
765 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
768 * Request queue structure.
770 * The request queue allows us to note sequence numbers that have been emitted
771 * and may be associated with active buffers to be retired.
773 * By keeping this list, we can avoid having to do questionable
774 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
775 * an emission time with seqnos for tracking how far ahead of the GPU we are.
777 struct drm_i915_gem_request {
778 /** On Which ring this request was generated */
779 struct intel_ring_buffer *ring;
781 /** GEM sequence number associated with this request. */
784 /** Time at which this request was emitted, in jiffies. */
785 unsigned long emitted_jiffies;
787 /** global list entry for this request */
788 struct list_head list;
790 /** file_priv list entry for this request */
791 struct list_head client_list;
794 struct drm_i915_file_private {
796 struct list_head request_list;
800 enum intel_chip_family {
807 extern struct drm_ioctl_desc i915_ioctls[];
808 extern int i915_max_ioctl;
809 extern unsigned int i915_fbpercrtc;
810 extern unsigned int i915_powersave;
811 extern unsigned int i915_lvds_downclock;
813 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
814 extern int i915_resume(struct drm_device *dev);
815 extern void i915_save_display(struct drm_device *dev);
816 extern void i915_restore_display(struct drm_device *dev);
817 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
818 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
821 extern void i915_kernel_lost_context(struct drm_device * dev);
822 extern int i915_driver_load(struct drm_device *, unsigned long flags);
823 extern int i915_driver_unload(struct drm_device *);
824 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
825 extern void i915_driver_lastclose(struct drm_device * dev);
826 extern void i915_driver_preclose(struct drm_device *dev,
827 struct drm_file *file_priv);
828 extern void i915_driver_postclose(struct drm_device *dev,
829 struct drm_file *file_priv);
830 extern int i915_driver_device_is_agp(struct drm_device * dev);
831 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
833 extern int i915_emit_box(struct drm_device *dev,
834 struct drm_clip_rect *boxes,
835 int i, int DR1, int DR4);
836 extern int i965_reset(struct drm_device *dev, u8 flags);
837 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
838 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
839 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
840 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
844 void i915_hangcheck_elapsed(unsigned long data);
845 void i915_destroy_error_state(struct drm_device *dev);
846 extern int i915_irq_emit(struct drm_device *dev, void *data,
847 struct drm_file *file_priv);
848 extern int i915_irq_wait(struct drm_device *dev, void *data,
849 struct drm_file *file_priv);
850 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
851 extern void i915_enable_interrupt (struct drm_device *dev);
853 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
854 extern void i915_driver_irq_preinstall(struct drm_device * dev);
855 extern int i915_driver_irq_postinstall(struct drm_device *dev);
856 extern void i915_driver_irq_uninstall(struct drm_device * dev);
857 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
858 struct drm_file *file_priv);
859 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
860 struct drm_file *file_priv);
861 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
862 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
863 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
864 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
865 extern int i915_vblank_swap(struct drm_device *dev, void *data,
866 struct drm_file *file_priv);
867 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
868 extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
869 extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
871 extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
875 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
878 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
880 void intel_enable_asle (struct drm_device *dev);
884 extern int i915_mem_alloc(struct drm_device *dev, void *data,
885 struct drm_file *file_priv);
886 extern int i915_mem_free(struct drm_device *dev, void *data,
887 struct drm_file *file_priv);
888 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
889 struct drm_file *file_priv);
890 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
891 struct drm_file *file_priv);
892 extern void i915_mem_takedown(struct mem_block **heap);
893 extern void i915_mem_release(struct drm_device * dev,
894 struct drm_file *file_priv, struct mem_block *heap);
896 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
897 struct drm_file *file_priv);
898 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
899 struct drm_file *file_priv);
900 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
901 struct drm_file *file_priv);
902 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
903 struct drm_file *file_priv);
904 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
905 struct drm_file *file_priv);
906 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
907 struct drm_file *file_priv);
908 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
909 struct drm_file *file_priv);
910 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
911 struct drm_file *file_priv);
912 int i915_gem_execbuffer(struct drm_device *dev, void *data,
913 struct drm_file *file_priv);
914 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
915 struct drm_file *file_priv);
916 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
917 struct drm_file *file_priv);
918 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
919 struct drm_file *file_priv);
920 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
921 struct drm_file *file_priv);
922 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
923 struct drm_file *file_priv);
924 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
925 struct drm_file *file_priv);
926 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
927 struct drm_file *file_priv);
928 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
929 struct drm_file *file_priv);
930 int i915_gem_set_tiling(struct drm_device *dev, void *data,
931 struct drm_file *file_priv);
932 int i915_gem_get_tiling(struct drm_device *dev, void *data,
933 struct drm_file *file_priv);
934 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
935 struct drm_file *file_priv);
936 void i915_gem_load(struct drm_device *dev);
937 int i915_gem_init_object(struct drm_gem_object *obj);
938 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
940 void i915_gem_free_object(struct drm_gem_object *obj);
941 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
942 void i915_gem_object_unpin(struct drm_gem_object *obj);
943 int i915_gem_object_unbind(struct drm_gem_object *obj);
944 void i915_gem_release_mmap(struct drm_gem_object *obj);
945 void i915_gem_lastclose(struct drm_device *dev);
946 uint32_t i915_get_gem_seqno(struct drm_device *dev,
947 struct intel_ring_buffer *ring);
948 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
949 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
950 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
951 void i915_gem_retire_requests(struct drm_device *dev,
952 struct intel_ring_buffer *ring);
953 void i915_gem_retire_work_handler(struct work_struct *work);
954 void i915_gem_clflush_object(struct drm_gem_object *obj);
955 int i915_gem_object_set_domain(struct drm_gem_object *obj,
956 uint32_t read_domains,
957 uint32_t write_domain);
958 int i915_gem_init_ringbuffer(struct drm_device *dev);
959 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
960 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
962 int i915_gem_idle(struct drm_device *dev);
963 uint32_t i915_add_request(struct drm_device *dev,
964 struct drm_file *file_priv,
965 uint32_t flush_domains,
966 struct intel_ring_buffer *ring);
967 int i915_do_wait_request(struct drm_device *dev,
968 uint32_t seqno, int interruptible,
969 struct intel_ring_buffer *ring);
970 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
971 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
973 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
974 int i915_gem_attach_phys_object(struct drm_device *dev,
975 struct drm_gem_object *obj, int id);
976 void i915_gem_detach_phys_object(struct drm_device *dev,
977 struct drm_gem_object *obj);
978 void i915_gem_free_all_phys_object(struct drm_device *dev);
979 int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
980 void i915_gem_object_put_pages(struct drm_gem_object *obj);
981 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
982 void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
984 void i915_gem_shrinker_init(void);
985 void i915_gem_shrinker_exit(void);
987 /* i915_gem_tiling.c */
988 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
989 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
990 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
991 bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
993 bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
996 /* i915_gem_debug.c */
997 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
998 const char *where, uint32_t mark);
1000 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
1002 #define i915_verify_inactive(dev, file, line)
1004 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
1005 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
1006 const char *where, uint32_t mark);
1007 void i915_dump_lru(struct drm_device *dev, const char *where);
1009 /* i915_debugfs.c */
1010 int i915_debugfs_init(struct drm_minor *minor);
1011 void i915_debugfs_cleanup(struct drm_minor *minor);
1013 /* i915_suspend.c */
1014 extern int i915_save_state(struct drm_device *dev);
1015 extern int i915_restore_state(struct drm_device *dev);
1017 /* i915_suspend.c */
1018 extern int i915_save_state(struct drm_device *dev);
1019 extern int i915_restore_state(struct drm_device *dev);
1022 /* i915_opregion.c */
1023 extern int intel_opregion_init(struct drm_device *dev, int resume);
1024 extern void intel_opregion_free(struct drm_device *dev, int suspend);
1025 extern void opregion_asle_intr(struct drm_device *dev);
1026 extern void ironlake_opregion_gse_intr(struct drm_device *dev);
1027 extern void opregion_enable_asle(struct drm_device *dev);
1029 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
1030 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
1031 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
1032 static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; }
1033 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
1037 extern void intel_modeset_init(struct drm_device *dev);
1038 extern void intel_modeset_cleanup(struct drm_device *dev);
1039 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1040 extern void i8xx_disable_fbc(struct drm_device *dev);
1041 extern void g4x_disable_fbc(struct drm_device *dev);
1042 extern void intel_disable_fbc(struct drm_device *dev);
1043 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1044 extern bool intel_fbc_enabled(struct drm_device *dev);
1045 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1046 extern void intel_detect_pch (struct drm_device *dev);
1047 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1050 * Lock test for when it's just for synchronization of ring access.
1052 * In that case, we don't need to do it when GEM is initialized as nobody else
1053 * has access to the ring.
1055 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1056 if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
1058 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1061 #define I915_READ(reg) readl(dev_priv->regs + (reg))
1062 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
1063 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1064 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1065 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1066 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1067 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1068 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1069 #define POSTING_READ(reg) (void)I915_READ(reg)
1070 #define POSTING_READ16(reg) (void)I915_READ16(reg)
1072 #define I915_VERBOSE 0
1074 #define BEGIN_LP_RING(n) do { \
1075 drm_i915_private_t *dev_priv = dev->dev_private; \
1077 DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \
1078 intel_ring_begin(dev, &dev_priv->render_ring, 4*(n)); \
1082 #define OUT_RING(x) do { \
1083 drm_i915_private_t *dev_priv = dev->dev_private; \
1085 DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \
1086 intel_ring_emit(dev, &dev_priv->render_ring, x); \
1089 #define ADVANCE_LP_RING() do { \
1090 drm_i915_private_t *dev_priv = dev->dev_private; \
1092 DRM_DEBUG("ADVANCE_LP_RING %x\n", \
1093 dev_priv->render_ring.tail); \
1094 intel_ring_advance(dev, &dev_priv->render_ring); \
1098 * Reads a dword out of the status page, which is written to from the command
1099 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1100 * MI_STORE_DATA_IMM.
1102 * The following dwords have a reserved meaning:
1103 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1104 * 0x04: ring 0 head pointer
1105 * 0x05: ring 1 head pointer (915-class)
1106 * 0x06: ring 2 head pointer (915-class)
1107 * 0x10-0x1b: Context status DWords (GM45)
1108 * 0x1f: Last written status offset. (GM45)
1110 * The area from dword 0x20 to 0x3ff is available for driver usage.
1112 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1113 (dev_priv->render_ring.status_page.page_addr))[reg])
1114 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1115 #define I915_GEM_HWS_INDEX 0x20
1116 #define I915_BREADCRUMB_INDEX 0x21
1118 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1120 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1121 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1122 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1123 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1124 #define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
1125 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1126 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1127 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1128 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1129 #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
1130 #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
1131 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1132 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1133 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1134 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1135 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1136 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1137 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1138 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1139 #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1140 #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1141 #define IS_GEN6(dev) (INTEL_INFO(dev)->is_gen6)
1142 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1144 #define IS_GEN3(dev) (IS_I915G(dev) || \
1150 #define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \
1151 (dev)->pci_device == 0x2982 || \
1152 (dev)->pci_device == 0x2992 || \
1153 (dev)->pci_device == 0x29A2 || \
1154 (dev)->pci_device == 0x2A02 || \
1155 (dev)->pci_device == 0x2A12 || \
1156 (dev)->pci_device == 0x2E02 || \
1157 (dev)->pci_device == 0x2E12 || \
1158 (dev)->pci_device == 0x2E22 || \
1159 (dev)->pci_device == 0x2E32 || \
1160 (dev)->pci_device == 0x2A42 || \
1161 (dev)->pci_device == 0x2E42)
1163 #define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev))
1164 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1166 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1167 * rows, which changed the alignment requirements and fence programming.
1169 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1171 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1172 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1173 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1174 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1175 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1176 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \
1178 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1179 /* dsparb controlled by hw only */
1180 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1182 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1183 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1184 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1185 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1187 #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
1189 #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
1191 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1192 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1194 #define PRIMARY_RINGBUFFER_SIZE (128*1024)