1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
53 #include "i915_params.h"
56 #include "intel_bios.h"
57 #include "intel_dpll_mgr.h"
59 #include "intel_lrc.h"
60 #include "intel_ringbuffer.h"
63 #include "i915_gem_fence_reg.h"
64 #include "i915_gem_object.h"
65 #include "i915_gem_gtt.h"
66 #include "i915_gem_render_state.h"
67 #include "i915_gem_request.h"
68 #include "i915_gem_timeline.h"
72 #include "intel_gvt.h"
74 /* General customization:
77 #define DRIVER_NAME "i915"
78 #define DRIVER_DESC "Intel Graphics"
79 #define DRIVER_DATE "20161205"
80 #define DRIVER_TIMESTAMP 1480926326
83 /* Many gcc seem to no see through this and fall over :( */
85 #define WARN_ON(x) ({ \
86 bool __i915_warn_cond = (x); \
87 if (__builtin_constant_p(__i915_warn_cond)) \
88 BUILD_BUG_ON(__i915_warn_cond); \
89 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
91 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
95 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
97 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
98 (long) (x), __func__);
100 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
101 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
102 * which may not necessarily be a user visible problem. This will either
103 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
104 * enable distros and users to tailor their preferred amount of i915 abrt
107 #define I915_STATE_WARN(condition, format...) ({ \
108 int __ret_warn_on = !!(condition); \
109 if (unlikely(__ret_warn_on)) \
110 if (!WARN(i915.verbose_state_checks, format)) \
112 unlikely(__ret_warn_on); \
115 #define I915_STATE_WARN_ON(x) \
116 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
118 bool __i915_inject_load_failure(const char *func, int line);
119 #define i915_inject_load_failure() \
120 __i915_inject_load_failure(__func__, __LINE__)
122 static inline const char *yesno(bool v)
124 return v ? "yes" : "no";
127 static inline const char *onoff(bool v)
129 return v ? "on" : "off";
132 static inline const char *enableddisabled(bool v)
134 return v ? "enabled" : "disabled";
143 I915_MAX_PIPES = _PIPE_EDP
145 #define pipe_name(p) ((p) + 'A')
157 static inline const char *transcoder_name(enum transcoder transcoder)
159 switch (transcoder) {
168 case TRANSCODER_DSI_A:
170 case TRANSCODER_DSI_C:
177 static inline bool transcoder_is_dsi(enum transcoder transcoder)
179 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
183 * Global legacy plane identifier. Valid only for primary/sprite
184 * planes on pre-g4x, and only for primary planes on g4x+.
191 #define plane_name(p) ((p) + 'A')
193 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
196 * Per-pipe plane identifier.
197 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
198 * number of planes per CRTC. Not all platforms really have this many planes,
199 * which means some arrays of size I915_MAX_PLANES may have unused entries
200 * between the topmost sprite plane and the cursor plane.
202 * This is expected to be passed to various register macros
203 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
213 #define for_each_plane_id_on_crtc(__crtc, __p) \
214 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
215 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
226 #define port_name(p) ((p) + 'A')
228 #define I915_NUM_PHYS_VLV 2
241 enum intel_display_power_domain {
245 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
246 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
247 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
248 POWER_DOMAIN_TRANSCODER_A,
249 POWER_DOMAIN_TRANSCODER_B,
250 POWER_DOMAIN_TRANSCODER_C,
251 POWER_DOMAIN_TRANSCODER_EDP,
252 POWER_DOMAIN_TRANSCODER_DSI_A,
253 POWER_DOMAIN_TRANSCODER_DSI_C,
254 POWER_DOMAIN_PORT_DDI_A_LANES,
255 POWER_DOMAIN_PORT_DDI_B_LANES,
256 POWER_DOMAIN_PORT_DDI_C_LANES,
257 POWER_DOMAIN_PORT_DDI_D_LANES,
258 POWER_DOMAIN_PORT_DDI_E_LANES,
259 POWER_DOMAIN_PORT_DSI,
260 POWER_DOMAIN_PORT_CRT,
261 POWER_DOMAIN_PORT_OTHER,
270 POWER_DOMAIN_MODESET,
276 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
277 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
278 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
279 #define POWER_DOMAIN_TRANSCODER(tran) \
280 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
281 (tran) + POWER_DOMAIN_TRANSCODER_A)
285 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
297 #define for_each_hpd_pin(__pin) \
298 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
300 struct i915_hotplug {
301 struct work_struct hotplug_work;
304 unsigned long last_jiffies;
309 HPD_MARK_DISABLED = 2
311 } stats[HPD_NUM_PINS];
313 struct delayed_work reenable_work;
315 struct intel_digital_port *irq_port[I915_MAX_PORTS];
318 struct work_struct dig_port_work;
320 struct work_struct poll_init_work;
324 * if we get a HPD irq from DP and a HPD irq from non-DP
325 * the non-DP HPD could block the workqueue on a mode config
326 * mutex getting, that userspace may have taken. However
327 * userspace is waiting on the DP workqueue to run which is
328 * blocked behind the non-DP one.
330 struct workqueue_struct *dp_wq;
333 #define I915_GEM_GPU_DOMAINS \
334 (I915_GEM_DOMAIN_RENDER | \
335 I915_GEM_DOMAIN_SAMPLER | \
336 I915_GEM_DOMAIN_COMMAND | \
337 I915_GEM_DOMAIN_INSTRUCTION | \
338 I915_GEM_DOMAIN_VERTEX)
340 #define for_each_pipe(__dev_priv, __p) \
341 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
342 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
343 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
344 for_each_if ((__mask) & (1 << (__p)))
345 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
347 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
349 #define for_each_sprite(__dev_priv, __p, __s) \
351 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
354 #define for_each_port_masked(__port, __ports_mask) \
355 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
356 for_each_if ((__ports_mask) & (1 << (__port)))
358 #define for_each_crtc(dev, crtc) \
359 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
361 #define for_each_intel_plane(dev, intel_plane) \
362 list_for_each_entry(intel_plane, \
363 &(dev)->mode_config.plane_list, \
366 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
367 list_for_each_entry(intel_plane, \
368 &(dev)->mode_config.plane_list, \
370 for_each_if ((plane_mask) & \
371 (1 << drm_plane_index(&intel_plane->base)))
373 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
374 list_for_each_entry(intel_plane, \
375 &(dev)->mode_config.plane_list, \
377 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
379 #define for_each_intel_crtc(dev, intel_crtc) \
380 list_for_each_entry(intel_crtc, \
381 &(dev)->mode_config.crtc_list, \
384 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
385 list_for_each_entry(intel_crtc, \
386 &(dev)->mode_config.crtc_list, \
388 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
390 #define for_each_intel_encoder(dev, intel_encoder) \
391 list_for_each_entry(intel_encoder, \
392 &(dev)->mode_config.encoder_list, \
395 #define for_each_intel_connector(dev, intel_connector) \
396 list_for_each_entry(intel_connector, \
397 &(dev)->mode_config.connector_list, \
400 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
401 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
402 for_each_if ((intel_encoder)->base.crtc == (__crtc))
404 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
405 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
406 for_each_if ((intel_connector)->base.encoder == (__encoder))
408 #define for_each_power_domain(domain, mask) \
409 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
410 for_each_if ((1 << (domain)) & (mask))
412 struct drm_i915_private;
413 struct i915_mm_struct;
414 struct i915_mmu_object;
416 struct drm_i915_file_private {
417 struct drm_i915_private *dev_priv;
418 struct drm_file *file;
422 struct list_head request_list;
423 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
424 * chosen to prevent the CPU getting more than a frame ahead of the GPU
425 * (when using lax throttling for the frontbuffer). We also use it to
426 * offer free GPU waitboosts for severely congested workloads.
428 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
430 struct idr context_idr;
432 struct intel_rps_client {
433 struct list_head link;
437 unsigned int bsd_engine;
439 /* Client can have a maximum of 3 contexts banned before
440 * it is denied of creating new contexts. As one context
441 * ban needs 4 consecutive hangs, and more if there is
442 * progress in between, this is a last resort stop gap measure
443 * to limit the badly behaving clients access to gpu.
445 #define I915_MAX_CLIENT_CONTEXT_BANS 3
449 /* Used by dp and fdi links */
450 struct intel_link_m_n {
458 void intel_link_compute_m_n(int bpp, int nlanes,
459 int pixel_clock, int link_clock,
460 struct intel_link_m_n *m_n);
462 /* Interface history:
465 * 1.2: Add Power Management
466 * 1.3: Add vblank support
467 * 1.4: Fix cmdbuffer path, add heap destroy
468 * 1.5: Add vblank pipe configuration
469 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
470 * - Support vertical blank on secondary display pipe
472 #define DRIVER_MAJOR 1
473 #define DRIVER_MINOR 6
474 #define DRIVER_PATCHLEVEL 0
476 struct opregion_header;
477 struct opregion_acpi;
478 struct opregion_swsci;
479 struct opregion_asle;
481 struct intel_opregion {
482 struct opregion_header *header;
483 struct opregion_acpi *acpi;
484 struct opregion_swsci *swsci;
485 u32 swsci_gbda_sub_functions;
486 u32 swsci_sbcb_sub_functions;
487 struct opregion_asle *asle;
492 struct work_struct asle_work;
494 #define OPREGION_SIZE (8*1024)
496 struct intel_overlay;
497 struct intel_overlay_error_state;
499 struct sdvo_device_mapping {
508 struct intel_connector;
509 struct intel_encoder;
510 struct intel_atomic_state;
511 struct intel_crtc_state;
512 struct intel_initial_plane_config;
517 struct drm_i915_display_funcs {
518 int (*get_display_clock_speed)(struct drm_i915_private *dev_priv);
519 int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
520 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
521 int (*compute_intermediate_wm)(struct drm_device *dev,
522 struct intel_crtc *intel_crtc,
523 struct intel_crtc_state *newstate);
524 void (*initial_watermarks)(struct intel_atomic_state *state,
525 struct intel_crtc_state *cstate);
526 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
527 struct intel_crtc_state *cstate);
528 void (*optimize_watermarks)(struct intel_atomic_state *state,
529 struct intel_crtc_state *cstate);
530 int (*compute_global_watermarks)(struct drm_atomic_state *state);
531 void (*update_wm)(struct intel_crtc *crtc);
532 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
533 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
534 /* Returns the active state of the crtc, and if the crtc is active,
535 * fills out the pipe-config with the hw state. */
536 bool (*get_pipe_config)(struct intel_crtc *,
537 struct intel_crtc_state *);
538 void (*get_initial_plane_config)(struct intel_crtc *,
539 struct intel_initial_plane_config *);
540 int (*crtc_compute_clock)(struct intel_crtc *crtc,
541 struct intel_crtc_state *crtc_state);
542 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
543 struct drm_atomic_state *old_state);
544 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
545 struct drm_atomic_state *old_state);
546 void (*update_crtcs)(struct drm_atomic_state *state,
547 unsigned int *crtc_vblank_mask);
548 void (*audio_codec_enable)(struct drm_connector *connector,
549 struct intel_encoder *encoder,
550 const struct drm_display_mode *adjusted_mode);
551 void (*audio_codec_disable)(struct intel_encoder *encoder);
552 void (*fdi_link_train)(struct drm_crtc *crtc);
553 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
554 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
555 struct drm_framebuffer *fb,
556 struct drm_i915_gem_object *obj,
557 struct drm_i915_gem_request *req,
559 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
560 /* clock updates for mode set */
562 /* render clock increase/decrease */
563 /* display clock increase/decrease */
564 /* pll clock increase/decrease */
566 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
567 void (*load_luts)(struct drm_crtc_state *crtc_state);
570 enum forcewake_domain_id {
571 FW_DOMAIN_ID_RENDER = 0,
572 FW_DOMAIN_ID_BLITTER,
578 enum forcewake_domains {
579 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
580 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
581 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
582 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
587 #define FW_REG_READ (1)
588 #define FW_REG_WRITE (2)
590 enum decoupled_power_domain {
591 GEN9_DECOUPLED_PD_BLITTER = 0,
592 GEN9_DECOUPLED_PD_RENDER,
593 GEN9_DECOUPLED_PD_MEDIA,
594 GEN9_DECOUPLED_PD_ALL
598 GEN9_DECOUPLED_OP_WRITE = 0,
599 GEN9_DECOUPLED_OP_READ
602 enum forcewake_domains
603 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
604 i915_reg_t reg, unsigned int op);
606 struct intel_uncore_funcs {
607 void (*force_wake_get)(struct drm_i915_private *dev_priv,
608 enum forcewake_domains domains);
609 void (*force_wake_put)(struct drm_i915_private *dev_priv,
610 enum forcewake_domains domains);
612 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
613 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
614 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
615 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
617 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
618 uint8_t val, bool trace);
619 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
620 uint16_t val, bool trace);
621 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
622 uint32_t val, bool trace);
625 struct intel_forcewake_range {
629 enum forcewake_domains domains;
632 struct intel_uncore {
633 spinlock_t lock; /** lock is also taken in irq contexts. */
635 const struct intel_forcewake_range *fw_domains_table;
636 unsigned int fw_domains_table_entries;
638 struct intel_uncore_funcs funcs;
642 enum forcewake_domains fw_domains;
643 enum forcewake_domains fw_domains_active;
645 struct intel_uncore_forcewake_domain {
646 struct drm_i915_private *i915;
647 enum forcewake_domain_id id;
648 enum forcewake_domains mask;
650 struct hrtimer timer;
657 } fw_domain[FW_DOMAIN_ID_COUNT];
659 int unclaimed_mmio_check;
662 /* Iterate over initialised fw domains */
663 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
664 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
665 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
667 for_each_if ((mask__) & (domain__)->mask)
669 #define for_each_fw_domain(domain__, dev_priv__) \
670 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
672 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
673 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
674 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
677 struct work_struct work;
679 uint32_t *dmc_payload;
680 uint32_t dmc_fw_size;
683 i915_reg_t mmioaddr[8];
684 uint32_t mmiodata[8];
686 uint32_t allowed_dc_mask;
689 #define DEV_INFO_FOR_EACH_FLAG(func) \
690 /* Keep is_* in chronological order */ \
698 func(is_broadwater); \
699 func(is_crestline); \
700 func(is_ivybridge); \
701 func(is_valleyview); \
702 func(is_cherryview); \
704 func(is_broadwell); \
707 func(is_geminilake); \
710 func(is_alpha_support); \
711 /* Keep has_* in alphabetical order */ \
712 func(has_64bit_reloc); \
717 func(has_fpga_dbg); \
718 func(has_gmbus_irq); \
719 func(has_gmch_display); \
722 func(has_hw_contexts); \
725 func(has_logical_ring_contexts); \
727 func(has_pipe_cxsr); \
728 func(has_pooled_eu); \
732 func(has_resource_streamer); \
733 func(has_runtime_pm); \
735 func(cursor_needs_physical); \
736 func(hws_needs_physical); \
737 func(overlay_needs_physical); \
739 func(has_decoupled_mmio)
741 struct sseu_dev_info {
747 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
750 u8 has_subslice_pg:1;
754 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
756 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
759 struct intel_device_info {
760 u32 display_mmio_offset;
763 u8 num_sprites[I915_MAX_PIPES];
766 u8 ring_mask; /* Rings supported by the HW */
768 #define DEFINE_FLAG(name) u8 name:1
769 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
771 u16 ddb_size; /* in blocks */
772 /* Register offsets for the various display pipes and transcoders */
773 int pipe_offsets[I915_MAX_TRANSCODERS];
774 int trans_offsets[I915_MAX_TRANSCODERS];
775 int palette_offsets[I915_MAX_PIPES];
776 int cursor_offsets[I915_MAX_PIPES];
778 /* Slice/subslice/EU info */
779 struct sseu_dev_info sseu;
782 u16 degamma_lut_size;
787 struct intel_display_error_state;
789 struct drm_i915_error_state {
792 struct timeval boottime;
793 struct timeval uptime;
795 struct drm_i915_private *i915;
802 struct intel_device_info device_info;
804 /* Generic register state */
812 u32 error; /* gen6+ */
813 u32 err_int; /* gen7 */
814 u32 fault_data0; /* gen8, gen9 */
815 u32 fault_data1; /* gen8, gen9 */
822 u64 fence[I915_MAX_NUM_FENCES];
823 struct intel_overlay_error_state *overlay;
824 struct intel_display_error_state *display;
825 struct drm_i915_error_object *semaphore;
826 struct drm_i915_error_object *guc_log;
828 struct drm_i915_error_engine {
830 /* Software tracked state */
833 unsigned long hangcheck_timestamp;
834 bool hangcheck_stalled;
835 enum intel_engine_hangcheck_action hangcheck_action;
836 struct i915_address_space *vm;
839 /* position of active request inside the ring */
840 u32 rq_head, rq_post, rq_tail;
842 /* our own tracking of ring head and tail */
865 u32 rc_psmi; /* sleep state */
866 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
867 struct intel_instdone instdone;
869 struct drm_i915_error_object {
875 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
877 struct drm_i915_error_object *wa_ctx;
879 struct drm_i915_error_request {
887 } *requests, execlist[2];
889 struct drm_i915_error_waiter {
890 char comm[TASK_COMM_LEN];
904 char comm[TASK_COMM_LEN];
906 } engine[I915_NUM_ENGINES];
908 struct drm_i915_error_buffer {
911 u32 rseqno[I915_NUM_ENGINES], wseqno;
915 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
922 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
923 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
924 struct i915_address_space *active_vm[I915_NUM_ENGINES];
927 enum i915_cache_level {
929 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
930 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
931 caches, eg sampler/render caches, and the
932 large Last-Level-Cache. LLC is coherent with
933 the CPU, but L3 is only visible to the GPU. */
934 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
937 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
939 #define DEFAULT_CONTEXT_HANDLE 0
942 * struct i915_gem_context - as the name implies, represents a context.
943 * @ref: reference count.
944 * @user_handle: userspace tracking identity for this context.
945 * @remap_slice: l3 row remapping information.
946 * @flags: context specific flags:
947 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
948 * @file_priv: filp associated with this context (NULL for global default
950 * @hang_stats: information about the role of this context in possible GPU
952 * @ppgtt: virtual memory space used by this context.
953 * @legacy_hw_ctx: render context backing object and whether it is correctly
954 * initialized (legacy ring submission mechanism only).
955 * @link: link in the global list of contexts.
957 * Contexts are memory images used by the hardware to store copies of their
960 struct i915_gem_context {
962 struct drm_i915_private *i915;
963 struct drm_i915_file_private *file_priv;
964 struct i915_hw_ppgtt *ppgtt;
969 #define CONTEXT_NO_ZEROMAP BIT(0)
970 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
972 /* Unique identifier for this context, used by the hw for tracking */
975 int priority; /* greater priorities are serviced first */
979 struct intel_context {
980 struct i915_vma *state;
981 struct intel_ring *ring;
982 uint32_t *lrc_reg_state;
986 } engine[I915_NUM_ENGINES];
989 struct atomic_notifier_head status_notifier;
990 bool execlists_force_single_submission;
992 struct list_head link;
999 unsigned int guilty_count; /* guilty of a hang */
1000 unsigned int active_count; /* active during hang */
1002 #define CONTEXT_SCORE_GUILTY 10
1003 #define CONTEXT_SCORE_BAN_THRESHOLD 40
1004 /* Accumulated score of hangs caused by this context */
1017 /* This is always the inner lock when overlapping with struct_mutex and
1018 * it's the outer lock when overlapping with stolen_lock. */
1021 unsigned int possible_framebuffer_bits;
1022 unsigned int busy_bits;
1023 unsigned int visible_pipes_mask;
1024 struct intel_crtc *crtc;
1026 struct drm_mm_node compressed_fb;
1027 struct drm_mm_node *compressed_llb;
1034 bool underrun_detected;
1035 struct work_struct underrun_work;
1037 struct intel_fbc_state_cache {
1039 unsigned int mode_flags;
1040 uint32_t hsw_bdw_pixel_rate;
1044 unsigned int rotation;
1051 u64 ilk_ggtt_offset;
1052 uint32_t pixel_format;
1053 unsigned int stride;
1055 unsigned int tiling_mode;
1059 struct intel_fbc_reg_params {
1063 unsigned int fence_y_offset;
1068 uint32_t pixel_format;
1069 unsigned int stride;
1076 struct intel_fbc_work {
1078 u32 scheduled_vblank;
1079 struct work_struct work;
1082 const char *no_fbc_reason;
1086 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1087 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1088 * parsing for same resolution.
1090 enum drrs_refresh_rate_type {
1093 DRRS_MAX_RR, /* RR count */
1096 enum drrs_support_type {
1097 DRRS_NOT_SUPPORTED = 0,
1098 STATIC_DRRS_SUPPORT = 1,
1099 SEAMLESS_DRRS_SUPPORT = 2
1105 struct delayed_work work;
1106 struct intel_dp *dp;
1107 unsigned busy_frontbuffer_bits;
1108 enum drrs_refresh_rate_type refresh_rate_type;
1109 enum drrs_support_type type;
1116 struct intel_dp *enabled;
1118 struct delayed_work work;
1119 unsigned busy_frontbuffer_bits;
1121 bool aux_frame_sync;
1126 PCH_NONE = 0, /* No PCH present */
1127 PCH_IBX, /* Ibexpeak PCH */
1128 PCH_CPT, /* Cougarpoint PCH */
1129 PCH_LPT, /* Lynxpoint PCH */
1130 PCH_SPT, /* Sunrisepoint PCH */
1131 PCH_KBP, /* Kabypoint PCH */
1135 enum intel_sbi_destination {
1140 #define QUIRK_PIPEA_FORCE (1<<0)
1141 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1142 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1143 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1144 #define QUIRK_PIPEB_FORCE (1<<4)
1145 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1148 struct intel_fbc_work;
1150 struct intel_gmbus {
1151 struct i2c_adapter adapter;
1152 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1155 i915_reg_t gpio_reg;
1156 struct i2c_algo_bit_data bit_algo;
1157 struct drm_i915_private *dev_priv;
1160 struct i915_suspend_saved_registers {
1162 u32 saveFBC_CONTROL;
1163 u32 saveCACHE_MODE_0;
1164 u32 saveMI_ARB_STATE;
1168 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1169 u32 savePCH_PORT_HOTPLUG;
1173 struct vlv_s0ix_state {
1180 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1181 u32 media_max_req_count;
1182 u32 gfx_max_req_count;
1208 u32 rp_down_timeout;
1214 /* Display 1 CZ domain */
1219 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1221 /* GT SA CZ domain */
1228 /* Display 2 CZ domain */
1232 u32 clock_gate_dis2;
1235 struct intel_rps_ei {
1241 struct intel_gen6_power_mgmt {
1243 * work, interrupts_enabled and pm_iir are protected by
1244 * dev_priv->irq_lock
1246 struct work_struct work;
1247 bool interrupts_enabled;
1250 /* PM interrupt bits that should never be masked */
1253 /* Frequencies are stored in potentially platform dependent multiples.
1254 * In other words, *_freq needs to be multiplied by X to be interesting.
1255 * Soft limits are those which are used for the dynamic reclocking done
1256 * by the driver (raise frequencies under heavy loads, and lower for
1257 * lighter loads). Hard limits are those imposed by the hardware.
1259 * A distinction is made for overclocking, which is never enabled by
1260 * default, and is considered to be above the hard limit if it's
1263 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1264 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1265 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1266 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1267 u8 min_freq; /* AKA RPn. Minimum frequency */
1268 u8 boost_freq; /* Frequency to request when wait boosting */
1269 u8 idle_freq; /* Frequency to request when we are idle */
1270 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1271 u8 rp1_freq; /* "less than" RP0 power/freqency */
1272 u8 rp0_freq; /* Non-overclocked max frequency. */
1273 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1275 u8 up_threshold; /* Current %busy required to uplock */
1276 u8 down_threshold; /* Current %busy required to downclock */
1279 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1281 spinlock_t client_lock;
1282 struct list_head clients;
1286 struct delayed_work autoenable_work;
1289 /* manual wa residency calculations */
1290 struct intel_rps_ei up_ei, down_ei;
1293 * Protects RPS/RC6 register access and PCU communication.
1294 * Must be taken after struct_mutex if nested. Note that
1295 * this lock may be held for long periods of time when
1296 * talking to hw - so only take it when talking to hw!
1298 struct mutex hw_lock;
1301 /* defined intel_pm.c */
1302 extern spinlock_t mchdev_lock;
1304 struct intel_ilk_power_mgmt {
1312 unsigned long last_time1;
1313 unsigned long chipset_power;
1316 unsigned long gfx_power;
1323 struct drm_i915_private;
1324 struct i915_power_well;
1326 struct i915_power_well_ops {
1328 * Synchronize the well's hw state to match the current sw state, for
1329 * example enable/disable it based on the current refcount. Called
1330 * during driver init and resume time, possibly after first calling
1331 * the enable/disable handlers.
1333 void (*sync_hw)(struct drm_i915_private *dev_priv,
1334 struct i915_power_well *power_well);
1336 * Enable the well and resources that depend on it (for example
1337 * interrupts located on the well). Called after the 0->1 refcount
1340 void (*enable)(struct drm_i915_private *dev_priv,
1341 struct i915_power_well *power_well);
1343 * Disable the well and resources that depend on it. Called after
1344 * the 1->0 refcount transition.
1346 void (*disable)(struct drm_i915_private *dev_priv,
1347 struct i915_power_well *power_well);
1348 /* Returns the hw enabled state. */
1349 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1350 struct i915_power_well *power_well);
1353 /* Power well structure for haswell */
1354 struct i915_power_well {
1357 /* power well enable/disable usage count */
1359 /* cached hw enabled state */
1361 unsigned long domains;
1362 /* unique identifier for this power well */
1365 * Arbitraty data associated with this power well. Platform and power
1369 const struct i915_power_well_ops *ops;
1372 struct i915_power_domains {
1374 * Power wells needed for initialization at driver init and suspend
1375 * time are on. They are kept on until after the first modeset.
1379 int power_well_count;
1382 int domain_use_count[POWER_DOMAIN_NUM];
1383 struct i915_power_well *power_wells;
1386 #define MAX_L3_SLICES 2
1387 struct intel_l3_parity {
1388 u32 *remap_info[MAX_L3_SLICES];
1389 struct work_struct error_work;
1393 struct i915_gem_mm {
1394 /** Memory allocator for GTT stolen memory */
1395 struct drm_mm stolen;
1396 /** Protects the usage of the GTT stolen memory allocator. This is
1397 * always the inner lock when overlapping with struct_mutex. */
1398 struct mutex stolen_lock;
1400 /** List of all objects in gtt_space. Used to restore gtt
1401 * mappings on resume */
1402 struct list_head bound_list;
1404 * List of objects which are not bound to the GTT (thus
1405 * are idle and not used by the GPU). These objects may or may
1406 * not actually have any pages attached.
1408 struct list_head unbound_list;
1410 /** List of all objects in gtt_space, currently mmaped by userspace.
1411 * All objects within this list must also be on bound_list.
1413 struct list_head userfault_list;
1416 * List of objects which are pending destruction.
1418 struct llist_head free_list;
1419 struct work_struct free_work;
1421 /** Usable portion of the GTT for GEM */
1422 unsigned long stolen_base; /* limited to low memory (32-bit) */
1424 /** PPGTT used for aliasing the PPGTT with the GTT */
1425 struct i915_hw_ppgtt *aliasing_ppgtt;
1427 struct notifier_block oom_notifier;
1428 struct notifier_block vmap_notifier;
1429 struct shrinker shrinker;
1431 /** LRU list of objects with fence regs on them. */
1432 struct list_head fence_list;
1435 * Are we in a non-interruptible section of code like
1440 /* the indicator for dispatch video commands on two BSD rings */
1441 atomic_t bsd_engine_dispatch_index;
1443 /** Bit 6 swizzling required for X tiling */
1444 uint32_t bit_6_swizzle_x;
1445 /** Bit 6 swizzling required for Y tiling */
1446 uint32_t bit_6_swizzle_y;
1448 /* accounting, useful for userland debugging */
1449 spinlock_t object_stat_lock;
1454 struct drm_i915_error_state_buf {
1455 struct drm_i915_private *i915;
1464 struct i915_error_state_file_priv {
1465 struct drm_i915_private *i915;
1466 struct drm_i915_error_state *error;
1469 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1470 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1472 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1473 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1475 struct i915_gpu_error {
1476 /* For hangcheck timer */
1477 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1478 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1480 struct delayed_work hangcheck_work;
1482 /* For reset and error_state handling. */
1484 /* Protected by the above dev->gpu_error.lock. */
1485 struct drm_i915_error_state *first_error;
1487 unsigned long missed_irq_rings;
1490 * State variable controlling the reset flow and count
1492 * This is a counter which gets incremented when reset is triggered,
1494 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1495 * meaning that any waiters holding onto the struct_mutex should
1496 * relinquish the lock immediately in order for the reset to start.
1498 * If reset is not completed succesfully, the I915_WEDGE bit is
1499 * set meaning that hardware is terminally sour and there is no
1500 * recovery. All waiters on the reset_queue will be woken when
1503 * This counter is used by the wait_seqno code to notice that reset
1504 * event happened and it needs to restart the entire ioctl (since most
1505 * likely the seqno it waited for won't ever signal anytime soon).
1507 * This is important for lock-free wait paths, where no contended lock
1508 * naturally enforces the correct ordering between the bail-out of the
1509 * waiter and the gpu reset work code.
1511 unsigned long reset_count;
1513 unsigned long flags;
1514 #define I915_RESET_IN_PROGRESS 0
1515 #define I915_WEDGED (BITS_PER_LONG - 1)
1518 * Waitqueue to signal when a hang is detected. Used to for waiters
1519 * to release the struct_mutex for the reset to procede.
1521 wait_queue_head_t wait_queue;
1524 * Waitqueue to signal when the reset has completed. Used by clients
1525 * that wait for dev_priv->mm.wedged to settle.
1527 wait_queue_head_t reset_queue;
1529 /* For missed irq/seqno simulation. */
1530 unsigned long test_irq_rings;
1533 enum modeset_restore {
1534 MODESET_ON_LID_OPEN,
1539 #define DP_AUX_A 0x40
1540 #define DP_AUX_B 0x10
1541 #define DP_AUX_C 0x20
1542 #define DP_AUX_D 0x30
1544 #define DDC_PIN_B 0x05
1545 #define DDC_PIN_C 0x04
1546 #define DDC_PIN_D 0x06
1548 struct ddi_vbt_port_info {
1550 * This is an index in the HDMI/DVI DDI buffer translation table.
1551 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1552 * populate this field.
1554 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1555 uint8_t hdmi_level_shift;
1557 uint8_t supports_dvi:1;
1558 uint8_t supports_hdmi:1;
1559 uint8_t supports_dp:1;
1561 uint8_t alternate_aux_channel;
1562 uint8_t alternate_ddc_pin;
1564 uint8_t dp_boost_level;
1565 uint8_t hdmi_boost_level;
1568 enum psr_lines_to_wait {
1569 PSR_0_LINES_TO_WAIT = 0,
1571 PSR_4_LINES_TO_WAIT,
1575 struct intel_vbt_data {
1576 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1577 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1580 unsigned int int_tv_support:1;
1581 unsigned int lvds_dither:1;
1582 unsigned int lvds_vbt:1;
1583 unsigned int int_crt_support:1;
1584 unsigned int lvds_use_ssc:1;
1585 unsigned int display_clock_mode:1;
1586 unsigned int fdi_rx_polarity_inverted:1;
1587 unsigned int panel_type:4;
1589 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1591 enum drrs_support_type drrs_type;
1602 struct edp_power_seq pps;
1607 bool require_aux_wakeup;
1609 enum psr_lines_to_wait lines_to_wait;
1610 int tp1_wakeup_time;
1611 int tp2_tp3_wakeup_time;
1617 bool active_low_pwm;
1618 u8 min_brightness; /* min_brightness/255 of max */
1619 enum intel_backlight_type type;
1625 struct mipi_config *config;
1626 struct mipi_pps_data *pps;
1630 const u8 *sequence[MIPI_SEQ_MAX];
1636 union child_device_config *child_dev;
1638 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1639 struct sdvo_device_mapping sdvo_mappings[2];
1642 enum intel_ddb_partitioning {
1644 INTEL_DDB_PART_5_6, /* IVB+ */
1647 struct intel_wm_level {
1655 struct ilk_wm_values {
1656 uint32_t wm_pipe[3];
1658 uint32_t wm_lp_spr[3];
1659 uint32_t wm_linetime[3];
1661 enum intel_ddb_partitioning partitioning;
1664 struct vlv_pipe_wm {
1665 uint16_t plane[I915_MAX_PLANES];
1673 struct vlv_wm_ddl_values {
1674 uint8_t plane[I915_MAX_PLANES];
1677 struct vlv_wm_values {
1678 struct vlv_pipe_wm pipe[3];
1679 struct vlv_sr_wm sr;
1680 struct vlv_wm_ddl_values ddl[3];
1685 struct skl_ddb_entry {
1686 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1689 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1691 return entry->end - entry->start;
1694 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1695 const struct skl_ddb_entry *e2)
1697 if (e1->start == e2->start && e1->end == e2->end)
1703 struct skl_ddb_allocation {
1704 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1705 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1708 struct skl_wm_values {
1709 unsigned dirty_pipes;
1710 struct skl_ddb_allocation ddb;
1713 struct skl_wm_level {
1715 uint16_t plane_res_b;
1716 uint8_t plane_res_l;
1720 * This struct helps tracking the state needed for runtime PM, which puts the
1721 * device in PCI D3 state. Notice that when this happens, nothing on the
1722 * graphics device works, even register access, so we don't get interrupts nor
1725 * Every piece of our code that needs to actually touch the hardware needs to
1726 * either call intel_runtime_pm_get or call intel_display_power_get with the
1727 * appropriate power domain.
1729 * Our driver uses the autosuspend delay feature, which means we'll only really
1730 * suspend if we stay with zero refcount for a certain amount of time. The
1731 * default value is currently very conservative (see intel_runtime_pm_enable), but
1732 * it can be changed with the standard runtime PM files from sysfs.
1734 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1735 * goes back to false exactly before we reenable the IRQs. We use this variable
1736 * to check if someone is trying to enable/disable IRQs while they're supposed
1737 * to be disabled. This shouldn't happen and we'll print some error messages in
1740 * For more, read the Documentation/power/runtime_pm.txt.
1742 struct i915_runtime_pm {
1743 atomic_t wakeref_count;
1748 enum intel_pipe_crc_source {
1749 INTEL_PIPE_CRC_SOURCE_NONE,
1750 INTEL_PIPE_CRC_SOURCE_PLANE1,
1751 INTEL_PIPE_CRC_SOURCE_PLANE2,
1752 INTEL_PIPE_CRC_SOURCE_PF,
1753 INTEL_PIPE_CRC_SOURCE_PIPE,
1754 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1755 INTEL_PIPE_CRC_SOURCE_TV,
1756 INTEL_PIPE_CRC_SOURCE_DP_B,
1757 INTEL_PIPE_CRC_SOURCE_DP_C,
1758 INTEL_PIPE_CRC_SOURCE_DP_D,
1759 INTEL_PIPE_CRC_SOURCE_AUTO,
1760 INTEL_PIPE_CRC_SOURCE_MAX,
1763 struct intel_pipe_crc_entry {
1768 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1769 struct intel_pipe_crc {
1771 bool opened; /* exclusive access to the result file */
1772 struct intel_pipe_crc_entry *entries;
1773 enum intel_pipe_crc_source source;
1775 wait_queue_head_t wq;
1778 struct i915_frontbuffer_tracking {
1782 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1789 struct i915_wa_reg {
1792 /* bitmask representing WA bits */
1797 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1798 * allowing it for RCS as we don't foresee any requirement of having
1799 * a whitelist for other engines. When it is really required for
1800 * other engines then the limit need to be increased.
1802 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1804 struct i915_workarounds {
1805 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1807 u32 hw_whitelist_count[I915_NUM_ENGINES];
1810 struct i915_virtual_gpu {
1814 /* used in computing the new watermarks state */
1815 struct intel_wm_config {
1816 unsigned int num_pipes_active;
1817 bool sprites_enabled;
1818 bool sprites_scaled;
1821 struct i915_oa_format {
1826 struct i915_oa_reg {
1831 struct i915_perf_stream;
1833 struct i915_perf_stream_ops {
1834 /* Enables the collection of HW samples, either in response to
1835 * I915_PERF_IOCTL_ENABLE or implicitly called when stream is
1836 * opened without I915_PERF_FLAG_DISABLED.
1838 void (*enable)(struct i915_perf_stream *stream);
1840 /* Disables the collection of HW samples, either in response to
1841 * I915_PERF_IOCTL_DISABLE or implicitly called before
1842 * destroying the stream.
1844 void (*disable)(struct i915_perf_stream *stream);
1846 /* Call poll_wait, passing a wait queue that will be woken
1847 * once there is something ready to read() for the stream
1849 void (*poll_wait)(struct i915_perf_stream *stream,
1853 /* For handling a blocking read, wait until there is something
1854 * to ready to read() for the stream. E.g. wait on the same
1855 * wait queue that would be passed to poll_wait().
1857 int (*wait_unlocked)(struct i915_perf_stream *stream);
1859 /* read - Copy buffered metrics as records to userspace
1860 * @buf: the userspace, destination buffer
1861 * @count: the number of bytes to copy, requested by userspace
1862 * @offset: zero at the start of the read, updated as the read
1863 * proceeds, it represents how many bytes have been
1864 * copied so far and the buffer offset for copying the
1867 * Copy as many buffered i915 perf samples and records for
1868 * this stream to userspace as will fit in the given buffer.
1870 * Only write complete records; returning -ENOSPC if there
1871 * isn't room for a complete record.
1873 * Return any error condition that results in a short read
1874 * such as -ENOSPC or -EFAULT, even though these may be
1875 * squashed before returning to userspace.
1877 int (*read)(struct i915_perf_stream *stream,
1882 /* Cleanup any stream specific resources.
1884 * The stream will always be disabled before this is called.
1886 void (*destroy)(struct i915_perf_stream *stream);
1889 struct i915_perf_stream {
1890 struct drm_i915_private *dev_priv;
1892 struct list_head link;
1897 struct i915_gem_context *ctx;
1900 const struct i915_perf_stream_ops *ops;
1903 struct i915_oa_ops {
1904 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1905 int (*enable_metric_set)(struct drm_i915_private *dev_priv);
1906 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1907 void (*oa_enable)(struct drm_i915_private *dev_priv);
1908 void (*oa_disable)(struct drm_i915_private *dev_priv);
1909 void (*update_oacontrol)(struct drm_i915_private *dev_priv);
1910 void (*update_hw_ctx_id_locked)(struct drm_i915_private *dev_priv,
1912 int (*read)(struct i915_perf_stream *stream,
1916 bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
1919 struct drm_i915_private {
1920 struct drm_device drm;
1922 struct kmem_cache *objects;
1923 struct kmem_cache *vmas;
1924 struct kmem_cache *requests;
1925 struct kmem_cache *dependencies;
1927 const struct intel_device_info info;
1929 int relative_constants_mode;
1933 struct intel_uncore uncore;
1935 struct i915_virtual_gpu vgpu;
1937 struct intel_gvt *gvt;
1939 struct intel_guc guc;
1941 struct intel_csr csr;
1943 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1945 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1946 * controller on different i2c buses. */
1947 struct mutex gmbus_mutex;
1950 * Base address of the gmbus and gpio block.
1952 uint32_t gpio_mmio_base;
1954 /* MMIO base address for MIPI regs */
1955 uint32_t mipi_mmio_base;
1957 uint32_t psr_mmio_base;
1959 uint32_t pps_mmio_base;
1961 wait_queue_head_t gmbus_wait_queue;
1963 struct pci_dev *bridge_dev;
1964 struct i915_gem_context *kernel_context;
1965 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1966 struct i915_vma *semaphore;
1968 struct drm_dma_handle *status_page_dmah;
1969 struct resource mch_res;
1971 /* protects the irq masks */
1972 spinlock_t irq_lock;
1974 /* protects the mmio flip data */
1975 spinlock_t mmio_flip_lock;
1977 bool display_irqs_enabled;
1979 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1980 struct pm_qos_request pm_qos;
1982 /* Sideband mailbox protection */
1983 struct mutex sb_lock;
1985 /** Cached value of IMR to avoid reads in updating the bitfield */
1988 u32 de_irq_mask[I915_MAX_PIPES];
1995 u32 pipestat_irq_mask[I915_MAX_PIPES];
1997 struct i915_hotplug hotplug;
1998 struct intel_fbc fbc;
1999 struct i915_drrs drrs;
2000 struct intel_opregion opregion;
2001 struct intel_vbt_data vbt;
2003 bool preserve_bios_swizzle;
2006 struct intel_overlay *overlay;
2008 /* backlight registers and fields in struct intel_panel */
2009 struct mutex backlight_lock;
2012 bool no_aux_handshake;
2014 /* protects panel power sequencer state */
2015 struct mutex pps_mutex;
2017 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
2018 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2020 unsigned int fsb_freq, mem_freq, is_ddr3;
2021 unsigned int skl_preferred_vco_freq;
2022 unsigned int cdclk_freq, max_cdclk_freq;
2025 * For reading holding any crtc lock is sufficient,
2026 * for writing must hold all of them.
2028 unsigned int atomic_cdclk_freq;
2030 unsigned int max_dotclk_freq;
2031 unsigned int rawclk_freq;
2032 unsigned int hpll_freq;
2033 unsigned int czclk_freq;
2036 unsigned int vco, ref;
2040 * wq - Driver workqueue for GEM.
2042 * NOTE: Work items scheduled here are not allowed to grab any modeset
2043 * locks, for otherwise the flushing done in the pageflip code will
2044 * result in deadlocks.
2046 struct workqueue_struct *wq;
2048 /* Display functions */
2049 struct drm_i915_display_funcs display;
2051 /* PCH chipset type */
2052 enum intel_pch pch_type;
2053 unsigned short pch_id;
2055 unsigned long quirks;
2057 enum modeset_restore modeset_restore;
2058 struct mutex modeset_restore_lock;
2059 struct drm_atomic_state *modeset_restore_state;
2060 struct drm_modeset_acquire_ctx reset_ctx;
2062 struct list_head vm_list; /* Global list of all address spaces */
2063 struct i915_ggtt ggtt; /* VM representing the global address space */
2065 struct i915_gem_mm mm;
2066 DECLARE_HASHTABLE(mm_structs, 7);
2067 struct mutex mm_lock;
2069 /* The hw wants to have a stable context identifier for the lifetime
2070 * of the context (for OA, PASID, faults, etc). This is limited
2071 * in execlists to 21 bits.
2073 struct ida context_hw_ida;
2074 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2076 /* Kernel Modesetting */
2078 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2079 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2080 wait_queue_head_t pending_flip_queue;
2082 #ifdef CONFIG_DEBUG_FS
2083 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2086 /* dpll and cdclk state is protected by connection_mutex */
2087 int num_shared_dpll;
2088 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2089 const struct intel_dpll_mgr *dpll_mgr;
2092 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2093 * Must be global rather than per dpll, because on some platforms
2094 * plls share registers.
2096 struct mutex dpll_lock;
2098 unsigned int active_crtcs;
2099 unsigned int min_pixclk[I915_MAX_PIPES];
2101 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2103 struct i915_workarounds workarounds;
2105 struct i915_frontbuffer_tracking fb_tracking;
2109 bool mchbar_need_disable;
2111 struct intel_l3_parity l3_parity;
2113 /* Cannot be determined by PCIID. You must always read a register. */
2116 /* gen6+ rps state */
2117 struct intel_gen6_power_mgmt rps;
2119 /* ilk-only ips/rps state. Everything in here is protected by the global
2120 * mchdev_lock in intel_pm.c */
2121 struct intel_ilk_power_mgmt ips;
2123 struct i915_power_domains power_domains;
2125 struct i915_psr psr;
2127 struct i915_gpu_error gpu_error;
2129 struct drm_i915_gem_object *vlv_pctx;
2131 #ifdef CONFIG_DRM_FBDEV_EMULATION
2132 /* list of fbdev register on this device */
2133 struct intel_fbdev *fbdev;
2134 struct work_struct fbdev_suspend_work;
2137 struct drm_property *broadcast_rgb_property;
2138 struct drm_property *force_audio_property;
2140 /* hda/i915 audio component */
2141 struct i915_audio_component *audio_component;
2142 bool audio_component_registered;
2144 * av_mutex - mutex for audio/video sync
2147 struct mutex av_mutex;
2149 uint32_t hw_context_size;
2150 struct list_head context_list;
2154 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2155 u32 chv_phy_control;
2157 * Shadows for CHV DPLL_MD regs to keep the state
2158 * checker somewhat working in the presence hardware
2159 * crappiness (can't read out DPLL_MD for pipes B & C).
2161 u32 chv_dpll_md[I915_MAX_PIPES];
2165 bool suspended_to_idle;
2166 struct i915_suspend_saved_registers regfile;
2167 struct vlv_s0ix_state vlv_s0ix_state;
2170 I915_SAGV_UNKNOWN = 0,
2173 I915_SAGV_NOT_CONTROLLED
2178 * Raw watermark latency values:
2179 * in 0.1us units for WM0,
2180 * in 0.5us units for WM1+.
2183 uint16_t pri_latency[5];
2185 uint16_t spr_latency[5];
2187 uint16_t cur_latency[5];
2189 * Raw watermark memory latency values
2190 * for SKL for all 8 levels
2193 uint16_t skl_latency[8];
2195 /* current hardware state */
2197 struct ilk_wm_values hw;
2198 struct skl_wm_values skl_hw;
2199 struct vlv_wm_values vlv;
2205 * Should be held around atomic WM register writing; also
2206 * protects * intel_crtc->wm.active and
2207 * cstate->wm.need_postvbl_update.
2209 struct mutex wm_mutex;
2212 * Set during HW readout of watermarks/DDB. Some platforms
2213 * need to know when we're still using BIOS-provided values
2214 * (which we don't fully trust).
2216 bool distrust_bios_wm;
2219 struct i915_runtime_pm pm;
2224 struct kobject *metrics_kobj;
2225 struct ctl_table_header *sysctl_header;
2228 struct list_head streams;
2230 spinlock_t hook_lock;
2233 struct i915_perf_stream *exclusive_stream;
2235 u32 specific_ctx_id;
2236 struct i915_vma *pinned_rcs_vma;
2238 struct hrtimer poll_check_timer;
2239 wait_queue_head_t poll_wq;
2243 int period_exponent;
2244 int timestamp_frequency;
2250 const struct i915_oa_reg *mux_regs;
2252 const struct i915_oa_reg *b_counter_regs;
2253 int b_counter_regs_len;
2256 struct i915_vma *vma;
2262 u32 gen7_latched_oastatus1;
2264 struct i915_oa_ops ops;
2265 const struct i915_oa_format *oa_formats;
2270 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2272 void (*resume)(struct drm_i915_private *);
2273 void (*cleanup_engine)(struct intel_engine_cs *engine);
2275 struct list_head timelines;
2276 struct i915_gem_timeline global_timeline;
2277 u32 active_requests;
2280 * Is the GPU currently considered idle, or busy executing
2281 * userspace requests? Whilst idle, we allow runtime power
2282 * management to power down the hardware and display clocks.
2283 * In order to reduce the effect on performance, there
2284 * is a slight delay before we do so.
2289 * We leave the user IRQ off as much as possible,
2290 * but this means that requests will finish and never
2291 * be retired once the system goes idle. Set a timer to
2292 * fire periodically while the ring is running. When it
2293 * fires, go retire requests.
2295 struct delayed_work retire_work;
2298 * When we detect an idle GPU, we want to turn on
2299 * powersaving features. So once we see that there
2300 * are no more requests outstanding and no more
2301 * arrive within a small period of time, we fire
2302 * off the idle_work.
2304 struct delayed_work idle_work;
2306 ktime_t last_init_time;
2309 /* perform PHY state sanity checks? */
2310 bool chv_phy_assert[2];
2312 /* Used to save the pipe-to-encoder mapping for audio */
2313 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2316 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2317 * will be rejected. Instead look for a better place.
2321 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2323 return container_of(dev, struct drm_i915_private, drm);
2326 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2328 return to_i915(dev_get_drvdata(kdev));
2331 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2333 return container_of(guc, struct drm_i915_private, guc);
2336 /* Simple iterator over all initialised engines */
2337 #define for_each_engine(engine__, dev_priv__, id__) \
2339 (id__) < I915_NUM_ENGINES; \
2341 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2343 #define __mask_next_bit(mask) ({ \
2344 int __idx = ffs(mask) - 1; \
2345 mask &= ~BIT(__idx); \
2349 /* Iterator over subset of engines selected by mask */
2350 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2351 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2352 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2354 enum hdmi_force_audio {
2355 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2356 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2357 HDMI_AUDIO_AUTO, /* trust EDID */
2358 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2361 #define I915_GTT_OFFSET_NONE ((u32)-1)
2364 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2365 * considered to be the frontbuffer for the given plane interface-wise. This
2366 * doesn't mean that the hw necessarily already scans it out, but that any
2367 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2369 * We have one bit per pipe and per scanout plane type.
2371 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2372 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2373 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2374 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2375 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2376 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2377 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2378 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2379 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2380 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2381 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2382 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2385 * Optimised SGL iterator for GEM objects
2387 static __always_inline struct sgt_iter {
2388 struct scatterlist *sgp;
2395 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2396 struct sgt_iter s = { .sgp = sgl };
2399 s.max = s.curr = s.sgp->offset;
2400 s.max += s.sgp->length;
2402 s.dma = sg_dma_address(s.sgp);
2404 s.pfn = page_to_pfn(sg_page(s.sgp));
2410 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2413 if (unlikely(sg_is_chain(sg)))
2414 sg = sg_chain_ptr(sg);
2419 * __sg_next - return the next scatterlist entry in a list
2420 * @sg: The current sg entry
2423 * If the entry is the last, return NULL; otherwise, step to the next
2424 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2425 * otherwise just return the pointer to the current element.
2427 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2429 #ifdef CONFIG_DEBUG_SG
2430 BUG_ON(sg->sg_magic != SG_MAGIC);
2432 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2436 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2437 * @__dmap: DMA address (output)
2438 * @__iter: 'struct sgt_iter' (iterator state, internal)
2439 * @__sgt: sg_table to iterate over (input)
2441 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2442 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2443 ((__dmap) = (__iter).dma + (__iter).curr); \
2444 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2445 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2448 * for_each_sgt_page - iterate over the pages of the given sg_table
2449 * @__pp: page pointer (output)
2450 * @__iter: 'struct sgt_iter' (iterator state, internal)
2451 * @__sgt: sg_table to iterate over (input)
2453 #define for_each_sgt_page(__pp, __iter, __sgt) \
2454 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2455 ((__pp) = (__iter).pfn == 0 ? NULL : \
2456 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2457 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2458 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2460 static inline const struct intel_device_info *
2461 intel_info(const struct drm_i915_private *dev_priv)
2463 return &dev_priv->info;
2466 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2468 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2469 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2471 #define REVID_FOREVER 0xff
2472 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2474 #define GEN_FOREVER (0)
2476 * Returns true if Gen is in inclusive range [Start, End].
2478 * Use GEN_FOREVER for unbound start and or end.
2480 #define IS_GEN(dev_priv, s, e) ({ \
2481 unsigned int __s = (s), __e = (e); \
2482 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2483 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2484 if ((__s) != GEN_FOREVER) \
2486 if ((__e) == GEN_FOREVER) \
2487 __e = BITS_PER_LONG - 1; \
2490 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2494 * Return true if revision is in range [since,until] inclusive.
2496 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2498 #define IS_REVID(p, since, until) \
2499 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2501 #define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577)
2502 #define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562)
2503 #define IS_I85X(dev_priv) ((dev_priv)->info.is_i85x)
2504 #define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572)
2505 #define IS_I915G(dev_priv) ((dev_priv)->info.is_i915g)
2506 #define IS_I915GM(dev_priv) (INTEL_DEVID(dev_priv) == 0x2592)
2507 #define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772)
2508 #define IS_I945GM(dev_priv) ((dev_priv)->info.is_i945gm)
2509 #define IS_BROADWATER(dev_priv) ((dev_priv)->info.is_broadwater)
2510 #define IS_CRESTLINE(dev_priv) ((dev_priv)->info.is_crestline)
2511 #define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
2512 #define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x)
2513 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2514 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2515 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.is_pineview)
2516 #define IS_G33(dev_priv) ((dev_priv)->info.is_g33)
2517 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2518 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.is_ivybridge)
2519 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2520 INTEL_DEVID(dev_priv) == 0x0152 || \
2521 INTEL_DEVID(dev_priv) == 0x015a)
2522 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.is_valleyview)
2523 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview)
2524 #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
2525 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
2526 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
2527 #define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
2528 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.is_geminilake)
2529 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
2530 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2531 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2532 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2533 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2534 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2535 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2536 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2537 /* ULX machines are also considered ULT. */
2538 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2539 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2540 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2541 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2542 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2543 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2544 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2545 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2546 /* ULX machines are also considered ULT. */
2547 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2548 INTEL_DEVID(dev_priv) == 0x0A1E)
2549 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2550 INTEL_DEVID(dev_priv) == 0x1913 || \
2551 INTEL_DEVID(dev_priv) == 0x1916 || \
2552 INTEL_DEVID(dev_priv) == 0x1921 || \
2553 INTEL_DEVID(dev_priv) == 0x1926)
2554 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2555 INTEL_DEVID(dev_priv) == 0x1915 || \
2556 INTEL_DEVID(dev_priv) == 0x191E)
2557 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2558 INTEL_DEVID(dev_priv) == 0x5913 || \
2559 INTEL_DEVID(dev_priv) == 0x5916 || \
2560 INTEL_DEVID(dev_priv) == 0x5921 || \
2561 INTEL_DEVID(dev_priv) == 0x5926)
2562 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2563 INTEL_DEVID(dev_priv) == 0x5915 || \
2564 INTEL_DEVID(dev_priv) == 0x591E)
2565 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2566 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2567 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2568 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2570 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2572 #define SKL_REVID_A0 0x0
2573 #define SKL_REVID_B0 0x1
2574 #define SKL_REVID_C0 0x2
2575 #define SKL_REVID_D0 0x3
2576 #define SKL_REVID_E0 0x4
2577 #define SKL_REVID_F0 0x5
2578 #define SKL_REVID_G0 0x6
2579 #define SKL_REVID_H0 0x7
2581 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2583 #define BXT_REVID_A0 0x0
2584 #define BXT_REVID_A1 0x1
2585 #define BXT_REVID_B0 0x3
2586 #define BXT_REVID_B_LAST 0x8
2587 #define BXT_REVID_C0 0x9
2589 #define IS_BXT_REVID(dev_priv, since, until) \
2590 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2592 #define KBL_REVID_A0 0x0
2593 #define KBL_REVID_B0 0x1
2594 #define KBL_REVID_C0 0x2
2595 #define KBL_REVID_D0 0x3
2596 #define KBL_REVID_E0 0x4
2598 #define IS_KBL_REVID(dev_priv, since, until) \
2599 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2602 * The genX designation typically refers to the render engine, so render
2603 * capability related checks should use IS_GEN, while display and other checks
2604 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2607 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2608 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2609 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2610 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2611 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2612 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2613 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2614 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2616 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && INTEL_INFO(dev_priv)->is_lp)
2618 #define ENGINE_MASK(id) BIT(id)
2619 #define RENDER_RING ENGINE_MASK(RCS)
2620 #define BSD_RING ENGINE_MASK(VCS)
2621 #define BLT_RING ENGINE_MASK(BCS)
2622 #define VEBOX_RING ENGINE_MASK(VECS)
2623 #define BSD2_RING ENGINE_MASK(VCS2)
2624 #define ALL_ENGINES (~0)
2626 #define HAS_ENGINE(dev_priv, id) \
2627 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2629 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2630 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2631 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2632 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2634 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2635 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2636 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2637 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2638 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2640 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2642 #define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts)
2643 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2644 ((dev_priv)->info.has_logical_ring_contexts)
2645 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2646 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2647 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2649 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2650 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2651 ((dev_priv)->info.overlay_needs_physical)
2653 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2654 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv))
2656 /* WaRsDisableCoarsePowerGating:skl,bxt */
2657 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2658 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2659 IS_SKL_GT3(dev_priv) || \
2660 IS_SKL_GT4(dev_priv))
2663 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2664 * even when in MSI mode. This results in spurious interrupt warnings if the
2665 * legacy irq no. is shared with another device. The kernel then disables that
2666 * interrupt source and so prevents the other device from working properly.
2668 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2669 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2671 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2672 * rows, which changed the alignment requirements and fence programming.
2674 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2675 !(IS_I915G(dev_priv) || \
2676 IS_I915GM(dev_priv)))
2677 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2678 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2680 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2681 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2682 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2684 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2686 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2688 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2689 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2690 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2691 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2692 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2694 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2696 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2697 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2700 * For now, anything with a GuC requires uCode loading, and then supports
2701 * command submission once loaded. But these are logically independent
2702 * properties, so we have separate macros to test them.
2704 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2705 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2706 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2708 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2710 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2712 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2713 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2714 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2715 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2716 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2717 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2718 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2719 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2720 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2721 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2722 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2723 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2725 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2726 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2727 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2728 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2729 #define HAS_PCH_LPT_LP(dev_priv) \
2730 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2731 #define HAS_PCH_LPT_H(dev_priv) \
2732 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2733 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2734 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2735 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2736 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2738 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2740 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2742 /* DPF == dynamic parity feature */
2743 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2744 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2745 2 : HAS_L3_DPF(dev_priv))
2747 #define GT_FREQUENCY_MULTIPLIER 50
2748 #define GEN9_FREQ_SCALER 3
2750 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2752 #include "i915_trace.h"
2754 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2756 #ifdef CONFIG_INTEL_IOMMU
2757 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2763 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2766 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2770 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2771 const char *fmt, ...);
2773 #define i915_report_error(dev_priv, fmt, ...) \
2774 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2776 #ifdef CONFIG_COMPAT
2777 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2780 #define i915_compat_ioctl NULL
2782 extern const struct dev_pm_ops i915_pm_ops;
2784 extern int i915_driver_load(struct pci_dev *pdev,
2785 const struct pci_device_id *ent);
2786 extern void i915_driver_unload(struct drm_device *dev);
2787 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2788 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2789 extern void i915_reset(struct drm_i915_private *dev_priv);
2790 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2791 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2792 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2793 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2794 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2795 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2796 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2797 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2799 /* intel_hotplug.c */
2800 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2801 u32 pin_mask, u32 long_mask);
2802 void intel_hpd_init(struct drm_i915_private *dev_priv);
2803 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2804 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2805 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2806 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2807 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2810 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2812 unsigned long delay;
2814 if (unlikely(!i915.enable_hangcheck))
2817 /* Don't continually defer the hangcheck so that it is always run at
2818 * least once after work has been scheduled on any ring. Otherwise,
2819 * we will ignore a hung ring if a second ring is kept busy.
2822 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2823 queue_delayed_work(system_long_wq,
2824 &dev_priv->gpu_error.hangcheck_work, delay);
2828 void i915_handle_error(struct drm_i915_private *dev_priv,
2830 const char *fmt, ...);
2832 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2833 int intel_irq_install(struct drm_i915_private *dev_priv);
2834 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2836 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
2837 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2838 bool restore_forcewake);
2839 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2840 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2841 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2842 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
2843 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
2845 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2846 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2847 enum forcewake_domains domains);
2848 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2849 enum forcewake_domains domains);
2850 /* Like above but the caller must manage the uncore.lock itself.
2851 * Must be used with I915_READ_FW and friends.
2853 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2854 enum forcewake_domains domains);
2855 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2856 enum forcewake_domains domains);
2857 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
2859 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2861 int intel_wait_for_register(struct drm_i915_private *dev_priv,
2865 const unsigned long timeout_ms);
2866 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
2870 const unsigned long timeout_ms);
2872 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2874 return dev_priv->gvt;
2877 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2879 return dev_priv->vgpu.active;
2883 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2887 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2890 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2891 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2892 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2895 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2896 uint32_t interrupt_mask,
2897 uint32_t enabled_irq_mask);
2899 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2901 ilk_update_display_irq(dev_priv, bits, bits);
2904 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2906 ilk_update_display_irq(dev_priv, bits, 0);
2908 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2910 uint32_t interrupt_mask,
2911 uint32_t enabled_irq_mask);
2912 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2913 enum pipe pipe, uint32_t bits)
2915 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2917 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2918 enum pipe pipe, uint32_t bits)
2920 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2922 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2923 uint32_t interrupt_mask,
2924 uint32_t enabled_irq_mask);
2926 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2928 ibx_display_interrupt_update(dev_priv, bits, bits);
2931 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2933 ibx_display_interrupt_update(dev_priv, bits, 0);
2937 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2938 struct drm_file *file_priv);
2939 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2940 struct drm_file *file_priv);
2941 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2942 struct drm_file *file_priv);
2943 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2944 struct drm_file *file_priv);
2945 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2946 struct drm_file *file_priv);
2947 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2948 struct drm_file *file_priv);
2949 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2950 struct drm_file *file_priv);
2951 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2952 struct drm_file *file_priv);
2953 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2954 struct drm_file *file_priv);
2955 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2956 struct drm_file *file_priv);
2957 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2958 struct drm_file *file);
2959 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2960 struct drm_file *file);
2961 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2962 struct drm_file *file_priv);
2963 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2964 struct drm_file *file_priv);
2965 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2966 struct drm_file *file_priv);
2967 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2968 struct drm_file *file_priv);
2969 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2970 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2971 struct drm_file *file);
2972 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2973 struct drm_file *file_priv);
2974 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2975 struct drm_file *file_priv);
2976 int i915_gem_load_init(struct drm_i915_private *dev_priv);
2977 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
2978 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2979 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2980 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2982 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
2983 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2984 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2985 const struct drm_i915_gem_object_ops *ops);
2986 struct drm_i915_gem_object *
2987 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
2988 struct drm_i915_gem_object *
2989 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
2990 const void *data, size_t size);
2991 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2992 void i915_gem_free_object(struct drm_gem_object *obj);
2994 struct i915_vma * __must_check
2995 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2996 const struct i915_ggtt_view *view,
3001 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3002 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3004 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3006 static inline int __sg_page_count(const struct scatterlist *sg)
3008 return sg->length >> PAGE_SHIFT;
3011 struct scatterlist *
3012 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3013 unsigned int n, unsigned int *offset);
3016 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3020 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3024 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3027 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3028 struct sg_table *pages);
3029 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3031 static inline int __must_check
3032 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3034 might_lock(&obj->mm.lock);
3036 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3039 return __i915_gem_object_get_pages(obj);
3043 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3045 GEM_BUG_ON(!obj->mm.pages);
3047 atomic_inc(&obj->mm.pages_pin_count);
3051 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3053 return atomic_read(&obj->mm.pages_pin_count);
3057 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3059 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3060 GEM_BUG_ON(!obj->mm.pages);
3062 atomic_dec(&obj->mm.pages_pin_count);
3063 GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count) < obj->bind_count);
3067 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3069 __i915_gem_object_unpin_pages(obj);
3072 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3077 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3078 enum i915_mm_subclass subclass);
3079 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3081 enum i915_map_type {
3087 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3088 * @obj - the object to map into kernel address space
3089 * @type - the type of mapping, used to select pgprot_t
3091 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3092 * pages and then returns a contiguous mapping of the backing storage into
3093 * the kernel address space. Based on the @type of mapping, the PTE will be
3094 * set to either WriteBack or WriteCombine (via pgprot_t).
3096 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3097 * mapping is no longer required.
3099 * Returns the pointer through which to access the mapped object, or an
3100 * ERR_PTR() on error.
3102 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3103 enum i915_map_type type);
3106 * i915_gem_object_unpin_map - releases an earlier mapping
3107 * @obj - the object to unmap
3109 * After pinning the object and mapping its pages, once you are finished
3110 * with your access, call i915_gem_object_unpin_map() to release the pin
3111 * upon the mapping. Once the pin count reaches zero, that mapping may be
3114 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3116 i915_gem_object_unpin_pages(obj);
3119 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3120 unsigned int *needs_clflush);
3121 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3122 unsigned int *needs_clflush);
3123 #define CLFLUSH_BEFORE 0x1
3124 #define CLFLUSH_AFTER 0x2
3125 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3128 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3130 i915_gem_object_unpin_pages(obj);
3133 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3134 void i915_vma_move_to_active(struct i915_vma *vma,
3135 struct drm_i915_gem_request *req,
3136 unsigned int flags);
3137 int i915_gem_dumb_create(struct drm_file *file_priv,
3138 struct drm_device *dev,
3139 struct drm_mode_create_dumb *args);
3140 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3141 uint32_t handle, uint64_t *offset);
3142 int i915_gem_mmap_gtt_version(void);
3144 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3145 struct drm_i915_gem_object *new,
3146 unsigned frontbuffer_bits);
3148 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3150 struct drm_i915_gem_request *
3151 i915_gem_find_active_request(struct intel_engine_cs *engine);
3153 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3155 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3157 return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3160 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3162 return unlikely(test_bit(I915_WEDGED, &error->flags));
3165 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3167 return i915_reset_in_progress(error) | i915_terminally_wedged(error);
3170 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3172 return READ_ONCE(error->reset_count);
3175 void i915_gem_reset(struct drm_i915_private *dev_priv);
3176 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3177 void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3178 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3179 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3180 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3181 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3182 int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3183 unsigned int flags);
3184 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3185 void i915_gem_resume(struct drm_i915_private *dev_priv);
3186 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3187 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3190 struct intel_rps_client *rps);
3191 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3194 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3197 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3200 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3201 struct i915_vma * __must_check
3202 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3204 const struct i915_ggtt_view *view);
3205 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3206 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3208 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3209 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3211 u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
3213 u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
3214 int tiling_mode, bool fenced);
3216 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3217 enum i915_cache_level cache_level);
3219 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3220 struct dma_buf *dma_buf);
3222 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3223 struct drm_gem_object *gem_obj, int flags);
3226 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3227 struct i915_address_space *vm,
3228 const struct i915_ggtt_view *view);
3231 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3232 struct i915_address_space *vm,
3233 const struct i915_ggtt_view *view);
3235 static inline struct i915_hw_ppgtt *
3236 i915_vm_to_ppgtt(struct i915_address_space *vm)
3238 return container_of(vm, struct i915_hw_ppgtt, base);
3241 static inline struct i915_vma *
3242 i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj,
3243 const struct i915_ggtt_view *view)
3245 return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view);
3248 static inline unsigned long
3249 i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o,
3250 const struct i915_ggtt_view *view)
3252 return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view));
3255 /* i915_gem_fence_reg.c */
3256 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3257 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3259 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3261 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3262 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3263 struct sg_table *pages);
3264 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3265 struct sg_table *pages);
3267 /* i915_gem_context.c */
3268 int __must_check i915_gem_context_init(struct drm_i915_private *dev_priv);
3269 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3270 void i915_gem_context_fini(struct drm_i915_private *dev_priv);
3271 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3272 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3273 int i915_switch_context(struct drm_i915_gem_request *req);
3274 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3276 i915_gem_context_pin_legacy(struct i915_gem_context *ctx,
3277 unsigned int flags);
3278 void i915_gem_context_free(struct kref *ctx_ref);
3279 struct i915_gem_context *
3280 i915_gem_context_create_gvt(struct drm_device *dev);
3282 static inline struct i915_gem_context *
3283 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3285 struct i915_gem_context *ctx;
3287 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3289 ctx = idr_find(&file_priv->context_idr, id);
3291 return ERR_PTR(-ENOENT);
3296 static inline struct i915_gem_context *
3297 i915_gem_context_get(struct i915_gem_context *ctx)
3299 kref_get(&ctx->ref);
3303 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3305 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3306 kref_put(&ctx->ref, i915_gem_context_free);
3309 static inline struct intel_timeline *
3310 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3311 struct intel_engine_cs *engine)
3313 struct i915_address_space *vm;
3315 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3316 return &vm->timeline.engine[engine->id];
3319 static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3321 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3324 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3325 struct drm_file *file);
3326 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3327 struct drm_file *file);
3328 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3329 struct drm_file *file_priv);
3330 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3331 struct drm_file *file_priv);
3332 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
3333 struct drm_file *file);
3335 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3336 struct drm_file *file);
3338 /* i915_gem_evict.c */
3339 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3340 u64 min_size, u64 alignment,
3341 unsigned cache_level,
3344 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3345 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3347 /* belongs in i915_gem_gtt.h */
3348 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3351 if (INTEL_GEN(dev_priv) < 6)
3352 intel_gtt_chipset_flush();
3355 /* i915_gem_stolen.c */
3356 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3357 struct drm_mm_node *node, u64 size,
3358 unsigned alignment);
3359 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3360 struct drm_mm_node *node, u64 size,
3361 unsigned alignment, u64 start,
3363 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3364 struct drm_mm_node *node);
3365 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3366 void i915_gem_cleanup_stolen(struct drm_device *dev);
3367 struct drm_i915_gem_object *
3368 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3369 struct drm_i915_gem_object *
3370 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3375 /* i915_gem_internal.c */
3376 struct drm_i915_gem_object *
3377 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3380 /* i915_gem_shrinker.c */
3381 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3382 unsigned long target,
3384 #define I915_SHRINK_PURGEABLE 0x1
3385 #define I915_SHRINK_UNBOUND 0x2
3386 #define I915_SHRINK_BOUND 0x4
3387 #define I915_SHRINK_ACTIVE 0x8
3388 #define I915_SHRINK_VMAPS 0x10
3389 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3390 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3391 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3394 /* i915_gem_tiling.c */
3395 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3397 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3399 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3400 i915_gem_object_is_tiled(obj);
3403 /* i915_debugfs.c */
3404 #ifdef CONFIG_DEBUG_FS
3405 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3406 void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3407 int i915_debugfs_connector_add(struct drm_connector *connector);
3408 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3410 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3411 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3412 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3414 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3417 /* i915_gpu_error.c */
3418 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3421 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3422 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3423 const struct i915_error_state_file_priv *error);
3424 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3425 struct drm_i915_private *i915,
3426 size_t count, loff_t pos);
3427 static inline void i915_error_state_buf_release(
3428 struct drm_i915_error_state_buf *eb)
3432 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3434 const char *error_msg);
3435 void i915_error_state_get(struct drm_device *dev,
3436 struct i915_error_state_file_priv *error_priv);
3437 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3438 void i915_destroy_error_state(struct drm_i915_private *dev_priv);
3442 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3444 const char *error_msg)
3448 static inline void i915_destroy_error_state(struct drm_i915_private *dev_priv)
3454 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3456 /* i915_cmd_parser.c */
3457 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3458 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3459 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3460 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3461 struct drm_i915_gem_object *batch_obj,
3462 struct drm_i915_gem_object *shadow_batch_obj,
3463 u32 batch_start_offset,
3468 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3469 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3470 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3471 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3473 /* i915_suspend.c */
3474 extern int i915_save_state(struct drm_i915_private *dev_priv);
3475 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3478 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3479 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3482 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3483 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3484 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3487 extern struct i2c_adapter *
3488 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3489 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3490 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3491 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3493 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3495 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3498 int intel_bios_init(struct drm_i915_private *dev_priv);
3499 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3500 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3501 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3502 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3503 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3504 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3505 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3506 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3508 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3512 /* intel_opregion.c */
3514 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3515 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3516 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3517 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3518 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3520 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3522 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3524 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3525 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3526 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3527 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3531 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3536 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3540 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3548 extern void intel_register_dsm_handler(void);
3549 extern void intel_unregister_dsm_handler(void);
3551 static inline void intel_register_dsm_handler(void) { return; }
3552 static inline void intel_unregister_dsm_handler(void) { return; }
3553 #endif /* CONFIG_ACPI */
3555 /* intel_device_info.c */
3556 static inline struct intel_device_info *
3557 mkwrite_device_info(struct drm_i915_private *dev_priv)
3559 return (struct intel_device_info *)&dev_priv->info;
3562 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3563 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3566 extern void intel_modeset_init_hw(struct drm_device *dev);
3567 extern int intel_modeset_init(struct drm_device *dev);
3568 extern void intel_modeset_gem_init(struct drm_device *dev);
3569 extern void intel_modeset_cleanup(struct drm_device *dev);
3570 extern int intel_connector_register(struct drm_connector *);
3571 extern void intel_connector_unregister(struct drm_connector *);
3572 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3574 extern void intel_display_resume(struct drm_device *dev);
3575 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3576 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3577 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3578 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3579 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3580 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3583 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3584 struct drm_file *file);
3587 extern struct intel_overlay_error_state *
3588 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3589 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3590 struct intel_overlay_error_state *error);
3592 extern struct intel_display_error_state *
3593 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3594 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3595 struct drm_i915_private *dev_priv,
3596 struct intel_display_error_state *error);
3598 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3599 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3601 /* intel_sideband.c */
3602 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3603 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3604 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3605 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3606 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3607 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3608 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3609 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3610 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3611 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3612 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3613 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3614 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3615 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3616 enum intel_sbi_destination destination);
3617 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3618 enum intel_sbi_destination destination);
3619 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3620 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3622 /* intel_dpio_phy.c */
3623 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3624 enum dpio_phy *phy, enum dpio_channel *ch);
3625 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3626 enum port port, u32 margin, u32 scale,
3627 u32 enable, u32 deemphasis);
3628 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3629 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3630 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3632 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3634 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3635 uint8_t lane_count);
3636 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3637 uint8_t lane_lat_optim_mask);
3638 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3640 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3641 u32 deemph_reg_value, u32 margin_reg_value,
3642 bool uniq_trans_scale);
3643 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3645 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3646 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3647 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3648 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3650 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3651 u32 demph_reg_value, u32 preemph_reg_value,
3652 u32 uniqtranscale_reg_value, u32 tx3_demph);
3653 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3654 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3655 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3657 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3658 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3660 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3661 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3663 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3664 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3665 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3666 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3668 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3669 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3670 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3671 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3673 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3674 * will be implemented using 2 32-bit writes in an arbitrary order with
3675 * an arbitrary delay between them. This can cause the hardware to
3676 * act upon the intermediate value, possibly leading to corruption and
3677 * machine death. For this reason we do not support I915_WRITE64, or
3678 * dev_priv->uncore.funcs.mmio_writeq.
3680 * When reading a 64-bit value as two 32-bit values, the delay may cause
3681 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3682 * occasionally a 64-bit register does not actualy support a full readq
3683 * and must be read using two 32-bit reads.
3685 * You have been warned.
3687 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3689 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3690 u32 upper, lower, old_upper, loop = 0; \
3691 upper = I915_READ(upper_reg); \
3693 old_upper = upper; \
3694 lower = I915_READ(lower_reg); \
3695 upper = I915_READ(upper_reg); \
3696 } while (upper != old_upper && loop++ < 2); \
3697 (u64)upper << 32 | lower; })
3699 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3700 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3702 #define __raw_read(x, s) \
3703 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3706 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3709 #define __raw_write(x, s) \
3710 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3711 i915_reg_t reg, uint##x##_t val) \
3713 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3728 /* These are untraced mmio-accessors that are only valid to be used inside
3729 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3732 * Think twice, and think again, before using these.
3734 * As an example, these accessors can possibly be used between:
3736 * spin_lock_irq(&dev_priv->uncore.lock);
3737 * intel_uncore_forcewake_get__locked();
3741 * intel_uncore_forcewake_put__locked();
3742 * spin_unlock_irq(&dev_priv->uncore.lock);
3745 * Note: some registers may not need forcewake held, so
3746 * intel_uncore_forcewake_{get,put} can be omitted, see
3747 * intel_uncore_forcewake_for_reg().
3749 * Certain architectures will die if the same cacheline is concurrently accessed
3750 * by different clients (e.g. on Ivybridge). Access to registers should
3751 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3752 * a more localised lock guarding all access to that bank of registers.
3754 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3755 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3756 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3757 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3759 /* "Broadcast RGB" property */
3760 #define INTEL_BROADCAST_RGB_AUTO 0
3761 #define INTEL_BROADCAST_RGB_FULL 1
3762 #define INTEL_BROADCAST_RGB_LIMITED 2
3764 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3766 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3767 return VLV_VGACNTRL;
3768 else if (INTEL_GEN(dev_priv) >= 5)
3769 return CPU_VGACNTRL;
3774 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3776 unsigned long j = msecs_to_jiffies(m);
3778 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3781 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3783 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3786 static inline unsigned long
3787 timespec_to_jiffies_timeout(const struct timespec *value)
3789 unsigned long j = timespec_to_jiffies(value);
3791 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3795 * If you need to wait X milliseconds between events A and B, but event B
3796 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3797 * when event A happened, then just before event B you call this function and
3798 * pass the timestamp as the first argument, and X as the second argument.
3801 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3803 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3806 * Don't re-read the value of "jiffies" every time since it may change
3807 * behind our back and break the math.
3809 tmp_jiffies = jiffies;
3810 target_jiffies = timestamp_jiffies +
3811 msecs_to_jiffies_timeout(to_wait_ms);
3813 if (time_after(target_jiffies, tmp_jiffies)) {
3814 remaining_jiffies = target_jiffies - tmp_jiffies;
3815 while (remaining_jiffies)
3817 schedule_timeout_uninterruptible(remaining_jiffies);
3822 __i915_request_irq_complete(struct drm_i915_gem_request *req)
3824 struct intel_engine_cs *engine = req->engine;
3826 /* Before we do the heavier coherent read of the seqno,
3827 * check the value (hopefully) in the CPU cacheline.
3829 if (__i915_gem_request_completed(req))
3832 /* Ensure our read of the seqno is coherent so that we
3833 * do not "miss an interrupt" (i.e. if this is the last
3834 * request and the seqno write from the GPU is not visible
3835 * by the time the interrupt fires, we will see that the
3836 * request is incomplete and go back to sleep awaiting
3837 * another interrupt that will never come.)
3839 * Strictly, we only need to do this once after an interrupt,
3840 * but it is easier and safer to do it every time the waiter
3843 if (engine->irq_seqno_barrier &&
3844 rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
3845 cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
3846 struct task_struct *tsk;
3848 /* The ordering of irq_posted versus applying the barrier
3849 * is crucial. The clearing of the current irq_posted must
3850 * be visible before we perform the barrier operation,
3851 * such that if a subsequent interrupt arrives, irq_posted
3852 * is reasserted and our task rewoken (which causes us to
3853 * do another __i915_request_irq_complete() immediately
3854 * and reapply the barrier). Conversely, if the clear
3855 * occurs after the barrier, then an interrupt that arrived
3856 * whilst we waited on the barrier would not trigger a
3857 * barrier on the next pass, and the read may not see the
3860 engine->irq_seqno_barrier(engine);
3862 /* If we consume the irq, but we are no longer the bottom-half,
3863 * the real bottom-half may not have serialised their own
3864 * seqno check with the irq-barrier (i.e. may have inspected
3865 * the seqno before we believe it coherent since they see
3866 * irq_posted == false but we are still running).
3869 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
3870 if (tsk && tsk != current)
3871 /* Note that if the bottom-half is changed as we
3872 * are sending the wake-up, the new bottom-half will
3873 * be woken by whomever made the change. We only have
3874 * to worry about when we steal the irq-posted for
3877 wake_up_process(tsk);
3880 if (__i915_gem_request_completed(req))
3887 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3888 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3891 int remap_io_mapping(struct vm_area_struct *vma,
3892 unsigned long addr, unsigned long pfn, unsigned long size,
3893 struct io_mapping *iomap);
3895 #define ptr_mask_bits(ptr) ({ \
3896 unsigned long __v = (unsigned long)(ptr); \
3897 (typeof(ptr))(__v & PAGE_MASK); \
3900 #define ptr_unpack_bits(ptr, bits) ({ \
3901 unsigned long __v = (unsigned long)(ptr); \
3902 (bits) = __v & ~PAGE_MASK; \
3903 (typeof(ptr))(__v & PAGE_MASK); \
3906 #define ptr_pack_bits(ptr, bits) \
3907 ((typeof(ptr))((unsigned long)(ptr) | (bits)))
3909 #define fetch_and_zero(ptr) ({ \
3910 typeof(*ptr) __T = *(ptr); \
3911 *(ptr) = (typeof(*ptr))0; \