1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 I915_MAX_PIPES = _PIPE_EDP
64 #define pipe_name(p) ((p) + 'A')
73 #define transcoder_name(t) ((t) + 'A')
80 #define plane_name(p) ((p) + 'A')
82 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites + (s) + 'A')
92 #define port_name(p) ((p) + 'A')
94 #define I915_NUM_PHYS_VLV 1
106 enum intel_display_power_domain {
110 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
111 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
112 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
113 POWER_DOMAIN_TRANSCODER_A,
114 POWER_DOMAIN_TRANSCODER_B,
115 POWER_DOMAIN_TRANSCODER_C,
116 POWER_DOMAIN_TRANSCODER_EDP,
124 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
126 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
127 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
128 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
129 #define POWER_DOMAIN_TRANSCODER(tran) \
130 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
131 (tran) + POWER_DOMAIN_TRANSCODER_A)
133 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
134 BIT(POWER_DOMAIN_PIPE_A) | \
135 BIT(POWER_DOMAIN_TRANSCODER_EDP))
136 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
137 BIT(POWER_DOMAIN_PIPE_A) | \
138 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
139 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
143 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
144 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
154 #define I915_GEM_GPU_DOMAINS \
155 (I915_GEM_DOMAIN_RENDER | \
156 I915_GEM_DOMAIN_SAMPLER | \
157 I915_GEM_DOMAIN_COMMAND | \
158 I915_GEM_DOMAIN_INSTRUCTION | \
159 I915_GEM_DOMAIN_VERTEX)
161 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
163 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
164 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
165 if ((intel_encoder)->base.crtc == (__crtc))
167 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
168 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
169 if ((intel_connector)->base.encoder == (__encoder))
171 struct drm_i915_private;
174 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
175 /* real shared dpll ids must be >= 0 */
179 #define I915_NUM_PLLS 2
181 struct intel_dpll_hw_state {
188 struct intel_shared_dpll {
189 int refcount; /* count of number of CRTCs sharing this PLL */
190 int active; /* count of number of active CRTCs (i.e. DPMS on) */
191 bool on; /* is the PLL actually active? Disabled during modeset */
193 /* should match the index in the dev_priv->shared_dplls array */
194 enum intel_dpll_id id;
195 struct intel_dpll_hw_state hw_state;
196 void (*mode_set)(struct drm_i915_private *dev_priv,
197 struct intel_shared_dpll *pll);
198 void (*enable)(struct drm_i915_private *dev_priv,
199 struct intel_shared_dpll *pll);
200 void (*disable)(struct drm_i915_private *dev_priv,
201 struct intel_shared_dpll *pll);
202 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
203 struct intel_shared_dpll *pll,
204 struct intel_dpll_hw_state *hw_state);
207 /* Used by dp and fdi links */
208 struct intel_link_m_n {
216 void intel_link_compute_m_n(int bpp, int nlanes,
217 int pixel_clock, int link_clock,
218 struct intel_link_m_n *m_n);
220 struct intel_ddi_plls {
226 /* Interface history:
229 * 1.2: Add Power Management
230 * 1.3: Add vblank support
231 * 1.4: Fix cmdbuffer path, add heap destroy
232 * 1.5: Add vblank pipe configuration
233 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
234 * - Support vertical blank on secondary display pipe
236 #define DRIVER_MAJOR 1
237 #define DRIVER_MINOR 6
238 #define DRIVER_PATCHLEVEL 0
240 #define WATCH_LISTS 0
243 #define I915_GEM_PHYS_CURSOR_0 1
244 #define I915_GEM_PHYS_CURSOR_1 2
245 #define I915_GEM_PHYS_OVERLAY_REGS 3
246 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
248 struct drm_i915_gem_phys_object {
250 struct page **page_list;
251 drm_dma_handle_t *handle;
252 struct drm_i915_gem_object *cur_obj;
255 struct opregion_header;
256 struct opregion_acpi;
257 struct opregion_swsci;
258 struct opregion_asle;
260 struct intel_opregion {
261 struct opregion_header __iomem *header;
262 struct opregion_acpi __iomem *acpi;
263 struct opregion_swsci __iomem *swsci;
264 u32 swsci_gbda_sub_functions;
265 u32 swsci_sbcb_sub_functions;
266 struct opregion_asle __iomem *asle;
268 u32 __iomem *lid_state;
269 struct work_struct asle_work;
271 #define OPREGION_SIZE (8*1024)
273 struct intel_overlay;
274 struct intel_overlay_error_state;
276 struct drm_i915_master_private {
277 drm_local_map_t *sarea;
278 struct _drm_i915_sarea *sarea_priv;
280 #define I915_FENCE_REG_NONE -1
281 #define I915_MAX_NUM_FENCES 32
282 /* 32 fences + sign bit for FENCE_REG_NONE */
283 #define I915_MAX_NUM_FENCE_BITS 6
285 struct drm_i915_fence_reg {
286 struct list_head lru_list;
287 struct drm_i915_gem_object *obj;
291 struct sdvo_device_mapping {
300 struct intel_display_error_state;
302 struct drm_i915_error_state {
306 /* Generic register state */
313 u32 error; /* gen6+ */
314 u32 err_int; /* gen7 */
320 u32 extra_instdone[I915_NUM_INSTDONE_REG];
321 u32 pipestat[I915_MAX_PIPES];
322 u64 fence[I915_MAX_NUM_FENCES];
323 struct intel_overlay_error_state *overlay;
324 struct intel_display_error_state *display;
326 struct drm_i915_error_ring {
328 /* Software tracked state */
331 enum intel_ring_hangcheck_action hangcheck_action;
334 /* our own tracking of ring head and tail */
338 u32 semaphore_seqno[I915_NUM_RINGS - 1];
356 u32 rc_psmi; /* sleep state */
357 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
359 struct drm_i915_error_object {
363 } *ringbuffer, *batchbuffer, *ctx, *hws_page;
365 struct drm_i915_error_request {
378 } ring[I915_NUM_RINGS];
379 struct drm_i915_error_buffer {
386 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
393 } **active_bo, **pinned_bo;
395 u32 *active_bo_count, *pinned_bo_count;
398 struct intel_connector;
399 struct intel_crtc_config;
404 struct drm_i915_display_funcs {
405 bool (*fbc_enabled)(struct drm_device *dev);
406 void (*enable_fbc)(struct drm_crtc *crtc);
407 void (*disable_fbc)(struct drm_device *dev);
408 int (*get_display_clock_speed)(struct drm_device *dev);
409 int (*get_fifo_size)(struct drm_device *dev, int plane);
411 * find_dpll() - Find the best values for the PLL
412 * @limit: limits for the PLL
413 * @crtc: current CRTC
414 * @target: target frequency in kHz
415 * @refclk: reference clock frequency in kHz
416 * @match_clock: if provided, @best_clock P divider must
417 * match the P divider from @match_clock
418 * used for LVDS downclocking
419 * @best_clock: best PLL values found
421 * Returns true on success, false on failure.
423 bool (*find_dpll)(const struct intel_limit *limit,
424 struct drm_crtc *crtc,
425 int target, int refclk,
426 struct dpll *match_clock,
427 struct dpll *best_clock);
428 void (*update_wm)(struct drm_crtc *crtc);
429 void (*update_sprite_wm)(struct drm_plane *plane,
430 struct drm_crtc *crtc,
431 uint32_t sprite_width, int pixel_size,
432 bool enable, bool scaled);
433 void (*modeset_global_resources)(struct drm_device *dev);
434 /* Returns the active state of the crtc, and if the crtc is active,
435 * fills out the pipe-config with the hw state. */
436 bool (*get_pipe_config)(struct intel_crtc *,
437 struct intel_crtc_config *);
438 int (*crtc_mode_set)(struct drm_crtc *crtc,
440 struct drm_framebuffer *old_fb);
441 void (*crtc_enable)(struct drm_crtc *crtc);
442 void (*crtc_disable)(struct drm_crtc *crtc);
443 void (*off)(struct drm_crtc *crtc);
444 void (*write_eld)(struct drm_connector *connector,
445 struct drm_crtc *crtc,
446 struct drm_display_mode *mode);
447 void (*fdi_link_train)(struct drm_crtc *crtc);
448 void (*init_clock_gating)(struct drm_device *dev);
449 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
450 struct drm_framebuffer *fb,
451 struct drm_i915_gem_object *obj,
453 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
455 void (*hpd_irq_setup)(struct drm_device *dev);
456 /* clock updates for mode set */
458 /* render clock increase/decrease */
459 /* display clock increase/decrease */
460 /* pll clock increase/decrease */
462 int (*setup_backlight)(struct intel_connector *connector);
463 uint32_t (*get_backlight)(struct intel_connector *connector);
464 void (*set_backlight)(struct intel_connector *connector,
466 void (*disable_backlight)(struct intel_connector *connector);
467 void (*enable_backlight)(struct intel_connector *connector);
470 struct intel_uncore_funcs {
471 void (*force_wake_get)(struct drm_i915_private *dev_priv,
473 void (*force_wake_put)(struct drm_i915_private *dev_priv,
476 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
477 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
478 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
479 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
481 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
482 uint8_t val, bool trace);
483 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
484 uint16_t val, bool trace);
485 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
486 uint32_t val, bool trace);
487 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
488 uint64_t val, bool trace);
491 struct intel_uncore {
492 spinlock_t lock; /** lock is also taken in irq contexts. */
494 struct intel_uncore_funcs funcs;
497 unsigned forcewake_count;
499 unsigned fw_rendercount;
500 unsigned fw_mediacount;
502 struct delayed_work force_wake_work;
505 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
506 func(is_mobile) sep \
509 func(is_i945gm) sep \
511 func(need_gfx_hws) sep \
513 func(is_pineview) sep \
514 func(is_broadwater) sep \
515 func(is_crestline) sep \
516 func(is_ivybridge) sep \
517 func(is_valleyview) sep \
518 func(is_haswell) sep \
519 func(is_preliminary) sep \
521 func(has_pipe_cxsr) sep \
522 func(has_hotplug) sep \
523 func(cursor_needs_physical) sep \
524 func(has_overlay) sep \
525 func(overlay_needs_physical) sep \
526 func(supports_tv) sep \
531 #define DEFINE_FLAG(name) u8 name:1
532 #define SEP_SEMICOLON ;
534 struct intel_device_info {
535 u32 display_mmio_offset;
539 u8 ring_mask; /* Rings supported by the HW */
540 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
541 /* Register offsets for the various display pipes and transcoders */
542 int pipe_offsets[I915_MAX_TRANSCODERS];
543 int trans_offsets[I915_MAX_TRANSCODERS];
544 int dpll_offsets[I915_MAX_PIPES];
545 int dpll_md_offsets[I915_MAX_PIPES];
546 int palette_offsets[I915_MAX_PIPES];
552 enum i915_cache_level {
554 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
555 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
556 caches, eg sampler/render caches, and the
557 large Last-Level-Cache. LLC is coherent with
558 the CPU, but L3 is only visible to the GPU. */
559 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
562 typedef uint32_t gen6_gtt_pte_t;
565 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
566 * VMA's presence cannot be guaranteed before binding, or after unbinding the
567 * object into/from the address space.
569 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
570 * will always be <= an objects lifetime. So object refcounting should cover us.
573 struct drm_mm_node node;
574 struct drm_i915_gem_object *obj;
575 struct i915_address_space *vm;
577 /** This object's place on the active/inactive lists */
578 struct list_head mm_list;
580 struct list_head vma_link; /* Link in the object's VMA list */
582 /** This vma's place in the batchbuffer or on the eviction list */
583 struct list_head exec_list;
586 * Used for performing relocations during execbuffer insertion.
588 struct hlist_node exec_node;
589 unsigned long exec_handle;
590 struct drm_i915_gem_exec_object2 *exec_entry;
593 * How many users have pinned this object in GTT space. The following
594 * users can each hold at most one reference: pwrite/pread, pin_ioctl
595 * (via user_pin_count), execbuffer (objects are not allowed multiple
596 * times for the same batchbuffer), and the framebuffer code. When
597 * switching/pageflipping, the framebuffer code has at most two buffers
600 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
601 * bits with absolutely no headroom. So use 4 bits. */
602 unsigned int pin_count:4;
603 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
605 /** Unmap an object from an address space. This usually consists of
606 * setting the valid PTE entries to a reserved scratch page. */
607 void (*unbind_vma)(struct i915_vma *vma);
608 /* Map an object into an address space with the given cache flags. */
609 #define GLOBAL_BIND (1<<0)
610 void (*bind_vma)(struct i915_vma *vma,
611 enum i915_cache_level cache_level,
615 struct i915_address_space {
617 struct drm_device *dev;
618 struct list_head global_link;
619 unsigned long start; /* Start offset always 0 for dri2 */
620 size_t total; /* size addr space maps (ex. 2GB for ggtt) */
628 * List of objects currently involved in rendering.
630 * Includes buffers having the contents of their GPU caches
631 * flushed, not necessarily primitives. last_rendering_seqno
632 * represents when the rendering involved will be completed.
634 * A reference is held on the buffer while on this list.
636 struct list_head active_list;
639 * LRU list of objects which are not in the ringbuffer and
640 * are ready to unbind, but are still in the GTT.
642 * last_rendering_seqno is 0 while an object is in this list.
644 * A reference is not held on the buffer while on this list,
645 * as merely being GTT-bound shouldn't prevent its being
646 * freed, and we'll pull it off the list in the free path.
648 struct list_head inactive_list;
650 /* FIXME: Need a more generic return type */
651 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
652 enum i915_cache_level level,
653 bool valid); /* Create a valid PTE */
654 void (*clear_range)(struct i915_address_space *vm,
655 unsigned int first_entry,
656 unsigned int num_entries,
658 void (*insert_entries)(struct i915_address_space *vm,
660 unsigned int first_entry,
661 enum i915_cache_level cache_level);
662 void (*cleanup)(struct i915_address_space *vm);
665 /* The Graphics Translation Table is the way in which GEN hardware translates a
666 * Graphics Virtual Address into a Physical Address. In addition to the normal
667 * collateral associated with any va->pa translations GEN hardware also has a
668 * portion of the GTT which can be mapped by the CPU and remain both coherent
669 * and correct (in cases like swizzling). That region is referred to as GMADR in
673 struct i915_address_space base;
674 size_t stolen_size; /* Total size of stolen memory */
676 unsigned long mappable_end; /* End offset that we can CPU map */
677 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
678 phys_addr_t mappable_base; /* PA of our GMADR */
680 /** "Graphics Stolen Memory" holds the global PTEs */
688 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
689 size_t *stolen, phys_addr_t *mappable_base,
690 unsigned long *mappable_end);
692 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
694 struct i915_hw_ppgtt {
695 struct i915_address_space base;
697 struct drm_mm_node node;
698 unsigned num_pd_entries;
700 struct page **pt_pages;
701 struct page *gen8_pt_pages;
703 struct page *pd_pages;
708 dma_addr_t pd_dma_addr[4];
711 dma_addr_t *pt_dma_addr;
712 dma_addr_t *gen8_pt_dma_addr[4];
715 int (*enable)(struct i915_hw_ppgtt *ppgtt);
716 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
717 struct intel_ring_buffer *ring,
719 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
722 struct i915_ctx_hang_stats {
723 /* This context had batch pending when hang was declared */
724 unsigned batch_pending;
726 /* This context had batch active when hang was declared */
727 unsigned batch_active;
729 /* Time when this context was last blamed for a GPU reset */
730 unsigned long guilty_ts;
732 /* This context is banned to submit more work */
736 /* This must match up with the value previously used for execbuf2.rsvd1. */
737 #define DEFAULT_CONTEXT_ID 0
738 struct i915_hw_context {
743 struct drm_i915_file_private *file_priv;
744 struct intel_ring_buffer *last_ring;
745 struct drm_i915_gem_object *obj;
746 struct i915_ctx_hang_stats hang_stats;
747 struct i915_address_space *vm;
749 struct list_head link;
758 struct drm_mm_node *compressed_fb;
759 struct drm_mm_node *compressed_llb;
761 struct intel_fbc_work {
762 struct delayed_work work;
763 struct drm_crtc *crtc;
764 struct drm_framebuffer *fb;
768 FBC_OK, /* FBC is enabled */
769 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
770 FBC_NO_OUTPUT, /* no outputs enabled to compress */
771 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
772 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
773 FBC_MODE_TOO_LARGE, /* mode too large for compression */
774 FBC_BAD_PLANE, /* fbc not supported on plane */
775 FBC_NOT_TILED, /* buffer not tiled */
776 FBC_MULTIPLE_PIPES, /* more than one pipe active */
778 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
788 PCH_NONE = 0, /* No PCH present */
789 PCH_IBX, /* Ibexpeak PCH */
790 PCH_CPT, /* Cougarpoint PCH */
791 PCH_LPT, /* Lynxpoint PCH */
795 enum intel_sbi_destination {
800 #define QUIRK_PIPEA_FORCE (1<<0)
801 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
802 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
805 struct intel_fbc_work;
808 struct i2c_adapter adapter;
812 struct i2c_algo_bit_data bit_algo;
813 struct drm_i915_private *dev_priv;
816 struct i915_suspend_saved_registers {
837 u32 saveTRANS_HTOTAL_A;
838 u32 saveTRANS_HBLANK_A;
839 u32 saveTRANS_HSYNC_A;
840 u32 saveTRANS_VTOTAL_A;
841 u32 saveTRANS_VBLANK_A;
842 u32 saveTRANS_VSYNC_A;
850 u32 savePFIT_PGM_RATIOS;
851 u32 saveBLC_HIST_CTL;
853 u32 saveBLC_PWM_CTL2;
854 u32 saveBLC_HIST_CTL_B;
855 u32 saveBLC_CPU_PWM_CTL;
856 u32 saveBLC_CPU_PWM_CTL2;
869 u32 saveTRANS_HTOTAL_B;
870 u32 saveTRANS_HBLANK_B;
871 u32 saveTRANS_HSYNC_B;
872 u32 saveTRANS_VTOTAL_B;
873 u32 saveTRANS_VBLANK_B;
874 u32 saveTRANS_VSYNC_B;
888 u32 savePP_ON_DELAYS;
889 u32 savePP_OFF_DELAYS;
897 u32 savePFIT_CONTROL;
898 u32 save_palette_a[256];
899 u32 save_palette_b[256];
910 u32 saveCACHE_MODE_0;
911 u32 saveMI_ARB_STATE;
922 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
933 u32 savePIPEA_GMCH_DATA_M;
934 u32 savePIPEB_GMCH_DATA_M;
935 u32 savePIPEA_GMCH_DATA_N;
936 u32 savePIPEB_GMCH_DATA_N;
937 u32 savePIPEA_DP_LINK_M;
938 u32 savePIPEB_DP_LINK_M;
939 u32 savePIPEA_DP_LINK_N;
940 u32 savePIPEB_DP_LINK_N;
951 u32 savePCH_DREF_CONTROL;
952 u32 saveDISP_ARB_CTL;
953 u32 savePIPEA_DATA_M1;
954 u32 savePIPEA_DATA_N1;
955 u32 savePIPEA_LINK_M1;
956 u32 savePIPEA_LINK_N1;
957 u32 savePIPEB_DATA_M1;
958 u32 savePIPEB_DATA_N1;
959 u32 savePIPEB_LINK_M1;
960 u32 savePIPEB_LINK_N1;
961 u32 saveMCHBAR_RENDER_STANDBY;
962 u32 savePCH_PORT_HOTPLUG;
965 struct intel_gen6_power_mgmt {
966 /* work and pm_iir are protected by dev_priv->irq_lock */
967 struct work_struct work;
982 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
985 struct delayed_work delayed_resume_work;
988 * Protects RPS/RC6 register access and PCU communication.
989 * Must be taken after struct_mutex if nested.
991 struct mutex hw_lock;
994 /* defined intel_pm.c */
995 extern spinlock_t mchdev_lock;
997 struct intel_ilk_power_mgmt {
1005 unsigned long last_time1;
1006 unsigned long chipset_power;
1008 struct timespec last_time2;
1009 unsigned long gfx_power;
1015 struct drm_i915_gem_object *pwrctx;
1016 struct drm_i915_gem_object *renderctx;
1019 /* Power well structure for haswell */
1020 struct i915_power_well {
1023 /* power well enable/disable usage count */
1025 unsigned long domains;
1027 void (*set)(struct drm_device *dev, struct i915_power_well *power_well,
1029 bool (*is_enabled)(struct drm_device *dev,
1030 struct i915_power_well *power_well);
1033 struct i915_power_domains {
1035 * Power wells needed for initialization at driver init and suspend
1036 * time are on. They are kept on until after the first modeset.
1039 int power_well_count;
1042 int domain_use_count[POWER_DOMAIN_NUM];
1043 struct i915_power_well *power_wells;
1046 struct i915_dri1_state {
1047 unsigned allow_batchbuffer : 1;
1048 u32 __iomem *gfx_hws_cpu_addr;
1059 struct i915_ums_state {
1061 * Flag if the X Server, and thus DRM, is not currently in
1062 * control of the device.
1064 * This is set between LeaveVT and EnterVT. It needs to be
1065 * replaced with a semaphore. It also needs to be
1066 * transitioned away from for kernel modesetting.
1071 #define MAX_L3_SLICES 2
1072 struct intel_l3_parity {
1073 u32 *remap_info[MAX_L3_SLICES];
1074 struct work_struct error_work;
1078 struct i915_gem_mm {
1079 /** Memory allocator for GTT stolen memory */
1080 struct drm_mm stolen;
1081 /** List of all objects in gtt_space. Used to restore gtt
1082 * mappings on resume */
1083 struct list_head bound_list;
1085 * List of objects which are not bound to the GTT (thus
1086 * are idle and not used by the GPU) but still have
1087 * (presumably uncached) pages still attached.
1089 struct list_head unbound_list;
1091 /** Usable portion of the GTT for GEM */
1092 unsigned long stolen_base; /* limited to low memory (32-bit) */
1094 /** PPGTT used for aliasing the PPGTT with the GTT */
1095 struct i915_hw_ppgtt *aliasing_ppgtt;
1097 struct shrinker inactive_shrinker;
1098 bool shrinker_no_lock_stealing;
1100 /** LRU list of objects with fence regs on them. */
1101 struct list_head fence_list;
1104 * We leave the user IRQ off as much as possible,
1105 * but this means that requests will finish and never
1106 * be retired once the system goes idle. Set a timer to
1107 * fire periodically while the ring is running. When it
1108 * fires, go retire requests.
1110 struct delayed_work retire_work;
1113 * When we detect an idle GPU, we want to turn on
1114 * powersaving features. So once we see that there
1115 * are no more requests outstanding and no more
1116 * arrive within a small period of time, we fire
1117 * off the idle_work.
1119 struct delayed_work idle_work;
1122 * Are we in a non-interruptible section of code like
1127 /** Bit 6 swizzling required for X tiling */
1128 uint32_t bit_6_swizzle_x;
1129 /** Bit 6 swizzling required for Y tiling */
1130 uint32_t bit_6_swizzle_y;
1132 /* storage for physical objects */
1133 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1135 /* accounting, useful for userland debugging */
1136 spinlock_t object_stat_lock;
1137 size_t object_memory;
1141 struct drm_i915_error_state_buf {
1150 struct i915_error_state_file_priv {
1151 struct drm_device *dev;
1152 struct drm_i915_error_state *error;
1155 struct i915_gpu_error {
1156 /* For hangcheck timer */
1157 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1158 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1159 /* Hang gpu twice in this window and your context gets banned */
1160 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1162 struct timer_list hangcheck_timer;
1164 /* For reset and error_state handling. */
1166 /* Protected by the above dev->gpu_error.lock. */
1167 struct drm_i915_error_state *first_error;
1168 struct work_struct work;
1171 unsigned long missed_irq_rings;
1174 * State variable controlling the reset flow and count
1176 * This is a counter which gets incremented when reset is triggered,
1177 * and again when reset has been handled. So odd values (lowest bit set)
1178 * means that reset is in progress and even values that
1179 * (reset_counter >> 1):th reset was successfully completed.
1181 * If reset is not completed succesfully, the I915_WEDGE bit is
1182 * set meaning that hardware is terminally sour and there is no
1183 * recovery. All waiters on the reset_queue will be woken when
1186 * This counter is used by the wait_seqno code to notice that reset
1187 * event happened and it needs to restart the entire ioctl (since most
1188 * likely the seqno it waited for won't ever signal anytime soon).
1190 * This is important for lock-free wait paths, where no contended lock
1191 * naturally enforces the correct ordering between the bail-out of the
1192 * waiter and the gpu reset work code.
1194 atomic_t reset_counter;
1196 #define I915_RESET_IN_PROGRESS_FLAG 1
1197 #define I915_WEDGED (1 << 31)
1200 * Waitqueue to signal when the reset has completed. Used by clients
1201 * that wait for dev_priv->mm.wedged to settle.
1203 wait_queue_head_t reset_queue;
1205 /* For gpu hang simulation. */
1206 unsigned int stop_rings;
1208 /* For missed irq/seqno simulation. */
1209 unsigned int test_irq_rings;
1212 enum modeset_restore {
1213 MODESET_ON_LID_OPEN,
1218 struct ddi_vbt_port_info {
1219 uint8_t hdmi_level_shift;
1221 uint8_t supports_dvi:1;
1222 uint8_t supports_hdmi:1;
1223 uint8_t supports_dp:1;
1226 struct intel_vbt_data {
1227 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1228 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1231 unsigned int int_tv_support:1;
1232 unsigned int lvds_dither:1;
1233 unsigned int lvds_vbt:1;
1234 unsigned int int_crt_support:1;
1235 unsigned int lvds_use_ssc:1;
1236 unsigned int display_clock_mode:1;
1237 unsigned int fdi_rx_polarity_inverted:1;
1239 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1244 int edp_preemphasis;
1246 bool edp_initialized;
1249 struct edp_power_seq edp_pps;
1253 bool active_low_pwm;
1264 union child_device_config *child_dev;
1266 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1269 enum intel_ddb_partitioning {
1271 INTEL_DDB_PART_5_6, /* IVB+ */
1274 struct intel_wm_level {
1282 struct ilk_wm_values {
1283 uint32_t wm_pipe[3];
1285 uint32_t wm_lp_spr[3];
1286 uint32_t wm_linetime[3];
1288 enum intel_ddb_partitioning partitioning;
1292 * This struct tracks the state needed for the Package C8+ feature.
1294 * Package states C8 and deeper are really deep PC states that can only be
1295 * reached when all the devices on the system allow it, so even if the graphics
1296 * device allows PC8+, it doesn't mean the system will actually get to these
1299 * Our driver only allows PC8+ when all the outputs are disabled, the power well
1300 * is disabled and the GPU is idle. When these conditions are met, we manually
1301 * do the other conditions: disable the interrupts, clocks and switch LCPLL
1304 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1305 * the state of some registers, so when we come back from PC8+ we need to
1306 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1307 * need to take care of the registers kept by RC6.
1309 * The interrupt disabling is part of the requirements. We can only leave the
1310 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
1311 * can lock the machine.
1313 * Ideally every piece of our code that needs PC8+ disabled would call
1314 * hsw_disable_package_c8, which would increment disable_count and prevent the
1315 * system from reaching PC8+. But we don't have a symmetric way to do this for
1316 * everything, so we have the requirements_met and gpu_idle variables. When we
1317 * switch requirements_met or gpu_idle to true we decrease disable_count, and
1318 * increase it in the opposite case. The requirements_met variable is true when
1319 * all the CRTCs, encoders and the power well are disabled. The gpu_idle
1320 * variable is true when the GPU is idle.
1322 * In addition to everything, we only actually enable PC8+ if disable_count
1323 * stays at zero for at least some seconds. This is implemented with the
1324 * enable_work variable. We do this so we don't enable/disable PC8 dozens of
1325 * consecutive times when all screens are disabled and some background app
1326 * queries the state of our connectors, or we have some application constantly
1327 * waking up to use the GPU. Only after the enable_work function actually
1328 * enables PC8+ the "enable" variable will become true, which means that it can
1329 * be false even if disable_count is 0.
1331 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1332 * goes back to false exactly before we reenable the IRQs. We use this variable
1333 * to check if someone is trying to enable/disable IRQs while they're supposed
1334 * to be disabled. This shouldn't happen and we'll print some error messages in
1335 * case it happens, but if it actually happens we'll also update the variables
1336 * inside struct regsave so when we restore the IRQs they will contain the
1337 * latest expected values.
1339 * For more, read "Display Sequences for Package C8" on our documentation.
1341 struct i915_package_c8 {
1342 bool requirements_met;
1345 /* Only true after the delayed work task actually enables it. */
1349 struct delayed_work enable_work;
1356 uint32_t gen6_pmimr;
1360 struct i915_runtime_pm {
1364 enum intel_pipe_crc_source {
1365 INTEL_PIPE_CRC_SOURCE_NONE,
1366 INTEL_PIPE_CRC_SOURCE_PLANE1,
1367 INTEL_PIPE_CRC_SOURCE_PLANE2,
1368 INTEL_PIPE_CRC_SOURCE_PF,
1369 INTEL_PIPE_CRC_SOURCE_PIPE,
1370 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1371 INTEL_PIPE_CRC_SOURCE_TV,
1372 INTEL_PIPE_CRC_SOURCE_DP_B,
1373 INTEL_PIPE_CRC_SOURCE_DP_C,
1374 INTEL_PIPE_CRC_SOURCE_DP_D,
1375 INTEL_PIPE_CRC_SOURCE_AUTO,
1376 INTEL_PIPE_CRC_SOURCE_MAX,
1379 struct intel_pipe_crc_entry {
1384 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1385 struct intel_pipe_crc {
1387 bool opened; /* exclusive access to the result file */
1388 struct intel_pipe_crc_entry *entries;
1389 enum intel_pipe_crc_source source;
1391 wait_queue_head_t wq;
1394 typedef struct drm_i915_private {
1395 struct drm_device *dev;
1396 struct kmem_cache *slab;
1398 const struct intel_device_info info;
1400 int relative_constants_mode;
1404 struct intel_uncore uncore;
1406 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1409 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1410 * controller on different i2c buses. */
1411 struct mutex gmbus_mutex;
1414 * Base address of the gmbus and gpio block.
1416 uint32_t gpio_mmio_base;
1418 wait_queue_head_t gmbus_wait_queue;
1420 struct pci_dev *bridge_dev;
1421 struct intel_ring_buffer ring[I915_NUM_RINGS];
1422 uint32_t last_seqno, next_seqno;
1424 drm_dma_handle_t *status_page_dmah;
1425 struct resource mch_res;
1427 /* protects the irq masks */
1428 spinlock_t irq_lock;
1430 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1431 struct pm_qos_request pm_qos;
1433 /* DPIO indirect register protection */
1434 struct mutex dpio_lock;
1436 /** Cached value of IMR to avoid reads in updating the bitfield */
1439 u32 de_irq_mask[I915_MAX_PIPES];
1443 u32 pipestat_irq_mask[I915_MAX_PIPES];
1445 struct work_struct hotplug_work;
1446 bool enable_hotplug_processing;
1448 unsigned long hpd_last_jiffies;
1453 HPD_MARK_DISABLED = 2
1455 } hpd_stats[HPD_NUM_PINS];
1457 struct timer_list hotplug_reenable_timer;
1459 struct i915_fbc fbc;
1460 struct intel_opregion opregion;
1461 struct intel_vbt_data vbt;
1464 struct intel_overlay *overlay;
1466 /* backlight registers and fields in struct intel_panel */
1467 spinlock_t backlight_lock;
1470 bool no_aux_handshake;
1472 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1473 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1474 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1476 unsigned int fsb_freq, mem_freq, is_ddr3;
1479 * wq - Driver workqueue for GEM.
1481 * NOTE: Work items scheduled here are not allowed to grab any modeset
1482 * locks, for otherwise the flushing done in the pageflip code will
1483 * result in deadlocks.
1485 struct workqueue_struct *wq;
1487 /* Display functions */
1488 struct drm_i915_display_funcs display;
1490 /* PCH chipset type */
1491 enum intel_pch pch_type;
1492 unsigned short pch_id;
1494 unsigned long quirks;
1496 enum modeset_restore modeset_restore;
1497 struct mutex modeset_restore_lock;
1499 struct list_head vm_list; /* Global list of all address spaces */
1500 struct i915_gtt gtt; /* VMA representing the global address space */
1502 struct i915_gem_mm mm;
1504 /* Kernel Modesetting */
1506 struct sdvo_device_mapping sdvo_mappings[2];
1508 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1509 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1510 wait_queue_head_t pending_flip_queue;
1512 #ifdef CONFIG_DEBUG_FS
1513 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1516 int num_shared_dpll;
1517 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1518 struct intel_ddi_plls ddi_plls;
1519 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1521 /* Reclocking support */
1522 bool render_reclock_avail;
1523 bool lvds_downclock_avail;
1524 /* indicates the reduced downclock for LVDS*/
1528 bool mchbar_need_disable;
1530 struct intel_l3_parity l3_parity;
1532 /* Cannot be determined by PCIID. You must always read a register. */
1535 /* gen6+ rps state */
1536 struct intel_gen6_power_mgmt rps;
1538 /* ilk-only ips/rps state. Everything in here is protected by the global
1539 * mchdev_lock in intel_pm.c */
1540 struct intel_ilk_power_mgmt ips;
1542 struct i915_power_domains power_domains;
1544 struct i915_psr psr;
1546 struct i915_gpu_error gpu_error;
1548 struct drm_i915_gem_object *vlv_pctx;
1550 #ifdef CONFIG_DRM_I915_FBDEV
1551 /* list of fbdev register on this device */
1552 struct intel_fbdev *fbdev;
1556 * The console may be contended at resume, but we don't
1557 * want it to block on it.
1559 struct work_struct console_resume_work;
1561 struct drm_property *broadcast_rgb_property;
1562 struct drm_property *force_audio_property;
1564 uint32_t hw_context_size;
1565 struct list_head context_list;
1569 struct i915_suspend_saved_registers regfile;
1573 * Raw watermark latency values:
1574 * in 0.1us units for WM0,
1575 * in 0.5us units for WM1+.
1578 uint16_t pri_latency[5];
1580 uint16_t spr_latency[5];
1582 uint16_t cur_latency[5];
1584 /* current hardware state */
1585 struct ilk_wm_values hw;
1588 struct i915_package_c8 pc8;
1590 struct i915_runtime_pm pm;
1592 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1594 struct i915_dri1_state dri1;
1595 /* Old ums support infrastructure, same warning applies. */
1596 struct i915_ums_state ums;
1597 } drm_i915_private_t;
1599 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1601 return dev->dev_private;
1604 /* Iterate over initialised rings */
1605 #define for_each_ring(ring__, dev_priv__, i__) \
1606 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1607 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1609 enum hdmi_force_audio {
1610 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1611 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1612 HDMI_AUDIO_AUTO, /* trust EDID */
1613 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1616 #define I915_GTT_OFFSET_NONE ((u32)-1)
1618 struct drm_i915_gem_object_ops {
1619 /* Interface between the GEM object and its backing storage.
1620 * get_pages() is called once prior to the use of the associated set
1621 * of pages before to binding them into the GTT, and put_pages() is
1622 * called after we no longer need them. As we expect there to be
1623 * associated cost with migrating pages between the backing storage
1624 * and making them available for the GPU (e.g. clflush), we may hold
1625 * onto the pages after they are no longer referenced by the GPU
1626 * in case they may be used again shortly (for example migrating the
1627 * pages to a different memory domain within the GTT). put_pages()
1628 * will therefore most likely be called when the object itself is
1629 * being released or under memory pressure (where we attempt to
1630 * reap pages for the shrinker).
1632 int (*get_pages)(struct drm_i915_gem_object *);
1633 void (*put_pages)(struct drm_i915_gem_object *);
1636 struct drm_i915_gem_object {
1637 struct drm_gem_object base;
1639 const struct drm_i915_gem_object_ops *ops;
1641 /** List of VMAs backed by this object */
1642 struct list_head vma_list;
1644 /** Stolen memory for this object, instead of being backed by shmem. */
1645 struct drm_mm_node *stolen;
1646 struct list_head global_list;
1648 struct list_head ring_list;
1649 /** Used in execbuf to temporarily hold a ref */
1650 struct list_head obj_exec_link;
1653 * This is set if the object is on the active lists (has pending
1654 * rendering and so a non-zero seqno), and is not set if it i s on
1655 * inactive (ready to be unbound) list.
1657 unsigned int active:1;
1660 * This is set if the object has been written to since last bound
1663 unsigned int dirty:1;
1666 * Fence register bits (if any) for this object. Will be set
1667 * as needed when mapped into the GTT.
1668 * Protected by dev->struct_mutex.
1670 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1673 * Advice: are the backing pages purgeable?
1675 unsigned int madv:2;
1678 * Current tiling mode for the object.
1680 unsigned int tiling_mode:2;
1682 * Whether the tiling parameters for the currently associated fence
1683 * register have changed. Note that for the purposes of tracking
1684 * tiling changes we also treat the unfenced register, the register
1685 * slot that the object occupies whilst it executes a fenced
1686 * command (such as BLT on gen2/3), as a "fence".
1688 unsigned int fence_dirty:1;
1691 * Is the object at the current location in the gtt mappable and
1692 * fenceable? Used to avoid costly recalculations.
1694 unsigned int map_and_fenceable:1;
1697 * Whether the current gtt mapping needs to be mappable (and isn't just
1698 * mappable by accident). Track pin and fault separate for a more
1699 * accurate mappable working set.
1701 unsigned int fault_mappable:1;
1702 unsigned int pin_mappable:1;
1703 unsigned int pin_display:1;
1706 * Is the GPU currently using a fence to access this buffer,
1708 unsigned int pending_fenced_gpu_access:1;
1709 unsigned int fenced_gpu_access:1;
1711 unsigned int cache_level:3;
1713 unsigned int has_aliasing_ppgtt_mapping:1;
1714 unsigned int has_global_gtt_mapping:1;
1715 unsigned int has_dma_mapping:1;
1717 struct sg_table *pages;
1718 int pages_pin_count;
1720 /* prime dma-buf support */
1721 void *dma_buf_vmapping;
1724 struct intel_ring_buffer *ring;
1726 /** Breadcrumb of last rendering to the buffer. */
1727 uint32_t last_read_seqno;
1728 uint32_t last_write_seqno;
1729 /** Breadcrumb of last fenced GPU access to the buffer. */
1730 uint32_t last_fenced_seqno;
1732 /** Current tiling stride for the object, if it's tiled. */
1735 /** References from framebuffers, locks out tiling changes. */
1736 unsigned long framebuffer_references;
1738 /** Record of address bit 17 of each page at last unbind. */
1739 unsigned long *bit_17;
1741 /** User space pin count and filp owning the pin */
1742 unsigned long user_pin_count;
1743 struct drm_file *pin_filp;
1745 /** for phy allocated objects */
1746 struct drm_i915_gem_phys_object *phys_obj;
1748 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1750 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1753 * Request queue structure.
1755 * The request queue allows us to note sequence numbers that have been emitted
1756 * and may be associated with active buffers to be retired.
1758 * By keeping this list, we can avoid having to do questionable
1759 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1760 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1762 struct drm_i915_gem_request {
1763 /** On Which ring this request was generated */
1764 struct intel_ring_buffer *ring;
1766 /** GEM sequence number associated with this request. */
1769 /** Position in the ringbuffer of the start of the request */
1772 /** Position in the ringbuffer of the end of the request */
1775 /** Context related to this request */
1776 struct i915_hw_context *ctx;
1778 /** Batch buffer related to this request if any */
1779 struct drm_i915_gem_object *batch_obj;
1781 /** Time at which this request was emitted, in jiffies. */
1782 unsigned long emitted_jiffies;
1784 /** global list entry for this request */
1785 struct list_head list;
1787 struct drm_i915_file_private *file_priv;
1788 /** file_priv list entry for this request */
1789 struct list_head client_list;
1792 struct drm_i915_file_private {
1793 struct drm_i915_private *dev_priv;
1797 struct list_head request_list;
1798 struct delayed_work idle_work;
1800 struct idr context_idr;
1802 struct i915_hw_context *private_default_ctx;
1803 atomic_t rps_wait_boost;
1806 #define INTEL_INFO(dev) (&to_i915(dev)->info)
1808 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1809 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1810 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1811 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1812 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1813 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1814 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1815 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1816 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1817 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1818 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1819 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1820 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1821 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1822 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1823 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1824 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1825 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1826 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1827 (dev)->pdev->device == 0x0152 || \
1828 (dev)->pdev->device == 0x015a)
1829 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1830 (dev)->pdev->device == 0x0106 || \
1831 (dev)->pdev->device == 0x010A)
1832 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1833 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1834 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8)
1835 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1836 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1837 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1838 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1839 (((dev)->pdev->device & 0xf) == 0x2 || \
1840 ((dev)->pdev->device & 0xf) == 0x6 || \
1841 ((dev)->pdev->device & 0xf) == 0xe))
1842 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1843 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1844 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1845 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1846 ((dev)->pdev->device & 0x00F0) == 0x0020)
1847 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1850 * The genX designation typically refers to the render engine, so render
1851 * capability related checks should use IS_GEN, while display and other checks
1852 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1855 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1856 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1857 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1858 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1859 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1860 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1861 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1863 #define RENDER_RING (1<<RCS)
1864 #define BSD_RING (1<<VCS)
1865 #define BLT_RING (1<<BCS)
1866 #define VEBOX_RING (1<<VECS)
1867 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1868 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1869 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1870 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1871 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1872 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1874 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1875 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
1876 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) \
1877 && !IS_BROADWELL(dev))
1878 #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false)
1879 #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
1881 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1882 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1884 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1885 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1887 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1888 * rows, which changed the alignment requirements and fence programming.
1890 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1892 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1893 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1894 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1895 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1896 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1898 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1899 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1900 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1902 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
1904 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1905 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1906 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1907 #define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
1908 #define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev))
1910 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1911 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1912 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1913 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1914 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1915 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1917 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1918 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1919 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1920 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1921 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1922 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1924 /* DPF == dynamic parity feature */
1925 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1926 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
1928 #define GT_FREQUENCY_MULTIPLIER 50
1930 #include "i915_trace.h"
1932 extern const struct drm_ioctl_desc i915_ioctls[];
1933 extern int i915_max_ioctl;
1935 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1936 extern int i915_resume(struct drm_device *dev);
1937 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1938 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1941 struct i915_params {
1943 int panel_ignore_lid;
1944 unsigned int powersave;
1946 unsigned int lvds_downclock;
1947 int lvds_channel_mode;
1949 int vbt_sdvo_panel_type;
1954 unsigned int preliminary_hw_support;
1955 int disable_power_well;
1959 int invert_brightness;
1960 /* leave bools at the end to not create holes */
1961 bool enable_hangcheck;
1963 bool prefault_disable;
1965 bool disable_display;
1967 extern struct i915_params i915 __read_mostly;
1970 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1971 extern void i915_kernel_lost_context(struct drm_device * dev);
1972 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1973 extern int i915_driver_unload(struct drm_device *);
1974 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1975 extern void i915_driver_lastclose(struct drm_device * dev);
1976 extern void i915_driver_preclose(struct drm_device *dev,
1977 struct drm_file *file_priv);
1978 extern void i915_driver_postclose(struct drm_device *dev,
1979 struct drm_file *file_priv);
1980 extern int i915_driver_device_is_agp(struct drm_device * dev);
1981 #ifdef CONFIG_COMPAT
1982 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1985 extern int i915_emit_box(struct drm_device *dev,
1986 struct drm_clip_rect *box,
1988 extern int intel_gpu_reset(struct drm_device *dev);
1989 extern int i915_reset(struct drm_device *dev);
1990 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1991 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1992 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1993 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1995 extern void intel_console_resume(struct work_struct *work);
1998 void i915_queue_hangcheck(struct drm_device *dev);
1999 void i915_handle_error(struct drm_device *dev, bool wedged);
2001 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
2003 extern void intel_irq_init(struct drm_device *dev);
2004 extern void intel_hpd_init(struct drm_device *dev);
2006 extern void intel_uncore_sanitize(struct drm_device *dev);
2007 extern void intel_uncore_early_sanitize(struct drm_device *dev);
2008 extern void intel_uncore_init(struct drm_device *dev);
2009 extern void intel_uncore_check_errors(struct drm_device *dev);
2010 extern void intel_uncore_fini(struct drm_device *dev);
2013 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe,
2017 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe,
2021 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2022 struct drm_file *file_priv);
2023 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2024 struct drm_file *file_priv);
2025 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2026 struct drm_file *file_priv);
2027 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2028 struct drm_file *file_priv);
2029 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2030 struct drm_file *file_priv);
2031 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2032 struct drm_file *file_priv);
2033 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2034 struct drm_file *file_priv);
2035 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2036 struct drm_file *file_priv);
2037 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2038 struct drm_file *file_priv);
2039 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2040 struct drm_file *file_priv);
2041 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2042 struct drm_file *file_priv);
2043 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2044 struct drm_file *file_priv);
2045 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2046 struct drm_file *file_priv);
2047 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2048 struct drm_file *file);
2049 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2050 struct drm_file *file);
2051 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2052 struct drm_file *file_priv);
2053 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2054 struct drm_file *file_priv);
2055 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2056 struct drm_file *file_priv);
2057 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2058 struct drm_file *file_priv);
2059 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2060 struct drm_file *file_priv);
2061 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2062 struct drm_file *file_priv);
2063 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2064 struct drm_file *file_priv);
2065 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2066 struct drm_file *file_priv);
2067 void i915_gem_load(struct drm_device *dev);
2068 void *i915_gem_object_alloc(struct drm_device *dev);
2069 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2070 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2071 const struct drm_i915_gem_object_ops *ops);
2072 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2074 void i915_init_vm(struct drm_i915_private *dev_priv,
2075 struct i915_address_space *vm);
2076 void i915_gem_free_object(struct drm_gem_object *obj);
2077 void i915_gem_vma_destroy(struct i915_vma *vma);
2079 #define PIN_MAPPABLE 0x1
2080 #define PIN_NONBLOCK 0x2
2081 #define PIN_GLOBAL 0x4
2082 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2083 struct i915_address_space *vm,
2086 int __must_check i915_vma_unbind(struct i915_vma *vma);
2087 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2088 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2089 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2090 void i915_gem_lastclose(struct drm_device *dev);
2092 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2093 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2095 struct sg_page_iter sg_iter;
2097 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2098 return sg_page_iter_page(&sg_iter);
2102 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2104 BUG_ON(obj->pages == NULL);
2105 obj->pages_pin_count++;
2107 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2109 BUG_ON(obj->pages_pin_count == 0);
2110 obj->pages_pin_count--;
2113 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2114 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2115 struct intel_ring_buffer *to);
2116 void i915_vma_move_to_active(struct i915_vma *vma,
2117 struct intel_ring_buffer *ring);
2118 int i915_gem_dumb_create(struct drm_file *file_priv,
2119 struct drm_device *dev,
2120 struct drm_mode_create_dumb *args);
2121 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2122 uint32_t handle, uint64_t *offset);
2124 * Returns true if seq1 is later than seq2.
2127 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2129 return (int32_t)(seq1 - seq2) >= 0;
2132 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2133 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2134 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2135 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2138 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
2140 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2141 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2142 dev_priv->fence_regs[obj->fence_reg].pin_count++;
2149 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
2151 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2152 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2153 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
2154 dev_priv->fence_regs[obj->fence_reg].pin_count--;
2158 bool i915_gem_retire_requests(struct drm_device *dev);
2159 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
2160 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2161 bool interruptible);
2162 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2164 return unlikely(atomic_read(&error->reset_counter)
2165 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2168 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2170 return atomic_read(&error->reset_counter) & I915_WEDGED;
2173 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2175 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2178 void i915_gem_reset(struct drm_device *dev);
2179 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2180 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2181 int __must_check i915_gem_init(struct drm_device *dev);
2182 int __must_check i915_gem_init_hw(struct drm_device *dev);
2183 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
2184 void i915_gem_init_swizzling(struct drm_device *dev);
2185 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2186 int __must_check i915_gpu_idle(struct drm_device *dev);
2187 int __must_check i915_gem_suspend(struct drm_device *dev);
2188 int __i915_add_request(struct intel_ring_buffer *ring,
2189 struct drm_file *file,
2190 struct drm_i915_gem_object *batch_obj,
2192 #define i915_add_request(ring, seqno) \
2193 __i915_add_request(ring, NULL, NULL, seqno)
2194 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2196 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2198 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2201 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2203 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2205 struct intel_ring_buffer *pipelined);
2206 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2207 int i915_gem_attach_phys_object(struct drm_device *dev,
2208 struct drm_i915_gem_object *obj,
2211 void i915_gem_detach_phys_object(struct drm_device *dev,
2212 struct drm_i915_gem_object *obj);
2213 void i915_gem_free_all_phys_object(struct drm_device *dev);
2214 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2215 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2218 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2220 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2221 int tiling_mode, bool fenced);
2223 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2224 enum i915_cache_level cache_level);
2226 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2227 struct dma_buf *dma_buf);
2229 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2230 struct drm_gem_object *gem_obj, int flags);
2232 void i915_gem_restore_fences(struct drm_device *dev);
2234 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2235 struct i915_address_space *vm);
2236 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2237 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2238 struct i915_address_space *vm);
2239 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2240 struct i915_address_space *vm);
2241 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2242 struct i915_address_space *vm);
2244 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2245 struct i915_address_space *vm);
2247 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2248 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2249 struct i915_vma *vma;
2250 list_for_each_entry(vma, &obj->vma_list, vma_link)
2251 if (vma->pin_count > 0)
2256 /* Some GGTT VM helpers */
2257 #define obj_to_ggtt(obj) \
2258 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2259 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2261 struct i915_address_space *ggtt =
2262 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2266 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2268 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2271 static inline unsigned long
2272 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2274 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2277 static inline unsigned long
2278 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2280 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2283 static inline int __must_check
2284 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2288 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
2292 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2294 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2297 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2299 /* i915_gem_context.c */
2300 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2301 int __must_check i915_gem_context_init(struct drm_device *dev);
2302 void i915_gem_context_fini(struct drm_device *dev);
2303 void i915_gem_context_reset(struct drm_device *dev);
2304 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2305 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2306 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2307 int i915_switch_context(struct intel_ring_buffer *ring,
2308 struct drm_file *file, struct i915_hw_context *to);
2309 struct i915_hw_context *
2310 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2311 void i915_gem_context_free(struct kref *ctx_ref);
2312 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2314 if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))
2315 kref_get(&ctx->ref);
2318 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2320 if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))
2321 kref_put(&ctx->ref, i915_gem_context_free);
2324 static inline bool i915_gem_context_is_default(const struct i915_hw_context *c)
2326 return c->id == DEFAULT_CONTEXT_ID;
2329 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2330 struct drm_file *file);
2331 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2332 struct drm_file *file);
2334 /* i915_gem_evict.c */
2335 int __must_check i915_gem_evict_something(struct drm_device *dev,
2336 struct i915_address_space *vm,
2339 unsigned cache_level,
2341 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2342 int i915_gem_evict_everything(struct drm_device *dev);
2344 /* i915_gem_gtt.c */
2345 void i915_check_and_clear_faults(struct drm_device *dev);
2346 void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
2347 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
2348 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
2349 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
2350 void i915_gem_init_global_gtt(struct drm_device *dev);
2351 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
2352 unsigned long mappable_end, unsigned long end);
2353 int i915_gem_gtt_init(struct drm_device *dev);
2354 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2356 if (INTEL_INFO(dev)->gen < 6)
2357 intel_gtt_chipset_flush();
2359 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
2360 static inline bool intel_enable_ppgtt(struct drm_device *dev, bool full)
2362 if (i915.enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
2365 if (i915.enable_ppgtt == 1 && full)
2368 #ifdef CONFIG_INTEL_IOMMU
2369 /* Disable ppgtt on SNB if VT-d is on. */
2370 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
2371 DRM_INFO("Disabling PPGTT because VT-d is on\n");
2377 return HAS_PPGTT(dev);
2379 return HAS_ALIASING_PPGTT(dev);
2382 static inline void ppgtt_release(struct kref *kref)
2384 struct i915_hw_ppgtt *ppgtt = container_of(kref, struct i915_hw_ppgtt, ref);
2385 struct drm_device *dev = ppgtt->base.dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct i915_address_space *vm = &ppgtt->base;
2389 if (ppgtt == dev_priv->mm.aliasing_ppgtt ||
2390 (list_empty(&vm->active_list) && list_empty(&vm->inactive_list))) {
2391 ppgtt->base.cleanup(&ppgtt->base);
2396 * Make sure vmas are unbound before we take down the drm_mm
2398 * FIXME: Proper refcounting should take care of this, this shouldn't be
2401 if (!list_empty(&vm->active_list)) {
2402 struct i915_vma *vma;
2404 list_for_each_entry(vma, &vm->active_list, mm_list)
2405 if (WARN_ON(list_empty(&vma->vma_link) ||
2406 list_is_singular(&vma->vma_link)))
2409 i915_gem_evict_vm(&ppgtt->base, true);
2411 i915_gem_retire_requests(dev);
2412 i915_gem_evict_vm(&ppgtt->base, false);
2415 ppgtt->base.cleanup(&ppgtt->base);
2418 /* i915_gem_stolen.c */
2419 int i915_gem_init_stolen(struct drm_device *dev);
2420 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2421 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2422 void i915_gem_cleanup_stolen(struct drm_device *dev);
2423 struct drm_i915_gem_object *
2424 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2425 struct drm_i915_gem_object *
2426 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2430 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2432 /* i915_gem_tiling.c */
2433 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2435 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2437 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2438 obj->tiling_mode != I915_TILING_NONE;
2441 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2442 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2443 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2445 /* i915_gem_debug.c */
2447 int i915_verify_lists(struct drm_device *dev);
2449 #define i915_verify_lists(dev) 0
2452 /* i915_debugfs.c */
2453 int i915_debugfs_init(struct drm_minor *minor);
2454 void i915_debugfs_cleanup(struct drm_minor *minor);
2455 #ifdef CONFIG_DEBUG_FS
2456 void intel_display_crc_init(struct drm_device *dev);
2458 static inline void intel_display_crc_init(struct drm_device *dev) {}
2461 /* i915_gpu_error.c */
2463 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2464 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2465 const struct i915_error_state_file_priv *error);
2466 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2467 size_t count, loff_t pos);
2468 static inline void i915_error_state_buf_release(
2469 struct drm_i915_error_state_buf *eb)
2473 void i915_capture_error_state(struct drm_device *dev);
2474 void i915_error_state_get(struct drm_device *dev,
2475 struct i915_error_state_file_priv *error_priv);
2476 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2477 void i915_destroy_error_state(struct drm_device *dev);
2479 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2480 const char *i915_cache_level_str(int type);
2482 /* i915_suspend.c */
2483 extern int i915_save_state(struct drm_device *dev);
2484 extern int i915_restore_state(struct drm_device *dev);
2487 void i915_save_display_reg(struct drm_device *dev);
2488 void i915_restore_display_reg(struct drm_device *dev);
2491 void i915_setup_sysfs(struct drm_device *dev_priv);
2492 void i915_teardown_sysfs(struct drm_device *dev_priv);
2495 extern int intel_setup_gmbus(struct drm_device *dev);
2496 extern void intel_teardown_gmbus(struct drm_device *dev);
2497 static inline bool intel_gmbus_is_port_valid(unsigned port)
2499 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2502 extern struct i2c_adapter *intel_gmbus_get_adapter(
2503 struct drm_i915_private *dev_priv, unsigned port);
2504 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2505 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2506 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2508 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2510 extern void intel_i2c_reset(struct drm_device *dev);
2512 /* intel_opregion.c */
2513 struct intel_encoder;
2514 extern int intel_opregion_setup(struct drm_device *dev);
2516 extern void intel_opregion_init(struct drm_device *dev);
2517 extern void intel_opregion_fini(struct drm_device *dev);
2518 extern void intel_opregion_asle_intr(struct drm_device *dev);
2519 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2521 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2524 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2525 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2526 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2528 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2533 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2541 extern void intel_register_dsm_handler(void);
2542 extern void intel_unregister_dsm_handler(void);
2544 static inline void intel_register_dsm_handler(void) { return; }
2545 static inline void intel_unregister_dsm_handler(void) { return; }
2546 #endif /* CONFIG_ACPI */
2549 extern void intel_modeset_init_hw(struct drm_device *dev);
2550 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2551 extern void intel_modeset_init(struct drm_device *dev);
2552 extern void intel_modeset_gem_init(struct drm_device *dev);
2553 extern void intel_modeset_cleanup(struct drm_device *dev);
2554 extern void intel_connector_unregister(struct intel_connector *);
2555 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2556 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2557 bool force_restore);
2558 extern void i915_redisable_vga(struct drm_device *dev);
2559 extern bool intel_fbc_enabled(struct drm_device *dev);
2560 extern void intel_disable_fbc(struct drm_device *dev);
2561 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2562 extern void intel_init_pch_refclk(struct drm_device *dev);
2563 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2564 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2565 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2566 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2567 extern void intel_detect_pch(struct drm_device *dev);
2568 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2569 extern int intel_enable_rc6(const struct drm_device *dev);
2571 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2572 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2573 struct drm_file *file);
2574 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2575 struct drm_file *file);
2578 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2579 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2580 struct intel_overlay_error_state *error);
2582 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2583 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2584 struct drm_device *dev,
2585 struct intel_display_error_state *error);
2587 /* On SNB platform, before reading ring registers forcewake bit
2588 * must be set to prevent GT core from power down and stale values being
2591 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2592 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2594 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2595 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2597 /* intel_sideband.c */
2598 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2599 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2600 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2601 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2602 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2603 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2604 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2605 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2606 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2607 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2608 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2609 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2610 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2611 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2612 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2613 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2614 enum intel_sbi_destination destination);
2615 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2616 enum intel_sbi_destination destination);
2617 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2618 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2620 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2621 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2623 void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2624 void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2626 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
2627 (((reg) >= 0x2000 && (reg) < 0x4000) ||\
2628 ((reg) >= 0x5000 && (reg) < 0x8000) ||\
2629 ((reg) >= 0xB000 && (reg) < 0x12000) ||\
2630 ((reg) >= 0x2E000 && (reg) < 0x30000))
2632 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
2633 (((reg) >= 0x12000 && (reg) < 0x14000) ||\
2634 ((reg) >= 0x22000 && (reg) < 0x24000) ||\
2635 ((reg) >= 0x30000 && (reg) < 0x40000))
2637 #define FORCEWAKE_RENDER (1 << 0)
2638 #define FORCEWAKE_MEDIA (1 << 1)
2639 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2642 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2643 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2645 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2646 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2647 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2648 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2650 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2651 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2652 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2653 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2655 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2656 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2658 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2659 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2661 /* "Broadcast RGB" property */
2662 #define INTEL_BROADCAST_RGB_AUTO 0
2663 #define INTEL_BROADCAST_RGB_FULL 1
2664 #define INTEL_BROADCAST_RGB_LIMITED 2
2666 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2668 if (HAS_PCH_SPLIT(dev))
2669 return CPU_VGACNTRL;
2670 else if (IS_VALLEYVIEW(dev))
2671 return VLV_VGACNTRL;
2676 static inline void __user *to_user_ptr(u64 address)
2678 return (void __user *)(uintptr_t)address;
2681 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2683 unsigned long j = msecs_to_jiffies(m);
2685 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2688 static inline unsigned long
2689 timespec_to_jiffies_timeout(const struct timespec *value)
2691 unsigned long j = timespec_to_jiffies(value);
2693 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2697 * If you need to wait X milliseconds between events A and B, but event B
2698 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2699 * when event A happened, then just before event B you call this function and
2700 * pass the timestamp as the first argument, and X as the second argument.
2703 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2705 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
2708 * Don't re-read the value of "jiffies" every time since it may change
2709 * behind our back and break the math.
2711 tmp_jiffies = jiffies;
2712 target_jiffies = timestamp_jiffies +
2713 msecs_to_jiffies_timeout(to_wait_ms);
2715 if (time_after(target_jiffies, tmp_jiffies)) {
2716 remaining_jiffies = target_jiffies - tmp_jiffies;
2717 while (remaining_jiffies)
2719 schedule_timeout_uninterruptible(remaining_jiffies);