1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
51 #include "i915_params.h"
54 #include "intel_bios.h"
55 #include "intel_dpll_mgr.h"
56 #include "intel_guc.h"
57 #include "intel_lrc.h"
58 #include "intel_ringbuffer.h"
61 #include "i915_gem_gtt.h"
62 #include "i915_gem_render_state.h"
64 #include "intel_gvt.h"
66 /* General customization:
69 #define DRIVER_NAME "i915"
70 #define DRIVER_DESC "Intel Graphics"
71 #define DRIVER_DATE "20160620"
74 /* Many gcc seem to no see through this and fall over :( */
76 #define WARN_ON(x) ({ \
77 bool __i915_warn_cond = (x); \
78 if (__builtin_constant_p(__i915_warn_cond)) \
79 BUILD_BUG_ON(__i915_warn_cond); \
80 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
82 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
86 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
88 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
89 (long) (x), __func__);
91 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
92 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
93 * which may not necessarily be a user visible problem. This will either
94 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
95 * enable distros and users to tailor their preferred amount of i915 abrt
98 #define I915_STATE_WARN(condition, format...) ({ \
99 int __ret_warn_on = !!(condition); \
100 if (unlikely(__ret_warn_on)) \
101 if (!WARN(i915.verbose_state_checks, format)) \
103 unlikely(__ret_warn_on); \
106 #define I915_STATE_WARN_ON(x) \
107 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
109 bool __i915_inject_load_failure(const char *func, int line);
110 #define i915_inject_load_failure() \
111 __i915_inject_load_failure(__func__, __LINE__)
113 static inline const char *yesno(bool v)
115 return v ? "yes" : "no";
118 static inline const char *onoff(bool v)
120 return v ? "on" : "off";
129 I915_MAX_PIPES = _PIPE_EDP
131 #define pipe_name(p) ((p) + 'A')
143 static inline const char *transcoder_name(enum transcoder transcoder)
145 switch (transcoder) {
154 case TRANSCODER_DSI_A:
156 case TRANSCODER_DSI_C:
163 static inline bool transcoder_is_dsi(enum transcoder transcoder)
165 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
169 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
170 * number of planes per CRTC. Not all platforms really have this many planes,
171 * which means some arrays of size I915_MAX_PLANES may have unused entries
172 * between the topmost sprite plane and the cursor plane.
181 #define plane_name(p) ((p) + 'A')
183 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
193 #define port_name(p) ((p) + 'A')
195 #define I915_NUM_PHYS_VLV 2
207 enum intel_display_power_domain {
211 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
212 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
213 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
214 POWER_DOMAIN_TRANSCODER_A,
215 POWER_DOMAIN_TRANSCODER_B,
216 POWER_DOMAIN_TRANSCODER_C,
217 POWER_DOMAIN_TRANSCODER_EDP,
218 POWER_DOMAIN_TRANSCODER_DSI_A,
219 POWER_DOMAIN_TRANSCODER_DSI_C,
220 POWER_DOMAIN_PORT_DDI_A_LANES,
221 POWER_DOMAIN_PORT_DDI_B_LANES,
222 POWER_DOMAIN_PORT_DDI_C_LANES,
223 POWER_DOMAIN_PORT_DDI_D_LANES,
224 POWER_DOMAIN_PORT_DDI_E_LANES,
225 POWER_DOMAIN_PORT_DSI,
226 POWER_DOMAIN_PORT_CRT,
227 POWER_DOMAIN_PORT_OTHER,
236 POWER_DOMAIN_MODESET,
242 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
243 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
244 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
245 #define POWER_DOMAIN_TRANSCODER(tran) \
246 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
247 (tran) + POWER_DOMAIN_TRANSCODER_A)
251 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
263 #define for_each_hpd_pin(__pin) \
264 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
266 struct i915_hotplug {
267 struct work_struct hotplug_work;
270 unsigned long last_jiffies;
275 HPD_MARK_DISABLED = 2
277 } stats[HPD_NUM_PINS];
279 struct delayed_work reenable_work;
281 struct intel_digital_port *irq_port[I915_MAX_PORTS];
284 struct work_struct dig_port_work;
287 * if we get a HPD irq from DP and a HPD irq from non-DP
288 * the non-DP HPD could block the workqueue on a mode config
289 * mutex getting, that userspace may have taken. However
290 * userspace is waiting on the DP workqueue to run which is
291 * blocked behind the non-DP one.
293 struct workqueue_struct *dp_wq;
296 #define I915_GEM_GPU_DOMAINS \
297 (I915_GEM_DOMAIN_RENDER | \
298 I915_GEM_DOMAIN_SAMPLER | \
299 I915_GEM_DOMAIN_COMMAND | \
300 I915_GEM_DOMAIN_INSTRUCTION | \
301 I915_GEM_DOMAIN_VERTEX)
303 #define for_each_pipe(__dev_priv, __p) \
304 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
305 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
306 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
307 for_each_if ((__mask) & (1 << (__p)))
308 #define for_each_plane(__dev_priv, __pipe, __p) \
310 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
312 #define for_each_sprite(__dev_priv, __p, __s) \
314 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
317 #define for_each_port_masked(__port, __ports_mask) \
318 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
319 for_each_if ((__ports_mask) & (1 << (__port)))
321 #define for_each_crtc(dev, crtc) \
322 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
324 #define for_each_intel_plane(dev, intel_plane) \
325 list_for_each_entry(intel_plane, \
326 &dev->mode_config.plane_list, \
329 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
330 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, \
332 for_each_if ((plane_mask) & \
333 (1 << drm_plane_index(&intel_plane->base)))
335 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
336 list_for_each_entry(intel_plane, \
337 &(dev)->mode_config.plane_list, \
339 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
341 #define for_each_intel_crtc(dev, intel_crtc) \
342 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
344 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
345 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) \
346 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
348 #define for_each_intel_encoder(dev, intel_encoder) \
349 list_for_each_entry(intel_encoder, \
350 &(dev)->mode_config.encoder_list, \
353 #define for_each_intel_connector(dev, intel_connector) \
354 list_for_each_entry(intel_connector, \
355 &dev->mode_config.connector_list, \
358 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
359 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
360 for_each_if ((intel_encoder)->base.crtc == (__crtc))
362 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
363 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
364 for_each_if ((intel_connector)->base.encoder == (__encoder))
366 #define for_each_power_domain(domain, mask) \
367 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
368 for_each_if ((1 << (domain)) & (mask))
370 struct drm_i915_private;
371 struct i915_mm_struct;
372 struct i915_mmu_object;
374 struct drm_i915_file_private {
375 struct drm_i915_private *dev_priv;
376 struct drm_file *file;
380 struct list_head request_list;
381 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
382 * chosen to prevent the CPU getting more than a frame ahead of the GPU
383 * (when using lax throttling for the frontbuffer). We also use it to
384 * offer free GPU waitboosts for severely congested workloads.
386 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
388 struct idr context_idr;
390 struct intel_rps_client {
391 struct list_head link;
395 unsigned int bsd_ring;
398 /* Used by dp and fdi links */
399 struct intel_link_m_n {
407 void intel_link_compute_m_n(int bpp, int nlanes,
408 int pixel_clock, int link_clock,
409 struct intel_link_m_n *m_n);
411 /* Interface history:
414 * 1.2: Add Power Management
415 * 1.3: Add vblank support
416 * 1.4: Fix cmdbuffer path, add heap destroy
417 * 1.5: Add vblank pipe configuration
418 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
419 * - Support vertical blank on secondary display pipe
421 #define DRIVER_MAJOR 1
422 #define DRIVER_MINOR 6
423 #define DRIVER_PATCHLEVEL 0
425 #define WATCH_LISTS 0
427 struct opregion_header;
428 struct opregion_acpi;
429 struct opregion_swsci;
430 struct opregion_asle;
432 struct intel_opregion {
433 struct opregion_header *header;
434 struct opregion_acpi *acpi;
435 struct opregion_swsci *swsci;
436 u32 swsci_gbda_sub_functions;
437 u32 swsci_sbcb_sub_functions;
438 struct opregion_asle *asle;
443 struct work_struct asle_work;
445 #define OPREGION_SIZE (8*1024)
447 struct intel_overlay;
448 struct intel_overlay_error_state;
450 #define I915_FENCE_REG_NONE -1
451 #define I915_MAX_NUM_FENCES 32
452 /* 32 fences + sign bit for FENCE_REG_NONE */
453 #define I915_MAX_NUM_FENCE_BITS 6
455 struct drm_i915_fence_reg {
456 struct list_head lru_list;
457 struct drm_i915_gem_object *obj;
461 struct sdvo_device_mapping {
470 struct intel_display_error_state;
472 struct drm_i915_error_state {
481 /* Generic register state */
489 u32 error; /* gen6+ */
490 u32 err_int; /* gen7 */
491 u32 fault_data0; /* gen8, gen9 */
492 u32 fault_data1; /* gen8, gen9 */
498 u32 extra_instdone[I915_NUM_INSTDONE_REG];
499 u64 fence[I915_MAX_NUM_FENCES];
500 struct intel_overlay_error_state *overlay;
501 struct intel_display_error_state *display;
502 struct drm_i915_error_object *semaphore_obj;
504 struct drm_i915_error_ring {
506 /* Software tracked state */
509 enum intel_ring_hangcheck_action hangcheck_action;
512 /* our own tracking of ring head and tail */
517 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
536 u32 rc_psmi; /* sleep state */
537 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
539 struct drm_i915_error_object {
543 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
545 struct drm_i915_error_object *wa_ctx;
547 struct drm_i915_error_request {
562 char comm[TASK_COMM_LEN];
563 } ring[I915_NUM_ENGINES];
565 struct drm_i915_error_buffer {
568 u32 rseqno[I915_NUM_ENGINES], wseqno;
572 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
580 } **active_bo, **pinned_bo;
582 u32 *active_bo_count, *pinned_bo_count;
586 struct intel_connector;
587 struct intel_encoder;
588 struct intel_crtc_state;
589 struct intel_initial_plane_config;
594 struct drm_i915_display_funcs {
595 int (*get_display_clock_speed)(struct drm_device *dev);
596 int (*get_fifo_size)(struct drm_device *dev, int plane);
597 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
598 int (*compute_intermediate_wm)(struct drm_device *dev,
599 struct intel_crtc *intel_crtc,
600 struct intel_crtc_state *newstate);
601 void (*initial_watermarks)(struct intel_crtc_state *cstate);
602 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
603 int (*compute_global_watermarks)(struct drm_atomic_state *state);
604 void (*update_wm)(struct drm_crtc *crtc);
605 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
606 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
607 /* Returns the active state of the crtc, and if the crtc is active,
608 * fills out the pipe-config with the hw state. */
609 bool (*get_pipe_config)(struct intel_crtc *,
610 struct intel_crtc_state *);
611 void (*get_initial_plane_config)(struct intel_crtc *,
612 struct intel_initial_plane_config *);
613 int (*crtc_compute_clock)(struct intel_crtc *crtc,
614 struct intel_crtc_state *crtc_state);
615 void (*crtc_enable)(struct drm_crtc *crtc);
616 void (*crtc_disable)(struct drm_crtc *crtc);
617 void (*audio_codec_enable)(struct drm_connector *connector,
618 struct intel_encoder *encoder,
619 const struct drm_display_mode *adjusted_mode);
620 void (*audio_codec_disable)(struct intel_encoder *encoder);
621 void (*fdi_link_train)(struct drm_crtc *crtc);
622 void (*init_clock_gating)(struct drm_device *dev);
623 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
624 struct drm_framebuffer *fb,
625 struct drm_i915_gem_object *obj,
626 struct drm_i915_gem_request *req,
628 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
629 /* clock updates for mode set */
631 /* render clock increase/decrease */
632 /* display clock increase/decrease */
633 /* pll clock increase/decrease */
635 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
636 void (*load_luts)(struct drm_crtc_state *crtc_state);
639 enum forcewake_domain_id {
640 FW_DOMAIN_ID_RENDER = 0,
641 FW_DOMAIN_ID_BLITTER,
647 enum forcewake_domains {
648 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
649 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
650 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
651 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
656 #define FW_REG_READ (1)
657 #define FW_REG_WRITE (2)
659 enum forcewake_domains
660 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
661 i915_reg_t reg, unsigned int op);
663 struct intel_uncore_funcs {
664 void (*force_wake_get)(struct drm_i915_private *dev_priv,
665 enum forcewake_domains domains);
666 void (*force_wake_put)(struct drm_i915_private *dev_priv,
667 enum forcewake_domains domains);
669 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
670 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
671 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
672 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
674 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
675 uint8_t val, bool trace);
676 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
677 uint16_t val, bool trace);
678 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
679 uint32_t val, bool trace);
680 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
681 uint64_t val, bool trace);
684 struct intel_uncore {
685 spinlock_t lock; /** lock is also taken in irq contexts. */
687 struct intel_uncore_funcs funcs;
690 enum forcewake_domains fw_domains;
692 struct intel_uncore_forcewake_domain {
693 struct drm_i915_private *i915;
694 enum forcewake_domain_id id;
695 enum forcewake_domains mask;
697 struct hrtimer timer;
704 } fw_domain[FW_DOMAIN_ID_COUNT];
706 int unclaimed_mmio_check;
709 /* Iterate over initialised fw domains */
710 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
711 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
712 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
714 for_each_if ((mask__) & (domain__)->mask)
716 #define for_each_fw_domain(domain__, dev_priv__) \
717 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
719 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
720 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
721 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
724 struct work_struct work;
726 uint32_t *dmc_payload;
727 uint32_t dmc_fw_size;
730 i915_reg_t mmioaddr[8];
731 uint32_t mmiodata[8];
733 uint32_t allowed_dc_mask;
736 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
737 func(is_mobile) sep \
740 func(is_i945gm) sep \
742 func(need_gfx_hws) sep \
744 func(is_pineview) sep \
745 func(is_broadwater) sep \
746 func(is_crestline) sep \
747 func(is_ivybridge) sep \
748 func(is_valleyview) sep \
749 func(is_cherryview) sep \
750 func(is_haswell) sep \
751 func(is_broadwell) sep \
752 func(is_skylake) sep \
753 func(is_broxton) sep \
754 func(is_kabylake) sep \
755 func(is_preliminary) sep \
757 func(has_pipe_cxsr) sep \
758 func(has_hotplug) sep \
759 func(cursor_needs_physical) sep \
760 func(has_overlay) sep \
761 func(overlay_needs_physical) sep \
762 func(supports_tv) sep \
764 func(has_snoop) sep \
766 func(has_fpga_dbg) sep \
769 #define DEFINE_FLAG(name) u8 name:1
770 #define SEP_SEMICOLON ;
772 struct intel_device_info {
773 u32 display_mmio_offset;
776 u8 num_sprites[I915_MAX_PIPES];
779 u8 ring_mask; /* Rings supported by the HW */
780 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
781 /* Register offsets for the various display pipes and transcoders */
782 int pipe_offsets[I915_MAX_TRANSCODERS];
783 int trans_offsets[I915_MAX_TRANSCODERS];
784 int palette_offsets[I915_MAX_PIPES];
785 int cursor_offsets[I915_MAX_PIPES];
787 /* Slice/subslice/EU info */
790 u8 subslice_per_slice;
794 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
797 u8 has_subslice_pg:1;
801 u16 degamma_lut_size;
809 enum i915_cache_level {
811 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
812 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
813 caches, eg sampler/render caches, and the
814 large Last-Level-Cache. LLC is coherent with
815 the CPU, but L3 is only visible to the GPU. */
816 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
819 struct i915_ctx_hang_stats {
820 /* This context had batch pending when hang was declared */
821 unsigned batch_pending;
823 /* This context had batch active when hang was declared */
824 unsigned batch_active;
826 /* Time when this context was last blamed for a GPU reset */
827 unsigned long guilty_ts;
829 /* If the contexts causes a second GPU hang within this time,
830 * it is permanently banned from submitting any more work.
832 unsigned long ban_period_seconds;
834 /* This context is banned to submit more work */
838 /* This must match up with the value previously used for execbuf2.rsvd1. */
839 #define DEFAULT_CONTEXT_HANDLE 0
842 * struct i915_gem_context - as the name implies, represents a context.
843 * @ref: reference count.
844 * @user_handle: userspace tracking identity for this context.
845 * @remap_slice: l3 row remapping information.
846 * @flags: context specific flags:
847 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
848 * @file_priv: filp associated with this context (NULL for global default
850 * @hang_stats: information about the role of this context in possible GPU
852 * @ppgtt: virtual memory space used by this context.
853 * @legacy_hw_ctx: render context backing object and whether it is correctly
854 * initialized (legacy ring submission mechanism only).
855 * @link: link in the global list of contexts.
857 * Contexts are memory images used by the hardware to store copies of their
860 struct i915_gem_context {
862 struct drm_i915_private *i915;
863 struct drm_i915_file_private *file_priv;
864 struct i915_hw_ppgtt *ppgtt;
866 struct i915_ctx_hang_stats hang_stats;
868 /* Unique identifier for this context, used by the hw for tracking */
872 #define CONTEXT_NO_ZEROMAP (1<<0)
874 struct intel_context {
875 struct drm_i915_gem_object *state;
876 struct intel_ringbuffer *ringbuf;
877 struct i915_vma *lrc_vma;
878 uint32_t *lrc_reg_state;
882 } engine[I915_NUM_ENGINES];
885 struct atomic_notifier_head status_notifier;
886 bool execlists_force_single_submission;
888 struct list_head link;
902 /* This is always the inner lock when overlapping with struct_mutex and
903 * it's the outer lock when overlapping with stolen_lock. */
906 unsigned int possible_framebuffer_bits;
907 unsigned int busy_bits;
908 unsigned int visible_pipes_mask;
909 struct intel_crtc *crtc;
911 struct drm_mm_node compressed_fb;
912 struct drm_mm_node *compressed_llb;
919 struct intel_fbc_state_cache {
921 unsigned int mode_flags;
922 uint32_t hsw_bdw_pixel_rate;
926 unsigned int rotation;
934 uint32_t pixel_format;
937 unsigned int tiling_mode;
941 struct intel_fbc_reg_params {
945 unsigned int fence_y_offset;
950 uint32_t pixel_format;
958 struct intel_fbc_work {
960 u32 scheduled_vblank;
961 struct work_struct work;
964 const char *no_fbc_reason;
968 * HIGH_RR is the highest eDP panel refresh rate read from EDID
969 * LOW_RR is the lowest eDP panel refresh rate found from EDID
970 * parsing for same resolution.
972 enum drrs_refresh_rate_type {
975 DRRS_MAX_RR, /* RR count */
978 enum drrs_support_type {
979 DRRS_NOT_SUPPORTED = 0,
980 STATIC_DRRS_SUPPORT = 1,
981 SEAMLESS_DRRS_SUPPORT = 2
987 struct delayed_work work;
989 unsigned busy_frontbuffer_bits;
990 enum drrs_refresh_rate_type refresh_rate_type;
991 enum drrs_support_type type;
998 struct intel_dp *enabled;
1000 struct delayed_work work;
1001 unsigned busy_frontbuffer_bits;
1003 bool aux_frame_sync;
1008 PCH_NONE = 0, /* No PCH present */
1009 PCH_IBX, /* Ibexpeak PCH */
1010 PCH_CPT, /* Cougarpoint PCH */
1011 PCH_LPT, /* Lynxpoint PCH */
1012 PCH_SPT, /* Sunrisepoint PCH */
1016 enum intel_sbi_destination {
1021 #define QUIRK_PIPEA_FORCE (1<<0)
1022 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1023 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1024 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1025 #define QUIRK_PIPEB_FORCE (1<<4)
1026 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1029 struct intel_fbc_work;
1031 struct intel_gmbus {
1032 struct i2c_adapter adapter;
1033 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1036 i915_reg_t gpio_reg;
1037 struct i2c_algo_bit_data bit_algo;
1038 struct drm_i915_private *dev_priv;
1041 struct i915_suspend_saved_registers {
1044 u32 savePP_ON_DELAYS;
1045 u32 savePP_OFF_DELAYS;
1050 u32 saveFBC_CONTROL;
1051 u32 saveCACHE_MODE_0;
1052 u32 saveMI_ARB_STATE;
1056 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1057 u32 savePCH_PORT_HOTPLUG;
1061 struct vlv_s0ix_state {
1068 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1069 u32 media_max_req_count;
1070 u32 gfx_max_req_count;
1096 u32 rp_down_timeout;
1102 /* Display 1 CZ domain */
1107 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1109 /* GT SA CZ domain */
1116 /* Display 2 CZ domain */
1120 u32 clock_gate_dis2;
1123 struct intel_rps_ei {
1129 struct intel_gen6_power_mgmt {
1131 * work, interrupts_enabled and pm_iir are protected by
1132 * dev_priv->irq_lock
1134 struct work_struct work;
1135 bool interrupts_enabled;
1140 /* Frequencies are stored in potentially platform dependent multiples.
1141 * In other words, *_freq needs to be multiplied by X to be interesting.
1142 * Soft limits are those which are used for the dynamic reclocking done
1143 * by the driver (raise frequencies under heavy loads, and lower for
1144 * lighter loads). Hard limits are those imposed by the hardware.
1146 * A distinction is made for overclocking, which is never enabled by
1147 * default, and is considered to be above the hard limit if it's
1150 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1151 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1152 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1153 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1154 u8 min_freq; /* AKA RPn. Minimum frequency */
1155 u8 idle_freq; /* Frequency to request when we are idle */
1156 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1157 u8 rp1_freq; /* "less than" RP0 power/freqency */
1158 u8 rp0_freq; /* Non-overclocked max frequency. */
1159 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1161 u8 up_threshold; /* Current %busy required to uplock */
1162 u8 down_threshold; /* Current %busy required to downclock */
1165 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1167 spinlock_t client_lock;
1168 struct list_head clients;
1172 struct delayed_work delayed_resume_work;
1175 struct intel_rps_client semaphores, mmioflips;
1177 /* manual wa residency calculations */
1178 struct intel_rps_ei up_ei, down_ei;
1181 * Protects RPS/RC6 register access and PCU communication.
1182 * Must be taken after struct_mutex if nested. Note that
1183 * this lock may be held for long periods of time when
1184 * talking to hw - so only take it when talking to hw!
1186 struct mutex hw_lock;
1189 /* defined intel_pm.c */
1190 extern spinlock_t mchdev_lock;
1192 struct intel_ilk_power_mgmt {
1200 unsigned long last_time1;
1201 unsigned long chipset_power;
1204 unsigned long gfx_power;
1211 struct drm_i915_private;
1212 struct i915_power_well;
1214 struct i915_power_well_ops {
1216 * Synchronize the well's hw state to match the current sw state, for
1217 * example enable/disable it based on the current refcount. Called
1218 * during driver init and resume time, possibly after first calling
1219 * the enable/disable handlers.
1221 void (*sync_hw)(struct drm_i915_private *dev_priv,
1222 struct i915_power_well *power_well);
1224 * Enable the well and resources that depend on it (for example
1225 * interrupts located on the well). Called after the 0->1 refcount
1228 void (*enable)(struct drm_i915_private *dev_priv,
1229 struct i915_power_well *power_well);
1231 * Disable the well and resources that depend on it. Called after
1232 * the 1->0 refcount transition.
1234 void (*disable)(struct drm_i915_private *dev_priv,
1235 struct i915_power_well *power_well);
1236 /* Returns the hw enabled state. */
1237 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1238 struct i915_power_well *power_well);
1241 /* Power well structure for haswell */
1242 struct i915_power_well {
1245 /* power well enable/disable usage count */
1247 /* cached hw enabled state */
1249 unsigned long domains;
1251 const struct i915_power_well_ops *ops;
1254 struct i915_power_domains {
1256 * Power wells needed for initialization at driver init and suspend
1257 * time are on. They are kept on until after the first modeset.
1261 int power_well_count;
1264 int domain_use_count[POWER_DOMAIN_NUM];
1265 struct i915_power_well *power_wells;
1268 #define MAX_L3_SLICES 2
1269 struct intel_l3_parity {
1270 u32 *remap_info[MAX_L3_SLICES];
1271 struct work_struct error_work;
1275 struct i915_gem_mm {
1276 /** Memory allocator for GTT stolen memory */
1277 struct drm_mm stolen;
1278 /** Protects the usage of the GTT stolen memory allocator. This is
1279 * always the inner lock when overlapping with struct_mutex. */
1280 struct mutex stolen_lock;
1282 /** List of all objects in gtt_space. Used to restore gtt
1283 * mappings on resume */
1284 struct list_head bound_list;
1286 * List of objects which are not bound to the GTT (thus
1287 * are idle and not used by the GPU) but still have
1288 * (presumably uncached) pages still attached.
1290 struct list_head unbound_list;
1292 /** Usable portion of the GTT for GEM */
1293 unsigned long stolen_base; /* limited to low memory (32-bit) */
1295 /** PPGTT used for aliasing the PPGTT with the GTT */
1296 struct i915_hw_ppgtt *aliasing_ppgtt;
1298 struct notifier_block oom_notifier;
1299 struct notifier_block vmap_notifier;
1300 struct shrinker shrinker;
1301 bool shrinker_no_lock_stealing;
1303 /** LRU list of objects with fence regs on them. */
1304 struct list_head fence_list;
1307 * We leave the user IRQ off as much as possible,
1308 * but this means that requests will finish and never
1309 * be retired once the system goes idle. Set a timer to
1310 * fire periodically while the ring is running. When it
1311 * fires, go retire requests.
1313 struct delayed_work retire_work;
1316 * When we detect an idle GPU, we want to turn on
1317 * powersaving features. So once we see that there
1318 * are no more requests outstanding and no more
1319 * arrive within a small period of time, we fire
1320 * off the idle_work.
1322 struct delayed_work idle_work;
1325 * Are we in a non-interruptible section of code like
1331 * Is the GPU currently considered idle, or busy executing userspace
1332 * requests? Whilst idle, we attempt to power down the hardware and
1333 * display clocks. In order to reduce the effect on performance, there
1334 * is a slight delay before we do so.
1338 /* the indicator for dispatch video commands on two BSD rings */
1339 unsigned int bsd_ring_dispatch_index;
1341 /** Bit 6 swizzling required for X tiling */
1342 uint32_t bit_6_swizzle_x;
1343 /** Bit 6 swizzling required for Y tiling */
1344 uint32_t bit_6_swizzle_y;
1346 /* accounting, useful for userland debugging */
1347 spinlock_t object_stat_lock;
1348 size_t object_memory;
1352 struct drm_i915_error_state_buf {
1353 struct drm_i915_private *i915;
1362 struct i915_error_state_file_priv {
1363 struct drm_device *dev;
1364 struct drm_i915_error_state *error;
1367 struct i915_gpu_error {
1368 /* For hangcheck timer */
1369 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1370 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1371 /* Hang gpu twice in this window and your context gets banned */
1372 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1374 struct workqueue_struct *hangcheck_wq;
1375 struct delayed_work hangcheck_work;
1377 /* For reset and error_state handling. */
1379 /* Protected by the above dev->gpu_error.lock. */
1380 struct drm_i915_error_state *first_error;
1382 unsigned long missed_irq_rings;
1385 * State variable controlling the reset flow and count
1387 * This is a counter which gets incremented when reset is triggered,
1388 * and again when reset has been handled. So odd values (lowest bit set)
1389 * means that reset is in progress and even values that
1390 * (reset_counter >> 1):th reset was successfully completed.
1392 * If reset is not completed succesfully, the I915_WEDGE bit is
1393 * set meaning that hardware is terminally sour and there is no
1394 * recovery. All waiters on the reset_queue will be woken when
1397 * This counter is used by the wait_seqno code to notice that reset
1398 * event happened and it needs to restart the entire ioctl (since most
1399 * likely the seqno it waited for won't ever signal anytime soon).
1401 * This is important for lock-free wait paths, where no contended lock
1402 * naturally enforces the correct ordering between the bail-out of the
1403 * waiter and the gpu reset work code.
1405 atomic_t reset_counter;
1407 #define I915_RESET_IN_PROGRESS_FLAG 1
1408 #define I915_WEDGED (1 << 31)
1411 * Waitqueue to signal when the reset has completed. Used by clients
1412 * that wait for dev_priv->mm.wedged to settle.
1414 wait_queue_head_t reset_queue;
1416 /* Userspace knobs for gpu hang simulation;
1417 * combines both a ring mask, and extra flags
1420 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1421 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1423 /* For missed irq/seqno simulation. */
1424 unsigned int test_irq_rings;
1427 enum modeset_restore {
1428 MODESET_ON_LID_OPEN,
1433 #define DP_AUX_A 0x40
1434 #define DP_AUX_B 0x10
1435 #define DP_AUX_C 0x20
1436 #define DP_AUX_D 0x30
1438 #define DDC_PIN_B 0x05
1439 #define DDC_PIN_C 0x04
1440 #define DDC_PIN_D 0x06
1442 struct ddi_vbt_port_info {
1444 * This is an index in the HDMI/DVI DDI buffer translation table.
1445 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1446 * populate this field.
1448 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1449 uint8_t hdmi_level_shift;
1451 uint8_t supports_dvi:1;
1452 uint8_t supports_hdmi:1;
1453 uint8_t supports_dp:1;
1455 uint8_t alternate_aux_channel;
1456 uint8_t alternate_ddc_pin;
1458 uint8_t dp_boost_level;
1459 uint8_t hdmi_boost_level;
1462 enum psr_lines_to_wait {
1463 PSR_0_LINES_TO_WAIT = 0,
1465 PSR_4_LINES_TO_WAIT,
1469 struct intel_vbt_data {
1470 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1471 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1474 unsigned int int_tv_support:1;
1475 unsigned int lvds_dither:1;
1476 unsigned int lvds_vbt:1;
1477 unsigned int int_crt_support:1;
1478 unsigned int lvds_use_ssc:1;
1479 unsigned int display_clock_mode:1;
1480 unsigned int fdi_rx_polarity_inverted:1;
1481 unsigned int panel_type:4;
1483 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1485 enum drrs_support_type drrs_type;
1496 struct edp_power_seq pps;
1501 bool require_aux_wakeup;
1503 enum psr_lines_to_wait lines_to_wait;
1504 int tp1_wakeup_time;
1505 int tp2_tp3_wakeup_time;
1511 bool active_low_pwm;
1512 u8 min_brightness; /* min_brightness/255 of max */
1513 enum intel_backlight_type type;
1519 struct mipi_config *config;
1520 struct mipi_pps_data *pps;
1524 const u8 *sequence[MIPI_SEQ_MAX];
1530 union child_device_config *child_dev;
1532 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1533 struct sdvo_device_mapping sdvo_mappings[2];
1536 enum intel_ddb_partitioning {
1538 INTEL_DDB_PART_5_6, /* IVB+ */
1541 struct intel_wm_level {
1549 struct ilk_wm_values {
1550 uint32_t wm_pipe[3];
1552 uint32_t wm_lp_spr[3];
1553 uint32_t wm_linetime[3];
1555 enum intel_ddb_partitioning partitioning;
1558 struct vlv_pipe_wm {
1569 struct vlv_wm_values {
1570 struct vlv_pipe_wm pipe[3];
1571 struct vlv_sr_wm sr;
1581 struct skl_ddb_entry {
1582 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1585 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1587 return entry->end - entry->start;
1590 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1591 const struct skl_ddb_entry *e2)
1593 if (e1->start == e2->start && e1->end == e2->end)
1599 struct skl_ddb_allocation {
1600 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1601 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1602 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1605 struct skl_wm_values {
1606 unsigned dirty_pipes;
1607 struct skl_ddb_allocation ddb;
1608 uint32_t wm_linetime[I915_MAX_PIPES];
1609 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1610 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1613 struct skl_wm_level {
1614 bool plane_en[I915_MAX_PLANES];
1615 uint16_t plane_res_b[I915_MAX_PLANES];
1616 uint8_t plane_res_l[I915_MAX_PLANES];
1620 * This struct helps tracking the state needed for runtime PM, which puts the
1621 * device in PCI D3 state. Notice that when this happens, nothing on the
1622 * graphics device works, even register access, so we don't get interrupts nor
1625 * Every piece of our code that needs to actually touch the hardware needs to
1626 * either call intel_runtime_pm_get or call intel_display_power_get with the
1627 * appropriate power domain.
1629 * Our driver uses the autosuspend delay feature, which means we'll only really
1630 * suspend if we stay with zero refcount for a certain amount of time. The
1631 * default value is currently very conservative (see intel_runtime_pm_enable), but
1632 * it can be changed with the standard runtime PM files from sysfs.
1634 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1635 * goes back to false exactly before we reenable the IRQs. We use this variable
1636 * to check if someone is trying to enable/disable IRQs while they're supposed
1637 * to be disabled. This shouldn't happen and we'll print some error messages in
1640 * For more, read the Documentation/power/runtime_pm.txt.
1642 struct i915_runtime_pm {
1643 atomic_t wakeref_count;
1644 atomic_t atomic_seq;
1649 enum intel_pipe_crc_source {
1650 INTEL_PIPE_CRC_SOURCE_NONE,
1651 INTEL_PIPE_CRC_SOURCE_PLANE1,
1652 INTEL_PIPE_CRC_SOURCE_PLANE2,
1653 INTEL_PIPE_CRC_SOURCE_PF,
1654 INTEL_PIPE_CRC_SOURCE_PIPE,
1655 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1656 INTEL_PIPE_CRC_SOURCE_TV,
1657 INTEL_PIPE_CRC_SOURCE_DP_B,
1658 INTEL_PIPE_CRC_SOURCE_DP_C,
1659 INTEL_PIPE_CRC_SOURCE_DP_D,
1660 INTEL_PIPE_CRC_SOURCE_AUTO,
1661 INTEL_PIPE_CRC_SOURCE_MAX,
1664 struct intel_pipe_crc_entry {
1669 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1670 struct intel_pipe_crc {
1672 bool opened; /* exclusive access to the result file */
1673 struct intel_pipe_crc_entry *entries;
1674 enum intel_pipe_crc_source source;
1676 wait_queue_head_t wq;
1679 struct i915_frontbuffer_tracking {
1683 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1690 struct i915_wa_reg {
1693 /* bitmask representing WA bits */
1698 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1699 * allowing it for RCS as we don't foresee any requirement of having
1700 * a whitelist for other engines. When it is really required for
1701 * other engines then the limit need to be increased.
1703 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1705 struct i915_workarounds {
1706 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1708 u32 hw_whitelist_count[I915_NUM_ENGINES];
1711 struct i915_virtual_gpu {
1715 struct i915_execbuffer_params {
1716 struct drm_device *dev;
1717 struct drm_file *file;
1718 uint32_t dispatch_flags;
1719 uint32_t args_batch_start_offset;
1720 uint64_t batch_obj_vm_offset;
1721 struct intel_engine_cs *engine;
1722 struct drm_i915_gem_object *batch_obj;
1723 struct i915_gem_context *ctx;
1724 struct drm_i915_gem_request *request;
1727 /* used in computing the new watermarks state */
1728 struct intel_wm_config {
1729 unsigned int num_pipes_active;
1730 bool sprites_enabled;
1731 bool sprites_scaled;
1734 struct drm_i915_private {
1735 struct drm_device *dev;
1736 struct kmem_cache *objects;
1737 struct kmem_cache *vmas;
1738 struct kmem_cache *requests;
1740 const struct intel_device_info info;
1742 int relative_constants_mode;
1746 struct intel_uncore uncore;
1748 struct i915_virtual_gpu vgpu;
1750 struct intel_gvt gvt;
1752 struct intel_guc guc;
1754 struct intel_csr csr;
1756 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1758 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1759 * controller on different i2c buses. */
1760 struct mutex gmbus_mutex;
1763 * Base address of the gmbus and gpio block.
1765 uint32_t gpio_mmio_base;
1767 /* MMIO base address for MIPI regs */
1768 uint32_t mipi_mmio_base;
1770 uint32_t psr_mmio_base;
1772 wait_queue_head_t gmbus_wait_queue;
1774 struct pci_dev *bridge_dev;
1775 struct i915_gem_context *kernel_context;
1776 struct intel_engine_cs engine[I915_NUM_ENGINES];
1777 struct drm_i915_gem_object *semaphore_obj;
1778 uint32_t last_seqno, next_seqno;
1780 struct drm_dma_handle *status_page_dmah;
1781 struct resource mch_res;
1783 /* protects the irq masks */
1784 spinlock_t irq_lock;
1786 /* protects the mmio flip data */
1787 spinlock_t mmio_flip_lock;
1789 bool display_irqs_enabled;
1791 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1792 struct pm_qos_request pm_qos;
1794 /* Sideband mailbox protection */
1795 struct mutex sb_lock;
1797 /** Cached value of IMR to avoid reads in updating the bitfield */
1800 u32 de_irq_mask[I915_MAX_PIPES];
1805 u32 pipestat_irq_mask[I915_MAX_PIPES];
1807 struct i915_hotplug hotplug;
1808 struct intel_fbc fbc;
1809 struct i915_drrs drrs;
1810 struct intel_opregion opregion;
1811 struct intel_vbt_data vbt;
1813 bool preserve_bios_swizzle;
1816 struct intel_overlay *overlay;
1818 /* backlight registers and fields in struct intel_panel */
1819 struct mutex backlight_lock;
1822 bool no_aux_handshake;
1824 /* protects panel power sequencer state */
1825 struct mutex pps_mutex;
1827 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1828 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1830 unsigned int fsb_freq, mem_freq, is_ddr3;
1831 unsigned int skl_preferred_vco_freq;
1832 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1833 unsigned int max_dotclk_freq;
1834 unsigned int rawclk_freq;
1835 unsigned int hpll_freq;
1836 unsigned int czclk_freq;
1839 unsigned int vco, ref;
1843 * wq - Driver workqueue for GEM.
1845 * NOTE: Work items scheduled here are not allowed to grab any modeset
1846 * locks, for otherwise the flushing done in the pageflip code will
1847 * result in deadlocks.
1849 struct workqueue_struct *wq;
1851 /* Display functions */
1852 struct drm_i915_display_funcs display;
1854 /* PCH chipset type */
1855 enum intel_pch pch_type;
1856 unsigned short pch_id;
1858 unsigned long quirks;
1860 enum modeset_restore modeset_restore;
1861 struct mutex modeset_restore_lock;
1862 struct drm_atomic_state *modeset_restore_state;
1864 struct list_head vm_list; /* Global list of all address spaces */
1865 struct i915_ggtt ggtt; /* VM representing the global address space */
1867 struct i915_gem_mm mm;
1868 DECLARE_HASHTABLE(mm_structs, 7);
1869 struct mutex mm_lock;
1871 /* The hw wants to have a stable context identifier for the lifetime
1872 * of the context (for OA, PASID, faults, etc). This is limited
1873 * in execlists to 21 bits.
1875 struct ida context_hw_ida;
1876 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1878 /* Kernel Modesetting */
1880 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1881 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1882 wait_queue_head_t pending_flip_queue;
1884 #ifdef CONFIG_DEBUG_FS
1885 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1888 /* dpll and cdclk state is protected by connection_mutex */
1889 int num_shared_dpll;
1890 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1891 const struct intel_dpll_mgr *dpll_mgr;
1894 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1895 * Must be global rather than per dpll, because on some platforms
1896 * plls share registers.
1898 struct mutex dpll_lock;
1900 unsigned int active_crtcs;
1901 unsigned int min_pixclk[I915_MAX_PIPES];
1903 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1905 struct i915_workarounds workarounds;
1907 struct i915_frontbuffer_tracking fb_tracking;
1911 bool mchbar_need_disable;
1913 struct intel_l3_parity l3_parity;
1915 /* Cannot be determined by PCIID. You must always read a register. */
1918 /* gen6+ rps state */
1919 struct intel_gen6_power_mgmt rps;
1921 /* ilk-only ips/rps state. Everything in here is protected by the global
1922 * mchdev_lock in intel_pm.c */
1923 struct intel_ilk_power_mgmt ips;
1925 struct i915_power_domains power_domains;
1927 struct i915_psr psr;
1929 struct i915_gpu_error gpu_error;
1931 struct drm_i915_gem_object *vlv_pctx;
1933 #ifdef CONFIG_DRM_FBDEV_EMULATION
1934 /* list of fbdev register on this device */
1935 struct intel_fbdev *fbdev;
1936 struct work_struct fbdev_suspend_work;
1939 struct drm_property *broadcast_rgb_property;
1940 struct drm_property *force_audio_property;
1942 /* hda/i915 audio component */
1943 struct i915_audio_component *audio_component;
1944 bool audio_component_registered;
1946 * av_mutex - mutex for audio/video sync
1949 struct mutex av_mutex;
1951 uint32_t hw_context_size;
1952 struct list_head context_list;
1956 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1957 u32 chv_phy_control;
1959 * Shadows for CHV DPLL_MD regs to keep the state
1960 * checker somewhat working in the presence hardware
1961 * crappiness (can't read out DPLL_MD for pipes B & C).
1963 u32 chv_dpll_md[I915_MAX_PIPES];
1967 bool suspended_to_idle;
1968 struct i915_suspend_saved_registers regfile;
1969 struct vlv_s0ix_state vlv_s0ix_state;
1973 * Raw watermark latency values:
1974 * in 0.1us units for WM0,
1975 * in 0.5us units for WM1+.
1978 uint16_t pri_latency[5];
1980 uint16_t spr_latency[5];
1982 uint16_t cur_latency[5];
1984 * Raw watermark memory latency values
1985 * for SKL for all 8 levels
1988 uint16_t skl_latency[8];
1991 * The skl_wm_values structure is a bit too big for stack
1992 * allocation, so we keep the staging struct where we store
1993 * intermediate results here instead.
1995 struct skl_wm_values skl_results;
1997 /* current hardware state */
1999 struct ilk_wm_values hw;
2000 struct skl_wm_values skl_hw;
2001 struct vlv_wm_values vlv;
2007 * Should be held around atomic WM register writing; also
2008 * protects * intel_crtc->wm.active and
2009 * cstate->wm.need_postvbl_update.
2011 struct mutex wm_mutex;
2014 * Set during HW readout of watermarks/DDB. Some platforms
2015 * need to know when we're still using BIOS-provided values
2016 * (which we don't fully trust).
2018 bool distrust_bios_wm;
2021 struct i915_runtime_pm pm;
2023 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2025 int (*execbuf_submit)(struct i915_execbuffer_params *params,
2026 struct drm_i915_gem_execbuffer2 *args,
2027 struct list_head *vmas);
2028 int (*init_engines)(struct drm_device *dev);
2029 void (*cleanup_engine)(struct intel_engine_cs *engine);
2030 void (*stop_engine)(struct intel_engine_cs *engine);
2033 /* perform PHY state sanity checks? */
2034 bool chv_phy_assert[2];
2036 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
2039 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2040 * will be rejected. Instead look for a better place.
2044 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2046 return dev->dev_private;
2049 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
2051 return to_i915(dev_get_drvdata(dev));
2054 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2056 return container_of(guc, struct drm_i915_private, guc);
2059 /* Simple iterator over all initialised engines */
2060 #define for_each_engine(engine__, dev_priv__) \
2061 for ((engine__) = &(dev_priv__)->engine[0]; \
2062 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2064 for_each_if (intel_engine_initialized(engine__))
2066 /* Iterator with engine_id */
2067 #define for_each_engine_id(engine__, dev_priv__, id__) \
2068 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2069 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2071 for_each_if (((id__) = (engine__)->id, \
2072 intel_engine_initialized(engine__)))
2074 /* Iterator over subset of engines selected by mask */
2075 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2076 for ((engine__) = &(dev_priv__)->engine[0]; \
2077 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2079 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2080 intel_engine_initialized(engine__))
2082 enum hdmi_force_audio {
2083 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2084 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2085 HDMI_AUDIO_AUTO, /* trust EDID */
2086 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2089 #define I915_GTT_OFFSET_NONE ((u32)-1)
2091 struct drm_i915_gem_object_ops {
2093 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2095 /* Interface between the GEM object and its backing storage.
2096 * get_pages() is called once prior to the use of the associated set
2097 * of pages before to binding them into the GTT, and put_pages() is
2098 * called after we no longer need them. As we expect there to be
2099 * associated cost with migrating pages between the backing storage
2100 * and making them available for the GPU (e.g. clflush), we may hold
2101 * onto the pages after they are no longer referenced by the GPU
2102 * in case they may be used again shortly (for example migrating the
2103 * pages to a different memory domain within the GTT). put_pages()
2104 * will therefore most likely be called when the object itself is
2105 * being released or under memory pressure (where we attempt to
2106 * reap pages for the shrinker).
2108 int (*get_pages)(struct drm_i915_gem_object *);
2109 void (*put_pages)(struct drm_i915_gem_object *);
2111 int (*dmabuf_export)(struct drm_i915_gem_object *);
2112 void (*release)(struct drm_i915_gem_object *);
2116 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2117 * considered to be the frontbuffer for the given plane interface-wise. This
2118 * doesn't mean that the hw necessarily already scans it out, but that any
2119 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2121 * We have one bit per pipe and per scanout plane type.
2123 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2124 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2125 #define INTEL_FRONTBUFFER_BITS \
2126 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2127 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2128 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2129 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2130 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2131 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2132 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2133 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2134 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2135 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2136 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2138 struct drm_i915_gem_object {
2139 struct drm_gem_object base;
2141 const struct drm_i915_gem_object_ops *ops;
2143 /** List of VMAs backed by this object */
2144 struct list_head vma_list;
2146 /** Stolen memory for this object, instead of being backed by shmem. */
2147 struct drm_mm_node *stolen;
2148 struct list_head global_list;
2150 struct list_head engine_list[I915_NUM_ENGINES];
2151 /** Used in execbuf to temporarily hold a ref */
2152 struct list_head obj_exec_link;
2154 struct list_head batch_pool_link;
2157 * This is set if the object is on the active lists (has pending
2158 * rendering and so a non-zero seqno), and is not set if it i s on
2159 * inactive (ready to be unbound) list.
2161 unsigned int active:I915_NUM_ENGINES;
2164 * This is set if the object has been written to since last bound
2167 unsigned int dirty:1;
2170 * Fence register bits (if any) for this object. Will be set
2171 * as needed when mapped into the GTT.
2172 * Protected by dev->struct_mutex.
2174 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2177 * Advice: are the backing pages purgeable?
2179 unsigned int madv:2;
2182 * Current tiling mode for the object.
2184 unsigned int tiling_mode:2;
2186 * Whether the tiling parameters for the currently associated fence
2187 * register have changed. Note that for the purposes of tracking
2188 * tiling changes we also treat the unfenced register, the register
2189 * slot that the object occupies whilst it executes a fenced
2190 * command (such as BLT on gen2/3), as a "fence".
2192 unsigned int fence_dirty:1;
2195 * Is the object at the current location in the gtt mappable and
2196 * fenceable? Used to avoid costly recalculations.
2198 unsigned int map_and_fenceable:1;
2201 * Whether the current gtt mapping needs to be mappable (and isn't just
2202 * mappable by accident). Track pin and fault separate for a more
2203 * accurate mappable working set.
2205 unsigned int fault_mappable:1;
2208 * Is the object to be mapped as read-only to the GPU
2209 * Only honoured if hardware has relevant pte bit
2211 unsigned long gt_ro:1;
2212 unsigned int cache_level:3;
2213 unsigned int cache_dirty:1;
2215 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2217 unsigned int has_wc_mmap;
2218 unsigned int pin_display;
2220 struct sg_table *pages;
2221 int pages_pin_count;
2223 struct scatterlist *sg;
2228 /** Breadcrumb of last rendering to the buffer.
2229 * There can only be one writer, but we allow for multiple readers.
2230 * If there is a writer that necessarily implies that all other
2231 * read requests are complete - but we may only be lazily clearing
2232 * the read requests. A read request is naturally the most recent
2233 * request on a ring, so we may have two different write and read
2234 * requests on one ring where the write request is older than the
2235 * read request. This allows for the CPU to read from an active
2236 * buffer by only waiting for the write to complete.
2238 struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES];
2239 struct drm_i915_gem_request *last_write_req;
2240 /** Breadcrumb of last fenced GPU access to the buffer. */
2241 struct drm_i915_gem_request *last_fenced_req;
2243 /** Current tiling stride for the object, if it's tiled. */
2246 /** References from framebuffers, locks out tiling changes. */
2247 unsigned long framebuffer_references;
2249 /** Record of address bit 17 of each page at last unbind. */
2250 unsigned long *bit_17;
2253 /** for phy allocated objects */
2254 struct drm_dma_handle *phys_handle;
2256 struct i915_gem_userptr {
2258 unsigned read_only :1;
2259 unsigned workers :4;
2260 #define I915_GEM_USERPTR_MAX_WORKERS 15
2262 struct i915_mm_struct *mm;
2263 struct i915_mmu_object *mmu_object;
2264 struct work_struct *work;
2268 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2271 i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
2273 return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
2277 * Optimised SGL iterator for GEM objects
2279 static __always_inline struct sgt_iter {
2280 struct scatterlist *sgp;
2287 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2288 struct sgt_iter s = { .sgp = sgl };
2291 s.max = s.curr = s.sgp->offset;
2292 s.max += s.sgp->length;
2294 s.dma = sg_dma_address(s.sgp);
2296 s.pfn = page_to_pfn(sg_page(s.sgp));
2303 * __sg_next - return the next scatterlist entry in a list
2304 * @sg: The current sg entry
2307 * If the entry is the last, return NULL; otherwise, step to the next
2308 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2309 * otherwise just return the pointer to the current element.
2311 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2313 #ifdef CONFIG_DEBUG_SG
2314 BUG_ON(sg->sg_magic != SG_MAGIC);
2316 return sg_is_last(sg) ? NULL :
2317 likely(!sg_is_chain(++sg)) ? sg :
2322 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2323 * @__dmap: DMA address (output)
2324 * @__iter: 'struct sgt_iter' (iterator state, internal)
2325 * @__sgt: sg_table to iterate over (input)
2327 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2328 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2329 ((__dmap) = (__iter).dma + (__iter).curr); \
2330 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2331 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2334 * for_each_sgt_page - iterate over the pages of the given sg_table
2335 * @__pp: page pointer (output)
2336 * @__iter: 'struct sgt_iter' (iterator state, internal)
2337 * @__sgt: sg_table to iterate over (input)
2339 #define for_each_sgt_page(__pp, __iter, __sgt) \
2340 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2341 ((__pp) = (__iter).pfn == 0 ? NULL : \
2342 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2343 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2344 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2347 * Request queue structure.
2349 * The request queue allows us to note sequence numbers that have been emitted
2350 * and may be associated with active buffers to be retired.
2352 * By keeping this list, we can avoid having to do questionable sequence
2353 * number comparisons on buffer last_read|write_seqno. It also allows an
2354 * emission time to be associated with the request for tracking how far ahead
2355 * of the GPU the submission is.
2357 * The requests are reference counted, so upon creation they should have an
2358 * initial reference taken using kref_init
2360 struct drm_i915_gem_request {
2363 /** On Which ring this request was generated */
2364 struct drm_i915_private *i915;
2365 struct intel_engine_cs *engine;
2366 unsigned reset_counter;
2368 /** GEM sequence number associated with the previous request,
2369 * when the HWS breadcrumb is equal to this the GPU is processing
2374 /** GEM sequence number associated with this request,
2375 * when the HWS breadcrumb is equal or greater than this the GPU
2376 * has finished processing this request.
2380 /** Position in the ringbuffer of the start of the request */
2384 * Position in the ringbuffer of the start of the postfix.
2385 * This is required to calculate the maximum available ringbuffer
2386 * space without overwriting the postfix.
2390 /** Position in the ringbuffer of the end of the whole request */
2393 /** Preallocate space in the ringbuffer for the emitting the request */
2397 * Context and ring buffer related to this request
2398 * Contexts are refcounted, so when this request is associated with a
2399 * context, we must increment the context's refcount, to guarantee that
2400 * it persists while any request is linked to it. Requests themselves
2401 * are also refcounted, so the request will only be freed when the last
2402 * reference to it is dismissed, and the code in
2403 * i915_gem_request_free() will then decrement the refcount on the
2406 struct i915_gem_context *ctx;
2407 struct intel_ringbuffer *ringbuf;
2410 * Context related to the previous request.
2411 * As the contexts are accessed by the hardware until the switch is
2412 * completed to a new context, the hardware may still be writing
2413 * to the context object after the breadcrumb is visible. We must
2414 * not unpin/unbind/prune that object whilst still active and so
2415 * we keep the previous context pinned until the following (this)
2416 * request is retired.
2418 struct i915_gem_context *previous_context;
2420 /** Batch buffer related to this request if any (used for
2421 error state dump only) */
2422 struct drm_i915_gem_object *batch_obj;
2424 /** Time at which this request was emitted, in jiffies. */
2425 unsigned long emitted_jiffies;
2427 /** global list entry for this request */
2428 struct list_head list;
2430 struct drm_i915_file_private *file_priv;
2431 /** file_priv list entry for this request */
2432 struct list_head client_list;
2434 /** process identifier submitting this request */
2438 * The ELSP only accepts two elements at a time, so we queue
2439 * context/tail pairs on a given queue (ring->execlist_queue) until the
2440 * hardware is available. The queue serves a double purpose: we also use
2441 * it to keep track of the up to 2 contexts currently in the hardware
2442 * (usually one in execution and the other queued up by the GPU): We
2443 * only remove elements from the head of the queue when the hardware
2444 * informs us that an element has been completed.
2446 * All accesses to the queue are mediated by a spinlock
2447 * (ring->execlist_lock).
2450 /** Execlist link in the submission queue.*/
2451 struct list_head execlist_link;
2453 /** Execlists no. of times this request has been sent to the ELSP */
2456 /** Execlists context hardware id. */
2460 struct drm_i915_gem_request * __must_check
2461 i915_gem_request_alloc(struct intel_engine_cs *engine,
2462 struct i915_gem_context *ctx);
2463 void i915_gem_request_free(struct kref *req_ref);
2464 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2465 struct drm_file *file);
2467 static inline uint32_t
2468 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2470 return req ? req->seqno : 0;
2473 static inline struct intel_engine_cs *
2474 i915_gem_request_get_engine(struct drm_i915_gem_request *req)
2476 return req ? req->engine : NULL;
2479 static inline struct drm_i915_gem_request *
2480 i915_gem_request_reference(struct drm_i915_gem_request *req)
2483 kref_get(&req->ref);
2488 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2490 kref_put(&req->ref, i915_gem_request_free);
2493 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2494 struct drm_i915_gem_request *src)
2497 i915_gem_request_reference(src);
2500 i915_gem_request_unreference(*pdst);
2506 * XXX: i915_gem_request_completed should be here but currently needs the
2507 * definition of i915_seqno_passed() which is below. It will be moved in
2508 * a later patch when the call to i915_seqno_passed() is obsoleted...
2512 * A command that requires special handling by the command parser.
2514 struct drm_i915_cmd_descriptor {
2516 * Flags describing how the command parser processes the command.
2518 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2519 * a length mask if not set
2520 * CMD_DESC_SKIP: The command is allowed but does not follow the
2521 * standard length encoding for the opcode range in
2523 * CMD_DESC_REJECT: The command is never allowed
2524 * CMD_DESC_REGISTER: The command should be checked against the
2525 * register whitelist for the appropriate ring
2526 * CMD_DESC_MASTER: The command is allowed if the submitting process
2530 #define CMD_DESC_FIXED (1<<0)
2531 #define CMD_DESC_SKIP (1<<1)
2532 #define CMD_DESC_REJECT (1<<2)
2533 #define CMD_DESC_REGISTER (1<<3)
2534 #define CMD_DESC_BITMASK (1<<4)
2535 #define CMD_DESC_MASTER (1<<5)
2538 * The command's unique identification bits and the bitmask to get them.
2539 * This isn't strictly the opcode field as defined in the spec and may
2540 * also include type, subtype, and/or subop fields.
2548 * The command's length. The command is either fixed length (i.e. does
2549 * not include a length field) or has a length field mask. The flag
2550 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2551 * a length mask. All command entries in a command table must include
2552 * length information.
2560 * Describes where to find a register address in the command to check
2561 * against the ring's register whitelist. Only valid if flags has the
2562 * CMD_DESC_REGISTER bit set.
2564 * A non-zero step value implies that the command may access multiple
2565 * registers in sequence (e.g. LRI), in that case step gives the
2566 * distance in dwords between individual offset fields.
2574 #define MAX_CMD_DESC_BITMASKS 3
2576 * Describes command checks where a particular dword is masked and
2577 * compared against an expected value. If the command does not match
2578 * the expected value, the parser rejects it. Only valid if flags has
2579 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2582 * If the check specifies a non-zero condition_mask then the parser
2583 * only performs the check when the bits specified by condition_mask
2590 u32 condition_offset;
2592 } bits[MAX_CMD_DESC_BITMASKS];
2596 * A table of commands requiring special handling by the command parser.
2598 * Each ring has an array of tables. Each table consists of an array of command
2599 * descriptors, which must be sorted with command opcodes in ascending order.
2601 struct drm_i915_cmd_table {
2602 const struct drm_i915_cmd_descriptor *table;
2606 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2607 #define __I915__(p) ({ \
2608 struct drm_i915_private *__p; \
2609 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2610 __p = (struct drm_i915_private *)p; \
2611 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2612 __p = to_i915((struct drm_device *)p); \
2617 #define INTEL_INFO(p) (&__I915__(p)->info)
2618 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2619 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2621 #define REVID_FOREVER 0xff
2622 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2624 #define GEN_FOREVER (0)
2626 * Returns true if Gen is in inclusive range [Start, End].
2628 * Use GEN_FOREVER for unbound start and or end.
2630 #define IS_GEN(p, s, e) ({ \
2631 unsigned int __s = (s), __e = (e); \
2632 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2633 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2634 if ((__s) != GEN_FOREVER) \
2636 if ((__e) == GEN_FOREVER) \
2637 __e = BITS_PER_LONG - 1; \
2640 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2644 * Return true if revision is in range [since,until] inclusive.
2646 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2648 #define IS_REVID(p, since, until) \
2649 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2651 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2652 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2653 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2654 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2655 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2656 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2657 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2658 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2659 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2660 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2661 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2662 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2663 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2664 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2665 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2666 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2667 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2668 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2669 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2670 INTEL_DEVID(dev) == 0x0152 || \
2671 INTEL_DEVID(dev) == 0x015a)
2672 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2673 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2674 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2675 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
2676 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2677 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2678 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2679 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2680 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2681 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2682 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2683 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2684 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2685 (INTEL_DEVID(dev) & 0xf) == 0xe))
2686 /* ULX machines are also considered ULT. */
2687 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2688 (INTEL_DEVID(dev) & 0xf) == 0xe)
2689 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2690 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2691 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2692 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2693 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2694 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2695 /* ULX machines are also considered ULT. */
2696 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2697 INTEL_DEVID(dev) == 0x0A1E)
2698 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2699 INTEL_DEVID(dev) == 0x1913 || \
2700 INTEL_DEVID(dev) == 0x1916 || \
2701 INTEL_DEVID(dev) == 0x1921 || \
2702 INTEL_DEVID(dev) == 0x1926)
2703 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2704 INTEL_DEVID(dev) == 0x1915 || \
2705 INTEL_DEVID(dev) == 0x191E)
2706 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2707 INTEL_DEVID(dev) == 0x5913 || \
2708 INTEL_DEVID(dev) == 0x5916 || \
2709 INTEL_DEVID(dev) == 0x5921 || \
2710 INTEL_DEVID(dev) == 0x5926)
2711 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2712 INTEL_DEVID(dev) == 0x5915 || \
2713 INTEL_DEVID(dev) == 0x591E)
2714 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2715 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2716 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2717 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2719 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2721 #define SKL_REVID_A0 0x0
2722 #define SKL_REVID_B0 0x1
2723 #define SKL_REVID_C0 0x2
2724 #define SKL_REVID_D0 0x3
2725 #define SKL_REVID_E0 0x4
2726 #define SKL_REVID_F0 0x5
2728 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2730 #define BXT_REVID_A0 0x0
2731 #define BXT_REVID_A1 0x1
2732 #define BXT_REVID_B0 0x3
2733 #define BXT_REVID_C0 0x9
2735 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2737 #define KBL_REVID_A0 0x0
2738 #define KBL_REVID_B0 0x1
2739 #define KBL_REVID_C0 0x2
2740 #define KBL_REVID_D0 0x3
2741 #define KBL_REVID_E0 0x4
2743 #define IS_KBL_REVID(p, since, until) \
2744 (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2747 * The genX designation typically refers to the render engine, so render
2748 * capability related checks should use IS_GEN, while display and other checks
2749 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2752 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen_mask & BIT(1))
2753 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen_mask & BIT(2))
2754 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen_mask & BIT(3))
2755 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen_mask & BIT(4))
2756 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen_mask & BIT(5))
2757 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen_mask & BIT(6))
2758 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen_mask & BIT(7))
2759 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen_mask & BIT(8))
2761 #define RENDER_RING (1<<RCS)
2762 #define BSD_RING (1<<VCS)
2763 #define BLT_RING (1<<BCS)
2764 #define VEBOX_RING (1<<VECS)
2765 #define BSD2_RING (1<<VCS2)
2766 #define ALL_ENGINES (~0)
2768 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2769 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2770 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2771 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2772 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2773 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2774 #define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED)
2775 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2777 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2779 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2780 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2781 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2782 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2783 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2785 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2786 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2788 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2789 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2791 /* WaRsDisableCoarsePowerGating:skl,bxt */
2792 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2793 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2794 IS_SKL_GT3(dev_priv) || \
2795 IS_SKL_GT4(dev_priv))
2798 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2799 * even when in MSI mode. This results in spurious interrupt warnings if the
2800 * legacy irq no. is shared with another device. The kernel then disables that
2801 * interrupt source and so prevents the other device from working properly.
2803 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2804 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2806 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2807 * rows, which changed the alignment requirements and fence programming.
2809 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2811 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2812 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2814 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2815 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2816 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2818 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2820 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2821 INTEL_INFO(dev)->gen >= 9)
2823 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2824 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2825 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2826 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2827 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2828 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2829 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2830 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2831 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2832 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2833 #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
2835 #define HAS_CSR(dev) (IS_GEN9(dev))
2838 * For now, anything with a GuC requires uCode loading, and then supports
2839 * command submission once loaded. But these are logically independent
2840 * properties, so we have separate macros to test them.
2842 #define HAS_GUC(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2843 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2844 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2846 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2847 INTEL_INFO(dev)->gen >= 8)
2849 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2850 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2853 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2855 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2856 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2857 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2858 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2859 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2860 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2861 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2862 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2863 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2864 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2865 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2867 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2868 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2869 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2870 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2871 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2872 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2873 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2874 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2875 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2877 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2878 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2880 /* DPF == dynamic parity feature */
2881 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2882 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2884 #define GT_FREQUENCY_MULTIPLIER 50
2885 #define GEN9_FREQ_SCALER 3
2887 #include "i915_trace.h"
2889 extern const struct drm_ioctl_desc i915_ioctls[];
2890 extern int i915_max_ioctl;
2892 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2893 extern int i915_resume_switcheroo(struct drm_device *dev);
2895 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2900 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2901 const char *fmt, ...);
2903 #define i915_report_error(dev_priv, fmt, ...) \
2904 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2906 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2907 extern int i915_driver_unload(struct drm_device *);
2908 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2909 extern void i915_driver_lastclose(struct drm_device * dev);
2910 extern void i915_driver_preclose(struct drm_device *dev,
2911 struct drm_file *file);
2912 extern void i915_driver_postclose(struct drm_device *dev,
2913 struct drm_file *file);
2914 #ifdef CONFIG_COMPAT
2915 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2918 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2919 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2920 extern int i915_reset(struct drm_i915_private *dev_priv);
2921 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2922 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2923 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2924 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2925 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2926 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2927 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2929 /* intel_hotplug.c */
2930 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2931 u32 pin_mask, u32 long_mask);
2932 void intel_hpd_init(struct drm_i915_private *dev_priv);
2933 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2934 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2935 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2938 void i915_queue_hangcheck(struct drm_i915_private *dev_priv);
2940 void i915_handle_error(struct drm_i915_private *dev_priv,
2942 const char *fmt, ...);
2944 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2945 int intel_irq_install(struct drm_i915_private *dev_priv);
2946 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2948 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
2949 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2950 bool restore_forcewake);
2951 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2952 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2953 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2954 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
2955 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
2957 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2958 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2959 enum forcewake_domains domains);
2960 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2961 enum forcewake_domains domains);
2962 /* Like above but the caller must manage the uncore.lock itself.
2963 * Must be used with I915_READ_FW and friends.
2965 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2966 enum forcewake_domains domains);
2967 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2968 enum forcewake_domains domains);
2969 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
2971 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2973 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2975 return dev_priv->gvt.initialized;
2978 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2980 return dev_priv->vgpu.active;
2984 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2988 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2991 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2992 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2993 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2996 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2997 uint32_t interrupt_mask,
2998 uint32_t enabled_irq_mask);
3000 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3002 ilk_update_display_irq(dev_priv, bits, bits);
3005 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3007 ilk_update_display_irq(dev_priv, bits, 0);
3009 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3011 uint32_t interrupt_mask,
3012 uint32_t enabled_irq_mask);
3013 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3014 enum pipe pipe, uint32_t bits)
3016 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3018 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3019 enum pipe pipe, uint32_t bits)
3021 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3023 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3024 uint32_t interrupt_mask,
3025 uint32_t enabled_irq_mask);
3027 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3029 ibx_display_interrupt_update(dev_priv, bits, bits);
3032 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3034 ibx_display_interrupt_update(dev_priv, bits, 0);
3039 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3040 struct drm_file *file_priv);
3041 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3042 struct drm_file *file_priv);
3043 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3044 struct drm_file *file_priv);
3045 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3046 struct drm_file *file_priv);
3047 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3048 struct drm_file *file_priv);
3049 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3050 struct drm_file *file_priv);
3051 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3052 struct drm_file *file_priv);
3053 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
3054 struct drm_i915_gem_request *req);
3055 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
3056 struct drm_i915_gem_execbuffer2 *args,
3057 struct list_head *vmas);
3058 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3059 struct drm_file *file_priv);
3060 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3061 struct drm_file *file_priv);
3062 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3063 struct drm_file *file_priv);
3064 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3065 struct drm_file *file);
3066 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3067 struct drm_file *file);
3068 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3069 struct drm_file *file_priv);
3070 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3071 struct drm_file *file_priv);
3072 int i915_gem_set_tiling(struct drm_device *dev, void *data,
3073 struct drm_file *file_priv);
3074 int i915_gem_get_tiling(struct drm_device *dev, void *data,
3075 struct drm_file *file_priv);
3076 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3077 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3078 struct drm_file *file);
3079 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3080 struct drm_file *file_priv);
3081 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3082 struct drm_file *file_priv);
3083 void i915_gem_load_init(struct drm_device *dev);
3084 void i915_gem_load_cleanup(struct drm_device *dev);
3085 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3086 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3088 void *i915_gem_object_alloc(struct drm_device *dev);
3089 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3090 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3091 const struct drm_i915_gem_object_ops *ops);
3092 struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
3094 struct drm_i915_gem_object *i915_gem_object_create_from_data(
3095 struct drm_device *dev, const void *data, size_t size);
3096 void i915_gem_free_object(struct drm_gem_object *obj);
3097 void i915_gem_vma_destroy(struct i915_vma *vma);
3099 /* Flags used by pin/bind&friends. */
3100 #define PIN_MAPPABLE (1<<0)
3101 #define PIN_NONBLOCK (1<<1)
3102 #define PIN_GLOBAL (1<<2)
3103 #define PIN_OFFSET_BIAS (1<<3)
3104 #define PIN_USER (1<<4)
3105 #define PIN_UPDATE (1<<5)
3106 #define PIN_ZONE_4G (1<<6)
3107 #define PIN_HIGH (1<<7)
3108 #define PIN_OFFSET_FIXED (1<<8)
3109 #define PIN_OFFSET_MASK (~4095)
3111 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3112 struct i915_address_space *vm,
3116 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3117 const struct i915_ggtt_view *view,
3121 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3123 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
3124 int __must_check i915_vma_unbind(struct i915_vma *vma);
3126 * BEWARE: Do not use the function below unless you can _absolutely_
3127 * _guarantee_ VMA in question is _not in use_ anywhere.
3129 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
3130 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
3131 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
3132 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3134 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3135 int *needs_clflush);
3137 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3139 static inline int __sg_page_count(struct scatterlist *sg)
3141 return sg->length >> PAGE_SHIFT;
3145 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
3147 static inline dma_addr_t
3148 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n)
3150 if (n < obj->get_page.last) {
3151 obj->get_page.sg = obj->pages->sgl;
3152 obj->get_page.last = 0;
3155 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3156 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3157 if (unlikely(sg_is_chain(obj->get_page.sg)))
3158 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3161 return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT);
3164 static inline struct page *
3165 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3167 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
3170 if (n < obj->get_page.last) {
3171 obj->get_page.sg = obj->pages->sgl;
3172 obj->get_page.last = 0;
3175 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3176 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3177 if (unlikely(sg_is_chain(obj->get_page.sg)))
3178 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3181 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3184 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3186 BUG_ON(obj->pages == NULL);
3187 obj->pages_pin_count++;
3190 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3192 BUG_ON(obj->pages_pin_count == 0);
3193 obj->pages_pin_count--;
3197 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3198 * @obj - the object to map into kernel address space
3200 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3201 * pages and then returns a contiguous mapping of the backing storage into
3202 * the kernel address space.
3204 * The caller must hold the struct_mutex, and is responsible for calling
3205 * i915_gem_object_unpin_map() when the mapping is no longer required.
3207 * Returns the pointer through which to access the mapped object, or an
3208 * ERR_PTR() on error.
3210 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj);
3213 * i915_gem_object_unpin_map - releases an earlier mapping
3214 * @obj - the object to unmap
3216 * After pinning the object and mapping its pages, once you are finished
3217 * with your access, call i915_gem_object_unpin_map() to release the pin
3218 * upon the mapping. Once the pin count reaches zero, that mapping may be
3221 * The caller must hold the struct_mutex.
3223 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3225 lockdep_assert_held(&obj->base.dev->struct_mutex);
3226 i915_gem_object_unpin_pages(obj);
3229 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3230 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3231 struct intel_engine_cs *to,
3232 struct drm_i915_gem_request **to_req);
3233 void i915_vma_move_to_active(struct i915_vma *vma,
3234 struct drm_i915_gem_request *req);
3235 int i915_gem_dumb_create(struct drm_file *file_priv,
3236 struct drm_device *dev,
3237 struct drm_mode_create_dumb *args);
3238 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3239 uint32_t handle, uint64_t *offset);
3241 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3242 struct drm_i915_gem_object *new,
3243 unsigned frontbuffer_bits);
3246 * Returns true if seq1 is later than seq2.
3249 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
3251 return (int32_t)(seq1 - seq2) >= 0;
3254 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
3255 bool lazy_coherency)
3257 if (!lazy_coherency && req->engine->irq_seqno_barrier)
3258 req->engine->irq_seqno_barrier(req->engine);
3259 return i915_seqno_passed(req->engine->get_seqno(req->engine),
3260 req->previous_seqno);
3263 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
3264 bool lazy_coherency)
3266 if (!lazy_coherency && req->engine->irq_seqno_barrier)
3267 req->engine->irq_seqno_barrier(req->engine);
3268 return i915_seqno_passed(req->engine->get_seqno(req->engine),
3272 int __must_check i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno);
3273 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3275 struct drm_i915_gem_request *
3276 i915_gem_find_active_request(struct intel_engine_cs *engine);
3278 bool i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3279 void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
3281 static inline u32 i915_reset_counter(struct i915_gpu_error *error)
3283 return atomic_read(&error->reset_counter);
3286 static inline bool __i915_reset_in_progress(u32 reset)
3288 return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
3291 static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
3293 return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3296 static inline bool __i915_terminally_wedged(u32 reset)
3298 return unlikely(reset & I915_WEDGED);
3301 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3303 return __i915_reset_in_progress(i915_reset_counter(error));
3306 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3308 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
3311 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3313 return __i915_terminally_wedged(i915_reset_counter(error));
3316 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3318 return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
3321 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3323 return dev_priv->gpu_error.stop_rings == 0 ||
3324 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3327 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3329 return dev_priv->gpu_error.stop_rings == 0 ||
3330 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3333 void i915_gem_reset(struct drm_device *dev);
3334 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3335 int __must_check i915_gem_init(struct drm_device *dev);
3336 int i915_gem_init_engines(struct drm_device *dev);
3337 int __must_check i915_gem_init_hw(struct drm_device *dev);
3338 void i915_gem_init_swizzling(struct drm_device *dev);
3339 void i915_gem_cleanup_engines(struct drm_device *dev);
3340 int __must_check i915_gpu_idle(struct drm_device *dev);
3341 int __must_check i915_gem_suspend(struct drm_device *dev);
3342 void __i915_add_request(struct drm_i915_gem_request *req,
3343 struct drm_i915_gem_object *batch_obj,
3345 #define i915_add_request(req) \
3346 __i915_add_request(req, NULL, true)
3347 #define i915_add_request_no_flush(req) \
3348 __i915_add_request(req, NULL, false)
3349 int __i915_wait_request(struct drm_i915_gem_request *req,
3352 struct intel_rps_client *rps);
3353 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3354 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3356 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3359 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3362 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3364 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3366 const struct i915_ggtt_view *view);
3367 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3368 const struct i915_ggtt_view *view);
3369 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3371 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3372 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3375 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3377 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3378 int tiling_mode, bool fenced);
3380 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3381 enum i915_cache_level cache_level);
3383 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3384 struct dma_buf *dma_buf);
3386 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3387 struct drm_gem_object *gem_obj, int flags);
3389 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3390 const struct i915_ggtt_view *view);
3391 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3392 struct i915_address_space *vm);
3394 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3396 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3399 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3400 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3401 const struct i915_ggtt_view *view);
3402 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3403 struct i915_address_space *vm);
3406 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3407 struct i915_address_space *vm);
3409 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3410 const struct i915_ggtt_view *view);
3413 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3414 struct i915_address_space *vm);
3416 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3417 const struct i915_ggtt_view *view);
3419 static inline struct i915_vma *
3420 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3422 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3424 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3426 /* Some GGTT VM helpers */
3427 static inline struct i915_hw_ppgtt *
3428 i915_vm_to_ppgtt(struct i915_address_space *vm)
3430 return container_of(vm, struct i915_hw_ppgtt, base);
3434 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3436 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3440 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj);
3442 static inline int __must_check
3443 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3447 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3448 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3450 return i915_gem_object_pin(obj, &ggtt->base,
3451 alignment, flags | PIN_GLOBAL);
3454 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3455 const struct i915_ggtt_view *view);
3457 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3459 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3462 /* i915_gem_fence.c */
3463 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3464 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3466 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3467 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3469 void i915_gem_restore_fences(struct drm_device *dev);
3471 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3472 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3473 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3475 /* i915_gem_context.c */
3476 int __must_check i915_gem_context_init(struct drm_device *dev);
3477 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3478 void i915_gem_context_fini(struct drm_device *dev);
3479 void i915_gem_context_reset(struct drm_device *dev);
3480 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3481 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3482 int i915_switch_context(struct drm_i915_gem_request *req);
3483 void i915_gem_context_free(struct kref *ctx_ref);
3484 struct drm_i915_gem_object *
3485 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3486 struct i915_gem_context *
3487 i915_gem_context_create_gvt(struct drm_device *dev);
3489 static inline struct i915_gem_context *
3490 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3492 struct i915_gem_context *ctx;
3494 lockdep_assert_held(&file_priv->dev_priv->dev->struct_mutex);
3496 ctx = idr_find(&file_priv->context_idr, id);
3498 return ERR_PTR(-ENOENT);
3503 static inline void i915_gem_context_reference(struct i915_gem_context *ctx)
3505 kref_get(&ctx->ref);
3508 static inline void i915_gem_context_unreference(struct i915_gem_context *ctx)
3510 lockdep_assert_held(&ctx->i915->dev->struct_mutex);
3511 kref_put(&ctx->ref, i915_gem_context_free);
3514 static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3516 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3519 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3520 struct drm_file *file);
3521 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3522 struct drm_file *file);
3523 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3524 struct drm_file *file_priv);
3525 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3526 struct drm_file *file_priv);
3527 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
3528 struct drm_file *file);
3530 /* i915_gem_evict.c */
3531 int __must_check i915_gem_evict_something(struct drm_device *dev,
3532 struct i915_address_space *vm,
3535 unsigned cache_level,
3536 unsigned long start,
3539 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3540 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3542 /* belongs in i915_gem_gtt.h */
3543 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3545 if (INTEL_GEN(dev_priv) < 6)
3546 intel_gtt_chipset_flush();
3549 /* i915_gem_stolen.c */
3550 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3551 struct drm_mm_node *node, u64 size,
3552 unsigned alignment);
3553 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3554 struct drm_mm_node *node, u64 size,
3555 unsigned alignment, u64 start,
3557 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3558 struct drm_mm_node *node);
3559 int i915_gem_init_stolen(struct drm_device *dev);
3560 void i915_gem_cleanup_stolen(struct drm_device *dev);
3561 struct drm_i915_gem_object *
3562 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3563 struct drm_i915_gem_object *
3564 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3569 /* i915_gem_shrinker.c */
3570 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3571 unsigned long target,
3573 #define I915_SHRINK_PURGEABLE 0x1
3574 #define I915_SHRINK_UNBOUND 0x2
3575 #define I915_SHRINK_BOUND 0x4
3576 #define I915_SHRINK_ACTIVE 0x8
3577 #define I915_SHRINK_VMAPS 0x10
3578 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3579 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3580 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3583 /* i915_gem_tiling.c */
3584 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3586 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3588 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3589 obj->tiling_mode != I915_TILING_NONE;
3592 /* i915_gem_debug.c */
3594 int i915_verify_lists(struct drm_device *dev);
3596 #define i915_verify_lists(dev) 0
3599 /* i915_debugfs.c */
3600 int i915_debugfs_init(struct drm_minor *minor);
3601 void i915_debugfs_cleanup(struct drm_minor *minor);
3602 #ifdef CONFIG_DEBUG_FS
3603 int i915_debugfs_connector_add(struct drm_connector *connector);
3604 void intel_display_crc_init(struct drm_device *dev);
3606 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3608 static inline void intel_display_crc_init(struct drm_device *dev) {}
3611 /* i915_gpu_error.c */
3613 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3614 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3615 const struct i915_error_state_file_priv *error);
3616 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3617 struct drm_i915_private *i915,
3618 size_t count, loff_t pos);
3619 static inline void i915_error_state_buf_release(
3620 struct drm_i915_error_state_buf *eb)
3624 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3626 const char *error_msg);
3627 void i915_error_state_get(struct drm_device *dev,
3628 struct i915_error_state_file_priv *error_priv);
3629 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3630 void i915_destroy_error_state(struct drm_device *dev);
3632 void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
3633 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3635 /* i915_cmd_parser.c */
3636 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3637 int i915_cmd_parser_init_ring(struct intel_engine_cs *engine);
3638 void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine);
3639 bool i915_needs_cmd_parser(struct intel_engine_cs *engine);
3640 int i915_parse_cmds(struct intel_engine_cs *engine,
3641 struct drm_i915_gem_object *batch_obj,
3642 struct drm_i915_gem_object *shadow_batch_obj,
3643 u32 batch_start_offset,
3647 /* i915_suspend.c */
3648 extern int i915_save_state(struct drm_device *dev);
3649 extern int i915_restore_state(struct drm_device *dev);
3652 void i915_setup_sysfs(struct drm_device *dev_priv);
3653 void i915_teardown_sysfs(struct drm_device *dev_priv);
3656 extern int intel_setup_gmbus(struct drm_device *dev);
3657 extern void intel_teardown_gmbus(struct drm_device *dev);
3658 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3661 extern struct i2c_adapter *
3662 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3663 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3664 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3665 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3667 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3669 extern void intel_i2c_reset(struct drm_device *dev);
3672 int intel_bios_init(struct drm_i915_private *dev_priv);
3673 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3674 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3675 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3676 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3677 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3678 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3679 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3680 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3683 /* intel_opregion.c */
3685 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3686 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3687 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3688 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3689 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3691 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3693 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3695 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3696 static inline void intel_opregion_init(struct drm_i915_private *dev) { }
3697 static inline void intel_opregion_fini(struct drm_i915_private *dev) { }
3698 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3702 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3707 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3711 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3719 extern void intel_register_dsm_handler(void);
3720 extern void intel_unregister_dsm_handler(void);
3722 static inline void intel_register_dsm_handler(void) { return; }
3723 static inline void intel_unregister_dsm_handler(void) { return; }
3724 #endif /* CONFIG_ACPI */
3727 extern void intel_modeset_init_hw(struct drm_device *dev);
3728 extern void intel_modeset_init(struct drm_device *dev);
3729 extern void intel_modeset_gem_init(struct drm_device *dev);
3730 extern void intel_modeset_cleanup(struct drm_device *dev);
3731 extern void intel_connector_unregister(struct intel_connector *);
3732 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3733 extern void intel_display_resume(struct drm_device *dev);
3734 extern void i915_redisable_vga(struct drm_device *dev);
3735 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3736 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3737 extern void intel_init_pch_refclk(struct drm_device *dev);
3738 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3739 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3741 extern void intel_detect_pch(struct drm_device *dev);
3743 extern bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv);
3744 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3745 struct drm_file *file);
3748 extern struct intel_overlay_error_state *
3749 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3750 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3751 struct intel_overlay_error_state *error);
3753 extern struct intel_display_error_state *
3754 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3755 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3756 struct drm_device *dev,
3757 struct intel_display_error_state *error);
3759 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3760 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3762 /* intel_sideband.c */
3763 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3764 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3765 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3766 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3767 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3768 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3769 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3770 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3771 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3772 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3773 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3774 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3775 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3776 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3777 enum intel_sbi_destination destination);
3778 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3779 enum intel_sbi_destination destination);
3780 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3781 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3783 /* intel_dpio_phy.c */
3784 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3785 u32 deemph_reg_value, u32 margin_reg_value,
3786 bool uniq_trans_scale);
3787 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3789 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3790 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3791 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3792 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3794 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3795 u32 demph_reg_value, u32 preemph_reg_value,
3796 u32 uniqtranscale_reg_value, u32 tx3_demph);
3797 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3798 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3799 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3801 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3802 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3804 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3805 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3807 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3808 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3809 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3810 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3812 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3813 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3814 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3815 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3817 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3818 * will be implemented using 2 32-bit writes in an arbitrary order with
3819 * an arbitrary delay between them. This can cause the hardware to
3820 * act upon the intermediate value, possibly leading to corruption and
3821 * machine death. You have been warned.
3823 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3824 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3826 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3827 u32 upper, lower, old_upper, loop = 0; \
3828 upper = I915_READ(upper_reg); \
3830 old_upper = upper; \
3831 lower = I915_READ(lower_reg); \
3832 upper = I915_READ(upper_reg); \
3833 } while (upper != old_upper && loop++ < 2); \
3834 (u64)upper << 32 | lower; })
3836 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3837 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3839 #define __raw_read(x, s) \
3840 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3843 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3846 #define __raw_write(x, s) \
3847 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3848 i915_reg_t reg, uint##x##_t val) \
3850 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3865 /* These are untraced mmio-accessors that are only valid to be used inside
3866 * criticial sections inside IRQ handlers where forcewake is explicitly
3868 * Think twice, and think again, before using these.
3869 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3870 * intel_uncore_forcewake_irqunlock().
3872 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3873 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3874 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3876 /* "Broadcast RGB" property */
3877 #define INTEL_BROADCAST_RGB_AUTO 0
3878 #define INTEL_BROADCAST_RGB_FULL 1
3879 #define INTEL_BROADCAST_RGB_LIMITED 2
3881 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3883 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3884 return VLV_VGACNTRL;
3885 else if (INTEL_INFO(dev)->gen >= 5)
3886 return CPU_VGACNTRL;
3891 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3893 unsigned long j = msecs_to_jiffies(m);
3895 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3898 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3900 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3903 static inline unsigned long
3904 timespec_to_jiffies_timeout(const struct timespec *value)
3906 unsigned long j = timespec_to_jiffies(value);
3908 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3912 * If you need to wait X milliseconds between events A and B, but event B
3913 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3914 * when event A happened, then just before event B you call this function and
3915 * pass the timestamp as the first argument, and X as the second argument.
3918 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3920 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3923 * Don't re-read the value of "jiffies" every time since it may change
3924 * behind our back and break the math.
3926 tmp_jiffies = jiffies;
3927 target_jiffies = timestamp_jiffies +
3928 msecs_to_jiffies_timeout(to_wait_ms);
3930 if (time_after(target_jiffies, tmp_jiffies)) {
3931 remaining_jiffies = target_jiffies - tmp_jiffies;
3932 while (remaining_jiffies)
3934 schedule_timeout_uninterruptible(remaining_jiffies);
3938 static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
3939 struct drm_i915_gem_request *req)
3941 if (engine->trace_irq_req == NULL && engine->irq_get(engine))
3942 i915_gem_request_assign(&engine->trace_irq_req, req);