1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
37 /* General customization:
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
56 #define I915_NUM_PIPE 2
61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
63 * 1.4: Fix cmdbuffer path, add heap destroy
64 * 1.5: Add vblank pipe configuration
65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
68 #define DRIVER_MAJOR 1
69 #define DRIVER_MINOR 6
70 #define DRIVER_PATCHLEVEL 0
72 #define WATCH_COHERENCY 0
77 #define WATCH_INACTIVE 0
78 #define WATCH_PWRITE 0
80 #define I915_GEM_PHYS_CURSOR_0 1
81 #define I915_GEM_PHYS_CURSOR_1 2
82 #define I915_GEM_PHYS_OVERLAY_REGS 3
83 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
85 struct drm_i915_gem_phys_object {
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
92 typedef struct _drm_i915_ring_buffer {
99 struct drm_gem_object *ring_obj;
100 } drm_i915_ring_buffer_t;
103 struct mem_block *next;
104 struct mem_block *prev;
107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
110 struct opregion_header;
111 struct opregion_acpi;
112 struct opregion_swsci;
113 struct opregion_asle;
115 struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
123 struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
127 #define I915_FENCE_REG_NONE -1
129 struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
133 struct sdvo_device_mapping {
140 struct drm_i915_error_state {
156 struct drm_i915_display_funcs {
157 void (*dpms)(struct drm_crtc *crtc, int mode);
158 bool (*fbc_enabled)(struct drm_crtc *crtc);
159 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
160 void (*disable_fbc)(struct drm_device *dev);
161 int (*get_display_clock_speed)(struct drm_device *dev);
162 int (*get_fifo_size)(struct drm_device *dev, int plane);
163 void (*update_wm)(struct drm_device *dev, int planea_clock,
164 int planeb_clock, int sr_hdisplay, int pixel_size);
165 /* clock updates for mode set */
167 /* render clock increase/decrease */
168 /* display clock increase/decrease */
169 /* pll clock increase/decrease */
170 /* clock gating init */
173 struct intel_overlay;
175 struct intel_device_info {
190 u8 has_pipe_cxsr : 1;
192 u8 cursor_needs_physical : 1;
195 typedef struct drm_i915_private {
196 struct drm_device *dev;
198 const struct intel_device_info *info;
204 struct pci_dev *bridge_dev;
205 drm_i915_ring_buffer_t ring;
207 drm_dma_handle_t *status_page_dmah;
208 void *hw_status_page;
209 dma_addr_t dma_status_page;
211 unsigned int status_gfx_addr;
212 drm_local_map_t hws_map;
213 struct drm_gem_object *hws_obj;
214 struct drm_gem_object *pwrctx;
216 struct resource mch_res;
224 wait_queue_head_t irq_queue;
225 atomic_t irq_received;
226 /** Protects user_irq_refcount and irq_mask_reg */
227 spinlock_t user_irq_lock;
228 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
229 int user_irq_refcount;
231 /** Cached value of IMR to avoid reads in updating the bitfield */
234 /** splitted irq regs for graphics and display engine on Ironlake,
235 irq_mask_reg is still used for display irq. */
237 u32 gt_irq_enable_reg;
238 u32 de_irq_enable_reg;
239 u32 pch_irq_mask_reg;
240 u32 pch_irq_enable_reg;
242 u32 hotplug_supported_mask;
243 struct work_struct hotplug_work;
245 int tex_lru_log_granularity;
246 int allow_batchbuffer;
247 struct mem_block *agp_heap;
248 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
251 /* For hangcheck timer */
252 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
253 struct timer_list hangcheck_timer;
259 unsigned long cfb_size;
260 unsigned long cfb_pitch;
266 struct intel_opregion opregion;
269 struct intel_overlay *overlay;
272 int backlight_duty_cycle; /* restore backlight to this value */
273 bool panel_wants_dither;
274 struct drm_display_mode *panel_fixed_mode;
275 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
276 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
278 /* Feature bits from the VBIOS */
279 unsigned int int_tv_support:1;
280 unsigned int lvds_dither:1;
281 unsigned int lvds_vbt:1;
282 unsigned int int_crt_support:1;
283 unsigned int lvds_use_ssc:1;
284 unsigned int edp_support:1;
288 struct notifier_block lid_notifier;
290 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */
291 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
292 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
293 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
295 unsigned int fsb_freq, mem_freq;
297 spinlock_t error_lock;
298 struct drm_i915_error_state *first_error;
299 struct work_struct error_work;
300 struct workqueue_struct *wq;
302 /* Display functions */
303 struct drm_i915_display_funcs display;
328 u32 saveTRANS_HTOTAL_A;
329 u32 saveTRANS_HBLANK_A;
330 u32 saveTRANS_HSYNC_A;
331 u32 saveTRANS_VTOTAL_A;
332 u32 saveTRANS_VBLANK_A;
333 u32 saveTRANS_VSYNC_A;
341 u32 savePFIT_PGM_RATIOS;
342 u32 saveBLC_HIST_CTL;
344 u32 saveBLC_PWM_CTL2;
345 u32 saveBLC_CPU_PWM_CTL;
346 u32 saveBLC_CPU_PWM_CTL2;
359 u32 saveTRANS_HTOTAL_B;
360 u32 saveTRANS_HBLANK_B;
361 u32 saveTRANS_HSYNC_B;
362 u32 saveTRANS_VTOTAL_B;
363 u32 saveTRANS_VBLANK_B;
364 u32 saveTRANS_VSYNC_B;
378 u32 savePP_ON_DELAYS;
379 u32 savePP_OFF_DELAYS;
387 u32 savePFIT_CONTROL;
388 u32 save_palette_a[256];
389 u32 save_palette_b[256];
390 u32 saveDPFC_CB_BASE;
391 u32 saveFBC_CFB_BASE;
394 u32 saveFBC_CONTROL2;
404 u32 saveCACHE_MODE_0;
405 u32 saveMI_ARB_STATE;
416 uint64_t saveFENCE[16];
427 u32 savePIPEA_GMCH_DATA_M;
428 u32 savePIPEB_GMCH_DATA_M;
429 u32 savePIPEA_GMCH_DATA_N;
430 u32 savePIPEB_GMCH_DATA_N;
431 u32 savePIPEA_DP_LINK_M;
432 u32 savePIPEB_DP_LINK_M;
433 u32 savePIPEA_DP_LINK_N;
434 u32 savePIPEB_DP_LINK_N;
445 u32 savePCH_DREF_CONTROL;
446 u32 saveDISP_ARB_CTL;
447 u32 savePIPEA_DATA_M1;
448 u32 savePIPEA_DATA_N1;
449 u32 savePIPEA_LINK_M1;
450 u32 savePIPEA_LINK_N1;
451 u32 savePIPEB_DATA_M1;
452 u32 savePIPEB_DATA_N1;
453 u32 savePIPEB_LINK_M1;
454 u32 savePIPEB_LINK_N1;
457 struct drm_mm gtt_space;
459 struct io_mapping *gtt_mapping;
463 * Membership on list of all loaded devices, used to evict
464 * inactive buffers under memory pressure.
466 * Modifications should only be done whilst holding the
467 * shrink_list_lock spinlock.
469 struct list_head shrink_list;
472 * List of objects currently involved in rendering from the
475 * Includes buffers having the contents of their GPU caches
476 * flushed, not necessarily primitives. last_rendering_seqno
477 * represents when the rendering involved will be completed.
479 * A reference is held on the buffer while on this list.
481 spinlock_t active_list_lock;
482 struct list_head active_list;
485 * List of objects which are not in the ringbuffer but which
486 * still have a write_domain which needs to be flushed before
489 * last_rendering_seqno is 0 while an object is in this list.
491 * A reference is held on the buffer while on this list.
493 struct list_head flushing_list;
496 * List of objects currently pending a GPU write flush.
498 * All elements on this list will belong to either the
499 * active_list or flushing_list, last_rendering_seqno can
500 * be used to differentiate between the two elements.
502 struct list_head gpu_write_list;
505 * LRU list of objects which are not in the ringbuffer and
506 * are ready to unbind, but are still in the GTT.
508 * last_rendering_seqno is 0 while an object is in this list.
510 * A reference is not held on the buffer while on this list,
511 * as merely being GTT-bound shouldn't prevent its being
512 * freed, and we'll pull it off the list in the free path.
514 struct list_head inactive_list;
516 /** LRU list of objects with fence regs on them. */
517 struct list_head fence_list;
520 * List of breadcrumbs associated with GPU requests currently
523 struct list_head request_list;
526 * We leave the user IRQ off as much as possible,
527 * but this means that requests will finish and never
528 * be retired once the system goes idle. Set a timer to
529 * fire periodically while the ring is running. When it
530 * fires, go retire requests.
532 struct delayed_work retire_work;
534 uint32_t next_gem_seqno;
537 * Waiting sequence number, if any
539 uint32_t waiting_gem_seqno;
542 * Last seq seen at irq time
544 uint32_t irq_gem_seqno;
547 * Flag if the X Server, and thus DRM, is not currently in
548 * control of the device.
550 * This is set between LeaveVT and EnterVT. It needs to be
551 * replaced with a semaphore. It also needs to be
552 * transitioned away from for kernel modesetting.
557 * Flag if the hardware appears to be wedged.
559 * This is set when attempts to idle the device timeout.
560 * It prevents command submission from occuring and makes
561 * every pending request fail
565 /** Bit 6 swizzling required for X tiling */
566 uint32_t bit_6_swizzle_x;
567 /** Bit 6 swizzling required for Y tiling */
568 uint32_t bit_6_swizzle_y;
570 /* storage for physical objects */
571 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
573 struct sdvo_device_mapping sdvo_mappings[2];
574 /* indicate whether the LVDS_BORDER should be enabled or not */
575 unsigned int lvds_border_bits;
577 struct drm_crtc *plane_to_crtc_mapping[2];
578 struct drm_crtc *pipe_to_crtc_mapping[2];
579 wait_queue_head_t pending_flip_queue;
581 /* Reclocking support */
582 bool render_reclock_avail;
583 bool lvds_downclock_avail;
584 /* indicates the reduced downclock for LVDS*/
586 struct work_struct idle_work;
587 struct timer_list idle_timer;
591 struct child_device_config *child_dev;
592 struct drm_connector *int_lvds_connector;
593 } drm_i915_private_t;
595 /** driver private structure attached to each drm_gem_object */
596 struct drm_i915_gem_object {
597 struct drm_gem_object *obj;
599 /** Current space allocated to this object in the GTT, if any. */
600 struct drm_mm_node *gtt_space;
602 /** This object's place on the active/flushing/inactive lists */
603 struct list_head list;
604 /** This object's place on GPU write list */
605 struct list_head gpu_write_list;
607 /** This object's place on the fenced object LRU */
608 struct list_head fence_list;
611 * This is set if the object is on the active or flushing lists
612 * (has pending rendering), and is not set if it's on inactive (ready
618 * This is set if the object has been written to since last bound
623 /** AGP memory structure for our GTT binding. */
624 DRM_AGP_MEM *agp_mem;
630 * Current offset of the object in GTT space.
632 * This is the same as gtt_space->start
637 * Fake offset for use by mmap(2)
639 uint64_t mmap_offset;
642 * Fence register bits (if any) for this object. Will be set
643 * as needed when mapped into the GTT.
644 * Protected by dev->struct_mutex.
648 /** How many users have pinned this object in GTT space */
651 /** Breadcrumb of last rendering to the buffer. */
652 uint32_t last_rendering_seqno;
654 /** Current tiling mode for the object. */
655 uint32_t tiling_mode;
658 /** Record of address bit 17 of each page at last unbind. */
661 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
665 * If present, while GEM_DOMAIN_CPU is in the read domain this array
666 * flags which individual pages are valid.
668 uint8_t *page_cpu_valid;
670 /** User space pin count and filp owning the pin */
671 uint32_t user_pin_count;
672 struct drm_file *pin_filp;
674 /** for phy allocated objects */
675 struct drm_i915_gem_phys_object *phys_obj;
678 * Used for checking the object doesn't appear more than once
679 * in an execbuffer object list.
684 * Advice: are the backing pages purgeable?
689 * Number of crtcs where this object is currently the fb, but
690 * will be page flipped away on the next vblank. When it
691 * reaches 0, dev_priv->pending_flip_queue will be woken up.
693 atomic_t pending_flip;
697 * Request queue structure.
699 * The request queue allows us to note sequence numbers that have been emitted
700 * and may be associated with active buffers to be retired.
702 * By keeping this list, we can avoid having to do questionable
703 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
704 * an emission time with seqnos for tracking how far ahead of the GPU we are.
706 struct drm_i915_gem_request {
707 /** GEM sequence number associated with this request. */
710 /** Time at which this request was emitted, in jiffies. */
711 unsigned long emitted_jiffies;
713 /** global list entry for this request */
714 struct list_head list;
716 /** file_priv list entry for this request */
717 struct list_head client_list;
720 struct drm_i915_file_private {
722 struct list_head request_list;
726 enum intel_chip_family {
733 extern struct drm_ioctl_desc i915_ioctls[];
734 extern int i915_max_ioctl;
735 extern unsigned int i915_fbpercrtc;
736 extern unsigned int i915_powersave;
737 extern unsigned int i915_lvds_downclock;
739 extern void i915_save_display(struct drm_device *dev);
740 extern void i915_restore_display(struct drm_device *dev);
741 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
742 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
745 extern void i915_kernel_lost_context(struct drm_device * dev);
746 extern int i915_driver_load(struct drm_device *, unsigned long flags);
747 extern int i915_driver_unload(struct drm_device *);
748 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
749 extern void i915_driver_lastclose(struct drm_device * dev);
750 extern void i915_driver_preclose(struct drm_device *dev,
751 struct drm_file *file_priv);
752 extern void i915_driver_postclose(struct drm_device *dev,
753 struct drm_file *file_priv);
754 extern int i915_driver_device_is_agp(struct drm_device * dev);
755 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
757 extern int i915_emit_box(struct drm_device *dev,
758 struct drm_clip_rect *boxes,
759 int i, int DR1, int DR4);
760 extern int i965_reset(struct drm_device *dev, u8 flags);
763 void i915_hangcheck_elapsed(unsigned long data);
764 extern int i915_irq_emit(struct drm_device *dev, void *data,
765 struct drm_file *file_priv);
766 extern int i915_irq_wait(struct drm_device *dev, void *data,
767 struct drm_file *file_priv);
768 void i915_user_irq_get(struct drm_device *dev);
769 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
770 void i915_user_irq_put(struct drm_device *dev);
771 extern void i915_enable_interrupt (struct drm_device *dev);
773 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
774 extern void i915_driver_irq_preinstall(struct drm_device * dev);
775 extern int i915_driver_irq_postinstall(struct drm_device *dev);
776 extern void i915_driver_irq_uninstall(struct drm_device * dev);
777 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
778 struct drm_file *file_priv);
779 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
780 struct drm_file *file_priv);
781 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
782 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
783 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
784 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
785 extern int i915_vblank_swap(struct drm_device *dev, void *data,
786 struct drm_file *file_priv);
787 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
790 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
793 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
795 void intel_enable_asle (struct drm_device *dev);
799 extern int i915_mem_alloc(struct drm_device *dev, void *data,
800 struct drm_file *file_priv);
801 extern int i915_mem_free(struct drm_device *dev, void *data,
802 struct drm_file *file_priv);
803 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
804 struct drm_file *file_priv);
805 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
806 struct drm_file *file_priv);
807 extern void i915_mem_takedown(struct mem_block **heap);
808 extern void i915_mem_release(struct drm_device * dev,
809 struct drm_file *file_priv, struct mem_block *heap);
811 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
812 struct drm_file *file_priv);
813 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
814 struct drm_file *file_priv);
815 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
816 struct drm_file *file_priv);
817 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
818 struct drm_file *file_priv);
819 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
820 struct drm_file *file_priv);
821 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
822 struct drm_file *file_priv);
823 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
824 struct drm_file *file_priv);
825 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
826 struct drm_file *file_priv);
827 int i915_gem_execbuffer(struct drm_device *dev, void *data,
828 struct drm_file *file_priv);
829 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
830 struct drm_file *file_priv);
831 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
832 struct drm_file *file_priv);
833 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
834 struct drm_file *file_priv);
835 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
836 struct drm_file *file_priv);
837 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
838 struct drm_file *file_priv);
839 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
840 struct drm_file *file_priv);
841 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
842 struct drm_file *file_priv);
843 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
844 struct drm_file *file_priv);
845 int i915_gem_set_tiling(struct drm_device *dev, void *data,
846 struct drm_file *file_priv);
847 int i915_gem_get_tiling(struct drm_device *dev, void *data,
848 struct drm_file *file_priv);
849 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
850 struct drm_file *file_priv);
851 void i915_gem_load(struct drm_device *dev);
852 int i915_gem_init_object(struct drm_gem_object *obj);
853 void i915_gem_free_object(struct drm_gem_object *obj);
854 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
855 void i915_gem_object_unpin(struct drm_gem_object *obj);
856 int i915_gem_object_unbind(struct drm_gem_object *obj);
857 void i915_gem_release_mmap(struct drm_gem_object *obj);
858 void i915_gem_lastclose(struct drm_device *dev);
859 uint32_t i915_get_gem_seqno(struct drm_device *dev);
860 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
861 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
862 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
863 void i915_gem_retire_requests(struct drm_device *dev);
864 void i915_gem_retire_work_handler(struct work_struct *work);
865 void i915_gem_clflush_object(struct drm_gem_object *obj);
866 int i915_gem_object_set_domain(struct drm_gem_object *obj,
867 uint32_t read_domains,
868 uint32_t write_domain);
869 int i915_gem_init_ringbuffer(struct drm_device *dev);
870 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
871 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
873 int i915_gem_idle(struct drm_device *dev);
874 uint32_t i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
875 uint32_t flush_domains);
876 int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible);
877 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
878 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
880 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
881 int i915_gem_attach_phys_object(struct drm_device *dev,
882 struct drm_gem_object *obj, int id);
883 void i915_gem_detach_phys_object(struct drm_device *dev,
884 struct drm_gem_object *obj);
885 void i915_gem_free_all_phys_object(struct drm_device *dev);
886 int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
887 void i915_gem_object_put_pages(struct drm_gem_object *obj);
888 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
889 void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
891 void i915_gem_shrinker_init(void);
892 void i915_gem_shrinker_exit(void);
894 /* i915_gem_tiling.c */
895 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
896 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
897 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
898 bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
900 bool i915_obj_fenceable(struct drm_device *dev, struct drm_gem_object *obj);
902 /* i915_gem_debug.c */
903 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
904 const char *where, uint32_t mark);
906 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
908 #define i915_verify_inactive(dev, file, line)
910 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
911 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
912 const char *where, uint32_t mark);
913 void i915_dump_lru(struct drm_device *dev, const char *where);
916 int i915_debugfs_init(struct drm_minor *minor);
917 void i915_debugfs_cleanup(struct drm_minor *minor);
920 extern int i915_save_state(struct drm_device *dev);
921 extern int i915_restore_state(struct drm_device *dev);
924 extern int i915_save_state(struct drm_device *dev);
925 extern int i915_restore_state(struct drm_device *dev);
928 /* i915_opregion.c */
929 extern int intel_opregion_init(struct drm_device *dev, int resume);
930 extern void intel_opregion_free(struct drm_device *dev, int suspend);
931 extern void opregion_asle_intr(struct drm_device *dev);
932 extern void ironlake_opregion_gse_intr(struct drm_device *dev);
933 extern void opregion_enable_asle(struct drm_device *dev);
935 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
936 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
937 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
938 static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; }
939 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
943 extern void intel_modeset_init(struct drm_device *dev);
944 extern void intel_modeset_cleanup(struct drm_device *dev);
945 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
946 extern void i8xx_disable_fbc(struct drm_device *dev);
947 extern void g4x_disable_fbc(struct drm_device *dev);
950 * Lock test for when it's just for synchronization of ring access.
952 * In that case, we don't need to do it when GEM is initialized as nobody else
953 * has access to the ring.
955 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
956 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
957 LOCK_TEST_WITH_RETURN(dev, file_priv); \
960 #define I915_READ(reg) readl(dev_priv->regs + (reg))
961 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
962 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
963 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
964 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
965 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
966 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
967 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
968 #define POSTING_READ(reg) (void)I915_READ(reg)
970 #define I915_VERBOSE 0
972 #define RING_LOCALS volatile unsigned int *ring_virt__;
974 #define BEGIN_LP_RING(n) do { \
975 int bytes__ = 4*(n); \
976 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
977 /* a wrap must occur between instructions so pad beforehand */ \
978 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
979 i915_wrap_ring(dev); \
980 if (unlikely (dev_priv->ring.space < bytes__)) \
981 i915_wait_ring(dev, bytes__, __func__); \
982 ring_virt__ = (unsigned int *) \
983 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
984 dev_priv->ring.tail += bytes__; \
985 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
986 dev_priv->ring.space -= bytes__; \
989 #define OUT_RING(n) do { \
990 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
991 *ring_virt__++ = (n); \
994 #define ADVANCE_LP_RING() do { \
996 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
997 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
1001 * Reads a dword out of the status page, which is written to from the command
1002 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1003 * MI_STORE_DATA_IMM.
1005 * The following dwords have a reserved meaning:
1006 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1007 * 0x04: ring 0 head pointer
1008 * 0x05: ring 1 head pointer (915-class)
1009 * 0x06: ring 2 head pointer (915-class)
1010 * 0x10-0x1b: Context status DWords (GM45)
1011 * 0x1f: Last written status offset. (GM45)
1013 * The area from dword 0x20 to 0x3ff is available for driver usage.
1015 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
1016 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1017 #define I915_GEM_HWS_INDEX 0x20
1018 #define I915_BREADCRUMB_INDEX 0x21
1020 extern int i915_wrap_ring(struct drm_device * dev);
1021 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1023 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1025 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1026 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1027 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
1028 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1029 #define IS_I8XX(dev) (INTEL_INFO(dev)->is_i8xx)
1030 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1031 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1032 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1033 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1034 #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
1035 #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
1036 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1037 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1038 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1039 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1040 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1041 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1042 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1043 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1044 #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1045 #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1046 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1048 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1050 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1051 * rows, which changed the alignment requirements and fence programming.
1053 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1055 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1056 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1057 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1058 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1059 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1060 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev))
1061 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1062 /* dsparb controlled by hw only */
1063 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1065 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1066 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1067 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1068 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1070 #define PRIMARY_RINGBUFFER_SIZE (128*1024)