drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34 #include <uapi/drm/drm_fourcc.h>
  35
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <linux/backlight.h>
  40 #include <linux/hashtable.h>
  41 #include <linux/intel-iommu.h>
  42 #include <linux/kref.h>
  43 #include <linux/pm_qos.h>
  44 #include <linux/reservation.h>
  45 #include <linux/shmem_fs.h>
  46
  47 #include <drm/drmP.h>
  48 #include <drm/intel-gtt.h>
  49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
  50 #include <drm/drm_gem.h>
  51 #include <drm/drm_auth.h>
  52
  53 #include "i915_params.h"
  54 #include "i915_reg.h"
  55
  56 #include "intel_bios.h"
  57 #include "intel_dpll_mgr.h"
  58 #include "intel_uc.h"
  59 #include "intel_lrc.h"
  60 #include "intel_ringbuffer.h"
  61
  62 #include "i915_gem.h"
  63 #include "i915_gem_fence_reg.h"
  64 #include "i915_gem_object.h"
  65 #include "i915_gem_gtt.h"
  66 #include "i915_gem_render_state.h"
  67 #include "i915_gem_request.h"
  68 #include "i915_gem_timeline.h"
  69
  70 #include "i915_vma.h"
  71
  72 #include "intel_gvt.h"
  73
  74 /* General customization:
  75  */
  76
  77 #define DRIVER_NAME             "i915"
  78 #define DRIVER_DESC             "Intel Graphics"
  79 #define DRIVER_DATE             "20161205"
  80 #define DRIVER_TIMESTAMP        1480926326
  81
  82 #undef WARN_ON
  83 /* Many gcc seem to no see through this and fall over :( */
  84 #if 0
  85 #define WARN_ON(x) ({ \
  86         bool __i915_warn_cond = (x); \
  87         if (__builtin_constant_p(__i915_warn_cond)) \
  88                 BUILD_BUG_ON(__i915_warn_cond); \
  89         WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
  90 #else
  91 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
  92 #endif
  93
  94 #undef WARN_ON_ONCE
  95 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
  96
  97 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
  98                              (long) (x), __func__);
  99
 100 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 101  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 102  * which may not necessarily be a user visible problem.  This will either
 103  * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 104  * enable distros and users to tailor their preferred amount of i915 abrt
 105  * spam.
 106  */
 107 #define I915_STATE_WARN(condition, format...) ({                        \
 108         int __ret_warn_on = !!(condition);                              \
 109         if (unlikely(__ret_warn_on))                                    \
 110                 if (!WARN(i915.verbose_state_checks, format))           \
 111                         DRM_ERROR(format);                              \
 112         unlikely(__ret_warn_on);                                        \
 113 })
 114
 115 #define I915_STATE_WARN_ON(x)                                           \
 116         I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
 117
 118 bool __i915_inject_load_failure(const char *func, int line);
 119 #define i915_inject_load_failure() \
 120         __i915_inject_load_failure(__func__, __LINE__)
 121
 122 typedef struct {
 123         uint32_t val;
 124 } uint_fixed_16_16_t;
 125
 126 #define FP_16_16_MAX ({ \
 127         uint_fixed_16_16_t fp; \
 128         fp.val = UINT_MAX; \
 129         fp; \
 130 })
 131
 132 static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
 133 {
 134         uint_fixed_16_16_t fp;
 135
 136         WARN_ON(val >> 16);
 137
 138         fp.val = val << 16;
 139         return fp;
 140 }
 141
 142 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
 143 {
 144         return DIV_ROUND_UP(fp.val, 1 << 16);
 145 }
 146
 147 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
 148 {
 149         return fp.val >> 16;
 150 }
 151
 152 static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
 153                                                  uint_fixed_16_16_t min2)
 154 {
 155         uint_fixed_16_16_t min;
 156
 157         min.val = min(min1.val, min2.val);
 158         return min;
 159 }
 160
 161 static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
 162                                                  uint_fixed_16_16_t max2)
 163 {
 164         uint_fixed_16_16_t max;
 165
 166         max.val = max(max1.val, max2.val);
 167         return max;
 168 }
 169
 170 static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
 171                                                           uint32_t d)
 172 {
 173         uint_fixed_16_16_t fp, res;
 174
 175         fp = u32_to_fixed_16_16(val);
 176         res.val = DIV_ROUND_UP(fp.val, d);
 177         return res;
 178 }
 179
 180 static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
 181                                                               uint32_t d)
 182 {
 183         uint_fixed_16_16_t res;
 184         uint64_t interm_val;
 185
 186         interm_val = (uint64_t)val << 16;
 187         interm_val = DIV_ROUND_UP_ULL(interm_val, d);
 188         WARN_ON(interm_val >> 32);
 189         res.val = (uint32_t) interm_val;
 190
 191         return res;
 192 }
 193
 194 static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
 195                                                      uint_fixed_16_16_t mul)
 196 {
 197         uint64_t intermediate_val;
 198         uint_fixed_16_16_t fp;
 199
 200         intermediate_val = (uint64_t) val * mul.val;
 201         WARN_ON(intermediate_val >> 32);
 202         fp.val = (uint32_t) intermediate_val;
 203         return fp;
 204 }
 205
 206 static inline const char *yesno(bool v)
 207 {
 208         return v ? "yes" : "no";
 209 }
 210
 211 static inline const char *onoff(bool v)
 212 {
 213         return v ? "on" : "off";
 214 }
 215
 216 static inline const char *enableddisabled(bool v)
 217 {
 218         return v ? "enabled" : "disabled";
 219 }
 220
 221 #define range_overflows(start, size, max) ({ \
 222         typeof(start) start__ = (start); \
 223         typeof(size) size__ = (size); \
 224         typeof(max) max__ = (max); \
 225         (void)(&start__ == &size__); \
 226         (void)(&start__ == &max__); \
 227         start__ > max__ || size__ > max__ - start__; \
 228 })
 229
 230 #define range_overflows_t(type, start, size, max) \
 231         range_overflows((type)(start), (type)(size), (type)(max))
 232
 233 enum pipe {
 234         INVALID_PIPE = -1,
 235         PIPE_A = 0,
 236         PIPE_B,
 237         PIPE_C,
 238         _PIPE_EDP,
 239         I915_MAX_PIPES = _PIPE_EDP
 240 };
 241 #define pipe_name(p) ((p) + 'A')
 242
 243 enum transcoder {
 244         TRANSCODER_A = 0,
 245         TRANSCODER_B,
 246         TRANSCODER_C,
 247         TRANSCODER_EDP,
 248         TRANSCODER_DSI_A,
 249         TRANSCODER_DSI_C,
 250         I915_MAX_TRANSCODERS
 251 };
 252
 253 static inline const char *transcoder_name(enum transcoder transcoder)
 254 {
 255         switch (transcoder) {
 256         case TRANSCODER_A:
 257                 return "A";
 258         case TRANSCODER_B:
 259                 return "B";
 260         case TRANSCODER_C:
 261                 return "C";
 262         case TRANSCODER_EDP:
 263                 return "EDP";
 264         case TRANSCODER_DSI_A:
 265                 return "DSI A";
 266         case TRANSCODER_DSI_C:
 267                 return "DSI C";
 268         default:
 269                 return "<invalid>";
 270         }
 271 }
 272
 273 static inline bool transcoder_is_dsi(enum transcoder transcoder)
 274 {
 275         return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
 276 }
 277
 278 /*
 279  * Global legacy plane identifier. Valid only for primary/sprite
 280  * planes on pre-g4x, and only for primary planes on g4x+.
 281  */
 282 enum plane {
 283         PLANE_A,
 284         PLANE_B,
 285         PLANE_C,
 286 };
 287 #define plane_name(p) ((p) + 'A')
 288
 289 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
 290
 291 /*
 292  * Per-pipe plane identifier.
 293  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 294  * number of planes per CRTC.  Not all platforms really have this many planes,
 295  * which means some arrays of size I915_MAX_PLANES may have unused entries
 296  * between the topmost sprite plane and the cursor plane.
 297  *
 298  * This is expected to be passed to various register macros
 299  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 300  */
 301 enum plane_id {
 302         PLANE_PRIMARY,
 303         PLANE_SPRITE0,
 304         PLANE_SPRITE1,
 305         PLANE_CURSOR,
 306         I915_MAX_PLANES,
 307 };
 308
 309 #define for_each_plane_id_on_crtc(__crtc, __p) \
 310         for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
 311                 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
 312
 313 enum port {
 314         PORT_NONE = -1,
 315         PORT_A = 0,
 316         PORT_B,
 317         PORT_C,
 318         PORT_D,
 319         PORT_E,
 320         I915_MAX_PORTS
 321 };
 322 #define port_name(p) ((p) + 'A')
 323
 324 #define I915_NUM_PHYS_VLV 2
 325
 326 enum dpio_channel {
 327         DPIO_CH0,
 328         DPIO_CH1
 329 };
 330
 331 enum dpio_phy {
 332         DPIO_PHY0,
 333         DPIO_PHY1,
 334         DPIO_PHY2,
 335 };
 336
 337 enum intel_display_power_domain {
 338         POWER_DOMAIN_PIPE_A,
 339         POWER_DOMAIN_PIPE_B,
 340         POWER_DOMAIN_PIPE_C,
 341         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 342         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 343         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
 344         POWER_DOMAIN_TRANSCODER_A,
 345         POWER_DOMAIN_TRANSCODER_B,
 346         POWER_DOMAIN_TRANSCODER_C,
 347         POWER_DOMAIN_TRANSCODER_EDP,
 348         POWER_DOMAIN_TRANSCODER_DSI_A,
 349         POWER_DOMAIN_TRANSCODER_DSI_C,
 350         POWER_DOMAIN_PORT_DDI_A_LANES,
 351         POWER_DOMAIN_PORT_DDI_B_LANES,
 352         POWER_DOMAIN_PORT_DDI_C_LANES,
 353         POWER_DOMAIN_PORT_DDI_D_LANES,
 354         POWER_DOMAIN_PORT_DDI_E_LANES,
 355         POWER_DOMAIN_PORT_DSI,
 356         POWER_DOMAIN_PORT_CRT,
 357         POWER_DOMAIN_PORT_OTHER,
 358         POWER_DOMAIN_VGA,
 359         POWER_DOMAIN_AUDIO,
 360         POWER_DOMAIN_PLLS,
 361         POWER_DOMAIN_AUX_A,
 362         POWER_DOMAIN_AUX_B,
 363         POWER_DOMAIN_AUX_C,
 364         POWER_DOMAIN_AUX_D,
 365         POWER_DOMAIN_GMBUS,
 366         POWER_DOMAIN_MODESET,
 367         POWER_DOMAIN_INIT,
 368
 369         POWER_DOMAIN_NUM,
 370 };
 371
 372 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 373 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 374                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 375 #define POWER_DOMAIN_TRANSCODER(tran) \
 376         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 377          (tran) + POWER_DOMAIN_TRANSCODER_A)
 378
 379 enum hpd_pin {
 380         HPD_NONE = 0,
 381         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 382         HPD_CRT,
 383         HPD_SDVO_B,
 384         HPD_SDVO_C,
 385         HPD_PORT_A,
 386         HPD_PORT_B,
 387         HPD_PORT_C,
 388         HPD_PORT_D,
 389         HPD_PORT_E,
 390         HPD_NUM_PINS
 391 };
 392
 393 #define for_each_hpd_pin(__pin) \
 394         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 395
 396 struct i915_hotplug {
 397         struct work_struct hotplug_work;
 398
 399         struct {
 400                 unsigned long last_jiffies;
 401                 int count;
 402                 enum {
 403                         HPD_ENABLED = 0,
 404                         HPD_DISABLED = 1,
 405                         HPD_MARK_DISABLED = 2
 406                 } state;
 407         } stats[HPD_NUM_PINS];
 408         u32 event_bits;
 409         struct delayed_work reenable_work;
 410
 411         struct intel_digital_port *irq_port[I915_MAX_PORTS];
 412         u32 long_port_mask;
 413         u32 short_port_mask;
 414         struct work_struct dig_port_work;
 415
 416         struct work_struct poll_init_work;
 417         bool poll_enabled;
 418
 419         /*
 420          * if we get a HPD irq from DP and a HPD irq from non-DP
 421          * the non-DP HPD could block the workqueue on a mode config
 422          * mutex getting, that userspace may have taken. However
 423          * userspace is waiting on the DP workqueue to run which is
 424          * blocked behind the non-DP one.
 425          */
 426         struct workqueue_struct *dp_wq;
 427 };
 428
 429 #define I915_GEM_GPU_DOMAINS \
 430         (I915_GEM_DOMAIN_RENDER | \
 431          I915_GEM_DOMAIN_SAMPLER | \
 432          I915_GEM_DOMAIN_COMMAND | \
 433          I915_GEM_DOMAIN_INSTRUCTION | \
 434          I915_GEM_DOMAIN_VERTEX)
 435
 436 #define for_each_pipe(__dev_priv, __p) \
 437         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
 438 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
 439         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
 440                 for_each_if ((__mask) & (1 << (__p)))
 441 #define for_each_universal_plane(__dev_priv, __pipe, __p)               \
 442         for ((__p) = 0;                                                 \
 443              (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
 444              (__p)++)
 445 #define for_each_sprite(__dev_priv, __p, __s)                           \
 446         for ((__s) = 0;                                                 \
 447              (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];        \
 448              (__s)++)
 449
 450 #define for_each_port_masked(__port, __ports_mask) \
 451         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)  \
 452                 for_each_if ((__ports_mask) & (1 << (__port)))
 453
 454 #define for_each_crtc(dev, crtc) \
 455         list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 456
 457 #define for_each_intel_plane(dev, intel_plane) \
 458         list_for_each_entry(intel_plane,                        \
 459                             &(dev)->mode_config.plane_list,     \
 460                             base.head)
 461
 462 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
 463         list_for_each_entry(intel_plane,                                \
 464                             &(dev)->mode_config.plane_list,             \
 465                             base.head)                                  \
 466                 for_each_if ((plane_mask) &                             \
 467                              (1 << drm_plane_index(&intel_plane->base)))
 468
 469 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
 470         list_for_each_entry(intel_plane,                                \
 471                             &(dev)->mode_config.plane_list,             \
 472                             base.head)                                  \
 473                 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
 474
 475 #define for_each_intel_crtc(dev, intel_crtc)                            \
 476         list_for_each_entry(intel_crtc,                                 \
 477                             &(dev)->mode_config.crtc_list,              \
 478                             base.head)
 479
 480 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)            \
 481         list_for_each_entry(intel_crtc,                                 \
 482                             &(dev)->mode_config.crtc_list,              \
 483                             base.head)                                  \
 484                 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
 485
 486 #define for_each_intel_encoder(dev, intel_encoder)              \
 487         list_for_each_entry(intel_encoder,                      \
 488                             &(dev)->mode_config.encoder_list,   \
 489                             base.head)
 490
 491 #define for_each_intel_connector(dev, intel_connector)          \
 492         list_for_each_entry(intel_connector,                    \
 493                             &(dev)->mode_config.connector_list, \
 494                             base.head)
 495
 496 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 497         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 498                 for_each_if ((intel_encoder)->base.crtc == (__crtc))
 499
 500 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 501         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 502                 for_each_if ((intel_connector)->base.encoder == (__encoder))
 503
 504 #define for_each_power_domain(domain, mask)                             \
 505         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
 506                 for_each_if ((1 << (domain)) & (mask))
 507
 508 struct drm_i915_private;
 509 struct i915_mm_struct;
 510 struct i915_mmu_object;
 511
 512 struct drm_i915_file_private {
 513         struct drm_i915_private *dev_priv;
 514         struct drm_file *file;
 515
 516         struct {
 517                 spinlock_t lock;
 518                 struct list_head request_list;
 519 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
 520  * chosen to prevent the CPU getting more than a frame ahead of the GPU
 521  * (when using lax throttling for the frontbuffer). We also use it to
 522  * offer free GPU waitboosts for severely congested workloads.
 523  */
 524 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
 525         } mm;
 526         struct idr context_idr;
 527
 528         struct intel_rps_client {
 529                 struct list_head link;
 530                 unsigned boosts;
 531         } rps;
 532
 533         unsigned int bsd_engine;
 534
 535 /* Client can have a maximum of 3 contexts banned before
 536  * it is denied of creating new contexts. As one context
 537  * ban needs 4 consecutive hangs, and more if there is
 538  * progress in between, this is a last resort stop gap measure
 539  * to limit the badly behaving clients access to gpu.
 540  */
 541 #define I915_MAX_CLIENT_CONTEXT_BANS 3
 542         int context_bans;
 543 };
 544
 545 /* Used by dp and fdi links */
 546 struct intel_link_m_n {
 547         uint32_t        tu;
 548         uint32_t        gmch_m;
 549         uint32_t        gmch_n;
 550         uint32_t        link_m;
 551         uint32_t        link_n;
 552 };
 553
 554 void intel_link_compute_m_n(int bpp, int nlanes,
 555                             int pixel_clock, int link_clock,
 556                             struct intel_link_m_n *m_n);
 557
 558 /* Interface history:
 559  *
 560  * 1.1: Original.
 561  * 1.2: Add Power Management
 562  * 1.3: Add vblank support
 563  * 1.4: Fix cmdbuffer path, add heap destroy
 564  * 1.5: Add vblank pipe configuration
 565  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 566  *      - Support vertical blank on secondary display pipe
 567  */
 568 #define DRIVER_MAJOR            1
 569 #define DRIVER_MINOR            6
 570 #define DRIVER_PATCHLEVEL       0
 571
 572 struct opregion_header;
 573 struct opregion_acpi;
 574 struct opregion_swsci;
 575 struct opregion_asle;
 576
 577 struct intel_opregion {
 578         struct opregion_header *header;
 579         struct opregion_acpi *acpi;
 580         struct opregion_swsci *swsci;
 581         u32 swsci_gbda_sub_functions;
 582         u32 swsci_sbcb_sub_functions;
 583         struct opregion_asle *asle;
 584         void *rvda;
 585         const void *vbt;
 586         u32 vbt_size;
 587         u32 *lid_state;
 588         struct work_struct asle_work;
 589 };
 590 #define OPREGION_SIZE            (8*1024)
 591
 592 struct intel_overlay;
 593 struct intel_overlay_error_state;
 594
 595 struct sdvo_device_mapping {
 596         u8 initialized;
 597         u8 dvo_port;
 598         u8 slave_addr;
 599         u8 dvo_wiring;
 600         u8 i2c_pin;
 601         u8 ddc_pin;
 602 };
 603
 604 struct intel_connector;
 605 struct intel_encoder;
 606 struct intel_atomic_state;
 607 struct intel_crtc_state;
 608 struct intel_initial_plane_config;
 609 struct intel_crtc;
 610 struct intel_limit;
 611 struct dpll;
 612
 613 struct drm_i915_display_funcs {
 614         int (*get_display_clock_speed)(struct drm_i915_private *dev_priv);
 615         int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
 616         int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
 617         int (*compute_intermediate_wm)(struct drm_device *dev,
 618                                        struct intel_crtc *intel_crtc,
 619                                        struct intel_crtc_state *newstate);
 620         void (*initial_watermarks)(struct intel_atomic_state *state,
 621                                    struct intel_crtc_state *cstate);
 622         void (*atomic_update_watermarks)(struct intel_atomic_state *state,
 623                                          struct intel_crtc_state *cstate);
 624         void (*optimize_watermarks)(struct intel_atomic_state *state,
 625                                     struct intel_crtc_state *cstate);
 626         int (*compute_global_watermarks)(struct drm_atomic_state *state);
 627         void (*update_wm)(struct intel_crtc *crtc);
 628         int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
 629         void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
 630         /* Returns the active state of the crtc, and if the crtc is active,
 631          * fills out the pipe-config with the hw state. */
 632         bool (*get_pipe_config)(struct intel_crtc *,
 633                                 struct intel_crtc_state *);
 634         void (*get_initial_plane_config)(struct intel_crtc *,
 635                                          struct intel_initial_plane_config *);
 636         int (*crtc_compute_clock)(struct intel_crtc *crtc,
 637                                   struct intel_crtc_state *crtc_state);
 638         void (*crtc_enable)(struct intel_crtc_state *pipe_config,
 639                             struct drm_atomic_state *old_state);
 640         void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
 641                              struct drm_atomic_state *old_state);
 642         void (*update_crtcs)(struct drm_atomic_state *state,
 643                              unsigned int *crtc_vblank_mask);
 644         void (*audio_codec_enable)(struct drm_connector *connector,
 645                                    struct intel_encoder *encoder,
 646                                    const struct drm_display_mode *adjusted_mode);
 647         void (*audio_codec_disable)(struct intel_encoder *encoder);
 648         void (*fdi_link_train)(struct drm_crtc *crtc);
 649         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
 650         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 651                           struct drm_framebuffer *fb,
 652                           struct drm_i915_gem_object *obj,
 653                           struct drm_i915_gem_request *req,
 654                           uint32_t flags);
 655         void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 656         /* clock updates for mode set */
 657         /* cursor updates */
 658         /* render clock increase/decrease */
 659         /* display clock increase/decrease */
 660         /* pll clock increase/decrease */
 661
 662         void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
 663         void (*load_luts)(struct drm_crtc_state *crtc_state);
 664 };
 665
 666 enum forcewake_domain_id {
 667         FW_DOMAIN_ID_RENDER = 0,
 668         FW_DOMAIN_ID_BLITTER,
 669         FW_DOMAIN_ID_MEDIA,
 670
 671         FW_DOMAIN_ID_COUNT
 672 };
 673
 674 enum forcewake_domains {
 675         FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
 676         FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
 677         FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
 678         FORCEWAKE_ALL = (FORCEWAKE_RENDER |
 679                          FORCEWAKE_BLITTER |
 680                          FORCEWAKE_MEDIA)
 681 };
 682
 683 #define FW_REG_READ  (1)
 684 #define FW_REG_WRITE (2)
 685
 686 enum decoupled_power_domain {
 687         GEN9_DECOUPLED_PD_BLITTER = 0,
 688         GEN9_DECOUPLED_PD_RENDER,
 689         GEN9_DECOUPLED_PD_MEDIA,
 690         GEN9_DECOUPLED_PD_ALL
 691 };
 692
 693 enum decoupled_ops {
 694         GEN9_DECOUPLED_OP_WRITE = 0,
 695         GEN9_DECOUPLED_OP_READ
 696 };
 697
 698 enum forcewake_domains
 699 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
 700                                i915_reg_t reg, unsigned int op);
 701
 702 struct intel_uncore_funcs {
 703         void (*force_wake_get)(struct drm_i915_private *dev_priv,
 704                                                         enum forcewake_domains domains);
 705         void (*force_wake_put)(struct drm_i915_private *dev_priv,
 706                                                         enum forcewake_domains domains);
 707
 708         uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 709         uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 710         uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 711         uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 712
 713         void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
 714                                 uint8_t val, bool trace);
 715         void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
 716                                 uint16_t val, bool trace);
 717         void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
 718                                 uint32_t val, bool trace);
 719 };
 720
 721 struct intel_forcewake_range {
 722         u32 start;
 723         u32 end;
 724
 725         enum forcewake_domains domains;
 726 };
 727
 728 struct intel_uncore {
 729         spinlock_t lock; /** lock is also taken in irq contexts. */
 730
 731         const struct intel_forcewake_range *fw_domains_table;
 732         unsigned int fw_domains_table_entries;
 733
 734         struct intel_uncore_funcs funcs;
 735
 736         unsigned fifo_count;
 737
 738         enum forcewake_domains fw_domains;
 739         enum forcewake_domains fw_domains_active;
 740
 741         struct intel_uncore_forcewake_domain {
 742                 struct drm_i915_private *i915;
 743                 enum forcewake_domain_id id;
 744                 enum forcewake_domains mask;
 745                 unsigned wake_count;
 746                 struct hrtimer timer;
 747                 i915_reg_t reg_set;
 748                 u32 val_set;
 749                 u32 val_clear;
 750                 i915_reg_t reg_ack;
 751                 i915_reg_t reg_post;
 752                 u32 val_reset;
 753         } fw_domain[FW_DOMAIN_ID_COUNT];
 754
 755         int unclaimed_mmio_check;
 756 };
 757
 758 /* Iterate over initialised fw domains */
 759 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
 760         for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
 761              (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
 762              (domain__)++) \
 763                 for_each_if ((mask__) & (domain__)->mask)
 764
 765 #define for_each_fw_domain(domain__, dev_priv__) \
 766         for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
 767
 768 #define CSR_VERSION(major, minor)       ((major) << 16 | (minor))
 769 #define CSR_VERSION_MAJOR(version)      ((version) >> 16)
 770 #define CSR_VERSION_MINOR(version)      ((version) & 0xffff)
 771
 772 struct intel_csr {
 773         struct work_struct work;
 774         const char *fw_path;
 775         uint32_t *dmc_payload;
 776         uint32_t dmc_fw_size;
 777         uint32_t version;
 778         uint32_t mmio_count;
 779         i915_reg_t mmioaddr[8];
 780         uint32_t mmiodata[8];
 781         uint32_t dc_state;
 782         uint32_t allowed_dc_mask;
 783 };
 784
 785 #define DEV_INFO_FOR_EACH_FLAG(func) \
 786         func(is_mobile); \
 787         func(is_lp); \
 788         func(is_alpha_support); \
 789         /* Keep has_* in alphabetical order */ \
 790         func(has_64bit_reloc); \
 791         func(has_aliasing_ppgtt); \
 792         func(has_csr); \
 793         func(has_ddi); \
 794         func(has_decoupled_mmio); \
 795         func(has_dp_mst); \
 796         func(has_fbc); \
 797         func(has_fpga_dbg); \
 798         func(has_full_ppgtt); \
 799         func(has_full_48bit_ppgtt); \
 800         func(has_gmbus_irq); \
 801         func(has_gmch_display); \
 802         func(has_guc); \
 803         func(has_hotplug); \
 804         func(has_hw_contexts); \
 805         func(has_l3_dpf); \
 806         func(has_llc); \
 807         func(has_logical_ring_contexts); \
 808         func(has_overlay); \
 809         func(has_pipe_cxsr); \
 810         func(has_pooled_eu); \
 811         func(has_psr); \
 812         func(has_rc6); \
 813         func(has_rc6p); \
 814         func(has_resource_streamer); \
 815         func(has_runtime_pm); \
 816         func(has_snoop); \
 817         func(cursor_needs_physical); \
 818         func(hws_needs_physical); \
 819         func(overlay_needs_physical); \
 820         func(supports_tv);
 821
 822 struct sseu_dev_info {
 823         u8 slice_mask;
 824         u8 subslice_mask;
 825         u8 eu_total;
 826         u8 eu_per_subslice;
 827         u8 min_eu_in_pool;
 828         /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
 829         u8 subslice_7eu[3];
 830         u8 has_slice_pg:1;
 831         u8 has_subslice_pg:1;
 832         u8 has_eu_pg:1;
 833 };
 834
 835 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
 836 {
 837         return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
 838 }
 839
 840 /* Keep in gen based order, and chronological order within a gen */
 841 enum intel_platform {
 842         INTEL_PLATFORM_UNINITIALIZED = 0,
 843         INTEL_I830,
 844         INTEL_I845G,
 845         INTEL_I85X,
 846         INTEL_I865G,
 847         INTEL_I915G,
 848         INTEL_I915GM,
 849         INTEL_I945G,
 850         INTEL_I945GM,
 851         INTEL_G33,
 852         INTEL_PINEVIEW,
 853         INTEL_I965G,
 854         INTEL_I965GM,
 855         INTEL_G45,
 856         INTEL_GM45,
 857         INTEL_IRONLAKE,
 858         INTEL_SANDYBRIDGE,
 859         INTEL_IVYBRIDGE,
 860         INTEL_VALLEYVIEW,
 861         INTEL_HASWELL,
 862         INTEL_BROADWELL,
 863         INTEL_CHERRYVIEW,
 864         INTEL_SKYLAKE,
 865         INTEL_BROXTON,
 866         INTEL_KABYLAKE,
 867         INTEL_GEMINILAKE,
 868 };
 869
 870 struct intel_device_info {
 871         u32 display_mmio_offset;
 872         u16 device_id;
 873         u8 num_pipes;
 874         u8 num_sprites[I915_MAX_PIPES];
 875         u8 gen;
 876         u16 gen_mask;
 877         enum intel_platform platform;
 878         u8 ring_mask; /* Rings supported by the HW */
 879         u8 num_rings;
 880 #define DEFINE_FLAG(name) u8 name:1
 881         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 882 #undef DEFINE_FLAG
 883         u16 ddb_size; /* in blocks */
 884         /* Register offsets for the various display pipes and transcoders */
 885         int pipe_offsets[I915_MAX_TRANSCODERS];
 886         int trans_offsets[I915_MAX_TRANSCODERS];
 887         int palette_offsets[I915_MAX_PIPES];
 888         int cursor_offsets[I915_MAX_PIPES];
 889
 890         /* Slice/subslice/EU info */
 891         struct sseu_dev_info sseu;
 892
 893         struct color_luts {
 894                 u16 degamma_lut_size;
 895                 u16 gamma_lut_size;
 896         } color;
 897 };
 898
 899 struct intel_display_error_state;
 900
 901 struct drm_i915_error_state {
 902         struct kref ref;
 903         struct timeval time;
 904         struct timeval boottime;
 905         struct timeval uptime;
 906
 907         struct drm_i915_private *i915;
 908
 909         char error_msg[128];
 910         bool simulated;
 911         int iommu;
 912         u32 reset_count;
 913         u32 suspend_count;
 914         struct intel_device_info device_info;
 915
 916         /* Generic register state */
 917         u32 eir;
 918         u32 pgtbl_er;
 919         u32 ier;
 920         u32 gtier[4];
 921         u32 ccid;
 922         u32 derrmr;
 923         u32 forcewake;
 924         u32 error; /* gen6+ */
 925         u32 err_int; /* gen7 */
 926         u32 fault_data0; /* gen8, gen9 */
 927         u32 fault_data1; /* gen8, gen9 */
 928         u32 done_reg;
 929         u32 gac_eco;
 930         u32 gam_ecochk;
 931         u32 gab_ctl;
 932         u32 gfx_mode;
 933
 934         u64 fence[I915_MAX_NUM_FENCES];
 935         struct intel_overlay_error_state *overlay;
 936         struct intel_display_error_state *display;
 937         struct drm_i915_error_object *semaphore;
 938         struct drm_i915_error_object *guc_log;
 939
 940         struct drm_i915_error_engine {
 941                 int engine_id;
 942                 /* Software tracked state */
 943                 bool waiting;
 944                 int num_waiters;
 945                 unsigned long hangcheck_timestamp;
 946                 bool hangcheck_stalled;
 947                 enum intel_engine_hangcheck_action hangcheck_action;
 948                 struct i915_address_space *vm;
 949                 int num_requests;
 950
 951                 /* position of active request inside the ring */
 952                 u32 rq_head, rq_post, rq_tail;
 953
 954                 /* our own tracking of ring head and tail */
 955                 u32 cpu_ring_head;
 956                 u32 cpu_ring_tail;
 957
 958                 u32 last_seqno;
 959
 960                 /* Register state */
 961                 u32 start;
 962                 u32 tail;
 963                 u32 head;
 964                 u32 ctl;
 965                 u32 mode;
 966                 u32 hws;
 967                 u32 ipeir;
 968                 u32 ipehr;
 969                 u32 bbstate;
 970                 u32 instpm;
 971                 u32 instps;
 972                 u32 seqno;
 973                 u64 bbaddr;
 974                 u64 acthd;
 975                 u32 fault_reg;
 976                 u64 faddr;
 977                 u32 rc_psmi; /* sleep state */
 978                 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
 979                 struct intel_instdone instdone;
 980
 981                 struct drm_i915_error_object {
 982                         u64 gtt_offset;
 983                         u64 gtt_size;
 984                         int page_count;
 985                         int unused;
 986                         u32 *pages[0];
 987                 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
 988
 989                 struct drm_i915_error_object *wa_ctx;
 990
 991                 struct drm_i915_error_request {
 992                         long jiffies;
 993                         pid_t pid;
 994                         u32 context;
 995                         int ban_score;
 996                         u32 seqno;
 997                         u32 head;
 998                         u32 tail;
 999                 } *requests, execlist[2];
1000
1001                 struct drm_i915_error_waiter {
1002                         char comm[TASK_COMM_LEN];
1003                         pid_t pid;
1004                         u32 seqno;
1005                 } *waiters;
1006
1007                 struct {
1008                         u32 gfx_mode;
1009                         union {
1010                                 u64 pdp[4];
1011                                 u32 pp_dir_base;
1012                         };
1013                 } vm_info;
1014
1015                 pid_t pid;
1016                 char comm[TASK_COMM_LEN];
1017                 int context_bans;
1018         } engine[I915_NUM_ENGINES];
1019
1020         struct drm_i915_error_buffer {
1021                 u32 size;
1022                 u32 name;
1023                 u32 rseqno[I915_NUM_ENGINES], wseqno;
1024                 u64 gtt_offset;
1025                 u32 read_domains;
1026                 u32 write_domain;
1027                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
1028                 u32 tiling:2;
1029                 u32 dirty:1;
1030                 u32 purgeable:1;
1031                 u32 userptr:1;
1032                 s32 engine:4;
1033                 u32 cache_level:3;
1034         } *active_bo[I915_NUM_ENGINES], *pinned_bo;
1035         u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
1036         struct i915_address_space *active_vm[I915_NUM_ENGINES];
1037 };
1038
1039 enum i915_cache_level {
1040         I915_CACHE_NONE = 0,
1041         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
1042         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
1043                               caches, eg sampler/render caches, and the
1044                               large Last-Level-Cache. LLC is coherent with
1045                               the CPU, but L3 is only visible to the GPU. */
1046         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1047 };
1048
1049 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1050
1051 #define DEFAULT_CONTEXT_HANDLE 0
1052
1053 /**
1054  * struct i915_gem_context - as the name implies, represents a context.
1055  * @ref: reference count.
1056  * @user_handle: userspace tracking identity for this context.
1057  * @remap_slice: l3 row remapping information.
1058  * @flags: context specific flags:
1059  *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
1060  * @file_priv: filp associated with this context (NULL for global default
1061  *             context).
1062  * @hang_stats: information about the role of this context in possible GPU
1063  *              hangs.
1064  * @ppgtt: virtual memory space used by this context.
1065  * @legacy_hw_ctx: render context backing object and whether it is correctly
1066  *                initialized (legacy ring submission mechanism only).
1067  * @link: link in the global list of contexts.
1068  *
1069  * Contexts are memory images used by the hardware to store copies of their
1070  * internal state.
1071  */
1072 struct i915_gem_context {
1073         struct kref ref;
1074         struct drm_i915_private *i915;
1075         struct drm_i915_file_private *file_priv;
1076         struct i915_hw_ppgtt *ppgtt;
1077         struct pid *pid;
1078         const char *name;
1079
1080         unsigned long flags;
1081 #define CONTEXT_NO_ZEROMAP              BIT(0)
1082 #define CONTEXT_NO_ERROR_CAPTURE        BIT(1)
1083
1084         /* Unique identifier for this context, used by the hw for tracking */
1085         unsigned int hw_id;
1086         u32 user_handle;
1087         int priority; /* greater priorities are serviced first */
1088
1089         u32 ggtt_alignment;
1090
1091         struct intel_context {
1092                 struct i915_vma *state;
1093                 struct intel_ring *ring;
1094                 uint32_t *lrc_reg_state;
1095                 u64 lrc_desc;
1096                 int pin_count;
1097                 bool initialised;
1098         } engine[I915_NUM_ENGINES];
1099         u32 ring_size;
1100         u32 desc_template;
1101         struct atomic_notifier_head status_notifier;
1102         bool execlists_force_single_submission;
1103
1104         struct list_head link;
1105
1106         u8 remap_slice;
1107         bool closed:1;
1108         bool bannable:1;
1109         bool banned:1;
1110
1111         unsigned int guilty_count; /* guilty of a hang */
1112         unsigned int active_count; /* active during hang */
1113
1114 #define CONTEXT_SCORE_GUILTY            10
1115 #define CONTEXT_SCORE_BAN_THRESHOLD     40
1116         /* Accumulated score of hangs caused by this context */
1117         int ban_score;
1118 };
1119
1120 enum fb_op_origin {
1121         ORIGIN_GTT,
1122         ORIGIN_CPU,
1123         ORIGIN_CS,
1124         ORIGIN_FLIP,
1125         ORIGIN_DIRTYFB,
1126 };
1127
1128 struct intel_fbc {
1129         /* This is always the inner lock when overlapping with struct_mutex and
1130          * it's the outer lock when overlapping with stolen_lock. */
1131         struct mutex lock;
1132         unsigned threshold;
1133         unsigned int possible_framebuffer_bits;
1134         unsigned int busy_bits;
1135         unsigned int visible_pipes_mask;
1136         struct intel_crtc *crtc;
1137
1138         struct drm_mm_node compressed_fb;
1139         struct drm_mm_node *compressed_llb;
1140
1141         bool false_color;
1142
1143         bool enabled;
1144         bool active;
1145
1146         bool underrun_detected;
1147         struct work_struct underrun_work;
1148
1149         struct intel_fbc_state_cache {
1150                 struct {
1151                         unsigned int mode_flags;
1152                         uint32_t hsw_bdw_pixel_rate;
1153                 } crtc;
1154
1155                 struct {
1156                         unsigned int rotation;
1157                         int src_w;
1158                         int src_h;
1159                         bool visible;
1160                 } plane;
1161
1162                 struct {
1163                         u64 ilk_ggtt_offset;
1164                         uint32_t pixel_format;
1165                         unsigned int stride;
1166                         int fence_reg;
1167                         unsigned int tiling_mode;
1168                 } fb;
1169         } state_cache;
1170
1171         struct intel_fbc_reg_params {
1172                 struct {
1173                         enum pipe pipe;
1174                         enum plane plane;
1175                         unsigned int fence_y_offset;
1176                 } crtc;
1177
1178                 struct {
1179                         u64 ggtt_offset;
1180                         uint32_t pixel_format;
1181                         unsigned int stride;
1182                         int fence_reg;
1183                 } fb;
1184
1185                 int cfb_size;
1186         } params;
1187
1188         struct intel_fbc_work {
1189                 bool scheduled;
1190                 u32 scheduled_vblank;
1191                 struct work_struct work;
1192         } work;
1193
1194         const char *no_fbc_reason;
1195 };
1196
1197 /**
1198  * HIGH_RR is the highest eDP panel refresh rate read from EDID
1199  * LOW_RR is the lowest eDP panel refresh rate found from EDID
1200  * parsing for same resolution.
1201  */
1202 enum drrs_refresh_rate_type {
1203         DRRS_HIGH_RR,
1204         DRRS_LOW_RR,
1205         DRRS_MAX_RR, /* RR count */
1206 };
1207
1208 enum drrs_support_type {
1209         DRRS_NOT_SUPPORTED = 0,
1210         STATIC_DRRS_SUPPORT = 1,
1211         SEAMLESS_DRRS_SUPPORT = 2
1212 };
1213
1214 struct intel_dp;
1215 struct i915_drrs {
1216         struct mutex mutex;
1217         struct delayed_work work;
1218         struct intel_dp *dp;
1219         unsigned busy_frontbuffer_bits;
1220         enum drrs_refresh_rate_type refresh_rate_type;
1221         enum drrs_support_type type;
1222 };
1223
1224 struct i915_psr {
1225         struct mutex lock;
1226         bool sink_support;
1227         bool source_ok;
1228         struct intel_dp *enabled;
1229         bool active;
1230         struct delayed_work work;
1231         unsigned busy_frontbuffer_bits;
1232         bool psr2_support;
1233         bool aux_frame_sync;
1234         bool link_standby;
1235 };
1236
1237 enum intel_pch {
1238         PCH_NONE = 0,   /* No PCH present */
1239         PCH_IBX,        /* Ibexpeak PCH */
1240         PCH_CPT,        /* Cougarpoint PCH */
1241         PCH_LPT,        /* Lynxpoint PCH */
1242         PCH_SPT,        /* Sunrisepoint PCH */
1243         PCH_KBP,        /* Kabypoint PCH */
1244         PCH_NOP,
1245 };
1246
1247 enum intel_sbi_destination {
1248         SBI_ICLK,
1249         SBI_MPHY,
1250 };
1251
1252 #define QUIRK_PIPEA_FORCE (1<<0)
1253 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1254 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1255 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1256 #define QUIRK_PIPEB_FORCE (1<<4)
1257 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1258
1259 struct intel_fbdev;
1260 struct intel_fbc_work;
1261
1262 struct intel_gmbus {
1263         struct i2c_adapter adapter;
1264 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1265         u32 force_bit;
1266         u32 reg0;
1267         i915_reg_t gpio_reg;
1268         struct i2c_algo_bit_data bit_algo;
1269         struct drm_i915_private *dev_priv;
1270 };
1271
1272 struct i915_suspend_saved_registers {
1273         u32 saveDSPARB;
1274         u32 saveFBC_CONTROL;
1275         u32 saveCACHE_MODE_0;
1276         u32 saveMI_ARB_STATE;
1277         u32 saveSWF0[16];
1278         u32 saveSWF1[16];
1279         u32 saveSWF3[3];
1280         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1281         u32 savePCH_PORT_HOTPLUG;
1282         u16 saveGCDGMBUS;
1283 };
1284
1285 struct vlv_s0ix_state {
1286         /* GAM */
1287         u32 wr_watermark;
1288         u32 gfx_prio_ctrl;
1289         u32 arb_mode;
1290         u32 gfx_pend_tlb0;
1291         u32 gfx_pend_tlb1;
1292         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1293         u32 media_max_req_count;
1294         u32 gfx_max_req_count;
1295         u32 render_hwsp;
1296         u32 ecochk;
1297         u32 bsd_hwsp;
1298         u32 blt_hwsp;
1299         u32 tlb_rd_addr;
1300
1301         /* MBC */
1302         u32 g3dctl;
1303         u32 gsckgctl;
1304         u32 mbctl;
1305
1306         /* GCP */
1307         u32 ucgctl1;
1308         u32 ucgctl3;
1309         u32 rcgctl1;
1310         u32 rcgctl2;
1311         u32 rstctl;
1312         u32 misccpctl;
1313
1314         /* GPM */
1315         u32 gfxpause;
1316         u32 rpdeuhwtc;
1317         u32 rpdeuc;
1318         u32 ecobus;
1319         u32 pwrdwnupctl;
1320         u32 rp_down_timeout;
1321         u32 rp_deucsw;
1322         u32 rcubmabdtmr;
1323         u32 rcedata;
1324         u32 spare2gh;
1325
1326         /* Display 1 CZ domain */
1327         u32 gt_imr;
1328         u32 gt_ier;
1329         u32 pm_imr;
1330         u32 pm_ier;
1331         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1332
1333         /* GT SA CZ domain */
1334         u32 tilectl;
1335         u32 gt_fifoctl;
1336         u32 gtlc_wake_ctrl;
1337         u32 gtlc_survive;
1338         u32 pmwgicz;
1339
1340         /* Display 2 CZ domain */
1341         u32 gu_ctl0;
1342         u32 gu_ctl1;
1343         u32 pcbr;
1344         u32 clock_gate_dis2;
1345 };
1346
1347 struct intel_rps_ei {
1348         u32 cz_clock;
1349         u32 render_c0;
1350         u32 media_c0;
1351 };
1352
1353 struct intel_gen6_power_mgmt {
1354         /*
1355          * work, interrupts_enabled and pm_iir are protected by
1356          * dev_priv->irq_lock
1357          */
1358         struct work_struct work;
1359         bool interrupts_enabled;
1360         u32 pm_iir;
1361
1362         /* PM interrupt bits that should never be masked */
1363         u32 pm_intr_keep;
1364
1365         /* Frequencies are stored in potentially platform dependent multiples.
1366          * In other words, *_freq needs to be multiplied by X to be interesting.
1367          * Soft limits are those which are used for the dynamic reclocking done
1368          * by the driver (raise frequencies under heavy loads, and lower for
1369          * lighter loads). Hard limits are those imposed by the hardware.
1370          *
1371          * A distinction is made for overclocking, which is never enabled by
1372          * default, and is considered to be above the hard limit if it's
1373          * possible at all.
1374          */
1375         u8 cur_freq;            /* Current frequency (cached, may not == HW) */
1376         u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
1377         u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
1378         u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
1379         u8 min_freq;            /* AKA RPn. Minimum frequency */
1380         u8 boost_freq;          /* Frequency to request when wait boosting */
1381         u8 idle_freq;           /* Frequency to request when we are idle */
1382         u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
1383         u8 rp1_freq;            /* "less than" RP0 power/freqency */
1384         u8 rp0_freq;            /* Non-overclocked max frequency. */
1385         u16 gpll_ref_freq;      /* vlv/chv GPLL reference frequency */
1386
1387         u8 up_threshold; /* Current %busy required to uplock */
1388         u8 down_threshold; /* Current %busy required to downclock */
1389
1390         int last_adj;
1391         enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1392
1393         spinlock_t client_lock;
1394         struct list_head clients;
1395         bool client_boost;
1396
1397         bool enabled;
1398         struct delayed_work autoenable_work;
1399         unsigned boosts;
1400
1401         /* manual wa residency calculations */
1402         struct intel_rps_ei up_ei, down_ei;
1403
1404         /*
1405          * Protects RPS/RC6 register access and PCU communication.
1406          * Must be taken after struct_mutex if nested. Note that
1407          * this lock may be held for long periods of time when
1408          * talking to hw - so only take it when talking to hw!
1409          */
1410         struct mutex hw_lock;
1411 };
1412
1413 /* defined intel_pm.c */
1414 extern spinlock_t mchdev_lock;
1415
1416 struct intel_ilk_power_mgmt {
1417         u8 cur_delay;
1418         u8 min_delay;
1419         u8 max_delay;
1420         u8 fmax;
1421         u8 fstart;
1422
1423         u64 last_count1;
1424         unsigned long last_time1;
1425         unsigned long chipset_power;
1426         u64 last_count2;
1427         u64 last_time2;
1428         unsigned long gfx_power;
1429         u8 corr;
1430
1431         int c_m;
1432         int r_t;
1433 };
1434
1435 struct drm_i915_private;
1436 struct i915_power_well;
1437
1438 struct i915_power_well_ops {
1439         /*
1440          * Synchronize the well's hw state to match the current sw state, for
1441          * example enable/disable it based on the current refcount. Called
1442          * during driver init and resume time, possibly after first calling
1443          * the enable/disable handlers.
1444          */
1445         void (*sync_hw)(struct drm_i915_private *dev_priv,
1446                         struct i915_power_well *power_well);
1447         /*
1448          * Enable the well and resources that depend on it (for example
1449          * interrupts located on the well). Called after the 0->1 refcount
1450          * transition.
1451          */
1452         void (*enable)(struct drm_i915_private *dev_priv,
1453                        struct i915_power_well *power_well);
1454         /*
1455          * Disable the well and resources that depend on it. Called after
1456          * the 1->0 refcount transition.
1457          */
1458         void (*disable)(struct drm_i915_private *dev_priv,
1459                         struct i915_power_well *power_well);
1460         /* Returns the hw enabled state. */
1461         bool (*is_enabled)(struct drm_i915_private *dev_priv,
1462                            struct i915_power_well *power_well);
1463 };
1464
1465 /* Power well structure for haswell */
1466 struct i915_power_well {
1467         const char *name;
1468         bool always_on;
1469         /* power well enable/disable usage count */
1470         int count;
1471         /* cached hw enabled state */
1472         bool hw_enabled;
1473         unsigned long domains;
1474         /* unique identifier for this power well */
1475         unsigned long id;
1476         /*
1477          * Arbitraty data associated with this power well. Platform and power
1478          * well specific.
1479          */
1480         unsigned long data;
1481         const struct i915_power_well_ops *ops;
1482 };
1483
1484 struct i915_power_domains {
1485         /*
1486          * Power wells needed for initialization at driver init and suspend
1487          * time are on. They are kept on until after the first modeset.
1488          */
1489         bool init_power_on;
1490         bool initializing;
1491         int power_well_count;
1492
1493         struct mutex lock;
1494         int domain_use_count[POWER_DOMAIN_NUM];
1495         struct i915_power_well *power_wells;
1496 };
1497
1498 #define MAX_L3_SLICES 2
1499 struct intel_l3_parity {
1500         u32 *remap_info[MAX_L3_SLICES];
1501         struct work_struct error_work;
1502         int which_slice;
1503 };
1504
1505 struct i915_gem_mm {
1506         /** Memory allocator for GTT stolen memory */
1507         struct drm_mm stolen;
1508         /** Protects the usage of the GTT stolen memory allocator. This is
1509          * always the inner lock when overlapping with struct_mutex. */
1510         struct mutex stolen_lock;
1511
1512         /** List of all objects in gtt_space. Used to restore gtt
1513          * mappings on resume */
1514         struct list_head bound_list;
1515         /**
1516          * List of objects which are not bound to the GTT (thus
1517          * are idle and not used by the GPU). These objects may or may
1518          * not actually have any pages attached.
1519          */
1520         struct list_head unbound_list;
1521
1522         /** List of all objects in gtt_space, currently mmaped by userspace.
1523          * All objects within this list must also be on bound_list.
1524          */
1525         struct list_head userfault_list;
1526
1527         /**
1528          * List of objects which are pending destruction.
1529          */
1530         struct llist_head free_list;
1531         struct work_struct free_work;
1532
1533         /** Usable portion of the GTT for GEM */
1534         unsigned long stolen_base; /* limited to low memory (32-bit) */
1535
1536         /** PPGTT used for aliasing the PPGTT with the GTT */
1537         struct i915_hw_ppgtt *aliasing_ppgtt;
1538
1539         struct notifier_block oom_notifier;
1540         struct notifier_block vmap_notifier;
1541         struct shrinker shrinker;
1542
1543         /** LRU list of objects with fence regs on them. */
1544         struct list_head fence_list;
1545
1546         /**
1547          * Are we in a non-interruptible section of code like
1548          * modesetting?
1549          */
1550         bool interruptible;
1551
1552         /* the indicator for dispatch video commands on two BSD rings */
1553         atomic_t bsd_engine_dispatch_index;
1554
1555         /** Bit 6 swizzling required for X tiling */
1556         uint32_t bit_6_swizzle_x;
1557         /** Bit 6 swizzling required for Y tiling */
1558         uint32_t bit_6_swizzle_y;
1559
1560         /* accounting, useful for userland debugging */
1561         spinlock_t object_stat_lock;
1562         u64 object_memory;
1563         u32 object_count;
1564 };
1565
1566 struct drm_i915_error_state_buf {
1567         struct drm_i915_private *i915;
1568         unsigned bytes;
1569         unsigned size;
1570         int err;
1571         u8 *buf;
1572         loff_t start;
1573         loff_t pos;
1574 };
1575
1576 struct i915_error_state_file_priv {
1577         struct drm_i915_private *i915;
1578         struct drm_i915_error_state *error;
1579 };
1580
1581 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1582 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1583
1584 #define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
1585 #define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */
1586
1587 struct i915_gpu_error {
1588         /* For hangcheck timer */
1589 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1590 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1591
1592         struct delayed_work hangcheck_work;
1593
1594         /* For reset and error_state handling. */
1595         spinlock_t lock;
1596         /* Protected by the above dev->gpu_error.lock. */
1597         struct drm_i915_error_state *first_error;
1598
1599         unsigned long missed_irq_rings;
1600
1601         /**
1602          * State variable controlling the reset flow and count
1603          *
1604          * This is a counter which gets incremented when reset is triggered,
1605          *
1606          * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1607          * meaning that any waiters holding onto the struct_mutex should
1608          * relinquish the lock immediately in order for the reset to start.
1609          *
1610          * If reset is not completed succesfully, the I915_WEDGE bit is
1611          * set meaning that hardware is terminally sour and there is no
1612          * recovery. All waiters on the reset_queue will be woken when
1613          * that happens.
1614          *
1615          * This counter is used by the wait_seqno code to notice that reset
1616          * event happened and it needs to restart the entire ioctl (since most
1617          * likely the seqno it waited for won't ever signal anytime soon).
1618          *
1619          * This is important for lock-free wait paths, where no contended lock
1620          * naturally enforces the correct ordering between the bail-out of the
1621          * waiter and the gpu reset work code.
1622          */
1623         unsigned long reset_count;
1624
1625         unsigned long flags;
1626 #define I915_RESET_IN_PROGRESS  0
1627 #define I915_WEDGED             (BITS_PER_LONG - 1)
1628
1629         /**
1630          * Waitqueue to signal when a hang is detected. Used to for waiters
1631          * to release the struct_mutex for the reset to procede.
1632          */
1633         wait_queue_head_t wait_queue;
1634
1635         /**
1636          * Waitqueue to signal when the reset has completed. Used by clients
1637          * that wait for dev_priv->mm.wedged to settle.
1638          */
1639         wait_queue_head_t reset_queue;
1640
1641         /* For missed irq/seqno simulation. */
1642         unsigned long test_irq_rings;
1643 };
1644
1645 enum modeset_restore {
1646         MODESET_ON_LID_OPEN,
1647         MODESET_DONE,
1648         MODESET_SUSPENDED,
1649 };
1650
1651 #define DP_AUX_A 0x40
1652 #define DP_AUX_B 0x10
1653 #define DP_AUX_C 0x20
1654 #define DP_AUX_D 0x30
1655
1656 #define DDC_PIN_B  0x05
1657 #define DDC_PIN_C  0x04
1658 #define DDC_PIN_D  0x06
1659
1660 struct ddi_vbt_port_info {
1661         /*
1662          * This is an index in the HDMI/DVI DDI buffer translation table.
1663          * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1664          * populate this field.
1665          */
1666 #define HDMI_LEVEL_SHIFT_UNKNOWN        0xff
1667         uint8_t hdmi_level_shift;
1668
1669         uint8_t supports_dvi:1;
1670         uint8_t supports_hdmi:1;
1671         uint8_t supports_dp:1;
1672         uint8_t supports_edp:1;
1673
1674         uint8_t alternate_aux_channel;
1675         uint8_t alternate_ddc_pin;
1676
1677         uint8_t dp_boost_level;
1678         uint8_t hdmi_boost_level;
1679 };
1680
1681 enum psr_lines_to_wait {
1682         PSR_0_LINES_TO_WAIT = 0,
1683         PSR_1_LINE_TO_WAIT,
1684         PSR_4_LINES_TO_WAIT,
1685         PSR_8_LINES_TO_WAIT
1686 };
1687
1688 struct intel_vbt_data {
1689         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1690         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1691
1692         /* Feature bits */
1693         unsigned int int_tv_support:1;
1694         unsigned int lvds_dither:1;
1695         unsigned int lvds_vbt:1;
1696         unsigned int int_crt_support:1;
1697         unsigned int lvds_use_ssc:1;
1698         unsigned int display_clock_mode:1;
1699         unsigned int fdi_rx_polarity_inverted:1;
1700         unsigned int panel_type:4;
1701         int lvds_ssc_freq;
1702         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1703
1704         enum drrs_support_type drrs_type;
1705
1706         struct {
1707                 int rate;
1708                 int lanes;
1709                 int preemphasis;
1710                 int vswing;
1711                 bool low_vswing;
1712                 bool initialized;
1713                 bool support;
1714                 int bpp;
1715                 struct edp_power_seq pps;
1716         } edp;
1717
1718         struct {
1719                 bool full_link;
1720                 bool require_aux_wakeup;
1721                 int idle_frames;
1722                 enum psr_lines_to_wait lines_to_wait;
1723                 int tp1_wakeup_time;
1724                 int tp2_tp3_wakeup_time;
1725         } psr;
1726
1727         struct {
1728                 u16 pwm_freq_hz;
1729                 bool present;
1730                 bool active_low_pwm;
1731                 u8 min_brightness;      /* min_brightness/255 of max */
1732                 u8 controller;          /* brightness controller number */
1733                 enum intel_backlight_type type;
1734         } backlight;
1735
1736         /* MIPI DSI */
1737         struct {
1738                 u16 panel_id;
1739                 struct mipi_config *config;
1740                 struct mipi_pps_data *pps;
1741                 u8 seq_version;
1742                 u32 size;
1743                 u8 *data;
1744                 const u8 *sequence[MIPI_SEQ_MAX];
1745         } dsi;
1746
1747         int crt_ddc_pin;
1748
1749         int child_dev_num;
1750         union child_device_config *child_dev;
1751
1752         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1753         struct sdvo_device_mapping sdvo_mappings[2];
1754 };
1755
1756 enum intel_ddb_partitioning {
1757         INTEL_DDB_PART_1_2,
1758         INTEL_DDB_PART_5_6, /* IVB+ */
1759 };
1760
1761 struct intel_wm_level {
1762         bool enable;
1763         uint32_t pri_val;
1764         uint32_t spr_val;
1765         uint32_t cur_val;
1766         uint32_t fbc_val;
1767 };
1768
1769 struct ilk_wm_values {
1770         uint32_t wm_pipe[3];
1771         uint32_t wm_lp[3];
1772         uint32_t wm_lp_spr[3];
1773         uint32_t wm_linetime[3];
1774         bool enable_fbc_wm;
1775         enum intel_ddb_partitioning partitioning;
1776 };
1777
1778 struct vlv_pipe_wm {
1779         uint16_t plane[I915_MAX_PLANES];
1780 };
1781
1782 struct vlv_sr_wm {
1783         uint16_t plane;
1784         uint16_t cursor;
1785 };
1786
1787 struct vlv_wm_ddl_values {
1788         uint8_t plane[I915_MAX_PLANES];
1789 };
1790
1791 struct vlv_wm_values {
1792         struct vlv_pipe_wm pipe[3];
1793         struct vlv_sr_wm sr;
1794         struct vlv_wm_ddl_values ddl[3];
1795         uint8_t level;
1796         bool cxsr;
1797 };
1798
1799 struct skl_ddb_entry {
1800         uint16_t start, end;    /* in number of blocks, 'end' is exclusive */
1801 };
1802
1803 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1804 {
1805         return entry->end - entry->start;
1806 }
1807
1808 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1809                                        const struct skl_ddb_entry *e2)
1810 {
1811         if (e1->start == e2->start && e1->end == e2->end)
1812                 return true;
1813
1814         return false;
1815 }
1816
1817 struct skl_ddb_allocation {
1818         struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1819         struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1820 };
1821
1822 struct skl_wm_values {
1823         unsigned dirty_pipes;
1824         struct skl_ddb_allocation ddb;
1825 };
1826
1827 struct skl_wm_level {
1828         bool plane_en;
1829         uint16_t plane_res_b;
1830         uint8_t plane_res_l;
1831 };
1832
1833 /*
1834  * This struct helps tracking the state needed for runtime PM, which puts the
1835  * device in PCI D3 state. Notice that when this happens, nothing on the
1836  * graphics device works, even register access, so we don't get interrupts nor
1837  * anything else.
1838  *
1839  * Every piece of our code that needs to actually touch the hardware needs to
1840  * either call intel_runtime_pm_get or call intel_display_power_get with the
1841  * appropriate power domain.
1842  *
1843  * Our driver uses the autosuspend delay feature, which means we'll only really
1844  * suspend if we stay with zero refcount for a certain amount of time. The
1845  * default value is currently very conservative (see intel_runtime_pm_enable), but
1846  * it can be changed with the standard runtime PM files from sysfs.
1847  *
1848  * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1849  * goes back to false exactly before we reenable the IRQs. We use this variable
1850  * to check if someone is trying to enable/disable IRQs while they're supposed
1851  * to be disabled. This shouldn't happen and we'll print some error messages in
1852  * case it happens.
1853  *
1854  * For more, read the Documentation/power/runtime_pm.txt.
1855  */
1856 struct i915_runtime_pm {
1857         atomic_t wakeref_count;
1858         bool suspended;
1859         bool irqs_enabled;
1860 };
1861
1862 enum intel_pipe_crc_source {
1863         INTEL_PIPE_CRC_SOURCE_NONE,
1864         INTEL_PIPE_CRC_SOURCE_PLANE1,
1865         INTEL_PIPE_CRC_SOURCE_PLANE2,
1866         INTEL_PIPE_CRC_SOURCE_PF,
1867         INTEL_PIPE_CRC_SOURCE_PIPE,
1868         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1869         INTEL_PIPE_CRC_SOURCE_TV,
1870         INTEL_PIPE_CRC_SOURCE_DP_B,
1871         INTEL_PIPE_CRC_SOURCE_DP_C,
1872         INTEL_PIPE_CRC_SOURCE_DP_D,
1873         INTEL_PIPE_CRC_SOURCE_AUTO,
1874         INTEL_PIPE_CRC_SOURCE_MAX,
1875 };
1876
1877 struct intel_pipe_crc_entry {
1878         uint32_t frame;
1879         uint32_t crc[5];
1880 };
1881
1882 #define INTEL_PIPE_CRC_ENTRIES_NR       128
1883 struct intel_pipe_crc {
1884         spinlock_t lock;
1885         bool opened;            /* exclusive access to the result file */
1886         struct intel_pipe_crc_entry *entries;
1887         enum intel_pipe_crc_source source;
1888         int head, tail;
1889         wait_queue_head_t wq;
1890 };
1891
1892 struct i915_frontbuffer_tracking {
1893         spinlock_t lock;
1894
1895         /*
1896          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1897          * scheduled flips.
1898          */
1899         unsigned busy_bits;
1900         unsigned flip_bits;
1901 };
1902
1903 struct i915_wa_reg {
1904         i915_reg_t addr;
1905         u32 value;
1906         /* bitmask representing WA bits */
1907         u32 mask;
1908 };
1909
1910 /*
1911  * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1912  * allowing it for RCS as we don't foresee any requirement of having
1913  * a whitelist for other engines. When it is really required for
1914  * other engines then the limit need to be increased.
1915  */
1916 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1917
1918 struct i915_workarounds {
1919         struct i915_wa_reg reg[I915_MAX_WA_REGS];
1920         u32 count;
1921         u32 hw_whitelist_count[I915_NUM_ENGINES];
1922 };
1923
1924 struct i915_virtual_gpu {
1925         bool active;
1926 };
1927
1928 /* used in computing the new watermarks state */
1929 struct intel_wm_config {
1930         unsigned int num_pipes_active;
1931         bool sprites_enabled;
1932         bool sprites_scaled;
1933 };
1934
1935 struct i915_oa_format {
1936         u32 format;
1937         int size;
1938 };
1939
1940 struct i915_oa_reg {
1941         i915_reg_t addr;
1942         u32 value;
1943 };
1944
1945 struct i915_perf_stream;
1946
1947 /**
1948  * struct i915_perf_stream_ops - the OPs to support a specific stream type
1949  */
1950 struct i915_perf_stream_ops {
1951         /**
1952          * @enable: Enables the collection of HW samples, either in response to
1953          * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1954          * without `I915_PERF_FLAG_DISABLED`.
1955          */
1956         void (*enable)(struct i915_perf_stream *stream);
1957
1958         /**
1959          * @disable: Disables the collection of HW samples, either in response
1960          * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1961          * the stream.
1962          */
1963         void (*disable)(struct i915_perf_stream *stream);
1964
1965         /**
1966          * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1967          * once there is something ready to read() for the stream
1968          */
1969         void (*poll_wait)(struct i915_perf_stream *stream,
1970                           struct file *file,
1971                           poll_table *wait);
1972
1973         /**
1974          * @wait_unlocked: For handling a blocking read, wait until there is
1975          * something to ready to read() for the stream. E.g. wait on the same
1976          * wait queue that would be passed to poll_wait().
1977          */
1978         int (*wait_unlocked)(struct i915_perf_stream *stream);
1979
1980         /**
1981          * @read: Copy buffered metrics as records to userspace
1982          * **buf**: the userspace, destination buffer
1983          * **count**: the number of bytes to copy, requested by userspace
1984          * **offset**: zero at the start of the read, updated as the read
1985          * proceeds, it represents how many bytes have been copied so far and
1986          * the buffer offset for copying the next record.
1987          *
1988          * Copy as many buffered i915 perf samples and records for this stream
1989          * to userspace as will fit in the given buffer.
1990          *
1991          * Only write complete records; returning -%ENOSPC if there isn't room
1992          * for a complete record.
1993          *
1994          * Return any error condition that results in a short read such as
1995          * -%ENOSPC or -%EFAULT, even though these may be squashed before
1996          * returning to userspace.
1997          */
1998         int (*read)(struct i915_perf_stream *stream,
1999                     char __user *buf,
2000                     size_t count,
2001                     size_t *offset);
2002
2003         /**
2004          * @destroy: Cleanup any stream specific resources.
2005          *
2006          * The stream will always be disabled before this is called.
2007          */
2008         void (*destroy)(struct i915_perf_stream *stream);
2009 };
2010
2011 /**
2012  * struct i915_perf_stream - state for a single open stream FD
2013  */
2014 struct i915_perf_stream {
2015         /**
2016          * @dev_priv: i915 drm device
2017          */
2018         struct drm_i915_private *dev_priv;
2019
2020         /**
2021          * @link: Links the stream into ``&drm_i915_private->streams``
2022          */
2023         struct list_head link;
2024
2025         /**
2026          * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
2027          * properties given when opening a stream, representing the contents
2028          * of a single sample as read() by userspace.
2029          */
2030         u32 sample_flags;
2031
2032         /**
2033          * @sample_size: Considering the configured contents of a sample
2034          * combined with the required header size, this is the total size
2035          * of a single sample record.
2036          */
2037         int sample_size;
2038
2039         /**
2040          * @ctx: %NULL if measuring system-wide across all contexts or a
2041          * specific context that is being monitored.
2042          */
2043         struct i915_gem_context *ctx;
2044
2045         /**
2046          * @enabled: Whether the stream is currently enabled, considering
2047          * whether the stream was opened in a disabled state and based
2048          * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
2049          */
2050         bool enabled;
2051
2052         /**
2053          * @ops: The callbacks providing the implementation of this specific
2054          * type of configured stream.
2055          */
2056         const struct i915_perf_stream_ops *ops;
2057 };
2058
2059 /**
2060  * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2061  */
2062 struct i915_oa_ops {
2063         /**
2064          * @init_oa_buffer: Resets the head and tail pointers of the
2065          * circular buffer for periodic OA reports.
2066          *
2067          * Called when first opening a stream for OA metrics, but also may be
2068          * called in response to an OA buffer overflow or other error
2069          * condition.
2070          *
2071          * Note it may be necessary to clear the full OA buffer here as part of
2072          * maintaining the invariable that new reports must be written to
2073          * zeroed memory for us to be able to reliable detect if an expected
2074          * report has not yet landed in memory.  (At least on Haswell the OA
2075          * buffer tail pointer is not synchronized with reports being visible
2076          * to the CPU)
2077          */
2078         void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2079
2080         /**
2081          * @enable_metric_set: Applies any MUX configuration to set up the
2082          * Boolean and Custom (B/C) counters that are part of the counter
2083          * reports being sampled. May apply system constraints such as
2084          * disabling EU clock gating as required.
2085          */
2086         int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2087
2088         /**
2089          * @disable_metric_set: Remove system constraints associated with using
2090          * the OA unit.
2091          */
2092         void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2093
2094         /**
2095          * @oa_enable: Enable periodic sampling
2096          */
2097         void (*oa_enable)(struct drm_i915_private *dev_priv);
2098
2099         /**
2100          * @oa_disable: Disable periodic sampling
2101          */
2102         void (*oa_disable)(struct drm_i915_private *dev_priv);
2103
2104         /**
2105          * @read: Copy data from the circular OA buffer into a given userspace
2106          * buffer.
2107          */
2108         int (*read)(struct i915_perf_stream *stream,
2109                     char __user *buf,
2110                     size_t count,
2111                     size_t *offset);
2112
2113         /**
2114          * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
2115          *
2116          * This is either called via fops or the poll check hrtimer (atomic
2117          * ctx) without any locks taken.
2118          *
2119          * It's safe to read OA config state here unlocked, assuming that this
2120          * is only called while the stream is enabled, while the global OA
2121          * configuration can't be modified.
2122          *
2123          * Efficiency is more important than avoiding some false positives
2124          * here, which will be handled gracefully - likely resulting in an
2125          * %EAGAIN error for userspace.
2126          */
2127         bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
2128 };
2129
2130 struct drm_i915_private {
2131         struct drm_device drm;
2132
2133         struct kmem_cache *objects;
2134         struct kmem_cache *vmas;
2135         struct kmem_cache *requests;
2136         struct kmem_cache *dependencies;
2137
2138         const struct intel_device_info info;
2139
2140         int relative_constants_mode;
2141
2142         void __iomem *regs;
2143
2144         struct intel_uncore uncore;
2145
2146         struct i915_virtual_gpu vgpu;
2147
2148         struct intel_gvt *gvt;
2149
2150         struct intel_guc guc;
2151
2152         struct intel_csr csr;
2153
2154         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2155
2156         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2157          * controller on different i2c buses. */
2158         struct mutex gmbus_mutex;
2159
2160         /**
2161          * Base address of the gmbus and gpio block.
2162          */
2163         uint32_t gpio_mmio_base;
2164
2165         /* MMIO base address for MIPI regs */
2166         uint32_t mipi_mmio_base;
2167
2168         uint32_t psr_mmio_base;
2169
2170         uint32_t pps_mmio_base;
2171
2172         wait_queue_head_t gmbus_wait_queue;
2173
2174         struct pci_dev *bridge_dev;
2175         struct i915_gem_context *kernel_context;
2176         struct intel_engine_cs *engine[I915_NUM_ENGINES];
2177         struct i915_vma *semaphore;
2178
2179         struct drm_dma_handle *status_page_dmah;
2180         struct resource mch_res;
2181
2182         /* protects the irq masks */
2183         spinlock_t irq_lock;
2184
2185         /* protects the mmio flip data */
2186         spinlock_t mmio_flip_lock;
2187
2188         bool display_irqs_enabled;
2189
2190         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2191         struct pm_qos_request pm_qos;
2192
2193         /* Sideband mailbox protection */
2194         struct mutex sb_lock;
2195
2196         /** Cached value of IMR to avoid reads in updating the bitfield */
2197         union {
2198                 u32 irq_mask;
2199                 u32 de_irq_mask[I915_MAX_PIPES];
2200         };
2201         u32 gt_irq_mask;
2202         u32 pm_imr;
2203         u32 pm_ier;
2204         u32 pm_rps_events;
2205         u32 pm_guc_events;
2206         u32 pipestat_irq_mask[I915_MAX_PIPES];
2207
2208         struct i915_hotplug hotplug;
2209         struct intel_fbc fbc;
2210         struct i915_drrs drrs;
2211         struct intel_opregion opregion;
2212         struct intel_vbt_data vbt;
2213
2214         bool preserve_bios_swizzle;
2215
2216         /* overlay */
2217         struct intel_overlay *overlay;
2218
2219         /* backlight registers and fields in struct intel_panel */
2220         struct mutex backlight_lock;
2221
2222         /* LVDS info */
2223         bool no_aux_handshake;
2224
2225         /* protects panel power sequencer state */
2226         struct mutex pps_mutex;
2227
2228         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
2229         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2230
2231         unsigned int fsb_freq, mem_freq, is_ddr3;
2232         unsigned int skl_preferred_vco_freq;
2233         unsigned int cdclk_freq, max_cdclk_freq;
2234
2235         /*
2236          * For reading holding any crtc lock is sufficient,
2237          * for writing must hold all of them.
2238          */
2239         unsigned int atomic_cdclk_freq;
2240
2241         unsigned int max_dotclk_freq;
2242         unsigned int rawclk_freq;
2243         unsigned int hpll_freq;
2244         unsigned int czclk_freq;
2245
2246         struct {
2247                 unsigned int vco, ref;
2248         } cdclk_pll;
2249
2250         /**
2251          * wq - Driver workqueue for GEM.
2252          *
2253          * NOTE: Work items scheduled here are not allowed to grab any modeset
2254          * locks, for otherwise the flushing done in the pageflip code will
2255          * result in deadlocks.
2256          */
2257         struct workqueue_struct *wq;
2258
2259         /* Display functions */
2260         struct drm_i915_display_funcs display;
2261
2262         /* PCH chipset type */
2263         enum intel_pch pch_type;
2264         unsigned short pch_id;
2265
2266         unsigned long quirks;
2267
2268         enum modeset_restore modeset_restore;
2269         struct mutex modeset_restore_lock;
2270         struct drm_atomic_state *modeset_restore_state;
2271         struct drm_modeset_acquire_ctx reset_ctx;
2272
2273         struct list_head vm_list; /* Global list of all address spaces */
2274         struct i915_ggtt ggtt; /* VM representing the global address space */
2275
2276         struct i915_gem_mm mm;
2277         DECLARE_HASHTABLE(mm_structs, 7);
2278         struct mutex mm_lock;
2279
2280         /* The hw wants to have a stable context identifier for the lifetime
2281          * of the context (for OA, PASID, faults, etc). This is limited
2282          * in execlists to 21 bits.
2283          */
2284         struct ida context_hw_ida;
2285 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2286
2287         /* Kernel Modesetting */
2288
2289         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2290         struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2291         wait_queue_head_t pending_flip_queue;
2292
2293 #ifdef CONFIG_DEBUG_FS
2294         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2295 #endif
2296
2297         /* dpll and cdclk state is protected by connection_mutex */
2298         int num_shared_dpll;
2299         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2300         const struct intel_dpll_mgr *dpll_mgr;
2301
2302         /*
2303          * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2304          * Must be global rather than per dpll, because on some platforms
2305          * plls share registers.
2306          */
2307         struct mutex dpll_lock;
2308
2309         unsigned int active_crtcs;
2310         unsigned int min_pixclk[I915_MAX_PIPES];
2311
2312         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2313
2314         struct i915_workarounds workarounds;
2315
2316         struct i915_frontbuffer_tracking fb_tracking;
2317
2318         u16 orig_clock;
2319
2320         bool mchbar_need_disable;
2321
2322         struct intel_l3_parity l3_parity;
2323
2324         /* Cannot be determined by PCIID. You must always read a register. */
2325         u32 edram_cap;
2326
2327         /* gen6+ rps state */
2328         struct intel_gen6_power_mgmt rps;
2329
2330         /* ilk-only ips/rps state. Everything in here is protected by the global
2331          * mchdev_lock in intel_pm.c */
2332         struct intel_ilk_power_mgmt ips;
2333
2334         struct i915_power_domains power_domains;
2335
2336         struct i915_psr psr;
2337
2338         struct i915_gpu_error gpu_error;
2339
2340         struct drm_i915_gem_object *vlv_pctx;
2341
2342 #ifdef CONFIG_DRM_FBDEV_EMULATION
2343         /* list of fbdev register on this device */
2344         struct intel_fbdev *fbdev;
2345         struct work_struct fbdev_suspend_work;
2346 #endif
2347
2348         struct drm_property *broadcast_rgb_property;
2349         struct drm_property *force_audio_property;
2350
2351         /* hda/i915 audio component */
2352         struct i915_audio_component *audio_component;
2353         bool audio_component_registered;
2354         /**
2355          * av_mutex - mutex for audio/video sync
2356          *
2357          */
2358         struct mutex av_mutex;
2359
2360         uint32_t hw_context_size;
2361         struct list_head context_list;
2362
2363         u32 fdi_rx_config;
2364
2365         /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2366         u32 chv_phy_control;
2367         /*
2368          * Shadows for CHV DPLL_MD regs to keep the state
2369          * checker somewhat working in the presence hardware
2370          * crappiness (can't read out DPLL_MD for pipes B & C).
2371          */
2372         u32 chv_dpll_md[I915_MAX_PIPES];
2373         u32 bxt_phy_grc;
2374
2375         u32 suspend_count;
2376         bool suspended_to_idle;
2377         struct i915_suspend_saved_registers regfile;
2378         struct vlv_s0ix_state vlv_s0ix_state;
2379
2380         enum {
2381                 I915_SAGV_UNKNOWN = 0,
2382                 I915_SAGV_DISABLED,
2383                 I915_SAGV_ENABLED,
2384                 I915_SAGV_NOT_CONTROLLED
2385         } sagv_status;
2386
2387         struct {
2388                 /* protects DSPARB registers on pre-g4x/vlv/chv */
2389                 spinlock_t dsparb_lock;
2390
2391                 /*
2392                  * Raw watermark latency values:
2393                  * in 0.1us units for WM0,
2394                  * in 0.5us units for WM1+.
2395                  */
2396                 /* primary */
2397                 uint16_t pri_latency[5];
2398                 /* sprite */
2399                 uint16_t spr_latency[5];
2400                 /* cursor */
2401                 uint16_t cur_latency[5];
2402                 /*
2403                  * Raw watermark memory latency values
2404                  * for SKL for all 8 levels
2405                  * in 1us units.
2406                  */
2407                 uint16_t skl_latency[8];
2408
2409                 /* current hardware state */
2410                 union {
2411                         struct ilk_wm_values hw;
2412                         struct skl_wm_values skl_hw;
2413                         struct vlv_wm_values vlv;
2414                 };
2415
2416                 uint8_t max_level;
2417
2418                 /*
2419                  * Should be held around atomic WM register writing; also
2420                  * protects * intel_crtc->wm.active and
2421                  * cstate->wm.need_postvbl_update.
2422                  */
2423                 struct mutex wm_mutex;
2424
2425                 /*
2426                  * Set during HW readout of watermarks/DDB.  Some platforms
2427                  * need to know when we're still using BIOS-provided values
2428                  * (which we don't fully trust).
2429                  */
2430                 bool distrust_bios_wm;
2431         } wm;
2432
2433         struct i915_runtime_pm pm;
2434
2435         struct {
2436                 bool initialized;
2437
2438                 struct kobject *metrics_kobj;
2439                 struct ctl_table_header *sysctl_header;
2440
2441                 struct mutex lock;
2442                 struct list_head streams;
2443
2444                 spinlock_t hook_lock;
2445
2446                 struct {
2447                         struct i915_perf_stream *exclusive_stream;
2448
2449                         u32 specific_ctx_id;
2450
2451                         struct hrtimer poll_check_timer;
2452                         wait_queue_head_t poll_wq;
2453                         bool pollin;
2454
2455                         bool periodic;
2456                         int period_exponent;
2457                         int timestamp_frequency;
2458
2459                         int tail_margin;
2460
2461                         int metrics_set;
2462
2463                         const struct i915_oa_reg *mux_regs;
2464                         int mux_regs_len;
2465                         const struct i915_oa_reg *b_counter_regs;
2466                         int b_counter_regs_len;
2467
2468                         struct {
2469                                 struct i915_vma *vma;
2470                                 u8 *vaddr;
2471                                 int format;
2472                                 int format_size;
2473                         } oa_buffer;
2474
2475                         u32 gen7_latched_oastatus1;
2476
2477                         struct i915_oa_ops ops;
2478                         const struct i915_oa_format *oa_formats;
2479                         int n_builtin_sets;
2480                 } oa;
2481         } perf;
2482
2483         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2484         struct {
2485                 void (*resume)(struct drm_i915_private *);
2486                 void (*cleanup_engine)(struct intel_engine_cs *engine);
2487
2488                 struct list_head timelines;
2489                 struct i915_gem_timeline global_timeline;
2490                 u32 active_requests;
2491
2492                 /**
2493                  * Is the GPU currently considered idle, or busy executing
2494                  * userspace requests? Whilst idle, we allow runtime power
2495                  * management to power down the hardware and display clocks.
2496                  * In order to reduce the effect on performance, there
2497                  * is a slight delay before we do so.
2498                  */
2499                 bool awake;
2500
2501                 /**
2502                  * We leave the user IRQ off as much as possible,
2503                  * but this means that requests will finish and never
2504                  * be retired once the system goes idle. Set a timer to
2505                  * fire periodically while the ring is running. When it
2506                  * fires, go retire requests.
2507                  */
2508                 struct delayed_work retire_work;
2509
2510                 /**
2511                  * When we detect an idle GPU, we want to turn on
2512                  * powersaving features. So once we see that there
2513                  * are no more requests outstanding and no more
2514                  * arrive within a small period of time, we fire
2515                  * off the idle_work.
2516                  */
2517                 struct delayed_work idle_work;
2518
2519                 ktime_t last_init_time;
2520         } gt;
2521
2522         /* perform PHY state sanity checks? */
2523         bool chv_phy_assert[2];
2524
2525         bool ipc_enabled;
2526
2527         /* Used to save the pipe-to-encoder mapping for audio */
2528         struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2529
2530         /*
2531          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2532          * will be rejected. Instead look for a better place.
2533          */
2534 };
2535
2536 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2537 {
2538         return container_of(dev, struct drm_i915_private, drm);
2539 }
2540
2541 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2542 {
2543         return to_i915(dev_get_drvdata(kdev));
2544 }
2545
2546 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2547 {
2548         return container_of(guc, struct drm_i915_private, guc);
2549 }
2550
2551 /* Simple iterator over all initialised engines */
2552 #define for_each_engine(engine__, dev_priv__, id__) \
2553         for ((id__) = 0; \
2554              (id__) < I915_NUM_ENGINES; \
2555              (id__)++) \
2556                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2557
2558 #define __mask_next_bit(mask) ({                                        \
2559         int __idx = ffs(mask) - 1;                                      \
2560         mask &= ~BIT(__idx);                                            \
2561         __idx;                                                          \
2562 })
2563
2564 /* Iterator over subset of engines selected by mask */
2565 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2566         for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;        \
2567              tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2568
2569 enum hdmi_force_audio {
2570         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
2571         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
2572         HDMI_AUDIO_AUTO,                /* trust EDID */
2573         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
2574 };
2575
2576 #define I915_GTT_OFFSET_NONE ((u32)-1)
2577
2578 /*
2579  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2580  * considered to be the frontbuffer for the given plane interface-wise. This
2581  * doesn't mean that the hw necessarily already scans it out, but that any
2582  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2583  *
2584  * We have one bit per pipe and per scanout plane type.
2585  */
2586 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2587 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2588 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2589         (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2590 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2591         (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2592 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2593         (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2594 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2595         (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2596 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2597         (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2598
2599 /*
2600  * Optimised SGL iterator for GEM objects
2601  */
2602 static __always_inline struct sgt_iter {
2603         struct scatterlist *sgp;
2604         union {
2605                 unsigned long pfn;
2606                 dma_addr_t dma;
2607         };
2608         unsigned int curr;
2609         unsigned int max;
2610 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2611         struct sgt_iter s = { .sgp = sgl };
2612
2613         if (s.sgp) {
2614                 s.max = s.curr = s.sgp->offset;
2615                 s.max += s.sgp->length;
2616                 if (dma)
2617                         s.dma = sg_dma_address(s.sgp);
2618                 else
2619                         s.pfn = page_to_pfn(sg_page(s.sgp));
2620         }
2621
2622         return s;
2623 }
2624
2625 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2626 {
2627         ++sg;
2628         if (unlikely(sg_is_chain(sg)))
2629                 sg = sg_chain_ptr(sg);
2630         return sg;
2631 }
2632
2633 /**
2634  * __sg_next - return the next scatterlist entry in a list
2635  * @sg:         The current sg entry
2636  *
2637  * Description:
2638  *   If the entry is the last, return NULL; otherwise, step to the next
2639  *   element in the array (@sg@+1). If that's a chain pointer, follow it;
2640  *   otherwise just return the pointer to the current element.
2641  **/
2642 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2643 {
2644 #ifdef CONFIG_DEBUG_SG
2645         BUG_ON(sg->sg_magic != SG_MAGIC);
2646 #endif
2647         return sg_is_last(sg) ? NULL : ____sg_next(sg);
2648 }
2649
2650 /**
2651  * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2652  * @__dmap:     DMA address (output)
2653  * @__iter:     'struct sgt_iter' (iterator state, internal)
2654  * @__sgt:      sg_table to iterate over (input)
2655  */
2656 #define for_each_sgt_dma(__dmap, __iter, __sgt)                         \
2657         for ((__iter) = __sgt_iter((__sgt)->sgl, true);                 \
2658              ((__dmap) = (__iter).dma + (__iter).curr);                 \
2659              (((__iter).curr += PAGE_SIZE) < (__iter).max) ||           \
2660              ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2661
2662 /**
2663  * for_each_sgt_page - iterate over the pages of the given sg_table
2664  * @__pp:       page pointer (output)
2665  * @__iter:     'struct sgt_iter' (iterator state, internal)
2666  * @__sgt:      sg_table to iterate over (input)
2667  */
2668 #define for_each_sgt_page(__pp, __iter, __sgt)                          \
2669         for ((__iter) = __sgt_iter((__sgt)->sgl, false);                \
2670              ((__pp) = (__iter).pfn == 0 ? NULL :                       \
2671               pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2672              (((__iter).curr += PAGE_SIZE) < (__iter).max) ||           \
2673              ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2674
2675 static inline const struct intel_device_info *
2676 intel_info(const struct drm_i915_private *dev_priv)
2677 {
2678         return &dev_priv->info;
2679 }
2680
2681 #define INTEL_INFO(dev_priv)    intel_info((dev_priv))
2682
2683 #define INTEL_GEN(dev_priv)     ((dev_priv)->info.gen)
2684 #define INTEL_DEVID(dev_priv)   ((dev_priv)->info.device_id)
2685
2686 #define REVID_FOREVER           0xff
2687 #define INTEL_REVID(dev_priv)   ((dev_priv)->drm.pdev->revision)
2688
2689 #define GEN_FOREVER (0)
2690 /*
2691  * Returns true if Gen is in inclusive range [Start, End].
2692  *
2693  * Use GEN_FOREVER for unbound start and or end.
2694  */
2695 #define IS_GEN(dev_priv, s, e) ({ \
2696         unsigned int __s = (s), __e = (e); \
2697         BUILD_BUG_ON(!__builtin_constant_p(s)); \
2698         BUILD_BUG_ON(!__builtin_constant_p(e)); \
2699         if ((__s) != GEN_FOREVER) \
2700                 __s = (s) - 1; \
2701         if ((__e) == GEN_FOREVER) \
2702                 __e = BITS_PER_LONG - 1; \
2703         else \
2704                 __e = (e) - 1; \
2705         !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2706 })
2707
2708 /*
2709  * Return true if revision is in range [since,until] inclusive.
2710  *
2711  * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2712  */
2713 #define IS_REVID(p, since, until) \
2714         (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2715
2716 #define IS_I830(dev_priv)       ((dev_priv)->info.platform == INTEL_I830)
2717 #define IS_I845G(dev_priv)      ((dev_priv)->info.platform == INTEL_I845G)
2718 #define IS_I85X(dev_priv)       ((dev_priv)->info.platform == INTEL_I85X)
2719 #define IS_I865G(dev_priv)      ((dev_priv)->info.platform == INTEL_I865G)
2720 #define IS_I915G(dev_priv)      ((dev_priv)->info.platform == INTEL_I915G)
2721 #define IS_I915GM(dev_priv)     ((dev_priv)->info.platform == INTEL_I915GM)
2722 #define IS_I945G(dev_priv)      ((dev_priv)->info.platform == INTEL_I945G)
2723 #define IS_I945GM(dev_priv)     ((dev_priv)->info.platform == INTEL_I945GM)
2724 #define IS_I965G(dev_priv)      ((dev_priv)->info.platform == INTEL_I965G)
2725 #define IS_I965GM(dev_priv)     ((dev_priv)->info.platform == INTEL_I965GM)
2726 #define IS_G45(dev_priv)        ((dev_priv)->info.platform == INTEL_G45)
2727 #define IS_GM45(dev_priv)       ((dev_priv)->info.platform == INTEL_GM45)
2728 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
2729 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2730 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2731 #define IS_PINEVIEW(dev_priv)   ((dev_priv)->info.platform == INTEL_PINEVIEW)
2732 #define IS_G33(dev_priv)        ((dev_priv)->info.platform == INTEL_G33)
2733 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2734 #define IS_IVYBRIDGE(dev_priv)  ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2735 #define IS_IVB_GT1(dev_priv)    (INTEL_DEVID(dev_priv) == 0x0156 || \
2736                                  INTEL_DEVID(dev_priv) == 0x0152 || \
2737                                  INTEL_DEVID(dev_priv) == 0x015a)
2738 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2739 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2740 #define IS_HASWELL(dev_priv)    ((dev_priv)->info.platform == INTEL_HASWELL)
2741 #define IS_BROADWELL(dev_priv)  ((dev_priv)->info.platform == INTEL_BROADWELL)
2742 #define IS_SKYLAKE(dev_priv)    ((dev_priv)->info.platform == INTEL_SKYLAKE)
2743 #define IS_BROXTON(dev_priv)    ((dev_priv)->info.platform == INTEL_BROXTON)
2744 #define IS_KABYLAKE(dev_priv)   ((dev_priv)->info.platform == INTEL_KABYLAKE)
2745 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2746 #define IS_MOBILE(dev_priv)     ((dev_priv)->info.is_mobile)
2747 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2748                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2749 #define IS_BDW_ULT(dev_priv)    (IS_BROADWELL(dev_priv) && \
2750                                  ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||       \
2751                                  (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||        \
2752                                  (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2753 /* ULX machines are also considered ULT. */
2754 #define IS_BDW_ULX(dev_priv)    (IS_BROADWELL(dev_priv) && \
2755                                  (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2756 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
2757                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2758 #define IS_HSW_ULT(dev_priv)    (IS_HASWELL(dev_priv) && \
2759                                  (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2760 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
2761                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2762 /* ULX machines are also considered ULT. */
2763 #define IS_HSW_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x0A0E || \
2764                                  INTEL_DEVID(dev_priv) == 0x0A1E)
2765 #define IS_SKL_ULT(dev_priv)    (INTEL_DEVID(dev_priv) == 0x1906 || \
2766                                  INTEL_DEVID(dev_priv) == 0x1913 || \
2767                                  INTEL_DEVID(dev_priv) == 0x1916 || \
2768                                  INTEL_DEVID(dev_priv) == 0x1921 || \
2769                                  INTEL_DEVID(dev_priv) == 0x1926)
2770 #define IS_SKL_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x190E || \
2771                                  INTEL_DEVID(dev_priv) == 0x1915 || \
2772                                  INTEL_DEVID(dev_priv) == 0x191E)
2773 #define IS_KBL_ULT(dev_priv)    (INTEL_DEVID(dev_priv) == 0x5906 || \
2774                                  INTEL_DEVID(dev_priv) == 0x5913 || \
2775                                  INTEL_DEVID(dev_priv) == 0x5916 || \
2776                                  INTEL_DEVID(dev_priv) == 0x5921 || \
2777                                  INTEL_DEVID(dev_priv) == 0x5926)
2778 #define IS_KBL_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x590E || \
2779                                  INTEL_DEVID(dev_priv) == 0x5915 || \
2780                                  INTEL_DEVID(dev_priv) == 0x591E)
2781 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
2782                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2783 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
2784                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2785
2786 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2787
2788 #define SKL_REVID_A0            0x0
2789 #define SKL_REVID_B0            0x1
2790 #define SKL_REVID_C0            0x2
2791 #define SKL_REVID_D0            0x3
2792 #define SKL_REVID_E0            0x4
2793 #define SKL_REVID_F0            0x5
2794 #define SKL_REVID_G0            0x6
2795 #define SKL_REVID_H0            0x7
2796
2797 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2798
2799 #define BXT_REVID_A0            0x0
2800 #define BXT_REVID_A1            0x1
2801 #define BXT_REVID_B0            0x3
2802 #define BXT_REVID_B_LAST        0x8
2803 #define BXT_REVID_C0            0x9
2804
2805 #define IS_BXT_REVID(dev_priv, since, until) \
2806         (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2807
2808 #define KBL_REVID_A0            0x0
2809 #define KBL_REVID_B0            0x1
2810 #define KBL_REVID_C0            0x2
2811 #define KBL_REVID_D0            0x3
2812 #define KBL_REVID_E0            0x4
2813
2814 #define IS_KBL_REVID(dev_priv, since, until) \
2815         (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2816
2817 /*
2818  * The genX designation typically refers to the render engine, so render
2819  * capability related checks should use IS_GEN, while display and other checks
2820  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2821  * chips, etc.).
2822  */
2823 #define IS_GEN2(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(1)))
2824 #define IS_GEN3(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(2)))
2825 #define IS_GEN4(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(3)))
2826 #define IS_GEN5(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(4)))
2827 #define IS_GEN6(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(5)))
2828 #define IS_GEN7(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(6)))
2829 #define IS_GEN8(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(7)))
2830 #define IS_GEN9(dev_priv)       (!!((dev_priv)->info.gen_mask & BIT(8)))
2831
2832 #define IS_GEN9_LP(dev_priv)    (IS_GEN9(dev_priv) && INTEL_INFO(dev_priv)->is_lp)
2833 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2834
2835 #define ENGINE_MASK(id) BIT(id)
2836 #define RENDER_RING     ENGINE_MASK(RCS)
2837 #define BSD_RING        ENGINE_MASK(VCS)
2838 #define BLT_RING        ENGINE_MASK(BCS)
2839 #define VEBOX_RING      ENGINE_MASK(VECS)
2840 #define BSD2_RING       ENGINE_MASK(VCS2)
2841 #define ALL_ENGINES     (~0)
2842
2843 #define HAS_ENGINE(dev_priv, id) \
2844         (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2845
2846 #define HAS_BSD(dev_priv)       HAS_ENGINE(dev_priv, VCS)
2847 #define HAS_BSD2(dev_priv)      HAS_ENGINE(dev_priv, VCS2)
2848 #define HAS_BLT(dev_priv)       HAS_ENGINE(dev_priv, BCS)
2849 #define HAS_VEBOX(dev_priv)     HAS_ENGINE(dev_priv, VECS)
2850
2851 #define HAS_LLC(dev_priv)       ((dev_priv)->info.has_llc)
2852 #define HAS_SNOOP(dev_priv)     ((dev_priv)->info.has_snoop)
2853 #define HAS_EDRAM(dev_priv)     (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2854 #define HAS_WT(dev_priv)        ((IS_HASWELL(dev_priv) || \
2855                                  IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2856
2857 #define HWS_NEEDS_PHYSICAL(dev_priv)    ((dev_priv)->info.hws_needs_physical)
2858
2859 #define HAS_HW_CONTEXTS(dev_priv)           ((dev_priv)->info.has_hw_contexts)
2860 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2861                 ((dev_priv)->info.has_logical_ring_contexts)
2862 #define USES_PPGTT(dev_priv)            (i915.enable_ppgtt)
2863 #define USES_FULL_PPGTT(dev_priv)       (i915.enable_ppgtt >= 2)
2864 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2865
2866 #define HAS_OVERLAY(dev_priv)            ((dev_priv)->info.has_overlay)
2867 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2868                 ((dev_priv)->info.overlay_needs_physical)
2869
2870 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2871 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
2872
2873 /* WaRsDisableCoarsePowerGating:skl,bxt */
2874 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2875         (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2876          IS_SKL_GT3(dev_priv) || \
2877          IS_SKL_GT4(dev_priv))
2878
2879 /*
2880  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2881  * even when in MSI mode. This results in spurious interrupt warnings if the
2882  * legacy irq no. is shared with another device. The kernel then disables that
2883  * interrupt source and so prevents the other device from working properly.
2884  */
2885 #define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
2886 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2887
2888 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2889  * rows, which changed the alignment requirements and fence programming.
2890  */
2891 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2892                                          !(IS_I915G(dev_priv) || \
2893                                          IS_I915GM(dev_priv)))
2894 #define SUPPORTS_TV(dev_priv)           ((dev_priv)->info.supports_tv)
2895 #define I915_HAS_HOTPLUG(dev_priv)      ((dev_priv)->info.has_hotplug)
2896
2897 #define HAS_FW_BLC(dev_priv)    (INTEL_GEN(dev_priv) > 2)
2898 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2899 #define HAS_FBC(dev_priv)       ((dev_priv)->info.has_fbc)
2900
2901 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2902
2903 #define HAS_DP_MST(dev_priv)    ((dev_priv)->info.has_dp_mst)
2904
2905 #define HAS_DDI(dev_priv)                ((dev_priv)->info.has_ddi)
2906 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2907 #define HAS_PSR(dev_priv)                ((dev_priv)->info.has_psr)
2908 #define HAS_RC6(dev_priv)                ((dev_priv)->info.has_rc6)
2909 #define HAS_RC6p(dev_priv)               ((dev_priv)->info.has_rc6p)
2910
2911 #define HAS_CSR(dev_priv)       ((dev_priv)->info.has_csr)
2912
2913 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2914 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2915
2916 /*
2917  * For now, anything with a GuC requires uCode loading, and then supports
2918  * command submission once loaded. But these are logically independent
2919  * properties, so we have separate macros to test them.
2920  */
2921 #define HAS_GUC(dev_priv)       ((dev_priv)->info.has_guc)
2922 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2923 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2924
2925 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2926
2927 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2928
2929 #define INTEL_PCH_DEVICE_ID_MASK                0xff00
2930 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
2931 #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
2932 #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
2933 #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
2934 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
2935 #define INTEL_PCH_SPT_DEVICE_ID_TYPE            0xA100
2936 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE         0x9D00
2937 #define INTEL_PCH_KBP_DEVICE_ID_TYPE            0xA200
2938 #define INTEL_PCH_P2X_DEVICE_ID_TYPE            0x7100
2939 #define INTEL_PCH_P3X_DEVICE_ID_TYPE            0x7000
2940 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE           0x2900 /* qemu q35 has 2918 */
2941
2942 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2943 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2944 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2945 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2946 #define HAS_PCH_LPT_LP(dev_priv) \
2947         ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2948 #define HAS_PCH_LPT_H(dev_priv) \
2949         ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2950 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2951 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2952 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2953 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2954
2955 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2956
2957 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2958
2959 /* DPF == dynamic parity feature */
2960 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2961 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2962                                  2 : HAS_L3_DPF(dev_priv))
2963
2964 #define GT_FREQUENCY_MULTIPLIER 50
2965 #define GEN9_FREQ_SCALER 3
2966
2967 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2968
2969 #include "i915_trace.h"
2970
2971 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2972 {
2973 #ifdef CONFIG_INTEL_IOMMU
2974         if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2975                 return true;
2976 #endif
2977         return false;
2978 }
2979
2980 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2981                                 int enable_ppgtt);
2982
2983 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2984
2985 /* i915_drv.c */
2986 void __printf(3, 4)
2987 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2988               const char *fmt, ...);
2989
2990 #define i915_report_error(dev_priv, fmt, ...)                              \
2991         __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2992
2993 #ifdef CONFIG_COMPAT
2994 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2995                               unsigned long arg);
2996 #else
2997 #define i915_compat_ioctl NULL
2998 #endif
2999 extern const struct dev_pm_ops i915_pm_ops;
3000
3001 extern int i915_driver_load(struct pci_dev *pdev,
3002                             const struct pci_device_id *ent);
3003 extern void i915_driver_unload(struct drm_device *dev);
3004 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
3005 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
3006 extern void i915_reset(struct drm_i915_private *dev_priv);
3007 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
3008 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
3009 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
3010 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
3011 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
3012 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
3013 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
3014 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3015
3016 /* intel_hotplug.c */
3017 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
3018                            u32 pin_mask, u32 long_mask);
3019 void intel_hpd_init(struct drm_i915_private *dev_priv);
3020 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
3021 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3022 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3023 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3024 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3025
3026 /* i915_irq.c */
3027 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3028 {
3029         unsigned long delay;
3030
3031         if (unlikely(!i915.enable_hangcheck))
3032                 return;
3033
3034         /* Don't continually defer the hangcheck so that it is always run at
3035          * least once after work has been scheduled on any ring. Otherwise,
3036          * we will ignore a hung ring if a second ring is kept busy.
3037          */
3038
3039         delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
3040         queue_delayed_work(system_long_wq,
3041                            &dev_priv->gpu_error.hangcheck_work, delay);
3042 }
3043
3044 __printf(3, 4)
3045 void i915_handle_error(struct drm_i915_private *dev_priv,
3046                        u32 engine_mask,
3047                        const char *fmt, ...);
3048
3049 extern void intel_irq_init(struct drm_i915_private *dev_priv);
3050 int intel_irq_install(struct drm_i915_private *dev_priv);
3051 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3052
3053 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
3054 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
3055                                         bool restore_forcewake);
3056 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
3057 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
3058 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
3059 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
3060 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
3061                                          bool restore);
3062 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
3063 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
3064                                 enum forcewake_domains domains);
3065 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
3066                                 enum forcewake_domains domains);
3067 /* Like above but the caller must manage the uncore.lock itself.
3068  * Must be used with I915_READ_FW and friends.
3069  */
3070 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
3071                                         enum forcewake_domains domains);
3072 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
3073                                         enum forcewake_domains domains);
3074 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
3075
3076 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
3077
3078 int intel_wait_for_register(struct drm_i915_private *dev_priv,
3079                             i915_reg_t reg,
3080                             const u32 mask,
3081                             const u32 value,
3082                             const unsigned long timeout_ms);
3083 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
3084                                i915_reg_t reg,
3085                                const u32 mask,
3086                                const u32 value,
3087                                const unsigned long timeout_ms);
3088
3089 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3090 {
3091         return dev_priv->gvt;
3092 }
3093
3094 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3095 {
3096         return dev_priv->vgpu.active;
3097 }
3098
3099 void
3100 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3101                      u32 status_mask);
3102
3103 void
3104 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3105                       u32 status_mask);
3106
3107 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3108 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3109 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3110                                    uint32_t mask,
3111                                    uint32_t bits);
3112 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3113                             uint32_t interrupt_mask,
3114                             uint32_t enabled_irq_mask);
3115 static inline void
3116 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3117 {
3118         ilk_update_display_irq(dev_priv, bits, bits);
3119 }
3120 static inline void
3121 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3122 {
3123         ilk_update_display_irq(dev_priv, bits, 0);
3124 }
3125 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3126                          enum pipe pipe,
3127                          uint32_t interrupt_mask,
3128                          uint32_t enabled_irq_mask);
3129 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3130                                        enum pipe pipe, uint32_t bits)
3131 {
3132         bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3133 }
3134 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3135                                         enum pipe pipe, uint32_t bits)
3136 {
3137         bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3138 }
3139 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3140                                   uint32_t interrupt_mask,
3141                                   uint32_t enabled_irq_mask);
3142 static inline void
3143 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3144 {
3145         ibx_display_interrupt_update(dev_priv, bits, bits);
3146 }
3147 static inline void
3148 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3149 {
3150         ibx_display_interrupt_update(dev_priv, bits, 0);
3151 }
3152
3153 /* i915_gem.c */
3154 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3155                           struct drm_file *file_priv);
3156 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3157                          struct drm_file *file_priv);
3158 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3159                           struct drm_file *file_priv);
3160 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3161                         struct drm_file *file_priv);
3162 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3163                         struct drm_file *file_priv);
3164 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3165                               struct drm_file *file_priv);
3166 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3167                              struct drm_file *file_priv);
3168 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3169                         struct drm_file *file_priv);
3170 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3171                          struct drm_file *file_priv);
3172 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3173                         struct drm_file *file_priv);
3174 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3175                                struct drm_file *file);
3176 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3177                                struct drm_file *file);
3178 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3179                             struct drm_file *file_priv);
3180 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3181                            struct drm_file *file_priv);
3182 int i915_gem_set_tiling(struct drm_device *dev, void *data,
3183                         struct drm_file *file_priv);
3184 int i915_gem_get_tiling(struct drm_device *dev, void *data,
3185                         struct drm_file *file_priv);
3186 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3187 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3188                            struct drm_file *file);
3189 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3190                                 struct drm_file *file_priv);
3191 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3192                         struct drm_file *file_priv);
3193 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3194 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3195 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3196 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3197 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3198
3199 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3200 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3201 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3202                          const struct drm_i915_gem_object_ops *ops);
3203 struct drm_i915_gem_object *
3204 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3205 struct drm_i915_gem_object *
3206 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3207                                  const void *data, size_t size);
3208 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3209 void i915_gem_free_object(struct drm_gem_object *obj);
3210
3211 struct i915_vma * __must_check
3212 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3213                          const struct i915_ggtt_view *view,
3214                          u64 size,
3215                          u64 alignment,
3216                          u64 flags);
3217
3218 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3219 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3220
3221 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3222
3223 static inline int __sg_page_count(const struct scatterlist *sg)
3224 {
3225         return sg->length >> PAGE_SHIFT;
3226 }
3227
3228 struct scatterlist *
3229 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3230                        unsigned int n, unsigned int *offset);
3231
3232 struct page *
3233 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3234                          unsigned int n);
3235
3236 struct page *
3237 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3238                                unsigned int n);
3239
3240 dma_addr_t
3241 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3242                                 unsigned long n);
3243
3244 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3245                                  struct sg_table *pages);
3246 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3247
3248 static inline int __must_check
3249 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3250 {
3251         might_lock(&obj->mm.lock);
3252
3253         if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3254                 return 0;
3255
3256         return __i915_gem_object_get_pages(obj);
3257 }
3258
3259 static inline void
3260 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3261 {
3262         GEM_BUG_ON(!obj->mm.pages);
3263
3264         atomic_inc(&obj->mm.pages_pin_count);
3265 }
3266
3267 static inline bool
3268 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3269 {
3270         return atomic_read(&obj->mm.pages_pin_count);
3271 }
3272
3273 static inline void
3274 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3275 {
3276         GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3277         GEM_BUG_ON(!obj->mm.pages);
3278
3279         atomic_dec(&obj->mm.pages_pin_count);
3280         GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count) < obj->bind_count);
3281 }
3282
3283 static inline void
3284 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3285 {
3286         __i915_gem_object_unpin_pages(obj);
3287 }
3288
3289 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3290         I915_MM_NORMAL = 0,
3291         I915_MM_SHRINKER
3292 };
3293
3294 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3295                                  enum i915_mm_subclass subclass);
3296 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3297
3298 enum i915_map_type {
3299         I915_MAP_WB = 0,
3300         I915_MAP_WC,
3301 };
3302
3303 /**
3304  * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3305  * @obj - the object to map into kernel address space
3306  * @type - the type of mapping, used to select pgprot_t
3307  *
3308  * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3309  * pages and then returns a contiguous mapping of the backing storage into
3310  * the kernel address space. Based on the @type of mapping, the PTE will be
3311  * set to either WriteBack or WriteCombine (via pgprot_t).
3312  *
3313  * The caller is responsible for calling i915_gem_object_unpin_map() when the
3314  * mapping is no longer required.
3315  *
3316  * Returns the pointer through which to access the mapped object, or an
3317  * ERR_PTR() on error.
3318  */
3319 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3320                                            enum i915_map_type type);
3321
3322 /**
3323  * i915_gem_object_unpin_map - releases an earlier mapping
3324  * @obj - the object to unmap
3325  *
3326  * After pinning the object and mapping its pages, once you are finished
3327  * with your access, call i915_gem_object_unpin_map() to release the pin
3328  * upon the mapping. Once the pin count reaches zero, that mapping may be
3329  * removed.
3330  */
3331 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3332 {
3333         i915_gem_object_unpin_pages(obj);
3334 }
3335
3336 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3337                                     unsigned int *needs_clflush);
3338 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3339                                      unsigned int *needs_clflush);
3340 #define CLFLUSH_BEFORE 0x1
3341 #define CLFLUSH_AFTER 0x2
3342 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3343
3344 static inline void
3345 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3346 {
3347         i915_gem_object_unpin_pages(obj);
3348 }
3349
3350 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3351 void i915_vma_move_to_active(struct i915_vma *vma,
3352                              struct drm_i915_gem_request *req,
3353                              unsigned int flags);
3354 int i915_gem_dumb_create(struct drm_file *file_priv,
3355                          struct drm_device *dev,
3356                          struct drm_mode_create_dumb *args);
3357 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3358                       uint32_t handle, uint64_t *offset);
3359 int i915_gem_mmap_gtt_version(void);
3360
3361 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3362                        struct drm_i915_gem_object *new,
3363                        unsigned frontbuffer_bits);
3364
3365 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3366
3367 struct drm_i915_gem_request *
3368 i915_gem_find_active_request(struct intel_engine_cs *engine);
3369
3370 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3371
3372 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3373 {
3374         return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3375 }
3376
3377 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3378 {
3379         return unlikely(test_bit(I915_WEDGED, &error->flags));
3380 }
3381
3382 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3383 {
3384         return i915_reset_in_progress(error) | i915_terminally_wedged(error);
3385 }
3386
3387 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3388 {
3389         return READ_ONCE(error->reset_count);
3390 }
3391
3392 void i915_gem_reset(struct drm_i915_private *dev_priv);
3393 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3394 void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3395 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3396 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3397 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3398 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3399 int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3400                                         unsigned int flags);
3401 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3402 void i915_gem_resume(struct drm_i915_private *dev_priv);
3403 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3404 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3405                          unsigned int flags,
3406                          long timeout,
3407                          struct intel_rps_client *rps);
3408 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3409                                   unsigned int flags,
3410                                   int priority);
3411 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3412
3413 int __must_check
3414 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3415                                   bool write);
3416 int __must_check
3417 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3418 struct i915_vma * __must_check
3419 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3420                                      u32 alignment,
3421                                      const struct i915_ggtt_view *view);
3422 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3423 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3424                                 int align);
3425 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3426 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3427
3428 u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
3429                            int tiling_mode);
3430 u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
3431                                 int tiling_mode, bool fenced);
3432
3433 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3434                                     enum i915_cache_level cache_level);
3435
3436 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3437                                 struct dma_buf *dma_buf);
3438
3439 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3440                                 struct drm_gem_object *gem_obj, int flags);
3441
3442 struct i915_vma *
3443 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3444                      struct i915_address_space *vm,
3445                      const struct i915_ggtt_view *view);
3446
3447 struct i915_vma *
3448 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3449                                   struct i915_address_space *vm,
3450                                   const struct i915_ggtt_view *view);
3451
3452 static inline struct i915_hw_ppgtt *
3453 i915_vm_to_ppgtt(struct i915_address_space *vm)
3454 {
3455         return container_of(vm, struct i915_hw_ppgtt, base);
3456 }
3457
3458 static inline struct i915_vma *
3459 i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj,
3460                         const struct i915_ggtt_view *view)
3461 {
3462         return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view);
3463 }
3464
3465 static inline unsigned long
3466 i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o,
3467                             const struct i915_ggtt_view *view)
3468 {
3469         return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view));
3470 }
3471
3472 /* i915_gem_fence_reg.c */
3473 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3474 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3475
3476 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3477
3478 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3479 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3480                                        struct sg_table *pages);
3481 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3482                                          struct sg_table *pages);
3483
3484 /* i915_gem_context.c */
3485 int __must_check i915_gem_context_init(struct drm_i915_private *dev_priv);
3486 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3487 void i915_gem_context_fini(struct drm_i915_private *dev_priv);
3488 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3489 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3490 int i915_switch_context(struct drm_i915_gem_request *req);
3491 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3492 void i915_gem_context_free(struct kref *ctx_ref);
3493 struct i915_gem_context *
3494 i915_gem_context_create_gvt(struct drm_device *dev);
3495
3496 static inline struct i915_gem_context *
3497 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3498 {
3499         struct i915_gem_context *ctx;
3500
3501         lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3502
3503         ctx = idr_find(&file_priv->context_idr, id);
3504         if (!ctx)
3505                 return ERR_PTR(-ENOENT);
3506
3507         return ctx;
3508 }
3509
3510 static inline struct i915_gem_context *
3511 i915_gem_context_get(struct i915_gem_context *ctx)
3512 {
3513         kref_get(&ctx->ref);
3514         return ctx;
3515 }
3516
3517 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3518 {
3519         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3520         kref_put(&ctx->ref, i915_gem_context_free);
3521 }
3522
3523 static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
3524 {
3525         struct mutex *lock = &ctx->i915->drm.struct_mutex;
3526
3527         if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
3528                 mutex_unlock(lock);
3529 }
3530
3531 static inline struct intel_timeline *
3532 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3533                                  struct intel_engine_cs *engine)
3534 {
3535         struct i915_address_space *vm;
3536
3537         vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3538         return &vm->timeline.engine[engine->id];
3539 }
3540
3541 static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3542 {
3543         return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3544 }
3545
3546 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3547                                   struct drm_file *file);
3548 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3549                                    struct drm_file *file);
3550 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3551                                     struct drm_file *file_priv);
3552 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3553                                     struct drm_file *file_priv);
3554 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
3555                                        struct drm_file *file);
3556
3557 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3558                          struct drm_file *file);
3559
3560 /* i915_gem_evict.c */
3561 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3562                                           u64 min_size, u64 alignment,
3563                                           unsigned cache_level,
3564                                           u64 start, u64 end,
3565                                           unsigned flags);
3566 int __must_check i915_gem_evict_for_vma(struct i915_vma *vma,
3567                                         unsigned int flags);
3568 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3569
3570 /* belongs in i915_gem_gtt.h */
3571 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3572 {
3573         wmb();
3574         if (INTEL_GEN(dev_priv) < 6)
3575                 intel_gtt_chipset_flush();
3576 }
3577
3578 /* i915_gem_stolen.c */
3579 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3580                                 struct drm_mm_node *node, u64 size,
3581                                 unsigned alignment);
3582 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3583                                          struct drm_mm_node *node, u64 size,
3584                                          unsigned alignment, u64 start,
3585                                          u64 end);
3586 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3587                                  struct drm_mm_node *node);
3588 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3589 void i915_gem_cleanup_stolen(struct drm_device *dev);
3590 struct drm_i915_gem_object *
3591 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3592 struct drm_i915_gem_object *
3593 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3594                                                u32 stolen_offset,
3595                                                u32 gtt_offset,
3596                                                u32 size);
3597
3598 /* i915_gem_internal.c */
3599 struct drm_i915_gem_object *
3600 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3601                                 unsigned int size);
3602
3603 /* i915_gem_shrinker.c */
3604 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3605                               unsigned long target,
3606                               unsigned flags);
3607 #define I915_SHRINK_PURGEABLE 0x1
3608 #define I915_SHRINK_UNBOUND 0x2
3609 #define I915_SHRINK_BOUND 0x4
3610 #define I915_SHRINK_ACTIVE 0x8
3611 #define I915_SHRINK_VMAPS 0x10
3612 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3613 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3614 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3615
3616
3617 /* i915_gem_tiling.c */
3618 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3619 {
3620         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3621
3622         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3623                 i915_gem_object_is_tiled(obj);
3624 }
3625
3626 /* i915_debugfs.c */
3627 #ifdef CONFIG_DEBUG_FS
3628 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3629 void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3630 int i915_debugfs_connector_add(struct drm_connector *connector);
3631 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3632 #else
3633 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3634 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3635 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3636 { return 0; }
3637 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3638 #endif
3639
3640 /* i915_gpu_error.c */
3641 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3642
3643 __printf(2, 3)
3644 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3645 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3646                             const struct i915_error_state_file_priv *error);
3647 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3648                               struct drm_i915_private *i915,
3649                               size_t count, loff_t pos);
3650 static inline void i915_error_state_buf_release(
3651         struct drm_i915_error_state_buf *eb)
3652 {
3653         kfree(eb->buf);
3654 }
3655 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3656                               u32 engine_mask,
3657                               const char *error_msg);
3658 void i915_error_state_get(struct drm_device *dev,
3659                           struct i915_error_state_file_priv *error_priv);
3660 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3661 void i915_destroy_error_state(struct drm_i915_private *dev_priv);
3662
3663 #else
3664
3665 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3666                                             u32 engine_mask,
3667                                             const char *error_msg)
3668 {
3669 }
3670
3671 static inline void i915_destroy_error_state(struct drm_i915_private *dev_priv)
3672 {
3673 }
3674
3675 #endif
3676
3677 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3678
3679 /* i915_cmd_parser.c */
3680 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3681 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3682 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3683 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3684                             struct drm_i915_gem_object *batch_obj,
3685                             struct drm_i915_gem_object *shadow_batch_obj,
3686                             u32 batch_start_offset,
3687                             u32 batch_len,
3688                             bool is_master);
3689
3690 /* i915_perf.c */
3691 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3692 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3693 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3694 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3695
3696 /* i915_suspend.c */
3697 extern int i915_save_state(struct drm_i915_private *dev_priv);
3698 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3699
3700 /* i915_sysfs.c */
3701 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3702 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3703
3704 /* intel_i2c.c */
3705 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3706 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3707 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3708                                      unsigned int pin);
3709
3710 extern struct i2c_adapter *
3711 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3712 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3713 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3714 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3715 {
3716         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3717 }
3718 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3719
3720 /* intel_bios.c */
3721 int intel_bios_init(struct drm_i915_private *dev_priv);
3722 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3723 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3724 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3725 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3726 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3727 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3728 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3729 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3730                                      enum port port);
3731 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3732                                 enum port port);
3733
3734
3735 /* intel_opregion.c */
3736 #ifdef CONFIG_ACPI
3737 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3738 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3739 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3740 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3741 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3742                                          bool enable);
3743 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3744                                          pci_power_t state);
3745 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3746 #else
3747 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3748 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3749 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3750 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3751 {
3752 }
3753 static inline int
3754 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3755 {
3756         return 0;
3757 }
3758 static inline int
3759 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3760 {
3761         return 0;
3762 }
3763 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3764 {
3765         return -ENODEV;
3766 }
3767 #endif
3768
3769 /* intel_acpi.c */
3770 #ifdef CONFIG_ACPI
3771 extern void intel_register_dsm_handler(void);
3772 extern void intel_unregister_dsm_handler(void);
3773 #else
3774 static inline void intel_register_dsm_handler(void) { return; }
3775 static inline void intel_unregister_dsm_handler(void) { return; }
3776 #endif /* CONFIG_ACPI */
3777
3778 /* intel_device_info.c */
3779 static inline struct intel_device_info *
3780 mkwrite_device_info(struct drm_i915_private *dev_priv)
3781 {
3782         return (struct intel_device_info *)&dev_priv->info;
3783 }
3784
3785 const char *intel_platform_name(enum intel_platform platform);
3786 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3787 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3788
3789 /* modesetting */
3790 extern void intel_modeset_init_hw(struct drm_device *dev);
3791 extern int intel_modeset_init(struct drm_device *dev);
3792 extern void intel_modeset_gem_init(struct drm_device *dev);
3793 extern void intel_modeset_cleanup(struct drm_device *dev);
3794 extern int intel_connector_register(struct drm_connector *);
3795 extern void intel_connector_unregister(struct drm_connector *);
3796 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3797                                        bool state);
3798 extern void intel_display_resume(struct drm_device *dev);
3799 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3800 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3801 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3802 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3803 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3804 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3805                                   bool enable);
3806
3807 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3808                         struct drm_file *file);
3809
3810 /* overlay */
3811 extern struct intel_overlay_error_state *
3812 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3813 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3814                                             struct intel_overlay_error_state *error);
3815
3816 extern struct intel_display_error_state *
3817 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3818 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3819                                             struct drm_i915_private *dev_priv,
3820                                             struct intel_display_error_state *error);
3821
3822 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3823 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3824 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3825                       u32 reply_mask, u32 reply, int timeout_base_ms);
3826
3827 /* intel_sideband.c */
3828 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3829 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3830 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3831 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3832 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3833 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3834 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3835 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3836 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3837 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3838 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3839 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3840 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3841 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3842                    enum intel_sbi_destination destination);
3843 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3844                      enum intel_sbi_destination destination);
3845 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3846 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3847
3848 /* intel_dpio_phy.c */
3849 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3850                              enum dpio_phy *phy, enum dpio_channel *ch);
3851 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3852                                   enum port port, u32 margin, u32 scale,
3853                                   u32 enable, u32 deemphasis);
3854 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3855 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3856 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3857                             enum dpio_phy phy);
3858 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3859                               enum dpio_phy phy);
3860 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3861                                              uint8_t lane_count);
3862 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3863                                      uint8_t lane_lat_optim_mask);
3864 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3865
3866 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3867                               u32 deemph_reg_value, u32 margin_reg_value,
3868                               bool uniq_trans_scale);
3869 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3870                               bool reset);
3871 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3872 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3873 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3874 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3875
3876 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3877                               u32 demph_reg_value, u32 preemph_reg_value,
3878                               u32 uniqtranscale_reg_value, u32 tx3_demph);
3879 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3880 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3881 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3882
3883 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3884 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3885
3886 #define I915_READ8(reg)         dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3887 #define I915_WRITE8(reg, val)   dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3888
3889 #define I915_READ16(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3890 #define I915_WRITE16(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3891 #define I915_READ16_NOTRACE(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3892 #define I915_WRITE16_NOTRACE(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3893
3894 #define I915_READ(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3895 #define I915_WRITE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3896 #define I915_READ_NOTRACE(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3897 #define I915_WRITE_NOTRACE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3898
3899 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3900  * will be implemented using 2 32-bit writes in an arbitrary order with
3901  * an arbitrary delay between them. This can cause the hardware to
3902  * act upon the intermediate value, possibly leading to corruption and
3903  * machine death. For this reason we do not support I915_WRITE64, or
3904  * dev_priv->uncore.funcs.mmio_writeq.
3905  *
3906  * When reading a 64-bit value as two 32-bit values, the delay may cause
3907  * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3908  * occasionally a 64-bit register does not actualy support a full readq
3909  * and must be read using two 32-bit reads.
3910  *
3911  * You have been warned.
3912  */
3913 #define I915_READ64(reg)        dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3914
3915 #define I915_READ64_2x32(lower_reg, upper_reg) ({                       \
3916         u32 upper, lower, old_upper, loop = 0;                          \
3917         upper = I915_READ(upper_reg);                                   \
3918         do {                                                            \
3919                 old_upper = upper;                                      \
3920                 lower = I915_READ(lower_reg);                           \
3921                 upper = I915_READ(upper_reg);                           \
3922         } while (upper != old_upper && loop++ < 2);                     \
3923         (u64)upper << 32 | lower; })
3924
3925 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
3926 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
3927
3928 #define __raw_read(x, s) \
3929 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3930                                              i915_reg_t reg) \
3931 { \
3932         return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3933 }
3934
3935 #define __raw_write(x, s) \
3936 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3937                                        i915_reg_t reg, uint##x##_t val) \
3938 { \
3939         write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3940 }
3941 __raw_read(8, b)
3942 __raw_read(16, w)
3943 __raw_read(32, l)
3944 __raw_read(64, q)
3945
3946 __raw_write(8, b)
3947 __raw_write(16, w)
3948 __raw_write(32, l)
3949 __raw_write(64, q)
3950
3951 #undef __raw_read
3952 #undef __raw_write
3953
3954 /* These are untraced mmio-accessors that are only valid to be used inside
3955  * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3956  * controlled.
3957  *
3958  * Think twice, and think again, before using these.
3959  *
3960  * As an example, these accessors can possibly be used between:
3961  *
3962  * spin_lock_irq(&dev_priv->uncore.lock);
3963  * intel_uncore_forcewake_get__locked();
3964  *
3965  * and
3966  *
3967  * intel_uncore_forcewake_put__locked();
3968  * spin_unlock_irq(&dev_priv->uncore.lock);
3969  *
3970  *
3971  * Note: some registers may not need forcewake held, so
3972  * intel_uncore_forcewake_{get,put} can be omitted, see
3973  * intel_uncore_forcewake_for_reg().
3974  *
3975  * Certain architectures will die if the same cacheline is concurrently accessed
3976  * by different clients (e.g. on Ivybridge). Access to registers should
3977  * therefore generally be serialised, by either the dev_priv->uncore.lock or
3978  * a more localised lock guarding all access to that bank of registers.
3979  */
3980 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3981 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3982 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3983 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3984
3985 /* "Broadcast RGB" property */
3986 #define INTEL_BROADCAST_RGB_AUTO 0
3987 #define INTEL_BROADCAST_RGB_FULL 1
3988 #define INTEL_BROADCAST_RGB_LIMITED 2
3989
3990 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3991 {
3992         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3993                 return VLV_VGACNTRL;
3994         else if (INTEL_GEN(dev_priv) >= 5)
3995                 return CPU_VGACNTRL;
3996         else
3997                 return VGACNTRL;
3998 }
3999
4000 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
4001 {
4002         unsigned long j = msecs_to_jiffies(m);
4003
4004         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4005 }
4006
4007 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
4008 {
4009         return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
4010 }
4011
4012 static inline unsigned long
4013 timespec_to_jiffies_timeout(const struct timespec *value)
4014 {
4015         unsigned long j = timespec_to_jiffies(value);
4016
4017         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4018 }
4019
4020 /*
4021  * If you need to wait X milliseconds between events A and B, but event B
4022  * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4023  * when event A happened, then just before event B you call this function and
4024  * pass the timestamp as the first argument, and X as the second argument.
4025  */
4026 static inline void
4027 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4028 {
4029         unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4030
4031         /*
4032          * Don't re-read the value of "jiffies" every time since it may change
4033          * behind our back and break the math.
4034          */
4035         tmp_jiffies = jiffies;
4036         target_jiffies = timestamp_jiffies +
4037                          msecs_to_jiffies_timeout(to_wait_ms);
4038
4039         if (time_after(target_jiffies, tmp_jiffies)) {
4040                 remaining_jiffies = target_jiffies - tmp_jiffies;
4041                 while (remaining_jiffies)
4042                         remaining_jiffies =
4043                             schedule_timeout_uninterruptible(remaining_jiffies);
4044         }
4045 }
4046
4047 static inline bool
4048 __i915_request_irq_complete(struct drm_i915_gem_request *req)
4049 {
4050         struct intel_engine_cs *engine = req->engine;
4051
4052         /* Before we do the heavier coherent read of the seqno,
4053          * check the value (hopefully) in the CPU cacheline.
4054          */
4055         if (__i915_gem_request_completed(req))
4056                 return true;
4057
4058         /* Ensure our read of the seqno is coherent so that we
4059          * do not "miss an interrupt" (i.e. if this is the last
4060          * request and the seqno write from the GPU is not visible
4061          * by the time the interrupt fires, we will see that the
4062          * request is incomplete and go back to sleep awaiting
4063          * another interrupt that will never come.)
4064          *
4065          * Strictly, we only need to do this once after an interrupt,
4066          * but it is easier and safer to do it every time the waiter
4067          * is woken.
4068          */
4069         if (engine->irq_seqno_barrier &&
4070             rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
4071             cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
4072                 struct task_struct *tsk;
4073
4074                 /* The ordering of irq_posted versus applying the barrier
4075                  * is crucial. The clearing of the current irq_posted must
4076                  * be visible before we perform the barrier operation,
4077                  * such that if a subsequent interrupt arrives, irq_posted
4078                  * is reasserted and our task rewoken (which causes us to
4079                  * do another __i915_request_irq_complete() immediately
4080                  * and reapply the barrier). Conversely, if the clear
4081                  * occurs after the barrier, then an interrupt that arrived
4082                  * whilst we waited on the barrier would not trigger a
4083                  * barrier on the next pass, and the read may not see the
4084                  * seqno update.
4085                  */
4086                 engine->irq_seqno_barrier(engine);
4087
4088                 /* If we consume the irq, but we are no longer the bottom-half,
4089                  * the real bottom-half may not have serialised their own
4090                  * seqno check with the irq-barrier (i.e. may have inspected
4091                  * the seqno before we believe it coherent since they see
4092                  * irq_posted == false but we are still running).
4093                  */
4094                 rcu_read_lock();
4095                 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
4096                 if (tsk && tsk != current)
4097                         /* Note that if the bottom-half is changed as we
4098                          * are sending the wake-up, the new bottom-half will
4099                          * be woken by whomever made the change. We only have
4100                          * to worry about when we steal the irq-posted for
4101                          * ourself.
4102                          */
4103                         wake_up_process(tsk);
4104                 rcu_read_unlock();
4105
4106                 if (__i915_gem_request_completed(req))
4107                         return true;
4108         }
4109
4110         return false;
4111 }
4112
4113 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4114 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4115
4116 /* i915_mm.c */
4117 int remap_io_mapping(struct vm_area_struct *vma,
4118                      unsigned long addr, unsigned long pfn, unsigned long size,
4119                      struct io_mapping *iomap);
4120
4121 #define ptr_mask_bits(ptr) ({                                           \
4122         unsigned long __v = (unsigned long)(ptr);                       \
4123         (typeof(ptr))(__v & PAGE_MASK);                                 \
4124 })
4125
4126 #define ptr_unpack_bits(ptr, bits) ({                                   \
4127         unsigned long __v = (unsigned long)(ptr);                       \
4128         (bits) = __v & ~PAGE_MASK;                                      \
4129         (typeof(ptr))(__v & PAGE_MASK);                                 \
4130 })
4131
4132 #define ptr_pack_bits(ptr, bits)                                        \
4133         ((typeof(ptr))((unsigned long)(ptr) | (bits)))
4134
4135 #define fetch_and_zero(ptr) ({                                          \
4136         typeof(*ptr) __T = *(ptr);                                      \
4137         *(ptr) = (typeof(*ptr))0;                                       \
4138         __T;                                                            \
4139 })
4140
4141 #endif