1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "i915_params.h"
39 #include "intel_bios.h"
40 #include "intel_ringbuffer.h"
41 #include "intel_lrc.h"
42 #include "i915_gem_gtt.h"
43 #include "i915_gem_render_state.h"
44 #include <linux/io-mapping.h>
45 #include <linux/i2c.h>
46 #include <linux/i2c-algo-bit.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <linux/backlight.h>
51 #include <linux/hashtable.h>
52 #include <linux/intel-iommu.h>
53 #include <linux/kref.h>
54 #include <linux/pm_qos.h>
55 #include "intel_guc.h"
57 /* General customization:
60 #define DRIVER_NAME "i915"
61 #define DRIVER_DESC "Intel Graphics"
62 #define DRIVER_DATE "20151218"
65 /* Many gcc seem to no see through this and fall over :( */
67 #define WARN_ON(x) ({ \
68 bool __i915_warn_cond = (x); \
69 if (__builtin_constant_p(__i915_warn_cond)) \
70 BUILD_BUG_ON(__i915_warn_cond); \
71 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
73 #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
77 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
79 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
80 (long) (x), __func__);
82 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
83 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
84 * which may not necessarily be a user visible problem. This will either
85 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
86 * enable distros and users to tailor their preferred amount of i915 abrt
89 #define I915_STATE_WARN(condition, format...) ({ \
90 int __ret_warn_on = !!(condition); \
91 if (unlikely(__ret_warn_on)) \
92 if (!WARN(i915.verbose_state_checks, format)) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) \
100 if (!WARN(i915.verbose_state_checks, \
101 "WARN_ON(" #condition ")\n")) \
102 DRM_ERROR("WARN_ON(" #condition ")\n"); \
103 unlikely(__ret_warn_on); \
106 static inline const char *yesno(bool v)
108 return v ? "yes" : "no";
117 I915_MAX_PIPES = _PIPE_EDP
119 #define pipe_name(p) ((p) + 'A')
128 #define transcoder_name(t) ((t) + 'A')
131 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
132 * number of planes per CRTC. Not all platforms really have this many planes,
133 * which means some arrays of size I915_MAX_PLANES may have unused entries
134 * between the topmost sprite plane and the cursor plane.
143 #define plane_name(p) ((p) + 'A')
145 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
155 #define port_name(p) ((p) + 'A')
157 #define I915_NUM_PHYS_VLV 2
169 enum intel_display_power_domain {
173 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
174 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
175 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
176 POWER_DOMAIN_TRANSCODER_A,
177 POWER_DOMAIN_TRANSCODER_B,
178 POWER_DOMAIN_TRANSCODER_C,
179 POWER_DOMAIN_TRANSCODER_EDP,
180 POWER_DOMAIN_PORT_DDI_A_LANES,
181 POWER_DOMAIN_PORT_DDI_B_LANES,
182 POWER_DOMAIN_PORT_DDI_C_LANES,
183 POWER_DOMAIN_PORT_DDI_D_LANES,
184 POWER_DOMAIN_PORT_DDI_E_LANES,
185 POWER_DOMAIN_PORT_DSI,
186 POWER_DOMAIN_PORT_CRT,
187 POWER_DOMAIN_PORT_OTHER,
196 POWER_DOMAIN_MODESET,
202 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
203 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
204 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
205 #define POWER_DOMAIN_TRANSCODER(tran) \
206 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
207 (tran) + POWER_DOMAIN_TRANSCODER_A)
211 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
223 #define for_each_hpd_pin(__pin) \
224 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
226 struct i915_hotplug {
227 struct work_struct hotplug_work;
230 unsigned long last_jiffies;
235 HPD_MARK_DISABLED = 2
237 } stats[HPD_NUM_PINS];
239 struct delayed_work reenable_work;
241 struct intel_digital_port *irq_port[I915_MAX_PORTS];
244 struct work_struct dig_port_work;
247 * if we get a HPD irq from DP and a HPD irq from non-DP
248 * the non-DP HPD could block the workqueue on a mode config
249 * mutex getting, that userspace may have taken. However
250 * userspace is waiting on the DP workqueue to run which is
251 * blocked behind the non-DP one.
253 struct workqueue_struct *dp_wq;
256 #define I915_GEM_GPU_DOMAINS \
257 (I915_GEM_DOMAIN_RENDER | \
258 I915_GEM_DOMAIN_SAMPLER | \
259 I915_GEM_DOMAIN_COMMAND | \
260 I915_GEM_DOMAIN_INSTRUCTION | \
261 I915_GEM_DOMAIN_VERTEX)
263 #define for_each_pipe(__dev_priv, __p) \
264 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
265 #define for_each_plane(__dev_priv, __pipe, __p) \
267 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
269 #define for_each_sprite(__dev_priv, __p, __s) \
271 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
274 #define for_each_crtc(dev, crtc) \
275 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
277 #define for_each_intel_plane(dev, intel_plane) \
278 list_for_each_entry(intel_plane, \
279 &dev->mode_config.plane_list, \
282 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
283 list_for_each_entry(intel_plane, \
284 &(dev)->mode_config.plane_list, \
286 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
288 #define for_each_intel_crtc(dev, intel_crtc) \
289 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
291 #define for_each_intel_encoder(dev, intel_encoder) \
292 list_for_each_entry(intel_encoder, \
293 &(dev)->mode_config.encoder_list, \
296 #define for_each_intel_connector(dev, intel_connector) \
297 list_for_each_entry(intel_connector, \
298 &dev->mode_config.connector_list, \
301 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
302 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
303 for_each_if ((intel_encoder)->base.crtc == (__crtc))
305 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
306 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
307 for_each_if ((intel_connector)->base.encoder == (__encoder))
309 #define for_each_power_domain(domain, mask) \
310 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
311 for_each_if ((1 << (domain)) & (mask))
313 struct drm_i915_private;
314 struct i915_mm_struct;
315 struct i915_mmu_object;
317 struct drm_i915_file_private {
318 struct drm_i915_private *dev_priv;
319 struct drm_file *file;
323 struct list_head request_list;
324 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
325 * chosen to prevent the CPU getting more than a frame ahead of the GPU
326 * (when using lax throttling for the frontbuffer). We also use it to
327 * offer free GPU waitboosts for severely congested workloads.
329 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
331 struct idr context_idr;
333 struct intel_rps_client {
334 struct list_head link;
338 struct intel_engine_cs *bsd_ring;
342 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
343 /* real shared dpll ids must be >= 0 */
344 DPLL_ID_PCH_PLL_A = 0,
345 DPLL_ID_PCH_PLL_B = 1,
352 DPLL_ID_SKL_DPLL1 = 0,
353 DPLL_ID_SKL_DPLL2 = 1,
354 DPLL_ID_SKL_DPLL3 = 2,
356 #define I915_NUM_PLLS 3
358 struct intel_dpll_hw_state {
371 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
372 * lower part of ctrl1 and they get shifted into position when writing
373 * the register. This allows us to easily compare the state to share
377 /* HDMI only, 0 when used for DP */
378 uint32_t cfgcr1, cfgcr2;
381 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
385 struct intel_shared_dpll_config {
386 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
387 struct intel_dpll_hw_state hw_state;
390 struct intel_shared_dpll {
391 struct intel_shared_dpll_config config;
393 int active; /* count of number of active CRTCs (i.e. DPMS on) */
394 bool on; /* is the PLL actually active? Disabled during modeset */
396 /* should match the index in the dev_priv->shared_dplls array */
397 enum intel_dpll_id id;
398 /* The mode_set hook is optional and should be used together with the
399 * intel_prepare_shared_dpll function. */
400 void (*mode_set)(struct drm_i915_private *dev_priv,
401 struct intel_shared_dpll *pll);
402 void (*enable)(struct drm_i915_private *dev_priv,
403 struct intel_shared_dpll *pll);
404 void (*disable)(struct drm_i915_private *dev_priv,
405 struct intel_shared_dpll *pll);
406 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
407 struct intel_shared_dpll *pll,
408 struct intel_dpll_hw_state *hw_state);
416 /* Used by dp and fdi links */
417 struct intel_link_m_n {
425 void intel_link_compute_m_n(int bpp, int nlanes,
426 int pixel_clock, int link_clock,
427 struct intel_link_m_n *m_n);
429 /* Interface history:
432 * 1.2: Add Power Management
433 * 1.3: Add vblank support
434 * 1.4: Fix cmdbuffer path, add heap destroy
435 * 1.5: Add vblank pipe configuration
436 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
437 * - Support vertical blank on secondary display pipe
439 #define DRIVER_MAJOR 1
440 #define DRIVER_MINOR 6
441 #define DRIVER_PATCHLEVEL 0
443 #define WATCH_LISTS 0
445 struct opregion_header;
446 struct opregion_acpi;
447 struct opregion_swsci;
448 struct opregion_asle;
450 struct intel_opregion {
451 struct opregion_header *header;
452 struct opregion_acpi *acpi;
453 struct opregion_swsci *swsci;
454 u32 swsci_gbda_sub_functions;
455 u32 swsci_sbcb_sub_functions;
456 struct opregion_asle *asle;
461 struct work_struct asle_work;
463 #define OPREGION_SIZE (8*1024)
465 struct intel_overlay;
466 struct intel_overlay_error_state;
468 #define I915_FENCE_REG_NONE -1
469 #define I915_MAX_NUM_FENCES 32
470 /* 32 fences + sign bit for FENCE_REG_NONE */
471 #define I915_MAX_NUM_FENCE_BITS 6
473 struct drm_i915_fence_reg {
474 struct list_head lru_list;
475 struct drm_i915_gem_object *obj;
479 struct sdvo_device_mapping {
488 struct intel_display_error_state;
490 struct drm_i915_error_state {
499 /* Generic register state */
507 u32 error; /* gen6+ */
508 u32 err_int; /* gen7 */
509 u32 fault_data0; /* gen8, gen9 */
510 u32 fault_data1; /* gen8, gen9 */
516 u32 extra_instdone[I915_NUM_INSTDONE_REG];
517 u64 fence[I915_MAX_NUM_FENCES];
518 struct intel_overlay_error_state *overlay;
519 struct intel_display_error_state *display;
520 struct drm_i915_error_object *semaphore_obj;
522 struct drm_i915_error_ring {
524 /* Software tracked state */
527 enum intel_ring_hangcheck_action hangcheck_action;
530 /* our own tracking of ring head and tail */
534 u32 semaphore_seqno[I915_NUM_RINGS - 1];
553 u32 rc_psmi; /* sleep state */
554 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
556 struct drm_i915_error_object {
560 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
562 struct drm_i915_error_request {
577 char comm[TASK_COMM_LEN];
578 } ring[I915_NUM_RINGS];
580 struct drm_i915_error_buffer {
583 u32 rseqno[I915_NUM_RINGS], wseqno;
587 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
595 } **active_bo, **pinned_bo;
597 u32 *active_bo_count, *pinned_bo_count;
601 struct intel_connector;
602 struct intel_encoder;
603 struct intel_crtc_state;
604 struct intel_initial_plane_config;
609 struct drm_i915_display_funcs {
610 int (*get_display_clock_speed)(struct drm_device *dev);
611 int (*get_fifo_size)(struct drm_device *dev, int plane);
613 * find_dpll() - Find the best values for the PLL
614 * @limit: limits for the PLL
615 * @crtc: current CRTC
616 * @target: target frequency in kHz
617 * @refclk: reference clock frequency in kHz
618 * @match_clock: if provided, @best_clock P divider must
619 * match the P divider from @match_clock
620 * used for LVDS downclocking
621 * @best_clock: best PLL values found
623 * Returns true on success, false on failure.
625 bool (*find_dpll)(const struct intel_limit *limit,
626 struct intel_crtc_state *crtc_state,
627 int target, int refclk,
628 struct dpll *match_clock,
629 struct dpll *best_clock);
630 int (*compute_pipe_wm)(struct intel_crtc *crtc,
631 struct drm_atomic_state *state);
632 void (*update_wm)(struct drm_crtc *crtc);
633 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
634 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
635 /* Returns the active state of the crtc, and if the crtc is active,
636 * fills out the pipe-config with the hw state. */
637 bool (*get_pipe_config)(struct intel_crtc *,
638 struct intel_crtc_state *);
639 void (*get_initial_plane_config)(struct intel_crtc *,
640 struct intel_initial_plane_config *);
641 int (*crtc_compute_clock)(struct intel_crtc *crtc,
642 struct intel_crtc_state *crtc_state);
643 void (*crtc_enable)(struct drm_crtc *crtc);
644 void (*crtc_disable)(struct drm_crtc *crtc);
645 void (*audio_codec_enable)(struct drm_connector *connector,
646 struct intel_encoder *encoder,
647 const struct drm_display_mode *adjusted_mode);
648 void (*audio_codec_disable)(struct intel_encoder *encoder);
649 void (*fdi_link_train)(struct drm_crtc *crtc);
650 void (*init_clock_gating)(struct drm_device *dev);
651 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
652 struct drm_framebuffer *fb,
653 struct drm_i915_gem_object *obj,
654 struct drm_i915_gem_request *req,
656 void (*update_primary_plane)(struct drm_crtc *crtc,
657 struct drm_framebuffer *fb,
659 void (*hpd_irq_setup)(struct drm_device *dev);
660 /* clock updates for mode set */
662 /* render clock increase/decrease */
663 /* display clock increase/decrease */
664 /* pll clock increase/decrease */
667 enum forcewake_domain_id {
668 FW_DOMAIN_ID_RENDER = 0,
669 FW_DOMAIN_ID_BLITTER,
675 enum forcewake_domains {
676 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
677 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
678 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
679 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
684 struct intel_uncore_funcs {
685 void (*force_wake_get)(struct drm_i915_private *dev_priv,
686 enum forcewake_domains domains);
687 void (*force_wake_put)(struct drm_i915_private *dev_priv,
688 enum forcewake_domains domains);
690 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
691 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
692 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
693 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
695 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
696 uint8_t val, bool trace);
697 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
698 uint16_t val, bool trace);
699 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
700 uint32_t val, bool trace);
701 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
702 uint64_t val, bool trace);
705 struct intel_uncore {
706 spinlock_t lock; /** lock is also taken in irq contexts. */
708 struct intel_uncore_funcs funcs;
711 enum forcewake_domains fw_domains;
713 struct intel_uncore_forcewake_domain {
714 struct drm_i915_private *i915;
715 enum forcewake_domain_id id;
717 struct timer_list timer;
724 } fw_domain[FW_DOMAIN_ID_COUNT];
727 /* Iterate over initialised fw domains */
728 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
729 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
730 (i__) < FW_DOMAIN_ID_COUNT; \
731 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
732 for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
734 #define for_each_fw_domain(domain__, dev_priv__, i__) \
735 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
737 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
738 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
739 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
742 struct work_struct work;
744 uint32_t *dmc_payload;
745 uint32_t dmc_fw_size;
748 i915_reg_t mmioaddr[8];
749 uint32_t mmiodata[8];
752 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
753 func(is_mobile) sep \
756 func(is_i945gm) sep \
758 func(need_gfx_hws) sep \
760 func(is_pineview) sep \
761 func(is_broadwater) sep \
762 func(is_crestline) sep \
763 func(is_ivybridge) sep \
764 func(is_valleyview) sep \
765 func(is_cherryview) sep \
766 func(is_haswell) sep \
767 func(is_skylake) sep \
768 func(is_broxton) sep \
769 func(is_kabylake) sep \
770 func(is_preliminary) sep \
772 func(has_pipe_cxsr) sep \
773 func(has_hotplug) sep \
774 func(cursor_needs_physical) sep \
775 func(has_overlay) sep \
776 func(overlay_needs_physical) sep \
777 func(supports_tv) sep \
782 #define DEFINE_FLAG(name) u8 name:1
783 #define SEP_SEMICOLON ;
785 struct intel_device_info {
786 u32 display_mmio_offset;
789 u8 num_sprites[I915_MAX_PIPES];
791 u8 ring_mask; /* Rings supported by the HW */
792 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
793 /* Register offsets for the various display pipes and transcoders */
794 int pipe_offsets[I915_MAX_TRANSCODERS];
795 int trans_offsets[I915_MAX_TRANSCODERS];
796 int palette_offsets[I915_MAX_PIPES];
797 int cursor_offsets[I915_MAX_PIPES];
799 /* Slice/subslice/EU info */
802 u8 subslice_per_slice;
805 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
808 u8 has_subslice_pg:1;
815 enum i915_cache_level {
817 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
818 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
819 caches, eg sampler/render caches, and the
820 large Last-Level-Cache. LLC is coherent with
821 the CPU, but L3 is only visible to the GPU. */
822 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
825 struct i915_ctx_hang_stats {
826 /* This context had batch pending when hang was declared */
827 unsigned batch_pending;
829 /* This context had batch active when hang was declared */
830 unsigned batch_active;
832 /* Time when this context was last blamed for a GPU reset */
833 unsigned long guilty_ts;
835 /* If the contexts causes a second GPU hang within this time,
836 * it is permanently banned from submitting any more work.
838 unsigned long ban_period_seconds;
840 /* This context is banned to submit more work */
844 /* This must match up with the value previously used for execbuf2.rsvd1. */
845 #define DEFAULT_CONTEXT_HANDLE 0
847 #define CONTEXT_NO_ZEROMAP (1<<0)
849 * struct intel_context - as the name implies, represents a context.
850 * @ref: reference count.
851 * @user_handle: userspace tracking identity for this context.
852 * @remap_slice: l3 row remapping information.
853 * @flags: context specific flags:
854 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
855 * @file_priv: filp associated with this context (NULL for global default
857 * @hang_stats: information about the role of this context in possible GPU
859 * @ppgtt: virtual memory space used by this context.
860 * @legacy_hw_ctx: render context backing object and whether it is correctly
861 * initialized (legacy ring submission mechanism only).
862 * @link: link in the global list of contexts.
864 * Contexts are memory images used by the hardware to store copies of their
867 struct intel_context {
871 struct drm_i915_private *i915;
873 struct drm_i915_file_private *file_priv;
874 struct i915_ctx_hang_stats hang_stats;
875 struct i915_hw_ppgtt *ppgtt;
877 /* Legacy ring buffer submission */
879 struct drm_i915_gem_object *rcs_state;
885 struct drm_i915_gem_object *state;
886 struct intel_ringbuffer *ringbuf;
888 } engine[I915_NUM_RINGS];
890 struct list_head link;
902 /* This is always the inner lock when overlapping with struct_mutex and
903 * it's the outer lock when overlapping with stolen_lock. */
907 unsigned int possible_framebuffer_bits;
908 unsigned int busy_bits;
909 struct intel_crtc *crtc;
912 struct drm_mm_node compressed_fb;
913 struct drm_mm_node *compressed_llb;
920 struct intel_fbc_work {
922 struct work_struct work;
923 struct drm_framebuffer *fb;
924 unsigned long enable_jiffies;
927 const char *no_fbc_reason;
929 bool (*is_active)(struct drm_i915_private *dev_priv);
930 void (*activate)(struct intel_crtc *crtc);
931 void (*deactivate)(struct drm_i915_private *dev_priv);
935 * HIGH_RR is the highest eDP panel refresh rate read from EDID
936 * LOW_RR is the lowest eDP panel refresh rate found from EDID
937 * parsing for same resolution.
939 enum drrs_refresh_rate_type {
942 DRRS_MAX_RR, /* RR count */
945 enum drrs_support_type {
946 DRRS_NOT_SUPPORTED = 0,
947 STATIC_DRRS_SUPPORT = 1,
948 SEAMLESS_DRRS_SUPPORT = 2
954 struct delayed_work work;
956 unsigned busy_frontbuffer_bits;
957 enum drrs_refresh_rate_type refresh_rate_type;
958 enum drrs_support_type type;
965 struct intel_dp *enabled;
967 struct delayed_work work;
968 unsigned busy_frontbuffer_bits;
974 PCH_NONE = 0, /* No PCH present */
975 PCH_IBX, /* Ibexpeak PCH */
976 PCH_CPT, /* Cougarpoint PCH */
977 PCH_LPT, /* Lynxpoint PCH */
978 PCH_SPT, /* Sunrisepoint PCH */
982 enum intel_sbi_destination {
987 #define QUIRK_PIPEA_FORCE (1<<0)
988 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
989 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
990 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
991 #define QUIRK_PIPEB_FORCE (1<<4)
992 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
995 struct intel_fbc_work;
998 struct i2c_adapter adapter;
1001 i915_reg_t gpio_reg;
1002 struct i2c_algo_bit_data bit_algo;
1003 struct drm_i915_private *dev_priv;
1006 struct i915_suspend_saved_registers {
1009 u32 savePP_ON_DELAYS;
1010 u32 savePP_OFF_DELAYS;
1015 u32 saveFBC_CONTROL;
1016 u32 saveCACHE_MODE_0;
1017 u32 saveMI_ARB_STATE;
1021 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1022 u32 savePCH_PORT_HOTPLUG;
1026 struct vlv_s0ix_state {
1033 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1034 u32 media_max_req_count;
1035 u32 gfx_max_req_count;
1061 u32 rp_down_timeout;
1067 /* Display 1 CZ domain */
1072 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1074 /* GT SA CZ domain */
1081 /* Display 2 CZ domain */
1085 u32 clock_gate_dis2;
1088 struct intel_rps_ei {
1094 struct intel_gen6_power_mgmt {
1096 * work, interrupts_enabled and pm_iir are protected by
1097 * dev_priv->irq_lock
1099 struct work_struct work;
1100 bool interrupts_enabled;
1103 /* Frequencies are stored in potentially platform dependent multiples.
1104 * In other words, *_freq needs to be multiplied by X to be interesting.
1105 * Soft limits are those which are used for the dynamic reclocking done
1106 * by the driver (raise frequencies under heavy loads, and lower for
1107 * lighter loads). Hard limits are those imposed by the hardware.
1109 * A distinction is made for overclocking, which is never enabled by
1110 * default, and is considered to be above the hard limit if it's
1113 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1114 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1115 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1116 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1117 u8 min_freq; /* AKA RPn. Minimum frequency */
1118 u8 idle_freq; /* Frequency to request when we are idle */
1119 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1120 u8 rp1_freq; /* "less than" RP0 power/freqency */
1121 u8 rp0_freq; /* Non-overclocked max frequency. */
1123 u8 up_threshold; /* Current %busy required to uplock */
1124 u8 down_threshold; /* Current %busy required to downclock */
1127 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1129 spinlock_t client_lock;
1130 struct list_head clients;
1134 struct delayed_work delayed_resume_work;
1137 struct intel_rps_client semaphores, mmioflips;
1139 /* manual wa residency calculations */
1140 struct intel_rps_ei up_ei, down_ei;
1143 * Protects RPS/RC6 register access and PCU communication.
1144 * Must be taken after struct_mutex if nested. Note that
1145 * this lock may be held for long periods of time when
1146 * talking to hw - so only take it when talking to hw!
1148 struct mutex hw_lock;
1151 /* defined intel_pm.c */
1152 extern spinlock_t mchdev_lock;
1154 struct intel_ilk_power_mgmt {
1162 unsigned long last_time1;
1163 unsigned long chipset_power;
1166 unsigned long gfx_power;
1173 struct drm_i915_private;
1174 struct i915_power_well;
1176 struct i915_power_well_ops {
1178 * Synchronize the well's hw state to match the current sw state, for
1179 * example enable/disable it based on the current refcount. Called
1180 * during driver init and resume time, possibly after first calling
1181 * the enable/disable handlers.
1183 void (*sync_hw)(struct drm_i915_private *dev_priv,
1184 struct i915_power_well *power_well);
1186 * Enable the well and resources that depend on it (for example
1187 * interrupts located on the well). Called after the 0->1 refcount
1190 void (*enable)(struct drm_i915_private *dev_priv,
1191 struct i915_power_well *power_well);
1193 * Disable the well and resources that depend on it. Called after
1194 * the 1->0 refcount transition.
1196 void (*disable)(struct drm_i915_private *dev_priv,
1197 struct i915_power_well *power_well);
1198 /* Returns the hw enabled state. */
1199 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1200 struct i915_power_well *power_well);
1203 /* Power well structure for haswell */
1204 struct i915_power_well {
1207 /* power well enable/disable usage count */
1209 /* cached hw enabled state */
1211 unsigned long domains;
1213 const struct i915_power_well_ops *ops;
1216 struct i915_power_domains {
1218 * Power wells needed for initialization at driver init and suspend
1219 * time are on. They are kept on until after the first modeset.
1223 int power_well_count;
1226 int domain_use_count[POWER_DOMAIN_NUM];
1227 struct i915_power_well *power_wells;
1230 #define MAX_L3_SLICES 2
1231 struct intel_l3_parity {
1232 u32 *remap_info[MAX_L3_SLICES];
1233 struct work_struct error_work;
1237 struct i915_gem_mm {
1238 /** Memory allocator for GTT stolen memory */
1239 struct drm_mm stolen;
1240 /** Protects the usage of the GTT stolen memory allocator. This is
1241 * always the inner lock when overlapping with struct_mutex. */
1242 struct mutex stolen_lock;
1244 /** List of all objects in gtt_space. Used to restore gtt
1245 * mappings on resume */
1246 struct list_head bound_list;
1248 * List of objects which are not bound to the GTT (thus
1249 * are idle and not used by the GPU) but still have
1250 * (presumably uncached) pages still attached.
1252 struct list_head unbound_list;
1254 /** Usable portion of the GTT for GEM */
1255 unsigned long stolen_base; /* limited to low memory (32-bit) */
1257 /** PPGTT used for aliasing the PPGTT with the GTT */
1258 struct i915_hw_ppgtt *aliasing_ppgtt;
1260 struct notifier_block oom_notifier;
1261 struct shrinker shrinker;
1262 bool shrinker_no_lock_stealing;
1264 /** LRU list of objects with fence regs on them. */
1265 struct list_head fence_list;
1268 * We leave the user IRQ off as much as possible,
1269 * but this means that requests will finish and never
1270 * be retired once the system goes idle. Set a timer to
1271 * fire periodically while the ring is running. When it
1272 * fires, go retire requests.
1274 struct delayed_work retire_work;
1277 * When we detect an idle GPU, we want to turn on
1278 * powersaving features. So once we see that there
1279 * are no more requests outstanding and no more
1280 * arrive within a small period of time, we fire
1281 * off the idle_work.
1283 struct delayed_work idle_work;
1286 * Are we in a non-interruptible section of code like
1292 * Is the GPU currently considered idle, or busy executing userspace
1293 * requests? Whilst idle, we attempt to power down the hardware and
1294 * display clocks. In order to reduce the effect on performance, there
1295 * is a slight delay before we do so.
1299 /* the indicator for dispatch video commands on two BSD rings */
1300 int bsd_ring_dispatch_index;
1302 /** Bit 6 swizzling required for X tiling */
1303 uint32_t bit_6_swizzle_x;
1304 /** Bit 6 swizzling required for Y tiling */
1305 uint32_t bit_6_swizzle_y;
1307 /* accounting, useful for userland debugging */
1308 spinlock_t object_stat_lock;
1309 size_t object_memory;
1313 struct drm_i915_error_state_buf {
1314 struct drm_i915_private *i915;
1323 struct i915_error_state_file_priv {
1324 struct drm_device *dev;
1325 struct drm_i915_error_state *error;
1328 struct i915_gpu_error {
1329 /* For hangcheck timer */
1330 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1331 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1332 /* Hang gpu twice in this window and your context gets banned */
1333 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1335 struct workqueue_struct *hangcheck_wq;
1336 struct delayed_work hangcheck_work;
1338 /* For reset and error_state handling. */
1340 /* Protected by the above dev->gpu_error.lock. */
1341 struct drm_i915_error_state *first_error;
1343 unsigned long missed_irq_rings;
1346 * State variable controlling the reset flow and count
1348 * This is a counter which gets incremented when reset is triggered,
1349 * and again when reset has been handled. So odd values (lowest bit set)
1350 * means that reset is in progress and even values that
1351 * (reset_counter >> 1):th reset was successfully completed.
1353 * If reset is not completed succesfully, the I915_WEDGE bit is
1354 * set meaning that hardware is terminally sour and there is no
1355 * recovery. All waiters on the reset_queue will be woken when
1358 * This counter is used by the wait_seqno code to notice that reset
1359 * event happened and it needs to restart the entire ioctl (since most
1360 * likely the seqno it waited for won't ever signal anytime soon).
1362 * This is important for lock-free wait paths, where no contended lock
1363 * naturally enforces the correct ordering between the bail-out of the
1364 * waiter and the gpu reset work code.
1366 atomic_t reset_counter;
1368 #define I915_RESET_IN_PROGRESS_FLAG 1
1369 #define I915_WEDGED (1 << 31)
1372 * Waitqueue to signal when the reset has completed. Used by clients
1373 * that wait for dev_priv->mm.wedged to settle.
1375 wait_queue_head_t reset_queue;
1377 /* Userspace knobs for gpu hang simulation;
1378 * combines both a ring mask, and extra flags
1381 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1382 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1384 /* For missed irq/seqno simulation. */
1385 unsigned int test_irq_rings;
1387 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1388 bool reload_in_reset;
1391 enum modeset_restore {
1392 MODESET_ON_LID_OPEN,
1397 #define DP_AUX_A 0x40
1398 #define DP_AUX_B 0x10
1399 #define DP_AUX_C 0x20
1400 #define DP_AUX_D 0x30
1402 #define DDC_PIN_B 0x05
1403 #define DDC_PIN_C 0x04
1404 #define DDC_PIN_D 0x06
1406 struct ddi_vbt_port_info {
1408 * This is an index in the HDMI/DVI DDI buffer translation table.
1409 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1410 * populate this field.
1412 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1413 uint8_t hdmi_level_shift;
1415 uint8_t supports_dvi:1;
1416 uint8_t supports_hdmi:1;
1417 uint8_t supports_dp:1;
1419 uint8_t alternate_aux_channel;
1420 uint8_t alternate_ddc_pin;
1422 uint8_t dp_boost_level;
1423 uint8_t hdmi_boost_level;
1426 enum psr_lines_to_wait {
1427 PSR_0_LINES_TO_WAIT = 0,
1429 PSR_4_LINES_TO_WAIT,
1433 struct intel_vbt_data {
1434 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1435 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1438 unsigned int int_tv_support:1;
1439 unsigned int lvds_dither:1;
1440 unsigned int lvds_vbt:1;
1441 unsigned int int_crt_support:1;
1442 unsigned int lvds_use_ssc:1;
1443 unsigned int display_clock_mode:1;
1444 unsigned int fdi_rx_polarity_inverted:1;
1445 unsigned int has_mipi:1;
1447 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1449 enum drrs_support_type drrs_type;
1454 int edp_preemphasis;
1456 bool edp_initialized;
1459 struct edp_power_seq edp_pps;
1463 bool require_aux_wakeup;
1465 enum psr_lines_to_wait lines_to_wait;
1466 int tp1_wakeup_time;
1467 int tp2_tp3_wakeup_time;
1473 bool active_low_pwm;
1474 u8 min_brightness; /* min_brightness/255 of max */
1481 struct mipi_config *config;
1482 struct mipi_pps_data *pps;
1486 u8 *sequence[MIPI_SEQ_MAX];
1492 union child_device_config *child_dev;
1494 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1497 enum intel_ddb_partitioning {
1499 INTEL_DDB_PART_5_6, /* IVB+ */
1502 struct intel_wm_level {
1510 struct ilk_wm_values {
1511 uint32_t wm_pipe[3];
1513 uint32_t wm_lp_spr[3];
1514 uint32_t wm_linetime[3];
1516 enum intel_ddb_partitioning partitioning;
1519 struct vlv_pipe_wm {
1530 struct vlv_wm_values {
1531 struct vlv_pipe_wm pipe[3];
1532 struct vlv_sr_wm sr;
1542 struct skl_ddb_entry {
1543 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1546 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1548 return entry->end - entry->start;
1551 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1552 const struct skl_ddb_entry *e2)
1554 if (e1->start == e2->start && e1->end == e2->end)
1560 struct skl_ddb_allocation {
1561 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1562 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1563 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1566 struct skl_wm_values {
1567 bool dirty[I915_MAX_PIPES];
1568 struct skl_ddb_allocation ddb;
1569 uint32_t wm_linetime[I915_MAX_PIPES];
1570 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1571 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1574 struct skl_wm_level {
1575 bool plane_en[I915_MAX_PLANES];
1576 uint16_t plane_res_b[I915_MAX_PLANES];
1577 uint8_t plane_res_l[I915_MAX_PLANES];
1581 * This struct helps tracking the state needed for runtime PM, which puts the
1582 * device in PCI D3 state. Notice that when this happens, nothing on the
1583 * graphics device works, even register access, so we don't get interrupts nor
1586 * Every piece of our code that needs to actually touch the hardware needs to
1587 * either call intel_runtime_pm_get or call intel_display_power_get with the
1588 * appropriate power domain.
1590 * Our driver uses the autosuspend delay feature, which means we'll only really
1591 * suspend if we stay with zero refcount for a certain amount of time. The
1592 * default value is currently very conservative (see intel_runtime_pm_enable), but
1593 * it can be changed with the standard runtime PM files from sysfs.
1595 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1596 * goes back to false exactly before we reenable the IRQs. We use this variable
1597 * to check if someone is trying to enable/disable IRQs while they're supposed
1598 * to be disabled. This shouldn't happen and we'll print some error messages in
1601 * For more, read the Documentation/power/runtime_pm.txt.
1603 struct i915_runtime_pm {
1604 atomic_t wakeref_count;
1605 atomic_t atomic_seq;
1610 enum intel_pipe_crc_source {
1611 INTEL_PIPE_CRC_SOURCE_NONE,
1612 INTEL_PIPE_CRC_SOURCE_PLANE1,
1613 INTEL_PIPE_CRC_SOURCE_PLANE2,
1614 INTEL_PIPE_CRC_SOURCE_PF,
1615 INTEL_PIPE_CRC_SOURCE_PIPE,
1616 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1617 INTEL_PIPE_CRC_SOURCE_TV,
1618 INTEL_PIPE_CRC_SOURCE_DP_B,
1619 INTEL_PIPE_CRC_SOURCE_DP_C,
1620 INTEL_PIPE_CRC_SOURCE_DP_D,
1621 INTEL_PIPE_CRC_SOURCE_AUTO,
1622 INTEL_PIPE_CRC_SOURCE_MAX,
1625 struct intel_pipe_crc_entry {
1630 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1631 struct intel_pipe_crc {
1633 bool opened; /* exclusive access to the result file */
1634 struct intel_pipe_crc_entry *entries;
1635 enum intel_pipe_crc_source source;
1637 wait_queue_head_t wq;
1640 struct i915_frontbuffer_tracking {
1644 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1651 struct i915_wa_reg {
1654 /* bitmask representing WA bits */
1658 #define I915_MAX_WA_REGS 16
1660 struct i915_workarounds {
1661 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1665 struct i915_virtual_gpu {
1669 struct i915_execbuffer_params {
1670 struct drm_device *dev;
1671 struct drm_file *file;
1672 uint32_t dispatch_flags;
1673 uint32_t args_batch_start_offset;
1674 uint64_t batch_obj_vm_offset;
1675 struct intel_engine_cs *ring;
1676 struct drm_i915_gem_object *batch_obj;
1677 struct intel_context *ctx;
1678 struct drm_i915_gem_request *request;
1681 /* used in computing the new watermarks state */
1682 struct intel_wm_config {
1683 unsigned int num_pipes_active;
1684 bool sprites_enabled;
1685 bool sprites_scaled;
1688 struct drm_i915_private {
1689 struct drm_device *dev;
1690 struct kmem_cache *objects;
1691 struct kmem_cache *vmas;
1692 struct kmem_cache *requests;
1694 const struct intel_device_info info;
1696 int relative_constants_mode;
1700 struct intel_uncore uncore;
1702 struct i915_virtual_gpu vgpu;
1704 struct intel_guc guc;
1706 struct intel_csr csr;
1708 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1710 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1711 * controller on different i2c buses. */
1712 struct mutex gmbus_mutex;
1715 * Base address of the gmbus and gpio block.
1717 uint32_t gpio_mmio_base;
1719 /* MMIO base address for MIPI regs */
1720 uint32_t mipi_mmio_base;
1722 uint32_t psr_mmio_base;
1724 wait_queue_head_t gmbus_wait_queue;
1726 struct pci_dev *bridge_dev;
1727 struct intel_engine_cs ring[I915_NUM_RINGS];
1728 struct drm_i915_gem_object *semaphore_obj;
1729 uint32_t last_seqno, next_seqno;
1731 struct drm_dma_handle *status_page_dmah;
1732 struct resource mch_res;
1734 /* protects the irq masks */
1735 spinlock_t irq_lock;
1737 /* protects the mmio flip data */
1738 spinlock_t mmio_flip_lock;
1740 bool display_irqs_enabled;
1742 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1743 struct pm_qos_request pm_qos;
1745 /* Sideband mailbox protection */
1746 struct mutex sb_lock;
1748 /** Cached value of IMR to avoid reads in updating the bitfield */
1751 u32 de_irq_mask[I915_MAX_PIPES];
1756 u32 pipestat_irq_mask[I915_MAX_PIPES];
1758 struct i915_hotplug hotplug;
1759 struct i915_fbc fbc;
1760 struct i915_drrs drrs;
1761 struct intel_opregion opregion;
1762 struct intel_vbt_data vbt;
1764 bool preserve_bios_swizzle;
1767 struct intel_overlay *overlay;
1769 /* backlight registers and fields in struct intel_panel */
1770 struct mutex backlight_lock;
1773 bool no_aux_handshake;
1775 /* protects panel power sequencer state */
1776 struct mutex pps_mutex;
1778 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1779 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1781 unsigned int fsb_freq, mem_freq, is_ddr3;
1782 unsigned int skl_boot_cdclk;
1783 unsigned int cdclk_freq, max_cdclk_freq;
1784 unsigned int max_dotclk_freq;
1785 unsigned int hpll_freq;
1786 unsigned int czclk_freq;
1789 * wq - Driver workqueue for GEM.
1791 * NOTE: Work items scheduled here are not allowed to grab any modeset
1792 * locks, for otherwise the flushing done in the pageflip code will
1793 * result in deadlocks.
1795 struct workqueue_struct *wq;
1797 /* Display functions */
1798 struct drm_i915_display_funcs display;
1800 /* PCH chipset type */
1801 enum intel_pch pch_type;
1802 unsigned short pch_id;
1804 unsigned long quirks;
1806 enum modeset_restore modeset_restore;
1807 struct mutex modeset_restore_lock;
1809 struct list_head vm_list; /* Global list of all address spaces */
1810 struct i915_gtt gtt; /* VM representing the global address space */
1812 struct i915_gem_mm mm;
1813 DECLARE_HASHTABLE(mm_structs, 7);
1814 struct mutex mm_lock;
1816 /* Kernel Modesetting */
1818 struct sdvo_device_mapping sdvo_mappings[2];
1820 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1821 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1822 wait_queue_head_t pending_flip_queue;
1824 #ifdef CONFIG_DEBUG_FS
1825 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1828 int num_shared_dpll;
1829 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1830 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1832 struct i915_workarounds workarounds;
1834 /* Reclocking support */
1835 bool render_reclock_avail;
1837 struct i915_frontbuffer_tracking fb_tracking;
1841 bool mchbar_need_disable;
1843 struct intel_l3_parity l3_parity;
1845 /* Cannot be determined by PCIID. You must always read a register. */
1848 /* gen6+ rps state */
1849 struct intel_gen6_power_mgmt rps;
1851 /* ilk-only ips/rps state. Everything in here is protected by the global
1852 * mchdev_lock in intel_pm.c */
1853 struct intel_ilk_power_mgmt ips;
1855 struct i915_power_domains power_domains;
1857 struct i915_psr psr;
1859 struct i915_gpu_error gpu_error;
1861 struct drm_i915_gem_object *vlv_pctx;
1863 #ifdef CONFIG_DRM_FBDEV_EMULATION
1864 /* list of fbdev register on this device */
1865 struct intel_fbdev *fbdev;
1866 struct work_struct fbdev_suspend_work;
1869 struct drm_property *broadcast_rgb_property;
1870 struct drm_property *force_audio_property;
1872 /* hda/i915 audio component */
1873 struct i915_audio_component *audio_component;
1874 bool audio_component_registered;
1876 * av_mutex - mutex for audio/video sync
1879 struct mutex av_mutex;
1881 uint32_t hw_context_size;
1882 struct list_head context_list;
1886 u32 chv_phy_control;
1889 bool suspended_to_idle;
1890 struct i915_suspend_saved_registers regfile;
1891 struct vlv_s0ix_state vlv_s0ix_state;
1895 * Raw watermark latency values:
1896 * in 0.1us units for WM0,
1897 * in 0.5us units for WM1+.
1900 uint16_t pri_latency[5];
1902 uint16_t spr_latency[5];
1904 uint16_t cur_latency[5];
1906 * Raw watermark memory latency values
1907 * for SKL for all 8 levels
1910 uint16_t skl_latency[8];
1912 /* Committed wm config */
1913 struct intel_wm_config config;
1916 * The skl_wm_values structure is a bit too big for stack
1917 * allocation, so we keep the staging struct where we store
1918 * intermediate results here instead.
1920 struct skl_wm_values skl_results;
1922 /* current hardware state */
1924 struct ilk_wm_values hw;
1925 struct skl_wm_values skl_hw;
1926 struct vlv_wm_values vlv;
1932 struct i915_runtime_pm pm;
1934 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1936 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1937 struct drm_i915_gem_execbuffer2 *args,
1938 struct list_head *vmas);
1939 int (*init_rings)(struct drm_device *dev);
1940 void (*cleanup_ring)(struct intel_engine_cs *ring);
1941 void (*stop_ring)(struct intel_engine_cs *ring);
1944 bool edp_low_vswing;
1946 /* perform PHY state sanity checks? */
1947 bool chv_phy_assert[2];
1949 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
1952 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1953 * will be rejected. Instead look for a better place.
1957 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1959 return dev->dev_private;
1962 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1964 return to_i915(dev_get_drvdata(dev));
1967 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
1969 return container_of(guc, struct drm_i915_private, guc);
1972 /* Iterate over initialised rings */
1973 #define for_each_ring(ring__, dev_priv__, i__) \
1974 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1975 for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))))
1977 enum hdmi_force_audio {
1978 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1979 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1980 HDMI_AUDIO_AUTO, /* trust EDID */
1981 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1984 #define I915_GTT_OFFSET_NONE ((u32)-1)
1986 struct drm_i915_gem_object_ops {
1987 /* Interface between the GEM object and its backing storage.
1988 * get_pages() is called once prior to the use of the associated set
1989 * of pages before to binding them into the GTT, and put_pages() is
1990 * called after we no longer need them. As we expect there to be
1991 * associated cost with migrating pages between the backing storage
1992 * and making them available for the GPU (e.g. clflush), we may hold
1993 * onto the pages after they are no longer referenced by the GPU
1994 * in case they may be used again shortly (for example migrating the
1995 * pages to a different memory domain within the GTT). put_pages()
1996 * will therefore most likely be called when the object itself is
1997 * being released or under memory pressure (where we attempt to
1998 * reap pages for the shrinker).
2000 int (*get_pages)(struct drm_i915_gem_object *);
2001 void (*put_pages)(struct drm_i915_gem_object *);
2002 int (*dmabuf_export)(struct drm_i915_gem_object *);
2003 void (*release)(struct drm_i915_gem_object *);
2007 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2008 * considered to be the frontbuffer for the given plane interface-wise. This
2009 * doesn't mean that the hw necessarily already scans it out, but that any
2010 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2012 * We have one bit per pipe and per scanout plane type.
2014 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2015 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2016 #define INTEL_FRONTBUFFER_BITS \
2017 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2018 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2019 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2020 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2021 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2022 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2023 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2024 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2025 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2026 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2027 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2029 struct drm_i915_gem_object {
2030 struct drm_gem_object base;
2032 const struct drm_i915_gem_object_ops *ops;
2034 /** List of VMAs backed by this object */
2035 struct list_head vma_list;
2037 /** Stolen memory for this object, instead of being backed by shmem. */
2038 struct drm_mm_node *stolen;
2039 struct list_head global_list;
2041 struct list_head ring_list[I915_NUM_RINGS];
2042 /** Used in execbuf to temporarily hold a ref */
2043 struct list_head obj_exec_link;
2045 struct list_head batch_pool_link;
2048 * This is set if the object is on the active lists (has pending
2049 * rendering and so a non-zero seqno), and is not set if it i s on
2050 * inactive (ready to be unbound) list.
2052 unsigned int active:I915_NUM_RINGS;
2055 * This is set if the object has been written to since last bound
2058 unsigned int dirty:1;
2061 * Fence register bits (if any) for this object. Will be set
2062 * as needed when mapped into the GTT.
2063 * Protected by dev->struct_mutex.
2065 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2068 * Advice: are the backing pages purgeable?
2070 unsigned int madv:2;
2073 * Current tiling mode for the object.
2075 unsigned int tiling_mode:2;
2077 * Whether the tiling parameters for the currently associated fence
2078 * register have changed. Note that for the purposes of tracking
2079 * tiling changes we also treat the unfenced register, the register
2080 * slot that the object occupies whilst it executes a fenced
2081 * command (such as BLT on gen2/3), as a "fence".
2083 unsigned int fence_dirty:1;
2086 * Is the object at the current location in the gtt mappable and
2087 * fenceable? Used to avoid costly recalculations.
2089 unsigned int map_and_fenceable:1;
2092 * Whether the current gtt mapping needs to be mappable (and isn't just
2093 * mappable by accident). Track pin and fault separate for a more
2094 * accurate mappable working set.
2096 unsigned int fault_mappable:1;
2099 * Is the object to be mapped as read-only to the GPU
2100 * Only honoured if hardware has relevant pte bit
2102 unsigned long gt_ro:1;
2103 unsigned int cache_level:3;
2104 unsigned int cache_dirty:1;
2106 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2108 unsigned int pin_display;
2110 struct sg_table *pages;
2111 int pages_pin_count;
2113 struct scatterlist *sg;
2117 /* prime dma-buf support */
2118 void *dma_buf_vmapping;
2121 /** Breadcrumb of last rendering to the buffer.
2122 * There can only be one writer, but we allow for multiple readers.
2123 * If there is a writer that necessarily implies that all other
2124 * read requests are complete - but we may only be lazily clearing
2125 * the read requests. A read request is naturally the most recent
2126 * request on a ring, so we may have two different write and read
2127 * requests on one ring where the write request is older than the
2128 * read request. This allows for the CPU to read from an active
2129 * buffer by only waiting for the write to complete.
2131 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2132 struct drm_i915_gem_request *last_write_req;
2133 /** Breadcrumb of last fenced GPU access to the buffer. */
2134 struct drm_i915_gem_request *last_fenced_req;
2136 /** Current tiling stride for the object, if it's tiled. */
2139 /** References from framebuffers, locks out tiling changes. */
2140 unsigned long framebuffer_references;
2142 /** Record of address bit 17 of each page at last unbind. */
2143 unsigned long *bit_17;
2146 /** for phy allocated objects */
2147 struct drm_dma_handle *phys_handle;
2149 struct i915_gem_userptr {
2151 unsigned read_only :1;
2152 unsigned workers :4;
2153 #define I915_GEM_USERPTR_MAX_WORKERS 15
2155 struct i915_mm_struct *mm;
2156 struct i915_mmu_object *mmu_object;
2157 struct work_struct *work;
2161 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2163 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2164 struct drm_i915_gem_object *new,
2165 unsigned frontbuffer_bits);
2168 * Request queue structure.
2170 * The request queue allows us to note sequence numbers that have been emitted
2171 * and may be associated with active buffers to be retired.
2173 * By keeping this list, we can avoid having to do questionable sequence
2174 * number comparisons on buffer last_read|write_seqno. It also allows an
2175 * emission time to be associated with the request for tracking how far ahead
2176 * of the GPU the submission is.
2178 * The requests are reference counted, so upon creation they should have an
2179 * initial reference taken using kref_init
2181 struct drm_i915_gem_request {
2184 /** On Which ring this request was generated */
2185 struct drm_i915_private *i915;
2186 struct intel_engine_cs *ring;
2188 /** GEM sequence number associated with the previous request,
2189 * when the HWS breadcrumb is equal to this the GPU is processing
2194 /** GEM sequence number associated with this request,
2195 * when the HWS breadcrumb is equal or greater than this the GPU
2196 * has finished processing this request.
2200 /** Position in the ringbuffer of the start of the request */
2204 * Position in the ringbuffer of the start of the postfix.
2205 * This is required to calculate the maximum available ringbuffer
2206 * space without overwriting the postfix.
2210 /** Position in the ringbuffer of the end of the whole request */
2214 * Context and ring buffer related to this request
2215 * Contexts are refcounted, so when this request is associated with a
2216 * context, we must increment the context's refcount, to guarantee that
2217 * it persists while any request is linked to it. Requests themselves
2218 * are also refcounted, so the request will only be freed when the last
2219 * reference to it is dismissed, and the code in
2220 * i915_gem_request_free() will then decrement the refcount on the
2223 struct intel_context *ctx;
2224 struct intel_ringbuffer *ringbuf;
2226 /** Batch buffer related to this request if any (used for
2227 error state dump only) */
2228 struct drm_i915_gem_object *batch_obj;
2230 /** Time at which this request was emitted, in jiffies. */
2231 unsigned long emitted_jiffies;
2233 /** global list entry for this request */
2234 struct list_head list;
2236 struct drm_i915_file_private *file_priv;
2237 /** file_priv list entry for this request */
2238 struct list_head client_list;
2240 /** process identifier submitting this request */
2244 * The ELSP only accepts two elements at a time, so we queue
2245 * context/tail pairs on a given queue (ring->execlist_queue) until the
2246 * hardware is available. The queue serves a double purpose: we also use
2247 * it to keep track of the up to 2 contexts currently in the hardware
2248 * (usually one in execution and the other queued up by the GPU): We
2249 * only remove elements from the head of the queue when the hardware
2250 * informs us that an element has been completed.
2252 * All accesses to the queue are mediated by a spinlock
2253 * (ring->execlist_lock).
2256 /** Execlist link in the submission queue.*/
2257 struct list_head execlist_link;
2259 /** Execlists no. of times this request has been sent to the ELSP */
2264 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2265 struct intel_context *ctx,
2266 struct drm_i915_gem_request **req_out);
2267 void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2268 void i915_gem_request_free(struct kref *req_ref);
2269 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2270 struct drm_file *file);
2272 static inline uint32_t
2273 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2275 return req ? req->seqno : 0;
2278 static inline struct intel_engine_cs *
2279 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2281 return req ? req->ring : NULL;
2284 static inline struct drm_i915_gem_request *
2285 i915_gem_request_reference(struct drm_i915_gem_request *req)
2288 kref_get(&req->ref);
2293 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2295 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2296 kref_put(&req->ref, i915_gem_request_free);
2300 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2302 struct drm_device *dev;
2307 dev = req->ring->dev;
2308 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2309 mutex_unlock(&dev->struct_mutex);
2312 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2313 struct drm_i915_gem_request *src)
2316 i915_gem_request_reference(src);
2319 i915_gem_request_unreference(*pdst);
2325 * XXX: i915_gem_request_completed should be here but currently needs the
2326 * definition of i915_seqno_passed() which is below. It will be moved in
2327 * a later patch when the call to i915_seqno_passed() is obsoleted...
2331 * A command that requires special handling by the command parser.
2333 struct drm_i915_cmd_descriptor {
2335 * Flags describing how the command parser processes the command.
2337 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2338 * a length mask if not set
2339 * CMD_DESC_SKIP: The command is allowed but does not follow the
2340 * standard length encoding for the opcode range in
2342 * CMD_DESC_REJECT: The command is never allowed
2343 * CMD_DESC_REGISTER: The command should be checked against the
2344 * register whitelist for the appropriate ring
2345 * CMD_DESC_MASTER: The command is allowed if the submitting process
2349 #define CMD_DESC_FIXED (1<<0)
2350 #define CMD_DESC_SKIP (1<<1)
2351 #define CMD_DESC_REJECT (1<<2)
2352 #define CMD_DESC_REGISTER (1<<3)
2353 #define CMD_DESC_BITMASK (1<<4)
2354 #define CMD_DESC_MASTER (1<<5)
2357 * The command's unique identification bits and the bitmask to get them.
2358 * This isn't strictly the opcode field as defined in the spec and may
2359 * also include type, subtype, and/or subop fields.
2367 * The command's length. The command is either fixed length (i.e. does
2368 * not include a length field) or has a length field mask. The flag
2369 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2370 * a length mask. All command entries in a command table must include
2371 * length information.
2379 * Describes where to find a register address in the command to check
2380 * against the ring's register whitelist. Only valid if flags has the
2381 * CMD_DESC_REGISTER bit set.
2383 * A non-zero step value implies that the command may access multiple
2384 * registers in sequence (e.g. LRI), in that case step gives the
2385 * distance in dwords between individual offset fields.
2393 #define MAX_CMD_DESC_BITMASKS 3
2395 * Describes command checks where a particular dword is masked and
2396 * compared against an expected value. If the command does not match
2397 * the expected value, the parser rejects it. Only valid if flags has
2398 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2401 * If the check specifies a non-zero condition_mask then the parser
2402 * only performs the check when the bits specified by condition_mask
2409 u32 condition_offset;
2411 } bits[MAX_CMD_DESC_BITMASKS];
2415 * A table of commands requiring special handling by the command parser.
2417 * Each ring has an array of tables. Each table consists of an array of command
2418 * descriptors, which must be sorted with command opcodes in ascending order.
2420 struct drm_i915_cmd_table {
2421 const struct drm_i915_cmd_descriptor *table;
2425 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2426 #define __I915__(p) ({ \
2427 struct drm_i915_private *__p; \
2428 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2429 __p = (struct drm_i915_private *)p; \
2430 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2431 __p = to_i915((struct drm_device *)p); \
2436 #define INTEL_INFO(p) (&__I915__(p)->info)
2437 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2438 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2440 #define REVID_FOREVER 0xff
2442 * Return true if revision is in range [since,until] inclusive.
2444 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2446 #define IS_REVID(p, since, until) \
2447 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2449 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2450 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2451 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2452 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2453 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2454 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2455 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2456 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2457 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2458 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2459 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2460 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2461 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2462 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2463 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2464 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2465 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2466 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2467 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2468 INTEL_DEVID(dev) == 0x0152 || \
2469 INTEL_DEVID(dev) == 0x015a)
2470 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2471 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2472 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2473 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2474 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2475 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2476 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2477 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2478 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2479 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2480 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2481 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2482 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2483 (INTEL_DEVID(dev) & 0xf) == 0xe))
2484 /* ULX machines are also considered ULT. */
2485 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2486 (INTEL_DEVID(dev) & 0xf) == 0xe)
2487 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2488 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2489 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2490 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2491 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2492 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2493 /* ULX machines are also considered ULT. */
2494 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2495 INTEL_DEVID(dev) == 0x0A1E)
2496 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2497 INTEL_DEVID(dev) == 0x1913 || \
2498 INTEL_DEVID(dev) == 0x1916 || \
2499 INTEL_DEVID(dev) == 0x1921 || \
2500 INTEL_DEVID(dev) == 0x1926)
2501 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2502 INTEL_DEVID(dev) == 0x1915 || \
2503 INTEL_DEVID(dev) == 0x191E)
2504 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2505 INTEL_DEVID(dev) == 0x5913 || \
2506 INTEL_DEVID(dev) == 0x5916 || \
2507 INTEL_DEVID(dev) == 0x5921 || \
2508 INTEL_DEVID(dev) == 0x5926)
2509 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2510 INTEL_DEVID(dev) == 0x5915 || \
2511 INTEL_DEVID(dev) == 0x591E)
2512 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2513 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2514 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2515 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2517 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2519 #define SKL_REVID_A0 0x0
2520 #define SKL_REVID_B0 0x1
2521 #define SKL_REVID_C0 0x2
2522 #define SKL_REVID_D0 0x3
2523 #define SKL_REVID_E0 0x4
2524 #define SKL_REVID_F0 0x5
2526 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2528 #define BXT_REVID_A0 0x0
2529 #define BXT_REVID_A1 0x1
2530 #define BXT_REVID_B0 0x3
2531 #define BXT_REVID_C0 0x9
2533 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2536 * The genX designation typically refers to the render engine, so render
2537 * capability related checks should use IS_GEN, while display and other checks
2538 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2541 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2542 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2543 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2544 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2545 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2546 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2547 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2548 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2550 #define RENDER_RING (1<<RCS)
2551 #define BSD_RING (1<<VCS)
2552 #define BLT_RING (1<<BCS)
2553 #define VEBOX_RING (1<<VECS)
2554 #define BSD2_RING (1<<VCS2)
2555 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2556 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2557 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2558 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2559 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2560 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2561 __I915__(dev)->ellc_size)
2562 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2564 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2565 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2566 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2567 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2568 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2570 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2571 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2573 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2574 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2576 /* WaRsDisableCoarsePowerGating:skl,bxt */
2577 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2578 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
2579 IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
2581 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2582 * even when in MSI mode. This results in spurious interrupt warnings if the
2583 * legacy irq no. is shared with another device. The kernel then disables that
2584 * interrupt source and so prevents the other device from working properly.
2586 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2587 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2589 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2590 * rows, which changed the alignment requirements and fence programming.
2592 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2594 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2595 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2597 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2598 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2599 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2601 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2603 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2604 INTEL_INFO(dev)->gen >= 9)
2606 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2607 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2608 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2609 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2610 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2611 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2612 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2613 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2615 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2616 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2618 #define HAS_CSR(dev) (IS_GEN9(dev))
2620 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2621 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2623 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2624 INTEL_INFO(dev)->gen >= 8)
2626 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2627 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2630 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2631 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2632 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2633 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2634 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2635 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2636 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2637 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2638 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2639 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2641 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2642 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2643 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2644 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2645 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2646 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2647 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2648 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2649 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2651 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2652 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2654 /* DPF == dynamic parity feature */
2655 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2656 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2658 #define GT_FREQUENCY_MULTIPLIER 50
2659 #define GEN9_FREQ_SCALER 3
2661 #include "i915_trace.h"
2663 extern const struct drm_ioctl_desc i915_ioctls[];
2664 extern int i915_max_ioctl;
2666 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2667 extern int i915_resume_switcheroo(struct drm_device *dev);
2670 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2671 extern int i915_driver_unload(struct drm_device *);
2672 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2673 extern void i915_driver_lastclose(struct drm_device * dev);
2674 extern void i915_driver_preclose(struct drm_device *dev,
2675 struct drm_file *file);
2676 extern void i915_driver_postclose(struct drm_device *dev,
2677 struct drm_file *file);
2678 #ifdef CONFIG_COMPAT
2679 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2682 extern int intel_gpu_reset(struct drm_device *dev);
2683 extern bool intel_has_gpu_reset(struct drm_device *dev);
2684 extern int i915_reset(struct drm_device *dev);
2685 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2686 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2687 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2688 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2689 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2691 /* intel_hotplug.c */
2692 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2693 void intel_hpd_init(struct drm_i915_private *dev_priv);
2694 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2695 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2696 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2699 void i915_queue_hangcheck(struct drm_device *dev);
2701 void i915_handle_error(struct drm_device *dev, bool wedged,
2702 const char *fmt, ...);
2704 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2705 int intel_irq_install(struct drm_i915_private *dev_priv);
2706 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2708 extern void intel_uncore_sanitize(struct drm_device *dev);
2709 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2710 bool restore_forcewake);
2711 extern void intel_uncore_init(struct drm_device *dev);
2712 extern void intel_uncore_check_errors(struct drm_device *dev);
2713 extern void intel_uncore_fini(struct drm_device *dev);
2714 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2715 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2716 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2717 enum forcewake_domains domains);
2718 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2719 enum forcewake_domains domains);
2720 /* Like above but the caller must manage the uncore.lock itself.
2721 * Must be used with I915_READ_FW and friends.
2723 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2724 enum forcewake_domains domains);
2725 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2726 enum forcewake_domains domains);
2727 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2728 static inline bool intel_vgpu_active(struct drm_device *dev)
2730 return to_i915(dev)->vgpu.active;
2734 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2738 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2741 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2742 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2743 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2746 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2747 uint32_t interrupt_mask,
2748 uint32_t enabled_irq_mask);
2750 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2752 ilk_update_display_irq(dev_priv, bits, bits);
2755 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2757 ilk_update_display_irq(dev_priv, bits, 0);
2759 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2761 uint32_t interrupt_mask,
2762 uint32_t enabled_irq_mask);
2763 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2764 enum pipe pipe, uint32_t bits)
2766 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2768 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2769 enum pipe pipe, uint32_t bits)
2771 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2773 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2774 uint32_t interrupt_mask,
2775 uint32_t enabled_irq_mask);
2777 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2779 ibx_display_interrupt_update(dev_priv, bits, bits);
2782 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2784 ibx_display_interrupt_update(dev_priv, bits, 0);
2789 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2790 struct drm_file *file_priv);
2791 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2792 struct drm_file *file_priv);
2793 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2794 struct drm_file *file_priv);
2795 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2796 struct drm_file *file_priv);
2797 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2798 struct drm_file *file_priv);
2799 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2800 struct drm_file *file_priv);
2801 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2802 struct drm_file *file_priv);
2803 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2804 struct drm_i915_gem_request *req);
2805 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2806 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2807 struct drm_i915_gem_execbuffer2 *args,
2808 struct list_head *vmas);
2809 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2810 struct drm_file *file_priv);
2811 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2812 struct drm_file *file_priv);
2813 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2814 struct drm_file *file_priv);
2815 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2816 struct drm_file *file);
2817 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2818 struct drm_file *file);
2819 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2820 struct drm_file *file_priv);
2821 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2822 struct drm_file *file_priv);
2823 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2824 struct drm_file *file_priv);
2825 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2826 struct drm_file *file_priv);
2827 int i915_gem_init_userptr(struct drm_device *dev);
2828 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2829 struct drm_file *file);
2830 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2831 struct drm_file *file_priv);
2832 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2833 struct drm_file *file_priv);
2834 void i915_gem_load(struct drm_device *dev);
2835 void *i915_gem_object_alloc(struct drm_device *dev);
2836 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2837 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2838 const struct drm_i915_gem_object_ops *ops);
2839 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2841 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2842 struct drm_device *dev, const void *data, size_t size);
2843 void i915_gem_free_object(struct drm_gem_object *obj);
2844 void i915_gem_vma_destroy(struct i915_vma *vma);
2846 /* Flags used by pin/bind&friends. */
2847 #define PIN_MAPPABLE (1<<0)
2848 #define PIN_NONBLOCK (1<<1)
2849 #define PIN_GLOBAL (1<<2)
2850 #define PIN_OFFSET_BIAS (1<<3)
2851 #define PIN_USER (1<<4)
2852 #define PIN_UPDATE (1<<5)
2853 #define PIN_ZONE_4G (1<<6)
2854 #define PIN_HIGH (1<<7)
2855 #define PIN_OFFSET_FIXED (1<<8)
2856 #define PIN_OFFSET_MASK (~4095)
2858 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2859 struct i915_address_space *vm,
2863 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2864 const struct i915_ggtt_view *view,
2868 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2870 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2871 int __must_check i915_vma_unbind(struct i915_vma *vma);
2873 * BEWARE: Do not use the function below unless you can _absolutely_
2874 * _guarantee_ VMA in question is _not in use_ anywhere.
2876 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2877 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2878 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2879 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2881 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2882 int *needs_clflush);
2884 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2886 static inline int __sg_page_count(struct scatterlist *sg)
2888 return sg->length >> PAGE_SHIFT;
2892 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
2894 static inline struct page *
2895 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2897 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2900 if (n < obj->get_page.last) {
2901 obj->get_page.sg = obj->pages->sgl;
2902 obj->get_page.last = 0;
2905 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2906 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2907 if (unlikely(sg_is_chain(obj->get_page.sg)))
2908 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2911 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2914 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2916 BUG_ON(obj->pages == NULL);
2917 obj->pages_pin_count++;
2919 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2921 BUG_ON(obj->pages_pin_count == 0);
2922 obj->pages_pin_count--;
2925 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2926 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2927 struct intel_engine_cs *to,
2928 struct drm_i915_gem_request **to_req);
2929 void i915_vma_move_to_active(struct i915_vma *vma,
2930 struct drm_i915_gem_request *req);
2931 int i915_gem_dumb_create(struct drm_file *file_priv,
2932 struct drm_device *dev,
2933 struct drm_mode_create_dumb *args);
2934 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2935 uint32_t handle, uint64_t *offset);
2937 * Returns true if seq1 is later than seq2.
2940 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2942 return (int32_t)(seq1 - seq2) >= 0;
2945 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
2946 bool lazy_coherency)
2948 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2949 return i915_seqno_passed(seqno, req->previous_seqno);
2952 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2953 bool lazy_coherency)
2955 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2956 return i915_seqno_passed(seqno, req->seqno);
2959 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2960 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2962 struct drm_i915_gem_request *
2963 i915_gem_find_active_request(struct intel_engine_cs *ring);
2965 bool i915_gem_retire_requests(struct drm_device *dev);
2966 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2967 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2968 bool interruptible);
2970 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2972 return unlikely(atomic_read(&error->reset_counter)
2973 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2976 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2978 return atomic_read(&error->reset_counter) & I915_WEDGED;
2981 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2983 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2986 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2988 return dev_priv->gpu_error.stop_rings == 0 ||
2989 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2992 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2994 return dev_priv->gpu_error.stop_rings == 0 ||
2995 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2998 void i915_gem_reset(struct drm_device *dev);
2999 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3000 int __must_check i915_gem_init(struct drm_device *dev);
3001 int i915_gem_init_rings(struct drm_device *dev);
3002 int __must_check i915_gem_init_hw(struct drm_device *dev);
3003 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3004 void i915_gem_init_swizzling(struct drm_device *dev);
3005 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
3006 int __must_check i915_gpu_idle(struct drm_device *dev);
3007 int __must_check i915_gem_suspend(struct drm_device *dev);
3008 void __i915_add_request(struct drm_i915_gem_request *req,
3009 struct drm_i915_gem_object *batch_obj,
3011 #define i915_add_request(req) \
3012 __i915_add_request(req, NULL, true)
3013 #define i915_add_request_no_flush(req) \
3014 __i915_add_request(req, NULL, false)
3015 int __i915_wait_request(struct drm_i915_gem_request *req,
3016 unsigned reset_counter,
3019 struct intel_rps_client *rps);
3020 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3021 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3023 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3026 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3029 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3031 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3033 const struct i915_ggtt_view *view);
3034 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3035 const struct i915_ggtt_view *view);
3036 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3038 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3039 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3042 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3044 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3045 int tiling_mode, bool fenced);
3047 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3048 enum i915_cache_level cache_level);
3050 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3051 struct dma_buf *dma_buf);
3053 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3054 struct drm_gem_object *gem_obj, int flags);
3056 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3057 const struct i915_ggtt_view *view);
3058 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3059 struct i915_address_space *vm);
3061 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3063 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3066 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3067 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3068 const struct i915_ggtt_view *view);
3069 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3070 struct i915_address_space *vm);
3072 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3073 struct i915_address_space *vm);
3075 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3076 struct i915_address_space *vm);
3078 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3079 const struct i915_ggtt_view *view);
3082 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3083 struct i915_address_space *vm);
3085 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3086 const struct i915_ggtt_view *view);
3088 static inline struct i915_vma *
3089 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3091 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3093 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3095 /* Some GGTT VM helpers */
3096 #define i915_obj_to_ggtt(obj) \
3097 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3098 static inline bool i915_is_ggtt(struct i915_address_space *vm)
3100 struct i915_address_space *ggtt =
3101 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
3105 static inline struct i915_hw_ppgtt *
3106 i915_vm_to_ppgtt(struct i915_address_space *vm)
3108 WARN_ON(i915_is_ggtt(vm));
3110 return container_of(vm, struct i915_hw_ppgtt, base);
3114 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3116 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3119 static inline unsigned long
3120 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3122 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3125 static inline int __must_check
3126 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3130 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3131 alignment, flags | PIN_GLOBAL);
3135 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3137 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3140 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3141 const struct i915_ggtt_view *view);
3143 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3145 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3148 /* i915_gem_fence.c */
3149 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3150 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3152 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3153 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3155 void i915_gem_restore_fences(struct drm_device *dev);
3157 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3158 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3159 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3161 /* i915_gem_context.c */
3162 int __must_check i915_gem_context_init(struct drm_device *dev);
3163 void i915_gem_context_fini(struct drm_device *dev);
3164 void i915_gem_context_reset(struct drm_device *dev);
3165 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3166 int i915_gem_context_enable(struct drm_i915_gem_request *req);
3167 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3168 int i915_switch_context(struct drm_i915_gem_request *req);
3169 struct intel_context *
3170 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3171 void i915_gem_context_free(struct kref *ctx_ref);
3172 struct drm_i915_gem_object *
3173 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3174 static inline void i915_gem_context_reference(struct intel_context *ctx)
3176 kref_get(&ctx->ref);
3179 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3181 kref_put(&ctx->ref, i915_gem_context_free);
3184 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3186 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3189 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3190 struct drm_file *file);
3191 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3192 struct drm_file *file);
3193 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3194 struct drm_file *file_priv);
3195 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3196 struct drm_file *file_priv);
3198 /* i915_gem_evict.c */
3199 int __must_check i915_gem_evict_something(struct drm_device *dev,
3200 struct i915_address_space *vm,
3203 unsigned cache_level,
3204 unsigned long start,
3207 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3208 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3210 /* belongs in i915_gem_gtt.h */
3211 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3213 if (INTEL_INFO(dev)->gen < 6)
3214 intel_gtt_chipset_flush();
3217 /* i915_gem_stolen.c */
3218 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3219 struct drm_mm_node *node, u64 size,
3220 unsigned alignment);
3221 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3222 struct drm_mm_node *node, u64 size,
3223 unsigned alignment, u64 start,
3225 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3226 struct drm_mm_node *node);
3227 int i915_gem_init_stolen(struct drm_device *dev);
3228 void i915_gem_cleanup_stolen(struct drm_device *dev);
3229 struct drm_i915_gem_object *
3230 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3231 struct drm_i915_gem_object *
3232 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3237 /* i915_gem_shrinker.c */
3238 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3239 unsigned long target,
3241 #define I915_SHRINK_PURGEABLE 0x1
3242 #define I915_SHRINK_UNBOUND 0x2
3243 #define I915_SHRINK_BOUND 0x4
3244 #define I915_SHRINK_ACTIVE 0x8
3245 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3246 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3249 /* i915_gem_tiling.c */
3250 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3252 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3254 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3255 obj->tiling_mode != I915_TILING_NONE;
3258 /* i915_gem_debug.c */
3260 int i915_verify_lists(struct drm_device *dev);
3262 #define i915_verify_lists(dev) 0
3265 /* i915_debugfs.c */
3266 int i915_debugfs_init(struct drm_minor *minor);
3267 void i915_debugfs_cleanup(struct drm_minor *minor);
3268 #ifdef CONFIG_DEBUG_FS
3269 int i915_debugfs_connector_add(struct drm_connector *connector);
3270 void intel_display_crc_init(struct drm_device *dev);
3272 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3274 static inline void intel_display_crc_init(struct drm_device *dev) {}
3277 /* i915_gpu_error.c */
3279 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3280 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3281 const struct i915_error_state_file_priv *error);
3282 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3283 struct drm_i915_private *i915,
3284 size_t count, loff_t pos);
3285 static inline void i915_error_state_buf_release(
3286 struct drm_i915_error_state_buf *eb)
3290 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3291 const char *error_msg);
3292 void i915_error_state_get(struct drm_device *dev,
3293 struct i915_error_state_file_priv *error_priv);
3294 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3295 void i915_destroy_error_state(struct drm_device *dev);
3297 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3298 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3300 /* i915_cmd_parser.c */
3301 int i915_cmd_parser_get_version(void);
3302 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3303 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3304 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3305 int i915_parse_cmds(struct intel_engine_cs *ring,
3306 struct drm_i915_gem_object *batch_obj,
3307 struct drm_i915_gem_object *shadow_batch_obj,
3308 u32 batch_start_offset,
3312 /* i915_suspend.c */
3313 extern int i915_save_state(struct drm_device *dev);
3314 extern int i915_restore_state(struct drm_device *dev);
3317 void i915_setup_sysfs(struct drm_device *dev_priv);
3318 void i915_teardown_sysfs(struct drm_device *dev_priv);
3321 extern int intel_setup_gmbus(struct drm_device *dev);
3322 extern void intel_teardown_gmbus(struct drm_device *dev);
3323 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3326 extern struct i2c_adapter *
3327 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3328 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3329 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3330 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3332 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3334 extern void intel_i2c_reset(struct drm_device *dev);
3337 int intel_bios_init(struct drm_i915_private *dev_priv);
3338 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3340 /* intel_opregion.c */
3342 extern int intel_opregion_setup(struct drm_device *dev);
3343 extern void intel_opregion_init(struct drm_device *dev);
3344 extern void intel_opregion_fini(struct drm_device *dev);
3345 extern void intel_opregion_asle_intr(struct drm_device *dev);
3346 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3348 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3351 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3352 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3353 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3354 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3356 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3361 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3369 extern void intel_register_dsm_handler(void);
3370 extern void intel_unregister_dsm_handler(void);
3372 static inline void intel_register_dsm_handler(void) { return; }
3373 static inline void intel_unregister_dsm_handler(void) { return; }
3374 #endif /* CONFIG_ACPI */
3377 extern void intel_modeset_init_hw(struct drm_device *dev);
3378 extern void intel_modeset_init(struct drm_device *dev);
3379 extern void intel_modeset_gem_init(struct drm_device *dev);
3380 extern void intel_modeset_cleanup(struct drm_device *dev);
3381 extern void intel_connector_unregister(struct intel_connector *);
3382 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3383 extern void intel_display_resume(struct drm_device *dev);
3384 extern void i915_redisable_vga(struct drm_device *dev);
3385 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3386 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3387 extern void intel_init_pch_refclk(struct drm_device *dev);
3388 extern void intel_set_rps(struct drm_device *dev, u8 val);
3389 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3391 extern void intel_detect_pch(struct drm_device *dev);
3392 extern int intel_enable_rc6(const struct drm_device *dev);
3394 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3395 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3396 struct drm_file *file);
3397 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3398 struct drm_file *file);
3401 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3402 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3403 struct intel_overlay_error_state *error);
3405 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3406 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3407 struct drm_device *dev,
3408 struct intel_display_error_state *error);
3410 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3411 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3413 /* intel_sideband.c */
3414 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3415 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3416 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3417 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3418 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3419 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3420 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3421 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3422 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3423 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3424 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3425 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3426 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3427 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3428 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3429 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3430 enum intel_sbi_destination destination);
3431 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3432 enum intel_sbi_destination destination);
3433 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3434 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3436 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3437 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3439 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3440 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3442 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3443 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3444 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3445 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3447 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3448 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3449 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3450 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3452 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3453 * will be implemented using 2 32-bit writes in an arbitrary order with
3454 * an arbitrary delay between them. This can cause the hardware to
3455 * act upon the intermediate value, possibly leading to corruption and
3456 * machine death. You have been warned.
3458 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3459 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3461 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3462 u32 upper, lower, old_upper, loop = 0; \
3463 upper = I915_READ(upper_reg); \
3465 old_upper = upper; \
3466 lower = I915_READ(lower_reg); \
3467 upper = I915_READ(upper_reg); \
3468 } while (upper != old_upper && loop++ < 2); \
3469 (u64)upper << 32 | lower; })
3471 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3472 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3474 #define __raw_read(x, s) \
3475 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3478 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3481 #define __raw_write(x, s) \
3482 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3483 i915_reg_t reg, uint##x##_t val) \
3485 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3500 /* These are untraced mmio-accessors that are only valid to be used inside
3501 * criticial sections inside IRQ handlers where forcewake is explicitly
3503 * Think twice, and think again, before using these.
3504 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3505 * intel_uncore_forcewake_irqunlock().
3507 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3508 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3509 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3511 /* "Broadcast RGB" property */
3512 #define INTEL_BROADCAST_RGB_AUTO 0
3513 #define INTEL_BROADCAST_RGB_FULL 1
3514 #define INTEL_BROADCAST_RGB_LIMITED 2
3516 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3518 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3519 return VLV_VGACNTRL;
3520 else if (INTEL_INFO(dev)->gen >= 5)
3521 return CPU_VGACNTRL;
3526 static inline void __user *to_user_ptr(u64 address)
3528 return (void __user *)(uintptr_t)address;
3531 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3533 unsigned long j = msecs_to_jiffies(m);
3535 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3538 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3540 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3543 static inline unsigned long
3544 timespec_to_jiffies_timeout(const struct timespec *value)
3546 unsigned long j = timespec_to_jiffies(value);
3548 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3552 * If you need to wait X milliseconds between events A and B, but event B
3553 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3554 * when event A happened, then just before event B you call this function and
3555 * pass the timestamp as the first argument, and X as the second argument.
3558 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3560 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3563 * Don't re-read the value of "jiffies" every time since it may change
3564 * behind our back and break the math.
3566 tmp_jiffies = jiffies;
3567 target_jiffies = timestamp_jiffies +
3568 msecs_to_jiffies_timeout(to_wait_ms);
3570 if (time_after(target_jiffies, tmp_jiffies)) {
3571 remaining_jiffies = target_jiffies - tmp_jiffies;
3572 while (remaining_jiffies)
3574 schedule_timeout_uninterruptible(remaining_jiffies);
3578 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3579 struct drm_i915_gem_request *req)
3581 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3582 i915_gem_request_assign(&ring->trace_irq_req, req);