1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "i915_params.h"
39 #include "intel_bios.h"
40 #include "intel_ringbuffer.h"
41 #include "intel_lrc.h"
42 #include "i915_gem_gtt.h"
43 #include "i915_gem_render_state.h"
44 #include <linux/io-mapping.h>
45 #include <linux/i2c.h>
46 #include <linux/i2c-algo-bit.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <linux/backlight.h>
51 #include <linux/hashtable.h>
52 #include <linux/intel-iommu.h>
53 #include <linux/kref.h>
54 #include <linux/pm_qos.h>
55 #include "intel_guc.h"
57 /* General customization:
60 #define DRIVER_NAME "i915"
61 #define DRIVER_DESC "Intel Graphics"
62 #define DRIVER_DATE "20160124"
65 /* Many gcc seem to no see through this and fall over :( */
67 #define WARN_ON(x) ({ \
68 bool __i915_warn_cond = (x); \
69 if (__builtin_constant_p(__i915_warn_cond)) \
70 BUILD_BUG_ON(__i915_warn_cond); \
71 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
73 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
77 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
79 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
80 (long) (x), __func__);
82 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
83 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
84 * which may not necessarily be a user visible problem. This will either
85 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
86 * enable distros and users to tailor their preferred amount of i915 abrt
89 #define I915_STATE_WARN(condition, format...) ({ \
90 int __ret_warn_on = !!(condition); \
91 if (unlikely(__ret_warn_on)) \
92 if (!WARN(i915.verbose_state_checks, format)) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(x) \
98 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
100 static inline const char *yesno(bool v)
102 return v ? "yes" : "no";
105 static inline const char *onoff(bool v)
107 return v ? "on" : "off";
116 I915_MAX_PIPES = _PIPE_EDP
118 #define pipe_name(p) ((p) + 'A')
127 #define transcoder_name(t) ((t) + 'A')
130 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
131 * number of planes per CRTC. Not all platforms really have this many planes,
132 * which means some arrays of size I915_MAX_PLANES may have unused entries
133 * between the topmost sprite plane and the cursor plane.
142 #define plane_name(p) ((p) + 'A')
144 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
154 #define port_name(p) ((p) + 'A')
156 #define I915_NUM_PHYS_VLV 2
168 enum intel_display_power_domain {
172 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
173 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
174 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
175 POWER_DOMAIN_TRANSCODER_A,
176 POWER_DOMAIN_TRANSCODER_B,
177 POWER_DOMAIN_TRANSCODER_C,
178 POWER_DOMAIN_TRANSCODER_EDP,
179 POWER_DOMAIN_PORT_DDI_A_LANES,
180 POWER_DOMAIN_PORT_DDI_B_LANES,
181 POWER_DOMAIN_PORT_DDI_C_LANES,
182 POWER_DOMAIN_PORT_DDI_D_LANES,
183 POWER_DOMAIN_PORT_DDI_E_LANES,
184 POWER_DOMAIN_PORT_DSI,
185 POWER_DOMAIN_PORT_CRT,
186 POWER_DOMAIN_PORT_OTHER,
195 POWER_DOMAIN_MODESET,
201 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
202 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
203 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
204 #define POWER_DOMAIN_TRANSCODER(tran) \
205 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
206 (tran) + POWER_DOMAIN_TRANSCODER_A)
210 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
222 #define for_each_hpd_pin(__pin) \
223 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
225 struct i915_hotplug {
226 struct work_struct hotplug_work;
229 unsigned long last_jiffies;
234 HPD_MARK_DISABLED = 2
236 } stats[HPD_NUM_PINS];
238 struct delayed_work reenable_work;
240 struct intel_digital_port *irq_port[I915_MAX_PORTS];
243 struct work_struct dig_port_work;
246 * if we get a HPD irq from DP and a HPD irq from non-DP
247 * the non-DP HPD could block the workqueue on a mode config
248 * mutex getting, that userspace may have taken. However
249 * userspace is waiting on the DP workqueue to run which is
250 * blocked behind the non-DP one.
252 struct workqueue_struct *dp_wq;
255 #define I915_GEM_GPU_DOMAINS \
256 (I915_GEM_DOMAIN_RENDER | \
257 I915_GEM_DOMAIN_SAMPLER | \
258 I915_GEM_DOMAIN_COMMAND | \
259 I915_GEM_DOMAIN_INSTRUCTION | \
260 I915_GEM_DOMAIN_VERTEX)
262 #define for_each_pipe(__dev_priv, __p) \
263 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
264 #define for_each_plane(__dev_priv, __pipe, __p) \
266 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
268 #define for_each_sprite(__dev_priv, __p, __s) \
270 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
273 #define for_each_crtc(dev, crtc) \
274 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
276 #define for_each_intel_plane(dev, intel_plane) \
277 list_for_each_entry(intel_plane, \
278 &dev->mode_config.plane_list, \
281 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
282 list_for_each_entry(intel_plane, \
283 &(dev)->mode_config.plane_list, \
285 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
287 #define for_each_intel_crtc(dev, intel_crtc) \
288 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
290 #define for_each_intel_encoder(dev, intel_encoder) \
291 list_for_each_entry(intel_encoder, \
292 &(dev)->mode_config.encoder_list, \
295 #define for_each_intel_connector(dev, intel_connector) \
296 list_for_each_entry(intel_connector, \
297 &dev->mode_config.connector_list, \
300 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
301 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
302 for_each_if ((intel_encoder)->base.crtc == (__crtc))
304 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
305 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
306 for_each_if ((intel_connector)->base.encoder == (__encoder))
308 #define for_each_power_domain(domain, mask) \
309 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
310 for_each_if ((1 << (domain)) & (mask))
312 struct drm_i915_private;
313 struct i915_mm_struct;
314 struct i915_mmu_object;
316 struct drm_i915_file_private {
317 struct drm_i915_private *dev_priv;
318 struct drm_file *file;
322 struct list_head request_list;
323 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
324 * chosen to prevent the CPU getting more than a frame ahead of the GPU
325 * (when using lax throttling for the frontbuffer). We also use it to
326 * offer free GPU waitboosts for severely congested workloads.
328 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
330 struct idr context_idr;
332 struct intel_rps_client {
333 struct list_head link;
337 unsigned int bsd_ring;
341 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
342 /* real shared dpll ids must be >= 0 */
343 DPLL_ID_PCH_PLL_A = 0,
344 DPLL_ID_PCH_PLL_B = 1,
351 DPLL_ID_SKL_DPLL1 = 0,
352 DPLL_ID_SKL_DPLL2 = 1,
353 DPLL_ID_SKL_DPLL3 = 2,
355 #define I915_NUM_PLLS 3
357 struct intel_dpll_hw_state {
370 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
371 * lower part of ctrl1 and they get shifted into position when writing
372 * the register. This allows us to easily compare the state to share
376 /* HDMI only, 0 when used for DP */
377 uint32_t cfgcr1, cfgcr2;
380 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
384 struct intel_shared_dpll_config {
385 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
386 struct intel_dpll_hw_state hw_state;
389 struct intel_shared_dpll {
390 struct intel_shared_dpll_config config;
392 int active; /* count of number of active CRTCs (i.e. DPMS on) */
393 bool on; /* is the PLL actually active? Disabled during modeset */
395 /* should match the index in the dev_priv->shared_dplls array */
396 enum intel_dpll_id id;
397 /* The mode_set hook is optional and should be used together with the
398 * intel_prepare_shared_dpll function. */
399 void (*mode_set)(struct drm_i915_private *dev_priv,
400 struct intel_shared_dpll *pll);
401 void (*enable)(struct drm_i915_private *dev_priv,
402 struct intel_shared_dpll *pll);
403 void (*disable)(struct drm_i915_private *dev_priv,
404 struct intel_shared_dpll *pll);
405 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
406 struct intel_shared_dpll *pll,
407 struct intel_dpll_hw_state *hw_state);
415 /* Used by dp and fdi links */
416 struct intel_link_m_n {
424 void intel_link_compute_m_n(int bpp, int nlanes,
425 int pixel_clock, int link_clock,
426 struct intel_link_m_n *m_n);
428 /* Interface history:
431 * 1.2: Add Power Management
432 * 1.3: Add vblank support
433 * 1.4: Fix cmdbuffer path, add heap destroy
434 * 1.5: Add vblank pipe configuration
435 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
436 * - Support vertical blank on secondary display pipe
438 #define DRIVER_MAJOR 1
439 #define DRIVER_MINOR 6
440 #define DRIVER_PATCHLEVEL 0
442 #define WATCH_LISTS 0
444 struct opregion_header;
445 struct opregion_acpi;
446 struct opregion_swsci;
447 struct opregion_asle;
449 struct intel_opregion {
450 struct opregion_header *header;
451 struct opregion_acpi *acpi;
452 struct opregion_swsci *swsci;
453 u32 swsci_gbda_sub_functions;
454 u32 swsci_sbcb_sub_functions;
455 struct opregion_asle *asle;
460 struct work_struct asle_work;
462 #define OPREGION_SIZE (8*1024)
464 struct intel_overlay;
465 struct intel_overlay_error_state;
467 #define I915_FENCE_REG_NONE -1
468 #define I915_MAX_NUM_FENCES 32
469 /* 32 fences + sign bit for FENCE_REG_NONE */
470 #define I915_MAX_NUM_FENCE_BITS 6
472 struct drm_i915_fence_reg {
473 struct list_head lru_list;
474 struct drm_i915_gem_object *obj;
478 struct sdvo_device_mapping {
487 struct intel_display_error_state;
489 struct drm_i915_error_state {
498 /* Generic register state */
506 u32 error; /* gen6+ */
507 u32 err_int; /* gen7 */
508 u32 fault_data0; /* gen8, gen9 */
509 u32 fault_data1; /* gen8, gen9 */
515 u32 extra_instdone[I915_NUM_INSTDONE_REG];
516 u64 fence[I915_MAX_NUM_FENCES];
517 struct intel_overlay_error_state *overlay;
518 struct intel_display_error_state *display;
519 struct drm_i915_error_object *semaphore_obj;
521 struct drm_i915_error_ring {
523 /* Software tracked state */
526 enum intel_ring_hangcheck_action hangcheck_action;
529 /* our own tracking of ring head and tail */
533 u32 semaphore_seqno[I915_NUM_RINGS - 1];
552 u32 rc_psmi; /* sleep state */
553 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
555 struct drm_i915_error_object {
559 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
561 struct drm_i915_error_request {
576 char comm[TASK_COMM_LEN];
577 } ring[I915_NUM_RINGS];
579 struct drm_i915_error_buffer {
582 u32 rseqno[I915_NUM_RINGS], wseqno;
586 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
594 } **active_bo, **pinned_bo;
596 u32 *active_bo_count, *pinned_bo_count;
600 struct intel_connector;
601 struct intel_encoder;
602 struct intel_crtc_state;
603 struct intel_initial_plane_config;
608 struct drm_i915_display_funcs {
609 int (*get_display_clock_speed)(struct drm_device *dev);
610 int (*get_fifo_size)(struct drm_device *dev, int plane);
612 * find_dpll() - Find the best values for the PLL
613 * @limit: limits for the PLL
614 * @crtc: current CRTC
615 * @target: target frequency in kHz
616 * @refclk: reference clock frequency in kHz
617 * @match_clock: if provided, @best_clock P divider must
618 * match the P divider from @match_clock
619 * used for LVDS downclocking
620 * @best_clock: best PLL values found
622 * Returns true on success, false on failure.
624 bool (*find_dpll)(const struct intel_limit *limit,
625 struct intel_crtc_state *crtc_state,
626 int target, int refclk,
627 struct dpll *match_clock,
628 struct dpll *best_clock);
629 int (*compute_pipe_wm)(struct intel_crtc *crtc,
630 struct drm_atomic_state *state);
631 void (*program_watermarks)(struct intel_crtc_state *cstate);
632 void (*update_wm)(struct drm_crtc *crtc);
633 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
634 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
635 /* Returns the active state of the crtc, and if the crtc is active,
636 * fills out the pipe-config with the hw state. */
637 bool (*get_pipe_config)(struct intel_crtc *,
638 struct intel_crtc_state *);
639 void (*get_initial_plane_config)(struct intel_crtc *,
640 struct intel_initial_plane_config *);
641 int (*crtc_compute_clock)(struct intel_crtc *crtc,
642 struct intel_crtc_state *crtc_state);
643 void (*crtc_enable)(struct drm_crtc *crtc);
644 void (*crtc_disable)(struct drm_crtc *crtc);
645 void (*audio_codec_enable)(struct drm_connector *connector,
646 struct intel_encoder *encoder,
647 const struct drm_display_mode *adjusted_mode);
648 void (*audio_codec_disable)(struct intel_encoder *encoder);
649 void (*fdi_link_train)(struct drm_crtc *crtc);
650 void (*init_clock_gating)(struct drm_device *dev);
651 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
652 struct drm_framebuffer *fb,
653 struct drm_i915_gem_object *obj,
654 struct drm_i915_gem_request *req,
656 void (*hpd_irq_setup)(struct drm_device *dev);
657 /* clock updates for mode set */
659 /* render clock increase/decrease */
660 /* display clock increase/decrease */
661 /* pll clock increase/decrease */
664 enum forcewake_domain_id {
665 FW_DOMAIN_ID_RENDER = 0,
666 FW_DOMAIN_ID_BLITTER,
672 enum forcewake_domains {
673 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
674 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
675 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
676 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
681 struct intel_uncore_funcs {
682 void (*force_wake_get)(struct drm_i915_private *dev_priv,
683 enum forcewake_domains domains);
684 void (*force_wake_put)(struct drm_i915_private *dev_priv,
685 enum forcewake_domains domains);
687 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
688 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
689 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
690 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
692 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
693 uint8_t val, bool trace);
694 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
695 uint16_t val, bool trace);
696 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
697 uint32_t val, bool trace);
698 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
699 uint64_t val, bool trace);
702 struct intel_uncore {
703 spinlock_t lock; /** lock is also taken in irq contexts. */
705 struct intel_uncore_funcs funcs;
708 enum forcewake_domains fw_domains;
710 struct intel_uncore_forcewake_domain {
711 struct drm_i915_private *i915;
712 enum forcewake_domain_id id;
714 struct timer_list timer;
721 } fw_domain[FW_DOMAIN_ID_COUNT];
723 int unclaimed_mmio_check;
726 /* Iterate over initialised fw domains */
727 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
728 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
729 (i__) < FW_DOMAIN_ID_COUNT; \
730 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
731 for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
733 #define for_each_fw_domain(domain__, dev_priv__, i__) \
734 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
736 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
737 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
738 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
741 struct work_struct work;
743 uint32_t *dmc_payload;
744 uint32_t dmc_fw_size;
747 i915_reg_t mmioaddr[8];
748 uint32_t mmiodata[8];
751 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
752 func(is_mobile) sep \
755 func(is_i945gm) sep \
757 func(need_gfx_hws) sep \
759 func(is_pineview) sep \
760 func(is_broadwater) sep \
761 func(is_crestline) sep \
762 func(is_ivybridge) sep \
763 func(is_valleyview) sep \
764 func(is_cherryview) sep \
765 func(is_haswell) sep \
766 func(is_skylake) sep \
767 func(is_broxton) sep \
768 func(is_kabylake) sep \
769 func(is_preliminary) sep \
771 func(has_pipe_cxsr) sep \
772 func(has_hotplug) sep \
773 func(cursor_needs_physical) sep \
774 func(has_overlay) sep \
775 func(overlay_needs_physical) sep \
776 func(supports_tv) sep \
781 #define DEFINE_FLAG(name) u8 name:1
782 #define SEP_SEMICOLON ;
784 struct intel_device_info {
785 u32 display_mmio_offset;
788 u8 num_sprites[I915_MAX_PIPES];
790 u8 ring_mask; /* Rings supported by the HW */
791 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
792 /* Register offsets for the various display pipes and transcoders */
793 int pipe_offsets[I915_MAX_TRANSCODERS];
794 int trans_offsets[I915_MAX_TRANSCODERS];
795 int palette_offsets[I915_MAX_PIPES];
796 int cursor_offsets[I915_MAX_PIPES];
798 /* Slice/subslice/EU info */
801 u8 subslice_per_slice;
804 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
807 u8 has_subslice_pg:1;
814 enum i915_cache_level {
816 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
817 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
818 caches, eg sampler/render caches, and the
819 large Last-Level-Cache. LLC is coherent with
820 the CPU, but L3 is only visible to the GPU. */
821 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
824 struct i915_ctx_hang_stats {
825 /* This context had batch pending when hang was declared */
826 unsigned batch_pending;
828 /* This context had batch active when hang was declared */
829 unsigned batch_active;
831 /* Time when this context was last blamed for a GPU reset */
832 unsigned long guilty_ts;
834 /* If the contexts causes a second GPU hang within this time,
835 * it is permanently banned from submitting any more work.
837 unsigned long ban_period_seconds;
839 /* This context is banned to submit more work */
843 /* This must match up with the value previously used for execbuf2.rsvd1. */
844 #define DEFAULT_CONTEXT_HANDLE 0
846 #define CONTEXT_NO_ZEROMAP (1<<0)
848 * struct intel_context - as the name implies, represents a context.
849 * @ref: reference count.
850 * @user_handle: userspace tracking identity for this context.
851 * @remap_slice: l3 row remapping information.
852 * @flags: context specific flags:
853 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
854 * @file_priv: filp associated with this context (NULL for global default
856 * @hang_stats: information about the role of this context in possible GPU
858 * @ppgtt: virtual memory space used by this context.
859 * @legacy_hw_ctx: render context backing object and whether it is correctly
860 * initialized (legacy ring submission mechanism only).
861 * @link: link in the global list of contexts.
863 * Contexts are memory images used by the hardware to store copies of their
866 struct intel_context {
870 struct drm_i915_private *i915;
872 struct drm_i915_file_private *file_priv;
873 struct i915_ctx_hang_stats hang_stats;
874 struct i915_hw_ppgtt *ppgtt;
876 /* Legacy ring buffer submission */
878 struct drm_i915_gem_object *rcs_state;
884 struct drm_i915_gem_object *state;
885 struct intel_ringbuffer *ringbuf;
887 struct i915_vma *lrc_vma;
889 uint32_t *lrc_reg_state;
890 } engine[I915_NUM_RINGS];
892 struct list_head link;
904 /* This is always the inner lock when overlapping with struct_mutex and
905 * it's the outer lock when overlapping with stolen_lock. */
908 unsigned int possible_framebuffer_bits;
909 unsigned int busy_bits;
910 unsigned int visible_pipes_mask;
911 struct intel_crtc *crtc;
913 struct drm_mm_node compressed_fb;
914 struct drm_mm_node *compressed_llb;
921 struct intel_fbc_state_cache {
923 unsigned int mode_flags;
924 uint32_t hsw_bdw_pixel_rate;
928 unsigned int rotation;
936 uint32_t pixel_format;
939 unsigned int tiling_mode;
943 struct intel_fbc_reg_params {
947 unsigned int fence_y_offset;
952 uint32_t pixel_format;
960 struct intel_fbc_work {
962 u32 scheduled_vblank;
963 struct work_struct work;
966 const char *no_fbc_reason;
970 * HIGH_RR is the highest eDP panel refresh rate read from EDID
971 * LOW_RR is the lowest eDP panel refresh rate found from EDID
972 * parsing for same resolution.
974 enum drrs_refresh_rate_type {
977 DRRS_MAX_RR, /* RR count */
980 enum drrs_support_type {
981 DRRS_NOT_SUPPORTED = 0,
982 STATIC_DRRS_SUPPORT = 1,
983 SEAMLESS_DRRS_SUPPORT = 2
989 struct delayed_work work;
991 unsigned busy_frontbuffer_bits;
992 enum drrs_refresh_rate_type refresh_rate_type;
993 enum drrs_support_type type;
1000 struct intel_dp *enabled;
1002 struct delayed_work work;
1003 unsigned busy_frontbuffer_bits;
1005 bool aux_frame_sync;
1010 PCH_NONE = 0, /* No PCH present */
1011 PCH_IBX, /* Ibexpeak PCH */
1012 PCH_CPT, /* Cougarpoint PCH */
1013 PCH_LPT, /* Lynxpoint PCH */
1014 PCH_SPT, /* Sunrisepoint PCH */
1018 enum intel_sbi_destination {
1023 #define QUIRK_PIPEA_FORCE (1<<0)
1024 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1025 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1026 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1027 #define QUIRK_PIPEB_FORCE (1<<4)
1028 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1031 struct intel_fbc_work;
1033 struct intel_gmbus {
1034 struct i2c_adapter adapter;
1037 i915_reg_t gpio_reg;
1038 struct i2c_algo_bit_data bit_algo;
1039 struct drm_i915_private *dev_priv;
1042 struct i915_suspend_saved_registers {
1045 u32 savePP_ON_DELAYS;
1046 u32 savePP_OFF_DELAYS;
1051 u32 saveFBC_CONTROL;
1052 u32 saveCACHE_MODE_0;
1053 u32 saveMI_ARB_STATE;
1057 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1058 u32 savePCH_PORT_HOTPLUG;
1062 struct vlv_s0ix_state {
1069 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1070 u32 media_max_req_count;
1071 u32 gfx_max_req_count;
1097 u32 rp_down_timeout;
1103 /* Display 1 CZ domain */
1108 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1110 /* GT SA CZ domain */
1117 /* Display 2 CZ domain */
1121 u32 clock_gate_dis2;
1124 struct intel_rps_ei {
1130 struct intel_gen6_power_mgmt {
1132 * work, interrupts_enabled and pm_iir are protected by
1133 * dev_priv->irq_lock
1135 struct work_struct work;
1136 bool interrupts_enabled;
1139 /* Frequencies are stored in potentially platform dependent multiples.
1140 * In other words, *_freq needs to be multiplied by X to be interesting.
1141 * Soft limits are those which are used for the dynamic reclocking done
1142 * by the driver (raise frequencies under heavy loads, and lower for
1143 * lighter loads). Hard limits are those imposed by the hardware.
1145 * A distinction is made for overclocking, which is never enabled by
1146 * default, and is considered to be above the hard limit if it's
1149 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1150 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1151 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1152 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1153 u8 min_freq; /* AKA RPn. Minimum frequency */
1154 u8 idle_freq; /* Frequency to request when we are idle */
1155 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1156 u8 rp1_freq; /* "less than" RP0 power/freqency */
1157 u8 rp0_freq; /* Non-overclocked max frequency. */
1159 u8 up_threshold; /* Current %busy required to uplock */
1160 u8 down_threshold; /* Current %busy required to downclock */
1163 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1165 spinlock_t client_lock;
1166 struct list_head clients;
1170 struct delayed_work delayed_resume_work;
1173 struct intel_rps_client semaphores, mmioflips;
1175 /* manual wa residency calculations */
1176 struct intel_rps_ei up_ei, down_ei;
1179 * Protects RPS/RC6 register access and PCU communication.
1180 * Must be taken after struct_mutex if nested. Note that
1181 * this lock may be held for long periods of time when
1182 * talking to hw - so only take it when talking to hw!
1184 struct mutex hw_lock;
1187 /* defined intel_pm.c */
1188 extern spinlock_t mchdev_lock;
1190 struct intel_ilk_power_mgmt {
1198 unsigned long last_time1;
1199 unsigned long chipset_power;
1202 unsigned long gfx_power;
1209 struct drm_i915_private;
1210 struct i915_power_well;
1212 struct i915_power_well_ops {
1214 * Synchronize the well's hw state to match the current sw state, for
1215 * example enable/disable it based on the current refcount. Called
1216 * during driver init and resume time, possibly after first calling
1217 * the enable/disable handlers.
1219 void (*sync_hw)(struct drm_i915_private *dev_priv,
1220 struct i915_power_well *power_well);
1222 * Enable the well and resources that depend on it (for example
1223 * interrupts located on the well). Called after the 0->1 refcount
1226 void (*enable)(struct drm_i915_private *dev_priv,
1227 struct i915_power_well *power_well);
1229 * Disable the well and resources that depend on it. Called after
1230 * the 1->0 refcount transition.
1232 void (*disable)(struct drm_i915_private *dev_priv,
1233 struct i915_power_well *power_well);
1234 /* Returns the hw enabled state. */
1235 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1236 struct i915_power_well *power_well);
1239 /* Power well structure for haswell */
1240 struct i915_power_well {
1243 /* power well enable/disable usage count */
1245 /* cached hw enabled state */
1247 unsigned long domains;
1249 const struct i915_power_well_ops *ops;
1252 struct i915_power_domains {
1254 * Power wells needed for initialization at driver init and suspend
1255 * time are on. They are kept on until after the first modeset.
1259 int power_well_count;
1262 int domain_use_count[POWER_DOMAIN_NUM];
1263 struct i915_power_well *power_wells;
1266 #define MAX_L3_SLICES 2
1267 struct intel_l3_parity {
1268 u32 *remap_info[MAX_L3_SLICES];
1269 struct work_struct error_work;
1273 struct i915_gem_mm {
1274 /** Memory allocator for GTT stolen memory */
1275 struct drm_mm stolen;
1276 /** Protects the usage of the GTT stolen memory allocator. This is
1277 * always the inner lock when overlapping with struct_mutex. */
1278 struct mutex stolen_lock;
1280 /** List of all objects in gtt_space. Used to restore gtt
1281 * mappings on resume */
1282 struct list_head bound_list;
1284 * List of objects which are not bound to the GTT (thus
1285 * are idle and not used by the GPU) but still have
1286 * (presumably uncached) pages still attached.
1288 struct list_head unbound_list;
1290 /** Usable portion of the GTT for GEM */
1291 unsigned long stolen_base; /* limited to low memory (32-bit) */
1293 /** PPGTT used for aliasing the PPGTT with the GTT */
1294 struct i915_hw_ppgtt *aliasing_ppgtt;
1296 struct notifier_block oom_notifier;
1297 struct shrinker shrinker;
1298 bool shrinker_no_lock_stealing;
1300 /** LRU list of objects with fence regs on them. */
1301 struct list_head fence_list;
1304 * We leave the user IRQ off as much as possible,
1305 * but this means that requests will finish and never
1306 * be retired once the system goes idle. Set a timer to
1307 * fire periodically while the ring is running. When it
1308 * fires, go retire requests.
1310 struct delayed_work retire_work;
1313 * When we detect an idle GPU, we want to turn on
1314 * powersaving features. So once we see that there
1315 * are no more requests outstanding and no more
1316 * arrive within a small period of time, we fire
1317 * off the idle_work.
1319 struct delayed_work idle_work;
1322 * Are we in a non-interruptible section of code like
1328 * Is the GPU currently considered idle, or busy executing userspace
1329 * requests? Whilst idle, we attempt to power down the hardware and
1330 * display clocks. In order to reduce the effect on performance, there
1331 * is a slight delay before we do so.
1335 /* the indicator for dispatch video commands on two BSD rings */
1336 unsigned int bsd_ring_dispatch_index;
1338 /** Bit 6 swizzling required for X tiling */
1339 uint32_t bit_6_swizzle_x;
1340 /** Bit 6 swizzling required for Y tiling */
1341 uint32_t bit_6_swizzle_y;
1343 /* accounting, useful for userland debugging */
1344 spinlock_t object_stat_lock;
1345 size_t object_memory;
1349 struct drm_i915_error_state_buf {
1350 struct drm_i915_private *i915;
1359 struct i915_error_state_file_priv {
1360 struct drm_device *dev;
1361 struct drm_i915_error_state *error;
1364 struct i915_gpu_error {
1365 /* For hangcheck timer */
1366 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1367 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1368 /* Hang gpu twice in this window and your context gets banned */
1369 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1371 struct workqueue_struct *hangcheck_wq;
1372 struct delayed_work hangcheck_work;
1374 /* For reset and error_state handling. */
1376 /* Protected by the above dev->gpu_error.lock. */
1377 struct drm_i915_error_state *first_error;
1379 unsigned long missed_irq_rings;
1382 * State variable controlling the reset flow and count
1384 * This is a counter which gets incremented when reset is triggered,
1385 * and again when reset has been handled. So odd values (lowest bit set)
1386 * means that reset is in progress and even values that
1387 * (reset_counter >> 1):th reset was successfully completed.
1389 * If reset is not completed succesfully, the I915_WEDGE bit is
1390 * set meaning that hardware is terminally sour and there is no
1391 * recovery. All waiters on the reset_queue will be woken when
1394 * This counter is used by the wait_seqno code to notice that reset
1395 * event happened and it needs to restart the entire ioctl (since most
1396 * likely the seqno it waited for won't ever signal anytime soon).
1398 * This is important for lock-free wait paths, where no contended lock
1399 * naturally enforces the correct ordering between the bail-out of the
1400 * waiter and the gpu reset work code.
1402 atomic_t reset_counter;
1404 #define I915_RESET_IN_PROGRESS_FLAG 1
1405 #define I915_WEDGED (1 << 31)
1408 * Waitqueue to signal when the reset has completed. Used by clients
1409 * that wait for dev_priv->mm.wedged to settle.
1411 wait_queue_head_t reset_queue;
1413 /* Userspace knobs for gpu hang simulation;
1414 * combines both a ring mask, and extra flags
1417 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1418 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1420 /* For missed irq/seqno simulation. */
1421 unsigned int test_irq_rings;
1423 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1424 bool reload_in_reset;
1427 enum modeset_restore {
1428 MODESET_ON_LID_OPEN,
1433 #define DP_AUX_A 0x40
1434 #define DP_AUX_B 0x10
1435 #define DP_AUX_C 0x20
1436 #define DP_AUX_D 0x30
1438 #define DDC_PIN_B 0x05
1439 #define DDC_PIN_C 0x04
1440 #define DDC_PIN_D 0x06
1442 struct ddi_vbt_port_info {
1444 * This is an index in the HDMI/DVI DDI buffer translation table.
1445 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1446 * populate this field.
1448 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1449 uint8_t hdmi_level_shift;
1451 uint8_t supports_dvi:1;
1452 uint8_t supports_hdmi:1;
1453 uint8_t supports_dp:1;
1455 uint8_t alternate_aux_channel;
1456 uint8_t alternate_ddc_pin;
1458 uint8_t dp_boost_level;
1459 uint8_t hdmi_boost_level;
1462 enum psr_lines_to_wait {
1463 PSR_0_LINES_TO_WAIT = 0,
1465 PSR_4_LINES_TO_WAIT,
1469 struct intel_vbt_data {
1470 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1471 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1474 unsigned int int_tv_support:1;
1475 unsigned int lvds_dither:1;
1476 unsigned int lvds_vbt:1;
1477 unsigned int int_crt_support:1;
1478 unsigned int lvds_use_ssc:1;
1479 unsigned int display_clock_mode:1;
1480 unsigned int fdi_rx_polarity_inverted:1;
1481 unsigned int has_mipi:1;
1483 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1485 enum drrs_support_type drrs_type;
1490 int edp_preemphasis;
1492 bool edp_initialized;
1495 struct edp_power_seq edp_pps;
1499 bool require_aux_wakeup;
1501 enum psr_lines_to_wait lines_to_wait;
1502 int tp1_wakeup_time;
1503 int tp2_tp3_wakeup_time;
1509 bool active_low_pwm;
1510 u8 min_brightness; /* min_brightness/255 of max */
1517 struct mipi_config *config;
1518 struct mipi_pps_data *pps;
1522 const u8 *sequence[MIPI_SEQ_MAX];
1528 union child_device_config *child_dev;
1530 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1533 enum intel_ddb_partitioning {
1535 INTEL_DDB_PART_5_6, /* IVB+ */
1538 struct intel_wm_level {
1546 struct ilk_wm_values {
1547 uint32_t wm_pipe[3];
1549 uint32_t wm_lp_spr[3];
1550 uint32_t wm_linetime[3];
1552 enum intel_ddb_partitioning partitioning;
1555 struct vlv_pipe_wm {
1566 struct vlv_wm_values {
1567 struct vlv_pipe_wm pipe[3];
1568 struct vlv_sr_wm sr;
1578 struct skl_ddb_entry {
1579 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1582 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1584 return entry->end - entry->start;
1587 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1588 const struct skl_ddb_entry *e2)
1590 if (e1->start == e2->start && e1->end == e2->end)
1596 struct skl_ddb_allocation {
1597 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1598 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1599 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1602 struct skl_wm_values {
1603 bool dirty[I915_MAX_PIPES];
1604 struct skl_ddb_allocation ddb;
1605 uint32_t wm_linetime[I915_MAX_PIPES];
1606 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1607 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1610 struct skl_wm_level {
1611 bool plane_en[I915_MAX_PLANES];
1612 uint16_t plane_res_b[I915_MAX_PLANES];
1613 uint8_t plane_res_l[I915_MAX_PLANES];
1617 * This struct helps tracking the state needed for runtime PM, which puts the
1618 * device in PCI D3 state. Notice that when this happens, nothing on the
1619 * graphics device works, even register access, so we don't get interrupts nor
1622 * Every piece of our code that needs to actually touch the hardware needs to
1623 * either call intel_runtime_pm_get or call intel_display_power_get with the
1624 * appropriate power domain.
1626 * Our driver uses the autosuspend delay feature, which means we'll only really
1627 * suspend if we stay with zero refcount for a certain amount of time. The
1628 * default value is currently very conservative (see intel_runtime_pm_enable), but
1629 * it can be changed with the standard runtime PM files from sysfs.
1631 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1632 * goes back to false exactly before we reenable the IRQs. We use this variable
1633 * to check if someone is trying to enable/disable IRQs while they're supposed
1634 * to be disabled. This shouldn't happen and we'll print some error messages in
1637 * For more, read the Documentation/power/runtime_pm.txt.
1639 struct i915_runtime_pm {
1640 atomic_t wakeref_count;
1641 atomic_t atomic_seq;
1646 enum intel_pipe_crc_source {
1647 INTEL_PIPE_CRC_SOURCE_NONE,
1648 INTEL_PIPE_CRC_SOURCE_PLANE1,
1649 INTEL_PIPE_CRC_SOURCE_PLANE2,
1650 INTEL_PIPE_CRC_SOURCE_PF,
1651 INTEL_PIPE_CRC_SOURCE_PIPE,
1652 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1653 INTEL_PIPE_CRC_SOURCE_TV,
1654 INTEL_PIPE_CRC_SOURCE_DP_B,
1655 INTEL_PIPE_CRC_SOURCE_DP_C,
1656 INTEL_PIPE_CRC_SOURCE_DP_D,
1657 INTEL_PIPE_CRC_SOURCE_AUTO,
1658 INTEL_PIPE_CRC_SOURCE_MAX,
1661 struct intel_pipe_crc_entry {
1666 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1667 struct intel_pipe_crc {
1669 bool opened; /* exclusive access to the result file */
1670 struct intel_pipe_crc_entry *entries;
1671 enum intel_pipe_crc_source source;
1673 wait_queue_head_t wq;
1676 struct i915_frontbuffer_tracking {
1680 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1687 struct i915_wa_reg {
1690 /* bitmask representing WA bits */
1695 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1696 * allowing it for RCS as we don't foresee any requirement of having
1697 * a whitelist for other engines. When it is really required for
1698 * other engines then the limit need to be increased.
1700 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1702 struct i915_workarounds {
1703 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1705 u32 hw_whitelist_count[I915_NUM_RINGS];
1708 struct i915_virtual_gpu {
1712 struct i915_execbuffer_params {
1713 struct drm_device *dev;
1714 struct drm_file *file;
1715 uint32_t dispatch_flags;
1716 uint32_t args_batch_start_offset;
1717 uint64_t batch_obj_vm_offset;
1718 struct intel_engine_cs *ring;
1719 struct drm_i915_gem_object *batch_obj;
1720 struct intel_context *ctx;
1721 struct drm_i915_gem_request *request;
1724 /* used in computing the new watermarks state */
1725 struct intel_wm_config {
1726 unsigned int num_pipes_active;
1727 bool sprites_enabled;
1728 bool sprites_scaled;
1731 struct drm_i915_private {
1732 struct drm_device *dev;
1733 struct kmem_cache *objects;
1734 struct kmem_cache *vmas;
1735 struct kmem_cache *requests;
1737 const struct intel_device_info info;
1739 int relative_constants_mode;
1743 struct intel_uncore uncore;
1745 struct i915_virtual_gpu vgpu;
1747 struct intel_guc guc;
1749 struct intel_csr csr;
1751 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1753 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1754 * controller on different i2c buses. */
1755 struct mutex gmbus_mutex;
1758 * Base address of the gmbus and gpio block.
1760 uint32_t gpio_mmio_base;
1762 /* MMIO base address for MIPI regs */
1763 uint32_t mipi_mmio_base;
1765 uint32_t psr_mmio_base;
1767 wait_queue_head_t gmbus_wait_queue;
1769 struct pci_dev *bridge_dev;
1770 struct intel_engine_cs ring[I915_NUM_RINGS];
1771 struct drm_i915_gem_object *semaphore_obj;
1772 uint32_t last_seqno, next_seqno;
1774 struct drm_dma_handle *status_page_dmah;
1775 struct resource mch_res;
1777 /* protects the irq masks */
1778 spinlock_t irq_lock;
1780 /* protects the mmio flip data */
1781 spinlock_t mmio_flip_lock;
1783 bool display_irqs_enabled;
1785 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1786 struct pm_qos_request pm_qos;
1788 /* Sideband mailbox protection */
1789 struct mutex sb_lock;
1791 /** Cached value of IMR to avoid reads in updating the bitfield */
1794 u32 de_irq_mask[I915_MAX_PIPES];
1799 u32 pipestat_irq_mask[I915_MAX_PIPES];
1801 struct i915_hotplug hotplug;
1802 struct intel_fbc fbc;
1803 struct i915_drrs drrs;
1804 struct intel_opregion opregion;
1805 struct intel_vbt_data vbt;
1807 bool preserve_bios_swizzle;
1810 struct intel_overlay *overlay;
1812 /* backlight registers and fields in struct intel_panel */
1813 struct mutex backlight_lock;
1816 bool no_aux_handshake;
1818 /* protects panel power sequencer state */
1819 struct mutex pps_mutex;
1821 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1822 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1824 unsigned int fsb_freq, mem_freq, is_ddr3;
1825 unsigned int skl_boot_cdclk;
1826 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1827 unsigned int max_dotclk_freq;
1828 unsigned int hpll_freq;
1829 unsigned int czclk_freq;
1832 * wq - Driver workqueue for GEM.
1834 * NOTE: Work items scheduled here are not allowed to grab any modeset
1835 * locks, for otherwise the flushing done in the pageflip code will
1836 * result in deadlocks.
1838 struct workqueue_struct *wq;
1840 /* Display functions */
1841 struct drm_i915_display_funcs display;
1843 /* PCH chipset type */
1844 enum intel_pch pch_type;
1845 unsigned short pch_id;
1847 unsigned long quirks;
1849 enum modeset_restore modeset_restore;
1850 struct mutex modeset_restore_lock;
1852 struct list_head vm_list; /* Global list of all address spaces */
1853 struct i915_gtt gtt; /* VM representing the global address space */
1855 struct i915_gem_mm mm;
1856 DECLARE_HASHTABLE(mm_structs, 7);
1857 struct mutex mm_lock;
1859 /* Kernel Modesetting */
1861 struct sdvo_device_mapping sdvo_mappings[2];
1863 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1864 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1865 wait_queue_head_t pending_flip_queue;
1867 #ifdef CONFIG_DEBUG_FS
1868 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1871 /* dpll and cdclk state is protected by connection_mutex */
1872 int num_shared_dpll;
1873 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1875 unsigned int active_crtcs;
1876 unsigned int min_pixclk[I915_MAX_PIPES];
1878 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1880 struct i915_workarounds workarounds;
1882 /* Reclocking support */
1883 bool render_reclock_avail;
1885 struct i915_frontbuffer_tracking fb_tracking;
1889 bool mchbar_need_disable;
1891 struct intel_l3_parity l3_parity;
1893 /* Cannot be determined by PCIID. You must always read a register. */
1896 /* gen6+ rps state */
1897 struct intel_gen6_power_mgmt rps;
1899 /* ilk-only ips/rps state. Everything in here is protected by the global
1900 * mchdev_lock in intel_pm.c */
1901 struct intel_ilk_power_mgmt ips;
1903 struct i915_power_domains power_domains;
1905 struct i915_psr psr;
1907 struct i915_gpu_error gpu_error;
1909 struct drm_i915_gem_object *vlv_pctx;
1911 #ifdef CONFIG_DRM_FBDEV_EMULATION
1912 /* list of fbdev register on this device */
1913 struct intel_fbdev *fbdev;
1914 struct work_struct fbdev_suspend_work;
1917 struct drm_property *broadcast_rgb_property;
1918 struct drm_property *force_audio_property;
1920 /* hda/i915 audio component */
1921 struct i915_audio_component *audio_component;
1922 bool audio_component_registered;
1924 * av_mutex - mutex for audio/video sync
1927 struct mutex av_mutex;
1929 uint32_t hw_context_size;
1930 struct list_head context_list;
1934 u32 chv_phy_control;
1937 bool suspended_to_idle;
1938 struct i915_suspend_saved_registers regfile;
1939 struct vlv_s0ix_state vlv_s0ix_state;
1943 * Raw watermark latency values:
1944 * in 0.1us units for WM0,
1945 * in 0.5us units for WM1+.
1948 uint16_t pri_latency[5];
1950 uint16_t spr_latency[5];
1952 uint16_t cur_latency[5];
1954 * Raw watermark memory latency values
1955 * for SKL for all 8 levels
1958 uint16_t skl_latency[8];
1960 /* Committed wm config */
1961 struct intel_wm_config config;
1964 * The skl_wm_values structure is a bit too big for stack
1965 * allocation, so we keep the staging struct where we store
1966 * intermediate results here instead.
1968 struct skl_wm_values skl_results;
1970 /* current hardware state */
1972 struct ilk_wm_values hw;
1973 struct skl_wm_values skl_hw;
1974 struct vlv_wm_values vlv;
1980 struct i915_runtime_pm pm;
1982 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1984 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1985 struct drm_i915_gem_execbuffer2 *args,
1986 struct list_head *vmas);
1987 int (*init_rings)(struct drm_device *dev);
1988 void (*cleanup_ring)(struct intel_engine_cs *ring);
1989 void (*stop_ring)(struct intel_engine_cs *ring);
1992 struct intel_context *kernel_context;
1994 bool edp_low_vswing;
1996 /* perform PHY state sanity checks? */
1997 bool chv_phy_assert[2];
1999 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
2002 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2003 * will be rejected. Instead look for a better place.
2007 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2009 return dev->dev_private;
2012 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
2014 return to_i915(dev_get_drvdata(dev));
2017 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2019 return container_of(guc, struct drm_i915_private, guc);
2022 /* Iterate over initialised rings */
2023 #define for_each_ring(ring__, dev_priv__, i__) \
2024 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
2025 for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))))
2027 enum hdmi_force_audio {
2028 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2029 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2030 HDMI_AUDIO_AUTO, /* trust EDID */
2031 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2034 #define I915_GTT_OFFSET_NONE ((u32)-1)
2036 struct drm_i915_gem_object_ops {
2038 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2040 /* Interface between the GEM object and its backing storage.
2041 * get_pages() is called once prior to the use of the associated set
2042 * of pages before to binding them into the GTT, and put_pages() is
2043 * called after we no longer need them. As we expect there to be
2044 * associated cost with migrating pages between the backing storage
2045 * and making them available for the GPU (e.g. clflush), we may hold
2046 * onto the pages after they are no longer referenced by the GPU
2047 * in case they may be used again shortly (for example migrating the
2048 * pages to a different memory domain within the GTT). put_pages()
2049 * will therefore most likely be called when the object itself is
2050 * being released or under memory pressure (where we attempt to
2051 * reap pages for the shrinker).
2053 int (*get_pages)(struct drm_i915_gem_object *);
2054 void (*put_pages)(struct drm_i915_gem_object *);
2056 int (*dmabuf_export)(struct drm_i915_gem_object *);
2057 void (*release)(struct drm_i915_gem_object *);
2061 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2062 * considered to be the frontbuffer for the given plane interface-wise. This
2063 * doesn't mean that the hw necessarily already scans it out, but that any
2064 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2066 * We have one bit per pipe and per scanout plane type.
2068 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2069 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2070 #define INTEL_FRONTBUFFER_BITS \
2071 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2072 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2073 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2074 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2075 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2076 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2077 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2078 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2079 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2080 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2081 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2083 struct drm_i915_gem_object {
2084 struct drm_gem_object base;
2086 const struct drm_i915_gem_object_ops *ops;
2088 /** List of VMAs backed by this object */
2089 struct list_head vma_list;
2091 /** Stolen memory for this object, instead of being backed by shmem. */
2092 struct drm_mm_node *stolen;
2093 struct list_head global_list;
2095 struct list_head ring_list[I915_NUM_RINGS];
2096 /** Used in execbuf to temporarily hold a ref */
2097 struct list_head obj_exec_link;
2099 struct list_head batch_pool_link;
2102 * This is set if the object is on the active lists (has pending
2103 * rendering and so a non-zero seqno), and is not set if it i s on
2104 * inactive (ready to be unbound) list.
2106 unsigned int active:I915_NUM_RINGS;
2109 * This is set if the object has been written to since last bound
2112 unsigned int dirty:1;
2115 * Fence register bits (if any) for this object. Will be set
2116 * as needed when mapped into the GTT.
2117 * Protected by dev->struct_mutex.
2119 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2122 * Advice: are the backing pages purgeable?
2124 unsigned int madv:2;
2127 * Current tiling mode for the object.
2129 unsigned int tiling_mode:2;
2131 * Whether the tiling parameters for the currently associated fence
2132 * register have changed. Note that for the purposes of tracking
2133 * tiling changes we also treat the unfenced register, the register
2134 * slot that the object occupies whilst it executes a fenced
2135 * command (such as BLT on gen2/3), as a "fence".
2137 unsigned int fence_dirty:1;
2140 * Is the object at the current location in the gtt mappable and
2141 * fenceable? Used to avoid costly recalculations.
2143 unsigned int map_and_fenceable:1;
2146 * Whether the current gtt mapping needs to be mappable (and isn't just
2147 * mappable by accident). Track pin and fault separate for a more
2148 * accurate mappable working set.
2150 unsigned int fault_mappable:1;
2153 * Is the object to be mapped as read-only to the GPU
2154 * Only honoured if hardware has relevant pte bit
2156 unsigned long gt_ro:1;
2157 unsigned int cache_level:3;
2158 unsigned int cache_dirty:1;
2160 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2162 unsigned int pin_display;
2164 struct sg_table *pages;
2165 int pages_pin_count;
2167 struct scatterlist *sg;
2171 /* prime dma-buf support */
2172 void *dma_buf_vmapping;
2175 /** Breadcrumb of last rendering to the buffer.
2176 * There can only be one writer, but we allow for multiple readers.
2177 * If there is a writer that necessarily implies that all other
2178 * read requests are complete - but we may only be lazily clearing
2179 * the read requests. A read request is naturally the most recent
2180 * request on a ring, so we may have two different write and read
2181 * requests on one ring where the write request is older than the
2182 * read request. This allows for the CPU to read from an active
2183 * buffer by only waiting for the write to complete.
2185 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2186 struct drm_i915_gem_request *last_write_req;
2187 /** Breadcrumb of last fenced GPU access to the buffer. */
2188 struct drm_i915_gem_request *last_fenced_req;
2190 /** Current tiling stride for the object, if it's tiled. */
2193 /** References from framebuffers, locks out tiling changes. */
2194 unsigned long framebuffer_references;
2196 /** Record of address bit 17 of each page at last unbind. */
2197 unsigned long *bit_17;
2200 /** for phy allocated objects */
2201 struct drm_dma_handle *phys_handle;
2203 struct i915_gem_userptr {
2205 unsigned read_only :1;
2206 unsigned workers :4;
2207 #define I915_GEM_USERPTR_MAX_WORKERS 15
2209 struct i915_mm_struct *mm;
2210 struct i915_mmu_object *mmu_object;
2211 struct work_struct *work;
2215 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2217 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2218 struct drm_i915_gem_object *new,
2219 unsigned frontbuffer_bits);
2222 * Request queue structure.
2224 * The request queue allows us to note sequence numbers that have been emitted
2225 * and may be associated with active buffers to be retired.
2227 * By keeping this list, we can avoid having to do questionable sequence
2228 * number comparisons on buffer last_read|write_seqno. It also allows an
2229 * emission time to be associated with the request for tracking how far ahead
2230 * of the GPU the submission is.
2232 * The requests are reference counted, so upon creation they should have an
2233 * initial reference taken using kref_init
2235 struct drm_i915_gem_request {
2238 /** On Which ring this request was generated */
2239 struct drm_i915_private *i915;
2240 struct intel_engine_cs *ring;
2242 /** GEM sequence number associated with the previous request,
2243 * when the HWS breadcrumb is equal to this the GPU is processing
2248 /** GEM sequence number associated with this request,
2249 * when the HWS breadcrumb is equal or greater than this the GPU
2250 * has finished processing this request.
2254 /** Position in the ringbuffer of the start of the request */
2258 * Position in the ringbuffer of the start of the postfix.
2259 * This is required to calculate the maximum available ringbuffer
2260 * space without overwriting the postfix.
2264 /** Position in the ringbuffer of the end of the whole request */
2268 * Context and ring buffer related to this request
2269 * Contexts are refcounted, so when this request is associated with a
2270 * context, we must increment the context's refcount, to guarantee that
2271 * it persists while any request is linked to it. Requests themselves
2272 * are also refcounted, so the request will only be freed when the last
2273 * reference to it is dismissed, and the code in
2274 * i915_gem_request_free() will then decrement the refcount on the
2277 struct intel_context *ctx;
2278 struct intel_ringbuffer *ringbuf;
2280 /** Batch buffer related to this request if any (used for
2281 error state dump only) */
2282 struct drm_i915_gem_object *batch_obj;
2284 /** Time at which this request was emitted, in jiffies. */
2285 unsigned long emitted_jiffies;
2287 /** global list entry for this request */
2288 struct list_head list;
2290 struct drm_i915_file_private *file_priv;
2291 /** file_priv list entry for this request */
2292 struct list_head client_list;
2294 /** process identifier submitting this request */
2298 * The ELSP only accepts two elements at a time, so we queue
2299 * context/tail pairs on a given queue (ring->execlist_queue) until the
2300 * hardware is available. The queue serves a double purpose: we also use
2301 * it to keep track of the up to 2 contexts currently in the hardware
2302 * (usually one in execution and the other queued up by the GPU): We
2303 * only remove elements from the head of the queue when the hardware
2304 * informs us that an element has been completed.
2306 * All accesses to the queue are mediated by a spinlock
2307 * (ring->execlist_lock).
2310 /** Execlist link in the submission queue.*/
2311 struct list_head execlist_link;
2313 /** Execlists no. of times this request has been sent to the ELSP */
2318 struct drm_i915_gem_request * __must_check
2319 i915_gem_request_alloc(struct intel_engine_cs *engine,
2320 struct intel_context *ctx);
2321 void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2322 void i915_gem_request_free(struct kref *req_ref);
2323 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2324 struct drm_file *file);
2326 static inline uint32_t
2327 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2329 return req ? req->seqno : 0;
2332 static inline struct intel_engine_cs *
2333 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2335 return req ? req->ring : NULL;
2338 static inline struct drm_i915_gem_request *
2339 i915_gem_request_reference(struct drm_i915_gem_request *req)
2342 kref_get(&req->ref);
2347 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2349 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2350 kref_put(&req->ref, i915_gem_request_free);
2354 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2356 struct drm_device *dev;
2361 dev = req->ring->dev;
2362 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2363 mutex_unlock(&dev->struct_mutex);
2366 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2367 struct drm_i915_gem_request *src)
2370 i915_gem_request_reference(src);
2373 i915_gem_request_unreference(*pdst);
2379 * XXX: i915_gem_request_completed should be here but currently needs the
2380 * definition of i915_seqno_passed() which is below. It will be moved in
2381 * a later patch when the call to i915_seqno_passed() is obsoleted...
2385 * A command that requires special handling by the command parser.
2387 struct drm_i915_cmd_descriptor {
2389 * Flags describing how the command parser processes the command.
2391 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2392 * a length mask if not set
2393 * CMD_DESC_SKIP: The command is allowed but does not follow the
2394 * standard length encoding for the opcode range in
2396 * CMD_DESC_REJECT: The command is never allowed
2397 * CMD_DESC_REGISTER: The command should be checked against the
2398 * register whitelist for the appropriate ring
2399 * CMD_DESC_MASTER: The command is allowed if the submitting process
2403 #define CMD_DESC_FIXED (1<<0)
2404 #define CMD_DESC_SKIP (1<<1)
2405 #define CMD_DESC_REJECT (1<<2)
2406 #define CMD_DESC_REGISTER (1<<3)
2407 #define CMD_DESC_BITMASK (1<<4)
2408 #define CMD_DESC_MASTER (1<<5)
2411 * The command's unique identification bits and the bitmask to get them.
2412 * This isn't strictly the opcode field as defined in the spec and may
2413 * also include type, subtype, and/or subop fields.
2421 * The command's length. The command is either fixed length (i.e. does
2422 * not include a length field) or has a length field mask. The flag
2423 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2424 * a length mask. All command entries in a command table must include
2425 * length information.
2433 * Describes where to find a register address in the command to check
2434 * against the ring's register whitelist. Only valid if flags has the
2435 * CMD_DESC_REGISTER bit set.
2437 * A non-zero step value implies that the command may access multiple
2438 * registers in sequence (e.g. LRI), in that case step gives the
2439 * distance in dwords between individual offset fields.
2447 #define MAX_CMD_DESC_BITMASKS 3
2449 * Describes command checks where a particular dword is masked and
2450 * compared against an expected value. If the command does not match
2451 * the expected value, the parser rejects it. Only valid if flags has
2452 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2455 * If the check specifies a non-zero condition_mask then the parser
2456 * only performs the check when the bits specified by condition_mask
2463 u32 condition_offset;
2465 } bits[MAX_CMD_DESC_BITMASKS];
2469 * A table of commands requiring special handling by the command parser.
2471 * Each ring has an array of tables. Each table consists of an array of command
2472 * descriptors, which must be sorted with command opcodes in ascending order.
2474 struct drm_i915_cmd_table {
2475 const struct drm_i915_cmd_descriptor *table;
2479 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2480 #define __I915__(p) ({ \
2481 struct drm_i915_private *__p; \
2482 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2483 __p = (struct drm_i915_private *)p; \
2484 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2485 __p = to_i915((struct drm_device *)p); \
2490 #define INTEL_INFO(p) (&__I915__(p)->info)
2491 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2492 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2494 #define REVID_FOREVER 0xff
2496 * Return true if revision is in range [since,until] inclusive.
2498 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2500 #define IS_REVID(p, since, until) \
2501 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2503 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2504 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2505 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2506 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2507 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2508 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2509 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2510 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2511 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2512 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2513 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2514 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2515 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2516 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2517 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2518 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2519 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2520 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2521 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2522 INTEL_DEVID(dev) == 0x0152 || \
2523 INTEL_DEVID(dev) == 0x015a)
2524 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2525 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2526 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2527 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2528 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2529 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2530 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2531 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2532 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2533 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2534 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2535 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2536 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2537 (INTEL_DEVID(dev) & 0xf) == 0xe))
2538 /* ULX machines are also considered ULT. */
2539 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2540 (INTEL_DEVID(dev) & 0xf) == 0xe)
2541 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2542 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2543 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2544 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2545 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2546 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2547 /* ULX machines are also considered ULT. */
2548 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2549 INTEL_DEVID(dev) == 0x0A1E)
2550 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2551 INTEL_DEVID(dev) == 0x1913 || \
2552 INTEL_DEVID(dev) == 0x1916 || \
2553 INTEL_DEVID(dev) == 0x1921 || \
2554 INTEL_DEVID(dev) == 0x1926)
2555 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2556 INTEL_DEVID(dev) == 0x1915 || \
2557 INTEL_DEVID(dev) == 0x191E)
2558 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2559 INTEL_DEVID(dev) == 0x5913 || \
2560 INTEL_DEVID(dev) == 0x5916 || \
2561 INTEL_DEVID(dev) == 0x5921 || \
2562 INTEL_DEVID(dev) == 0x5926)
2563 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2564 INTEL_DEVID(dev) == 0x5915 || \
2565 INTEL_DEVID(dev) == 0x591E)
2566 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2567 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2568 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2569 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2571 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2573 #define SKL_REVID_A0 0x0
2574 #define SKL_REVID_B0 0x1
2575 #define SKL_REVID_C0 0x2
2576 #define SKL_REVID_D0 0x3
2577 #define SKL_REVID_E0 0x4
2578 #define SKL_REVID_F0 0x5
2580 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2582 #define BXT_REVID_A0 0x0
2583 #define BXT_REVID_A1 0x1
2584 #define BXT_REVID_B0 0x3
2585 #define BXT_REVID_C0 0x9
2587 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2590 * The genX designation typically refers to the render engine, so render
2591 * capability related checks should use IS_GEN, while display and other checks
2592 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2595 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2596 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2597 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2598 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2599 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2600 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2601 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2602 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2604 #define RENDER_RING (1<<RCS)
2605 #define BSD_RING (1<<VCS)
2606 #define BLT_RING (1<<BCS)
2607 #define VEBOX_RING (1<<VECS)
2608 #define BSD2_RING (1<<VCS2)
2609 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2610 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2611 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2612 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2613 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2614 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2615 __I915__(dev)->ellc_size)
2616 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2618 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2619 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2620 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2621 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2622 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2624 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2625 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2627 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2628 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2630 /* WaRsDisableCoarsePowerGating:skl,bxt */
2631 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2632 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
2633 IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
2635 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2636 * even when in MSI mode. This results in spurious interrupt warnings if the
2637 * legacy irq no. is shared with another device. The kernel then disables that
2638 * interrupt source and so prevents the other device from working properly.
2640 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2641 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2643 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2644 * rows, which changed the alignment requirements and fence programming.
2646 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2648 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2649 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2651 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2652 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2653 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2655 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2657 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2658 INTEL_INFO(dev)->gen >= 9)
2660 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2661 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2662 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2663 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2664 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2665 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2666 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2667 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2669 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2670 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2672 #define HAS_CSR(dev) (IS_GEN9(dev))
2674 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2675 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2677 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2678 INTEL_INFO(dev)->gen >= 8)
2680 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2681 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2684 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2685 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2686 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2687 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2688 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2689 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2690 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2691 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2692 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2693 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2695 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2696 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2697 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2698 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2699 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2700 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2701 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2702 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2703 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2705 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2706 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2708 /* DPF == dynamic parity feature */
2709 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2710 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2712 #define GT_FREQUENCY_MULTIPLIER 50
2713 #define GEN9_FREQ_SCALER 3
2715 #include "i915_trace.h"
2717 extern const struct drm_ioctl_desc i915_ioctls[];
2718 extern int i915_max_ioctl;
2720 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2721 extern int i915_resume_switcheroo(struct drm_device *dev);
2724 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2725 extern int i915_driver_unload(struct drm_device *);
2726 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2727 extern void i915_driver_lastclose(struct drm_device * dev);
2728 extern void i915_driver_preclose(struct drm_device *dev,
2729 struct drm_file *file);
2730 extern void i915_driver_postclose(struct drm_device *dev,
2731 struct drm_file *file);
2732 #ifdef CONFIG_COMPAT
2733 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2736 extern int intel_gpu_reset(struct drm_device *dev);
2737 extern bool intel_has_gpu_reset(struct drm_device *dev);
2738 extern int i915_reset(struct drm_device *dev);
2739 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2740 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2741 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2742 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2743 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2745 /* intel_hotplug.c */
2746 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2747 void intel_hpd_init(struct drm_i915_private *dev_priv);
2748 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2749 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2750 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2753 void i915_queue_hangcheck(struct drm_device *dev);
2755 void i915_handle_error(struct drm_device *dev, bool wedged,
2756 const char *fmt, ...);
2758 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2759 int intel_irq_install(struct drm_i915_private *dev_priv);
2760 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2762 extern void intel_uncore_sanitize(struct drm_device *dev);
2763 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2764 bool restore_forcewake);
2765 extern void intel_uncore_init(struct drm_device *dev);
2766 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2767 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2768 extern void intel_uncore_fini(struct drm_device *dev);
2769 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2770 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2771 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2772 enum forcewake_domains domains);
2773 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2774 enum forcewake_domains domains);
2775 /* Like above but the caller must manage the uncore.lock itself.
2776 * Must be used with I915_READ_FW and friends.
2778 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2779 enum forcewake_domains domains);
2780 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2781 enum forcewake_domains domains);
2782 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2783 static inline bool intel_vgpu_active(struct drm_device *dev)
2785 return to_i915(dev)->vgpu.active;
2789 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2793 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2796 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2797 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2798 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2801 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2802 uint32_t interrupt_mask,
2803 uint32_t enabled_irq_mask);
2805 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2807 ilk_update_display_irq(dev_priv, bits, bits);
2810 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2812 ilk_update_display_irq(dev_priv, bits, 0);
2814 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2816 uint32_t interrupt_mask,
2817 uint32_t enabled_irq_mask);
2818 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2819 enum pipe pipe, uint32_t bits)
2821 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2823 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2824 enum pipe pipe, uint32_t bits)
2826 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2828 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2829 uint32_t interrupt_mask,
2830 uint32_t enabled_irq_mask);
2832 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2834 ibx_display_interrupt_update(dev_priv, bits, bits);
2837 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2839 ibx_display_interrupt_update(dev_priv, bits, 0);
2844 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2845 struct drm_file *file_priv);
2846 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2847 struct drm_file *file_priv);
2848 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2849 struct drm_file *file_priv);
2850 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2851 struct drm_file *file_priv);
2852 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2853 struct drm_file *file_priv);
2854 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2855 struct drm_file *file_priv);
2856 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2857 struct drm_file *file_priv);
2858 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2859 struct drm_i915_gem_request *req);
2860 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2861 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2862 struct drm_i915_gem_execbuffer2 *args,
2863 struct list_head *vmas);
2864 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2865 struct drm_file *file_priv);
2866 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2867 struct drm_file *file_priv);
2868 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2869 struct drm_file *file_priv);
2870 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2871 struct drm_file *file);
2872 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2873 struct drm_file *file);
2874 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2875 struct drm_file *file_priv);
2876 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2877 struct drm_file *file_priv);
2878 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2879 struct drm_file *file_priv);
2880 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2881 struct drm_file *file_priv);
2882 int i915_gem_init_userptr(struct drm_device *dev);
2883 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2884 struct drm_file *file);
2885 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2886 struct drm_file *file_priv);
2887 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2888 struct drm_file *file_priv);
2889 void i915_gem_load_init(struct drm_device *dev);
2890 void i915_gem_load_cleanup(struct drm_device *dev);
2891 void *i915_gem_object_alloc(struct drm_device *dev);
2892 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2893 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2894 const struct drm_i915_gem_object_ops *ops);
2895 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2897 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2898 struct drm_device *dev, const void *data, size_t size);
2899 void i915_gem_free_object(struct drm_gem_object *obj);
2900 void i915_gem_vma_destroy(struct i915_vma *vma);
2902 /* Flags used by pin/bind&friends. */
2903 #define PIN_MAPPABLE (1<<0)
2904 #define PIN_NONBLOCK (1<<1)
2905 #define PIN_GLOBAL (1<<2)
2906 #define PIN_OFFSET_BIAS (1<<3)
2907 #define PIN_USER (1<<4)
2908 #define PIN_UPDATE (1<<5)
2909 #define PIN_ZONE_4G (1<<6)
2910 #define PIN_HIGH (1<<7)
2911 #define PIN_OFFSET_FIXED (1<<8)
2912 #define PIN_OFFSET_MASK (~4095)
2914 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2915 struct i915_address_space *vm,
2919 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2920 const struct i915_ggtt_view *view,
2924 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2926 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2927 int __must_check i915_vma_unbind(struct i915_vma *vma);
2929 * BEWARE: Do not use the function below unless you can _absolutely_
2930 * _guarantee_ VMA in question is _not in use_ anywhere.
2932 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2933 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2934 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2935 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2937 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2938 int *needs_clflush);
2940 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2942 static inline int __sg_page_count(struct scatterlist *sg)
2944 return sg->length >> PAGE_SHIFT;
2948 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
2950 static inline struct page *
2951 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2953 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2956 if (n < obj->get_page.last) {
2957 obj->get_page.sg = obj->pages->sgl;
2958 obj->get_page.last = 0;
2961 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2962 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2963 if (unlikely(sg_is_chain(obj->get_page.sg)))
2964 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2967 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2970 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2972 BUG_ON(obj->pages == NULL);
2973 obj->pages_pin_count++;
2975 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2977 BUG_ON(obj->pages_pin_count == 0);
2978 obj->pages_pin_count--;
2981 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2982 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2983 struct intel_engine_cs *to,
2984 struct drm_i915_gem_request **to_req);
2985 void i915_vma_move_to_active(struct i915_vma *vma,
2986 struct drm_i915_gem_request *req);
2987 int i915_gem_dumb_create(struct drm_file *file_priv,
2988 struct drm_device *dev,
2989 struct drm_mode_create_dumb *args);
2990 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2991 uint32_t handle, uint64_t *offset);
2993 * Returns true if seq1 is later than seq2.
2996 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2998 return (int32_t)(seq1 - seq2) >= 0;
3001 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
3002 bool lazy_coherency)
3004 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
3005 return i915_seqno_passed(seqno, req->previous_seqno);
3008 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
3009 bool lazy_coherency)
3011 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
3012 return i915_seqno_passed(seqno, req->seqno);
3015 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
3016 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3018 struct drm_i915_gem_request *
3019 i915_gem_find_active_request(struct intel_engine_cs *ring);
3021 bool i915_gem_retire_requests(struct drm_device *dev);
3022 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
3023 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
3024 bool interruptible);
3026 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3028 return unlikely(atomic_read(&error->reset_counter)
3029 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3032 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3034 return atomic_read(&error->reset_counter) & I915_WEDGED;
3037 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3039 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
3042 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3044 return dev_priv->gpu_error.stop_rings == 0 ||
3045 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3048 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3050 return dev_priv->gpu_error.stop_rings == 0 ||
3051 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3054 void i915_gem_reset(struct drm_device *dev);
3055 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3056 int __must_check i915_gem_init(struct drm_device *dev);
3057 int i915_gem_init_rings(struct drm_device *dev);
3058 int __must_check i915_gem_init_hw(struct drm_device *dev);
3059 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3060 void i915_gem_init_swizzling(struct drm_device *dev);
3061 void i915_gem_cleanup_engines(struct drm_device *dev);
3062 int __must_check i915_gpu_idle(struct drm_device *dev);
3063 int __must_check i915_gem_suspend(struct drm_device *dev);
3064 void __i915_add_request(struct drm_i915_gem_request *req,
3065 struct drm_i915_gem_object *batch_obj,
3067 #define i915_add_request(req) \
3068 __i915_add_request(req, NULL, true)
3069 #define i915_add_request_no_flush(req) \
3070 __i915_add_request(req, NULL, false)
3071 int __i915_wait_request(struct drm_i915_gem_request *req,
3072 unsigned reset_counter,
3075 struct intel_rps_client *rps);
3076 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3077 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3079 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3082 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3085 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3087 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3089 const struct i915_ggtt_view *view);
3090 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3091 const struct i915_ggtt_view *view);
3092 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3094 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3095 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3098 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3100 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3101 int tiling_mode, bool fenced);
3103 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3104 enum i915_cache_level cache_level);
3106 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3107 struct dma_buf *dma_buf);
3109 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3110 struct drm_gem_object *gem_obj, int flags);
3112 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3113 const struct i915_ggtt_view *view);
3114 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3115 struct i915_address_space *vm);
3117 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3119 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3122 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3123 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3124 const struct i915_ggtt_view *view);
3125 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3126 struct i915_address_space *vm);
3128 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3129 struct i915_address_space *vm);
3131 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3132 struct i915_address_space *vm);
3134 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3135 const struct i915_ggtt_view *view);
3138 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3139 struct i915_address_space *vm);
3141 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3142 const struct i915_ggtt_view *view);
3144 static inline struct i915_vma *
3145 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3147 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3149 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3151 /* Some GGTT VM helpers */
3152 #define i915_obj_to_ggtt(obj) \
3153 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3154 static inline bool i915_is_ggtt(struct i915_address_space *vm)
3156 struct i915_address_space *ggtt =
3157 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
3161 static inline struct i915_hw_ppgtt *
3162 i915_vm_to_ppgtt(struct i915_address_space *vm)
3164 WARN_ON(i915_is_ggtt(vm));
3166 return container_of(vm, struct i915_hw_ppgtt, base);
3170 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3172 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3175 static inline unsigned long
3176 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3178 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3181 static inline int __must_check
3182 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3186 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3187 alignment, flags | PIN_GLOBAL);
3191 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3193 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3196 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3197 const struct i915_ggtt_view *view);
3199 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3201 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3204 /* i915_gem_fence.c */
3205 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3206 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3208 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3209 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3211 void i915_gem_restore_fences(struct drm_device *dev);
3213 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3214 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3215 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3217 /* i915_gem_context.c */
3218 int __must_check i915_gem_context_init(struct drm_device *dev);
3219 void i915_gem_context_fini(struct drm_device *dev);
3220 void i915_gem_context_reset(struct drm_device *dev);
3221 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3222 int i915_gem_context_enable(struct drm_i915_gem_request *req);
3223 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3224 int i915_switch_context(struct drm_i915_gem_request *req);
3225 struct intel_context *
3226 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3227 void i915_gem_context_free(struct kref *ctx_ref);
3228 struct drm_i915_gem_object *
3229 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3230 static inline void i915_gem_context_reference(struct intel_context *ctx)
3232 kref_get(&ctx->ref);
3235 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3237 kref_put(&ctx->ref, i915_gem_context_free);
3240 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3242 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3245 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3246 struct drm_file *file);
3247 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3248 struct drm_file *file);
3249 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3250 struct drm_file *file_priv);
3251 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3252 struct drm_file *file_priv);
3254 /* i915_gem_evict.c */
3255 int __must_check i915_gem_evict_something(struct drm_device *dev,
3256 struct i915_address_space *vm,
3259 unsigned cache_level,
3260 unsigned long start,
3263 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3264 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3266 /* belongs in i915_gem_gtt.h */
3267 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3269 if (INTEL_INFO(dev)->gen < 6)
3270 intel_gtt_chipset_flush();
3273 /* i915_gem_stolen.c */
3274 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3275 struct drm_mm_node *node, u64 size,
3276 unsigned alignment);
3277 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3278 struct drm_mm_node *node, u64 size,
3279 unsigned alignment, u64 start,
3281 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3282 struct drm_mm_node *node);
3283 int i915_gem_init_stolen(struct drm_device *dev);
3284 void i915_gem_cleanup_stolen(struct drm_device *dev);
3285 struct drm_i915_gem_object *
3286 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3287 struct drm_i915_gem_object *
3288 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3293 /* i915_gem_shrinker.c */
3294 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3295 unsigned long target,
3297 #define I915_SHRINK_PURGEABLE 0x1
3298 #define I915_SHRINK_UNBOUND 0x2
3299 #define I915_SHRINK_BOUND 0x4
3300 #define I915_SHRINK_ACTIVE 0x8
3301 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3302 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3303 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3306 /* i915_gem_tiling.c */
3307 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3309 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3311 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3312 obj->tiling_mode != I915_TILING_NONE;
3315 /* i915_gem_debug.c */
3317 int i915_verify_lists(struct drm_device *dev);
3319 #define i915_verify_lists(dev) 0
3322 /* i915_debugfs.c */
3323 int i915_debugfs_init(struct drm_minor *minor);
3324 void i915_debugfs_cleanup(struct drm_minor *minor);
3325 #ifdef CONFIG_DEBUG_FS
3326 int i915_debugfs_connector_add(struct drm_connector *connector);
3327 void intel_display_crc_init(struct drm_device *dev);
3329 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3331 static inline void intel_display_crc_init(struct drm_device *dev) {}
3334 /* i915_gpu_error.c */
3336 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3337 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3338 const struct i915_error_state_file_priv *error);
3339 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3340 struct drm_i915_private *i915,
3341 size_t count, loff_t pos);
3342 static inline void i915_error_state_buf_release(
3343 struct drm_i915_error_state_buf *eb)
3347 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3348 const char *error_msg);
3349 void i915_error_state_get(struct drm_device *dev,
3350 struct i915_error_state_file_priv *error_priv);
3351 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3352 void i915_destroy_error_state(struct drm_device *dev);
3354 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3355 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3357 /* i915_cmd_parser.c */
3358 int i915_cmd_parser_get_version(void);
3359 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3360 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3361 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3362 int i915_parse_cmds(struct intel_engine_cs *ring,
3363 struct drm_i915_gem_object *batch_obj,
3364 struct drm_i915_gem_object *shadow_batch_obj,
3365 u32 batch_start_offset,
3369 /* i915_suspend.c */
3370 extern int i915_save_state(struct drm_device *dev);
3371 extern int i915_restore_state(struct drm_device *dev);
3374 void i915_setup_sysfs(struct drm_device *dev_priv);
3375 void i915_teardown_sysfs(struct drm_device *dev_priv);
3378 extern int intel_setup_gmbus(struct drm_device *dev);
3379 extern void intel_teardown_gmbus(struct drm_device *dev);
3380 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3383 extern struct i2c_adapter *
3384 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3385 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3386 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3387 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3389 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3391 extern void intel_i2c_reset(struct drm_device *dev);
3394 int intel_bios_init(struct drm_i915_private *dev_priv);
3395 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3397 /* intel_opregion.c */
3399 extern int intel_opregion_setup(struct drm_device *dev);
3400 extern void intel_opregion_init(struct drm_device *dev);
3401 extern void intel_opregion_fini(struct drm_device *dev);
3402 extern void intel_opregion_asle_intr(struct drm_device *dev);
3403 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3405 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3408 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3409 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3410 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3411 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3413 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3418 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3426 extern void intel_register_dsm_handler(void);
3427 extern void intel_unregister_dsm_handler(void);
3429 static inline void intel_register_dsm_handler(void) { return; }
3430 static inline void intel_unregister_dsm_handler(void) { return; }
3431 #endif /* CONFIG_ACPI */
3434 extern void intel_modeset_init_hw(struct drm_device *dev);
3435 extern void intel_modeset_init(struct drm_device *dev);
3436 extern void intel_modeset_gem_init(struct drm_device *dev);
3437 extern void intel_modeset_cleanup(struct drm_device *dev);
3438 extern void intel_connector_unregister(struct intel_connector *);
3439 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3440 extern void intel_display_resume(struct drm_device *dev);
3441 extern void i915_redisable_vga(struct drm_device *dev);
3442 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3443 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3444 extern void intel_init_pch_refclk(struct drm_device *dev);
3445 extern void intel_set_rps(struct drm_device *dev, u8 val);
3446 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3448 extern void intel_detect_pch(struct drm_device *dev);
3449 extern int intel_enable_rc6(const struct drm_device *dev);
3451 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3452 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3453 struct drm_file *file);
3454 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3455 struct drm_file *file);
3458 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3459 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3460 struct intel_overlay_error_state *error);
3462 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3463 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3464 struct drm_device *dev,
3465 struct intel_display_error_state *error);
3467 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3468 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3470 /* intel_sideband.c */
3471 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3472 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3473 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3474 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3475 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3476 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3477 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3478 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3479 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3480 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3481 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3482 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3483 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3484 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3485 enum intel_sbi_destination destination);
3486 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3487 enum intel_sbi_destination destination);
3488 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3489 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3491 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3492 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3494 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3495 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3497 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3498 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3499 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3500 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3502 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3503 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3504 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3505 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3507 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3508 * will be implemented using 2 32-bit writes in an arbitrary order with
3509 * an arbitrary delay between them. This can cause the hardware to
3510 * act upon the intermediate value, possibly leading to corruption and
3511 * machine death. You have been warned.
3513 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3514 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3516 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3517 u32 upper, lower, old_upper, loop = 0; \
3518 upper = I915_READ(upper_reg); \
3520 old_upper = upper; \
3521 lower = I915_READ(lower_reg); \
3522 upper = I915_READ(upper_reg); \
3523 } while (upper != old_upper && loop++ < 2); \
3524 (u64)upper << 32 | lower; })
3526 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3527 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3529 #define __raw_read(x, s) \
3530 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3533 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3536 #define __raw_write(x, s) \
3537 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3538 i915_reg_t reg, uint##x##_t val) \
3540 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3555 /* These are untraced mmio-accessors that are only valid to be used inside
3556 * criticial sections inside IRQ handlers where forcewake is explicitly
3558 * Think twice, and think again, before using these.
3559 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3560 * intel_uncore_forcewake_irqunlock().
3562 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3563 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3564 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3566 /* "Broadcast RGB" property */
3567 #define INTEL_BROADCAST_RGB_AUTO 0
3568 #define INTEL_BROADCAST_RGB_FULL 1
3569 #define INTEL_BROADCAST_RGB_LIMITED 2
3571 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3573 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3574 return VLV_VGACNTRL;
3575 else if (INTEL_INFO(dev)->gen >= 5)
3576 return CPU_VGACNTRL;
3581 static inline void __user *to_user_ptr(u64 address)
3583 return (void __user *)(uintptr_t)address;
3586 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3588 unsigned long j = msecs_to_jiffies(m);
3590 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3593 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3595 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3598 static inline unsigned long
3599 timespec_to_jiffies_timeout(const struct timespec *value)
3601 unsigned long j = timespec_to_jiffies(value);
3603 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3607 * If you need to wait X milliseconds between events A and B, but event B
3608 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3609 * when event A happened, then just before event B you call this function and
3610 * pass the timestamp as the first argument, and X as the second argument.
3613 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3615 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3618 * Don't re-read the value of "jiffies" every time since it may change
3619 * behind our back and break the math.
3621 tmp_jiffies = jiffies;
3622 target_jiffies = timestamp_jiffies +
3623 msecs_to_jiffies_timeout(to_wait_ms);
3625 if (time_after(target_jiffies, tmp_jiffies)) {
3626 remaining_jiffies = target_jiffies - tmp_jiffies;
3627 while (remaining_jiffies)
3629 schedule_timeout_uninterruptible(remaining_jiffies);
3633 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3634 struct drm_i915_gem_request *req)
3636 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3637 i915_gem_request_assign(&ring->trace_irq_req, req);