1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
54 /* General customization:
57 #define DRIVER_NAME "i915"
58 #define DRIVER_DESC "Intel Graphics"
59 #define DRIVER_DATE "20150522"
62 /* Many gcc seem to no see through this and fall over :( */
64 #define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
74 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
76 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
77 (long) (x), __func__);
79 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
80 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
81 * which may not necessarily be a user visible problem. This will either
82 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
83 * enable distros and users to tailor their preferred amount of i915 abrt
86 #define I915_STATE_WARN(condition, format...) ({ \
87 int __ret_warn_on = !!(condition); \
88 if (unlikely(__ret_warn_on)) { \
89 if (i915.verbose_state_checks) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) { \
100 if (i915.verbose_state_checks) \
101 WARN(1, "WARN_ON(" #condition ")\n"); \
103 DRM_ERROR("WARN_ON(" #condition ")\n"); \
105 unlikely(__ret_warn_on); \
114 I915_MAX_PIPES = _PIPE_EDP
116 #define pipe_name(p) ((p) + 'A')
125 #define transcoder_name(t) ((t) + 'A')
128 * This is the maximum (across all platforms) number of planes (primary +
129 * sprites) that can be active at the same time on one pipe.
131 * This value doesn't count the cursor plane.
133 #define I915_MAX_PLANES 4
140 #define plane_name(p) ((p) + 'A')
142 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
152 #define port_name(p) ((p) + 'A')
154 #define I915_NUM_PHYS_VLV 2
166 enum intel_display_power_domain {
170 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
171 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
172 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
173 POWER_DOMAIN_TRANSCODER_A,
174 POWER_DOMAIN_TRANSCODER_B,
175 POWER_DOMAIN_TRANSCODER_C,
176 POWER_DOMAIN_TRANSCODER_EDP,
177 POWER_DOMAIN_PORT_DDI_A_2_LANES,
178 POWER_DOMAIN_PORT_DDI_A_4_LANES,
179 POWER_DOMAIN_PORT_DDI_B_2_LANES,
180 POWER_DOMAIN_PORT_DDI_B_4_LANES,
181 POWER_DOMAIN_PORT_DDI_C_2_LANES,
182 POWER_DOMAIN_PORT_DDI_C_4_LANES,
183 POWER_DOMAIN_PORT_DDI_D_2_LANES,
184 POWER_DOMAIN_PORT_DDI_D_4_LANES,
185 POWER_DOMAIN_PORT_DSI,
186 POWER_DOMAIN_PORT_CRT,
187 POWER_DOMAIN_PORT_OTHER,
200 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
201 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
202 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
203 #define POWER_DOMAIN_TRANSCODER(tran) \
204 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
205 (tran) + POWER_DOMAIN_TRANSCODER_A)
209 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
210 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
220 #define I915_GEM_GPU_DOMAINS \
221 (I915_GEM_DOMAIN_RENDER | \
222 I915_GEM_DOMAIN_SAMPLER | \
223 I915_GEM_DOMAIN_COMMAND | \
224 I915_GEM_DOMAIN_INSTRUCTION | \
225 I915_GEM_DOMAIN_VERTEX)
227 #define for_each_pipe(__dev_priv, __p) \
228 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
229 #define for_each_plane(__dev_priv, __pipe, __p) \
231 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
233 #define for_each_sprite(__dev_priv, __p, __s) \
235 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
238 #define for_each_crtc(dev, crtc) \
239 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
241 #define for_each_intel_plane(dev, intel_plane) \
242 list_for_each_entry(intel_plane, \
243 &dev->mode_config.plane_list, \
246 #define for_each_intel_crtc(dev, intel_crtc) \
247 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
249 #define for_each_intel_encoder(dev, intel_encoder) \
250 list_for_each_entry(intel_encoder, \
251 &(dev)->mode_config.encoder_list, \
254 #define for_each_intel_connector(dev, intel_connector) \
255 list_for_each_entry(intel_connector, \
256 &dev->mode_config.connector_list, \
259 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
260 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
261 if ((intel_encoder)->base.crtc == (__crtc))
263 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
264 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
265 if ((intel_connector)->base.encoder == (__encoder))
267 #define for_each_power_domain(domain, mask) \
268 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
269 if ((1 << (domain)) & (mask))
271 struct drm_i915_private;
272 struct i915_mm_struct;
273 struct i915_mmu_object;
275 struct drm_i915_file_private {
276 struct drm_i915_private *dev_priv;
277 struct drm_file *file;
281 struct list_head request_list;
282 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
283 * chosen to prevent the CPU getting more than a frame ahead of the GPU
284 * (when using lax throttling for the frontbuffer). We also use it to
285 * offer free GPU waitboosts for severely congested workloads.
287 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
289 struct idr context_idr;
291 struct intel_rps_client {
292 struct list_head link;
296 struct intel_engine_cs *bsd_ring;
300 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
301 /* real shared dpll ids must be >= 0 */
302 DPLL_ID_PCH_PLL_A = 0,
303 DPLL_ID_PCH_PLL_B = 1,
308 DPLL_ID_SKL_DPLL1 = 0,
309 DPLL_ID_SKL_DPLL2 = 1,
310 DPLL_ID_SKL_DPLL3 = 2,
312 #define I915_NUM_PLLS 3
314 struct intel_dpll_hw_state {
326 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
327 * lower part of ctrl1 and they get shifted into position when writing
328 * the register. This allows us to easily compare the state to share
332 /* HDMI only, 0 when used for DP */
333 uint32_t cfgcr1, cfgcr2;
336 uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pll10, pcsdw12;
339 struct intel_shared_dpll_config {
340 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
341 struct intel_dpll_hw_state hw_state;
344 struct intel_shared_dpll {
345 struct intel_shared_dpll_config config;
346 struct intel_shared_dpll_config *new_config;
348 int active; /* count of number of active CRTCs (i.e. DPMS on) */
349 bool on; /* is the PLL actually active? Disabled during modeset */
351 /* should match the index in the dev_priv->shared_dplls array */
352 enum intel_dpll_id id;
353 /* The mode_set hook is optional and should be used together with the
354 * intel_prepare_shared_dpll function. */
355 void (*mode_set)(struct drm_i915_private *dev_priv,
356 struct intel_shared_dpll *pll);
357 void (*enable)(struct drm_i915_private *dev_priv,
358 struct intel_shared_dpll *pll);
359 void (*disable)(struct drm_i915_private *dev_priv,
360 struct intel_shared_dpll *pll);
361 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
362 struct intel_shared_dpll *pll,
363 struct intel_dpll_hw_state *hw_state);
371 /* Used by dp and fdi links */
372 struct intel_link_m_n {
380 void intel_link_compute_m_n(int bpp, int nlanes,
381 int pixel_clock, int link_clock,
382 struct intel_link_m_n *m_n);
384 /* Interface history:
387 * 1.2: Add Power Management
388 * 1.3: Add vblank support
389 * 1.4: Fix cmdbuffer path, add heap destroy
390 * 1.5: Add vblank pipe configuration
391 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
392 * - Support vertical blank on secondary display pipe
394 #define DRIVER_MAJOR 1
395 #define DRIVER_MINOR 6
396 #define DRIVER_PATCHLEVEL 0
398 #define WATCH_LISTS 0
400 struct opregion_header;
401 struct opregion_acpi;
402 struct opregion_swsci;
403 struct opregion_asle;
405 struct intel_opregion {
406 struct opregion_header __iomem *header;
407 struct opregion_acpi __iomem *acpi;
408 struct opregion_swsci __iomem *swsci;
409 u32 swsci_gbda_sub_functions;
410 u32 swsci_sbcb_sub_functions;
411 struct opregion_asle __iomem *asle;
413 u32 __iomem *lid_state;
414 struct work_struct asle_work;
416 #define OPREGION_SIZE (8*1024)
418 struct intel_overlay;
419 struct intel_overlay_error_state;
421 #define I915_FENCE_REG_NONE -1
422 #define I915_MAX_NUM_FENCES 32
423 /* 32 fences + sign bit for FENCE_REG_NONE */
424 #define I915_MAX_NUM_FENCE_BITS 6
426 struct drm_i915_fence_reg {
427 struct list_head lru_list;
428 struct drm_i915_gem_object *obj;
432 struct sdvo_device_mapping {
441 struct intel_display_error_state;
443 struct drm_i915_error_state {
451 /* Generic register state */
459 u32 error; /* gen6+ */
460 u32 err_int; /* gen7 */
461 u32 fault_data0; /* gen8, gen9 */
462 u32 fault_data1; /* gen8, gen9 */
468 u32 extra_instdone[I915_NUM_INSTDONE_REG];
469 u64 fence[I915_MAX_NUM_FENCES];
470 struct intel_overlay_error_state *overlay;
471 struct intel_display_error_state *display;
472 struct drm_i915_error_object *semaphore_obj;
474 struct drm_i915_error_ring {
476 /* Software tracked state */
479 enum intel_ring_hangcheck_action hangcheck_action;
482 /* our own tracking of ring head and tail */
486 u32 semaphore_seqno[I915_NUM_RINGS - 1];
505 u32 rc_psmi; /* sleep state */
506 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
508 struct drm_i915_error_object {
512 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
514 struct drm_i915_error_request {
529 char comm[TASK_COMM_LEN];
530 } ring[I915_NUM_RINGS];
532 struct drm_i915_error_buffer {
535 u32 rseqno[I915_NUM_RINGS], wseqno;
539 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
547 } **active_bo, **pinned_bo;
549 u32 *active_bo_count, *pinned_bo_count;
553 struct intel_connector;
554 struct intel_encoder;
555 struct intel_crtc_state;
556 struct intel_initial_plane_config;
561 struct drm_i915_display_funcs {
562 bool (*fbc_enabled)(struct drm_device *dev);
563 void (*enable_fbc)(struct drm_crtc *crtc);
564 void (*disable_fbc)(struct drm_device *dev);
565 int (*get_display_clock_speed)(struct drm_device *dev);
566 int (*get_fifo_size)(struct drm_device *dev, int plane);
568 * find_dpll() - Find the best values for the PLL
569 * @limit: limits for the PLL
570 * @crtc: current CRTC
571 * @target: target frequency in kHz
572 * @refclk: reference clock frequency in kHz
573 * @match_clock: if provided, @best_clock P divider must
574 * match the P divider from @match_clock
575 * used for LVDS downclocking
576 * @best_clock: best PLL values found
578 * Returns true on success, false on failure.
580 bool (*find_dpll)(const struct intel_limit *limit,
581 struct intel_crtc_state *crtc_state,
582 int target, int refclk,
583 struct dpll *match_clock,
584 struct dpll *best_clock);
585 void (*update_wm)(struct drm_crtc *crtc);
586 void (*update_sprite_wm)(struct drm_plane *plane,
587 struct drm_crtc *crtc,
588 uint32_t sprite_width, uint32_t sprite_height,
589 int pixel_size, bool enable, bool scaled);
590 void (*modeset_global_resources)(struct drm_atomic_state *state);
591 /* Returns the active state of the crtc, and if the crtc is active,
592 * fills out the pipe-config with the hw state. */
593 bool (*get_pipe_config)(struct intel_crtc *,
594 struct intel_crtc_state *);
595 void (*get_initial_plane_config)(struct intel_crtc *,
596 struct intel_initial_plane_config *);
597 int (*crtc_compute_clock)(struct intel_crtc *crtc,
598 struct intel_crtc_state *crtc_state);
599 void (*crtc_enable)(struct drm_crtc *crtc);
600 void (*crtc_disable)(struct drm_crtc *crtc);
601 void (*off)(struct drm_crtc *crtc);
602 void (*audio_codec_enable)(struct drm_connector *connector,
603 struct intel_encoder *encoder,
604 struct drm_display_mode *mode);
605 void (*audio_codec_disable)(struct intel_encoder *encoder);
606 void (*fdi_link_train)(struct drm_crtc *crtc);
607 void (*init_clock_gating)(struct drm_device *dev);
608 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
609 struct drm_framebuffer *fb,
610 struct drm_i915_gem_object *obj,
611 struct intel_engine_cs *ring,
613 void (*update_primary_plane)(struct drm_crtc *crtc,
614 struct drm_framebuffer *fb,
616 void (*hpd_irq_setup)(struct drm_device *dev);
617 /* clock updates for mode set */
619 /* render clock increase/decrease */
620 /* display clock increase/decrease */
621 /* pll clock increase/decrease */
623 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
624 uint32_t (*get_backlight)(struct intel_connector *connector);
625 void (*set_backlight)(struct intel_connector *connector,
627 void (*disable_backlight)(struct intel_connector *connector);
628 void (*enable_backlight)(struct intel_connector *connector);
631 enum forcewake_domain_id {
632 FW_DOMAIN_ID_RENDER = 0,
633 FW_DOMAIN_ID_BLITTER,
639 enum forcewake_domains {
640 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
641 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
642 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
643 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
648 struct intel_uncore_funcs {
649 void (*force_wake_get)(struct drm_i915_private *dev_priv,
650 enum forcewake_domains domains);
651 void (*force_wake_put)(struct drm_i915_private *dev_priv,
652 enum forcewake_domains domains);
654 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
655 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
656 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
657 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
659 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
660 uint8_t val, bool trace);
661 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
662 uint16_t val, bool trace);
663 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
664 uint32_t val, bool trace);
665 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
666 uint64_t val, bool trace);
669 struct intel_uncore {
670 spinlock_t lock; /** lock is also taken in irq contexts. */
672 struct intel_uncore_funcs funcs;
675 enum forcewake_domains fw_domains;
677 struct intel_uncore_forcewake_domain {
678 struct drm_i915_private *i915;
679 enum forcewake_domain_id id;
681 struct timer_list timer;
688 } fw_domain[FW_DOMAIN_ID_COUNT];
691 /* Iterate over initialised fw domains */
692 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
693 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
694 (i__) < FW_DOMAIN_ID_COUNT; \
695 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
696 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
698 #define for_each_fw_domain(domain__, dev_priv__, i__) \
699 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
702 FW_UNINITIALIZED = 0,
710 uint32_t dmc_fw_size;
712 uint32_t mmioaddr[8];
713 uint32_t mmiodata[8];
714 enum csr_state state;
717 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
718 func(is_mobile) sep \
721 func(is_i945gm) sep \
723 func(need_gfx_hws) sep \
725 func(is_pineview) sep \
726 func(is_broadwater) sep \
727 func(is_crestline) sep \
728 func(is_ivybridge) sep \
729 func(is_valleyview) sep \
730 func(is_haswell) sep \
731 func(is_skylake) sep \
732 func(is_preliminary) sep \
734 func(has_pipe_cxsr) sep \
735 func(has_hotplug) sep \
736 func(cursor_needs_physical) sep \
737 func(has_overlay) sep \
738 func(overlay_needs_physical) sep \
739 func(supports_tv) sep \
744 #define DEFINE_FLAG(name) u8 name:1
745 #define SEP_SEMICOLON ;
747 struct intel_device_info {
748 u32 display_mmio_offset;
751 u8 num_sprites[I915_MAX_PIPES];
753 u8 ring_mask; /* Rings supported by the HW */
754 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
755 /* Register offsets for the various display pipes and transcoders */
756 int pipe_offsets[I915_MAX_TRANSCODERS];
757 int trans_offsets[I915_MAX_TRANSCODERS];
758 int palette_offsets[I915_MAX_PIPES];
759 int cursor_offsets[I915_MAX_PIPES];
761 /* Slice/subslice/EU info */
764 u8 subslice_per_slice;
767 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
770 u8 has_subslice_pg:1;
777 enum i915_cache_level {
779 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
780 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
781 caches, eg sampler/render caches, and the
782 large Last-Level-Cache. LLC is coherent with
783 the CPU, but L3 is only visible to the GPU. */
784 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
787 struct i915_ctx_hang_stats {
788 /* This context had batch pending when hang was declared */
789 unsigned batch_pending;
791 /* This context had batch active when hang was declared */
792 unsigned batch_active;
794 /* Time when this context was last blamed for a GPU reset */
795 unsigned long guilty_ts;
797 /* If the contexts causes a second GPU hang within this time,
798 * it is permanently banned from submitting any more work.
800 unsigned long ban_period_seconds;
802 /* This context is banned to submit more work */
806 /* This must match up with the value previously used for execbuf2.rsvd1. */
807 #define DEFAULT_CONTEXT_HANDLE 0
809 * struct intel_context - as the name implies, represents a context.
810 * @ref: reference count.
811 * @user_handle: userspace tracking identity for this context.
812 * @remap_slice: l3 row remapping information.
813 * @file_priv: filp associated with this context (NULL for global default
815 * @hang_stats: information about the role of this context in possible GPU
817 * @ppgtt: virtual memory space used by this context.
818 * @legacy_hw_ctx: render context backing object and whether it is correctly
819 * initialized (legacy ring submission mechanism only).
820 * @link: link in the global list of contexts.
822 * Contexts are memory images used by the hardware to store copies of their
825 struct intel_context {
829 struct drm_i915_file_private *file_priv;
830 struct i915_ctx_hang_stats hang_stats;
831 struct i915_hw_ppgtt *ppgtt;
833 /* Legacy ring buffer submission */
835 struct drm_i915_gem_object *rcs_state;
840 bool rcs_initialized;
842 struct drm_i915_gem_object *state;
843 struct intel_ringbuffer *ringbuf;
845 } engine[I915_NUM_RINGS];
847 struct list_head link;
858 unsigned long uncompressed_size;
861 unsigned int possible_framebuffer_bits;
862 unsigned int busy_bits;
863 struct intel_crtc *crtc;
866 struct drm_mm_node compressed_fb;
867 struct drm_mm_node *compressed_llb;
871 /* Tracks whether the HW is actually enabled, not whether the feature is
875 struct intel_fbc_work {
876 struct delayed_work work;
877 struct drm_crtc *crtc;
878 struct drm_framebuffer *fb;
882 FBC_OK, /* FBC is enabled */
883 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
884 FBC_NO_OUTPUT, /* no outputs enabled to compress */
885 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
886 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
887 FBC_MODE_TOO_LARGE, /* mode too large for compression */
888 FBC_BAD_PLANE, /* fbc not supported on plane */
889 FBC_NOT_TILED, /* buffer not tiled */
890 FBC_MULTIPLE_PIPES, /* more than one pipe active */
892 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
897 * HIGH_RR is the highest eDP panel refresh rate read from EDID
898 * LOW_RR is the lowest eDP panel refresh rate found from EDID
899 * parsing for same resolution.
901 enum drrs_refresh_rate_type {
904 DRRS_MAX_RR, /* RR count */
907 enum drrs_support_type {
908 DRRS_NOT_SUPPORTED = 0,
909 STATIC_DRRS_SUPPORT = 1,
910 SEAMLESS_DRRS_SUPPORT = 2
916 struct delayed_work work;
918 unsigned busy_frontbuffer_bits;
919 enum drrs_refresh_rate_type refresh_rate_type;
920 enum drrs_support_type type;
927 struct intel_dp *enabled;
929 struct delayed_work work;
930 unsigned busy_frontbuffer_bits;
936 PCH_NONE = 0, /* No PCH present */
937 PCH_IBX, /* Ibexpeak PCH */
938 PCH_CPT, /* Cougarpoint PCH */
939 PCH_LPT, /* Lynxpoint PCH */
940 PCH_SPT, /* Sunrisepoint PCH */
944 enum intel_sbi_destination {
949 #define QUIRK_PIPEA_FORCE (1<<0)
950 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
951 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
952 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
953 #define QUIRK_PIPEB_FORCE (1<<4)
954 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
957 struct intel_fbc_work;
960 struct i2c_adapter adapter;
964 struct i2c_algo_bit_data bit_algo;
965 struct drm_i915_private *dev_priv;
968 struct i915_suspend_saved_registers {
971 u32 savePP_ON_DELAYS;
972 u32 savePP_OFF_DELAYS;
978 u32 saveCACHE_MODE_0;
979 u32 saveMI_ARB_STATE;
983 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
984 u32 savePCH_PORT_HOTPLUG;
988 struct vlv_s0ix_state {
995 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
996 u32 media_max_req_count;
997 u32 gfx_max_req_count;
1023 u32 rp_down_timeout;
1029 /* Display 1 CZ domain */
1034 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1036 /* GT SA CZ domain */
1043 /* Display 2 CZ domain */
1047 u32 clock_gate_dis2;
1050 struct intel_rps_ei {
1056 struct intel_gen6_power_mgmt {
1058 * work, interrupts_enabled and pm_iir are protected by
1059 * dev_priv->irq_lock
1061 struct work_struct work;
1062 bool interrupts_enabled;
1065 /* Frequencies are stored in potentially platform dependent multiples.
1066 * In other words, *_freq needs to be multiplied by X to be interesting.
1067 * Soft limits are those which are used for the dynamic reclocking done
1068 * by the driver (raise frequencies under heavy loads, and lower for
1069 * lighter loads). Hard limits are those imposed by the hardware.
1071 * A distinction is made for overclocking, which is never enabled by
1072 * default, and is considered to be above the hard limit if it's
1075 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1076 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1077 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1078 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1079 u8 min_freq; /* AKA RPn. Minimum frequency */
1080 u8 idle_freq; /* Frequency to request when we are idle */
1081 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1082 u8 rp1_freq; /* "less than" RP0 power/freqency */
1083 u8 rp0_freq; /* Non-overclocked max frequency. */
1086 u8 up_threshold; /* Current %busy required to uplock */
1087 u8 down_threshold; /* Current %busy required to downclock */
1090 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1092 spinlock_t client_lock;
1093 struct list_head clients;
1097 struct delayed_work delayed_resume_work;
1100 struct intel_rps_client semaphores, mmioflips;
1102 /* manual wa residency calculations */
1103 struct intel_rps_ei up_ei, down_ei;
1106 * Protects RPS/RC6 register access and PCU communication.
1107 * Must be taken after struct_mutex if nested. Note that
1108 * this lock may be held for long periods of time when
1109 * talking to hw - so only take it when talking to hw!
1111 struct mutex hw_lock;
1114 /* defined intel_pm.c */
1115 extern spinlock_t mchdev_lock;
1117 struct intel_ilk_power_mgmt {
1125 unsigned long last_time1;
1126 unsigned long chipset_power;
1129 unsigned long gfx_power;
1136 struct drm_i915_private;
1137 struct i915_power_well;
1139 struct i915_power_well_ops {
1141 * Synchronize the well's hw state to match the current sw state, for
1142 * example enable/disable it based on the current refcount. Called
1143 * during driver init and resume time, possibly after first calling
1144 * the enable/disable handlers.
1146 void (*sync_hw)(struct drm_i915_private *dev_priv,
1147 struct i915_power_well *power_well);
1149 * Enable the well and resources that depend on it (for example
1150 * interrupts located on the well). Called after the 0->1 refcount
1153 void (*enable)(struct drm_i915_private *dev_priv,
1154 struct i915_power_well *power_well);
1156 * Disable the well and resources that depend on it. Called after
1157 * the 1->0 refcount transition.
1159 void (*disable)(struct drm_i915_private *dev_priv,
1160 struct i915_power_well *power_well);
1161 /* Returns the hw enabled state. */
1162 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1163 struct i915_power_well *power_well);
1166 /* Power well structure for haswell */
1167 struct i915_power_well {
1170 /* power well enable/disable usage count */
1172 /* cached hw enabled state */
1174 unsigned long domains;
1176 const struct i915_power_well_ops *ops;
1179 struct i915_power_domains {
1181 * Power wells needed for initialization at driver init and suspend
1182 * time are on. They are kept on until after the first modeset.
1186 int power_well_count;
1189 int domain_use_count[POWER_DOMAIN_NUM];
1190 struct i915_power_well *power_wells;
1193 #define MAX_L3_SLICES 2
1194 struct intel_l3_parity {
1195 u32 *remap_info[MAX_L3_SLICES];
1196 struct work_struct error_work;
1200 struct i915_gem_mm {
1201 /** Memory allocator for GTT stolen memory */
1202 struct drm_mm stolen;
1203 /** List of all objects in gtt_space. Used to restore gtt
1204 * mappings on resume */
1205 struct list_head bound_list;
1207 * List of objects which are not bound to the GTT (thus
1208 * are idle and not used by the GPU) but still have
1209 * (presumably uncached) pages still attached.
1211 struct list_head unbound_list;
1213 /** Usable portion of the GTT for GEM */
1214 unsigned long stolen_base; /* limited to low memory (32-bit) */
1216 /** PPGTT used for aliasing the PPGTT with the GTT */
1217 struct i915_hw_ppgtt *aliasing_ppgtt;
1219 struct notifier_block oom_notifier;
1220 struct shrinker shrinker;
1221 bool shrinker_no_lock_stealing;
1223 /** LRU list of objects with fence regs on them. */
1224 struct list_head fence_list;
1227 * We leave the user IRQ off as much as possible,
1228 * but this means that requests will finish and never
1229 * be retired once the system goes idle. Set a timer to
1230 * fire periodically while the ring is running. When it
1231 * fires, go retire requests.
1233 struct delayed_work retire_work;
1236 * When we detect an idle GPU, we want to turn on
1237 * powersaving features. So once we see that there
1238 * are no more requests outstanding and no more
1239 * arrive within a small period of time, we fire
1240 * off the idle_work.
1242 struct delayed_work idle_work;
1245 * Are we in a non-interruptible section of code like
1251 * Is the GPU currently considered idle, or busy executing userspace
1252 * requests? Whilst idle, we attempt to power down the hardware and
1253 * display clocks. In order to reduce the effect on performance, there
1254 * is a slight delay before we do so.
1258 /* the indicator for dispatch video commands on two BSD rings */
1259 int bsd_ring_dispatch_index;
1261 /** Bit 6 swizzling required for X tiling */
1262 uint32_t bit_6_swizzle_x;
1263 /** Bit 6 swizzling required for Y tiling */
1264 uint32_t bit_6_swizzle_y;
1266 /* accounting, useful for userland debugging */
1267 spinlock_t object_stat_lock;
1268 size_t object_memory;
1272 struct drm_i915_error_state_buf {
1273 struct drm_i915_private *i915;
1282 struct i915_error_state_file_priv {
1283 struct drm_device *dev;
1284 struct drm_i915_error_state *error;
1287 struct i915_gpu_error {
1288 /* For hangcheck timer */
1289 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1290 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1291 /* Hang gpu twice in this window and your context gets banned */
1292 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1294 struct workqueue_struct *hangcheck_wq;
1295 struct delayed_work hangcheck_work;
1297 /* For reset and error_state handling. */
1299 /* Protected by the above dev->gpu_error.lock. */
1300 struct drm_i915_error_state *first_error;
1302 unsigned long missed_irq_rings;
1305 * State variable controlling the reset flow and count
1307 * This is a counter which gets incremented when reset is triggered,
1308 * and again when reset has been handled. So odd values (lowest bit set)
1309 * means that reset is in progress and even values that
1310 * (reset_counter >> 1):th reset was successfully completed.
1312 * If reset is not completed succesfully, the I915_WEDGE bit is
1313 * set meaning that hardware is terminally sour and there is no
1314 * recovery. All waiters on the reset_queue will be woken when
1317 * This counter is used by the wait_seqno code to notice that reset
1318 * event happened and it needs to restart the entire ioctl (since most
1319 * likely the seqno it waited for won't ever signal anytime soon).
1321 * This is important for lock-free wait paths, where no contended lock
1322 * naturally enforces the correct ordering between the bail-out of the
1323 * waiter and the gpu reset work code.
1325 atomic_t reset_counter;
1327 #define I915_RESET_IN_PROGRESS_FLAG 1
1328 #define I915_WEDGED (1 << 31)
1331 * Waitqueue to signal when the reset has completed. Used by clients
1332 * that wait for dev_priv->mm.wedged to settle.
1334 wait_queue_head_t reset_queue;
1336 /* Userspace knobs for gpu hang simulation;
1337 * combines both a ring mask, and extra flags
1340 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1341 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1343 /* For missed irq/seqno simulation. */
1344 unsigned int test_irq_rings;
1346 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1347 bool reload_in_reset;
1350 enum modeset_restore {
1351 MODESET_ON_LID_OPEN,
1356 struct ddi_vbt_port_info {
1358 * This is an index in the HDMI/DVI DDI buffer translation table.
1359 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1360 * populate this field.
1362 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1363 uint8_t hdmi_level_shift;
1365 uint8_t supports_dvi:1;
1366 uint8_t supports_hdmi:1;
1367 uint8_t supports_dp:1;
1370 enum psr_lines_to_wait {
1371 PSR_0_LINES_TO_WAIT = 0,
1373 PSR_4_LINES_TO_WAIT,
1377 struct intel_vbt_data {
1378 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1379 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1382 unsigned int int_tv_support:1;
1383 unsigned int lvds_dither:1;
1384 unsigned int lvds_vbt:1;
1385 unsigned int int_crt_support:1;
1386 unsigned int lvds_use_ssc:1;
1387 unsigned int display_clock_mode:1;
1388 unsigned int fdi_rx_polarity_inverted:1;
1389 unsigned int has_mipi:1;
1391 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1393 enum drrs_support_type drrs_type;
1398 int edp_preemphasis;
1400 bool edp_initialized;
1403 struct edp_power_seq edp_pps;
1407 bool require_aux_wakeup;
1409 enum psr_lines_to_wait lines_to_wait;
1410 int tp1_wakeup_time;
1411 int tp2_tp3_wakeup_time;
1417 bool active_low_pwm;
1418 u8 min_brightness; /* min_brightness/255 of max */
1425 struct mipi_config *config;
1426 struct mipi_pps_data *pps;
1430 u8 *sequence[MIPI_SEQ_MAX];
1436 union child_device_config *child_dev;
1438 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1441 enum intel_ddb_partitioning {
1443 INTEL_DDB_PART_5_6, /* IVB+ */
1446 struct intel_wm_level {
1454 struct ilk_wm_values {
1455 uint32_t wm_pipe[3];
1457 uint32_t wm_lp_spr[3];
1458 uint32_t wm_linetime[3];
1460 enum intel_ddb_partitioning partitioning;
1463 struct vlv_wm_values {
1482 struct skl_ddb_entry {
1483 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1486 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1488 return entry->end - entry->start;
1491 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1492 const struct skl_ddb_entry *e2)
1494 if (e1->start == e2->start && e1->end == e2->end)
1500 struct skl_ddb_allocation {
1501 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1502 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1503 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */
1504 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1507 struct skl_wm_values {
1508 bool dirty[I915_MAX_PIPES];
1509 struct skl_ddb_allocation ddb;
1510 uint32_t wm_linetime[I915_MAX_PIPES];
1511 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1512 uint32_t cursor[I915_MAX_PIPES][8];
1513 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1514 uint32_t cursor_trans[I915_MAX_PIPES];
1517 struct skl_wm_level {
1518 bool plane_en[I915_MAX_PLANES];
1520 uint16_t plane_res_b[I915_MAX_PLANES];
1521 uint8_t plane_res_l[I915_MAX_PLANES];
1522 uint16_t cursor_res_b;
1523 uint8_t cursor_res_l;
1527 * This struct helps tracking the state needed for runtime PM, which puts the
1528 * device in PCI D3 state. Notice that when this happens, nothing on the
1529 * graphics device works, even register access, so we don't get interrupts nor
1532 * Every piece of our code that needs to actually touch the hardware needs to
1533 * either call intel_runtime_pm_get or call intel_display_power_get with the
1534 * appropriate power domain.
1536 * Our driver uses the autosuspend delay feature, which means we'll only really
1537 * suspend if we stay with zero refcount for a certain amount of time. The
1538 * default value is currently very conservative (see intel_runtime_pm_enable), but
1539 * it can be changed with the standard runtime PM files from sysfs.
1541 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1542 * goes back to false exactly before we reenable the IRQs. We use this variable
1543 * to check if someone is trying to enable/disable IRQs while they're supposed
1544 * to be disabled. This shouldn't happen and we'll print some error messages in
1547 * For more, read the Documentation/power/runtime_pm.txt.
1549 struct i915_runtime_pm {
1554 enum intel_pipe_crc_source {
1555 INTEL_PIPE_CRC_SOURCE_NONE,
1556 INTEL_PIPE_CRC_SOURCE_PLANE1,
1557 INTEL_PIPE_CRC_SOURCE_PLANE2,
1558 INTEL_PIPE_CRC_SOURCE_PF,
1559 INTEL_PIPE_CRC_SOURCE_PIPE,
1560 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1561 INTEL_PIPE_CRC_SOURCE_TV,
1562 INTEL_PIPE_CRC_SOURCE_DP_B,
1563 INTEL_PIPE_CRC_SOURCE_DP_C,
1564 INTEL_PIPE_CRC_SOURCE_DP_D,
1565 INTEL_PIPE_CRC_SOURCE_AUTO,
1566 INTEL_PIPE_CRC_SOURCE_MAX,
1569 struct intel_pipe_crc_entry {
1574 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1575 struct intel_pipe_crc {
1577 bool opened; /* exclusive access to the result file */
1578 struct intel_pipe_crc_entry *entries;
1579 enum intel_pipe_crc_source source;
1581 wait_queue_head_t wq;
1584 struct i915_frontbuffer_tracking {
1588 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1595 struct i915_wa_reg {
1598 /* bitmask representing WA bits */
1602 #define I915_MAX_WA_REGS 16
1604 struct i915_workarounds {
1605 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1609 struct i915_virtual_gpu {
1613 struct drm_i915_private {
1614 struct drm_device *dev;
1615 struct kmem_cache *objects;
1616 struct kmem_cache *vmas;
1617 struct kmem_cache *requests;
1619 const struct intel_device_info info;
1621 int relative_constants_mode;
1625 struct intel_uncore uncore;
1627 struct i915_virtual_gpu vgpu;
1629 struct intel_csr csr;
1631 /* Display CSR-related protection */
1632 struct mutex csr_lock;
1634 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1636 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1637 * controller on different i2c buses. */
1638 struct mutex gmbus_mutex;
1641 * Base address of the gmbus and gpio block.
1643 uint32_t gpio_mmio_base;
1645 /* MMIO base address for MIPI regs */
1646 uint32_t mipi_mmio_base;
1648 wait_queue_head_t gmbus_wait_queue;
1650 struct pci_dev *bridge_dev;
1651 struct intel_engine_cs ring[I915_NUM_RINGS];
1652 struct drm_i915_gem_object *semaphore_obj;
1653 uint32_t last_seqno, next_seqno;
1655 struct drm_dma_handle *status_page_dmah;
1656 struct resource mch_res;
1658 /* protects the irq masks */
1659 spinlock_t irq_lock;
1661 /* protects the mmio flip data */
1662 spinlock_t mmio_flip_lock;
1664 bool display_irqs_enabled;
1666 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1667 struct pm_qos_request pm_qos;
1669 /* Sideband mailbox protection */
1670 struct mutex sb_lock;
1672 /** Cached value of IMR to avoid reads in updating the bitfield */
1675 u32 de_irq_mask[I915_MAX_PIPES];
1680 u32 pipestat_irq_mask[I915_MAX_PIPES];
1682 struct work_struct hotplug_work;
1684 unsigned long hpd_last_jiffies;
1689 HPD_MARK_DISABLED = 2
1691 } hpd_stats[HPD_NUM_PINS];
1693 struct delayed_work hotplug_reenable_work;
1695 struct i915_fbc fbc;
1696 struct i915_drrs drrs;
1697 struct intel_opregion opregion;
1698 struct intel_vbt_data vbt;
1700 bool preserve_bios_swizzle;
1703 struct intel_overlay *overlay;
1705 /* backlight registers and fields in struct intel_panel */
1706 struct mutex backlight_lock;
1709 bool no_aux_handshake;
1711 /* protects panel power sequencer state */
1712 struct mutex pps_mutex;
1714 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1715 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1716 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1718 unsigned int fsb_freq, mem_freq, is_ddr3;
1719 unsigned int skl_boot_cdclk;
1720 unsigned int cdclk_freq;
1721 unsigned int hpll_freq;
1724 * wq - Driver workqueue for GEM.
1726 * NOTE: Work items scheduled here are not allowed to grab any modeset
1727 * locks, for otherwise the flushing done in the pageflip code will
1728 * result in deadlocks.
1730 struct workqueue_struct *wq;
1732 /* Display functions */
1733 struct drm_i915_display_funcs display;
1735 /* PCH chipset type */
1736 enum intel_pch pch_type;
1737 unsigned short pch_id;
1739 unsigned long quirks;
1741 enum modeset_restore modeset_restore;
1742 struct mutex modeset_restore_lock;
1744 struct list_head vm_list; /* Global list of all address spaces */
1745 struct i915_gtt gtt; /* VM representing the global address space */
1747 struct i915_gem_mm mm;
1748 DECLARE_HASHTABLE(mm_structs, 7);
1749 struct mutex mm_lock;
1751 /* Kernel Modesetting */
1753 struct sdvo_device_mapping sdvo_mappings[2];
1755 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1756 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1757 wait_queue_head_t pending_flip_queue;
1759 #ifdef CONFIG_DEBUG_FS
1760 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1763 int num_shared_dpll;
1764 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1765 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1767 struct i915_workarounds workarounds;
1769 /* Reclocking support */
1770 bool render_reclock_avail;
1771 bool lvds_downclock_avail;
1772 /* indicates the reduced downclock for LVDS*/
1775 struct i915_frontbuffer_tracking fb_tracking;
1779 bool mchbar_need_disable;
1781 struct intel_l3_parity l3_parity;
1783 /* Cannot be determined by PCIID. You must always read a register. */
1786 /* gen6+ rps state */
1787 struct intel_gen6_power_mgmt rps;
1789 /* ilk-only ips/rps state. Everything in here is protected by the global
1790 * mchdev_lock in intel_pm.c */
1791 struct intel_ilk_power_mgmt ips;
1793 struct i915_power_domains power_domains;
1795 struct i915_psr psr;
1797 struct i915_gpu_error gpu_error;
1799 struct drm_i915_gem_object *vlv_pctx;
1801 #ifdef CONFIG_DRM_I915_FBDEV
1802 /* list of fbdev register on this device */
1803 struct intel_fbdev *fbdev;
1804 struct work_struct fbdev_suspend_work;
1807 struct drm_property *broadcast_rgb_property;
1808 struct drm_property *force_audio_property;
1810 /* hda/i915 audio component */
1811 bool audio_component_registered;
1813 uint32_t hw_context_size;
1814 struct list_head context_list;
1818 u32 chv_phy_control;
1821 struct i915_suspend_saved_registers regfile;
1822 struct vlv_s0ix_state vlv_s0ix_state;
1826 * Raw watermark latency values:
1827 * in 0.1us units for WM0,
1828 * in 0.5us units for WM1+.
1831 uint16_t pri_latency[5];
1833 uint16_t spr_latency[5];
1835 uint16_t cur_latency[5];
1837 * Raw watermark memory latency values
1838 * for SKL for all 8 levels
1841 uint16_t skl_latency[8];
1844 * The skl_wm_values structure is a bit too big for stack
1845 * allocation, so we keep the staging struct where we store
1846 * intermediate results here instead.
1848 struct skl_wm_values skl_results;
1850 /* current hardware state */
1852 struct ilk_wm_values hw;
1853 struct skl_wm_values skl_hw;
1854 struct vlv_wm_values vlv;
1858 struct i915_runtime_pm pm;
1860 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1861 u32 long_hpd_port_mask;
1862 u32 short_hpd_port_mask;
1863 struct work_struct dig_port_work;
1866 * if we get a HPD irq from DP and a HPD irq from non-DP
1867 * the non-DP HPD could block the workqueue on a mode config
1868 * mutex getting, that userspace may have taken. However
1869 * userspace is waiting on the DP workqueue to run which is
1870 * blocked behind the non-DP one.
1872 struct workqueue_struct *dp_wq;
1874 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1876 int (*execbuf_submit)(struct drm_device *dev, struct drm_file *file,
1877 struct intel_engine_cs *ring,
1878 struct intel_context *ctx,
1879 struct drm_i915_gem_execbuffer2 *args,
1880 struct list_head *vmas,
1881 struct drm_i915_gem_object *batch_obj,
1882 u64 exec_start, u32 flags);
1883 int (*init_rings)(struct drm_device *dev);
1884 void (*cleanup_ring)(struct intel_engine_cs *ring);
1885 void (*stop_ring)(struct intel_engine_cs *ring);
1888 bool edp_low_vswing;
1891 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1892 * will be rejected. Instead look for a better place.
1896 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1898 return dev->dev_private;
1901 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1903 return to_i915(dev_get_drvdata(dev));
1906 /* Iterate over initialised rings */
1907 #define for_each_ring(ring__, dev_priv__, i__) \
1908 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1909 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1911 enum hdmi_force_audio {
1912 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1913 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1914 HDMI_AUDIO_AUTO, /* trust EDID */
1915 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1918 #define I915_GTT_OFFSET_NONE ((u32)-1)
1920 struct drm_i915_gem_object_ops {
1921 /* Interface between the GEM object and its backing storage.
1922 * get_pages() is called once prior to the use of the associated set
1923 * of pages before to binding them into the GTT, and put_pages() is
1924 * called after we no longer need them. As we expect there to be
1925 * associated cost with migrating pages between the backing storage
1926 * and making them available for the GPU (e.g. clflush), we may hold
1927 * onto the pages after they are no longer referenced by the GPU
1928 * in case they may be used again shortly (for example migrating the
1929 * pages to a different memory domain within the GTT). put_pages()
1930 * will therefore most likely be called when the object itself is
1931 * being released or under memory pressure (where we attempt to
1932 * reap pages for the shrinker).
1934 int (*get_pages)(struct drm_i915_gem_object *);
1935 void (*put_pages)(struct drm_i915_gem_object *);
1936 int (*dmabuf_export)(struct drm_i915_gem_object *);
1937 void (*release)(struct drm_i915_gem_object *);
1941 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1942 * considered to be the frontbuffer for the given plane interface-vise. This
1943 * doesn't mean that the hw necessarily already scans it out, but that any
1944 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1946 * We have one bit per pipe and per scanout plane type.
1948 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1949 #define INTEL_FRONTBUFFER_BITS \
1950 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1951 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1952 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1953 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1954 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1955 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1956 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1957 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1958 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1959 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1960 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1962 struct drm_i915_gem_object {
1963 struct drm_gem_object base;
1965 const struct drm_i915_gem_object_ops *ops;
1967 /** List of VMAs backed by this object */
1968 struct list_head vma_list;
1970 /** Stolen memory for this object, instead of being backed by shmem. */
1971 struct drm_mm_node *stolen;
1972 struct list_head global_list;
1974 struct list_head ring_list[I915_NUM_RINGS];
1975 /** Used in execbuf to temporarily hold a ref */
1976 struct list_head obj_exec_link;
1978 struct list_head batch_pool_link;
1981 * This is set if the object is on the active lists (has pending
1982 * rendering and so a non-zero seqno), and is not set if it i s on
1983 * inactive (ready to be unbound) list.
1985 unsigned int active:I915_NUM_RINGS;
1988 * This is set if the object has been written to since last bound
1991 unsigned int dirty:1;
1994 * Fence register bits (if any) for this object. Will be set
1995 * as needed when mapped into the GTT.
1996 * Protected by dev->struct_mutex.
1998 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2001 * Advice: are the backing pages purgeable?
2003 unsigned int madv:2;
2006 * Current tiling mode for the object.
2008 unsigned int tiling_mode:2;
2010 * Whether the tiling parameters for the currently associated fence
2011 * register have changed. Note that for the purposes of tracking
2012 * tiling changes we also treat the unfenced register, the register
2013 * slot that the object occupies whilst it executes a fenced
2014 * command (such as BLT on gen2/3), as a "fence".
2016 unsigned int fence_dirty:1;
2019 * Is the object at the current location in the gtt mappable and
2020 * fenceable? Used to avoid costly recalculations.
2022 unsigned int map_and_fenceable:1;
2025 * Whether the current gtt mapping needs to be mappable (and isn't just
2026 * mappable by accident). Track pin and fault separate for a more
2027 * accurate mappable working set.
2029 unsigned int fault_mappable:1;
2032 * Is the object to be mapped as read-only to the GPU
2033 * Only honoured if hardware has relevant pte bit
2035 unsigned long gt_ro:1;
2036 unsigned int cache_level:3;
2037 unsigned int cache_dirty:1;
2039 unsigned int has_dma_mapping:1;
2041 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2043 unsigned int pin_display;
2045 struct sg_table *pages;
2046 int pages_pin_count;
2048 struct scatterlist *sg;
2052 /* prime dma-buf support */
2053 void *dma_buf_vmapping;
2056 /** Breadcrumb of last rendering to the buffer.
2057 * There can only be one writer, but we allow for multiple readers.
2058 * If there is a writer that necessarily implies that all other
2059 * read requests are complete - but we may only be lazily clearing
2060 * the read requests. A read request is naturally the most recent
2061 * request on a ring, so we may have two different write and read
2062 * requests on one ring where the write request is older than the
2063 * read request. This allows for the CPU to read from an active
2064 * buffer by only waiting for the write to complete.
2066 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2067 struct drm_i915_gem_request *last_write_req;
2068 /** Breadcrumb of last fenced GPU access to the buffer. */
2069 struct drm_i915_gem_request *last_fenced_req;
2071 /** Current tiling stride for the object, if it's tiled. */
2074 /** References from framebuffers, locks out tiling changes. */
2075 unsigned long framebuffer_references;
2077 /** Record of address bit 17 of each page at last unbind. */
2078 unsigned long *bit_17;
2081 /** for phy allocated objects */
2082 struct drm_dma_handle *phys_handle;
2084 struct i915_gem_userptr {
2086 unsigned read_only :1;
2087 unsigned workers :4;
2088 #define I915_GEM_USERPTR_MAX_WORKERS 15
2090 struct i915_mm_struct *mm;
2091 struct i915_mmu_object *mmu_object;
2092 struct work_struct *work;
2096 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2098 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2099 struct drm_i915_gem_object *new,
2100 unsigned frontbuffer_bits);
2103 * Request queue structure.
2105 * The request queue allows us to note sequence numbers that have been emitted
2106 * and may be associated with active buffers to be retired.
2108 * By keeping this list, we can avoid having to do questionable sequence
2109 * number comparisons on buffer last_read|write_seqno. It also allows an
2110 * emission time to be associated with the request for tracking how far ahead
2111 * of the GPU the submission is.
2113 * The requests are reference counted, so upon creation they should have an
2114 * initial reference taken using kref_init
2116 struct drm_i915_gem_request {
2119 /** On Which ring this request was generated */
2120 struct drm_i915_private *i915;
2121 struct intel_engine_cs *ring;
2123 /** GEM sequence number associated with this request. */
2126 /** Position in the ringbuffer of the start of the request */
2130 * Position in the ringbuffer of the start of the postfix.
2131 * This is required to calculate the maximum available ringbuffer
2132 * space without overwriting the postfix.
2136 /** Position in the ringbuffer of the end of the whole request */
2140 * Context and ring buffer related to this request
2141 * Contexts are refcounted, so when this request is associated with a
2142 * context, we must increment the context's refcount, to guarantee that
2143 * it persists while any request is linked to it. Requests themselves
2144 * are also refcounted, so the request will only be freed when the last
2145 * reference to it is dismissed, and the code in
2146 * i915_gem_request_free() will then decrement the refcount on the
2149 struct intel_context *ctx;
2150 struct intel_ringbuffer *ringbuf;
2152 /** Batch buffer related to this request if any */
2153 struct drm_i915_gem_object *batch_obj;
2155 /** Time at which this request was emitted, in jiffies. */
2156 unsigned long emitted_jiffies;
2158 /** global list entry for this request */
2159 struct list_head list;
2161 struct drm_i915_file_private *file_priv;
2162 /** file_priv list entry for this request */
2163 struct list_head client_list;
2165 /** process identifier submitting this request */
2169 * The ELSP only accepts two elements at a time, so we queue
2170 * context/tail pairs on a given queue (ring->execlist_queue) until the
2171 * hardware is available. The queue serves a double purpose: we also use
2172 * it to keep track of the up to 2 contexts currently in the hardware
2173 * (usually one in execution and the other queued up by the GPU): We
2174 * only remove elements from the head of the queue when the hardware
2175 * informs us that an element has been completed.
2177 * All accesses to the queue are mediated by a spinlock
2178 * (ring->execlist_lock).
2181 /** Execlist link in the submission queue.*/
2182 struct list_head execlist_link;
2184 /** Execlists no. of times this request has been sent to the ELSP */
2189 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2190 struct intel_context *ctx);
2191 void i915_gem_request_free(struct kref *req_ref);
2193 static inline uint32_t
2194 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2196 return req ? req->seqno : 0;
2199 static inline struct intel_engine_cs *
2200 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2202 return req ? req->ring : NULL;
2205 static inline struct drm_i915_gem_request *
2206 i915_gem_request_reference(struct drm_i915_gem_request *req)
2209 kref_get(&req->ref);
2214 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2216 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2217 kref_put(&req->ref, i915_gem_request_free);
2221 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2223 struct drm_device *dev;
2228 dev = req->ring->dev;
2229 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2230 mutex_unlock(&dev->struct_mutex);
2233 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2234 struct drm_i915_gem_request *src)
2237 i915_gem_request_reference(src);
2240 i915_gem_request_unreference(*pdst);
2246 * XXX: i915_gem_request_completed should be here but currently needs the
2247 * definition of i915_seqno_passed() which is below. It will be moved in
2248 * a later patch when the call to i915_seqno_passed() is obsoleted...
2252 * A command that requires special handling by the command parser.
2254 struct drm_i915_cmd_descriptor {
2256 * Flags describing how the command parser processes the command.
2258 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2259 * a length mask if not set
2260 * CMD_DESC_SKIP: The command is allowed but does not follow the
2261 * standard length encoding for the opcode range in
2263 * CMD_DESC_REJECT: The command is never allowed
2264 * CMD_DESC_REGISTER: The command should be checked against the
2265 * register whitelist for the appropriate ring
2266 * CMD_DESC_MASTER: The command is allowed if the submitting process
2270 #define CMD_DESC_FIXED (1<<0)
2271 #define CMD_DESC_SKIP (1<<1)
2272 #define CMD_DESC_REJECT (1<<2)
2273 #define CMD_DESC_REGISTER (1<<3)
2274 #define CMD_DESC_BITMASK (1<<4)
2275 #define CMD_DESC_MASTER (1<<5)
2278 * The command's unique identification bits and the bitmask to get them.
2279 * This isn't strictly the opcode field as defined in the spec and may
2280 * also include type, subtype, and/or subop fields.
2288 * The command's length. The command is either fixed length (i.e. does
2289 * not include a length field) or has a length field mask. The flag
2290 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2291 * a length mask. All command entries in a command table must include
2292 * length information.
2300 * Describes where to find a register address in the command to check
2301 * against the ring's register whitelist. Only valid if flags has the
2302 * CMD_DESC_REGISTER bit set.
2304 * A non-zero step value implies that the command may access multiple
2305 * registers in sequence (e.g. LRI), in that case step gives the
2306 * distance in dwords between individual offset fields.
2314 #define MAX_CMD_DESC_BITMASKS 3
2316 * Describes command checks where a particular dword is masked and
2317 * compared against an expected value. If the command does not match
2318 * the expected value, the parser rejects it. Only valid if flags has
2319 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2322 * If the check specifies a non-zero condition_mask then the parser
2323 * only performs the check when the bits specified by condition_mask
2330 u32 condition_offset;
2332 } bits[MAX_CMD_DESC_BITMASKS];
2336 * A table of commands requiring special handling by the command parser.
2338 * Each ring has an array of tables. Each table consists of an array of command
2339 * descriptors, which must be sorted with command opcodes in ascending order.
2341 struct drm_i915_cmd_table {
2342 const struct drm_i915_cmd_descriptor *table;
2346 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2347 #define __I915__(p) ({ \
2348 struct drm_i915_private *__p; \
2349 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2350 __p = (struct drm_i915_private *)p; \
2351 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2352 __p = to_i915((struct drm_device *)p); \
2357 #define INTEL_INFO(p) (&__I915__(p)->info)
2358 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2359 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2361 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2362 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2363 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2364 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2365 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2366 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2367 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2368 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2369 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2370 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2371 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2372 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2373 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2374 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2375 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2376 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2377 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2378 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2379 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2380 INTEL_DEVID(dev) == 0x0152 || \
2381 INTEL_DEVID(dev) == 0x015a)
2382 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2383 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2384 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2385 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2386 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2387 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2388 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2389 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2390 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2391 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2392 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2393 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2394 (INTEL_DEVID(dev) & 0xf) == 0xe))
2395 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2396 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2397 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2398 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2399 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2400 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2401 /* ULX machines are also considered ULT. */
2402 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2403 INTEL_DEVID(dev) == 0x0A1E)
2404 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2406 #define SKL_REVID_A0 (0x0)
2407 #define SKL_REVID_B0 (0x1)
2408 #define SKL_REVID_C0 (0x2)
2409 #define SKL_REVID_D0 (0x3)
2410 #define SKL_REVID_E0 (0x4)
2411 #define SKL_REVID_F0 (0x5)
2413 #define BXT_REVID_A0 (0x0)
2414 #define BXT_REVID_B0 (0x3)
2415 #define BXT_REVID_C0 (0x6)
2418 * The genX designation typically refers to the render engine, so render
2419 * capability related checks should use IS_GEN, while display and other checks
2420 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2423 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2424 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2425 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2426 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2427 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2428 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2429 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2430 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2432 #define RENDER_RING (1<<RCS)
2433 #define BSD_RING (1<<VCS)
2434 #define BLT_RING (1<<BCS)
2435 #define VEBOX_RING (1<<VECS)
2436 #define BSD2_RING (1<<VCS2)
2437 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2438 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2439 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2440 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2441 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2442 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2443 __I915__(dev)->ellc_size)
2444 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2446 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2447 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2448 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2449 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2451 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2452 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2454 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2455 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2457 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2458 * even when in MSI mode. This results in spurious interrupt warnings if the
2459 * legacy irq no. is shared with another device. The kernel then disables that
2460 * interrupt source and so prevents the other device from working properly.
2462 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2463 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2465 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2466 * rows, which changed the alignment requirements and fence programming.
2468 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2470 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2471 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2472 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2473 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2474 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2476 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2477 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2478 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2480 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2482 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2483 INTEL_INFO(dev)->gen >= 9)
2485 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2486 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2487 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2488 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2490 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2491 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2493 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2494 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2496 #define HAS_CSR(dev) (IS_SKYLAKE(dev))
2498 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2499 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2500 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2501 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2502 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2503 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2504 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2505 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2507 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2508 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2509 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2510 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2511 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2512 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2513 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2515 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2517 /* DPF == dynamic parity feature */
2518 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2519 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2521 #define GT_FREQUENCY_MULTIPLIER 50
2522 #define GEN9_FREQ_SCALER 3
2524 #include "i915_trace.h"
2526 extern const struct drm_ioctl_desc i915_ioctls[];
2527 extern int i915_max_ioctl;
2529 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2530 extern int i915_resume_legacy(struct drm_device *dev);
2533 struct i915_params {
2535 int panel_ignore_lid;
2537 unsigned int lvds_downclock;
2538 int lvds_channel_mode;
2540 int vbt_sdvo_panel_type;
2544 int enable_execlists;
2546 unsigned int preliminary_hw_support;
2547 int disable_power_well;
2549 int invert_brightness;
2550 int enable_cmd_parser;
2551 /* leave bools at the end to not create holes */
2552 bool enable_hangcheck;
2554 bool prefault_disable;
2555 bool load_detect_test;
2557 bool disable_display;
2558 bool disable_vtd_wa;
2561 bool verbose_state_checks;
2562 bool nuclear_pageflip;
2565 extern struct i915_params i915 __read_mostly;
2568 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2569 extern int i915_driver_unload(struct drm_device *);
2570 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2571 extern void i915_driver_lastclose(struct drm_device * dev);
2572 extern void i915_driver_preclose(struct drm_device *dev,
2573 struct drm_file *file);
2574 extern void i915_driver_postclose(struct drm_device *dev,
2575 struct drm_file *file);
2576 extern int i915_driver_device_is_agp(struct drm_device * dev);
2577 #ifdef CONFIG_COMPAT
2578 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2581 extern int intel_gpu_reset(struct drm_device *dev);
2582 extern int i915_reset(struct drm_device *dev);
2583 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2584 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2585 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2586 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2587 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2588 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2589 void i915_firmware_load_error_print(const char *fw_path, int err);
2592 void i915_queue_hangcheck(struct drm_device *dev);
2594 void i915_handle_error(struct drm_device *dev, bool wedged,
2595 const char *fmt, ...);
2597 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2598 extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2599 int intel_irq_install(struct drm_i915_private *dev_priv);
2600 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2602 extern void intel_uncore_sanitize(struct drm_device *dev);
2603 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2604 bool restore_forcewake);
2605 extern void intel_uncore_init(struct drm_device *dev);
2606 extern void intel_uncore_check_errors(struct drm_device *dev);
2607 extern void intel_uncore_fini(struct drm_device *dev);
2608 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2609 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2610 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2611 enum forcewake_domains domains);
2612 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2613 enum forcewake_domains domains);
2614 /* Like above but the caller must manage the uncore.lock itself.
2615 * Must be used with I915_READ_FW and friends.
2617 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2618 enum forcewake_domains domains);
2619 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2620 enum forcewake_domains domains);
2621 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2622 static inline bool intel_vgpu_active(struct drm_device *dev)
2624 return to_i915(dev)->vgpu.active;
2628 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2632 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2635 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2636 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2638 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2640 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2641 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2642 uint32_t interrupt_mask,
2643 uint32_t enabled_irq_mask);
2644 #define ibx_enable_display_interrupt(dev_priv, bits) \
2645 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2646 #define ibx_disable_display_interrupt(dev_priv, bits) \
2647 ibx_display_interrupt_update((dev_priv), (bits), 0)
2650 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2651 struct drm_file *file_priv);
2652 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2653 struct drm_file *file_priv);
2654 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2655 struct drm_file *file_priv);
2656 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2657 struct drm_file *file_priv);
2658 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2659 struct drm_file *file_priv);
2660 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2661 struct drm_file *file_priv);
2662 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2663 struct drm_file *file_priv);
2664 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2665 struct intel_engine_cs *ring);
2666 void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2667 struct drm_file *file,
2668 struct intel_engine_cs *ring,
2669 struct drm_i915_gem_object *obj);
2670 int i915_gem_ringbuffer_submission(struct drm_device *dev,
2671 struct drm_file *file,
2672 struct intel_engine_cs *ring,
2673 struct intel_context *ctx,
2674 struct drm_i915_gem_execbuffer2 *args,
2675 struct list_head *vmas,
2676 struct drm_i915_gem_object *batch_obj,
2677 u64 exec_start, u32 flags);
2678 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2679 struct drm_file *file_priv);
2680 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2681 struct drm_file *file_priv);
2682 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2683 struct drm_file *file_priv);
2684 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2685 struct drm_file *file);
2686 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2687 struct drm_file *file);
2688 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2689 struct drm_file *file_priv);
2690 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2691 struct drm_file *file_priv);
2692 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2693 struct drm_file *file_priv);
2694 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2695 struct drm_file *file_priv);
2696 int i915_gem_init_userptr(struct drm_device *dev);
2697 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2698 struct drm_file *file);
2699 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2700 struct drm_file *file_priv);
2701 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2702 struct drm_file *file_priv);
2703 void i915_gem_load(struct drm_device *dev);
2704 void *i915_gem_object_alloc(struct drm_device *dev);
2705 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2706 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2707 const struct drm_i915_gem_object_ops *ops);
2708 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2710 void i915_init_vm(struct drm_i915_private *dev_priv,
2711 struct i915_address_space *vm);
2712 void i915_gem_free_object(struct drm_gem_object *obj);
2713 void i915_gem_vma_destroy(struct i915_vma *vma);
2715 /* Flags used by pin/bind&friends. */
2716 #define PIN_MAPPABLE (1<<0)
2717 #define PIN_NONBLOCK (1<<1)
2718 #define PIN_GLOBAL (1<<2)
2719 #define PIN_OFFSET_BIAS (1<<3)
2720 #define PIN_USER (1<<4)
2721 #define PIN_UPDATE (1<<5)
2722 #define PIN_OFFSET_MASK (~4095)
2724 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2725 struct i915_address_space *vm,
2729 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2730 const struct i915_ggtt_view *view,
2734 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2736 int __must_check i915_vma_unbind(struct i915_vma *vma);
2737 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2738 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2739 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2741 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2742 int *needs_clflush);
2744 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2746 static inline int __sg_page_count(struct scatterlist *sg)
2748 return sg->length >> PAGE_SHIFT;
2751 static inline struct page *
2752 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2754 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2757 if (n < obj->get_page.last) {
2758 obj->get_page.sg = obj->pages->sgl;
2759 obj->get_page.last = 0;
2762 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2763 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2764 if (unlikely(sg_is_chain(obj->get_page.sg)))
2765 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2768 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2771 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2773 BUG_ON(obj->pages == NULL);
2774 obj->pages_pin_count++;
2776 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2778 BUG_ON(obj->pages_pin_count == 0);
2779 obj->pages_pin_count--;
2782 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2783 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2784 struct intel_engine_cs *to);
2785 void i915_vma_move_to_active(struct i915_vma *vma,
2786 struct intel_engine_cs *ring);
2787 int i915_gem_dumb_create(struct drm_file *file_priv,
2788 struct drm_device *dev,
2789 struct drm_mode_create_dumb *args);
2790 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2791 uint32_t handle, uint64_t *offset);
2793 * Returns true if seq1 is later than seq2.
2796 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2798 return (int32_t)(seq1 - seq2) >= 0;
2801 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2802 bool lazy_coherency)
2806 BUG_ON(req == NULL);
2808 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2810 return i915_seqno_passed(seqno, req->seqno);
2813 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2814 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2815 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2816 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2818 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2819 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2821 struct drm_i915_gem_request *
2822 i915_gem_find_active_request(struct intel_engine_cs *ring);
2824 bool i915_gem_retire_requests(struct drm_device *dev);
2825 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2826 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2827 bool interruptible);
2828 int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req);
2830 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2832 return unlikely(atomic_read(&error->reset_counter)
2833 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2836 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2838 return atomic_read(&error->reset_counter) & I915_WEDGED;
2841 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2843 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2846 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2848 return dev_priv->gpu_error.stop_rings == 0 ||
2849 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2852 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2854 return dev_priv->gpu_error.stop_rings == 0 ||
2855 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2858 void i915_gem_reset(struct drm_device *dev);
2859 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2860 int __must_check i915_gem_init(struct drm_device *dev);
2861 int i915_gem_init_rings(struct drm_device *dev);
2862 int __must_check i915_gem_init_hw(struct drm_device *dev);
2863 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2864 void i915_gem_init_swizzling(struct drm_device *dev);
2865 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2866 int __must_check i915_gpu_idle(struct drm_device *dev);
2867 int __must_check i915_gem_suspend(struct drm_device *dev);
2868 int __i915_add_request(struct intel_engine_cs *ring,
2869 struct drm_file *file,
2870 struct drm_i915_gem_object *batch_obj);
2871 #define i915_add_request(ring) \
2872 __i915_add_request(ring, NULL, NULL)
2873 int __i915_wait_request(struct drm_i915_gem_request *req,
2874 unsigned reset_counter,
2877 struct intel_rps_client *rps);
2878 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2879 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2881 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2884 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2887 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2889 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2891 struct intel_engine_cs *pipelined,
2892 const struct i915_ggtt_view *view);
2893 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
2894 const struct i915_ggtt_view *view);
2895 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2897 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2898 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2901 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2903 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2904 int tiling_mode, bool fenced);
2906 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2907 enum i915_cache_level cache_level);
2909 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2910 struct dma_buf *dma_buf);
2912 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2913 struct drm_gem_object *gem_obj, int flags);
2915 void i915_gem_restore_fences(struct drm_device *dev);
2918 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
2919 const struct i915_ggtt_view *view);
2921 i915_gem_obj_offset(struct drm_i915_gem_object *o,
2922 struct i915_address_space *vm);
2923 static inline unsigned long
2924 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
2926 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
2929 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2930 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
2931 const struct i915_ggtt_view *view);
2932 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2933 struct i915_address_space *vm);
2935 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2936 struct i915_address_space *vm);
2938 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2939 struct i915_address_space *vm);
2941 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
2942 const struct i915_ggtt_view *view);
2945 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2946 struct i915_address_space *vm);
2948 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2949 const struct i915_ggtt_view *view);
2951 static inline struct i915_vma *
2952 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
2954 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
2956 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
2958 /* Some GGTT VM helpers */
2959 #define i915_obj_to_ggtt(obj) \
2960 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2961 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2963 struct i915_address_space *ggtt =
2964 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2968 static inline struct i915_hw_ppgtt *
2969 i915_vm_to_ppgtt(struct i915_address_space *vm)
2971 WARN_ON(i915_is_ggtt(vm));
2973 return container_of(vm, struct i915_hw_ppgtt, base);
2977 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2979 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
2982 static inline unsigned long
2983 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2985 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2988 static inline int __must_check
2989 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2993 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2994 alignment, flags | PIN_GLOBAL);
2998 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3000 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3003 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3004 const struct i915_ggtt_view *view);
3006 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3008 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3011 /* i915_gem_context.c */
3012 int __must_check i915_gem_context_init(struct drm_device *dev);
3013 void i915_gem_context_fini(struct drm_device *dev);
3014 void i915_gem_context_reset(struct drm_device *dev);
3015 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3016 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
3017 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3018 int i915_switch_context(struct intel_engine_cs *ring,
3019 struct intel_context *to);
3020 struct intel_context *
3021 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3022 void i915_gem_context_free(struct kref *ctx_ref);
3023 struct drm_i915_gem_object *
3024 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3025 static inline void i915_gem_context_reference(struct intel_context *ctx)
3027 kref_get(&ctx->ref);
3030 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3032 kref_put(&ctx->ref, i915_gem_context_free);
3035 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3037 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3040 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3041 struct drm_file *file);
3042 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3043 struct drm_file *file);
3044 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3045 struct drm_file *file_priv);
3046 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3047 struct drm_file *file_priv);
3049 /* i915_gem_evict.c */
3050 int __must_check i915_gem_evict_something(struct drm_device *dev,
3051 struct i915_address_space *vm,
3054 unsigned cache_level,
3055 unsigned long start,
3058 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3059 int i915_gem_evict_everything(struct drm_device *dev);
3061 /* belongs in i915_gem_gtt.h */
3062 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3064 if (INTEL_INFO(dev)->gen < 6)
3065 intel_gtt_chipset_flush();
3068 /* i915_gem_stolen.c */
3069 int i915_gem_init_stolen(struct drm_device *dev);
3070 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
3071 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
3072 void i915_gem_cleanup_stolen(struct drm_device *dev);
3073 struct drm_i915_gem_object *
3074 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3075 struct drm_i915_gem_object *
3076 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3081 /* i915_gem_shrinker.c */
3082 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3085 #define I915_SHRINK_PURGEABLE 0x1
3086 #define I915_SHRINK_UNBOUND 0x2
3087 #define I915_SHRINK_BOUND 0x4
3088 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3089 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3092 /* i915_gem_tiling.c */
3093 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3095 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3097 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3098 obj->tiling_mode != I915_TILING_NONE;
3101 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3102 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3103 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3105 /* i915_gem_debug.c */
3107 int i915_verify_lists(struct drm_device *dev);
3109 #define i915_verify_lists(dev) 0
3112 /* i915_debugfs.c */
3113 int i915_debugfs_init(struct drm_minor *minor);
3114 void i915_debugfs_cleanup(struct drm_minor *minor);
3115 #ifdef CONFIG_DEBUG_FS
3116 int i915_debugfs_connector_add(struct drm_connector *connector);
3117 void intel_display_crc_init(struct drm_device *dev);
3119 static inline int i915_debugfs_connector_add(struct drm_connector *connector) {}
3120 static inline void intel_display_crc_init(struct drm_device *dev) {}
3123 /* i915_gpu_error.c */
3125 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3126 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3127 const struct i915_error_state_file_priv *error);
3128 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3129 struct drm_i915_private *i915,
3130 size_t count, loff_t pos);
3131 static inline void i915_error_state_buf_release(
3132 struct drm_i915_error_state_buf *eb)
3136 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3137 const char *error_msg);
3138 void i915_error_state_get(struct drm_device *dev,
3139 struct i915_error_state_file_priv *error_priv);
3140 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3141 void i915_destroy_error_state(struct drm_device *dev);
3143 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3144 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3146 /* i915_cmd_parser.c */
3147 int i915_cmd_parser_get_version(void);
3148 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3149 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3150 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3151 int i915_parse_cmds(struct intel_engine_cs *ring,
3152 struct drm_i915_gem_object *batch_obj,
3153 struct drm_i915_gem_object *shadow_batch_obj,
3154 u32 batch_start_offset,
3158 /* i915_suspend.c */
3159 extern int i915_save_state(struct drm_device *dev);
3160 extern int i915_restore_state(struct drm_device *dev);
3163 void i915_setup_sysfs(struct drm_device *dev_priv);
3164 void i915_teardown_sysfs(struct drm_device *dev_priv);
3167 extern int intel_setup_gmbus(struct drm_device *dev);
3168 extern void intel_teardown_gmbus(struct drm_device *dev);
3169 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3172 extern struct i2c_adapter *
3173 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3174 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3175 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3176 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3178 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3180 extern void intel_i2c_reset(struct drm_device *dev);
3182 /* intel_opregion.c */
3184 extern int intel_opregion_setup(struct drm_device *dev);
3185 extern void intel_opregion_init(struct drm_device *dev);
3186 extern void intel_opregion_fini(struct drm_device *dev);
3187 extern void intel_opregion_asle_intr(struct drm_device *dev);
3188 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3190 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3193 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3194 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3195 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3196 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3198 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3203 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3211 extern void intel_register_dsm_handler(void);
3212 extern void intel_unregister_dsm_handler(void);
3214 static inline void intel_register_dsm_handler(void) { return; }
3215 static inline void intel_unregister_dsm_handler(void) { return; }
3216 #endif /* CONFIG_ACPI */
3219 extern void intel_modeset_init_hw(struct drm_device *dev);
3220 extern void intel_modeset_init(struct drm_device *dev);
3221 extern void intel_modeset_gem_init(struct drm_device *dev);
3222 extern void intel_modeset_cleanup(struct drm_device *dev);
3223 extern void intel_connector_unregister(struct intel_connector *);
3224 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3225 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
3226 bool force_restore);
3227 extern void i915_redisable_vga(struct drm_device *dev);
3228 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3229 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3230 extern void intel_init_pch_refclk(struct drm_device *dev);
3231 extern void intel_set_rps(struct drm_device *dev, u8 val);
3232 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3234 extern void intel_detect_pch(struct drm_device *dev);
3235 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3236 extern int intel_enable_rc6(const struct drm_device *dev);
3238 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3239 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3240 struct drm_file *file);
3241 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3242 struct drm_file *file);
3245 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3246 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3247 struct intel_overlay_error_state *error);
3249 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3250 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3251 struct drm_device *dev,
3252 struct intel_display_error_state *error);
3254 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3255 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3257 /* intel_sideband.c */
3258 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3259 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3260 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3261 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3262 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3263 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3264 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3265 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3266 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3267 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3268 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3269 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3270 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3271 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3272 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3273 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3274 enum intel_sbi_destination destination);
3275 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3276 enum intel_sbi_destination destination);
3277 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3278 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3280 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3281 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3283 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3284 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3286 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3287 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3288 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3289 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3291 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3292 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3293 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3294 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3296 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3297 * will be implemented using 2 32-bit writes in an arbitrary order with
3298 * an arbitrary delay between them. This can cause the hardware to
3299 * act upon the intermediate value, possibly leading to corruption and
3300 * machine death. You have been warned.
3302 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3303 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3305 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3306 u32 upper = I915_READ(upper_reg); \
3307 u32 lower = I915_READ(lower_reg); \
3308 u32 tmp = I915_READ(upper_reg); \
3309 if (upper != tmp) { \
3311 lower = I915_READ(lower_reg); \
3312 WARN_ON(I915_READ(upper_reg) != upper); \
3314 (u64)upper << 32 | lower; })
3316 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3317 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3319 /* These are untraced mmio-accessors that are only valid to be used inside
3320 * criticial sections inside IRQ handlers where forcewake is explicitly
3322 * Think twice, and think again, before using these.
3323 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3324 * intel_uncore_forcewake_irqunlock().
3326 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3327 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3328 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3330 /* "Broadcast RGB" property */
3331 #define INTEL_BROADCAST_RGB_AUTO 0
3332 #define INTEL_BROADCAST_RGB_FULL 1
3333 #define INTEL_BROADCAST_RGB_LIMITED 2
3335 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3337 if (IS_VALLEYVIEW(dev))
3338 return VLV_VGACNTRL;
3339 else if (INTEL_INFO(dev)->gen >= 5)
3340 return CPU_VGACNTRL;
3345 static inline void __user *to_user_ptr(u64 address)
3347 return (void __user *)(uintptr_t)address;
3350 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3352 unsigned long j = msecs_to_jiffies(m);
3354 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3357 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3359 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3362 static inline unsigned long
3363 timespec_to_jiffies_timeout(const struct timespec *value)
3365 unsigned long j = timespec_to_jiffies(value);
3367 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3371 * If you need to wait X milliseconds between events A and B, but event B
3372 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3373 * when event A happened, then just before event B you call this function and
3374 * pass the timestamp as the first argument, and X as the second argument.
3377 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3379 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3382 * Don't re-read the value of "jiffies" every time since it may change
3383 * behind our back and break the math.
3385 tmp_jiffies = jiffies;
3386 target_jiffies = timestamp_jiffies +
3387 msecs_to_jiffies_timeout(to_wait_ms);
3389 if (time_after(target_jiffies, tmp_jiffies)) {
3390 remaining_jiffies = target_jiffies - tmp_jiffies;
3391 while (remaining_jiffies)
3393 schedule_timeout_uninterruptible(remaining_jiffies);
3397 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3398 struct drm_i915_gem_request *req)
3400 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3401 i915_gem_request_assign(&ring->trace_irq_req, req);