1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_bios.h"
59 #include "intel_dpll_mgr.h"
61 #include "intel_lrc.h"
62 #include "intel_ringbuffer.h"
65 #include "i915_gem_context.h"
66 #include "i915_gem_fence_reg.h"
67 #include "i915_gem_object.h"
68 #include "i915_gem_gtt.h"
69 #include "i915_gem_render_state.h"
70 #include "i915_gem_request.h"
71 #include "i915_gem_timeline.h"
75 #include "intel_gvt.h"
77 /* General customization:
80 #define DRIVER_NAME "i915"
81 #define DRIVER_DESC "Intel Graphics"
82 #define DRIVER_DATE "20170403"
83 #define DRIVER_TIMESTAMP 1491198738
85 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
86 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
87 * which may not necessarily be a user visible problem. This will either
88 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
89 * enable distros and users to tailor their preferred amount of i915 abrt
92 #define I915_STATE_WARN(condition, format...) ({ \
93 int __ret_warn_on = !!(condition); \
94 if (unlikely(__ret_warn_on)) \
95 if (!WARN(i915.verbose_state_checks, format)) \
97 unlikely(__ret_warn_on); \
100 #define I915_STATE_WARN_ON(x) \
101 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
103 bool __i915_inject_load_failure(const char *func, int line);
104 #define i915_inject_load_failure() \
105 __i915_inject_load_failure(__func__, __LINE__)
109 } uint_fixed_16_16_t;
111 #define FP_16_16_MAX ({ \
112 uint_fixed_16_16_t fp; \
117 static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
119 uint_fixed_16_16_t fp;
127 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
129 return DIV_ROUND_UP(fp.val, 1 << 16);
132 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
137 static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
138 uint_fixed_16_16_t min2)
140 uint_fixed_16_16_t min;
142 min.val = min(min1.val, min2.val);
146 static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
147 uint_fixed_16_16_t max2)
149 uint_fixed_16_16_t max;
151 max.val = max(max1.val, max2.val);
155 static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
158 uint_fixed_16_16_t fp, res;
160 fp = u32_to_fixed_16_16(val);
161 res.val = DIV_ROUND_UP(fp.val, d);
165 static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
168 uint_fixed_16_16_t res;
171 interm_val = (uint64_t)val << 16;
172 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
173 WARN_ON(interm_val >> 32);
174 res.val = (uint32_t) interm_val;
179 static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
180 uint_fixed_16_16_t mul)
182 uint64_t intermediate_val;
183 uint_fixed_16_16_t fp;
185 intermediate_val = (uint64_t) val * mul.val;
186 WARN_ON(intermediate_val >> 32);
187 fp.val = (uint32_t) intermediate_val;
191 static inline const char *yesno(bool v)
193 return v ? "yes" : "no";
196 static inline const char *onoff(bool v)
198 return v ? "on" : "off";
201 static inline const char *enableddisabled(bool v)
203 return v ? "enabled" : "disabled";
212 I915_MAX_PIPES = _PIPE_EDP
214 #define pipe_name(p) ((p) + 'A')
226 static inline const char *transcoder_name(enum transcoder transcoder)
228 switch (transcoder) {
237 case TRANSCODER_DSI_A:
239 case TRANSCODER_DSI_C:
246 static inline bool transcoder_is_dsi(enum transcoder transcoder)
248 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
252 * Global legacy plane identifier. Valid only for primary/sprite
253 * planes on pre-g4x, and only for primary planes on g4x+.
260 #define plane_name(p) ((p) + 'A')
262 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
265 * Per-pipe plane identifier.
266 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
267 * number of planes per CRTC. Not all platforms really have this many planes,
268 * which means some arrays of size I915_MAX_PLANES may have unused entries
269 * between the topmost sprite plane and the cursor plane.
271 * This is expected to be passed to various register macros
272 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
283 #define for_each_plane_id_on_crtc(__crtc, __p) \
284 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
285 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
296 #define port_name(p) ((p) + 'A')
298 #define I915_NUM_PHYS_VLV 2
311 enum intel_display_power_domain {
315 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
316 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
317 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
318 POWER_DOMAIN_TRANSCODER_A,
319 POWER_DOMAIN_TRANSCODER_B,
320 POWER_DOMAIN_TRANSCODER_C,
321 POWER_DOMAIN_TRANSCODER_EDP,
322 POWER_DOMAIN_TRANSCODER_DSI_A,
323 POWER_DOMAIN_TRANSCODER_DSI_C,
324 POWER_DOMAIN_PORT_DDI_A_LANES,
325 POWER_DOMAIN_PORT_DDI_B_LANES,
326 POWER_DOMAIN_PORT_DDI_C_LANES,
327 POWER_DOMAIN_PORT_DDI_D_LANES,
328 POWER_DOMAIN_PORT_DDI_E_LANES,
329 POWER_DOMAIN_PORT_DDI_A_IO,
330 POWER_DOMAIN_PORT_DDI_B_IO,
331 POWER_DOMAIN_PORT_DDI_C_IO,
332 POWER_DOMAIN_PORT_DDI_D_IO,
333 POWER_DOMAIN_PORT_DDI_E_IO,
334 POWER_DOMAIN_PORT_DSI,
335 POWER_DOMAIN_PORT_CRT,
336 POWER_DOMAIN_PORT_OTHER,
345 POWER_DOMAIN_MODESET,
351 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
352 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
353 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
354 #define POWER_DOMAIN_TRANSCODER(tran) \
355 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
356 (tran) + POWER_DOMAIN_TRANSCODER_A)
360 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
372 #define for_each_hpd_pin(__pin) \
373 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
375 #define HPD_STORM_DEFAULT_THRESHOLD 5
377 struct i915_hotplug {
378 struct work_struct hotplug_work;
381 unsigned long last_jiffies;
386 HPD_MARK_DISABLED = 2
388 } stats[HPD_NUM_PINS];
390 struct delayed_work reenable_work;
392 struct intel_digital_port *irq_port[I915_MAX_PORTS];
395 struct work_struct dig_port_work;
397 struct work_struct poll_init_work;
400 unsigned int hpd_storm_threshold;
403 * if we get a HPD irq from DP and a HPD irq from non-DP
404 * the non-DP HPD could block the workqueue on a mode config
405 * mutex getting, that userspace may have taken. However
406 * userspace is waiting on the DP workqueue to run which is
407 * blocked behind the non-DP one.
409 struct workqueue_struct *dp_wq;
412 #define I915_GEM_GPU_DOMAINS \
413 (I915_GEM_DOMAIN_RENDER | \
414 I915_GEM_DOMAIN_SAMPLER | \
415 I915_GEM_DOMAIN_COMMAND | \
416 I915_GEM_DOMAIN_INSTRUCTION | \
417 I915_GEM_DOMAIN_VERTEX)
419 #define for_each_pipe(__dev_priv, __p) \
420 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
421 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
422 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
423 for_each_if ((__mask) & (1 << (__p)))
424 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
426 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
428 #define for_each_sprite(__dev_priv, __p, __s) \
430 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
433 #define for_each_port_masked(__port, __ports_mask) \
434 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
435 for_each_if ((__ports_mask) & (1 << (__port)))
437 #define for_each_crtc(dev, crtc) \
438 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
440 #define for_each_intel_plane(dev, intel_plane) \
441 list_for_each_entry(intel_plane, \
442 &(dev)->mode_config.plane_list, \
445 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
446 list_for_each_entry(intel_plane, \
447 &(dev)->mode_config.plane_list, \
449 for_each_if ((plane_mask) & \
450 (1 << drm_plane_index(&intel_plane->base)))
452 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
453 list_for_each_entry(intel_plane, \
454 &(dev)->mode_config.plane_list, \
456 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
458 #define for_each_intel_crtc(dev, intel_crtc) \
459 list_for_each_entry(intel_crtc, \
460 &(dev)->mode_config.crtc_list, \
463 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
464 list_for_each_entry(intel_crtc, \
465 &(dev)->mode_config.crtc_list, \
467 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
469 #define for_each_intel_encoder(dev, intel_encoder) \
470 list_for_each_entry(intel_encoder, \
471 &(dev)->mode_config.encoder_list, \
474 #define for_each_intel_connector_iter(intel_connector, iter) \
475 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
477 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
478 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
479 for_each_if ((intel_encoder)->base.crtc == (__crtc))
481 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
482 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
483 for_each_if ((intel_connector)->base.encoder == (__encoder))
485 #define for_each_power_domain(domain, mask) \
486 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
487 for_each_if (BIT_ULL(domain) & (mask))
489 #define for_each_power_well(__dev_priv, __power_well) \
490 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
491 (__power_well) - (__dev_priv)->power_domains.power_wells < \
492 (__dev_priv)->power_domains.power_well_count; \
495 #define for_each_power_well_rev(__dev_priv, __power_well) \
496 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
497 (__dev_priv)->power_domains.power_well_count - 1; \
498 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
501 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
502 for_each_power_well(__dev_priv, __power_well) \
503 for_each_if ((__power_well)->domains & (__domain_mask))
505 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
506 for_each_power_well_rev(__dev_priv, __power_well) \
507 for_each_if ((__power_well)->domains & (__domain_mask))
509 #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
511 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
512 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
513 (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
515 for_each_if (plane_state)
517 struct drm_i915_private;
518 struct i915_mm_struct;
519 struct i915_mmu_object;
521 struct drm_i915_file_private {
522 struct drm_i915_private *dev_priv;
523 struct drm_file *file;
527 struct list_head request_list;
528 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
529 * chosen to prevent the CPU getting more than a frame ahead of the GPU
530 * (when using lax throttling for the frontbuffer). We also use it to
531 * offer free GPU waitboosts for severely congested workloads.
533 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
535 struct idr context_idr;
537 struct intel_rps_client {
538 struct list_head link;
542 unsigned int bsd_engine;
544 /* Client can have a maximum of 3 contexts banned before
545 * it is denied of creating new contexts. As one context
546 * ban needs 4 consecutive hangs, and more if there is
547 * progress in between, this is a last resort stop gap measure
548 * to limit the badly behaving clients access to gpu.
550 #define I915_MAX_CLIENT_CONTEXT_BANS 3
554 /* Used by dp and fdi links */
555 struct intel_link_m_n {
563 void intel_link_compute_m_n(int bpp, int nlanes,
564 int pixel_clock, int link_clock,
565 struct intel_link_m_n *m_n,
568 /* Interface history:
571 * 1.2: Add Power Management
572 * 1.3: Add vblank support
573 * 1.4: Fix cmdbuffer path, add heap destroy
574 * 1.5: Add vblank pipe configuration
575 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
576 * - Support vertical blank on secondary display pipe
578 #define DRIVER_MAJOR 1
579 #define DRIVER_MINOR 6
580 #define DRIVER_PATCHLEVEL 0
582 struct opregion_header;
583 struct opregion_acpi;
584 struct opregion_swsci;
585 struct opregion_asle;
587 struct intel_opregion {
588 struct opregion_header *header;
589 struct opregion_acpi *acpi;
590 struct opregion_swsci *swsci;
591 u32 swsci_gbda_sub_functions;
592 u32 swsci_sbcb_sub_functions;
593 struct opregion_asle *asle;
598 struct work_struct asle_work;
600 #define OPREGION_SIZE (8*1024)
602 struct intel_overlay;
603 struct intel_overlay_error_state;
605 struct sdvo_device_mapping {
614 struct intel_connector;
615 struct intel_encoder;
616 struct intel_atomic_state;
617 struct intel_crtc_state;
618 struct intel_initial_plane_config;
622 struct intel_cdclk_state;
624 struct drm_i915_display_funcs {
625 void (*get_cdclk)(struct drm_i915_private *dev_priv,
626 struct intel_cdclk_state *cdclk_state);
627 void (*set_cdclk)(struct drm_i915_private *dev_priv,
628 const struct intel_cdclk_state *cdclk_state);
629 int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
630 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
631 int (*compute_intermediate_wm)(struct drm_device *dev,
632 struct intel_crtc *intel_crtc,
633 struct intel_crtc_state *newstate);
634 void (*initial_watermarks)(struct intel_atomic_state *state,
635 struct intel_crtc_state *cstate);
636 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
637 struct intel_crtc_state *cstate);
638 void (*optimize_watermarks)(struct intel_atomic_state *state,
639 struct intel_crtc_state *cstate);
640 int (*compute_global_watermarks)(struct drm_atomic_state *state);
641 void (*update_wm)(struct intel_crtc *crtc);
642 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
643 /* Returns the active state of the crtc, and if the crtc is active,
644 * fills out the pipe-config with the hw state. */
645 bool (*get_pipe_config)(struct intel_crtc *,
646 struct intel_crtc_state *);
647 void (*get_initial_plane_config)(struct intel_crtc *,
648 struct intel_initial_plane_config *);
649 int (*crtc_compute_clock)(struct intel_crtc *crtc,
650 struct intel_crtc_state *crtc_state);
651 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
652 struct drm_atomic_state *old_state);
653 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
654 struct drm_atomic_state *old_state);
655 void (*update_crtcs)(struct drm_atomic_state *state,
656 unsigned int *crtc_vblank_mask);
657 void (*audio_codec_enable)(struct drm_connector *connector,
658 struct intel_encoder *encoder,
659 const struct drm_display_mode *adjusted_mode);
660 void (*audio_codec_disable)(struct intel_encoder *encoder);
661 void (*fdi_link_train)(struct intel_crtc *crtc,
662 const struct intel_crtc_state *crtc_state);
663 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
664 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
665 struct drm_framebuffer *fb,
666 struct drm_i915_gem_object *obj,
667 struct drm_i915_gem_request *req,
669 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
670 /* clock updates for mode set */
672 /* render clock increase/decrease */
673 /* display clock increase/decrease */
674 /* pll clock increase/decrease */
676 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
677 void (*load_luts)(struct drm_crtc_state *crtc_state);
680 enum forcewake_domain_id {
681 FW_DOMAIN_ID_RENDER = 0,
682 FW_DOMAIN_ID_BLITTER,
688 enum forcewake_domains {
689 FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER),
690 FORCEWAKE_BLITTER = BIT(FW_DOMAIN_ID_BLITTER),
691 FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA),
692 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
697 #define FW_REG_READ (1)
698 #define FW_REG_WRITE (2)
700 enum decoupled_power_domain {
701 GEN9_DECOUPLED_PD_BLITTER = 0,
702 GEN9_DECOUPLED_PD_RENDER,
703 GEN9_DECOUPLED_PD_MEDIA,
704 GEN9_DECOUPLED_PD_ALL
708 GEN9_DECOUPLED_OP_WRITE = 0,
709 GEN9_DECOUPLED_OP_READ
712 enum forcewake_domains
713 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
714 i915_reg_t reg, unsigned int op);
716 struct intel_uncore_funcs {
717 void (*force_wake_get)(struct drm_i915_private *dev_priv,
718 enum forcewake_domains domains);
719 void (*force_wake_put)(struct drm_i915_private *dev_priv,
720 enum forcewake_domains domains);
722 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv,
723 i915_reg_t r, bool trace);
724 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv,
725 i915_reg_t r, bool trace);
726 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv,
727 i915_reg_t r, bool trace);
728 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv,
729 i915_reg_t r, bool trace);
731 void (*mmio_writeb)(struct drm_i915_private *dev_priv,
732 i915_reg_t r, uint8_t val, bool trace);
733 void (*mmio_writew)(struct drm_i915_private *dev_priv,
734 i915_reg_t r, uint16_t val, bool trace);
735 void (*mmio_writel)(struct drm_i915_private *dev_priv,
736 i915_reg_t r, uint32_t val, bool trace);
739 struct intel_forcewake_range {
743 enum forcewake_domains domains;
746 struct intel_uncore {
747 spinlock_t lock; /** lock is also taken in irq contexts. */
749 const struct intel_forcewake_range *fw_domains_table;
750 unsigned int fw_domains_table_entries;
752 struct notifier_block pmic_bus_access_nb;
753 struct intel_uncore_funcs funcs;
757 enum forcewake_domains fw_domains;
758 enum forcewake_domains fw_domains_active;
764 struct intel_uncore_forcewake_domain {
765 enum forcewake_domain_id id;
766 enum forcewake_domains mask;
768 struct hrtimer timer;
771 } fw_domain[FW_DOMAIN_ID_COUNT];
773 int unclaimed_mmio_check;
776 #define __mask_next_bit(mask) ({ \
777 int __idx = ffs(mask) - 1; \
778 mask &= ~BIT(__idx); \
782 /* Iterate over initialised fw domains */
783 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__, tmp__) \
784 for (tmp__ = (mask__); \
785 tmp__ ? (domain__ = &(dev_priv__)->uncore.fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
787 #define for_each_fw_domain(domain__, dev_priv__, tmp__) \
788 for_each_fw_domain_masked(domain__, (dev_priv__)->uncore.fw_domains, dev_priv__, tmp__)
790 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
791 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
792 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
795 struct work_struct work;
797 uint32_t *dmc_payload;
798 uint32_t dmc_fw_size;
801 i915_reg_t mmioaddr[8];
802 uint32_t mmiodata[8];
804 uint32_t allowed_dc_mask;
807 #define DEV_INFO_FOR_EACH_FLAG(func) \
810 func(is_alpha_support); \
811 /* Keep has_* in alphabetical order */ \
812 func(has_64bit_reloc); \
813 func(has_aliasing_ppgtt); \
816 func(has_decoupled_mmio); \
819 func(has_fpga_dbg); \
820 func(has_full_ppgtt); \
821 func(has_full_48bit_ppgtt); \
822 func(has_gmbus_irq); \
823 func(has_gmch_display); \
826 func(has_hw_contexts); \
829 func(has_logical_ring_contexts); \
831 func(has_pipe_cxsr); \
832 func(has_pooled_eu); \
836 func(has_resource_streamer); \
837 func(has_runtime_pm); \
839 func(unfenced_needs_alignment); \
840 func(cursor_needs_physical); \
841 func(hws_needs_physical); \
842 func(overlay_needs_physical); \
845 struct sseu_dev_info {
851 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
854 u8 has_subslice_pg:1;
858 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
860 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
863 /* Keep in gen based order, and chronological order within a gen */
864 enum intel_platform {
865 INTEL_PLATFORM_UNINITIALIZED = 0,
894 struct intel_device_info {
895 u32 display_mmio_offset;
898 u8 num_sprites[I915_MAX_PIPES];
899 u8 num_scalers[I915_MAX_PIPES];
902 enum intel_platform platform;
903 u8 ring_mask; /* Rings supported by the HW */
905 #define DEFINE_FLAG(name) u8 name:1
906 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
908 u16 ddb_size; /* in blocks */
909 /* Register offsets for the various display pipes and transcoders */
910 int pipe_offsets[I915_MAX_TRANSCODERS];
911 int trans_offsets[I915_MAX_TRANSCODERS];
912 int palette_offsets[I915_MAX_PIPES];
913 int cursor_offsets[I915_MAX_PIPES];
915 /* Slice/subslice/EU info */
916 struct sseu_dev_info sseu;
919 u16 degamma_lut_size;
924 struct intel_display_error_state;
926 struct i915_gpu_state {
929 struct timeval boottime;
930 struct timeval uptime;
932 struct drm_i915_private *i915;
942 struct intel_device_info device_info;
943 struct i915_params params;
945 /* Generic register state */
949 u32 gtier[4], ngtier;
953 u32 error; /* gen6+ */
954 u32 err_int; /* gen7 */
955 u32 fault_data0; /* gen8, gen9 */
956 u32 fault_data1; /* gen8, gen9 */
964 u64 fence[I915_MAX_NUM_FENCES];
965 struct intel_overlay_error_state *overlay;
966 struct intel_display_error_state *display;
967 struct drm_i915_error_object *semaphore;
968 struct drm_i915_error_object *guc_log;
970 struct drm_i915_error_engine {
972 /* Software tracked state */
975 unsigned long hangcheck_timestamp;
976 bool hangcheck_stalled;
977 enum intel_engine_hangcheck_action hangcheck_action;
978 struct i915_address_space *vm;
981 /* position of active request inside the ring */
982 u32 rq_head, rq_post, rq_tail;
984 /* our own tracking of ring head and tail */
1007 u32 rc_psmi; /* sleep state */
1008 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
1009 struct intel_instdone instdone;
1011 struct drm_i915_error_context {
1012 char comm[TASK_COMM_LEN];
1021 struct drm_i915_error_object {
1027 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
1029 struct drm_i915_error_object *wa_ctx;
1031 struct drm_i915_error_request {
1039 } *requests, execlist[2];
1041 struct drm_i915_error_waiter {
1042 char comm[TASK_COMM_LEN];
1054 } engine[I915_NUM_ENGINES];
1056 struct drm_i915_error_buffer {
1059 u32 rseqno[I915_NUM_ENGINES], wseqno;
1063 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
1070 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
1071 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
1072 struct i915_address_space *active_vm[I915_NUM_ENGINES];
1075 enum i915_cache_level {
1076 I915_CACHE_NONE = 0,
1077 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
1078 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
1079 caches, eg sampler/render caches, and the
1080 large Last-Level-Cache. LLC is coherent with
1081 the CPU, but L3 is only visible to the GPU. */
1082 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1085 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1096 /* This is always the inner lock when overlapping with struct_mutex and
1097 * it's the outer lock when overlapping with stolen_lock. */
1100 unsigned int possible_framebuffer_bits;
1101 unsigned int busy_bits;
1102 unsigned int visible_pipes_mask;
1103 struct intel_crtc *crtc;
1105 struct drm_mm_node compressed_fb;
1106 struct drm_mm_node *compressed_llb;
1113 bool underrun_detected;
1114 struct work_struct underrun_work;
1116 struct intel_fbc_state_cache {
1117 struct i915_vma *vma;
1120 unsigned int mode_flags;
1121 uint32_t hsw_bdw_pixel_rate;
1125 unsigned int rotation;
1132 const struct drm_format_info *format;
1133 unsigned int stride;
1137 struct intel_fbc_reg_params {
1138 struct i915_vma *vma;
1143 unsigned int fence_y_offset;
1147 const struct drm_format_info *format;
1148 unsigned int stride;
1154 struct intel_fbc_work {
1156 u32 scheduled_vblank;
1157 struct work_struct work;
1160 const char *no_fbc_reason;
1164 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1165 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1166 * parsing for same resolution.
1168 enum drrs_refresh_rate_type {
1171 DRRS_MAX_RR, /* RR count */
1174 enum drrs_support_type {
1175 DRRS_NOT_SUPPORTED = 0,
1176 STATIC_DRRS_SUPPORT = 1,
1177 SEAMLESS_DRRS_SUPPORT = 2
1183 struct delayed_work work;
1184 struct intel_dp *dp;
1185 unsigned busy_frontbuffer_bits;
1186 enum drrs_refresh_rate_type refresh_rate_type;
1187 enum drrs_support_type type;
1194 struct intel_dp *enabled;
1196 struct delayed_work work;
1197 unsigned busy_frontbuffer_bits;
1199 bool aux_frame_sync;
1201 bool y_cord_support;
1202 bool colorimetry_support;
1207 PCH_NONE = 0, /* No PCH present */
1208 PCH_IBX, /* Ibexpeak PCH */
1209 PCH_CPT, /* Cougarpoint PCH */
1210 PCH_LPT, /* Lynxpoint PCH */
1211 PCH_SPT, /* Sunrisepoint PCH */
1212 PCH_KBP, /* Kabypoint PCH */
1216 enum intel_sbi_destination {
1221 #define QUIRK_PIPEA_FORCE (1<<0)
1222 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1223 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1224 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1225 #define QUIRK_PIPEB_FORCE (1<<4)
1226 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1229 struct intel_fbc_work;
1231 struct intel_gmbus {
1232 struct i2c_adapter adapter;
1233 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1236 i915_reg_t gpio_reg;
1237 struct i2c_algo_bit_data bit_algo;
1238 struct drm_i915_private *dev_priv;
1241 struct i915_suspend_saved_registers {
1243 u32 saveFBC_CONTROL;
1244 u32 saveCACHE_MODE_0;
1245 u32 saveMI_ARB_STATE;
1249 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1250 u32 savePCH_PORT_HOTPLUG;
1254 struct vlv_s0ix_state {
1261 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1262 u32 media_max_req_count;
1263 u32 gfx_max_req_count;
1289 u32 rp_down_timeout;
1295 /* Display 1 CZ domain */
1300 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1302 /* GT SA CZ domain */
1309 /* Display 2 CZ domain */
1313 u32 clock_gate_dis2;
1316 struct intel_rps_ei {
1322 struct intel_gen6_power_mgmt {
1324 * work, interrupts_enabled and pm_iir are protected by
1325 * dev_priv->irq_lock
1327 struct work_struct work;
1328 bool interrupts_enabled;
1331 /* PM interrupt bits that should never be masked */
1334 /* Frequencies are stored in potentially platform dependent multiples.
1335 * In other words, *_freq needs to be multiplied by X to be interesting.
1336 * Soft limits are those which are used for the dynamic reclocking done
1337 * by the driver (raise frequencies under heavy loads, and lower for
1338 * lighter loads). Hard limits are those imposed by the hardware.
1340 * A distinction is made for overclocking, which is never enabled by
1341 * default, and is considered to be above the hard limit if it's
1344 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1345 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1346 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1347 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1348 u8 min_freq; /* AKA RPn. Minimum frequency */
1349 u8 boost_freq; /* Frequency to request when wait boosting */
1350 u8 idle_freq; /* Frequency to request when we are idle */
1351 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1352 u8 rp1_freq; /* "less than" RP0 power/freqency */
1353 u8 rp0_freq; /* Non-overclocked max frequency. */
1354 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1356 u8 up_threshold; /* Current %busy required to uplock */
1357 u8 down_threshold; /* Current %busy required to downclock */
1360 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1362 spinlock_t client_lock;
1363 struct list_head clients;
1367 struct delayed_work autoenable_work;
1370 /* manual wa residency calculations */
1371 struct intel_rps_ei ei;
1374 * Protects RPS/RC6 register access and PCU communication.
1375 * Must be taken after struct_mutex if nested. Note that
1376 * this lock may be held for long periods of time when
1377 * talking to hw - so only take it when talking to hw!
1379 struct mutex hw_lock;
1382 /* defined intel_pm.c */
1383 extern spinlock_t mchdev_lock;
1385 struct intel_ilk_power_mgmt {
1393 unsigned long last_time1;
1394 unsigned long chipset_power;
1397 unsigned long gfx_power;
1404 struct drm_i915_private;
1405 struct i915_power_well;
1407 struct i915_power_well_ops {
1409 * Synchronize the well's hw state to match the current sw state, for
1410 * example enable/disable it based on the current refcount. Called
1411 * during driver init and resume time, possibly after first calling
1412 * the enable/disable handlers.
1414 void (*sync_hw)(struct drm_i915_private *dev_priv,
1415 struct i915_power_well *power_well);
1417 * Enable the well and resources that depend on it (for example
1418 * interrupts located on the well). Called after the 0->1 refcount
1421 void (*enable)(struct drm_i915_private *dev_priv,
1422 struct i915_power_well *power_well);
1424 * Disable the well and resources that depend on it. Called after
1425 * the 1->0 refcount transition.
1427 void (*disable)(struct drm_i915_private *dev_priv,
1428 struct i915_power_well *power_well);
1429 /* Returns the hw enabled state. */
1430 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1431 struct i915_power_well *power_well);
1434 /* Power well structure for haswell */
1435 struct i915_power_well {
1438 /* power well enable/disable usage count */
1440 /* cached hw enabled state */
1443 /* unique identifier for this power well */
1446 * Arbitraty data associated with this power well. Platform and power
1450 const struct i915_power_well_ops *ops;
1453 struct i915_power_domains {
1455 * Power wells needed for initialization at driver init and suspend
1456 * time are on. They are kept on until after the first modeset.
1460 int power_well_count;
1463 int domain_use_count[POWER_DOMAIN_NUM];
1464 struct i915_power_well *power_wells;
1467 #define MAX_L3_SLICES 2
1468 struct intel_l3_parity {
1469 u32 *remap_info[MAX_L3_SLICES];
1470 struct work_struct error_work;
1474 struct i915_gem_mm {
1475 /** Memory allocator for GTT stolen memory */
1476 struct drm_mm stolen;
1477 /** Protects the usage of the GTT stolen memory allocator. This is
1478 * always the inner lock when overlapping with struct_mutex. */
1479 struct mutex stolen_lock;
1481 /** List of all objects in gtt_space. Used to restore gtt
1482 * mappings on resume */
1483 struct list_head bound_list;
1485 * List of objects which are not bound to the GTT (thus
1486 * are idle and not used by the GPU). These objects may or may
1487 * not actually have any pages attached.
1489 struct list_head unbound_list;
1491 /** List of all objects in gtt_space, currently mmaped by userspace.
1492 * All objects within this list must also be on bound_list.
1494 struct list_head userfault_list;
1497 * List of objects which are pending destruction.
1499 struct llist_head free_list;
1500 struct work_struct free_work;
1502 /** Usable portion of the GTT for GEM */
1503 dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1505 /** PPGTT used for aliasing the PPGTT with the GTT */
1506 struct i915_hw_ppgtt *aliasing_ppgtt;
1508 struct notifier_block oom_notifier;
1509 struct notifier_block vmap_notifier;
1510 struct shrinker shrinker;
1512 /** LRU list of objects with fence regs on them. */
1513 struct list_head fence_list;
1516 * Are we in a non-interruptible section of code like
1521 /* the indicator for dispatch video commands on two BSD rings */
1522 atomic_t bsd_engine_dispatch_index;
1524 /** Bit 6 swizzling required for X tiling */
1525 uint32_t bit_6_swizzle_x;
1526 /** Bit 6 swizzling required for Y tiling */
1527 uint32_t bit_6_swizzle_y;
1529 /* accounting, useful for userland debugging */
1530 spinlock_t object_stat_lock;
1535 struct drm_i915_error_state_buf {
1536 struct drm_i915_private *i915;
1545 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1546 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1548 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1549 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1551 struct i915_gpu_error {
1552 /* For hangcheck timer */
1553 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1554 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1556 struct delayed_work hangcheck_work;
1558 /* For reset and error_state handling. */
1560 /* Protected by the above dev->gpu_error.lock. */
1561 struct i915_gpu_state *first_error;
1563 unsigned long missed_irq_rings;
1566 * State variable controlling the reset flow and count
1568 * This is a counter which gets incremented when reset is triggered,
1570 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1571 * meaning that any waiters holding onto the struct_mutex should
1572 * relinquish the lock immediately in order for the reset to start.
1574 * If reset is not completed succesfully, the I915_WEDGE bit is
1575 * set meaning that hardware is terminally sour and there is no
1576 * recovery. All waiters on the reset_queue will be woken when
1579 * This counter is used by the wait_seqno code to notice that reset
1580 * event happened and it needs to restart the entire ioctl (since most
1581 * likely the seqno it waited for won't ever signal anytime soon).
1583 * This is important for lock-free wait paths, where no contended lock
1584 * naturally enforces the correct ordering between the bail-out of the
1585 * waiter and the gpu reset work code.
1587 unsigned long reset_count;
1590 * flags: Control various stages of the GPU reset
1592 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
1593 * other users acquiring the struct_mutex. To do this we set the
1594 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
1595 * and then check for that bit before acquiring the struct_mutex (in
1596 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
1597 * secondary role in preventing two concurrent global reset attempts.
1599 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
1600 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
1601 * but it may be held by some long running waiter (that we cannot
1602 * interrupt without causing trouble). Once we are ready to do the GPU
1603 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
1604 * they already hold the struct_mutex and want to participate they can
1605 * inspect the bit and do the reset directly, otherwise the worker
1606 * waits for the struct_mutex.
1608 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
1609 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
1610 * i915_gem_request_alloc(), this bit is checked and the sequence
1611 * aborted (with -EIO reported to userspace) if set.
1613 unsigned long flags;
1614 #define I915_RESET_BACKOFF 0
1615 #define I915_RESET_HANDOFF 1
1616 #define I915_WEDGED (BITS_PER_LONG - 1)
1619 * Waitqueue to signal when a hang is detected. Used to for waiters
1620 * to release the struct_mutex for the reset to procede.
1622 wait_queue_head_t wait_queue;
1625 * Waitqueue to signal when the reset has completed. Used by clients
1626 * that wait for dev_priv->mm.wedged to settle.
1628 wait_queue_head_t reset_queue;
1630 /* For missed irq/seqno simulation. */
1631 unsigned long test_irq_rings;
1634 enum modeset_restore {
1635 MODESET_ON_LID_OPEN,
1640 #define DP_AUX_A 0x40
1641 #define DP_AUX_B 0x10
1642 #define DP_AUX_C 0x20
1643 #define DP_AUX_D 0x30
1645 #define DDC_PIN_B 0x05
1646 #define DDC_PIN_C 0x04
1647 #define DDC_PIN_D 0x06
1649 struct ddi_vbt_port_info {
1651 * This is an index in the HDMI/DVI DDI buffer translation table.
1652 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1653 * populate this field.
1655 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1656 uint8_t hdmi_level_shift;
1658 uint8_t supports_dvi:1;
1659 uint8_t supports_hdmi:1;
1660 uint8_t supports_dp:1;
1661 uint8_t supports_edp:1;
1663 uint8_t alternate_aux_channel;
1664 uint8_t alternate_ddc_pin;
1666 uint8_t dp_boost_level;
1667 uint8_t hdmi_boost_level;
1670 enum psr_lines_to_wait {
1671 PSR_0_LINES_TO_WAIT = 0,
1673 PSR_4_LINES_TO_WAIT,
1677 struct intel_vbt_data {
1678 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1679 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1682 unsigned int int_tv_support:1;
1683 unsigned int lvds_dither:1;
1684 unsigned int lvds_vbt:1;
1685 unsigned int int_crt_support:1;
1686 unsigned int lvds_use_ssc:1;
1687 unsigned int display_clock_mode:1;
1688 unsigned int fdi_rx_polarity_inverted:1;
1689 unsigned int panel_type:4;
1691 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1693 enum drrs_support_type drrs_type;
1704 struct edp_power_seq pps;
1709 bool require_aux_wakeup;
1711 enum psr_lines_to_wait lines_to_wait;
1712 int tp1_wakeup_time;
1713 int tp2_tp3_wakeup_time;
1719 bool active_low_pwm;
1720 u8 min_brightness; /* min_brightness/255 of max */
1721 u8 controller; /* brightness controller number */
1722 enum intel_backlight_type type;
1728 struct mipi_config *config;
1729 struct mipi_pps_data *pps;
1733 const u8 *sequence[MIPI_SEQ_MAX];
1739 union child_device_config *child_dev;
1741 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1742 struct sdvo_device_mapping sdvo_mappings[2];
1745 enum intel_ddb_partitioning {
1747 INTEL_DDB_PART_5_6, /* IVB+ */
1750 struct intel_wm_level {
1758 struct ilk_wm_values {
1759 uint32_t wm_pipe[3];
1761 uint32_t wm_lp_spr[3];
1762 uint32_t wm_linetime[3];
1764 enum intel_ddb_partitioning partitioning;
1767 struct vlv_pipe_wm {
1768 uint16_t plane[I915_MAX_PLANES];
1776 struct vlv_wm_ddl_values {
1777 uint8_t plane[I915_MAX_PLANES];
1780 struct vlv_wm_values {
1781 struct vlv_pipe_wm pipe[3];
1782 struct vlv_sr_wm sr;
1783 struct vlv_wm_ddl_values ddl[3];
1788 struct skl_ddb_entry {
1789 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1792 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1794 return entry->end - entry->start;
1797 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1798 const struct skl_ddb_entry *e2)
1800 if (e1->start == e2->start && e1->end == e2->end)
1806 struct skl_ddb_allocation {
1807 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1808 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1811 struct skl_wm_values {
1812 unsigned dirty_pipes;
1813 struct skl_ddb_allocation ddb;
1816 struct skl_wm_level {
1818 uint16_t plane_res_b;
1819 uint8_t plane_res_l;
1823 * This struct helps tracking the state needed for runtime PM, which puts the
1824 * device in PCI D3 state. Notice that when this happens, nothing on the
1825 * graphics device works, even register access, so we don't get interrupts nor
1828 * Every piece of our code that needs to actually touch the hardware needs to
1829 * either call intel_runtime_pm_get or call intel_display_power_get with the
1830 * appropriate power domain.
1832 * Our driver uses the autosuspend delay feature, which means we'll only really
1833 * suspend if we stay with zero refcount for a certain amount of time. The
1834 * default value is currently very conservative (see intel_runtime_pm_enable), but
1835 * it can be changed with the standard runtime PM files from sysfs.
1837 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1838 * goes back to false exactly before we reenable the IRQs. We use this variable
1839 * to check if someone is trying to enable/disable IRQs while they're supposed
1840 * to be disabled. This shouldn't happen and we'll print some error messages in
1843 * For more, read the Documentation/power/runtime_pm.txt.
1845 struct i915_runtime_pm {
1846 atomic_t wakeref_count;
1851 enum intel_pipe_crc_source {
1852 INTEL_PIPE_CRC_SOURCE_NONE,
1853 INTEL_PIPE_CRC_SOURCE_PLANE1,
1854 INTEL_PIPE_CRC_SOURCE_PLANE2,
1855 INTEL_PIPE_CRC_SOURCE_PF,
1856 INTEL_PIPE_CRC_SOURCE_PIPE,
1857 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1858 INTEL_PIPE_CRC_SOURCE_TV,
1859 INTEL_PIPE_CRC_SOURCE_DP_B,
1860 INTEL_PIPE_CRC_SOURCE_DP_C,
1861 INTEL_PIPE_CRC_SOURCE_DP_D,
1862 INTEL_PIPE_CRC_SOURCE_AUTO,
1863 INTEL_PIPE_CRC_SOURCE_MAX,
1866 struct intel_pipe_crc_entry {
1871 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1872 struct intel_pipe_crc {
1874 bool opened; /* exclusive access to the result file */
1875 struct intel_pipe_crc_entry *entries;
1876 enum intel_pipe_crc_source source;
1878 wait_queue_head_t wq;
1882 struct i915_frontbuffer_tracking {
1886 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1893 struct i915_wa_reg {
1896 /* bitmask representing WA bits */
1901 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1902 * allowing it for RCS as we don't foresee any requirement of having
1903 * a whitelist for other engines. When it is really required for
1904 * other engines then the limit need to be increased.
1906 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1908 struct i915_workarounds {
1909 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1911 u32 hw_whitelist_count[I915_NUM_ENGINES];
1914 struct i915_virtual_gpu {
1918 /* used in computing the new watermarks state */
1919 struct intel_wm_config {
1920 unsigned int num_pipes_active;
1921 bool sprites_enabled;
1922 bool sprites_scaled;
1925 struct i915_oa_format {
1930 struct i915_oa_reg {
1935 struct i915_perf_stream;
1938 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1940 struct i915_perf_stream_ops {
1942 * @enable: Enables the collection of HW samples, either in response to
1943 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1944 * without `I915_PERF_FLAG_DISABLED`.
1946 void (*enable)(struct i915_perf_stream *stream);
1949 * @disable: Disables the collection of HW samples, either in response
1950 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1953 void (*disable)(struct i915_perf_stream *stream);
1956 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1957 * once there is something ready to read() for the stream
1959 void (*poll_wait)(struct i915_perf_stream *stream,
1964 * @wait_unlocked: For handling a blocking read, wait until there is
1965 * something to ready to read() for the stream. E.g. wait on the same
1966 * wait queue that would be passed to poll_wait().
1968 int (*wait_unlocked)(struct i915_perf_stream *stream);
1971 * @read: Copy buffered metrics as records to userspace
1972 * **buf**: the userspace, destination buffer
1973 * **count**: the number of bytes to copy, requested by userspace
1974 * **offset**: zero at the start of the read, updated as the read
1975 * proceeds, it represents how many bytes have been copied so far and
1976 * the buffer offset for copying the next record.
1978 * Copy as many buffered i915 perf samples and records for this stream
1979 * to userspace as will fit in the given buffer.
1981 * Only write complete records; returning -%ENOSPC if there isn't room
1982 * for a complete record.
1984 * Return any error condition that results in a short read such as
1985 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1986 * returning to userspace.
1988 int (*read)(struct i915_perf_stream *stream,
1994 * @destroy: Cleanup any stream specific resources.
1996 * The stream will always be disabled before this is called.
1998 void (*destroy)(struct i915_perf_stream *stream);
2002 * struct i915_perf_stream - state for a single open stream FD
2004 struct i915_perf_stream {
2006 * @dev_priv: i915 drm device
2008 struct drm_i915_private *dev_priv;
2011 * @link: Links the stream into ``&drm_i915_private->streams``
2013 struct list_head link;
2016 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
2017 * properties given when opening a stream, representing the contents
2018 * of a single sample as read() by userspace.
2023 * @sample_size: Considering the configured contents of a sample
2024 * combined with the required header size, this is the total size
2025 * of a single sample record.
2030 * @ctx: %NULL if measuring system-wide across all contexts or a
2031 * specific context that is being monitored.
2033 struct i915_gem_context *ctx;
2036 * @enabled: Whether the stream is currently enabled, considering
2037 * whether the stream was opened in a disabled state and based
2038 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
2043 * @ops: The callbacks providing the implementation of this specific
2044 * type of configured stream.
2046 const struct i915_perf_stream_ops *ops;
2050 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2052 struct i915_oa_ops {
2054 * @init_oa_buffer: Resets the head and tail pointers of the
2055 * circular buffer for periodic OA reports.
2057 * Called when first opening a stream for OA metrics, but also may be
2058 * called in response to an OA buffer overflow or other error
2061 * Note it may be necessary to clear the full OA buffer here as part of
2062 * maintaining the invariable that new reports must be written to
2063 * zeroed memory for us to be able to reliable detect if an expected
2064 * report has not yet landed in memory. (At least on Haswell the OA
2065 * buffer tail pointer is not synchronized with reports being visible
2068 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2071 * @enable_metric_set: Applies any MUX configuration to set up the
2072 * Boolean and Custom (B/C) counters that are part of the counter
2073 * reports being sampled. May apply system constraints such as
2074 * disabling EU clock gating as required.
2076 int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2079 * @disable_metric_set: Remove system constraints associated with using
2082 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2085 * @oa_enable: Enable periodic sampling
2087 void (*oa_enable)(struct drm_i915_private *dev_priv);
2090 * @oa_disable: Disable periodic sampling
2092 void (*oa_disable)(struct drm_i915_private *dev_priv);
2095 * @read: Copy data from the circular OA buffer into a given userspace
2098 int (*read)(struct i915_perf_stream *stream,
2104 * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
2106 * This is either called via fops or the poll check hrtimer (atomic
2107 * ctx) without any locks taken.
2109 * It's safe to read OA config state here unlocked, assuming that this
2110 * is only called while the stream is enabled, while the global OA
2111 * configuration can't be modified.
2113 * Efficiency is more important than avoiding some false positives
2114 * here, which will be handled gracefully - likely resulting in an
2115 * %EAGAIN error for userspace.
2117 bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
2120 struct intel_cdclk_state {
2121 unsigned int cdclk, vco, ref;
2124 struct drm_i915_private {
2125 struct drm_device drm;
2127 struct kmem_cache *objects;
2128 struct kmem_cache *vmas;
2129 struct kmem_cache *requests;
2130 struct kmem_cache *dependencies;
2132 const struct intel_device_info info;
2136 struct intel_uncore uncore;
2138 struct i915_virtual_gpu vgpu;
2140 struct intel_gvt *gvt;
2142 struct intel_huc huc;
2143 struct intel_guc guc;
2145 struct intel_csr csr;
2147 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2149 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2150 * controller on different i2c buses. */
2151 struct mutex gmbus_mutex;
2154 * Base address of the gmbus and gpio block.
2156 uint32_t gpio_mmio_base;
2158 /* MMIO base address for MIPI regs */
2159 uint32_t mipi_mmio_base;
2161 uint32_t psr_mmio_base;
2163 uint32_t pps_mmio_base;
2165 wait_queue_head_t gmbus_wait_queue;
2167 struct pci_dev *bridge_dev;
2168 struct i915_gem_context *kernel_context;
2169 struct intel_engine_cs *engine[I915_NUM_ENGINES];
2170 struct i915_vma *semaphore;
2172 struct drm_dma_handle *status_page_dmah;
2173 struct resource mch_res;
2175 /* protects the irq masks */
2176 spinlock_t irq_lock;
2178 /* protects the mmio flip data */
2179 spinlock_t mmio_flip_lock;
2181 bool display_irqs_enabled;
2183 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2184 struct pm_qos_request pm_qos;
2186 /* Sideband mailbox protection */
2187 struct mutex sb_lock;
2189 /** Cached value of IMR to avoid reads in updating the bitfield */
2192 u32 de_irq_mask[I915_MAX_PIPES];
2199 u32 pipestat_irq_mask[I915_MAX_PIPES];
2201 struct i915_hotplug hotplug;
2202 struct intel_fbc fbc;
2203 struct i915_drrs drrs;
2204 struct intel_opregion opregion;
2205 struct intel_vbt_data vbt;
2207 bool preserve_bios_swizzle;
2210 struct intel_overlay *overlay;
2212 /* backlight registers and fields in struct intel_panel */
2213 struct mutex backlight_lock;
2216 bool no_aux_handshake;
2218 /* protects panel power sequencer state */
2219 struct mutex pps_mutex;
2221 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
2222 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
2224 unsigned int fsb_freq, mem_freq, is_ddr3;
2225 unsigned int skl_preferred_vco_freq;
2226 unsigned int max_cdclk_freq;
2228 unsigned int max_dotclk_freq;
2229 unsigned int rawclk_freq;
2230 unsigned int hpll_freq;
2231 unsigned int czclk_freq;
2235 * The current logical cdclk state.
2236 * See intel_atomic_state.cdclk.logical
2238 * For reading holding any crtc lock is sufficient,
2239 * for writing must hold all of them.
2241 struct intel_cdclk_state logical;
2243 * The current actual cdclk state.
2244 * See intel_atomic_state.cdclk.actual
2246 struct intel_cdclk_state actual;
2247 /* The current hardware cdclk state */
2248 struct intel_cdclk_state hw;
2252 * wq - Driver workqueue for GEM.
2254 * NOTE: Work items scheduled here are not allowed to grab any modeset
2255 * locks, for otherwise the flushing done in the pageflip code will
2256 * result in deadlocks.
2258 struct workqueue_struct *wq;
2260 /* Display functions */
2261 struct drm_i915_display_funcs display;
2263 /* PCH chipset type */
2264 enum intel_pch pch_type;
2265 unsigned short pch_id;
2267 unsigned long quirks;
2269 enum modeset_restore modeset_restore;
2270 struct mutex modeset_restore_lock;
2271 struct drm_atomic_state *modeset_restore_state;
2272 struct drm_modeset_acquire_ctx reset_ctx;
2274 struct list_head vm_list; /* Global list of all address spaces */
2275 struct i915_ggtt ggtt; /* VM representing the global address space */
2277 struct i915_gem_mm mm;
2278 DECLARE_HASHTABLE(mm_structs, 7);
2279 struct mutex mm_lock;
2281 /* The hw wants to have a stable context identifier for the lifetime
2282 * of the context (for OA, PASID, faults, etc). This is limited
2283 * in execlists to 21 bits.
2285 struct ida context_hw_ida;
2286 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2288 /* Kernel Modesetting */
2290 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2291 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2292 wait_queue_head_t pending_flip_queue;
2294 #ifdef CONFIG_DEBUG_FS
2295 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2298 /* dpll and cdclk state is protected by connection_mutex */
2299 int num_shared_dpll;
2300 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2301 const struct intel_dpll_mgr *dpll_mgr;
2304 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2305 * Must be global rather than per dpll, because on some platforms
2306 * plls share registers.
2308 struct mutex dpll_lock;
2310 unsigned int active_crtcs;
2311 unsigned int min_pixclk[I915_MAX_PIPES];
2313 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2315 struct i915_workarounds workarounds;
2317 struct i915_frontbuffer_tracking fb_tracking;
2319 struct intel_atomic_helper {
2320 struct llist_head free_list;
2321 struct work_struct free_work;
2326 bool mchbar_need_disable;
2328 struct intel_l3_parity l3_parity;
2330 /* Cannot be determined by PCIID. You must always read a register. */
2333 /* gen6+ rps state */
2334 struct intel_gen6_power_mgmt rps;
2336 /* ilk-only ips/rps state. Everything in here is protected by the global
2337 * mchdev_lock in intel_pm.c */
2338 struct intel_ilk_power_mgmt ips;
2340 struct i915_power_domains power_domains;
2342 struct i915_psr psr;
2344 struct i915_gpu_error gpu_error;
2346 struct drm_i915_gem_object *vlv_pctx;
2348 #ifdef CONFIG_DRM_FBDEV_EMULATION
2349 /* list of fbdev register on this device */
2350 struct intel_fbdev *fbdev;
2351 struct work_struct fbdev_suspend_work;
2354 struct drm_property *broadcast_rgb_property;
2355 struct drm_property *force_audio_property;
2357 /* hda/i915 audio component */
2358 struct i915_audio_component *audio_component;
2359 bool audio_component_registered;
2361 * av_mutex - mutex for audio/video sync
2364 struct mutex av_mutex;
2366 uint32_t hw_context_size;
2367 struct list_head context_list;
2371 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2372 u32 chv_phy_control;
2374 * Shadows for CHV DPLL_MD regs to keep the state
2375 * checker somewhat working in the presence hardware
2376 * crappiness (can't read out DPLL_MD for pipes B & C).
2378 u32 chv_dpll_md[I915_MAX_PIPES];
2382 bool suspended_to_idle;
2383 struct i915_suspend_saved_registers regfile;
2384 struct vlv_s0ix_state vlv_s0ix_state;
2387 I915_SAGV_UNKNOWN = 0,
2390 I915_SAGV_NOT_CONTROLLED
2395 * Raw watermark latency values:
2396 * in 0.1us units for WM0,
2397 * in 0.5us units for WM1+.
2400 uint16_t pri_latency[5];
2402 uint16_t spr_latency[5];
2404 uint16_t cur_latency[5];
2406 * Raw watermark memory latency values
2407 * for SKL for all 8 levels
2410 uint16_t skl_latency[8];
2412 /* current hardware state */
2414 struct ilk_wm_values hw;
2415 struct skl_wm_values skl_hw;
2416 struct vlv_wm_values vlv;
2422 * Should be held around atomic WM register writing; also
2423 * protects * intel_crtc->wm.active and
2424 * cstate->wm.need_postvbl_update.
2426 struct mutex wm_mutex;
2429 * Set during HW readout of watermarks/DDB. Some platforms
2430 * need to know when we're still using BIOS-provided values
2431 * (which we don't fully trust).
2433 bool distrust_bios_wm;
2436 struct i915_runtime_pm pm;
2441 struct kobject *metrics_kobj;
2442 struct ctl_table_header *sysctl_header;
2445 struct list_head streams;
2447 spinlock_t hook_lock;
2450 struct i915_perf_stream *exclusive_stream;
2452 u32 specific_ctx_id;
2454 struct hrtimer poll_check_timer;
2455 wait_queue_head_t poll_wq;
2459 int period_exponent;
2460 int timestamp_frequency;
2466 const struct i915_oa_reg *mux_regs;
2468 const struct i915_oa_reg *b_counter_regs;
2469 int b_counter_regs_len;
2472 struct i915_vma *vma;
2478 u32 gen7_latched_oastatus1;
2480 struct i915_oa_ops ops;
2481 const struct i915_oa_format *oa_formats;
2486 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2488 void (*resume)(struct drm_i915_private *);
2489 void (*cleanup_engine)(struct intel_engine_cs *engine);
2491 struct list_head timelines;
2492 struct i915_gem_timeline global_timeline;
2493 u32 active_requests;
2496 * Is the GPU currently considered idle, or busy executing
2497 * userspace requests? Whilst idle, we allow runtime power
2498 * management to power down the hardware and display clocks.
2499 * In order to reduce the effect on performance, there
2500 * is a slight delay before we do so.
2505 * We leave the user IRQ off as much as possible,
2506 * but this means that requests will finish and never
2507 * be retired once the system goes idle. Set a timer to
2508 * fire periodically while the ring is running. When it
2509 * fires, go retire requests.
2511 struct delayed_work retire_work;
2514 * When we detect an idle GPU, we want to turn on
2515 * powersaving features. So once we see that there
2516 * are no more requests outstanding and no more
2517 * arrive within a small period of time, we fire
2518 * off the idle_work.
2520 struct delayed_work idle_work;
2522 ktime_t last_init_time;
2525 /* perform PHY state sanity checks? */
2526 bool chv_phy_assert[2];
2530 /* Used to save the pipe-to-encoder mapping for audio */
2531 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2533 /* necessary resource sharing with HDMI LPE audio driver. */
2535 struct platform_device *platdev;
2540 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2541 * will be rejected. Instead look for a better place.
2545 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2547 return container_of(dev, struct drm_i915_private, drm);
2550 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2552 return to_i915(dev_get_drvdata(kdev));
2555 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2557 return container_of(guc, struct drm_i915_private, guc);
2560 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2562 return container_of(huc, struct drm_i915_private, huc);
2565 /* Simple iterator over all initialised engines */
2566 #define for_each_engine(engine__, dev_priv__, id__) \
2568 (id__) < I915_NUM_ENGINES; \
2570 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2572 /* Iterator over subset of engines selected by mask */
2573 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2574 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2575 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2577 enum hdmi_force_audio {
2578 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2579 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2580 HDMI_AUDIO_AUTO, /* trust EDID */
2581 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2584 #define I915_GTT_OFFSET_NONE ((u32)-1)
2587 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2588 * considered to be the frontbuffer for the given plane interface-wise. This
2589 * doesn't mean that the hw necessarily already scans it out, but that any
2590 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2592 * We have one bit per pipe and per scanout plane type.
2594 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2595 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2596 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2597 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2598 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2599 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2600 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2601 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2602 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2603 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2604 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2605 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2608 * Optimised SGL iterator for GEM objects
2610 static __always_inline struct sgt_iter {
2611 struct scatterlist *sgp;
2618 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2619 struct sgt_iter s = { .sgp = sgl };
2622 s.max = s.curr = s.sgp->offset;
2623 s.max += s.sgp->length;
2625 s.dma = sg_dma_address(s.sgp);
2627 s.pfn = page_to_pfn(sg_page(s.sgp));
2633 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2636 if (unlikely(sg_is_chain(sg)))
2637 sg = sg_chain_ptr(sg);
2642 * __sg_next - return the next scatterlist entry in a list
2643 * @sg: The current sg entry
2646 * If the entry is the last, return NULL; otherwise, step to the next
2647 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2648 * otherwise just return the pointer to the current element.
2650 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2652 #ifdef CONFIG_DEBUG_SG
2653 BUG_ON(sg->sg_magic != SG_MAGIC);
2655 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2659 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2660 * @__dmap: DMA address (output)
2661 * @__iter: 'struct sgt_iter' (iterator state, internal)
2662 * @__sgt: sg_table to iterate over (input)
2664 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2665 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2666 ((__dmap) = (__iter).dma + (__iter).curr); \
2667 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2668 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2671 * for_each_sgt_page - iterate over the pages of the given sg_table
2672 * @__pp: page pointer (output)
2673 * @__iter: 'struct sgt_iter' (iterator state, internal)
2674 * @__sgt: sg_table to iterate over (input)
2676 #define for_each_sgt_page(__pp, __iter, __sgt) \
2677 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2678 ((__pp) = (__iter).pfn == 0 ? NULL : \
2679 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2680 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2681 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2683 static inline const struct intel_device_info *
2684 intel_info(const struct drm_i915_private *dev_priv)
2686 return &dev_priv->info;
2689 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2691 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2692 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2694 #define REVID_FOREVER 0xff
2695 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2697 #define GEN_FOREVER (0)
2699 * Returns true if Gen is in inclusive range [Start, End].
2701 * Use GEN_FOREVER for unbound start and or end.
2703 #define IS_GEN(dev_priv, s, e) ({ \
2704 unsigned int __s = (s), __e = (e); \
2705 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2706 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2707 if ((__s) != GEN_FOREVER) \
2709 if ((__e) == GEN_FOREVER) \
2710 __e = BITS_PER_LONG - 1; \
2713 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2717 * Return true if revision is in range [since,until] inclusive.
2719 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2721 #define IS_REVID(p, since, until) \
2722 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2724 #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830)
2725 #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G)
2726 #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
2727 #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G)
2728 #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
2729 #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM)
2730 #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G)
2731 #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
2732 #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G)
2733 #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM)
2734 #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45)
2735 #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45)
2736 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2737 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2738 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2739 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW)
2740 #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2741 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2742 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2743 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2744 INTEL_DEVID(dev_priv) == 0x0152 || \
2745 INTEL_DEVID(dev_priv) == 0x015a)
2746 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2747 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2748 #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
2749 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
2750 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
2751 #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
2752 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
2753 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2754 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2755 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2756 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2757 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2758 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2759 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2760 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2761 /* ULX machines are also considered ULT. */
2762 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2763 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2764 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2765 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2766 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2767 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2768 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2769 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2770 /* ULX machines are also considered ULT. */
2771 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2772 INTEL_DEVID(dev_priv) == 0x0A1E)
2773 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2774 INTEL_DEVID(dev_priv) == 0x1913 || \
2775 INTEL_DEVID(dev_priv) == 0x1916 || \
2776 INTEL_DEVID(dev_priv) == 0x1921 || \
2777 INTEL_DEVID(dev_priv) == 0x1926)
2778 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2779 INTEL_DEVID(dev_priv) == 0x1915 || \
2780 INTEL_DEVID(dev_priv) == 0x191E)
2781 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2782 INTEL_DEVID(dev_priv) == 0x5913 || \
2783 INTEL_DEVID(dev_priv) == 0x5916 || \
2784 INTEL_DEVID(dev_priv) == 0x5921 || \
2785 INTEL_DEVID(dev_priv) == 0x5926)
2786 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2787 INTEL_DEVID(dev_priv) == 0x5915 || \
2788 INTEL_DEVID(dev_priv) == 0x591E)
2789 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2790 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2791 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2792 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2794 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2796 #define SKL_REVID_A0 0x0
2797 #define SKL_REVID_B0 0x1
2798 #define SKL_REVID_C0 0x2
2799 #define SKL_REVID_D0 0x3
2800 #define SKL_REVID_E0 0x4
2801 #define SKL_REVID_F0 0x5
2802 #define SKL_REVID_G0 0x6
2803 #define SKL_REVID_H0 0x7
2805 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2807 #define BXT_REVID_A0 0x0
2808 #define BXT_REVID_A1 0x1
2809 #define BXT_REVID_B0 0x3
2810 #define BXT_REVID_B_LAST 0x8
2811 #define BXT_REVID_C0 0x9
2813 #define IS_BXT_REVID(dev_priv, since, until) \
2814 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2816 #define KBL_REVID_A0 0x0
2817 #define KBL_REVID_B0 0x1
2818 #define KBL_REVID_C0 0x2
2819 #define KBL_REVID_D0 0x3
2820 #define KBL_REVID_E0 0x4
2822 #define IS_KBL_REVID(dev_priv, since, until) \
2823 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2825 #define GLK_REVID_A0 0x0
2826 #define GLK_REVID_A1 0x1
2828 #define IS_GLK_REVID(dev_priv, since, until) \
2829 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2832 * The genX designation typically refers to the render engine, so render
2833 * capability related checks should use IS_GEN, while display and other checks
2834 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2837 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2838 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2839 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2840 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2841 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2842 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2843 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2844 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2846 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2847 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2848 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2850 #define ENGINE_MASK(id) BIT(id)
2851 #define RENDER_RING ENGINE_MASK(RCS)
2852 #define BSD_RING ENGINE_MASK(VCS)
2853 #define BLT_RING ENGINE_MASK(BCS)
2854 #define VEBOX_RING ENGINE_MASK(VECS)
2855 #define BSD2_RING ENGINE_MASK(VCS2)
2856 #define ALL_ENGINES (~0)
2858 #define HAS_ENGINE(dev_priv, id) \
2859 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2861 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2862 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2863 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2864 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2866 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2867 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2868 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2869 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2870 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2872 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2874 #define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts)
2875 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2876 ((dev_priv)->info.has_logical_ring_contexts)
2877 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2878 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2879 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2881 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2882 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2883 ((dev_priv)->info.overlay_needs_physical)
2885 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2886 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2888 /* WaRsDisableCoarsePowerGating:skl,bxt */
2889 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2890 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2893 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2894 * even when in MSI mode. This results in spurious interrupt warnings if the
2895 * legacy irq no. is shared with another device. The kernel then disables that
2896 * interrupt source and so prevents the other device from working properly.
2898 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2899 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2901 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2902 * rows, which changed the alignment requirements and fence programming.
2904 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2905 !(IS_I915G(dev_priv) || \
2906 IS_I915GM(dev_priv)))
2907 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2908 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2910 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2911 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2912 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2914 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2916 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2918 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2919 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2920 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2921 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2922 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2924 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2926 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2927 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2930 * For now, anything with a GuC requires uCode loading, and then supports
2931 * command submission once loaded. But these are logically independent
2932 * properties, so we have separate macros to test them.
2934 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2935 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2936 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2937 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2939 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2941 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2943 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2944 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2945 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2946 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2947 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2948 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2949 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2950 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2951 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2952 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2953 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2954 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2956 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2957 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2958 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2959 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2960 #define HAS_PCH_LPT_LP(dev_priv) \
2961 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2962 #define HAS_PCH_LPT_H(dev_priv) \
2963 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2964 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2965 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2966 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2967 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2969 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2971 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2973 /* DPF == dynamic parity feature */
2974 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2975 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2976 2 : HAS_L3_DPF(dev_priv))
2978 #define GT_FREQUENCY_MULTIPLIER 50
2979 #define GEN9_FREQ_SCALER 3
2981 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2983 #include "i915_trace.h"
2985 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2987 #ifdef CONFIG_INTEL_IOMMU
2988 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2995 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2997 #ifdef CONFIG_INTEL_IOMMU
2998 if (IS_BROXTON(dev_priv) && intel_iommu_gfx_mapped)
3004 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
3007 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
3011 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
3012 const char *fmt, ...);
3014 #define i915_report_error(dev_priv, fmt, ...) \
3015 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
3017 #ifdef CONFIG_COMPAT
3018 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
3021 #define i915_compat_ioctl NULL
3023 extern const struct dev_pm_ops i915_pm_ops;
3025 extern int i915_driver_load(struct pci_dev *pdev,
3026 const struct pci_device_id *ent);
3027 extern void i915_driver_unload(struct drm_device *dev);
3028 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
3029 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
3030 extern void i915_reset(struct drm_i915_private *dev_priv);
3031 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
3032 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
3033 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
3034 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
3035 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
3036 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
3037 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
3038 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3040 int intel_engines_init_early(struct drm_i915_private *dev_priv);
3041 int intel_engines_init(struct drm_i915_private *dev_priv);
3043 /* intel_hotplug.c */
3044 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
3045 u32 pin_mask, u32 long_mask);
3046 void intel_hpd_init(struct drm_i915_private *dev_priv);
3047 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
3048 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3049 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3050 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3051 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3054 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
3056 unsigned long delay;
3058 if (unlikely(!i915.enable_hangcheck))
3061 /* Don't continually defer the hangcheck so that it is always run at
3062 * least once after work has been scheduled on any ring. Otherwise,
3063 * we will ignore a hung ring if a second ring is kept busy.
3066 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
3067 queue_delayed_work(system_long_wq,
3068 &dev_priv->gpu_error.hangcheck_work, delay);
3072 void i915_handle_error(struct drm_i915_private *dev_priv,
3074 const char *fmt, ...);
3076 extern void intel_irq_init(struct drm_i915_private *dev_priv);
3077 int intel_irq_install(struct drm_i915_private *dev_priv);
3078 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3080 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
3081 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
3082 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
3083 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
3084 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
3085 extern void intel_uncore_suspend(struct drm_i915_private *dev_priv);
3086 extern void intel_uncore_resume_early(struct drm_i915_private *dev_priv);
3087 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
3088 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
3089 enum forcewake_domains domains);
3090 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
3091 enum forcewake_domains domains);
3092 /* Like above but the caller must manage the uncore.lock itself.
3093 * Must be used with I915_READ_FW and friends.
3095 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
3096 enum forcewake_domains domains);
3097 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
3098 enum forcewake_domains domains);
3099 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
3101 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
3103 int intel_wait_for_register(struct drm_i915_private *dev_priv,
3107 const unsigned long timeout_ms);
3108 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
3112 const unsigned long timeout_ms);
3114 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3116 return dev_priv->gvt;
3119 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3121 return dev_priv->vgpu.active;
3125 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3129 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3132 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3133 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3134 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3137 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3138 uint32_t interrupt_mask,
3139 uint32_t enabled_irq_mask);
3141 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3143 ilk_update_display_irq(dev_priv, bits, bits);
3146 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3148 ilk_update_display_irq(dev_priv, bits, 0);
3150 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3152 uint32_t interrupt_mask,
3153 uint32_t enabled_irq_mask);
3154 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3155 enum pipe pipe, uint32_t bits)
3157 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3159 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3160 enum pipe pipe, uint32_t bits)
3162 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3164 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3165 uint32_t interrupt_mask,
3166 uint32_t enabled_irq_mask);
3168 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3170 ibx_display_interrupt_update(dev_priv, bits, bits);
3173 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3175 ibx_display_interrupt_update(dev_priv, bits, 0);
3179 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3180 struct drm_file *file_priv);
3181 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3182 struct drm_file *file_priv);
3183 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3184 struct drm_file *file_priv);
3185 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3186 struct drm_file *file_priv);
3187 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3188 struct drm_file *file_priv);
3189 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3190 struct drm_file *file_priv);
3191 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3192 struct drm_file *file_priv);
3193 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3194 struct drm_file *file_priv);
3195 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3196 struct drm_file *file_priv);
3197 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3198 struct drm_file *file_priv);
3199 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3200 struct drm_file *file);
3201 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3202 struct drm_file *file);
3203 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3204 struct drm_file *file_priv);
3205 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3206 struct drm_file *file_priv);
3207 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
3208 struct drm_file *file_priv);
3209 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
3210 struct drm_file *file_priv);
3211 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3212 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3213 struct drm_file *file);
3214 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3215 struct drm_file *file_priv);
3216 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3217 struct drm_file *file_priv);
3218 void i915_gem_sanitize(struct drm_i915_private *i915);
3219 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3220 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3221 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3222 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3223 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3225 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3226 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3227 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3228 const struct drm_i915_gem_object_ops *ops);
3229 struct drm_i915_gem_object *
3230 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3231 struct drm_i915_gem_object *
3232 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3233 const void *data, size_t size);
3234 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3235 void i915_gem_free_object(struct drm_gem_object *obj);
3237 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
3239 /* A single pass should suffice to release all the freed objects (along
3240 * most call paths) , but be a little more paranoid in that freeing
3241 * the objects does take a little amount of time, during which the rcu
3242 * callbacks could have added new objects into the freed list, and
3243 * armed the work again.
3247 } while (flush_work(&i915->mm.free_work));
3250 struct i915_vma * __must_check
3251 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3252 const struct i915_ggtt_view *view,
3257 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3258 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3260 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3262 static inline int __sg_page_count(const struct scatterlist *sg)
3264 return sg->length >> PAGE_SHIFT;
3267 struct scatterlist *
3268 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3269 unsigned int n, unsigned int *offset);
3272 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3276 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3280 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3283 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3284 struct sg_table *pages);
3285 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3287 static inline int __must_check
3288 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3290 might_lock(&obj->mm.lock);
3292 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3295 return __i915_gem_object_get_pages(obj);
3299 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3301 GEM_BUG_ON(!obj->mm.pages);
3303 atomic_inc(&obj->mm.pages_pin_count);
3307 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3309 return atomic_read(&obj->mm.pages_pin_count);
3313 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3315 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3316 GEM_BUG_ON(!obj->mm.pages);
3318 atomic_dec(&obj->mm.pages_pin_count);
3322 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3324 __i915_gem_object_unpin_pages(obj);
3327 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3332 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3333 enum i915_mm_subclass subclass);
3334 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3336 enum i915_map_type {
3342 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3343 * @obj: the object to map into kernel address space
3344 * @type: the type of mapping, used to select pgprot_t
3346 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3347 * pages and then returns a contiguous mapping of the backing storage into
3348 * the kernel address space. Based on the @type of mapping, the PTE will be
3349 * set to either WriteBack or WriteCombine (via pgprot_t).
3351 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3352 * mapping is no longer required.
3354 * Returns the pointer through which to access the mapped object, or an
3355 * ERR_PTR() on error.
3357 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3358 enum i915_map_type type);
3361 * i915_gem_object_unpin_map - releases an earlier mapping
3362 * @obj: the object to unmap
3364 * After pinning the object and mapping its pages, once you are finished
3365 * with your access, call i915_gem_object_unpin_map() to release the pin
3366 * upon the mapping. Once the pin count reaches zero, that mapping may be
3369 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3371 i915_gem_object_unpin_pages(obj);
3374 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3375 unsigned int *needs_clflush);
3376 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3377 unsigned int *needs_clflush);
3378 #define CLFLUSH_BEFORE BIT(0)
3379 #define CLFLUSH_AFTER BIT(1)
3380 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3383 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3385 i915_gem_object_unpin_pages(obj);
3388 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3389 void i915_vma_move_to_active(struct i915_vma *vma,
3390 struct drm_i915_gem_request *req,
3391 unsigned int flags);
3392 int i915_gem_dumb_create(struct drm_file *file_priv,
3393 struct drm_device *dev,
3394 struct drm_mode_create_dumb *args);
3395 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3396 uint32_t handle, uint64_t *offset);
3397 int i915_gem_mmap_gtt_version(void);
3399 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3400 struct drm_i915_gem_object *new,
3401 unsigned frontbuffer_bits);
3403 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3405 struct drm_i915_gem_request *
3406 i915_gem_find_active_request(struct intel_engine_cs *engine);
3408 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3410 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
3412 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3415 static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3417 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3420 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3422 return unlikely(test_bit(I915_WEDGED, &error->flags));
3425 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3427 return i915_reset_backoff(error) | i915_terminally_wedged(error);
3430 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3432 return READ_ONCE(error->reset_count);
3435 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3436 void i915_gem_reset(struct drm_i915_private *dev_priv);
3437 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3438 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3439 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3441 void i915_gem_init_mmio(struct drm_i915_private *i915);
3442 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3443 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3444 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3445 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3446 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3447 unsigned int flags);
3448 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3449 void i915_gem_resume(struct drm_i915_private *dev_priv);
3450 int i915_gem_fault(struct vm_fault *vmf);
3451 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3454 struct intel_rps_client *rps);
3455 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3458 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3461 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3464 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3465 struct i915_vma * __must_check
3466 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3468 const struct i915_ggtt_view *view);
3469 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3470 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3472 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3473 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3475 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3476 enum i915_cache_level cache_level);
3478 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3479 struct dma_buf *dma_buf);
3481 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3482 struct drm_gem_object *gem_obj, int flags);
3484 static inline struct i915_hw_ppgtt *
3485 i915_vm_to_ppgtt(struct i915_address_space *vm)
3487 return container_of(vm, struct i915_hw_ppgtt, base);
3490 /* i915_gem_fence_reg.c */
3491 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3492 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3494 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3495 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3497 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3498 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3499 struct sg_table *pages);
3500 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3501 struct sg_table *pages);
3503 static inline struct i915_gem_context *
3504 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3506 struct i915_gem_context *ctx;
3508 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3510 ctx = idr_find(&file_priv->context_idr, id);
3512 return ERR_PTR(-ENOENT);
3517 static inline struct i915_gem_context *
3518 i915_gem_context_get(struct i915_gem_context *ctx)
3520 kref_get(&ctx->ref);
3524 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3526 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3527 kref_put(&ctx->ref, i915_gem_context_free);
3530 static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
3532 struct mutex *lock = &ctx->i915->drm.struct_mutex;
3534 if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
3538 static inline struct intel_timeline *
3539 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3540 struct intel_engine_cs *engine)
3542 struct i915_address_space *vm;
3544 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3545 return &vm->timeline.engine[engine->id];
3548 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3549 struct drm_file *file);
3551 /* i915_gem_evict.c */
3552 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3553 u64 min_size, u64 alignment,
3554 unsigned cache_level,
3557 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3558 struct drm_mm_node *node,
3559 unsigned int flags);
3560 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3562 /* belongs in i915_gem_gtt.h */
3563 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3566 if (INTEL_GEN(dev_priv) < 6)
3567 intel_gtt_chipset_flush();
3570 /* i915_gem_stolen.c */
3571 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3572 struct drm_mm_node *node, u64 size,
3573 unsigned alignment);
3574 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3575 struct drm_mm_node *node, u64 size,
3576 unsigned alignment, u64 start,
3578 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3579 struct drm_mm_node *node);
3580 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3581 void i915_gem_cleanup_stolen(struct drm_device *dev);
3582 struct drm_i915_gem_object *
3583 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3584 struct drm_i915_gem_object *
3585 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3590 /* i915_gem_internal.c */
3591 struct drm_i915_gem_object *
3592 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3595 /* i915_gem_shrinker.c */
3596 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3597 unsigned long target,
3599 #define I915_SHRINK_PURGEABLE 0x1
3600 #define I915_SHRINK_UNBOUND 0x2
3601 #define I915_SHRINK_BOUND 0x4
3602 #define I915_SHRINK_ACTIVE 0x8
3603 #define I915_SHRINK_VMAPS 0x10
3604 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3605 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3606 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3609 /* i915_gem_tiling.c */
3610 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3612 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3614 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3615 i915_gem_object_is_tiled(obj);
3618 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3619 unsigned int tiling, unsigned int stride);
3620 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3621 unsigned int tiling, unsigned int stride);
3623 /* i915_debugfs.c */
3624 #ifdef CONFIG_DEBUG_FS
3625 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3626 int i915_debugfs_connector_add(struct drm_connector *connector);
3627 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3629 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3630 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3632 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3635 /* i915_gpu_error.c */
3636 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3639 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3640 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3641 const struct i915_gpu_state *gpu);
3642 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3643 struct drm_i915_private *i915,
3644 size_t count, loff_t pos);
3645 static inline void i915_error_state_buf_release(
3646 struct drm_i915_error_state_buf *eb)
3651 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3652 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3654 const char *error_msg);
3656 static inline struct i915_gpu_state *
3657 i915_gpu_state_get(struct i915_gpu_state *gpu)
3659 kref_get(&gpu->ref);
3663 void __i915_gpu_state_free(struct kref *kref);
3664 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
3667 kref_put(&gpu->ref, __i915_gpu_state_free);
3670 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
3671 void i915_reset_error_state(struct drm_i915_private *i915);
3675 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3677 const char *error_msg)
3681 static inline struct i915_gpu_state *
3682 i915_first_error_state(struct drm_i915_private *i915)
3687 static inline void i915_reset_error_state(struct drm_i915_private *i915)
3693 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3695 /* i915_cmd_parser.c */
3696 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3697 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3698 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3699 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3700 struct drm_i915_gem_object *batch_obj,
3701 struct drm_i915_gem_object *shadow_batch_obj,
3702 u32 batch_start_offset,
3707 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3708 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3709 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3710 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3712 /* i915_suspend.c */
3713 extern int i915_save_state(struct drm_i915_private *dev_priv);
3714 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3717 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3718 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3720 /* intel_lpe_audio.c */
3721 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3722 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3723 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3724 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3725 void *eld, int port, int pipe, int tmds_clk_speed,
3726 bool dp_output, int link_rate);
3729 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3730 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3731 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3734 extern struct i2c_adapter *
3735 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3736 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3737 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3738 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3740 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3742 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3745 void intel_bios_init(struct drm_i915_private *dev_priv);
3746 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3747 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3748 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3749 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3750 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3751 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3752 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3753 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3755 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3759 /* intel_opregion.c */
3761 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3762 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3763 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3764 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3765 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3767 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3769 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3771 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3772 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3773 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3774 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3778 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3783 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3787 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3795 extern void intel_register_dsm_handler(void);
3796 extern void intel_unregister_dsm_handler(void);
3798 static inline void intel_register_dsm_handler(void) { return; }
3799 static inline void intel_unregister_dsm_handler(void) { return; }
3800 #endif /* CONFIG_ACPI */
3802 /* intel_device_info.c */
3803 static inline struct intel_device_info *
3804 mkwrite_device_info(struct drm_i915_private *dev_priv)
3806 return (struct intel_device_info *)&dev_priv->info;
3809 const char *intel_platform_name(enum intel_platform platform);
3810 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3811 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3814 extern void intel_modeset_init_hw(struct drm_device *dev);
3815 extern int intel_modeset_init(struct drm_device *dev);
3816 extern void intel_modeset_gem_init(struct drm_device *dev);
3817 extern void intel_modeset_cleanup(struct drm_device *dev);
3818 extern int intel_connector_register(struct drm_connector *);
3819 extern void intel_connector_unregister(struct drm_connector *);
3820 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3822 extern void intel_display_resume(struct drm_device *dev);
3823 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3824 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3825 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3826 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3827 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3828 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3831 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3832 struct drm_file *file);
3835 extern struct intel_overlay_error_state *
3836 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3837 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3838 struct intel_overlay_error_state *error);
3840 extern struct intel_display_error_state *
3841 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3842 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3843 struct intel_display_error_state *error);
3845 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3846 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3847 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3848 u32 reply_mask, u32 reply, int timeout_base_ms);
3850 /* intel_sideband.c */
3851 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3852 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3853 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3854 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3855 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3856 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3857 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3858 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3859 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3860 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3861 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3862 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3863 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3864 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3865 enum intel_sbi_destination destination);
3866 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3867 enum intel_sbi_destination destination);
3868 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3869 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3871 /* intel_dpio_phy.c */
3872 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3873 enum dpio_phy *phy, enum dpio_channel *ch);
3874 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3875 enum port port, u32 margin, u32 scale,
3876 u32 enable, u32 deemphasis);
3877 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3878 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3879 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3881 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3883 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
3884 uint8_t lane_count);
3885 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3886 uint8_t lane_lat_optim_mask);
3887 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3889 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3890 u32 deemph_reg_value, u32 margin_reg_value,
3891 bool uniq_trans_scale);
3892 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3894 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3895 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3896 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3897 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3899 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3900 u32 demph_reg_value, u32 preemph_reg_value,
3901 u32 uniqtranscale_reg_value, u32 tx3_demph);
3902 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3903 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3904 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3906 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3907 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3908 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3909 const i915_reg_t reg);
3911 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3912 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3914 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3915 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3916 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3917 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3919 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3920 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3921 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3922 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3924 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3925 * will be implemented using 2 32-bit writes in an arbitrary order with
3926 * an arbitrary delay between them. This can cause the hardware to
3927 * act upon the intermediate value, possibly leading to corruption and
3928 * machine death. For this reason we do not support I915_WRITE64, or
3929 * dev_priv->uncore.funcs.mmio_writeq.
3931 * When reading a 64-bit value as two 32-bit values, the delay may cause
3932 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3933 * occasionally a 64-bit register does not actualy support a full readq
3934 * and must be read using two 32-bit reads.
3936 * You have been warned.
3938 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3940 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3941 u32 upper, lower, old_upper, loop = 0; \
3942 upper = I915_READ(upper_reg); \
3944 old_upper = upper; \
3945 lower = I915_READ(lower_reg); \
3946 upper = I915_READ(upper_reg); \
3947 } while (upper != old_upper && loop++ < 2); \
3948 (u64)upper << 32 | lower; })
3950 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3951 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3953 #define __raw_read(x, s) \
3954 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3957 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3960 #define __raw_write(x, s) \
3961 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3962 i915_reg_t reg, uint##x##_t val) \
3964 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3979 /* These are untraced mmio-accessors that are only valid to be used inside
3980 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3983 * Think twice, and think again, before using these.
3985 * As an example, these accessors can possibly be used between:
3987 * spin_lock_irq(&dev_priv->uncore.lock);
3988 * intel_uncore_forcewake_get__locked();
3992 * intel_uncore_forcewake_put__locked();
3993 * spin_unlock_irq(&dev_priv->uncore.lock);
3996 * Note: some registers may not need forcewake held, so
3997 * intel_uncore_forcewake_{get,put} can be omitted, see
3998 * intel_uncore_forcewake_for_reg().
4000 * Certain architectures will die if the same cacheline is concurrently accessed
4001 * by different clients (e.g. on Ivybridge). Access to registers should
4002 * therefore generally be serialised, by either the dev_priv->uncore.lock or
4003 * a more localised lock guarding all access to that bank of registers.
4005 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
4006 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
4007 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
4008 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
4010 /* "Broadcast RGB" property */
4011 #define INTEL_BROADCAST_RGB_AUTO 0
4012 #define INTEL_BROADCAST_RGB_FULL 1
4013 #define INTEL_BROADCAST_RGB_LIMITED 2
4015 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
4017 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4018 return VLV_VGACNTRL;
4019 else if (INTEL_GEN(dev_priv) >= 5)
4020 return CPU_VGACNTRL;
4025 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
4027 unsigned long j = msecs_to_jiffies(m);
4029 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4032 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
4034 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
4037 static inline unsigned long
4038 timespec_to_jiffies_timeout(const struct timespec *value)
4040 unsigned long j = timespec_to_jiffies(value);
4042 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
4046 * If you need to wait X milliseconds between events A and B, but event B
4047 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4048 * when event A happened, then just before event B you call this function and
4049 * pass the timestamp as the first argument, and X as the second argument.
4052 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
4054 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4057 * Don't re-read the value of "jiffies" every time since it may change
4058 * behind our back and break the math.
4060 tmp_jiffies = jiffies;
4061 target_jiffies = timestamp_jiffies +
4062 msecs_to_jiffies_timeout(to_wait_ms);
4064 if (time_after(target_jiffies, tmp_jiffies)) {
4065 remaining_jiffies = target_jiffies - tmp_jiffies;
4066 while (remaining_jiffies)
4068 schedule_timeout_uninterruptible(remaining_jiffies);
4073 __i915_request_irq_complete(const struct drm_i915_gem_request *req)
4075 struct intel_engine_cs *engine = req->engine;
4078 /* Note that the engine may have wrapped around the seqno, and
4079 * so our request->global_seqno will be ahead of the hardware,
4080 * even though it completed the request before wrapping. We catch
4081 * this by kicking all the waiters before resetting the seqno
4082 * in hardware, and also signal the fence.
4084 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
4087 /* The request was dequeued before we were awoken. We check after
4088 * inspecting the hw to confirm that this was the same request
4089 * that generated the HWS update. The memory barriers within
4090 * the request execution are sufficient to ensure that a check
4091 * after reading the value from hw matches this request.
4093 seqno = i915_gem_request_global_seqno(req);
4097 /* Before we do the heavier coherent read of the seqno,
4098 * check the value (hopefully) in the CPU cacheline.
4100 if (__i915_gem_request_completed(req, seqno))
4103 /* Ensure our read of the seqno is coherent so that we
4104 * do not "miss an interrupt" (i.e. if this is the last
4105 * request and the seqno write from the GPU is not visible
4106 * by the time the interrupt fires, we will see that the
4107 * request is incomplete and go back to sleep awaiting
4108 * another interrupt that will never come.)
4110 * Strictly, we only need to do this once after an interrupt,
4111 * but it is easier and safer to do it every time the waiter
4114 if (engine->irq_seqno_barrier &&
4115 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4116 struct intel_breadcrumbs *b = &engine->breadcrumbs;
4118 /* The ordering of irq_posted versus applying the barrier
4119 * is crucial. The clearing of the current irq_posted must
4120 * be visible before we perform the barrier operation,
4121 * such that if a subsequent interrupt arrives, irq_posted
4122 * is reasserted and our task rewoken (which causes us to
4123 * do another __i915_request_irq_complete() immediately
4124 * and reapply the barrier). Conversely, if the clear
4125 * occurs after the barrier, then an interrupt that arrived
4126 * whilst we waited on the barrier would not trigger a
4127 * barrier on the next pass, and the read may not see the
4130 engine->irq_seqno_barrier(engine);
4132 /* If we consume the irq, but we are no longer the bottom-half,
4133 * the real bottom-half may not have serialised their own
4134 * seqno check with the irq-barrier (i.e. may have inspected
4135 * the seqno before we believe it coherent since they see
4136 * irq_posted == false but we are still running).
4138 spin_lock_irq(&b->irq_lock);
4139 if (b->irq_wait && b->irq_wait->tsk != current)
4140 /* Note that if the bottom-half is changed as we
4141 * are sending the wake-up, the new bottom-half will
4142 * be woken by whomever made the change. We only have
4143 * to worry about when we steal the irq-posted for
4146 wake_up_process(b->irq_wait->tsk);
4147 spin_unlock_irq(&b->irq_lock);
4149 if (__i915_gem_request_completed(req, seqno))
4156 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4157 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4159 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4160 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4161 * perform the operation. To check beforehand, pass in the parameters to
4162 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4163 * you only need to pass in the minor offsets, page-aligned pointers are
4166 * For just checking for SSE4.1, in the foreknowledge that the future use
4167 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4169 #define i915_can_memcpy_from_wc(dst, src, len) \
4170 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4172 #define i915_has_memcpy_from_wc() \
4173 i915_memcpy_from_wc(NULL, NULL, 0)
4176 int remap_io_mapping(struct vm_area_struct *vma,
4177 unsigned long addr, unsigned long pfn, unsigned long size,
4178 struct io_mapping *iomap);
4180 static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
4182 return (obj->cache_level != I915_CACHE_NONE ||
4183 HAS_LLC(to_i915(obj->base.dev)));