1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
89 #define port_name(p) ((p) + 'A')
91 enum intel_display_power_domain {
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
98 POWER_DOMAIN_TRANSCODER_A,
99 POWER_DOMAIN_TRANSCODER_B,
100 POWER_DOMAIN_TRANSCODER_C,
101 POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF,
104 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
105 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
106 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
107 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
111 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
112 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
122 #define I915_GEM_GPU_DOMAINS \
123 (I915_GEM_DOMAIN_RENDER | \
124 I915_GEM_DOMAIN_SAMPLER | \
125 I915_GEM_DOMAIN_COMMAND | \
126 I915_GEM_DOMAIN_INSTRUCTION | \
127 I915_GEM_DOMAIN_VERTEX)
129 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
131 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
133 if ((intel_encoder)->base.crtc == (__crtc))
135 struct drm_i915_private;
138 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
139 /* real shared dpll ids must be >= 0 */
143 #define I915_NUM_PLLS 2
145 struct intel_dpll_hw_state {
152 struct intel_shared_dpll {
153 int refcount; /* count of number of CRTCs sharing this PLL */
154 int active; /* count of number of active CRTCs (i.e. DPMS on) */
155 bool on; /* is the PLL actually active? Disabled during modeset */
157 /* should match the index in the dev_priv->shared_dplls array */
158 enum intel_dpll_id id;
159 struct intel_dpll_hw_state hw_state;
160 void (*mode_set)(struct drm_i915_private *dev_priv,
161 struct intel_shared_dpll *pll);
162 void (*enable)(struct drm_i915_private *dev_priv,
163 struct intel_shared_dpll *pll);
164 void (*disable)(struct drm_i915_private *dev_priv,
165 struct intel_shared_dpll *pll);
166 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
167 struct intel_shared_dpll *pll,
168 struct intel_dpll_hw_state *hw_state);
171 /* Used by dp and fdi links */
172 struct intel_link_m_n {
180 void intel_link_compute_m_n(int bpp, int nlanes,
181 int pixel_clock, int link_clock,
182 struct intel_link_m_n *m_n);
184 struct intel_ddi_plls {
190 /* Interface history:
193 * 1.2: Add Power Management
194 * 1.3: Add vblank support
195 * 1.4: Fix cmdbuffer path, add heap destroy
196 * 1.5: Add vblank pipe configuration
197 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
198 * - Support vertical blank on secondary display pipe
200 #define DRIVER_MAJOR 1
201 #define DRIVER_MINOR 6
202 #define DRIVER_PATCHLEVEL 0
204 #define WATCH_LISTS 0
207 #define I915_GEM_PHYS_CURSOR_0 1
208 #define I915_GEM_PHYS_CURSOR_1 2
209 #define I915_GEM_PHYS_OVERLAY_REGS 3
210 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
212 struct drm_i915_gem_phys_object {
214 struct page **page_list;
215 drm_dma_handle_t *handle;
216 struct drm_i915_gem_object *cur_obj;
219 struct opregion_header;
220 struct opregion_acpi;
221 struct opregion_swsci;
222 struct opregion_asle;
224 struct intel_opregion {
225 struct opregion_header __iomem *header;
226 struct opregion_acpi __iomem *acpi;
227 struct opregion_swsci __iomem *swsci;
228 struct opregion_asle __iomem *asle;
230 u32 __iomem *lid_state;
232 #define OPREGION_SIZE (8*1024)
234 struct intel_overlay;
235 struct intel_overlay_error_state;
237 struct drm_i915_master_private {
238 drm_local_map_t *sarea;
239 struct _drm_i915_sarea *sarea_priv;
241 #define I915_FENCE_REG_NONE -1
242 #define I915_MAX_NUM_FENCES 32
243 /* 32 fences + sign bit for FENCE_REG_NONE */
244 #define I915_MAX_NUM_FENCE_BITS 6
246 struct drm_i915_fence_reg {
247 struct list_head lru_list;
248 struct drm_i915_gem_object *obj;
252 struct sdvo_device_mapping {
261 struct intel_display_error_state;
263 struct drm_i915_error_state {
271 bool waiting[I915_NUM_RINGS];
272 u32 pipestat[I915_MAX_PIPES];
273 u32 tail[I915_NUM_RINGS];
274 u32 head[I915_NUM_RINGS];
275 u32 ctl[I915_NUM_RINGS];
276 u32 ipeir[I915_NUM_RINGS];
277 u32 ipehr[I915_NUM_RINGS];
278 u32 instdone[I915_NUM_RINGS];
279 u32 acthd[I915_NUM_RINGS];
280 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
281 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
282 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
283 /* our own tracking of ring head and tail */
284 u32 cpu_ring_head[I915_NUM_RINGS];
285 u32 cpu_ring_tail[I915_NUM_RINGS];
286 u32 error; /* gen6+ */
287 u32 err_int; /* gen7 */
288 u32 instpm[I915_NUM_RINGS];
289 u32 instps[I915_NUM_RINGS];
290 u32 extra_instdone[I915_NUM_INSTDONE_REG];
291 u32 seqno[I915_NUM_RINGS];
293 u32 fault_reg[I915_NUM_RINGS];
295 u32 faddr[I915_NUM_RINGS];
296 u64 fence[I915_MAX_NUM_FENCES];
298 struct drm_i915_error_ring {
299 struct drm_i915_error_object {
303 } *ringbuffer, *batchbuffer, *ctx;
304 struct drm_i915_error_request {
310 } ring[I915_NUM_RINGS];
311 struct drm_i915_error_buffer {
318 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
325 } **active_bo, **pinned_bo;
326 u32 *active_bo_count, *pinned_bo_count;
327 struct intel_overlay_error_state *overlay;
328 struct intel_display_error_state *display;
331 struct intel_crtc_config;
336 struct drm_i915_display_funcs {
337 bool (*fbc_enabled)(struct drm_device *dev);
338 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
339 void (*disable_fbc)(struct drm_device *dev);
340 int (*get_display_clock_speed)(struct drm_device *dev);
341 int (*get_fifo_size)(struct drm_device *dev, int plane);
343 * find_dpll() - Find the best values for the PLL
344 * @limit: limits for the PLL
345 * @crtc: current CRTC
346 * @target: target frequency in kHz
347 * @refclk: reference clock frequency in kHz
348 * @match_clock: if provided, @best_clock P divider must
349 * match the P divider from @match_clock
350 * used for LVDS downclocking
351 * @best_clock: best PLL values found
353 * Returns true on success, false on failure.
355 bool (*find_dpll)(const struct intel_limit *limit,
356 struct drm_crtc *crtc,
357 int target, int refclk,
358 struct dpll *match_clock,
359 struct dpll *best_clock);
360 void (*update_wm)(struct drm_device *dev);
361 void (*update_sprite_wm)(struct drm_plane *plane,
362 struct drm_crtc *crtc,
363 uint32_t sprite_width, int pixel_size,
364 bool enable, bool scaled);
365 void (*modeset_global_resources)(struct drm_device *dev);
366 /* Returns the active state of the crtc, and if the crtc is active,
367 * fills out the pipe-config with the hw state. */
368 bool (*get_pipe_config)(struct intel_crtc *,
369 struct intel_crtc_config *);
370 void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *);
371 int (*crtc_mode_set)(struct drm_crtc *crtc,
373 struct drm_framebuffer *old_fb);
374 void (*crtc_enable)(struct drm_crtc *crtc);
375 void (*crtc_disable)(struct drm_crtc *crtc);
376 void (*off)(struct drm_crtc *crtc);
377 void (*write_eld)(struct drm_connector *connector,
378 struct drm_crtc *crtc);
379 void (*fdi_link_train)(struct drm_crtc *crtc);
380 void (*init_clock_gating)(struct drm_device *dev);
381 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
382 struct drm_framebuffer *fb,
383 struct drm_i915_gem_object *obj,
385 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
387 void (*hpd_irq_setup)(struct drm_device *dev);
388 /* clock updates for mode set */
390 /* render clock increase/decrease */
391 /* display clock increase/decrease */
392 /* pll clock increase/decrease */
395 struct intel_uncore_funcs {
396 void (*force_wake_get)(struct drm_i915_private *dev_priv);
397 void (*force_wake_put)(struct drm_i915_private *dev_priv);
400 struct intel_uncore {
401 spinlock_t lock; /** lock is also taken in irq contexts. */
403 struct intel_uncore_funcs funcs;
406 unsigned forcewake_count;
409 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
410 func(is_mobile) sep \
413 func(is_i945gm) sep \
415 func(need_gfx_hws) sep \
417 func(is_pineview) sep \
418 func(is_broadwater) sep \
419 func(is_crestline) sep \
420 func(is_ivybridge) sep \
421 func(is_valleyview) sep \
422 func(is_haswell) sep \
423 func(has_force_wake) sep \
425 func(has_pipe_cxsr) sep \
426 func(has_hotplug) sep \
427 func(cursor_needs_physical) sep \
428 func(has_overlay) sep \
429 func(overlay_needs_physical) sep \
430 func(supports_tv) sep \
431 func(has_bsd_ring) sep \
432 func(has_blt_ring) sep \
433 func(has_vebox_ring) sep \
438 #define DEFINE_FLAG(name) u8 name:1
439 #define SEP_SEMICOLON ;
441 struct intel_device_info {
442 u32 display_mmio_offset;
445 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
451 enum i915_cache_level {
453 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
454 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
455 caches, eg sampler/render caches, and the
456 large Last-Level-Cache. LLC is coherent with
457 the CPU, but L3 is only visible to the GPU. */
458 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
461 typedef uint32_t gen6_gtt_pte_t;
463 struct i915_address_space {
465 struct drm_device *dev;
466 struct list_head global_link;
467 unsigned long start; /* Start offset always 0 for dri2 */
468 size_t total; /* size addr space maps (ex. 2GB for ggtt) */
476 * List of objects currently involved in rendering.
478 * Includes buffers having the contents of their GPU caches
479 * flushed, not necessarily primitives. last_rendering_seqno
480 * represents when the rendering involved will be completed.
482 * A reference is held on the buffer while on this list.
484 struct list_head active_list;
487 * LRU list of objects which are not in the ringbuffer and
488 * are ready to unbind, but are still in the GTT.
490 * last_rendering_seqno is 0 while an object is in this list.
492 * A reference is not held on the buffer while on this list,
493 * as merely being GTT-bound shouldn't prevent its being
494 * freed, and we'll pull it off the list in the free path.
496 struct list_head inactive_list;
498 /* FIXME: Need a more generic return type */
499 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
500 enum i915_cache_level level,
501 bool valid); /* Create a valid PTE */
502 void (*clear_range)(struct i915_address_space *vm,
503 unsigned int first_entry,
504 unsigned int num_entries,
506 void (*insert_entries)(struct i915_address_space *vm,
508 unsigned int first_entry,
509 enum i915_cache_level cache_level);
510 void (*cleanup)(struct i915_address_space *vm);
513 /* The Graphics Translation Table is the way in which GEN hardware translates a
514 * Graphics Virtual Address into a Physical Address. In addition to the normal
515 * collateral associated with any va->pa translations GEN hardware also has a
516 * portion of the GTT which can be mapped by the CPU and remain both coherent
517 * and correct (in cases like swizzling). That region is referred to as GMADR in
521 struct i915_address_space base;
522 size_t stolen_size; /* Total size of stolen memory */
524 unsigned long mappable_end; /* End offset that we can CPU map */
525 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
526 phys_addr_t mappable_base; /* PA of our GMADR */
528 /** "Graphics Stolen Memory" holds the global PTEs */
536 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
537 size_t *stolen, phys_addr_t *mappable_base,
538 unsigned long *mappable_end);
540 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
542 struct i915_hw_ppgtt {
543 struct i915_address_space base;
544 unsigned num_pd_entries;
545 struct page **pt_pages;
547 dma_addr_t *pt_dma_addr;
549 int (*enable)(struct drm_device *dev);
553 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
554 * VMA's presence cannot be guaranteed before binding, or after unbinding the
555 * object into/from the address space.
557 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
558 * will always be <= an objects lifetime. So object refcounting should cover us.
561 struct drm_mm_node node;
562 struct drm_i915_gem_object *obj;
563 struct i915_address_space *vm;
565 /** This object's place on the active/inactive lists */
566 struct list_head mm_list;
568 struct list_head vma_link; /* Link in the object's VMA list */
570 /** This vma's place in the batchbuffer or on the eviction list */
571 struct list_head exec_list;
575 struct i915_ctx_hang_stats {
576 /* This context had batch pending when hang was declared */
577 unsigned batch_pending;
579 /* This context had batch active when hang was declared */
580 unsigned batch_active;
583 /* This must match up with the value previously used for execbuf2.rsvd1. */
584 #define DEFAULT_CONTEXT_ID 0
585 struct i915_hw_context {
589 struct drm_i915_file_private *file_priv;
590 struct intel_ring_buffer *ring;
591 struct drm_i915_gem_object *obj;
592 struct i915_ctx_hang_stats hang_stats;
601 struct drm_mm_node *compressed_fb;
602 struct drm_mm_node *compressed_llb;
604 struct intel_fbc_work {
605 struct delayed_work work;
606 struct drm_crtc *crtc;
607 struct drm_framebuffer *fb;
612 FBC_OK, /* FBC is enabled */
613 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
614 FBC_NO_OUTPUT, /* no outputs enabled to compress */
615 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
616 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
617 FBC_MODE_TOO_LARGE, /* mode too large for compression */
618 FBC_BAD_PLANE, /* fbc not supported on plane */
619 FBC_NOT_TILED, /* buffer not tiled */
620 FBC_MULTIPLE_PIPES, /* more than one pipe active */
622 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
627 PSR_NO_SOURCE, /* Not supported on platform */
628 PSR_NO_SINK, /* Not supported by panel */
631 PSR_PWR_WELL_ENABLED,
635 PSR_INTERLACED_ENABLED,
640 PCH_NONE = 0, /* No PCH present */
641 PCH_IBX, /* Ibexpeak PCH */
642 PCH_CPT, /* Cougarpoint PCH */
643 PCH_LPT, /* Lynxpoint PCH */
647 enum intel_sbi_destination {
652 #define QUIRK_PIPEA_FORCE (1<<0)
653 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
654 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
655 #define QUIRK_NO_PCH_PWM_ENABLE (1<<3)
658 struct intel_fbc_work;
661 struct i2c_adapter adapter;
665 struct i2c_algo_bit_data bit_algo;
666 struct drm_i915_private *dev_priv;
669 struct i915_suspend_saved_registers {
690 u32 saveTRANS_HTOTAL_A;
691 u32 saveTRANS_HBLANK_A;
692 u32 saveTRANS_HSYNC_A;
693 u32 saveTRANS_VTOTAL_A;
694 u32 saveTRANS_VBLANK_A;
695 u32 saveTRANS_VSYNC_A;
703 u32 savePFIT_PGM_RATIOS;
704 u32 saveBLC_HIST_CTL;
706 u32 saveBLC_PWM_CTL2;
707 u32 saveBLC_CPU_PWM_CTL;
708 u32 saveBLC_CPU_PWM_CTL2;
721 u32 saveTRANS_HTOTAL_B;
722 u32 saveTRANS_HBLANK_B;
723 u32 saveTRANS_HSYNC_B;
724 u32 saveTRANS_VTOTAL_B;
725 u32 saveTRANS_VBLANK_B;
726 u32 saveTRANS_VSYNC_B;
740 u32 savePP_ON_DELAYS;
741 u32 savePP_OFF_DELAYS;
749 u32 savePFIT_CONTROL;
750 u32 save_palette_a[256];
751 u32 save_palette_b[256];
752 u32 saveDPFC_CB_BASE;
753 u32 saveFBC_CFB_BASE;
756 u32 saveFBC_CONTROL2;
766 u32 saveCACHE_MODE_0;
767 u32 saveMI_ARB_STATE;
778 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
789 u32 savePIPEA_GMCH_DATA_M;
790 u32 savePIPEB_GMCH_DATA_M;
791 u32 savePIPEA_GMCH_DATA_N;
792 u32 savePIPEB_GMCH_DATA_N;
793 u32 savePIPEA_DP_LINK_M;
794 u32 savePIPEB_DP_LINK_M;
795 u32 savePIPEA_DP_LINK_N;
796 u32 savePIPEB_DP_LINK_N;
807 u32 savePCH_DREF_CONTROL;
808 u32 saveDISP_ARB_CTL;
809 u32 savePIPEA_DATA_M1;
810 u32 savePIPEA_DATA_N1;
811 u32 savePIPEA_LINK_M1;
812 u32 savePIPEA_LINK_N1;
813 u32 savePIPEB_DATA_M1;
814 u32 savePIPEB_DATA_N1;
815 u32 savePIPEB_LINK_M1;
816 u32 savePIPEB_LINK_N1;
817 u32 saveMCHBAR_RENDER_STANDBY;
818 u32 savePCH_PORT_HOTPLUG;
821 struct intel_gen6_power_mgmt {
822 /* work and pm_iir are protected by dev_priv->irq_lock */
823 struct work_struct work;
826 /* On vlv we need to manually drop to Vmin with a delayed work. */
827 struct delayed_work vlv_work;
829 /* The below variables an all the rps hw state are protected by
830 * dev->struct mutext. */
837 struct delayed_work delayed_resume_work;
840 * Protects RPS/RC6 register access and PCU communication.
841 * Must be taken after struct_mutex if nested.
843 struct mutex hw_lock;
846 /* defined intel_pm.c */
847 extern spinlock_t mchdev_lock;
849 struct intel_ilk_power_mgmt {
857 unsigned long last_time1;
858 unsigned long chipset_power;
860 struct timespec last_time2;
861 unsigned long gfx_power;
867 struct drm_i915_gem_object *pwrctx;
868 struct drm_i915_gem_object *renderctx;
871 /* Power well structure for haswell */
872 struct i915_power_well {
873 struct drm_device *device;
875 /* power well enable/disable usage count */
880 struct i915_dri1_state {
881 unsigned allow_batchbuffer : 1;
882 u32 __iomem *gfx_hws_cpu_addr;
893 struct i915_ums_state {
895 * Flag if the X Server, and thus DRM, is not currently in
896 * control of the device.
898 * This is set between LeaveVT and EnterVT. It needs to be
899 * replaced with a semaphore. It also needs to be
900 * transitioned away from for kernel modesetting.
905 struct intel_l3_parity {
907 struct work_struct error_work;
911 /** Memory allocator for GTT stolen memory */
912 struct drm_mm stolen;
913 /** List of all objects in gtt_space. Used to restore gtt
914 * mappings on resume */
915 struct list_head bound_list;
917 * List of objects which are not bound to the GTT (thus
918 * are idle and not used by the GPU) but still have
919 * (presumably uncached) pages still attached.
921 struct list_head unbound_list;
923 /** Usable portion of the GTT for GEM */
924 unsigned long stolen_base; /* limited to low memory (32-bit) */
926 /** PPGTT used for aliasing the PPGTT with the GTT */
927 struct i915_hw_ppgtt *aliasing_ppgtt;
929 struct shrinker inactive_shrinker;
930 bool shrinker_no_lock_stealing;
932 /** LRU list of objects with fence regs on them. */
933 struct list_head fence_list;
936 * We leave the user IRQ off as much as possible,
937 * but this means that requests will finish and never
938 * be retired once the system goes idle. Set a timer to
939 * fire periodically while the ring is running. When it
940 * fires, go retire requests.
942 struct delayed_work retire_work;
945 * Are we in a non-interruptible section of code like
950 /** Bit 6 swizzling required for X tiling */
951 uint32_t bit_6_swizzle_x;
952 /** Bit 6 swizzling required for Y tiling */
953 uint32_t bit_6_swizzle_y;
955 /* storage for physical objects */
956 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
958 /* accounting, useful for userland debugging */
959 spinlock_t object_stat_lock;
960 size_t object_memory;
964 struct drm_i915_error_state_buf {
973 struct i915_error_state_file_priv {
974 struct drm_device *dev;
975 struct drm_i915_error_state *error;
978 struct i915_gpu_error {
979 /* For hangcheck timer */
980 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
981 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
982 struct timer_list hangcheck_timer;
984 /* For reset and error_state handling. */
986 /* Protected by the above dev->gpu_error.lock. */
987 struct drm_i915_error_state *first_error;
988 struct work_struct work;
990 unsigned long last_reset;
993 * State variable and reset counter controlling the reset flow
995 * Upper bits are for the reset counter. This counter is used by the
996 * wait_seqno code to race-free noticed that a reset event happened and
997 * that it needs to restart the entire ioctl (since most likely the
998 * seqno it waited for won't ever signal anytime soon).
1000 * This is important for lock-free wait paths, where no contended lock
1001 * naturally enforces the correct ordering between the bail-out of the
1002 * waiter and the gpu reset work code.
1004 * Lowest bit controls the reset state machine: Set means a reset is in
1005 * progress. This state will (presuming we don't have any bugs) decay
1006 * into either unset (successful reset) or the special WEDGED value (hw
1007 * terminally sour). All waiters on the reset_queue will be woken when
1010 atomic_t reset_counter;
1013 * Special values/flags for reset_counter
1015 * Note that the code relies on
1016 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
1019 #define I915_RESET_IN_PROGRESS_FLAG 1
1020 #define I915_WEDGED 0xffffffff
1023 * Waitqueue to signal when the reset has completed. Used by clients
1024 * that wait for dev_priv->mm.wedged to settle.
1026 wait_queue_head_t reset_queue;
1028 /* For gpu hang simulation. */
1029 unsigned int stop_rings;
1032 enum modeset_restore {
1033 MODESET_ON_LID_OPEN,
1038 struct intel_vbt_data {
1039 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1040 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1043 unsigned int int_tv_support:1;
1044 unsigned int lvds_dither:1;
1045 unsigned int lvds_vbt:1;
1046 unsigned int int_crt_support:1;
1047 unsigned int lvds_use_ssc:1;
1048 unsigned int display_clock_mode:1;
1049 unsigned int fdi_rx_polarity_inverted:1;
1051 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1056 int edp_preemphasis;
1058 bool edp_initialized;
1061 struct edp_power_seq edp_pps;
1066 struct child_device_config *child_dev;
1069 enum intel_ddb_partitioning {
1071 INTEL_DDB_PART_5_6, /* IVB+ */
1074 struct intel_wm_level {
1083 * This struct tracks the state needed for the Package C8+ feature.
1085 * Package states C8 and deeper are really deep PC states that can only be
1086 * reached when all the devices on the system allow it, so even if the graphics
1087 * device allows PC8+, it doesn't mean the system will actually get to these
1090 * Our driver only allows PC8+ when all the outputs are disabled, the power well
1091 * is disabled and the GPU is idle. When these conditions are met, we manually
1092 * do the other conditions: disable the interrupts, clocks and switch LCPLL
1095 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1096 * the state of some registers, so when we come back from PC8+ we need to
1097 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1098 * need to take care of the registers kept by RC6.
1100 * The interrupt disabling is part of the requirements. We can only leave the
1101 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
1102 * can lock the machine.
1104 * Ideally every piece of our code that needs PC8+ disabled would call
1105 * hsw_disable_package_c8, which would increment disable_count and prevent the
1106 * system from reaching PC8+. But we don't have a symmetric way to do this for
1107 * everything, so we have the requirements_met and gpu_idle variables. When we
1108 * switch requirements_met or gpu_idle to true we decrease disable_count, and
1109 * increase it in the opposite case. The requirements_met variable is true when
1110 * all the CRTCs, encoders and the power well are disabled. The gpu_idle
1111 * variable is true when the GPU is idle.
1113 * In addition to everything, we only actually enable PC8+ if disable_count
1114 * stays at zero for at least some seconds. This is implemented with the
1115 * enable_work variable. We do this so we don't enable/disable PC8 dozens of
1116 * consecutive times when all screens are disabled and some background app
1117 * queries the state of our connectors, or we have some application constantly
1118 * waking up to use the GPU. Only after the enable_work function actually
1119 * enables PC8+ the "enable" variable will become true, which means that it can
1120 * be false even if disable_count is 0.
1122 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1123 * goes back to false exactly before we reenable the IRQs. We use this variable
1124 * to check if someone is trying to enable/disable IRQs while they're supposed
1125 * to be disabled. This shouldn't happen and we'll print some error messages in
1126 * case it happens, but if it actually happens we'll also update the variables
1127 * inside struct regsave so when we restore the IRQs they will contain the
1128 * latest expected values.
1130 * For more, read "Display Sequences for Package C8" on our documentation.
1132 struct i915_package_c8 {
1133 bool requirements_met;
1136 /* Only true after the delayed work task actually enables it. */
1140 struct delayed_work enable_work;
1147 uint32_t gen6_pmimr;
1151 typedef struct drm_i915_private {
1152 struct drm_device *dev;
1153 struct kmem_cache *slab;
1155 const struct intel_device_info *info;
1157 int relative_constants_mode;
1161 struct intel_uncore uncore;
1163 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1166 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1167 * controller on different i2c buses. */
1168 struct mutex gmbus_mutex;
1171 * Base address of the gmbus and gpio block.
1173 uint32_t gpio_mmio_base;
1175 wait_queue_head_t gmbus_wait_queue;
1177 struct pci_dev *bridge_dev;
1178 struct intel_ring_buffer ring[I915_NUM_RINGS];
1179 uint32_t last_seqno, next_seqno;
1181 drm_dma_handle_t *status_page_dmah;
1182 struct resource mch_res;
1184 atomic_t irq_received;
1186 /* protects the irq masks */
1187 spinlock_t irq_lock;
1189 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1190 struct pm_qos_request pm_qos;
1192 /* DPIO indirect register protection */
1193 struct mutex dpio_lock;
1195 /** Cached value of IMR to avoid reads in updating the bitfield */
1200 struct work_struct hotplug_work;
1201 bool enable_hotplug_processing;
1203 unsigned long hpd_last_jiffies;
1208 HPD_MARK_DISABLED = 2
1210 } hpd_stats[HPD_NUM_PINS];
1212 struct timer_list hotplug_reenable_timer;
1216 struct i915_fbc fbc;
1217 struct intel_opregion opregion;
1218 struct intel_vbt_data vbt;
1221 struct intel_overlay *overlay;
1222 unsigned int sprite_scaling_enabled;
1228 spinlock_t lock; /* bl registers and the above bl fields */
1229 struct backlight_device *device;
1233 bool no_aux_handshake;
1235 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1236 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1237 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1239 unsigned int fsb_freq, mem_freq, is_ddr3;
1242 * wq - Driver workqueue for GEM.
1244 * NOTE: Work items scheduled here are not allowed to grab any modeset
1245 * locks, for otherwise the flushing done in the pageflip code will
1246 * result in deadlocks.
1248 struct workqueue_struct *wq;
1250 /* Display functions */
1251 struct drm_i915_display_funcs display;
1253 /* PCH chipset type */
1254 enum intel_pch pch_type;
1255 unsigned short pch_id;
1257 unsigned long quirks;
1259 enum modeset_restore modeset_restore;
1260 struct mutex modeset_restore_lock;
1262 struct list_head vm_list; /* Global list of all address spaces */
1263 struct i915_gtt gtt; /* VMA representing the global address space */
1265 struct i915_gem_mm mm;
1267 /* Kernel Modesetting */
1269 struct sdvo_device_mapping sdvo_mappings[2];
1271 struct drm_crtc *plane_to_crtc_mapping[3];
1272 struct drm_crtc *pipe_to_crtc_mapping[3];
1273 wait_queue_head_t pending_flip_queue;
1275 int num_shared_dpll;
1276 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1277 struct intel_ddi_plls ddi_plls;
1279 /* Reclocking support */
1280 bool render_reclock_avail;
1281 bool lvds_downclock_avail;
1282 /* indicates the reduced downclock for LVDS*/
1286 bool mchbar_need_disable;
1288 struct intel_l3_parity l3_parity;
1290 /* Cannot be determined by PCIID. You must always read a register. */
1293 /* gen6+ rps state */
1294 struct intel_gen6_power_mgmt rps;
1296 /* ilk-only ips/rps state. Everything in here is protected by the global
1297 * mchdev_lock in intel_pm.c */
1298 struct intel_ilk_power_mgmt ips;
1300 /* Haswell power well */
1301 struct i915_power_well power_well;
1303 enum no_psr_reason no_psr_reason;
1305 struct i915_gpu_error gpu_error;
1307 struct drm_i915_gem_object *vlv_pctx;
1309 /* list of fbdev register on this device */
1310 struct intel_fbdev *fbdev;
1313 * The console may be contended at resume, but we don't
1314 * want it to block on it.
1316 struct work_struct console_resume_work;
1318 struct drm_property *broadcast_rgb_property;
1319 struct drm_property *force_audio_property;
1321 bool hw_contexts_disabled;
1322 uint32_t hw_context_size;
1326 struct i915_suspend_saved_registers regfile;
1330 * Raw watermark latency values:
1331 * in 0.1us units for WM0,
1332 * in 0.5us units for WM1+.
1335 uint16_t pri_latency[5];
1337 uint16_t spr_latency[5];
1339 uint16_t cur_latency[5];
1342 struct i915_package_c8 pc8;
1344 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1346 struct i915_dri1_state dri1;
1347 /* Old ums support infrastructure, same warning applies. */
1348 struct i915_ums_state ums;
1349 } drm_i915_private_t;
1351 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1353 return dev->dev_private;
1356 /* Iterate over initialised rings */
1357 #define for_each_ring(ring__, dev_priv__, i__) \
1358 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1359 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1361 enum hdmi_force_audio {
1362 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1363 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1364 HDMI_AUDIO_AUTO, /* trust EDID */
1365 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1368 #define I915_GTT_OFFSET_NONE ((u32)-1)
1370 struct drm_i915_gem_object_ops {
1371 /* Interface between the GEM object and its backing storage.
1372 * get_pages() is called once prior to the use of the associated set
1373 * of pages before to binding them into the GTT, and put_pages() is
1374 * called after we no longer need them. As we expect there to be
1375 * associated cost with migrating pages between the backing storage
1376 * and making them available for the GPU (e.g. clflush), we may hold
1377 * onto the pages after they are no longer referenced by the GPU
1378 * in case they may be used again shortly (for example migrating the
1379 * pages to a different memory domain within the GTT). put_pages()
1380 * will therefore most likely be called when the object itself is
1381 * being released or under memory pressure (where we attempt to
1382 * reap pages for the shrinker).
1384 int (*get_pages)(struct drm_i915_gem_object *);
1385 void (*put_pages)(struct drm_i915_gem_object *);
1388 struct drm_i915_gem_object {
1389 struct drm_gem_object base;
1391 const struct drm_i915_gem_object_ops *ops;
1393 /** List of VMAs backed by this object */
1394 struct list_head vma_list;
1396 /** Stolen memory for this object, instead of being backed by shmem. */
1397 struct drm_mm_node *stolen;
1398 struct list_head global_list;
1400 struct list_head ring_list;
1401 /** Used in execbuf to temporarily hold a ref */
1402 struct list_head obj_exec_link;
1403 /** This object's place in the batchbuffer or on the eviction list */
1404 struct list_head exec_list;
1407 * This is set if the object is on the active lists (has pending
1408 * rendering and so a non-zero seqno), and is not set if it i s on
1409 * inactive (ready to be unbound) list.
1411 unsigned int active:1;
1414 * This is set if the object has been written to since last bound
1417 unsigned int dirty:1;
1420 * Fence register bits (if any) for this object. Will be set
1421 * as needed when mapped into the GTT.
1422 * Protected by dev->struct_mutex.
1424 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1427 * Advice: are the backing pages purgeable?
1429 unsigned int madv:2;
1432 * Current tiling mode for the object.
1434 unsigned int tiling_mode:2;
1436 * Whether the tiling parameters for the currently associated fence
1437 * register have changed. Note that for the purposes of tracking
1438 * tiling changes we also treat the unfenced register, the register
1439 * slot that the object occupies whilst it executes a fenced
1440 * command (such as BLT on gen2/3), as a "fence".
1442 unsigned int fence_dirty:1;
1444 /** How many users have pinned this object in GTT space. The following
1445 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1446 * (via user_pin_count), execbuffer (objects are not allowed multiple
1447 * times for the same batchbuffer), and the framebuffer code. When
1448 * switching/pageflipping, the framebuffer code has at most two buffers
1451 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1452 * bits with absolutely no headroom. So use 4 bits. */
1453 unsigned int pin_count:4;
1454 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1457 * Is the object at the current location in the gtt mappable and
1458 * fenceable? Used to avoid costly recalculations.
1460 unsigned int map_and_fenceable:1;
1463 * Whether the current gtt mapping needs to be mappable (and isn't just
1464 * mappable by accident). Track pin and fault separate for a more
1465 * accurate mappable working set.
1467 unsigned int fault_mappable:1;
1468 unsigned int pin_mappable:1;
1469 unsigned int pin_display:1;
1472 * Is the GPU currently using a fence to access this buffer,
1474 unsigned int pending_fenced_gpu_access:1;
1475 unsigned int fenced_gpu_access:1;
1477 unsigned int cache_level:3;
1479 unsigned int has_aliasing_ppgtt_mapping:1;
1480 unsigned int has_global_gtt_mapping:1;
1481 unsigned int has_dma_mapping:1;
1483 struct sg_table *pages;
1484 int pages_pin_count;
1486 /* prime dma-buf support */
1487 void *dma_buf_vmapping;
1491 * Used for performing relocations during execbuffer insertion.
1493 struct hlist_node exec_node;
1494 unsigned long exec_handle;
1495 struct drm_i915_gem_exec_object2 *exec_entry;
1497 struct intel_ring_buffer *ring;
1499 /** Breadcrumb of last rendering to the buffer. */
1500 uint32_t last_read_seqno;
1501 uint32_t last_write_seqno;
1502 /** Breadcrumb of last fenced GPU access to the buffer. */
1503 uint32_t last_fenced_seqno;
1505 /** Current tiling stride for the object, if it's tiled. */
1508 /** Record of address bit 17 of each page at last unbind. */
1509 unsigned long *bit_17;
1511 /** User space pin count and filp owning the pin */
1512 uint32_t user_pin_count;
1513 struct drm_file *pin_filp;
1515 /** for phy allocated objects */
1516 struct drm_i915_gem_phys_object *phys_obj;
1518 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1520 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1523 * Request queue structure.
1525 * The request queue allows us to note sequence numbers that have been emitted
1526 * and may be associated with active buffers to be retired.
1528 * By keeping this list, we can avoid having to do questionable
1529 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1530 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1532 struct drm_i915_gem_request {
1533 /** On Which ring this request was generated */
1534 struct intel_ring_buffer *ring;
1536 /** GEM sequence number associated with this request. */
1539 /** Position in the ringbuffer of the start of the request */
1542 /** Position in the ringbuffer of the end of the request */
1545 /** Context related to this request */
1546 struct i915_hw_context *ctx;
1548 /** Batch buffer related to this request if any */
1549 struct drm_i915_gem_object *batch_obj;
1551 /** Time at which this request was emitted, in jiffies. */
1552 unsigned long emitted_jiffies;
1554 /** global list entry for this request */
1555 struct list_head list;
1557 struct drm_i915_file_private *file_priv;
1558 /** file_priv list entry for this request */
1559 struct list_head client_list;
1562 struct drm_i915_file_private {
1565 struct list_head request_list;
1567 struct idr context_idr;
1569 struct i915_ctx_hang_stats hang_stats;
1572 #define INTEL_INFO(dev) (to_i915(dev)->info)
1574 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1575 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1576 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1577 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1578 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1579 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1580 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1581 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1582 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1583 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1584 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1585 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1586 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1587 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1588 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1589 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1590 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1591 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1592 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1593 (dev)->pci_device == 0x0152 || \
1594 (dev)->pci_device == 0x015a)
1595 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1596 (dev)->pci_device == 0x0106 || \
1597 (dev)->pci_device == 0x010A)
1598 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1599 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1600 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1601 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1602 ((dev)->pci_device & 0xFF00) == 0x0C00)
1603 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1604 ((dev)->pci_device & 0xFF00) == 0x0A00)
1607 * The genX designation typically refers to the render engine, so render
1608 * capability related checks should use IS_GEN, while display and other checks
1609 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1612 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1613 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1614 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1615 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1616 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1617 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1619 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1620 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1621 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
1622 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1623 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1624 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1626 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1627 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1629 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1630 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1632 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1633 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1635 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1636 * rows, which changed the alignment requirements and fence programming.
1638 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1640 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1641 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1642 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1643 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1644 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1645 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1647 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1648 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1649 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1651 #define HAS_IPS(dev) (IS_ULT(dev))
1653 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1654 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1655 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1657 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1658 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1659 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1660 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1661 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1662 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1664 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1665 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1666 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1667 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1668 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1669 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1671 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1673 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1675 #define GT_FREQUENCY_MULTIPLIER 50
1677 #include "i915_trace.h"
1680 * RC6 is a special power stage which allows the GPU to enter an very
1681 * low-voltage mode when idle, using down to 0V while at this stage. This
1682 * stage is entered automatically when the GPU is idle when RC6 support is
1683 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1685 * There are different RC6 modes available in Intel GPU, which differentiate
1686 * among each other with the latency required to enter and leave RC6 and
1687 * voltage consumed by the GPU in different states.
1689 * The combination of the following flags define which states GPU is allowed
1690 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1691 * RC6pp is deepest RC6. Their support by hardware varies according to the
1692 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1693 * which brings the most power savings; deeper states save more power, but
1694 * require higher latency to switch to and wake up.
1696 #define INTEL_RC6_ENABLE (1<<0)
1697 #define INTEL_RC6p_ENABLE (1<<1)
1698 #define INTEL_RC6pp_ENABLE (1<<2)
1700 extern const struct drm_ioctl_desc i915_ioctls[];
1701 extern int i915_max_ioctl;
1702 extern unsigned int i915_fbpercrtc __always_unused;
1703 extern int i915_panel_ignore_lid __read_mostly;
1704 extern unsigned int i915_powersave __read_mostly;
1705 extern int i915_semaphores __read_mostly;
1706 extern unsigned int i915_lvds_downclock __read_mostly;
1707 extern int i915_lvds_channel_mode __read_mostly;
1708 extern int i915_panel_use_ssc __read_mostly;
1709 extern int i915_vbt_sdvo_panel_type __read_mostly;
1710 extern int i915_enable_rc6 __read_mostly;
1711 extern int i915_enable_fbc __read_mostly;
1712 extern bool i915_enable_hangcheck __read_mostly;
1713 extern int i915_enable_ppgtt __read_mostly;
1714 extern int i915_enable_psr __read_mostly;
1715 extern unsigned int i915_preliminary_hw_support __read_mostly;
1716 extern int i915_disable_power_well __read_mostly;
1717 extern int i915_enable_ips __read_mostly;
1718 extern bool i915_fastboot __read_mostly;
1719 extern int i915_enable_pc8 __read_mostly;
1720 extern int i915_pc8_timeout __read_mostly;
1721 extern bool i915_prefault_disable __read_mostly;
1723 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1724 extern int i915_resume(struct drm_device *dev);
1725 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1726 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1729 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1730 extern void i915_kernel_lost_context(struct drm_device * dev);
1731 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1732 extern int i915_driver_unload(struct drm_device *);
1733 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1734 extern void i915_driver_lastclose(struct drm_device * dev);
1735 extern void i915_driver_preclose(struct drm_device *dev,
1736 struct drm_file *file_priv);
1737 extern void i915_driver_postclose(struct drm_device *dev,
1738 struct drm_file *file_priv);
1739 extern int i915_driver_device_is_agp(struct drm_device * dev);
1740 #ifdef CONFIG_COMPAT
1741 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1744 extern int i915_emit_box(struct drm_device *dev,
1745 struct drm_clip_rect *box,
1747 extern int intel_gpu_reset(struct drm_device *dev);
1748 extern int i915_reset(struct drm_device *dev);
1749 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1750 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1751 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1752 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1754 extern void intel_console_resume(struct work_struct *work);
1757 void i915_queue_hangcheck(struct drm_device *dev);
1758 void i915_handle_error(struct drm_device *dev, bool wedged);
1760 extern void intel_irq_init(struct drm_device *dev);
1761 extern void intel_pm_init(struct drm_device *dev);
1762 extern void intel_hpd_init(struct drm_device *dev);
1763 extern void intel_pm_init(struct drm_device *dev);
1765 extern void intel_uncore_sanitize(struct drm_device *dev);
1766 extern void intel_uncore_early_sanitize(struct drm_device *dev);
1767 extern void intel_uncore_init(struct drm_device *dev);
1768 extern void intel_uncore_clear_errors(struct drm_device *dev);
1769 extern void intel_uncore_check_errors(struct drm_device *dev);
1772 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1775 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1778 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1779 struct drm_file *file_priv);
1780 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1781 struct drm_file *file_priv);
1782 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1783 struct drm_file *file_priv);
1784 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1785 struct drm_file *file_priv);
1786 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1787 struct drm_file *file_priv);
1788 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1789 struct drm_file *file_priv);
1790 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1791 struct drm_file *file_priv);
1792 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1793 struct drm_file *file_priv);
1794 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1795 struct drm_file *file_priv);
1796 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1797 struct drm_file *file_priv);
1798 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1799 struct drm_file *file_priv);
1800 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1801 struct drm_file *file_priv);
1802 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1803 struct drm_file *file_priv);
1804 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1805 struct drm_file *file);
1806 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1807 struct drm_file *file);
1808 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1809 struct drm_file *file_priv);
1810 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1811 struct drm_file *file_priv);
1812 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1813 struct drm_file *file_priv);
1814 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1815 struct drm_file *file_priv);
1816 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1817 struct drm_file *file_priv);
1818 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1819 struct drm_file *file_priv);
1820 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1821 struct drm_file *file_priv);
1822 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1823 struct drm_file *file_priv);
1824 void i915_gem_load(struct drm_device *dev);
1825 void *i915_gem_object_alloc(struct drm_device *dev);
1826 void i915_gem_object_free(struct drm_i915_gem_object *obj);
1827 int i915_gem_init_object(struct drm_gem_object *obj);
1828 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1829 const struct drm_i915_gem_object_ops *ops);
1830 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1832 void i915_gem_free_object(struct drm_gem_object *obj);
1833 struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
1834 struct i915_address_space *vm);
1835 void i915_gem_vma_destroy(struct i915_vma *vma);
1837 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1838 struct i915_address_space *vm,
1840 bool map_and_fenceable,
1842 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1843 int __must_check i915_vma_unbind(struct i915_vma *vma);
1844 int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);
1845 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1846 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1847 void i915_gem_lastclose(struct drm_device *dev);
1849 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1850 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1852 struct sg_page_iter sg_iter;
1854 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
1855 return sg_page_iter_page(&sg_iter);
1859 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1861 BUG_ON(obj->pages == NULL);
1862 obj->pages_pin_count++;
1864 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1866 BUG_ON(obj->pages_pin_count == 0);
1867 obj->pages_pin_count--;
1870 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1871 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1872 struct intel_ring_buffer *to);
1873 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1874 struct intel_ring_buffer *ring);
1876 int i915_gem_dumb_create(struct drm_file *file_priv,
1877 struct drm_device *dev,
1878 struct drm_mode_create_dumb *args);
1879 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1880 uint32_t handle, uint64_t *offset);
1882 * Returns true if seq1 is later than seq2.
1885 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1887 return (int32_t)(seq1 - seq2) >= 0;
1890 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1891 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1892 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1893 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1896 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1898 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1899 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1900 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1907 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1909 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1910 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1911 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
1912 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1916 void i915_gem_retire_requests(struct drm_device *dev);
1917 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1918 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
1919 bool interruptible);
1920 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1922 return unlikely(atomic_read(&error->reset_counter)
1923 & I915_RESET_IN_PROGRESS_FLAG);
1926 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1928 return atomic_read(&error->reset_counter) == I915_WEDGED;
1931 void i915_gem_reset(struct drm_device *dev);
1932 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
1933 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1934 int __must_check i915_gem_init(struct drm_device *dev);
1935 int __must_check i915_gem_init_hw(struct drm_device *dev);
1936 void i915_gem_l3_remap(struct drm_device *dev);
1937 void i915_gem_init_swizzling(struct drm_device *dev);
1938 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1939 int __must_check i915_gpu_idle(struct drm_device *dev);
1940 int __must_check i915_gem_idle(struct drm_device *dev);
1941 int __i915_add_request(struct intel_ring_buffer *ring,
1942 struct drm_file *file,
1943 struct drm_i915_gem_object *batch_obj,
1945 #define i915_add_request(ring, seqno) \
1946 __i915_add_request(ring, NULL, NULL, seqno)
1947 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1949 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1951 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1954 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1956 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1958 struct intel_ring_buffer *pipelined);
1959 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
1960 int i915_gem_attach_phys_object(struct drm_device *dev,
1961 struct drm_i915_gem_object *obj,
1964 void i915_gem_detach_phys_object(struct drm_device *dev,
1965 struct drm_i915_gem_object *obj);
1966 void i915_gem_free_all_phys_object(struct drm_device *dev);
1967 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1970 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1972 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1973 int tiling_mode, bool fenced);
1975 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1976 enum i915_cache_level cache_level);
1978 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1979 struct dma_buf *dma_buf);
1981 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1982 struct drm_gem_object *gem_obj, int flags);
1984 void i915_gem_restore_fences(struct drm_device *dev);
1986 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
1987 struct i915_address_space *vm);
1988 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
1989 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
1990 struct i915_address_space *vm);
1991 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
1992 struct i915_address_space *vm);
1993 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
1994 struct i915_address_space *vm);
1996 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
1997 struct i915_address_space *vm);
1998 /* Some GGTT VM helpers */
1999 #define obj_to_ggtt(obj) \
2000 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2001 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2003 struct i915_address_space *ggtt =
2004 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2008 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2010 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2013 static inline unsigned long
2014 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2016 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2019 static inline unsigned long
2020 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2022 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2025 static inline int __must_check
2026 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2028 bool map_and_fenceable,
2031 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment,
2032 map_and_fenceable, nonblocking);
2036 /* i915_gem_context.c */
2037 void i915_gem_context_init(struct drm_device *dev);
2038 void i915_gem_context_fini(struct drm_device *dev);
2039 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2040 int i915_switch_context(struct intel_ring_buffer *ring,
2041 struct drm_file *file, int to_id);
2042 void i915_gem_context_free(struct kref *ctx_ref);
2043 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2045 kref_get(&ctx->ref);
2048 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2050 kref_put(&ctx->ref, i915_gem_context_free);
2053 struct i915_ctx_hang_stats * __must_check
2054 i915_gem_context_get_hang_stats(struct drm_device *dev,
2055 struct drm_file *file,
2057 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2058 struct drm_file *file);
2059 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2060 struct drm_file *file);
2062 /* i915_gem_gtt.c */
2063 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
2064 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
2065 struct drm_i915_gem_object *obj,
2066 enum i915_cache_level cache_level);
2067 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
2068 struct drm_i915_gem_object *obj);
2070 void i915_check_and_clear_faults(struct drm_device *dev);
2071 void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
2072 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
2073 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
2074 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
2075 enum i915_cache_level cache_level);
2076 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
2077 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
2078 void i915_gem_init_global_gtt(struct drm_device *dev);
2079 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
2080 unsigned long mappable_end, unsigned long end);
2081 int i915_gem_gtt_init(struct drm_device *dev);
2082 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2084 if (INTEL_INFO(dev)->gen < 6)
2085 intel_gtt_chipset_flush();
2089 /* i915_gem_evict.c */
2090 int __must_check i915_gem_evict_something(struct drm_device *dev,
2091 struct i915_address_space *vm,
2094 unsigned cache_level,
2097 int i915_gem_evict_everything(struct drm_device *dev);
2099 /* i915_gem_stolen.c */
2100 int i915_gem_init_stolen(struct drm_device *dev);
2101 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2102 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2103 void i915_gem_cleanup_stolen(struct drm_device *dev);
2104 struct drm_i915_gem_object *
2105 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2106 struct drm_i915_gem_object *
2107 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2111 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2113 /* i915_gem_tiling.c */
2114 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2116 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2118 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2119 obj->tiling_mode != I915_TILING_NONE;
2122 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2123 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2124 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2126 /* i915_gem_debug.c */
2128 int i915_verify_lists(struct drm_device *dev);
2130 #define i915_verify_lists(dev) 0
2133 /* i915_debugfs.c */
2134 int i915_debugfs_init(struct drm_minor *minor);
2135 void i915_debugfs_cleanup(struct drm_minor *minor);
2137 /* i915_gpu_error.c */
2139 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2140 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2141 const struct i915_error_state_file_priv *error);
2142 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2143 size_t count, loff_t pos);
2144 static inline void i915_error_state_buf_release(
2145 struct drm_i915_error_state_buf *eb)
2149 void i915_capture_error_state(struct drm_device *dev);
2150 void i915_error_state_get(struct drm_device *dev,
2151 struct i915_error_state_file_priv *error_priv);
2152 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2153 void i915_destroy_error_state(struct drm_device *dev);
2155 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2156 const char *i915_cache_level_str(int type);
2158 /* i915_suspend.c */
2159 extern int i915_save_state(struct drm_device *dev);
2160 extern int i915_restore_state(struct drm_device *dev);
2163 void i915_save_display_reg(struct drm_device *dev);
2164 void i915_restore_display_reg(struct drm_device *dev);
2167 void i915_setup_sysfs(struct drm_device *dev_priv);
2168 void i915_teardown_sysfs(struct drm_device *dev_priv);
2171 extern int intel_setup_gmbus(struct drm_device *dev);
2172 extern void intel_teardown_gmbus(struct drm_device *dev);
2173 static inline bool intel_gmbus_is_port_valid(unsigned port)
2175 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2178 extern struct i2c_adapter *intel_gmbus_get_adapter(
2179 struct drm_i915_private *dev_priv, unsigned port);
2180 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2181 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2182 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2184 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2186 extern void intel_i2c_reset(struct drm_device *dev);
2188 /* intel_opregion.c */
2189 extern int intel_opregion_setup(struct drm_device *dev);
2191 extern void intel_opregion_init(struct drm_device *dev);
2192 extern void intel_opregion_fini(struct drm_device *dev);
2193 extern void intel_opregion_asle_intr(struct drm_device *dev);
2195 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2196 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2197 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2202 extern void intel_register_dsm_handler(void);
2203 extern void intel_unregister_dsm_handler(void);
2205 static inline void intel_register_dsm_handler(void) { return; }
2206 static inline void intel_unregister_dsm_handler(void) { return; }
2207 #endif /* CONFIG_ACPI */
2210 extern void intel_modeset_init_hw(struct drm_device *dev);
2211 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2212 extern void intel_modeset_init(struct drm_device *dev);
2213 extern void intel_modeset_gem_init(struct drm_device *dev);
2214 extern void intel_modeset_cleanup(struct drm_device *dev);
2215 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2216 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2217 bool force_restore);
2218 extern void i915_redisable_vga(struct drm_device *dev);
2219 extern bool intel_fbc_enabled(struct drm_device *dev);
2220 extern void intel_disable_fbc(struct drm_device *dev);
2221 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2222 extern void intel_init_pch_refclk(struct drm_device *dev);
2223 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2224 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2225 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2226 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2227 extern void intel_detect_pch(struct drm_device *dev);
2228 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2229 extern int intel_enable_rc6(const struct drm_device *dev);
2231 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2232 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2233 struct drm_file *file);
2236 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2237 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2238 struct intel_overlay_error_state *error);
2240 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2241 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2242 struct drm_device *dev,
2243 struct intel_display_error_state *error);
2245 /* On SNB platform, before reading ring registers forcewake bit
2246 * must be set to prevent GT core from power down and stale values being
2249 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
2250 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
2252 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2253 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2255 /* intel_sideband.c */
2256 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2257 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2258 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2259 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
2260 void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
2261 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2262 enum intel_sbi_destination destination);
2263 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2264 enum intel_sbi_destination destination);
2266 int vlv_gpu_freq(int ddr_freq, int val);
2267 int vlv_freq_opcode(int ddr_freq, int val);
2269 #define __i915_read(x) \
2270 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace);
2277 #define __i915_write(x) \
2278 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace);
2285 #define I915_READ8(reg) i915_read8(dev_priv, (reg), true)
2286 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val), true)
2288 #define I915_READ16(reg) i915_read16(dev_priv, (reg), true)
2289 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val), true)
2290 #define I915_READ16_NOTRACE(reg) i915_read16(dev_priv, (reg), false)
2291 #define I915_WRITE16_NOTRACE(reg, val) i915_write16(dev_priv, (reg), (val), false)
2293 #define I915_READ(reg) i915_read32(dev_priv, (reg), true)
2294 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val), true)
2295 #define I915_READ_NOTRACE(reg) i915_read32(dev_priv, (reg), false)
2296 #define I915_WRITE_NOTRACE(reg, val) i915_write32(dev_priv, (reg), (val), false)
2298 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val), true)
2299 #define I915_READ64(reg) i915_read64(dev_priv, (reg), true)
2301 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2302 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2304 /* "Broadcast RGB" property */
2305 #define INTEL_BROADCAST_RGB_AUTO 0
2306 #define INTEL_BROADCAST_RGB_FULL 1
2307 #define INTEL_BROADCAST_RGB_LIMITED 2
2309 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2311 if (HAS_PCH_SPLIT(dev))
2312 return CPU_VGACNTRL;
2313 else if (IS_VALLEYVIEW(dev))
2314 return VLV_VGACNTRL;
2319 static inline void __user *to_user_ptr(u64 address)
2321 return (void __user *)(uintptr_t)address;
2324 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2326 unsigned long j = msecs_to_jiffies(m);
2328 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2331 static inline unsigned long
2332 timespec_to_jiffies_timeout(const struct timespec *value)
2334 unsigned long j = timespec_to_jiffies(value);
2336 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);