1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "intel_lrc.h"
39 #include "i915_gem_gtt.h"
40 #include "i915_gem_render_state.h"
41 #include <linux/io-mapping.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
44 #include <drm/intel-gtt.h>
45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
46 #include <drm/drm_gem.h>
47 #include <linux/backlight.h>
48 #include <linux/hashtable.h>
49 #include <linux/intel-iommu.h>
50 #include <linux/kref.h>
51 #include <linux/pm_qos.h>
53 /* General customization:
56 #define DRIVER_NAME "i915"
57 #define DRIVER_DESC "Intel Graphics"
58 #define DRIVER_DATE "20141121"
61 #define WARN_ON(x) WARN(x, "WARN_ON(" #x ")")
69 I915_MAX_PIPES = _PIPE_EDP
71 #define pipe_name(p) ((p) + 'A')
80 #define transcoder_name(t) ((t) + 'A')
83 * This is the maximum (across all platforms) number of planes (primary +
84 * sprites) that can be active at the same time on one pipe.
86 * This value doesn't count the cursor plane.
88 #define I915_MAX_PLANES 3
95 #define plane_name(p) ((p) + 'A')
97 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
107 #define port_name(p) ((p) + 'A')
109 #define I915_NUM_PHYS_VLV 2
121 enum intel_display_power_domain {
125 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
126 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
127 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
128 POWER_DOMAIN_TRANSCODER_A,
129 POWER_DOMAIN_TRANSCODER_B,
130 POWER_DOMAIN_TRANSCODER_C,
131 POWER_DOMAIN_TRANSCODER_EDP,
132 POWER_DOMAIN_PORT_DDI_A_2_LANES,
133 POWER_DOMAIN_PORT_DDI_A_4_LANES,
134 POWER_DOMAIN_PORT_DDI_B_2_LANES,
135 POWER_DOMAIN_PORT_DDI_B_4_LANES,
136 POWER_DOMAIN_PORT_DDI_C_2_LANES,
137 POWER_DOMAIN_PORT_DDI_C_4_LANES,
138 POWER_DOMAIN_PORT_DDI_D_2_LANES,
139 POWER_DOMAIN_PORT_DDI_D_4_LANES,
140 POWER_DOMAIN_PORT_DSI,
141 POWER_DOMAIN_PORT_CRT,
142 POWER_DOMAIN_PORT_OTHER,
151 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
152 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
153 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
154 #define POWER_DOMAIN_TRANSCODER(tran) \
155 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
156 (tran) + POWER_DOMAIN_TRANSCODER_A)
160 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
161 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
171 #define I915_GEM_GPU_DOMAINS \
172 (I915_GEM_DOMAIN_RENDER | \
173 I915_GEM_DOMAIN_SAMPLER | \
174 I915_GEM_DOMAIN_COMMAND | \
175 I915_GEM_DOMAIN_INSTRUCTION | \
176 I915_GEM_DOMAIN_VERTEX)
178 #define for_each_pipe(__dev_priv, __p) \
179 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
180 #define for_each_plane(pipe, p) \
181 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
182 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
184 #define for_each_crtc(dev, crtc) \
185 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
187 #define for_each_intel_crtc(dev, intel_crtc) \
188 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
190 #define for_each_intel_encoder(dev, intel_encoder) \
191 list_for_each_entry(intel_encoder, \
192 &(dev)->mode_config.encoder_list, \
195 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
196 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
197 if ((intel_encoder)->base.crtc == (__crtc))
199 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
200 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
201 if ((intel_connector)->base.encoder == (__encoder))
203 #define for_each_power_domain(domain, mask) \
204 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
205 if ((1 << (domain)) & (mask))
207 struct drm_i915_private;
208 struct i915_mm_struct;
209 struct i915_mmu_object;
212 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
213 /* real shared dpll ids must be >= 0 */
214 DPLL_ID_PCH_PLL_A = 0,
215 DPLL_ID_PCH_PLL_B = 1,
220 DPLL_ID_SKL_DPLL1 = 0,
221 DPLL_ID_SKL_DPLL2 = 1,
222 DPLL_ID_SKL_DPLL3 = 2,
224 #define I915_NUM_PLLS 3
226 struct intel_dpll_hw_state {
238 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
239 * lower part of crtl1 and they get shifted into position when writing
240 * the register. This allows us to easily compare the state to share
244 /* HDMI only, 0 when used for DP */
245 uint32_t cfgcr1, cfgcr2;
248 struct intel_shared_dpll_config {
249 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
250 struct intel_dpll_hw_state hw_state;
253 struct intel_shared_dpll {
254 struct intel_shared_dpll_config config;
255 struct intel_shared_dpll_config *new_config;
257 int active; /* count of number of active CRTCs (i.e. DPMS on) */
258 bool on; /* is the PLL actually active? Disabled during modeset */
260 /* should match the index in the dev_priv->shared_dplls array */
261 enum intel_dpll_id id;
262 /* The mode_set hook is optional and should be used together with the
263 * intel_prepare_shared_dpll function. */
264 void (*mode_set)(struct drm_i915_private *dev_priv,
265 struct intel_shared_dpll *pll);
266 void (*enable)(struct drm_i915_private *dev_priv,
267 struct intel_shared_dpll *pll);
268 void (*disable)(struct drm_i915_private *dev_priv,
269 struct intel_shared_dpll *pll);
270 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
271 struct intel_shared_dpll *pll,
272 struct intel_dpll_hw_state *hw_state);
280 /* Used by dp and fdi links */
281 struct intel_link_m_n {
289 void intel_link_compute_m_n(int bpp, int nlanes,
290 int pixel_clock, int link_clock,
291 struct intel_link_m_n *m_n);
293 /* Interface history:
296 * 1.2: Add Power Management
297 * 1.3: Add vblank support
298 * 1.4: Fix cmdbuffer path, add heap destroy
299 * 1.5: Add vblank pipe configuration
300 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
301 * - Support vertical blank on secondary display pipe
303 #define DRIVER_MAJOR 1
304 #define DRIVER_MINOR 6
305 #define DRIVER_PATCHLEVEL 0
307 #define WATCH_LISTS 0
309 struct opregion_header;
310 struct opregion_acpi;
311 struct opregion_swsci;
312 struct opregion_asle;
314 struct intel_opregion {
315 struct opregion_header __iomem *header;
316 struct opregion_acpi __iomem *acpi;
317 struct opregion_swsci __iomem *swsci;
318 u32 swsci_gbda_sub_functions;
319 u32 swsci_sbcb_sub_functions;
320 struct opregion_asle __iomem *asle;
322 u32 __iomem *lid_state;
323 struct work_struct asle_work;
325 #define OPREGION_SIZE (8*1024)
327 struct intel_overlay;
328 struct intel_overlay_error_state;
330 #define I915_FENCE_REG_NONE -1
331 #define I915_MAX_NUM_FENCES 32
332 /* 32 fences + sign bit for FENCE_REG_NONE */
333 #define I915_MAX_NUM_FENCE_BITS 6
335 struct drm_i915_fence_reg {
336 struct list_head lru_list;
337 struct drm_i915_gem_object *obj;
341 struct sdvo_device_mapping {
350 struct intel_display_error_state;
352 struct drm_i915_error_state {
360 /* Generic register state */
368 u32 error; /* gen6+ */
369 u32 err_int; /* gen7 */
375 u32 extra_instdone[I915_NUM_INSTDONE_REG];
376 u64 fence[I915_MAX_NUM_FENCES];
377 struct intel_overlay_error_state *overlay;
378 struct intel_display_error_state *display;
379 struct drm_i915_error_object *semaphore_obj;
381 struct drm_i915_error_ring {
383 /* Software tracked state */
386 enum intel_ring_hangcheck_action hangcheck_action;
389 /* our own tracking of ring head and tail */
393 u32 semaphore_seqno[I915_NUM_RINGS - 1];
411 u32 rc_psmi; /* sleep state */
412 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
414 struct drm_i915_error_object {
418 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
420 struct drm_i915_error_request {
435 char comm[TASK_COMM_LEN];
436 } ring[I915_NUM_RINGS];
438 struct drm_i915_error_buffer {
445 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
453 } **active_bo, **pinned_bo;
455 u32 *active_bo_count, *pinned_bo_count;
459 struct intel_connector;
460 struct intel_encoder;
461 struct intel_crtc_config;
462 struct intel_plane_config;
467 struct drm_i915_display_funcs {
468 bool (*fbc_enabled)(struct drm_device *dev);
469 void (*enable_fbc)(struct drm_crtc *crtc);
470 void (*disable_fbc)(struct drm_device *dev);
471 int (*get_display_clock_speed)(struct drm_device *dev);
472 int (*get_fifo_size)(struct drm_device *dev, int plane);
474 * find_dpll() - Find the best values for the PLL
475 * @limit: limits for the PLL
476 * @crtc: current CRTC
477 * @target: target frequency in kHz
478 * @refclk: reference clock frequency in kHz
479 * @match_clock: if provided, @best_clock P divider must
480 * match the P divider from @match_clock
481 * used for LVDS downclocking
482 * @best_clock: best PLL values found
484 * Returns true on success, false on failure.
486 bool (*find_dpll)(const struct intel_limit *limit,
487 struct intel_crtc *crtc,
488 int target, int refclk,
489 struct dpll *match_clock,
490 struct dpll *best_clock);
491 void (*update_wm)(struct drm_crtc *crtc);
492 void (*update_sprite_wm)(struct drm_plane *plane,
493 struct drm_crtc *crtc,
494 uint32_t sprite_width, uint32_t sprite_height,
495 int pixel_size, bool enable, bool scaled);
496 void (*modeset_global_resources)(struct drm_device *dev);
497 /* Returns the active state of the crtc, and if the crtc is active,
498 * fills out the pipe-config with the hw state. */
499 bool (*get_pipe_config)(struct intel_crtc *,
500 struct intel_crtc_config *);
501 void (*get_plane_config)(struct intel_crtc *,
502 struct intel_plane_config *);
503 int (*crtc_compute_clock)(struct intel_crtc *crtc);
504 void (*crtc_enable)(struct drm_crtc *crtc);
505 void (*crtc_disable)(struct drm_crtc *crtc);
506 void (*off)(struct drm_crtc *crtc);
507 void (*audio_codec_enable)(struct drm_connector *connector,
508 struct intel_encoder *encoder,
509 struct drm_display_mode *mode);
510 void (*audio_codec_disable)(struct intel_encoder *encoder);
511 void (*fdi_link_train)(struct drm_crtc *crtc);
512 void (*init_clock_gating)(struct drm_device *dev);
513 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
514 struct drm_framebuffer *fb,
515 struct drm_i915_gem_object *obj,
516 struct intel_engine_cs *ring,
518 void (*update_primary_plane)(struct drm_crtc *crtc,
519 struct drm_framebuffer *fb,
521 void (*hpd_irq_setup)(struct drm_device *dev);
522 /* clock updates for mode set */
524 /* render clock increase/decrease */
525 /* display clock increase/decrease */
526 /* pll clock increase/decrease */
528 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
529 uint32_t (*get_backlight)(struct intel_connector *connector);
530 void (*set_backlight)(struct intel_connector *connector,
532 void (*disable_backlight)(struct intel_connector *connector);
533 void (*enable_backlight)(struct intel_connector *connector);
536 struct intel_uncore_funcs {
537 void (*force_wake_get)(struct drm_i915_private *dev_priv,
539 void (*force_wake_put)(struct drm_i915_private *dev_priv,
542 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
543 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
544 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
545 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
547 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
548 uint8_t val, bool trace);
549 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
550 uint16_t val, bool trace);
551 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
552 uint32_t val, bool trace);
553 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
554 uint64_t val, bool trace);
557 struct intel_uncore {
558 spinlock_t lock; /** lock is also taken in irq contexts. */
560 struct intel_uncore_funcs funcs;
563 unsigned forcewake_count;
565 unsigned fw_rendercount;
566 unsigned fw_mediacount;
567 unsigned fw_blittercount;
569 struct timer_list force_wake_timer;
572 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
573 func(is_mobile) sep \
576 func(is_i945gm) sep \
578 func(need_gfx_hws) sep \
580 func(is_pineview) sep \
581 func(is_broadwater) sep \
582 func(is_crestline) sep \
583 func(is_ivybridge) sep \
584 func(is_valleyview) sep \
585 func(is_haswell) sep \
586 func(is_skylake) sep \
587 func(is_preliminary) sep \
589 func(has_pipe_cxsr) sep \
590 func(has_hotplug) sep \
591 func(cursor_needs_physical) sep \
592 func(has_overlay) sep \
593 func(overlay_needs_physical) sep \
594 func(supports_tv) sep \
599 #define DEFINE_FLAG(name) u8 name:1
600 #define SEP_SEMICOLON ;
602 struct intel_device_info {
603 u32 display_mmio_offset;
606 u8 num_sprites[I915_MAX_PIPES];
608 u8 ring_mask; /* Rings supported by the HW */
609 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
610 /* Register offsets for the various display pipes and transcoders */
611 int pipe_offsets[I915_MAX_TRANSCODERS];
612 int trans_offsets[I915_MAX_TRANSCODERS];
613 int palette_offsets[I915_MAX_PIPES];
614 int cursor_offsets[I915_MAX_PIPES];
620 enum i915_cache_level {
622 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
623 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
624 caches, eg sampler/render caches, and the
625 large Last-Level-Cache. LLC is coherent with
626 the CPU, but L3 is only visible to the GPU. */
627 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
630 struct i915_ctx_hang_stats {
631 /* This context had batch pending when hang was declared */
632 unsigned batch_pending;
634 /* This context had batch active when hang was declared */
635 unsigned batch_active;
637 /* Time when this context was last blamed for a GPU reset */
638 unsigned long guilty_ts;
640 /* This context is banned to submit more work */
644 /* This must match up with the value previously used for execbuf2.rsvd1. */
645 #define DEFAULT_CONTEXT_HANDLE 0
647 * struct intel_context - as the name implies, represents a context.
648 * @ref: reference count.
649 * @user_handle: userspace tracking identity for this context.
650 * @remap_slice: l3 row remapping information.
651 * @file_priv: filp associated with this context (NULL for global default
653 * @hang_stats: information about the role of this context in possible GPU
655 * @vm: virtual memory space used by this context.
656 * @legacy_hw_ctx: render context backing object and whether it is correctly
657 * initialized (legacy ring submission mechanism only).
658 * @link: link in the global list of contexts.
660 * Contexts are memory images used by the hardware to store copies of their
663 struct intel_context {
667 struct drm_i915_file_private *file_priv;
668 struct i915_ctx_hang_stats hang_stats;
669 struct i915_hw_ppgtt *ppgtt;
671 /* Legacy ring buffer submission */
673 struct drm_i915_gem_object *rcs_state;
678 bool rcs_initialized;
680 struct drm_i915_gem_object *state;
681 struct intel_ringbuffer *ringbuf;
683 } engine[I915_NUM_RINGS];
685 struct list_head link;
695 struct drm_mm_node compressed_fb;
696 struct drm_mm_node *compressed_llb;
700 /* Tracks whether the HW is actually enabled, not whether the feature is
704 /* On gen8 some rings cannont perform fbc clean operation so for now
705 * we are doing this on SW with mmio.
706 * This variable works in the opposite information direction
707 * of ring->fbc_dirty telling software on frontbuffer tracking
708 * to perform the cache clean on sw side.
710 bool need_sw_cache_clean;
712 struct intel_fbc_work {
713 struct delayed_work work;
714 struct drm_crtc *crtc;
715 struct drm_framebuffer *fb;
719 FBC_OK, /* FBC is enabled */
720 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
721 FBC_NO_OUTPUT, /* no outputs enabled to compress */
722 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
723 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
724 FBC_MODE_TOO_LARGE, /* mode too large for compression */
725 FBC_BAD_PLANE, /* fbc not supported on plane */
726 FBC_NOT_TILED, /* buffer not tiled */
727 FBC_MULTIPLE_PIPES, /* more than one pipe active */
729 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
734 struct intel_connector *connector;
742 struct intel_dp *enabled;
744 struct delayed_work work;
745 unsigned busy_frontbuffer_bits;
749 PCH_NONE = 0, /* No PCH present */
750 PCH_IBX, /* Ibexpeak PCH */
751 PCH_CPT, /* Cougarpoint PCH */
752 PCH_LPT, /* Lynxpoint PCH */
753 PCH_SPT, /* Sunrisepoint PCH */
757 enum intel_sbi_destination {
762 #define QUIRK_PIPEA_FORCE (1<<0)
763 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
764 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
765 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
766 #define QUIRK_PIPEB_FORCE (1<<4)
767 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
770 struct intel_fbc_work;
773 struct i2c_adapter adapter;
777 struct i2c_algo_bit_data bit_algo;
778 struct drm_i915_private *dev_priv;
781 struct i915_suspend_saved_registers {
802 u32 saveTRANS_HTOTAL_A;
803 u32 saveTRANS_HBLANK_A;
804 u32 saveTRANS_HSYNC_A;
805 u32 saveTRANS_VTOTAL_A;
806 u32 saveTRANS_VBLANK_A;
807 u32 saveTRANS_VSYNC_A;
815 u32 savePFIT_PGM_RATIOS;
816 u32 saveBLC_HIST_CTL;
818 u32 saveBLC_PWM_CTL2;
819 u32 saveBLC_CPU_PWM_CTL;
820 u32 saveBLC_CPU_PWM_CTL2;
833 u32 saveTRANS_HTOTAL_B;
834 u32 saveTRANS_HBLANK_B;
835 u32 saveTRANS_HSYNC_B;
836 u32 saveTRANS_VTOTAL_B;
837 u32 saveTRANS_VBLANK_B;
838 u32 saveTRANS_VSYNC_B;
852 u32 savePP_ON_DELAYS;
853 u32 savePP_OFF_DELAYS;
861 u32 savePFIT_CONTROL;
862 u32 save_palette_a[256];
863 u32 save_palette_b[256];
874 u32 saveCACHE_MODE_0;
875 u32 saveMI_ARB_STATE;
886 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
897 u32 savePIPEA_GMCH_DATA_M;
898 u32 savePIPEB_GMCH_DATA_M;
899 u32 savePIPEA_GMCH_DATA_N;
900 u32 savePIPEB_GMCH_DATA_N;
901 u32 savePIPEA_DP_LINK_M;
902 u32 savePIPEB_DP_LINK_M;
903 u32 savePIPEA_DP_LINK_N;
904 u32 savePIPEB_DP_LINK_N;
915 u32 savePCH_DREF_CONTROL;
916 u32 saveDISP_ARB_CTL;
917 u32 savePIPEA_DATA_M1;
918 u32 savePIPEA_DATA_N1;
919 u32 savePIPEA_LINK_M1;
920 u32 savePIPEA_LINK_N1;
921 u32 savePIPEB_DATA_M1;
922 u32 savePIPEB_DATA_N1;
923 u32 savePIPEB_LINK_M1;
924 u32 savePIPEB_LINK_N1;
925 u32 saveMCHBAR_RENDER_STANDBY;
926 u32 savePCH_PORT_HOTPLUG;
929 struct vlv_s0ix_state {
936 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
937 u32 media_max_req_count;
938 u32 gfx_max_req_count;
970 /* Display 1 CZ domain */
975 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
977 /* GT SA CZ domain */
984 /* Display 2 CZ domain */
990 struct intel_rps_ei {
996 struct intel_gen6_power_mgmt {
998 * work, interrupts_enabled and pm_iir are protected by
1001 struct work_struct work;
1002 bool interrupts_enabled;
1005 /* Frequencies are stored in potentially platform dependent multiples.
1006 * In other words, *_freq needs to be multiplied by X to be interesting.
1007 * Soft limits are those which are used for the dynamic reclocking done
1008 * by the driver (raise frequencies under heavy loads, and lower for
1009 * lighter loads). Hard limits are those imposed by the hardware.
1011 * A distinction is made for overclocking, which is never enabled by
1012 * default, and is considered to be above the hard limit if it's
1015 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1016 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1017 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1018 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1019 u8 min_freq; /* AKA RPn. Minimum frequency */
1020 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1021 u8 rp1_freq; /* "less than" RP0 power/freqency */
1022 u8 rp0_freq; /* Non-overclocked max frequency. */
1025 u32 ei_interrupt_count;
1028 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1031 struct delayed_work delayed_resume_work;
1033 /* manual wa residency calculations */
1034 struct intel_rps_ei up_ei, down_ei;
1037 * Protects RPS/RC6 register access and PCU communication.
1038 * Must be taken after struct_mutex if nested.
1040 struct mutex hw_lock;
1043 /* defined intel_pm.c */
1044 extern spinlock_t mchdev_lock;
1046 struct intel_ilk_power_mgmt {
1054 unsigned long last_time1;
1055 unsigned long chipset_power;
1058 unsigned long gfx_power;
1064 struct drm_i915_gem_object *pwrctx;
1065 struct drm_i915_gem_object *renderctx;
1068 struct drm_i915_private;
1069 struct i915_power_well;
1071 struct i915_power_well_ops {
1073 * Synchronize the well's hw state to match the current sw state, for
1074 * example enable/disable it based on the current refcount. Called
1075 * during driver init and resume time, possibly after first calling
1076 * the enable/disable handlers.
1078 void (*sync_hw)(struct drm_i915_private *dev_priv,
1079 struct i915_power_well *power_well);
1081 * Enable the well and resources that depend on it (for example
1082 * interrupts located on the well). Called after the 0->1 refcount
1085 void (*enable)(struct drm_i915_private *dev_priv,
1086 struct i915_power_well *power_well);
1088 * Disable the well and resources that depend on it. Called after
1089 * the 1->0 refcount transition.
1091 void (*disable)(struct drm_i915_private *dev_priv,
1092 struct i915_power_well *power_well);
1093 /* Returns the hw enabled state. */
1094 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1095 struct i915_power_well *power_well);
1098 /* Power well structure for haswell */
1099 struct i915_power_well {
1102 /* power well enable/disable usage count */
1104 /* cached hw enabled state */
1106 unsigned long domains;
1108 const struct i915_power_well_ops *ops;
1111 struct i915_power_domains {
1113 * Power wells needed for initialization at driver init and suspend
1114 * time are on. They are kept on until after the first modeset.
1118 int power_well_count;
1121 int domain_use_count[POWER_DOMAIN_NUM];
1122 struct i915_power_well *power_wells;
1125 #define MAX_L3_SLICES 2
1126 struct intel_l3_parity {
1127 u32 *remap_info[MAX_L3_SLICES];
1128 struct work_struct error_work;
1132 struct i915_gem_mm {
1133 /** Memory allocator for GTT stolen memory */
1134 struct drm_mm stolen;
1135 /** List of all objects in gtt_space. Used to restore gtt
1136 * mappings on resume */
1137 struct list_head bound_list;
1139 * List of objects which are not bound to the GTT (thus
1140 * are idle and not used by the GPU) but still have
1141 * (presumably uncached) pages still attached.
1143 struct list_head unbound_list;
1145 /** Usable portion of the GTT for GEM */
1146 unsigned long stolen_base; /* limited to low memory (32-bit) */
1148 /** PPGTT used for aliasing the PPGTT with the GTT */
1149 struct i915_hw_ppgtt *aliasing_ppgtt;
1151 struct notifier_block oom_notifier;
1152 struct shrinker shrinker;
1153 bool shrinker_no_lock_stealing;
1155 /** LRU list of objects with fence regs on them. */
1156 struct list_head fence_list;
1159 * We leave the user IRQ off as much as possible,
1160 * but this means that requests will finish and never
1161 * be retired once the system goes idle. Set a timer to
1162 * fire periodically while the ring is running. When it
1163 * fires, go retire requests.
1165 struct delayed_work retire_work;
1168 * When we detect an idle GPU, we want to turn on
1169 * powersaving features. So once we see that there
1170 * are no more requests outstanding and no more
1171 * arrive within a small period of time, we fire
1172 * off the idle_work.
1174 struct delayed_work idle_work;
1177 * Are we in a non-interruptible section of code like
1183 * Is the GPU currently considered idle, or busy executing userspace
1184 * requests? Whilst idle, we attempt to power down the hardware and
1185 * display clocks. In order to reduce the effect on performance, there
1186 * is a slight delay before we do so.
1190 /* the indicator for dispatch video commands on two BSD rings */
1191 int bsd_ring_dispatch_index;
1193 /** Bit 6 swizzling required for X tiling */
1194 uint32_t bit_6_swizzle_x;
1195 /** Bit 6 swizzling required for Y tiling */
1196 uint32_t bit_6_swizzle_y;
1198 /* accounting, useful for userland debugging */
1199 spinlock_t object_stat_lock;
1200 size_t object_memory;
1204 struct drm_i915_error_state_buf {
1205 struct drm_i915_private *i915;
1214 struct i915_error_state_file_priv {
1215 struct drm_device *dev;
1216 struct drm_i915_error_state *error;
1219 struct i915_gpu_error {
1220 /* For hangcheck timer */
1221 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1222 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1223 /* Hang gpu twice in this window and your context gets banned */
1224 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1226 struct timer_list hangcheck_timer;
1228 /* For reset and error_state handling. */
1230 /* Protected by the above dev->gpu_error.lock. */
1231 struct drm_i915_error_state *first_error;
1232 struct work_struct work;
1235 unsigned long missed_irq_rings;
1238 * State variable controlling the reset flow and count
1240 * This is a counter which gets incremented when reset is triggered,
1241 * and again when reset has been handled. So odd values (lowest bit set)
1242 * means that reset is in progress and even values that
1243 * (reset_counter >> 1):th reset was successfully completed.
1245 * If reset is not completed succesfully, the I915_WEDGE bit is
1246 * set meaning that hardware is terminally sour and there is no
1247 * recovery. All waiters on the reset_queue will be woken when
1250 * This counter is used by the wait_seqno code to notice that reset
1251 * event happened and it needs to restart the entire ioctl (since most
1252 * likely the seqno it waited for won't ever signal anytime soon).
1254 * This is important for lock-free wait paths, where no contended lock
1255 * naturally enforces the correct ordering between the bail-out of the
1256 * waiter and the gpu reset work code.
1258 atomic_t reset_counter;
1260 #define I915_RESET_IN_PROGRESS_FLAG 1
1261 #define I915_WEDGED (1 << 31)
1264 * Waitqueue to signal when the reset has completed. Used by clients
1265 * that wait for dev_priv->mm.wedged to settle.
1267 wait_queue_head_t reset_queue;
1269 /* Userspace knobs for gpu hang simulation;
1270 * combines both a ring mask, and extra flags
1273 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1274 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1276 /* For missed irq/seqno simulation. */
1277 unsigned int test_irq_rings;
1279 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1280 bool reload_in_reset;
1283 enum modeset_restore {
1284 MODESET_ON_LID_OPEN,
1289 struct ddi_vbt_port_info {
1291 * This is an index in the HDMI/DVI DDI buffer translation table.
1292 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1293 * populate this field.
1295 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1296 uint8_t hdmi_level_shift;
1298 uint8_t supports_dvi:1;
1299 uint8_t supports_hdmi:1;
1300 uint8_t supports_dp:1;
1303 enum drrs_support_type {
1304 DRRS_NOT_SUPPORTED = 0,
1305 STATIC_DRRS_SUPPORT = 1,
1306 SEAMLESS_DRRS_SUPPORT = 2
1309 enum psr_lines_to_wait {
1310 PSR_0_LINES_TO_WAIT = 0,
1312 PSR_4_LINES_TO_WAIT,
1316 struct intel_vbt_data {
1317 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1318 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1321 unsigned int int_tv_support:1;
1322 unsigned int lvds_dither:1;
1323 unsigned int lvds_vbt:1;
1324 unsigned int int_crt_support:1;
1325 unsigned int lvds_use_ssc:1;
1326 unsigned int display_clock_mode:1;
1327 unsigned int fdi_rx_polarity_inverted:1;
1328 unsigned int has_mipi:1;
1330 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1332 enum drrs_support_type drrs_type;
1337 int edp_preemphasis;
1339 bool edp_initialized;
1342 struct edp_power_seq edp_pps;
1346 bool require_aux_wakeup;
1348 enum psr_lines_to_wait lines_to_wait;
1349 int tp1_wakeup_time;
1350 int tp2_tp3_wakeup_time;
1356 bool active_low_pwm;
1357 u8 min_brightness; /* min_brightness/255 of max */
1364 struct mipi_config *config;
1365 struct mipi_pps_data *pps;
1369 u8 *sequence[MIPI_SEQ_MAX];
1375 union child_device_config *child_dev;
1377 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1380 enum intel_ddb_partitioning {
1382 INTEL_DDB_PART_5_6, /* IVB+ */
1385 struct intel_wm_level {
1393 struct ilk_wm_values {
1394 uint32_t wm_pipe[3];
1396 uint32_t wm_lp_spr[3];
1397 uint32_t wm_linetime[3];
1399 enum intel_ddb_partitioning partitioning;
1402 struct skl_ddb_entry {
1403 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1406 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1408 return entry->end - entry->start;
1411 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1412 const struct skl_ddb_entry *e2)
1414 if (e1->start == e2->start && e1->end == e2->end)
1420 struct skl_ddb_allocation {
1421 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1422 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1423 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1426 struct skl_wm_values {
1427 bool dirty[I915_MAX_PIPES];
1428 struct skl_ddb_allocation ddb;
1429 uint32_t wm_linetime[I915_MAX_PIPES];
1430 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1431 uint32_t cursor[I915_MAX_PIPES][8];
1432 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1433 uint32_t cursor_trans[I915_MAX_PIPES];
1436 struct skl_wm_level {
1437 bool plane_en[I915_MAX_PLANES];
1439 uint16_t plane_res_b[I915_MAX_PLANES];
1440 uint8_t plane_res_l[I915_MAX_PLANES];
1441 uint16_t cursor_res_b;
1442 uint8_t cursor_res_l;
1446 * This struct helps tracking the state needed for runtime PM, which puts the
1447 * device in PCI D3 state. Notice that when this happens, nothing on the
1448 * graphics device works, even register access, so we don't get interrupts nor
1451 * Every piece of our code that needs to actually touch the hardware needs to
1452 * either call intel_runtime_pm_get or call intel_display_power_get with the
1453 * appropriate power domain.
1455 * Our driver uses the autosuspend delay feature, which means we'll only really
1456 * suspend if we stay with zero refcount for a certain amount of time. The
1457 * default value is currently very conservative (see intel_runtime_pm_enable), but
1458 * it can be changed with the standard runtime PM files from sysfs.
1460 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1461 * goes back to false exactly before we reenable the IRQs. We use this variable
1462 * to check if someone is trying to enable/disable IRQs while they're supposed
1463 * to be disabled. This shouldn't happen and we'll print some error messages in
1466 * For more, read the Documentation/power/runtime_pm.txt.
1468 struct i915_runtime_pm {
1473 enum intel_pipe_crc_source {
1474 INTEL_PIPE_CRC_SOURCE_NONE,
1475 INTEL_PIPE_CRC_SOURCE_PLANE1,
1476 INTEL_PIPE_CRC_SOURCE_PLANE2,
1477 INTEL_PIPE_CRC_SOURCE_PF,
1478 INTEL_PIPE_CRC_SOURCE_PIPE,
1479 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1480 INTEL_PIPE_CRC_SOURCE_TV,
1481 INTEL_PIPE_CRC_SOURCE_DP_B,
1482 INTEL_PIPE_CRC_SOURCE_DP_C,
1483 INTEL_PIPE_CRC_SOURCE_DP_D,
1484 INTEL_PIPE_CRC_SOURCE_AUTO,
1485 INTEL_PIPE_CRC_SOURCE_MAX,
1488 struct intel_pipe_crc_entry {
1493 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1494 struct intel_pipe_crc {
1496 bool opened; /* exclusive access to the result file */
1497 struct intel_pipe_crc_entry *entries;
1498 enum intel_pipe_crc_source source;
1500 wait_queue_head_t wq;
1503 struct i915_frontbuffer_tracking {
1507 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1514 struct i915_wa_reg {
1517 /* bitmask representing WA bits */
1521 #define I915_MAX_WA_REGS 16
1523 struct i915_workarounds {
1524 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1528 struct drm_i915_private {
1529 struct drm_device *dev;
1530 struct kmem_cache *slab;
1532 const struct intel_device_info info;
1534 int relative_constants_mode;
1538 struct intel_uncore uncore;
1540 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1543 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1544 * controller on different i2c buses. */
1545 struct mutex gmbus_mutex;
1548 * Base address of the gmbus and gpio block.
1550 uint32_t gpio_mmio_base;
1552 /* MMIO base address for MIPI regs */
1553 uint32_t mipi_mmio_base;
1555 wait_queue_head_t gmbus_wait_queue;
1557 struct pci_dev *bridge_dev;
1558 struct intel_engine_cs ring[I915_NUM_RINGS];
1559 struct drm_i915_gem_object *semaphore_obj;
1560 uint32_t last_seqno, next_seqno;
1562 struct drm_dma_handle *status_page_dmah;
1563 struct resource mch_res;
1565 /* protects the irq masks */
1566 spinlock_t irq_lock;
1568 /* protects the mmio flip data */
1569 spinlock_t mmio_flip_lock;
1571 bool display_irqs_enabled;
1573 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1574 struct pm_qos_request pm_qos;
1576 /* DPIO indirect register protection */
1577 struct mutex dpio_lock;
1579 /** Cached value of IMR to avoid reads in updating the bitfield */
1582 u32 de_irq_mask[I915_MAX_PIPES];
1587 u32 pipestat_irq_mask[I915_MAX_PIPES];
1589 struct work_struct hotplug_work;
1591 unsigned long hpd_last_jiffies;
1596 HPD_MARK_DISABLED = 2
1598 } hpd_stats[HPD_NUM_PINS];
1600 struct delayed_work hotplug_reenable_work;
1602 struct i915_fbc fbc;
1603 struct i915_drrs drrs;
1604 struct intel_opregion opregion;
1605 struct intel_vbt_data vbt;
1607 bool preserve_bios_swizzle;
1610 struct intel_overlay *overlay;
1612 /* backlight registers and fields in struct intel_panel */
1613 struct mutex backlight_lock;
1616 bool no_aux_handshake;
1618 /* protects panel power sequencer state */
1619 struct mutex pps_mutex;
1621 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1622 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1623 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1625 unsigned int fsb_freq, mem_freq, is_ddr3;
1626 unsigned int vlv_cdclk_freq;
1627 unsigned int hpll_freq;
1630 * wq - Driver workqueue for GEM.
1632 * NOTE: Work items scheduled here are not allowed to grab any modeset
1633 * locks, for otherwise the flushing done in the pageflip code will
1634 * result in deadlocks.
1636 struct workqueue_struct *wq;
1638 /* Display functions */
1639 struct drm_i915_display_funcs display;
1641 /* PCH chipset type */
1642 enum intel_pch pch_type;
1643 unsigned short pch_id;
1645 unsigned long quirks;
1647 enum modeset_restore modeset_restore;
1648 struct mutex modeset_restore_lock;
1650 struct list_head vm_list; /* Global list of all address spaces */
1651 struct i915_gtt gtt; /* VM representing the global address space */
1653 struct i915_gem_mm mm;
1654 DECLARE_HASHTABLE(mm_structs, 7);
1655 struct mutex mm_lock;
1657 /* Kernel Modesetting */
1659 struct sdvo_device_mapping sdvo_mappings[2];
1661 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1662 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1663 wait_queue_head_t pending_flip_queue;
1665 #ifdef CONFIG_DEBUG_FS
1666 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1669 int num_shared_dpll;
1670 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1671 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1673 struct i915_workarounds workarounds;
1675 /* Reclocking support */
1676 bool render_reclock_avail;
1677 bool lvds_downclock_avail;
1678 /* indicates the reduced downclock for LVDS*/
1681 struct i915_frontbuffer_tracking fb_tracking;
1685 bool mchbar_need_disable;
1687 struct intel_l3_parity l3_parity;
1689 /* Cannot be determined by PCIID. You must always read a register. */
1692 /* gen6+ rps state */
1693 struct intel_gen6_power_mgmt rps;
1695 /* ilk-only ips/rps state. Everything in here is protected by the global
1696 * mchdev_lock in intel_pm.c */
1697 struct intel_ilk_power_mgmt ips;
1699 struct i915_power_domains power_domains;
1701 struct i915_psr psr;
1703 struct i915_gpu_error gpu_error;
1705 struct drm_i915_gem_object *vlv_pctx;
1707 #ifdef CONFIG_DRM_I915_FBDEV
1708 /* list of fbdev register on this device */
1709 struct intel_fbdev *fbdev;
1710 struct work_struct fbdev_suspend_work;
1713 struct drm_property *broadcast_rgb_property;
1714 struct drm_property *force_audio_property;
1716 uint32_t hw_context_size;
1717 struct list_head context_list;
1722 struct i915_suspend_saved_registers regfile;
1723 struct vlv_s0ix_state vlv_s0ix_state;
1727 * Raw watermark latency values:
1728 * in 0.1us units for WM0,
1729 * in 0.5us units for WM1+.
1732 uint16_t pri_latency[5];
1734 uint16_t spr_latency[5];
1736 uint16_t cur_latency[5];
1738 * Raw watermark memory latency values
1739 * for SKL for all 8 levels
1742 uint16_t skl_latency[8];
1745 * The skl_wm_values structure is a bit too big for stack
1746 * allocation, so we keep the staging struct where we store
1747 * intermediate results here instead.
1749 struct skl_wm_values skl_results;
1751 /* current hardware state */
1753 struct ilk_wm_values hw;
1754 struct skl_wm_values skl_hw;
1758 struct i915_runtime_pm pm;
1760 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1761 u32 long_hpd_port_mask;
1762 u32 short_hpd_port_mask;
1763 struct work_struct dig_port_work;
1766 * if we get a HPD irq from DP and a HPD irq from non-DP
1767 * the non-DP HPD could block the workqueue on a mode config
1768 * mutex getting, that userspace may have taken. However
1769 * userspace is waiting on the DP workqueue to run which is
1770 * blocked behind the non-DP one.
1772 struct workqueue_struct *dp_wq;
1774 uint32_t bios_vgacntr;
1776 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1778 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
1779 struct intel_engine_cs *ring,
1780 struct intel_context *ctx,
1781 struct drm_i915_gem_execbuffer2 *args,
1782 struct list_head *vmas,
1783 struct drm_i915_gem_object *batch_obj,
1784 u64 exec_start, u32 flags);
1785 int (*init_rings)(struct drm_device *dev);
1786 void (*cleanup_ring)(struct intel_engine_cs *ring);
1787 void (*stop_ring)(struct intel_engine_cs *ring);
1791 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1792 * will be rejected. Instead look for a better place.
1796 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1798 return dev->dev_private;
1801 /* Iterate over initialised rings */
1802 #define for_each_ring(ring__, dev_priv__, i__) \
1803 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1804 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1806 enum hdmi_force_audio {
1807 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1808 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1809 HDMI_AUDIO_AUTO, /* trust EDID */
1810 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1813 #define I915_GTT_OFFSET_NONE ((u32)-1)
1815 struct drm_i915_gem_object_ops {
1816 /* Interface between the GEM object and its backing storage.
1817 * get_pages() is called once prior to the use of the associated set
1818 * of pages before to binding them into the GTT, and put_pages() is
1819 * called after we no longer need them. As we expect there to be
1820 * associated cost with migrating pages between the backing storage
1821 * and making them available for the GPU (e.g. clflush), we may hold
1822 * onto the pages after they are no longer referenced by the GPU
1823 * in case they may be used again shortly (for example migrating the
1824 * pages to a different memory domain within the GTT). put_pages()
1825 * will therefore most likely be called when the object itself is
1826 * being released or under memory pressure (where we attempt to
1827 * reap pages for the shrinker).
1829 int (*get_pages)(struct drm_i915_gem_object *);
1830 void (*put_pages)(struct drm_i915_gem_object *);
1831 int (*dmabuf_export)(struct drm_i915_gem_object *);
1832 void (*release)(struct drm_i915_gem_object *);
1836 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1837 * considered to be the frontbuffer for the given plane interface-vise. This
1838 * doesn't mean that the hw necessarily already scans it out, but that any
1839 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1841 * We have one bit per pipe and per scanout plane type.
1843 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1844 #define INTEL_FRONTBUFFER_BITS \
1845 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1846 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1847 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1848 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1849 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1850 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1851 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1852 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1853 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1854 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1855 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1857 struct drm_i915_gem_object {
1858 struct drm_gem_object base;
1860 const struct drm_i915_gem_object_ops *ops;
1862 /** List of VMAs backed by this object */
1863 struct list_head vma_list;
1865 /** Stolen memory for this object, instead of being backed by shmem. */
1866 struct drm_mm_node *stolen;
1867 struct list_head global_list;
1869 struct list_head ring_list;
1870 /** Used in execbuf to temporarily hold a ref */
1871 struct list_head obj_exec_link;
1874 * This is set if the object is on the active lists (has pending
1875 * rendering and so a non-zero seqno), and is not set if it i s on
1876 * inactive (ready to be unbound) list.
1878 unsigned int active:1;
1881 * This is set if the object has been written to since last bound
1884 unsigned int dirty:1;
1887 * Fence register bits (if any) for this object. Will be set
1888 * as needed when mapped into the GTT.
1889 * Protected by dev->struct_mutex.
1891 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1894 * Advice: are the backing pages purgeable?
1896 unsigned int madv:2;
1899 * Current tiling mode for the object.
1901 unsigned int tiling_mode:2;
1903 * Whether the tiling parameters for the currently associated fence
1904 * register have changed. Note that for the purposes of tracking
1905 * tiling changes we also treat the unfenced register, the register
1906 * slot that the object occupies whilst it executes a fenced
1907 * command (such as BLT on gen2/3), as a "fence".
1909 unsigned int fence_dirty:1;
1912 * Is the object at the current location in the gtt mappable and
1913 * fenceable? Used to avoid costly recalculations.
1915 unsigned int map_and_fenceable:1;
1918 * Whether the current gtt mapping needs to be mappable (and isn't just
1919 * mappable by accident). Track pin and fault separate for a more
1920 * accurate mappable working set.
1922 unsigned int fault_mappable:1;
1923 unsigned int pin_mappable:1;
1924 unsigned int pin_display:1;
1927 * Is the object to be mapped as read-only to the GPU
1928 * Only honoured if hardware has relevant pte bit
1930 unsigned long gt_ro:1;
1931 unsigned int cache_level:3;
1933 unsigned int has_dma_mapping:1;
1935 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1937 struct sg_table *pages;
1938 int pages_pin_count;
1940 /* prime dma-buf support */
1941 void *dma_buf_vmapping;
1944 struct intel_engine_cs *ring;
1946 /** Breadcrumb of last rendering to the buffer. */
1947 uint32_t last_read_seqno;
1948 uint32_t last_write_seqno;
1949 /** Breadcrumb of last fenced GPU access to the buffer. */
1950 uint32_t last_fenced_seqno;
1952 /** Current tiling stride for the object, if it's tiled. */
1955 /** References from framebuffers, locks out tiling changes. */
1956 unsigned long framebuffer_references;
1958 /** Record of address bit 17 of each page at last unbind. */
1959 unsigned long *bit_17;
1961 /** User space pin count and filp owning the pin */
1962 unsigned long user_pin_count;
1963 struct drm_file *pin_filp;
1966 /** for phy allocated objects */
1967 struct drm_dma_handle *phys_handle;
1969 struct i915_gem_userptr {
1971 unsigned read_only :1;
1972 unsigned workers :4;
1973 #define I915_GEM_USERPTR_MAX_WORKERS 15
1975 struct i915_mm_struct *mm;
1976 struct i915_mmu_object *mmu_object;
1977 struct work_struct *work;
1981 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1983 void i915_gem_track_fb(struct drm_i915_gem_object *old,
1984 struct drm_i915_gem_object *new,
1985 unsigned frontbuffer_bits);
1988 * Request queue structure.
1990 * The request queue allows us to note sequence numbers that have been emitted
1991 * and may be associated with active buffers to be retired.
1993 * By keeping this list, we can avoid having to do questionable
1994 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1995 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1997 struct drm_i915_gem_request {
1998 /** On Which ring this request was generated */
1999 struct intel_engine_cs *ring;
2001 /** GEM sequence number associated with this request. */
2004 /** Position in the ringbuffer of the start of the request */
2007 /** Position in the ringbuffer of the end of the request */
2010 /** Context related to this request */
2011 struct intel_context *ctx;
2013 /** Batch buffer related to this request if any */
2014 struct drm_i915_gem_object *batch_obj;
2016 /** Time at which this request was emitted, in jiffies. */
2017 unsigned long emitted_jiffies;
2019 /** global list entry for this request */
2020 struct list_head list;
2022 struct drm_i915_file_private *file_priv;
2023 /** file_priv list entry for this request */
2024 struct list_head client_list;
2027 struct drm_i915_file_private {
2028 struct drm_i915_private *dev_priv;
2029 struct drm_file *file;
2033 struct list_head request_list;
2034 struct delayed_work idle_work;
2036 struct idr context_idr;
2038 atomic_t rps_wait_boost;
2039 struct intel_engine_cs *bsd_ring;
2043 * A command that requires special handling by the command parser.
2045 struct drm_i915_cmd_descriptor {
2047 * Flags describing how the command parser processes the command.
2049 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2050 * a length mask if not set
2051 * CMD_DESC_SKIP: The command is allowed but does not follow the
2052 * standard length encoding for the opcode range in
2054 * CMD_DESC_REJECT: The command is never allowed
2055 * CMD_DESC_REGISTER: The command should be checked against the
2056 * register whitelist for the appropriate ring
2057 * CMD_DESC_MASTER: The command is allowed if the submitting process
2061 #define CMD_DESC_FIXED (1<<0)
2062 #define CMD_DESC_SKIP (1<<1)
2063 #define CMD_DESC_REJECT (1<<2)
2064 #define CMD_DESC_REGISTER (1<<3)
2065 #define CMD_DESC_BITMASK (1<<4)
2066 #define CMD_DESC_MASTER (1<<5)
2069 * The command's unique identification bits and the bitmask to get them.
2070 * This isn't strictly the opcode field as defined in the spec and may
2071 * also include type, subtype, and/or subop fields.
2079 * The command's length. The command is either fixed length (i.e. does
2080 * not include a length field) or has a length field mask. The flag
2081 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2082 * a length mask. All command entries in a command table must include
2083 * length information.
2091 * Describes where to find a register address in the command to check
2092 * against the ring's register whitelist. Only valid if flags has the
2093 * CMD_DESC_REGISTER bit set.
2100 #define MAX_CMD_DESC_BITMASKS 3
2102 * Describes command checks where a particular dword is masked and
2103 * compared against an expected value. If the command does not match
2104 * the expected value, the parser rejects it. Only valid if flags has
2105 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2108 * If the check specifies a non-zero condition_mask then the parser
2109 * only performs the check when the bits specified by condition_mask
2116 u32 condition_offset;
2118 } bits[MAX_CMD_DESC_BITMASKS];
2122 * A table of commands requiring special handling by the command parser.
2124 * Each ring has an array of tables. Each table consists of an array of command
2125 * descriptors, which must be sorted with command opcodes in ascending order.
2127 struct drm_i915_cmd_table {
2128 const struct drm_i915_cmd_descriptor *table;
2132 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2133 #define __I915__(p) ({ \
2134 struct drm_i915_private *__p; \
2135 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2136 __p = (struct drm_i915_private *)p; \
2137 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2138 __p = to_i915((struct drm_device *)p); \
2143 #define INTEL_INFO(p) (&__I915__(p)->info)
2144 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2146 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2147 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2148 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2149 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2150 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2151 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2152 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2153 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2154 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2155 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2156 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2157 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2158 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2159 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2160 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2161 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2162 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2163 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2164 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2165 INTEL_DEVID(dev) == 0x0152 || \
2166 INTEL_DEVID(dev) == 0x015a)
2167 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2168 INTEL_DEVID(dev) == 0x0106 || \
2169 INTEL_DEVID(dev) == 0x010A)
2170 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2171 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2172 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2173 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2174 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2175 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2176 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2177 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2178 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2179 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2180 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2181 (INTEL_DEVID(dev) & 0xf) == 0xe))
2182 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2183 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2184 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2185 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2186 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2187 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2188 /* ULX machines are also considered ULT. */
2189 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2190 INTEL_DEVID(dev) == 0x0A1E)
2191 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2194 * The genX designation typically refers to the render engine, so render
2195 * capability related checks should use IS_GEN, while display and other checks
2196 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2199 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2200 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2201 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2202 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2203 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2204 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2205 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2206 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2208 #define RENDER_RING (1<<RCS)
2209 #define BSD_RING (1<<VCS)
2210 #define BLT_RING (1<<BCS)
2211 #define VEBOX_RING (1<<VECS)
2212 #define BSD2_RING (1<<VCS2)
2213 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2214 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2215 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2216 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2217 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2218 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2219 __I915__(dev)->ellc_size)
2220 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2222 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2223 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2224 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2225 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2227 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2228 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2230 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2231 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2233 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2234 * even when in MSI mode. This results in spurious interrupt warnings if the
2235 * legacy irq no. is shared with another device. The kernel then disables that
2236 * interrupt source and so prevents the other device from working properly.
2238 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2239 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2241 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2242 * rows, which changed the alignment requirements and fence programming.
2244 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2246 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2247 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2248 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2249 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2250 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2252 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2253 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2254 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2256 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2258 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2259 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2260 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2261 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2262 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2263 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2264 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2266 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2267 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2268 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2269 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2270 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2271 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2272 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2273 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2275 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2276 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2277 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2278 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2279 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2280 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2281 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2283 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2285 /* DPF == dynamic parity feature */
2286 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2287 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2289 #define GT_FREQUENCY_MULTIPLIER 50
2291 #include "i915_trace.h"
2293 extern const struct drm_ioctl_desc i915_ioctls[];
2294 extern int i915_max_ioctl;
2296 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2297 extern int i915_resume_legacy(struct drm_device *dev);
2298 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2299 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2302 struct i915_params {
2304 int panel_ignore_lid;
2305 unsigned int powersave;
2307 unsigned int lvds_downclock;
2308 int lvds_channel_mode;
2310 int vbt_sdvo_panel_type;
2314 int enable_execlists;
2316 unsigned int preliminary_hw_support;
2317 int disable_power_well;
2319 int invert_brightness;
2320 int enable_cmd_parser;
2321 /* leave bools at the end to not create holes */
2322 bool enable_hangcheck;
2324 bool prefault_disable;
2326 bool disable_display;
2327 bool disable_vtd_wa;
2331 extern struct i915_params i915 __read_mostly;
2334 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2335 extern int i915_driver_unload(struct drm_device *);
2336 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2337 extern void i915_driver_lastclose(struct drm_device * dev);
2338 extern void i915_driver_preclose(struct drm_device *dev,
2339 struct drm_file *file);
2340 extern void i915_driver_postclose(struct drm_device *dev,
2341 struct drm_file *file);
2342 extern int i915_driver_device_is_agp(struct drm_device * dev);
2343 #ifdef CONFIG_COMPAT
2344 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2347 extern int intel_gpu_reset(struct drm_device *dev);
2348 extern int i915_reset(struct drm_device *dev);
2349 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2350 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2351 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2352 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2353 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2354 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2357 void i915_queue_hangcheck(struct drm_device *dev);
2359 void i915_handle_error(struct drm_device *dev, bool wedged,
2360 const char *fmt, ...);
2362 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2363 extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2364 int intel_irq_install(struct drm_i915_private *dev_priv);
2365 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2367 extern void intel_uncore_sanitize(struct drm_device *dev);
2368 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2369 bool restore_forcewake);
2370 extern void intel_uncore_init(struct drm_device *dev);
2371 extern void intel_uncore_check_errors(struct drm_device *dev);
2372 extern void intel_uncore_fini(struct drm_device *dev);
2373 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2376 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2380 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2383 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2384 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2386 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2388 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2389 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2390 uint32_t interrupt_mask,
2391 uint32_t enabled_irq_mask);
2392 #define ibx_enable_display_interrupt(dev_priv, bits) \
2393 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2394 #define ibx_disable_display_interrupt(dev_priv, bits) \
2395 ibx_display_interrupt_update((dev_priv), (bits), 0)
2398 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2399 struct drm_file *file_priv);
2400 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2401 struct drm_file *file_priv);
2402 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2403 struct drm_file *file_priv);
2404 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2405 struct drm_file *file_priv);
2406 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2407 struct drm_file *file_priv);
2408 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2409 struct drm_file *file_priv);
2410 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2411 struct drm_file *file_priv);
2412 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2413 struct intel_engine_cs *ring);
2414 void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2415 struct drm_file *file,
2416 struct intel_engine_cs *ring,
2417 struct drm_i915_gem_object *obj);
2418 int i915_gem_ringbuffer_submission(struct drm_device *dev,
2419 struct drm_file *file,
2420 struct intel_engine_cs *ring,
2421 struct intel_context *ctx,
2422 struct drm_i915_gem_execbuffer2 *args,
2423 struct list_head *vmas,
2424 struct drm_i915_gem_object *batch_obj,
2425 u64 exec_start, u32 flags);
2426 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2427 struct drm_file *file_priv);
2428 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2429 struct drm_file *file_priv);
2430 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2431 struct drm_file *file_priv);
2432 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2433 struct drm_file *file_priv);
2434 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2435 struct drm_file *file_priv);
2436 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2437 struct drm_file *file);
2438 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2439 struct drm_file *file);
2440 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2441 struct drm_file *file_priv);
2442 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2443 struct drm_file *file_priv);
2444 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2445 struct drm_file *file_priv);
2446 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2447 struct drm_file *file_priv);
2448 int i915_gem_init_userptr(struct drm_device *dev);
2449 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2450 struct drm_file *file);
2451 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2452 struct drm_file *file_priv);
2453 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2454 struct drm_file *file_priv);
2455 void i915_gem_load(struct drm_device *dev);
2456 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
2459 #define I915_SHRINK_PURGEABLE 0x1
2460 #define I915_SHRINK_UNBOUND 0x2
2461 #define I915_SHRINK_BOUND 0x4
2462 void *i915_gem_object_alloc(struct drm_device *dev);
2463 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2464 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2465 const struct drm_i915_gem_object_ops *ops);
2466 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2468 void i915_init_vm(struct drm_i915_private *dev_priv,
2469 struct i915_address_space *vm);
2470 void i915_gem_free_object(struct drm_gem_object *obj);
2471 void i915_gem_vma_destroy(struct i915_vma *vma);
2473 #define PIN_MAPPABLE 0x1
2474 #define PIN_NONBLOCK 0x2
2475 #define PIN_GLOBAL 0x4
2476 #define PIN_OFFSET_BIAS 0x8
2477 #define PIN_OFFSET_MASK (~4095)
2478 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2479 struct i915_address_space *vm,
2482 int __must_check i915_vma_unbind(struct i915_vma *vma);
2483 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2484 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2485 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2487 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2488 int *needs_clflush);
2490 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2491 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2493 struct sg_page_iter sg_iter;
2495 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2496 return sg_page_iter_page(&sg_iter);
2500 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2502 BUG_ON(obj->pages == NULL);
2503 obj->pages_pin_count++;
2505 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2507 BUG_ON(obj->pages_pin_count == 0);
2508 obj->pages_pin_count--;
2511 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2512 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2513 struct intel_engine_cs *to);
2514 void i915_vma_move_to_active(struct i915_vma *vma,
2515 struct intel_engine_cs *ring);
2516 int i915_gem_dumb_create(struct drm_file *file_priv,
2517 struct drm_device *dev,
2518 struct drm_mode_create_dumb *args);
2519 int i915_gem_dumb_map_offset(struct drm_file *file_priv,
2520 struct drm_device *dev, uint32_t handle,
2523 * Returns true if seq1 is later than seq2.
2526 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2528 return (int32_t)(seq1 - seq2) >= 0;
2531 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2532 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2533 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2534 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2536 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2537 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2539 struct drm_i915_gem_request *
2540 i915_gem_find_active_request(struct intel_engine_cs *ring);
2542 bool i915_gem_retire_requests(struct drm_device *dev);
2543 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2544 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2545 bool interruptible);
2546 int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno);
2548 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2550 return unlikely(atomic_read(&error->reset_counter)
2551 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2554 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2556 return atomic_read(&error->reset_counter) & I915_WEDGED;
2559 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2561 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2564 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2566 return dev_priv->gpu_error.stop_rings == 0 ||
2567 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2570 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2572 return dev_priv->gpu_error.stop_rings == 0 ||
2573 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2576 void i915_gem_reset(struct drm_device *dev);
2577 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2578 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2579 int __must_check i915_gem_init(struct drm_device *dev);
2580 int i915_gem_init_rings(struct drm_device *dev);
2581 int __must_check i915_gem_init_hw(struct drm_device *dev);
2582 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2583 void i915_gem_init_swizzling(struct drm_device *dev);
2584 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2585 int __must_check i915_gpu_idle(struct drm_device *dev);
2586 int __must_check i915_gem_suspend(struct drm_device *dev);
2587 int __i915_add_request(struct intel_engine_cs *ring,
2588 struct drm_file *file,
2589 struct drm_i915_gem_object *batch_obj,
2591 #define i915_add_request(ring, seqno) \
2592 __i915_add_request(ring, NULL, NULL, seqno)
2593 int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno,
2594 unsigned reset_counter,
2597 struct drm_i915_file_private *file_priv);
2598 int __must_check i915_wait_seqno(struct intel_engine_cs *ring,
2600 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2602 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2605 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2607 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2609 struct intel_engine_cs *pipelined);
2610 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2611 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2613 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2614 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2617 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2619 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2620 int tiling_mode, bool fenced);
2622 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2623 enum i915_cache_level cache_level);
2625 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2626 struct dma_buf *dma_buf);
2628 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2629 struct drm_gem_object *gem_obj, int flags);
2631 void i915_gem_restore_fences(struct drm_device *dev);
2633 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2634 struct i915_address_space *vm);
2635 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2636 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2637 struct i915_address_space *vm);
2638 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2639 struct i915_address_space *vm);
2640 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2641 struct i915_address_space *vm);
2643 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2644 struct i915_address_space *vm);
2646 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2647 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2648 struct i915_vma *vma;
2649 list_for_each_entry(vma, &obj->vma_list, vma_link)
2650 if (vma->pin_count > 0)
2655 /* Some GGTT VM helpers */
2656 #define i915_obj_to_ggtt(obj) \
2657 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2658 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2660 struct i915_address_space *ggtt =
2661 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2665 static inline struct i915_hw_ppgtt *
2666 i915_vm_to_ppgtt(struct i915_address_space *vm)
2668 WARN_ON(i915_is_ggtt(vm));
2670 return container_of(vm, struct i915_hw_ppgtt, base);
2674 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2676 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj));
2679 static inline unsigned long
2680 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2682 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj));
2685 static inline unsigned long
2686 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2688 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2691 static inline int __must_check
2692 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2696 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2697 alignment, flags | PIN_GLOBAL);
2701 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2703 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2706 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2708 /* i915_gem_context.c */
2709 int __must_check i915_gem_context_init(struct drm_device *dev);
2710 void i915_gem_context_fini(struct drm_device *dev);
2711 void i915_gem_context_reset(struct drm_device *dev);
2712 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2713 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2714 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2715 int i915_switch_context(struct intel_engine_cs *ring,
2716 struct intel_context *to);
2717 struct intel_context *
2718 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2719 void i915_gem_context_free(struct kref *ctx_ref);
2720 struct drm_i915_gem_object *
2721 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
2722 static inline void i915_gem_context_reference(struct intel_context *ctx)
2724 kref_get(&ctx->ref);
2727 static inline void i915_gem_context_unreference(struct intel_context *ctx)
2729 kref_put(&ctx->ref, i915_gem_context_free);
2732 static inline bool i915_gem_context_is_default(const struct intel_context *c)
2734 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
2737 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2738 struct drm_file *file);
2739 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2740 struct drm_file *file);
2742 /* i915_gem_evict.c */
2743 int __must_check i915_gem_evict_something(struct drm_device *dev,
2744 struct i915_address_space *vm,
2747 unsigned cache_level,
2748 unsigned long start,
2751 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2752 int i915_gem_evict_everything(struct drm_device *dev);
2754 /* belongs in i915_gem_gtt.h */
2755 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2757 if (INTEL_INFO(dev)->gen < 6)
2758 intel_gtt_chipset_flush();
2761 /* i915_gem_stolen.c */
2762 int i915_gem_init_stolen(struct drm_device *dev);
2763 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
2764 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2765 void i915_gem_cleanup_stolen(struct drm_device *dev);
2766 struct drm_i915_gem_object *
2767 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2768 struct drm_i915_gem_object *
2769 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2774 /* i915_gem_tiling.c */
2775 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2777 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2779 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2780 obj->tiling_mode != I915_TILING_NONE;
2783 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2784 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2785 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2787 /* i915_gem_debug.c */
2789 int i915_verify_lists(struct drm_device *dev);
2791 #define i915_verify_lists(dev) 0
2794 /* i915_debugfs.c */
2795 int i915_debugfs_init(struct drm_minor *minor);
2796 void i915_debugfs_cleanup(struct drm_minor *minor);
2797 #ifdef CONFIG_DEBUG_FS
2798 void intel_display_crc_init(struct drm_device *dev);
2800 static inline void intel_display_crc_init(struct drm_device *dev) {}
2803 /* i915_gpu_error.c */
2805 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2806 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2807 const struct i915_error_state_file_priv *error);
2808 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2809 struct drm_i915_private *i915,
2810 size_t count, loff_t pos);
2811 static inline void i915_error_state_buf_release(
2812 struct drm_i915_error_state_buf *eb)
2816 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2817 const char *error_msg);
2818 void i915_error_state_get(struct drm_device *dev,
2819 struct i915_error_state_file_priv *error_priv);
2820 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2821 void i915_destroy_error_state(struct drm_device *dev);
2823 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2824 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2826 /* i915_cmd_parser.c */
2827 int i915_cmd_parser_get_version(void);
2828 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
2829 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
2830 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
2831 int i915_parse_cmds(struct intel_engine_cs *ring,
2832 struct drm_i915_gem_object *batch_obj,
2833 u32 batch_start_offset,
2836 /* i915_suspend.c */
2837 extern int i915_save_state(struct drm_device *dev);
2838 extern int i915_restore_state(struct drm_device *dev);
2841 void i915_save_display_reg(struct drm_device *dev);
2842 void i915_restore_display_reg(struct drm_device *dev);
2845 void i915_setup_sysfs(struct drm_device *dev_priv);
2846 void i915_teardown_sysfs(struct drm_device *dev_priv);
2849 extern int intel_setup_gmbus(struct drm_device *dev);
2850 extern void intel_teardown_gmbus(struct drm_device *dev);
2851 static inline bool intel_gmbus_is_port_valid(unsigned port)
2853 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2856 extern struct i2c_adapter *intel_gmbus_get_adapter(
2857 struct drm_i915_private *dev_priv, unsigned port);
2858 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2859 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2860 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2862 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2864 extern void intel_i2c_reset(struct drm_device *dev);
2866 /* intel_opregion.c */
2868 extern int intel_opregion_setup(struct drm_device *dev);
2869 extern void intel_opregion_init(struct drm_device *dev);
2870 extern void intel_opregion_fini(struct drm_device *dev);
2871 extern void intel_opregion_asle_intr(struct drm_device *dev);
2872 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2874 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2877 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2878 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2879 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2880 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2882 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2887 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2895 extern void intel_register_dsm_handler(void);
2896 extern void intel_unregister_dsm_handler(void);
2898 static inline void intel_register_dsm_handler(void) { return; }
2899 static inline void intel_unregister_dsm_handler(void) { return; }
2900 #endif /* CONFIG_ACPI */
2903 extern void intel_modeset_init_hw(struct drm_device *dev);
2904 extern void intel_modeset_init(struct drm_device *dev);
2905 extern void intel_modeset_gem_init(struct drm_device *dev);
2906 extern void intel_modeset_cleanup(struct drm_device *dev);
2907 extern void intel_connector_unregister(struct intel_connector *);
2908 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2909 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2910 bool force_restore);
2911 extern void i915_redisable_vga(struct drm_device *dev);
2912 extern void i915_redisable_vga_power_on(struct drm_device *dev);
2913 extern bool intel_fbc_enabled(struct drm_device *dev);
2914 extern void bdw_fbc_sw_flush(struct drm_device *dev, u32 value);
2915 extern void intel_disable_fbc(struct drm_device *dev);
2916 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2917 extern void intel_init_pch_refclk(struct drm_device *dev);
2918 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2919 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2920 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
2922 extern void intel_detect_pch(struct drm_device *dev);
2923 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2924 extern int intel_enable_rc6(const struct drm_device *dev);
2926 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2927 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2928 struct drm_file *file);
2929 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2930 struct drm_file *file);
2932 void intel_notify_mmio_flip(struct intel_engine_cs *ring);
2935 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2936 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2937 struct intel_overlay_error_state *error);
2939 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2940 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2941 struct drm_device *dev,
2942 struct intel_display_error_state *error);
2944 /* On SNB platform, before reading ring registers forcewake bit
2945 * must be set to prevent GT core from power down and stale values being
2948 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2949 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2950 void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
2952 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
2953 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
2955 /* intel_sideband.c */
2956 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2957 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2958 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2959 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2960 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2961 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2962 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2963 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2964 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2965 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2966 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2967 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2968 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2969 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2970 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2971 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2972 enum intel_sbi_destination destination);
2973 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2974 enum intel_sbi_destination destination);
2975 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2976 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2978 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2979 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2981 #define FORCEWAKE_RENDER (1 << 0)
2982 #define FORCEWAKE_MEDIA (1 << 1)
2983 #define FORCEWAKE_BLITTER (1 << 2)
2984 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA | \
2988 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2989 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2991 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2992 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2993 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2994 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2996 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2997 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2998 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2999 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3001 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3002 * will be implemented using 2 32-bit writes in an arbitrary order with
3003 * an arbitrary delay between them. This can cause the hardware to
3004 * act upon the intermediate value, possibly leading to corruption and
3005 * machine death. You have been warned.
3007 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3008 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3010 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3011 u32 upper = I915_READ(upper_reg); \
3012 u32 lower = I915_READ(lower_reg); \
3013 u32 tmp = I915_READ(upper_reg); \
3014 if (upper != tmp) { \
3016 lower = I915_READ(lower_reg); \
3017 WARN_ON(I915_READ(upper_reg) != upper); \
3019 (u64)upper << 32 | lower; })
3021 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3022 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3024 /* "Broadcast RGB" property */
3025 #define INTEL_BROADCAST_RGB_AUTO 0
3026 #define INTEL_BROADCAST_RGB_FULL 1
3027 #define INTEL_BROADCAST_RGB_LIMITED 2
3029 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3031 if (IS_VALLEYVIEW(dev))
3032 return VLV_VGACNTRL;
3033 else if (INTEL_INFO(dev)->gen >= 5)
3034 return CPU_VGACNTRL;
3039 static inline void __user *to_user_ptr(u64 address)
3041 return (void __user *)(uintptr_t)address;
3044 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3046 unsigned long j = msecs_to_jiffies(m);
3048 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3051 static inline unsigned long
3052 timespec_to_jiffies_timeout(const struct timespec *value)
3054 unsigned long j = timespec_to_jiffies(value);
3056 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3060 * If you need to wait X milliseconds between events A and B, but event B
3061 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3062 * when event A happened, then just before event B you call this function and
3063 * pass the timestamp as the first argument, and X as the second argument.
3066 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3068 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3071 * Don't re-read the value of "jiffies" every time since it may change
3072 * behind our back and break the math.
3074 tmp_jiffies = jiffies;
3075 target_jiffies = timestamp_jiffies +
3076 msecs_to_jiffies_timeout(to_wait_ms);
3078 if (time_after(target_jiffies, tmp_jiffies)) {
3079 remaining_jiffies = target_jiffies - tmp_jiffies;
3080 while (remaining_jiffies)
3082 schedule_timeout_uninterruptible(remaining_jiffies);