1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "intel_lrc.h"
39 #include "i915_gem_gtt.h"
40 #include "i915_gem_render_state.h"
41 #include <linux/io-mapping.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
44 #include <drm/intel-gtt.h>
45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
46 #include <drm/drm_gem.h>
47 #include <linux/backlight.h>
48 #include <linux/hashtable.h>
49 #include <linux/intel-iommu.h>
50 #include <linux/kref.h>
51 #include <linux/pm_qos.h>
53 /* General customization:
56 #define DRIVER_NAME "i915"
57 #define DRIVER_DESC "Intel Graphics"
58 #define DRIVER_DATE "20141107"
61 #define WARN_ON(x) WARN(x, "WARN_ON(" #x ")")
69 I915_MAX_PIPES = _PIPE_EDP
71 #define pipe_name(p) ((p) + 'A')
80 #define transcoder_name(t) ((t) + 'A')
83 * This is the maximum (across all platforms) number of planes (primary +
84 * sprites) that can be active at the same time on one pipe.
86 * This value doesn't count the cursor plane.
88 #define I915_MAX_PLANES 3
95 #define plane_name(p) ((p) + 'A')
97 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
107 #define port_name(p) ((p) + 'A')
109 #define I915_NUM_PHYS_VLV 2
121 enum intel_display_power_domain {
125 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
126 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
127 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
128 POWER_DOMAIN_TRANSCODER_A,
129 POWER_DOMAIN_TRANSCODER_B,
130 POWER_DOMAIN_TRANSCODER_C,
131 POWER_DOMAIN_TRANSCODER_EDP,
132 POWER_DOMAIN_PORT_DDI_A_2_LANES,
133 POWER_DOMAIN_PORT_DDI_A_4_LANES,
134 POWER_DOMAIN_PORT_DDI_B_2_LANES,
135 POWER_DOMAIN_PORT_DDI_B_4_LANES,
136 POWER_DOMAIN_PORT_DDI_C_2_LANES,
137 POWER_DOMAIN_PORT_DDI_C_4_LANES,
138 POWER_DOMAIN_PORT_DDI_D_2_LANES,
139 POWER_DOMAIN_PORT_DDI_D_4_LANES,
140 POWER_DOMAIN_PORT_DSI,
141 POWER_DOMAIN_PORT_CRT,
142 POWER_DOMAIN_PORT_OTHER,
151 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
152 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
153 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
154 #define POWER_DOMAIN_TRANSCODER(tran) \
155 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
156 (tran) + POWER_DOMAIN_TRANSCODER_A)
160 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
161 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
171 #define I915_GEM_GPU_DOMAINS \
172 (I915_GEM_DOMAIN_RENDER | \
173 I915_GEM_DOMAIN_SAMPLER | \
174 I915_GEM_DOMAIN_COMMAND | \
175 I915_GEM_DOMAIN_INSTRUCTION | \
176 I915_GEM_DOMAIN_VERTEX)
178 #define for_each_pipe(__dev_priv, __p) \
179 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
180 #define for_each_plane(pipe, p) \
181 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
182 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
184 #define for_each_crtc(dev, crtc) \
185 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
187 #define for_each_intel_crtc(dev, intel_crtc) \
188 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
190 #define for_each_intel_encoder(dev, intel_encoder) \
191 list_for_each_entry(intel_encoder, \
192 &(dev)->mode_config.encoder_list, \
195 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
196 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
197 if ((intel_encoder)->base.crtc == (__crtc))
199 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
200 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
201 if ((intel_connector)->base.encoder == (__encoder))
203 #define for_each_power_domain(domain, mask) \
204 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
205 if ((1 << (domain)) & (mask))
207 struct drm_i915_private;
208 struct i915_mm_struct;
209 struct i915_mmu_object;
212 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
213 /* real shared dpll ids must be >= 0 */
214 DPLL_ID_PCH_PLL_A = 0,
215 DPLL_ID_PCH_PLL_B = 1,
220 DPLL_ID_SKL_DPLL1 = 0,
221 DPLL_ID_SKL_DPLL2 = 1,
222 DPLL_ID_SKL_DPLL3 = 2,
224 #define I915_NUM_PLLS 3
226 struct intel_dpll_hw_state {
238 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
239 * lower part of crtl1 and they get shifted into position when writing
240 * the register. This allows us to easily compare the state to share
244 /* HDMI only, 0 when used for DP */
245 uint32_t cfgcr1, cfgcr2;
248 struct intel_shared_dpll_config {
249 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
250 struct intel_dpll_hw_state hw_state;
253 struct intel_shared_dpll {
254 struct intel_shared_dpll_config config;
255 struct intel_shared_dpll_config *new_config;
257 int active; /* count of number of active CRTCs (i.e. DPMS on) */
258 bool on; /* is the PLL actually active? Disabled during modeset */
260 /* should match the index in the dev_priv->shared_dplls array */
261 enum intel_dpll_id id;
262 /* The mode_set hook is optional and should be used together with the
263 * intel_prepare_shared_dpll function. */
264 void (*mode_set)(struct drm_i915_private *dev_priv,
265 struct intel_shared_dpll *pll);
266 void (*enable)(struct drm_i915_private *dev_priv,
267 struct intel_shared_dpll *pll);
268 void (*disable)(struct drm_i915_private *dev_priv,
269 struct intel_shared_dpll *pll);
270 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
271 struct intel_shared_dpll *pll,
272 struct intel_dpll_hw_state *hw_state);
280 /* Used by dp and fdi links */
281 struct intel_link_m_n {
289 void intel_link_compute_m_n(int bpp, int nlanes,
290 int pixel_clock, int link_clock,
291 struct intel_link_m_n *m_n);
293 /* Interface history:
296 * 1.2: Add Power Management
297 * 1.3: Add vblank support
298 * 1.4: Fix cmdbuffer path, add heap destroy
299 * 1.5: Add vblank pipe configuration
300 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
301 * - Support vertical blank on secondary display pipe
303 #define DRIVER_MAJOR 1
304 #define DRIVER_MINOR 6
305 #define DRIVER_PATCHLEVEL 0
307 #define WATCH_LISTS 0
309 struct opregion_header;
310 struct opregion_acpi;
311 struct opregion_swsci;
312 struct opregion_asle;
314 struct intel_opregion {
315 struct opregion_header __iomem *header;
316 struct opregion_acpi __iomem *acpi;
317 struct opregion_swsci __iomem *swsci;
318 u32 swsci_gbda_sub_functions;
319 u32 swsci_sbcb_sub_functions;
320 struct opregion_asle __iomem *asle;
322 u32 __iomem *lid_state;
323 struct work_struct asle_work;
325 #define OPREGION_SIZE (8*1024)
327 struct intel_overlay;
328 struct intel_overlay_error_state;
330 struct drm_local_map;
332 struct drm_i915_master_private {
333 struct drm_local_map *sarea;
334 struct _drm_i915_sarea *sarea_priv;
336 #define I915_FENCE_REG_NONE -1
337 #define I915_MAX_NUM_FENCES 32
338 /* 32 fences + sign bit for FENCE_REG_NONE */
339 #define I915_MAX_NUM_FENCE_BITS 6
341 struct drm_i915_fence_reg {
342 struct list_head lru_list;
343 struct drm_i915_gem_object *obj;
347 struct sdvo_device_mapping {
356 struct intel_display_error_state;
358 struct drm_i915_error_state {
366 /* Generic register state */
374 u32 error; /* gen6+ */
375 u32 err_int; /* gen7 */
381 u32 extra_instdone[I915_NUM_INSTDONE_REG];
382 u64 fence[I915_MAX_NUM_FENCES];
383 struct intel_overlay_error_state *overlay;
384 struct intel_display_error_state *display;
385 struct drm_i915_error_object *semaphore_obj;
387 struct drm_i915_error_ring {
389 /* Software tracked state */
392 enum intel_ring_hangcheck_action hangcheck_action;
395 /* our own tracking of ring head and tail */
399 u32 semaphore_seqno[I915_NUM_RINGS - 1];
417 u32 rc_psmi; /* sleep state */
418 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
420 struct drm_i915_error_object {
424 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
426 struct drm_i915_error_request {
441 char comm[TASK_COMM_LEN];
442 } ring[I915_NUM_RINGS];
444 struct drm_i915_error_buffer {
451 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
459 } **active_bo, **pinned_bo;
461 u32 *active_bo_count, *pinned_bo_count;
465 struct intel_connector;
466 struct intel_encoder;
467 struct intel_crtc_config;
468 struct intel_plane_config;
473 struct drm_i915_display_funcs {
474 bool (*fbc_enabled)(struct drm_device *dev);
475 void (*enable_fbc)(struct drm_crtc *crtc);
476 void (*disable_fbc)(struct drm_device *dev);
477 int (*get_display_clock_speed)(struct drm_device *dev);
478 int (*get_fifo_size)(struct drm_device *dev, int plane);
480 * find_dpll() - Find the best values for the PLL
481 * @limit: limits for the PLL
482 * @crtc: current CRTC
483 * @target: target frequency in kHz
484 * @refclk: reference clock frequency in kHz
485 * @match_clock: if provided, @best_clock P divider must
486 * match the P divider from @match_clock
487 * used for LVDS downclocking
488 * @best_clock: best PLL values found
490 * Returns true on success, false on failure.
492 bool (*find_dpll)(const struct intel_limit *limit,
493 struct intel_crtc *crtc,
494 int target, int refclk,
495 struct dpll *match_clock,
496 struct dpll *best_clock);
497 void (*update_wm)(struct drm_crtc *crtc);
498 void (*update_sprite_wm)(struct drm_plane *plane,
499 struct drm_crtc *crtc,
500 uint32_t sprite_width, uint32_t sprite_height,
501 int pixel_size, bool enable, bool scaled);
502 void (*modeset_global_resources)(struct drm_device *dev);
503 /* Returns the active state of the crtc, and if the crtc is active,
504 * fills out the pipe-config with the hw state. */
505 bool (*get_pipe_config)(struct intel_crtc *,
506 struct intel_crtc_config *);
507 void (*get_plane_config)(struct intel_crtc *,
508 struct intel_plane_config *);
509 int (*crtc_compute_clock)(struct intel_crtc *crtc);
510 void (*crtc_enable)(struct drm_crtc *crtc);
511 void (*crtc_disable)(struct drm_crtc *crtc);
512 void (*off)(struct drm_crtc *crtc);
513 void (*audio_codec_enable)(struct drm_connector *connector,
514 struct intel_encoder *encoder,
515 struct drm_display_mode *mode);
516 void (*audio_codec_disable)(struct intel_encoder *encoder);
517 void (*fdi_link_train)(struct drm_crtc *crtc);
518 void (*init_clock_gating)(struct drm_device *dev);
519 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
520 struct drm_framebuffer *fb,
521 struct drm_i915_gem_object *obj,
522 struct intel_engine_cs *ring,
524 void (*update_primary_plane)(struct drm_crtc *crtc,
525 struct drm_framebuffer *fb,
527 void (*hpd_irq_setup)(struct drm_device *dev);
528 /* clock updates for mode set */
530 /* render clock increase/decrease */
531 /* display clock increase/decrease */
532 /* pll clock increase/decrease */
534 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
535 uint32_t (*get_backlight)(struct intel_connector *connector);
536 void (*set_backlight)(struct intel_connector *connector,
538 void (*disable_backlight)(struct intel_connector *connector);
539 void (*enable_backlight)(struct intel_connector *connector);
542 struct intel_uncore_funcs {
543 void (*force_wake_get)(struct drm_i915_private *dev_priv,
545 void (*force_wake_put)(struct drm_i915_private *dev_priv,
548 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
549 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
550 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
551 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
553 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
554 uint8_t val, bool trace);
555 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
556 uint16_t val, bool trace);
557 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
558 uint32_t val, bool trace);
559 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
560 uint64_t val, bool trace);
563 struct intel_uncore {
564 spinlock_t lock; /** lock is also taken in irq contexts. */
566 struct intel_uncore_funcs funcs;
569 unsigned forcewake_count;
571 unsigned fw_rendercount;
572 unsigned fw_mediacount;
573 unsigned fw_blittercount;
575 struct timer_list force_wake_timer;
578 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
579 func(is_mobile) sep \
582 func(is_i945gm) sep \
584 func(need_gfx_hws) sep \
586 func(is_pineview) sep \
587 func(is_broadwater) sep \
588 func(is_crestline) sep \
589 func(is_ivybridge) sep \
590 func(is_valleyview) sep \
591 func(is_haswell) sep \
592 func(is_skylake) sep \
593 func(is_preliminary) sep \
595 func(has_pipe_cxsr) sep \
596 func(has_hotplug) sep \
597 func(cursor_needs_physical) sep \
598 func(has_overlay) sep \
599 func(overlay_needs_physical) sep \
600 func(supports_tv) sep \
605 #define DEFINE_FLAG(name) u8 name:1
606 #define SEP_SEMICOLON ;
608 struct intel_device_info {
609 u32 display_mmio_offset;
612 u8 num_sprites[I915_MAX_PIPES];
614 u8 ring_mask; /* Rings supported by the HW */
615 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
616 /* Register offsets for the various display pipes and transcoders */
617 int pipe_offsets[I915_MAX_TRANSCODERS];
618 int trans_offsets[I915_MAX_TRANSCODERS];
619 int palette_offsets[I915_MAX_PIPES];
620 int cursor_offsets[I915_MAX_PIPES];
626 enum i915_cache_level {
628 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
629 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
630 caches, eg sampler/render caches, and the
631 large Last-Level-Cache. LLC is coherent with
632 the CPU, but L3 is only visible to the GPU. */
633 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
636 struct i915_ctx_hang_stats {
637 /* This context had batch pending when hang was declared */
638 unsigned batch_pending;
640 /* This context had batch active when hang was declared */
641 unsigned batch_active;
643 /* Time when this context was last blamed for a GPU reset */
644 unsigned long guilty_ts;
646 /* This context is banned to submit more work */
650 /* This must match up with the value previously used for execbuf2.rsvd1. */
651 #define DEFAULT_CONTEXT_HANDLE 0
653 * struct intel_context - as the name implies, represents a context.
654 * @ref: reference count.
655 * @user_handle: userspace tracking identity for this context.
656 * @remap_slice: l3 row remapping information.
657 * @file_priv: filp associated with this context (NULL for global default
659 * @hang_stats: information about the role of this context in possible GPU
661 * @vm: virtual memory space used by this context.
662 * @legacy_hw_ctx: render context backing object and whether it is correctly
663 * initialized (legacy ring submission mechanism only).
664 * @link: link in the global list of contexts.
666 * Contexts are memory images used by the hardware to store copies of their
669 struct intel_context {
673 struct drm_i915_file_private *file_priv;
674 struct i915_ctx_hang_stats hang_stats;
675 struct i915_hw_ppgtt *ppgtt;
677 /* Legacy ring buffer submission */
679 struct drm_i915_gem_object *rcs_state;
684 bool rcs_initialized;
686 struct drm_i915_gem_object *state;
687 struct intel_ringbuffer *ringbuf;
688 } engine[I915_NUM_RINGS];
690 struct list_head link;
700 struct drm_mm_node compressed_fb;
701 struct drm_mm_node *compressed_llb;
705 /* Tracks whether the HW is actually enabled, not whether the feature is
709 /* On gen8 some rings cannont perform fbc clean operation so for now
710 * we are doing this on SW with mmio.
711 * This variable works in the opposite information direction
712 * of ring->fbc_dirty telling software on frontbuffer tracking
713 * to perform the cache clean on sw side.
715 bool need_sw_cache_clean;
717 struct intel_fbc_work {
718 struct delayed_work work;
719 struct drm_crtc *crtc;
720 struct drm_framebuffer *fb;
724 FBC_OK, /* FBC is enabled */
725 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
726 FBC_NO_OUTPUT, /* no outputs enabled to compress */
727 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
728 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
729 FBC_MODE_TOO_LARGE, /* mode too large for compression */
730 FBC_BAD_PLANE, /* fbc not supported on plane */
731 FBC_NOT_TILED, /* buffer not tiled */
732 FBC_MULTIPLE_PIPES, /* more than one pipe active */
734 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
739 struct intel_connector *connector;
747 struct intel_dp *enabled;
749 struct delayed_work work;
750 unsigned busy_frontbuffer_bits;
754 PCH_NONE = 0, /* No PCH present */
755 PCH_IBX, /* Ibexpeak PCH */
756 PCH_CPT, /* Cougarpoint PCH */
757 PCH_LPT, /* Lynxpoint PCH */
758 PCH_SPT, /* Sunrisepoint PCH */
762 enum intel_sbi_destination {
767 #define QUIRK_PIPEA_FORCE (1<<0)
768 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
769 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
770 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
771 #define QUIRK_PIPEB_FORCE (1<<4)
774 struct intel_fbc_work;
777 struct i2c_adapter adapter;
781 struct i2c_algo_bit_data bit_algo;
782 struct drm_i915_private *dev_priv;
785 struct i915_suspend_saved_registers {
806 u32 saveTRANS_HTOTAL_A;
807 u32 saveTRANS_HBLANK_A;
808 u32 saveTRANS_HSYNC_A;
809 u32 saveTRANS_VTOTAL_A;
810 u32 saveTRANS_VBLANK_A;
811 u32 saveTRANS_VSYNC_A;
819 u32 savePFIT_PGM_RATIOS;
820 u32 saveBLC_HIST_CTL;
822 u32 saveBLC_PWM_CTL2;
823 u32 saveBLC_CPU_PWM_CTL;
824 u32 saveBLC_CPU_PWM_CTL2;
837 u32 saveTRANS_HTOTAL_B;
838 u32 saveTRANS_HBLANK_B;
839 u32 saveTRANS_HSYNC_B;
840 u32 saveTRANS_VTOTAL_B;
841 u32 saveTRANS_VBLANK_B;
842 u32 saveTRANS_VSYNC_B;
856 u32 savePP_ON_DELAYS;
857 u32 savePP_OFF_DELAYS;
865 u32 savePFIT_CONTROL;
866 u32 save_palette_a[256];
867 u32 save_palette_b[256];
878 u32 saveCACHE_MODE_0;
879 u32 saveMI_ARB_STATE;
890 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
901 u32 savePIPEA_GMCH_DATA_M;
902 u32 savePIPEB_GMCH_DATA_M;
903 u32 savePIPEA_GMCH_DATA_N;
904 u32 savePIPEB_GMCH_DATA_N;
905 u32 savePIPEA_DP_LINK_M;
906 u32 savePIPEB_DP_LINK_M;
907 u32 savePIPEA_DP_LINK_N;
908 u32 savePIPEB_DP_LINK_N;
919 u32 savePCH_DREF_CONTROL;
920 u32 saveDISP_ARB_CTL;
921 u32 savePIPEA_DATA_M1;
922 u32 savePIPEA_DATA_N1;
923 u32 savePIPEA_LINK_M1;
924 u32 savePIPEA_LINK_N1;
925 u32 savePIPEB_DATA_M1;
926 u32 savePIPEB_DATA_N1;
927 u32 savePIPEB_LINK_M1;
928 u32 savePIPEB_LINK_N1;
929 u32 saveMCHBAR_RENDER_STANDBY;
930 u32 savePCH_PORT_HOTPLUG;
933 struct vlv_s0ix_state {
940 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
941 u32 media_max_req_count;
942 u32 gfx_max_req_count;
974 /* Display 1 CZ domain */
979 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
981 /* GT SA CZ domain */
988 /* Display 2 CZ domain */
994 struct intel_rps_ei {
1000 struct intel_gen6_power_mgmt {
1001 /* work and pm_iir are protected by dev_priv->irq_lock */
1002 struct work_struct work;
1005 /* Frequencies are stored in potentially platform dependent multiples.
1006 * In other words, *_freq needs to be multiplied by X to be interesting.
1007 * Soft limits are those which are used for the dynamic reclocking done
1008 * by the driver (raise frequencies under heavy loads, and lower for
1009 * lighter loads). Hard limits are those imposed by the hardware.
1011 * A distinction is made for overclocking, which is never enabled by
1012 * default, and is considered to be above the hard limit if it's
1015 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1016 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1017 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1018 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1019 u8 min_freq; /* AKA RPn. Minimum frequency */
1020 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1021 u8 rp1_freq; /* "less than" RP0 power/freqency */
1022 u8 rp0_freq; /* Non-overclocked max frequency. */
1025 u32 ei_interrupt_count;
1028 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1031 struct delayed_work delayed_resume_work;
1033 /* manual wa residency calculations */
1034 struct intel_rps_ei up_ei, down_ei;
1037 * Protects RPS/RC6 register access and PCU communication.
1038 * Must be taken after struct_mutex if nested.
1040 struct mutex hw_lock;
1043 /* defined intel_pm.c */
1044 extern spinlock_t mchdev_lock;
1046 struct intel_ilk_power_mgmt {
1054 unsigned long last_time1;
1055 unsigned long chipset_power;
1058 unsigned long gfx_power;
1064 struct drm_i915_gem_object *pwrctx;
1065 struct drm_i915_gem_object *renderctx;
1068 struct drm_i915_private;
1069 struct i915_power_well;
1071 struct i915_power_well_ops {
1073 * Synchronize the well's hw state to match the current sw state, for
1074 * example enable/disable it based on the current refcount. Called
1075 * during driver init and resume time, possibly after first calling
1076 * the enable/disable handlers.
1078 void (*sync_hw)(struct drm_i915_private *dev_priv,
1079 struct i915_power_well *power_well);
1081 * Enable the well and resources that depend on it (for example
1082 * interrupts located on the well). Called after the 0->1 refcount
1085 void (*enable)(struct drm_i915_private *dev_priv,
1086 struct i915_power_well *power_well);
1088 * Disable the well and resources that depend on it. Called after
1089 * the 1->0 refcount transition.
1091 void (*disable)(struct drm_i915_private *dev_priv,
1092 struct i915_power_well *power_well);
1093 /* Returns the hw enabled state. */
1094 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1095 struct i915_power_well *power_well);
1098 /* Power well structure for haswell */
1099 struct i915_power_well {
1102 /* power well enable/disable usage count */
1104 /* cached hw enabled state */
1106 unsigned long domains;
1108 const struct i915_power_well_ops *ops;
1111 struct i915_power_domains {
1113 * Power wells needed for initialization at driver init and suspend
1114 * time are on. They are kept on until after the first modeset.
1118 int power_well_count;
1121 int domain_use_count[POWER_DOMAIN_NUM];
1122 struct i915_power_well *power_wells;
1125 struct i915_dri1_state {
1126 unsigned allow_batchbuffer : 1;
1127 u32 __iomem *gfx_hws_cpu_addr;
1138 struct i915_ums_state {
1140 * Flag if the X Server, and thus DRM, is not currently in
1141 * control of the device.
1143 * This is set between LeaveVT and EnterVT. It needs to be
1144 * replaced with a semaphore. It also needs to be
1145 * transitioned away from for kernel modesetting.
1150 #define MAX_L3_SLICES 2
1151 struct intel_l3_parity {
1152 u32 *remap_info[MAX_L3_SLICES];
1153 struct work_struct error_work;
1157 struct i915_gem_mm {
1158 /** Memory allocator for GTT stolen memory */
1159 struct drm_mm stolen;
1160 /** List of all objects in gtt_space. Used to restore gtt
1161 * mappings on resume */
1162 struct list_head bound_list;
1164 * List of objects which are not bound to the GTT (thus
1165 * are idle and not used by the GPU) but still have
1166 * (presumably uncached) pages still attached.
1168 struct list_head unbound_list;
1170 /** Usable portion of the GTT for GEM */
1171 unsigned long stolen_base; /* limited to low memory (32-bit) */
1173 /** PPGTT used for aliasing the PPGTT with the GTT */
1174 struct i915_hw_ppgtt *aliasing_ppgtt;
1176 struct notifier_block oom_notifier;
1177 struct shrinker shrinker;
1178 bool shrinker_no_lock_stealing;
1180 /** LRU list of objects with fence regs on them. */
1181 struct list_head fence_list;
1184 * We leave the user IRQ off as much as possible,
1185 * but this means that requests will finish and never
1186 * be retired once the system goes idle. Set a timer to
1187 * fire periodically while the ring is running. When it
1188 * fires, go retire requests.
1190 struct delayed_work retire_work;
1193 * When we detect an idle GPU, we want to turn on
1194 * powersaving features. So once we see that there
1195 * are no more requests outstanding and no more
1196 * arrive within a small period of time, we fire
1197 * off the idle_work.
1199 struct delayed_work idle_work;
1202 * Are we in a non-interruptible section of code like
1208 * Is the GPU currently considered idle, or busy executing userspace
1209 * requests? Whilst idle, we attempt to power down the hardware and
1210 * display clocks. In order to reduce the effect on performance, there
1211 * is a slight delay before we do so.
1215 /* the indicator for dispatch video commands on two BSD rings */
1216 int bsd_ring_dispatch_index;
1218 /** Bit 6 swizzling required for X tiling */
1219 uint32_t bit_6_swizzle_x;
1220 /** Bit 6 swizzling required for Y tiling */
1221 uint32_t bit_6_swizzle_y;
1223 /* accounting, useful for userland debugging */
1224 spinlock_t object_stat_lock;
1225 size_t object_memory;
1229 struct drm_i915_error_state_buf {
1230 struct drm_i915_private *i915;
1239 struct i915_error_state_file_priv {
1240 struct drm_device *dev;
1241 struct drm_i915_error_state *error;
1244 struct i915_gpu_error {
1245 /* For hangcheck timer */
1246 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1247 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1248 /* Hang gpu twice in this window and your context gets banned */
1249 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1251 struct timer_list hangcheck_timer;
1253 /* For reset and error_state handling. */
1255 /* Protected by the above dev->gpu_error.lock. */
1256 struct drm_i915_error_state *first_error;
1257 struct work_struct work;
1260 unsigned long missed_irq_rings;
1263 * State variable controlling the reset flow and count
1265 * This is a counter which gets incremented when reset is triggered,
1266 * and again when reset has been handled. So odd values (lowest bit set)
1267 * means that reset is in progress and even values that
1268 * (reset_counter >> 1):th reset was successfully completed.
1270 * If reset is not completed succesfully, the I915_WEDGE bit is
1271 * set meaning that hardware is terminally sour and there is no
1272 * recovery. All waiters on the reset_queue will be woken when
1275 * This counter is used by the wait_seqno code to notice that reset
1276 * event happened and it needs to restart the entire ioctl (since most
1277 * likely the seqno it waited for won't ever signal anytime soon).
1279 * This is important for lock-free wait paths, where no contended lock
1280 * naturally enforces the correct ordering between the bail-out of the
1281 * waiter and the gpu reset work code.
1283 atomic_t reset_counter;
1285 #define I915_RESET_IN_PROGRESS_FLAG 1
1286 #define I915_WEDGED (1 << 31)
1289 * Waitqueue to signal when the reset has completed. Used by clients
1290 * that wait for dev_priv->mm.wedged to settle.
1292 wait_queue_head_t reset_queue;
1294 /* Userspace knobs for gpu hang simulation;
1295 * combines both a ring mask, and extra flags
1298 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1299 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1301 /* For missed irq/seqno simulation. */
1302 unsigned int test_irq_rings;
1304 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1305 bool reload_in_reset;
1308 enum modeset_restore {
1309 MODESET_ON_LID_OPEN,
1314 struct ddi_vbt_port_info {
1316 * This is an index in the HDMI/DVI DDI buffer translation table.
1317 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1318 * populate this field.
1320 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1321 uint8_t hdmi_level_shift;
1323 uint8_t supports_dvi:1;
1324 uint8_t supports_hdmi:1;
1325 uint8_t supports_dp:1;
1328 enum drrs_support_type {
1329 DRRS_NOT_SUPPORTED = 0,
1330 STATIC_DRRS_SUPPORT = 1,
1331 SEAMLESS_DRRS_SUPPORT = 2
1334 struct intel_vbt_data {
1335 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1336 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1339 unsigned int int_tv_support:1;
1340 unsigned int lvds_dither:1;
1341 unsigned int lvds_vbt:1;
1342 unsigned int int_crt_support:1;
1343 unsigned int lvds_use_ssc:1;
1344 unsigned int display_clock_mode:1;
1345 unsigned int fdi_rx_polarity_inverted:1;
1346 unsigned int has_mipi:1;
1348 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1350 enum drrs_support_type drrs_type;
1355 int edp_preemphasis;
1357 bool edp_initialized;
1360 struct edp_power_seq edp_pps;
1365 bool active_low_pwm;
1366 u8 min_brightness; /* min_brightness/255 of max */
1373 struct mipi_config *config;
1374 struct mipi_pps_data *pps;
1378 u8 *sequence[MIPI_SEQ_MAX];
1384 union child_device_config *child_dev;
1386 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1389 enum intel_ddb_partitioning {
1391 INTEL_DDB_PART_5_6, /* IVB+ */
1394 struct intel_wm_level {
1402 struct ilk_wm_values {
1403 uint32_t wm_pipe[3];
1405 uint32_t wm_lp_spr[3];
1406 uint32_t wm_linetime[3];
1408 enum intel_ddb_partitioning partitioning;
1411 struct skl_ddb_entry {
1412 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1415 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1417 return entry->end - entry->start;
1420 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1421 const struct skl_ddb_entry *e2)
1423 if (e1->start == e2->start && e1->end == e2->end)
1429 struct skl_ddb_allocation {
1430 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1431 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1432 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1435 struct skl_wm_values {
1436 bool dirty[I915_MAX_PIPES];
1437 struct skl_ddb_allocation ddb;
1438 uint32_t wm_linetime[I915_MAX_PIPES];
1439 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1440 uint32_t cursor[I915_MAX_PIPES][8];
1441 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1442 uint32_t cursor_trans[I915_MAX_PIPES];
1445 struct skl_wm_level {
1446 bool plane_en[I915_MAX_PLANES];
1448 uint16_t plane_res_b[I915_MAX_PLANES];
1449 uint8_t plane_res_l[I915_MAX_PLANES];
1450 uint16_t cursor_res_b;
1451 uint8_t cursor_res_l;
1455 * This struct helps tracking the state needed for runtime PM, which puts the
1456 * device in PCI D3 state. Notice that when this happens, nothing on the
1457 * graphics device works, even register access, so we don't get interrupts nor
1460 * Every piece of our code that needs to actually touch the hardware needs to
1461 * either call intel_runtime_pm_get or call intel_display_power_get with the
1462 * appropriate power domain.
1464 * Our driver uses the autosuspend delay feature, which means we'll only really
1465 * suspend if we stay with zero refcount for a certain amount of time. The
1466 * default value is currently very conservative (see intel_runtime_pm_enable), but
1467 * it can be changed with the standard runtime PM files from sysfs.
1469 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1470 * goes back to false exactly before we reenable the IRQs. We use this variable
1471 * to check if someone is trying to enable/disable IRQs while they're supposed
1472 * to be disabled. This shouldn't happen and we'll print some error messages in
1475 * For more, read the Documentation/power/runtime_pm.txt.
1477 struct i915_runtime_pm {
1482 enum intel_pipe_crc_source {
1483 INTEL_PIPE_CRC_SOURCE_NONE,
1484 INTEL_PIPE_CRC_SOURCE_PLANE1,
1485 INTEL_PIPE_CRC_SOURCE_PLANE2,
1486 INTEL_PIPE_CRC_SOURCE_PF,
1487 INTEL_PIPE_CRC_SOURCE_PIPE,
1488 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1489 INTEL_PIPE_CRC_SOURCE_TV,
1490 INTEL_PIPE_CRC_SOURCE_DP_B,
1491 INTEL_PIPE_CRC_SOURCE_DP_C,
1492 INTEL_PIPE_CRC_SOURCE_DP_D,
1493 INTEL_PIPE_CRC_SOURCE_AUTO,
1494 INTEL_PIPE_CRC_SOURCE_MAX,
1497 struct intel_pipe_crc_entry {
1502 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1503 struct intel_pipe_crc {
1505 bool opened; /* exclusive access to the result file */
1506 struct intel_pipe_crc_entry *entries;
1507 enum intel_pipe_crc_source source;
1509 wait_queue_head_t wq;
1512 struct i915_frontbuffer_tracking {
1516 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1523 struct i915_wa_reg {
1526 /* bitmask representing WA bits */
1530 #define I915_MAX_WA_REGS 16
1532 struct i915_workarounds {
1533 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1537 struct drm_i915_private {
1538 struct drm_device *dev;
1539 struct kmem_cache *slab;
1541 const struct intel_device_info info;
1543 int relative_constants_mode;
1547 struct intel_uncore uncore;
1549 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1552 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1553 * controller on different i2c buses. */
1554 struct mutex gmbus_mutex;
1557 * Base address of the gmbus and gpio block.
1559 uint32_t gpio_mmio_base;
1561 /* MMIO base address for MIPI regs */
1562 uint32_t mipi_mmio_base;
1564 wait_queue_head_t gmbus_wait_queue;
1566 struct pci_dev *bridge_dev;
1567 struct intel_engine_cs ring[I915_NUM_RINGS];
1568 struct drm_i915_gem_object *semaphore_obj;
1569 uint32_t last_seqno, next_seqno;
1571 struct drm_dma_handle *status_page_dmah;
1572 struct resource mch_res;
1574 /* protects the irq masks */
1575 spinlock_t irq_lock;
1577 /* protects the mmio flip data */
1578 spinlock_t mmio_flip_lock;
1580 bool display_irqs_enabled;
1582 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1583 struct pm_qos_request pm_qos;
1585 /* DPIO indirect register protection */
1586 struct mutex dpio_lock;
1588 /** Cached value of IMR to avoid reads in updating the bitfield */
1591 u32 de_irq_mask[I915_MAX_PIPES];
1596 u32 pipestat_irq_mask[I915_MAX_PIPES];
1598 struct work_struct hotplug_work;
1600 unsigned long hpd_last_jiffies;
1605 HPD_MARK_DISABLED = 2
1607 } hpd_stats[HPD_NUM_PINS];
1609 struct delayed_work hotplug_reenable_work;
1611 struct i915_fbc fbc;
1612 struct i915_drrs drrs;
1613 struct intel_opregion opregion;
1614 struct intel_vbt_data vbt;
1616 bool preserve_bios_swizzle;
1619 struct intel_overlay *overlay;
1621 /* backlight registers and fields in struct intel_panel */
1622 struct mutex backlight_lock;
1625 bool no_aux_handshake;
1627 /* protects panel power sequencer state */
1628 struct mutex pps_mutex;
1630 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1631 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1632 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1634 unsigned int fsb_freq, mem_freq, is_ddr3;
1635 unsigned int vlv_cdclk_freq;
1636 unsigned int hpll_freq;
1639 * wq - Driver workqueue for GEM.
1641 * NOTE: Work items scheduled here are not allowed to grab any modeset
1642 * locks, for otherwise the flushing done in the pageflip code will
1643 * result in deadlocks.
1645 struct workqueue_struct *wq;
1647 /* Display functions */
1648 struct drm_i915_display_funcs display;
1650 /* PCH chipset type */
1651 enum intel_pch pch_type;
1652 unsigned short pch_id;
1654 unsigned long quirks;
1656 enum modeset_restore modeset_restore;
1657 struct mutex modeset_restore_lock;
1659 struct list_head vm_list; /* Global list of all address spaces */
1660 struct i915_gtt gtt; /* VM representing the global address space */
1662 struct i915_gem_mm mm;
1663 DECLARE_HASHTABLE(mm_structs, 7);
1664 struct mutex mm_lock;
1666 /* Kernel Modesetting */
1668 struct sdvo_device_mapping sdvo_mappings[2];
1670 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1671 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1672 wait_queue_head_t pending_flip_queue;
1674 #ifdef CONFIG_DEBUG_FS
1675 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1678 int num_shared_dpll;
1679 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1680 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1682 struct i915_workarounds workarounds;
1684 /* Reclocking support */
1685 bool render_reclock_avail;
1686 bool lvds_downclock_avail;
1687 /* indicates the reduced downclock for LVDS*/
1690 struct i915_frontbuffer_tracking fb_tracking;
1694 bool mchbar_need_disable;
1696 struct intel_l3_parity l3_parity;
1698 /* Cannot be determined by PCIID. You must always read a register. */
1701 /* gen6+ rps state */
1702 struct intel_gen6_power_mgmt rps;
1704 /* ilk-only ips/rps state. Everything in here is protected by the global
1705 * mchdev_lock in intel_pm.c */
1706 struct intel_ilk_power_mgmt ips;
1708 struct i915_power_domains power_domains;
1710 struct i915_psr psr;
1712 struct i915_gpu_error gpu_error;
1714 struct drm_i915_gem_object *vlv_pctx;
1716 #ifdef CONFIG_DRM_I915_FBDEV
1717 /* list of fbdev register on this device */
1718 struct intel_fbdev *fbdev;
1719 struct work_struct fbdev_suspend_work;
1722 struct drm_property *broadcast_rgb_property;
1723 struct drm_property *force_audio_property;
1725 uint32_t hw_context_size;
1726 struct list_head context_list;
1731 struct i915_suspend_saved_registers regfile;
1732 struct vlv_s0ix_state vlv_s0ix_state;
1736 * Raw watermark latency values:
1737 * in 0.1us units for WM0,
1738 * in 0.5us units for WM1+.
1741 uint16_t pri_latency[5];
1743 uint16_t spr_latency[5];
1745 uint16_t cur_latency[5];
1747 * Raw watermark memory latency values
1748 * for SKL for all 8 levels
1751 uint16_t skl_latency[8];
1754 * The skl_wm_values structure is a bit too big for stack
1755 * allocation, so we keep the staging struct where we store
1756 * intermediate results here instead.
1758 struct skl_wm_values skl_results;
1760 /* current hardware state */
1762 struct ilk_wm_values hw;
1763 struct skl_wm_values skl_hw;
1767 struct i915_runtime_pm pm;
1769 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1770 u32 long_hpd_port_mask;
1771 u32 short_hpd_port_mask;
1772 struct work_struct dig_port_work;
1775 * if we get a HPD irq from DP and a HPD irq from non-DP
1776 * the non-DP HPD could block the workqueue on a mode config
1777 * mutex getting, that userspace may have taken. However
1778 * userspace is waiting on the DP workqueue to run which is
1779 * blocked behind the non-DP one.
1781 struct workqueue_struct *dp_wq;
1783 uint32_t bios_vgacntr;
1785 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1787 struct i915_dri1_state dri1;
1788 /* Old ums support infrastructure, same warning applies. */
1789 struct i915_ums_state ums;
1791 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1793 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
1794 struct intel_engine_cs *ring,
1795 struct intel_context *ctx,
1796 struct drm_i915_gem_execbuffer2 *args,
1797 struct list_head *vmas,
1798 struct drm_i915_gem_object *batch_obj,
1799 u64 exec_start, u32 flags);
1800 int (*init_rings)(struct drm_device *dev);
1801 void (*cleanup_ring)(struct intel_engine_cs *ring);
1802 void (*stop_ring)(struct intel_engine_cs *ring);
1806 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1807 * will be rejected. Instead look for a better place.
1811 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1813 return dev->dev_private;
1816 /* Iterate over initialised rings */
1817 #define for_each_ring(ring__, dev_priv__, i__) \
1818 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1819 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1821 enum hdmi_force_audio {
1822 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1823 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1824 HDMI_AUDIO_AUTO, /* trust EDID */
1825 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1828 #define I915_GTT_OFFSET_NONE ((u32)-1)
1830 struct drm_i915_gem_object_ops {
1831 /* Interface between the GEM object and its backing storage.
1832 * get_pages() is called once prior to the use of the associated set
1833 * of pages before to binding them into the GTT, and put_pages() is
1834 * called after we no longer need them. As we expect there to be
1835 * associated cost with migrating pages between the backing storage
1836 * and making them available for the GPU (e.g. clflush), we may hold
1837 * onto the pages after they are no longer referenced by the GPU
1838 * in case they may be used again shortly (for example migrating the
1839 * pages to a different memory domain within the GTT). put_pages()
1840 * will therefore most likely be called when the object itself is
1841 * being released or under memory pressure (where we attempt to
1842 * reap pages for the shrinker).
1844 int (*get_pages)(struct drm_i915_gem_object *);
1845 void (*put_pages)(struct drm_i915_gem_object *);
1846 int (*dmabuf_export)(struct drm_i915_gem_object *);
1847 void (*release)(struct drm_i915_gem_object *);
1851 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1852 * considered to be the frontbuffer for the given plane interface-vise. This
1853 * doesn't mean that the hw necessarily already scans it out, but that any
1854 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1856 * We have one bit per pipe and per scanout plane type.
1858 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1859 #define INTEL_FRONTBUFFER_BITS \
1860 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1861 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1862 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1863 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1864 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1865 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1866 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1867 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1868 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1869 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1870 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1872 struct drm_i915_gem_object {
1873 struct drm_gem_object base;
1875 const struct drm_i915_gem_object_ops *ops;
1877 /** List of VMAs backed by this object */
1878 struct list_head vma_list;
1880 /** Stolen memory for this object, instead of being backed by shmem. */
1881 struct drm_mm_node *stolen;
1882 struct list_head global_list;
1884 struct list_head ring_list;
1885 /** Used in execbuf to temporarily hold a ref */
1886 struct list_head obj_exec_link;
1889 * This is set if the object is on the active lists (has pending
1890 * rendering and so a non-zero seqno), and is not set if it i s on
1891 * inactive (ready to be unbound) list.
1893 unsigned int active:1;
1896 * This is set if the object has been written to since last bound
1899 unsigned int dirty:1;
1902 * Fence register bits (if any) for this object. Will be set
1903 * as needed when mapped into the GTT.
1904 * Protected by dev->struct_mutex.
1906 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1909 * Advice: are the backing pages purgeable?
1911 unsigned int madv:2;
1914 * Current tiling mode for the object.
1916 unsigned int tiling_mode:2;
1918 * Whether the tiling parameters for the currently associated fence
1919 * register have changed. Note that for the purposes of tracking
1920 * tiling changes we also treat the unfenced register, the register
1921 * slot that the object occupies whilst it executes a fenced
1922 * command (such as BLT on gen2/3), as a "fence".
1924 unsigned int fence_dirty:1;
1927 * Is the object at the current location in the gtt mappable and
1928 * fenceable? Used to avoid costly recalculations.
1930 unsigned int map_and_fenceable:1;
1933 * Whether the current gtt mapping needs to be mappable (and isn't just
1934 * mappable by accident). Track pin and fault separate for a more
1935 * accurate mappable working set.
1937 unsigned int fault_mappable:1;
1938 unsigned int pin_mappable:1;
1939 unsigned int pin_display:1;
1942 * Is the object to be mapped as read-only to the GPU
1943 * Only honoured if hardware has relevant pte bit
1945 unsigned long gt_ro:1;
1946 unsigned int cache_level:3;
1948 unsigned int has_dma_mapping:1;
1950 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1952 struct sg_table *pages;
1953 int pages_pin_count;
1955 /* prime dma-buf support */
1956 void *dma_buf_vmapping;
1959 struct intel_engine_cs *ring;
1961 /** Breadcrumb of last rendering to the buffer. */
1962 uint32_t last_read_seqno;
1963 uint32_t last_write_seqno;
1964 /** Breadcrumb of last fenced GPU access to the buffer. */
1965 uint32_t last_fenced_seqno;
1967 /** Current tiling stride for the object, if it's tiled. */
1970 /** References from framebuffers, locks out tiling changes. */
1971 unsigned long framebuffer_references;
1973 /** Record of address bit 17 of each page at last unbind. */
1974 unsigned long *bit_17;
1976 /** User space pin count and filp owning the pin */
1977 unsigned long user_pin_count;
1978 struct drm_file *pin_filp;
1981 /** for phy allocated objects */
1982 struct drm_dma_handle *phys_handle;
1984 struct i915_gem_userptr {
1986 unsigned read_only :1;
1987 unsigned workers :4;
1988 #define I915_GEM_USERPTR_MAX_WORKERS 15
1990 struct i915_mm_struct *mm;
1991 struct i915_mmu_object *mmu_object;
1992 struct work_struct *work;
1996 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1998 void i915_gem_track_fb(struct drm_i915_gem_object *old,
1999 struct drm_i915_gem_object *new,
2000 unsigned frontbuffer_bits);
2003 * Request queue structure.
2005 * The request queue allows us to note sequence numbers that have been emitted
2006 * and may be associated with active buffers to be retired.
2008 * By keeping this list, we can avoid having to do questionable
2009 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
2010 * an emission time with seqnos for tracking how far ahead of the GPU we are.
2012 struct drm_i915_gem_request {
2013 /** On Which ring this request was generated */
2014 struct intel_engine_cs *ring;
2016 /** GEM sequence number associated with this request. */
2019 /** Position in the ringbuffer of the start of the request */
2022 /** Position in the ringbuffer of the end of the request */
2025 /** Context related to this request */
2026 struct intel_context *ctx;
2028 /** Batch buffer related to this request if any */
2029 struct drm_i915_gem_object *batch_obj;
2031 /** Time at which this request was emitted, in jiffies. */
2032 unsigned long emitted_jiffies;
2034 /** global list entry for this request */
2035 struct list_head list;
2037 struct drm_i915_file_private *file_priv;
2038 /** file_priv list entry for this request */
2039 struct list_head client_list;
2042 struct drm_i915_file_private {
2043 struct drm_i915_private *dev_priv;
2044 struct drm_file *file;
2048 struct list_head request_list;
2049 struct delayed_work idle_work;
2051 struct idr context_idr;
2053 atomic_t rps_wait_boost;
2054 struct intel_engine_cs *bsd_ring;
2058 * A command that requires special handling by the command parser.
2060 struct drm_i915_cmd_descriptor {
2062 * Flags describing how the command parser processes the command.
2064 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2065 * a length mask if not set
2066 * CMD_DESC_SKIP: The command is allowed but does not follow the
2067 * standard length encoding for the opcode range in
2069 * CMD_DESC_REJECT: The command is never allowed
2070 * CMD_DESC_REGISTER: The command should be checked against the
2071 * register whitelist for the appropriate ring
2072 * CMD_DESC_MASTER: The command is allowed if the submitting process
2076 #define CMD_DESC_FIXED (1<<0)
2077 #define CMD_DESC_SKIP (1<<1)
2078 #define CMD_DESC_REJECT (1<<2)
2079 #define CMD_DESC_REGISTER (1<<3)
2080 #define CMD_DESC_BITMASK (1<<4)
2081 #define CMD_DESC_MASTER (1<<5)
2084 * The command's unique identification bits and the bitmask to get them.
2085 * This isn't strictly the opcode field as defined in the spec and may
2086 * also include type, subtype, and/or subop fields.
2094 * The command's length. The command is either fixed length (i.e. does
2095 * not include a length field) or has a length field mask. The flag
2096 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2097 * a length mask. All command entries in a command table must include
2098 * length information.
2106 * Describes where to find a register address in the command to check
2107 * against the ring's register whitelist. Only valid if flags has the
2108 * CMD_DESC_REGISTER bit set.
2115 #define MAX_CMD_DESC_BITMASKS 3
2117 * Describes command checks where a particular dword is masked and
2118 * compared against an expected value. If the command does not match
2119 * the expected value, the parser rejects it. Only valid if flags has
2120 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2123 * If the check specifies a non-zero condition_mask then the parser
2124 * only performs the check when the bits specified by condition_mask
2131 u32 condition_offset;
2133 } bits[MAX_CMD_DESC_BITMASKS];
2137 * A table of commands requiring special handling by the command parser.
2139 * Each ring has an array of tables. Each table consists of an array of command
2140 * descriptors, which must be sorted with command opcodes in ascending order.
2142 struct drm_i915_cmd_table {
2143 const struct drm_i915_cmd_descriptor *table;
2147 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2148 #define __I915__(p) ({ \
2149 struct drm_i915_private *__p; \
2150 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2151 __p = (struct drm_i915_private *)p; \
2152 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2153 __p = to_i915((struct drm_device *)p); \
2158 #define INTEL_INFO(p) (&__I915__(p)->info)
2159 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2161 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2162 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2163 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2164 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2165 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2166 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2167 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2168 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2169 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2170 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2171 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2172 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2173 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2174 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2175 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2176 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2177 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2178 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2179 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2180 INTEL_DEVID(dev) == 0x0152 || \
2181 INTEL_DEVID(dev) == 0x015a)
2182 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2183 INTEL_DEVID(dev) == 0x0106 || \
2184 INTEL_DEVID(dev) == 0x010A)
2185 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2186 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2187 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2188 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2189 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2190 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2191 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2192 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2193 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2194 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2195 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2196 (INTEL_DEVID(dev) & 0xf) == 0xe))
2197 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2198 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2199 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2200 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2201 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2202 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2203 /* ULX machines are also considered ULT. */
2204 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2205 INTEL_DEVID(dev) == 0x0A1E)
2206 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2209 * The genX designation typically refers to the render engine, so render
2210 * capability related checks should use IS_GEN, while display and other checks
2211 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2214 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2215 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2216 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2217 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2218 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2219 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2220 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2221 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2223 #define RENDER_RING (1<<RCS)
2224 #define BSD_RING (1<<VCS)
2225 #define BLT_RING (1<<BCS)
2226 #define VEBOX_RING (1<<VECS)
2227 #define BSD2_RING (1<<VCS2)
2228 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2229 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2230 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2231 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2232 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2233 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2234 __I915__(dev)->ellc_size)
2235 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2237 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2238 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2239 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2240 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2242 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2243 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2245 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2246 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2248 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2249 * even when in MSI mode. This results in spurious interrupt warnings if the
2250 * legacy irq no. is shared with another device. The kernel then disables that
2251 * interrupt source and so prevents the other device from working properly.
2253 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2254 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2256 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2257 * rows, which changed the alignment requirements and fence programming.
2259 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2261 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2262 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2263 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2264 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2265 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2267 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2268 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2269 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2271 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2273 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2274 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2275 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2276 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2277 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2278 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2279 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2281 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2282 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2283 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2284 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2285 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2286 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2287 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2288 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2290 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2291 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2292 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2293 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2294 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2295 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2296 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2298 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2300 /* DPF == dynamic parity feature */
2301 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2302 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2304 #define GT_FREQUENCY_MULTIPLIER 50
2306 #include "i915_trace.h"
2308 extern const struct drm_ioctl_desc i915_ioctls[];
2309 extern int i915_max_ioctl;
2311 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2312 extern int i915_resume_legacy(struct drm_device *dev);
2313 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2314 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2317 struct i915_params {
2319 int panel_ignore_lid;
2320 unsigned int powersave;
2322 unsigned int lvds_downclock;
2323 int lvds_channel_mode;
2325 int vbt_sdvo_panel_type;
2329 int enable_execlists;
2331 unsigned int preliminary_hw_support;
2332 int disable_power_well;
2334 int invert_brightness;
2335 int enable_cmd_parser;
2336 /* leave bools at the end to not create holes */
2337 bool enable_hangcheck;
2339 bool prefault_disable;
2341 bool disable_display;
2342 bool disable_vtd_wa;
2346 extern struct i915_params i915 __read_mostly;
2349 void i915_update_dri1_breadcrumb(struct drm_device *dev);
2350 extern void i915_kernel_lost_context(struct drm_device * dev);
2351 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2352 extern int i915_driver_unload(struct drm_device *);
2353 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2354 extern void i915_driver_lastclose(struct drm_device * dev);
2355 extern void i915_driver_preclose(struct drm_device *dev,
2356 struct drm_file *file);
2357 extern void i915_driver_postclose(struct drm_device *dev,
2358 struct drm_file *file);
2359 extern int i915_driver_device_is_agp(struct drm_device * dev);
2360 #ifdef CONFIG_COMPAT
2361 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2364 extern int i915_emit_box(struct drm_device *dev,
2365 struct drm_clip_rect *box,
2367 extern int intel_gpu_reset(struct drm_device *dev);
2368 extern int i915_reset(struct drm_device *dev);
2369 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2370 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2371 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2372 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2373 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2374 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2377 void i915_queue_hangcheck(struct drm_device *dev);
2379 void i915_handle_error(struct drm_device *dev, bool wedged,
2380 const char *fmt, ...);
2382 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2383 extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2384 int intel_irq_install(struct drm_i915_private *dev_priv);
2385 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2387 extern void intel_uncore_sanitize(struct drm_device *dev);
2388 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2389 bool restore_forcewake);
2390 extern void intel_uncore_init(struct drm_device *dev);
2391 extern void intel_uncore_check_errors(struct drm_device *dev);
2392 extern void intel_uncore_fini(struct drm_device *dev);
2393 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2396 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2400 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2403 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2404 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2406 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2408 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2409 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2410 uint32_t interrupt_mask,
2411 uint32_t enabled_irq_mask);
2412 #define ibx_enable_display_interrupt(dev_priv, bits) \
2413 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2414 #define ibx_disable_display_interrupt(dev_priv, bits) \
2415 ibx_display_interrupt_update((dev_priv), (bits), 0)
2418 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2419 struct drm_file *file_priv);
2420 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2421 struct drm_file *file_priv);
2422 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2423 struct drm_file *file_priv);
2424 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2425 struct drm_file *file_priv);
2426 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2427 struct drm_file *file_priv);
2428 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2429 struct drm_file *file_priv);
2430 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2431 struct drm_file *file_priv);
2432 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2433 struct drm_file *file_priv);
2434 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2435 struct intel_engine_cs *ring);
2436 void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2437 struct drm_file *file,
2438 struct intel_engine_cs *ring,
2439 struct drm_i915_gem_object *obj);
2440 int i915_gem_ringbuffer_submission(struct drm_device *dev,
2441 struct drm_file *file,
2442 struct intel_engine_cs *ring,
2443 struct intel_context *ctx,
2444 struct drm_i915_gem_execbuffer2 *args,
2445 struct list_head *vmas,
2446 struct drm_i915_gem_object *batch_obj,
2447 u64 exec_start, u32 flags);
2448 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2449 struct drm_file *file_priv);
2450 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2451 struct drm_file *file_priv);
2452 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2453 struct drm_file *file_priv);
2454 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2455 struct drm_file *file_priv);
2456 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2457 struct drm_file *file_priv);
2458 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2459 struct drm_file *file);
2460 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2461 struct drm_file *file);
2462 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2463 struct drm_file *file_priv);
2464 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2465 struct drm_file *file_priv);
2466 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2467 struct drm_file *file_priv);
2468 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2469 struct drm_file *file_priv);
2470 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2471 struct drm_file *file_priv);
2472 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2473 struct drm_file *file_priv);
2474 int i915_gem_init_userptr(struct drm_device *dev);
2475 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2476 struct drm_file *file);
2477 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2478 struct drm_file *file_priv);
2479 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2480 struct drm_file *file_priv);
2481 void i915_gem_load(struct drm_device *dev);
2482 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
2485 #define I915_SHRINK_PURGEABLE 0x1
2486 #define I915_SHRINK_UNBOUND 0x2
2487 #define I915_SHRINK_BOUND 0x4
2488 void *i915_gem_object_alloc(struct drm_device *dev);
2489 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2490 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2491 const struct drm_i915_gem_object_ops *ops);
2492 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2494 void i915_init_vm(struct drm_i915_private *dev_priv,
2495 struct i915_address_space *vm);
2496 void i915_gem_free_object(struct drm_gem_object *obj);
2497 void i915_gem_vma_destroy(struct i915_vma *vma);
2499 #define PIN_MAPPABLE 0x1
2500 #define PIN_NONBLOCK 0x2
2501 #define PIN_GLOBAL 0x4
2502 #define PIN_OFFSET_BIAS 0x8
2503 #define PIN_OFFSET_MASK (~4095)
2504 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2505 struct i915_address_space *vm,
2508 int __must_check i915_vma_unbind(struct i915_vma *vma);
2509 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2510 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2511 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2512 void i915_gem_lastclose(struct drm_device *dev);
2514 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2515 int *needs_clflush);
2517 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2518 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2520 struct sg_page_iter sg_iter;
2522 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2523 return sg_page_iter_page(&sg_iter);
2527 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2529 BUG_ON(obj->pages == NULL);
2530 obj->pages_pin_count++;
2532 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2534 BUG_ON(obj->pages_pin_count == 0);
2535 obj->pages_pin_count--;
2538 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2539 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2540 struct intel_engine_cs *to);
2541 void i915_vma_move_to_active(struct i915_vma *vma,
2542 struct intel_engine_cs *ring);
2543 int i915_gem_dumb_create(struct drm_file *file_priv,
2544 struct drm_device *dev,
2545 struct drm_mode_create_dumb *args);
2546 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2547 uint32_t handle, uint64_t *offset);
2549 * Returns true if seq1 is later than seq2.
2552 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2554 return (int32_t)(seq1 - seq2) >= 0;
2557 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2558 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2559 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2560 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2562 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2563 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2565 struct drm_i915_gem_request *
2566 i915_gem_find_active_request(struct intel_engine_cs *ring);
2568 bool i915_gem_retire_requests(struct drm_device *dev);
2569 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2570 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2571 bool interruptible);
2572 int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno);
2574 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2576 return unlikely(atomic_read(&error->reset_counter)
2577 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2580 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2582 return atomic_read(&error->reset_counter) & I915_WEDGED;
2585 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2587 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2590 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2592 return dev_priv->gpu_error.stop_rings == 0 ||
2593 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2596 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2598 return dev_priv->gpu_error.stop_rings == 0 ||
2599 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2602 void i915_gem_reset(struct drm_device *dev);
2603 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2604 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2605 int __must_check i915_gem_init(struct drm_device *dev);
2606 int i915_gem_init_rings(struct drm_device *dev);
2607 int __must_check i915_gem_init_hw(struct drm_device *dev);
2608 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2609 void i915_gem_init_swizzling(struct drm_device *dev);
2610 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2611 int __must_check i915_gpu_idle(struct drm_device *dev);
2612 int __must_check i915_gem_suspend(struct drm_device *dev);
2613 int __i915_add_request(struct intel_engine_cs *ring,
2614 struct drm_file *file,
2615 struct drm_i915_gem_object *batch_obj,
2617 #define i915_add_request(ring, seqno) \
2618 __i915_add_request(ring, NULL, NULL, seqno)
2619 int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno,
2620 unsigned reset_counter,
2623 struct drm_i915_file_private *file_priv);
2624 int __must_check i915_wait_seqno(struct intel_engine_cs *ring,
2626 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2628 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2631 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2633 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2635 struct intel_engine_cs *pipelined);
2636 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2637 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2639 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2640 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2643 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2645 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2646 int tiling_mode, bool fenced);
2648 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2649 enum i915_cache_level cache_level);
2651 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2652 struct dma_buf *dma_buf);
2654 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2655 struct drm_gem_object *gem_obj, int flags);
2657 void i915_gem_restore_fences(struct drm_device *dev);
2659 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2660 struct i915_address_space *vm);
2661 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2662 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2663 struct i915_address_space *vm);
2664 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2665 struct i915_address_space *vm);
2666 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2667 struct i915_address_space *vm);
2669 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2670 struct i915_address_space *vm);
2672 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2673 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2674 struct i915_vma *vma;
2675 list_for_each_entry(vma, &obj->vma_list, vma_link)
2676 if (vma->pin_count > 0)
2681 /* Some GGTT VM helpers */
2682 #define i915_obj_to_ggtt(obj) \
2683 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2684 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2686 struct i915_address_space *ggtt =
2687 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2691 static inline struct i915_hw_ppgtt *
2692 i915_vm_to_ppgtt(struct i915_address_space *vm)
2694 WARN_ON(i915_is_ggtt(vm));
2696 return container_of(vm, struct i915_hw_ppgtt, base);
2700 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2702 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj));
2705 static inline unsigned long
2706 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2708 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj));
2711 static inline unsigned long
2712 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2714 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2717 static inline int __must_check
2718 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2722 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2723 alignment, flags | PIN_GLOBAL);
2727 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2729 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2732 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2734 /* i915_gem_context.c */
2735 int __must_check i915_gem_context_init(struct drm_device *dev);
2736 void i915_gem_context_fini(struct drm_device *dev);
2737 void i915_gem_context_reset(struct drm_device *dev);
2738 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2739 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2740 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2741 int i915_switch_context(struct intel_engine_cs *ring,
2742 struct intel_context *to);
2743 struct intel_context *
2744 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2745 void i915_gem_context_free(struct kref *ctx_ref);
2746 struct drm_i915_gem_object *
2747 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
2748 static inline void i915_gem_context_reference(struct intel_context *ctx)
2750 kref_get(&ctx->ref);
2753 static inline void i915_gem_context_unreference(struct intel_context *ctx)
2755 kref_put(&ctx->ref, i915_gem_context_free);
2758 static inline bool i915_gem_context_is_default(const struct intel_context *c)
2760 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
2763 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2764 struct drm_file *file);
2765 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2766 struct drm_file *file);
2768 /* i915_gem_evict.c */
2769 int __must_check i915_gem_evict_something(struct drm_device *dev,
2770 struct i915_address_space *vm,
2773 unsigned cache_level,
2774 unsigned long start,
2777 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2778 int i915_gem_evict_everything(struct drm_device *dev);
2780 /* belongs in i915_gem_gtt.h */
2781 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2783 if (INTEL_INFO(dev)->gen < 6)
2784 intel_gtt_chipset_flush();
2787 /* i915_gem_stolen.c */
2788 int i915_gem_init_stolen(struct drm_device *dev);
2789 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
2790 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2791 void i915_gem_cleanup_stolen(struct drm_device *dev);
2792 struct drm_i915_gem_object *
2793 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2794 struct drm_i915_gem_object *
2795 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2800 /* i915_gem_tiling.c */
2801 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2803 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2805 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2806 obj->tiling_mode != I915_TILING_NONE;
2809 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2810 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2811 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2813 /* i915_gem_debug.c */
2815 int i915_verify_lists(struct drm_device *dev);
2817 #define i915_verify_lists(dev) 0
2820 /* i915_debugfs.c */
2821 int i915_debugfs_init(struct drm_minor *minor);
2822 void i915_debugfs_cleanup(struct drm_minor *minor);
2823 #ifdef CONFIG_DEBUG_FS
2824 void intel_display_crc_init(struct drm_device *dev);
2826 static inline void intel_display_crc_init(struct drm_device *dev) {}
2829 /* i915_gpu_error.c */
2831 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2832 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2833 const struct i915_error_state_file_priv *error);
2834 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2835 struct drm_i915_private *i915,
2836 size_t count, loff_t pos);
2837 static inline void i915_error_state_buf_release(
2838 struct drm_i915_error_state_buf *eb)
2842 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2843 const char *error_msg);
2844 void i915_error_state_get(struct drm_device *dev,
2845 struct i915_error_state_file_priv *error_priv);
2846 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2847 void i915_destroy_error_state(struct drm_device *dev);
2849 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2850 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2852 /* i915_cmd_parser.c */
2853 int i915_cmd_parser_get_version(void);
2854 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
2855 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
2856 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
2857 int i915_parse_cmds(struct intel_engine_cs *ring,
2858 struct drm_i915_gem_object *batch_obj,
2859 u32 batch_start_offset,
2862 /* i915_suspend.c */
2863 extern int i915_save_state(struct drm_device *dev);
2864 extern int i915_restore_state(struct drm_device *dev);
2867 void i915_save_display_reg(struct drm_device *dev);
2868 void i915_restore_display_reg(struct drm_device *dev);
2871 void i915_setup_sysfs(struct drm_device *dev_priv);
2872 void i915_teardown_sysfs(struct drm_device *dev_priv);
2875 extern int intel_setup_gmbus(struct drm_device *dev);
2876 extern void intel_teardown_gmbus(struct drm_device *dev);
2877 static inline bool intel_gmbus_is_port_valid(unsigned port)
2879 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2882 extern struct i2c_adapter *intel_gmbus_get_adapter(
2883 struct drm_i915_private *dev_priv, unsigned port);
2884 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2885 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2886 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2888 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2890 extern void intel_i2c_reset(struct drm_device *dev);
2892 /* intel_opregion.c */
2894 extern int intel_opregion_setup(struct drm_device *dev);
2895 extern void intel_opregion_init(struct drm_device *dev);
2896 extern void intel_opregion_fini(struct drm_device *dev);
2897 extern void intel_opregion_asle_intr(struct drm_device *dev);
2898 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2900 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2903 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2904 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2905 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2906 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2908 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2913 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2921 extern void intel_register_dsm_handler(void);
2922 extern void intel_unregister_dsm_handler(void);
2924 static inline void intel_register_dsm_handler(void) { return; }
2925 static inline void intel_unregister_dsm_handler(void) { return; }
2926 #endif /* CONFIG_ACPI */
2929 extern void intel_modeset_init_hw(struct drm_device *dev);
2930 extern void intel_modeset_init(struct drm_device *dev);
2931 extern void intel_modeset_gem_init(struct drm_device *dev);
2932 extern void intel_modeset_cleanup(struct drm_device *dev);
2933 extern void intel_connector_unregister(struct intel_connector *);
2934 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2935 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2936 bool force_restore);
2937 extern void i915_redisable_vga(struct drm_device *dev);
2938 extern void i915_redisable_vga_power_on(struct drm_device *dev);
2939 extern bool intel_fbc_enabled(struct drm_device *dev);
2940 extern void bdw_fbc_sw_flush(struct drm_device *dev, u32 value);
2941 extern void intel_disable_fbc(struct drm_device *dev);
2942 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2943 extern void intel_init_pch_refclk(struct drm_device *dev);
2944 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2945 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2946 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
2948 extern void intel_detect_pch(struct drm_device *dev);
2949 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2950 extern int intel_enable_rc6(const struct drm_device *dev);
2952 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2953 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2954 struct drm_file *file);
2955 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2956 struct drm_file *file);
2958 void intel_notify_mmio_flip(struct intel_engine_cs *ring);
2961 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2962 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2963 struct intel_overlay_error_state *error);
2965 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2966 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2967 struct drm_device *dev,
2968 struct intel_display_error_state *error);
2970 /* On SNB platform, before reading ring registers forcewake bit
2971 * must be set to prevent GT core from power down and stale values being
2974 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2975 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2976 void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
2978 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2979 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2981 /* intel_sideband.c */
2982 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2983 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2984 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2985 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2986 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2987 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2988 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2989 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2990 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2991 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2992 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2993 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2994 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2995 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2996 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2997 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2998 enum intel_sbi_destination destination);
2999 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3000 enum intel_sbi_destination destination);
3001 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3002 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3004 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
3005 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
3007 #define FORCEWAKE_RENDER (1 << 0)
3008 #define FORCEWAKE_MEDIA (1 << 1)
3009 #define FORCEWAKE_BLITTER (1 << 2)
3010 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA | \
3014 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3015 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3017 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3018 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3019 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3020 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3022 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3023 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3024 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3025 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3027 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3028 * will be implemented using 2 32-bit writes in an arbitrary order with
3029 * an arbitrary delay between them. This can cause the hardware to
3030 * act upon the intermediate value, possibly leading to corruption and
3031 * machine death. You have been warned.
3033 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3034 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3036 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3037 u32 upper = I915_READ(upper_reg); \
3038 u32 lower = I915_READ(lower_reg); \
3039 u32 tmp = I915_READ(upper_reg); \
3040 if (upper != tmp) { \
3042 lower = I915_READ(lower_reg); \
3043 WARN_ON(I915_READ(upper_reg) != upper); \
3045 (u64)upper << 32 | lower; })
3047 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3048 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3050 /* "Broadcast RGB" property */
3051 #define INTEL_BROADCAST_RGB_AUTO 0
3052 #define INTEL_BROADCAST_RGB_FULL 1
3053 #define INTEL_BROADCAST_RGB_LIMITED 2
3055 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3057 if (IS_VALLEYVIEW(dev))
3058 return VLV_VGACNTRL;
3059 else if (INTEL_INFO(dev)->gen >= 5)
3060 return CPU_VGACNTRL;
3065 static inline void __user *to_user_ptr(u64 address)
3067 return (void __user *)(uintptr_t)address;
3070 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3072 unsigned long j = msecs_to_jiffies(m);
3074 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3077 static inline unsigned long
3078 timespec_to_jiffies_timeout(const struct timespec *value)
3080 unsigned long j = timespec_to_jiffies(value);
3082 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3086 * If you need to wait X milliseconds between events A and B, but event B
3087 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3088 * when event A happened, then just before event B you call this function and
3089 * pass the timestamp as the first argument, and X as the second argument.
3092 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3094 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3097 * Don't re-read the value of "jiffies" every time since it may change
3098 * behind our back and break the math.
3100 tmp_jiffies = jiffies;
3101 target_jiffies = timestamp_jiffies +
3102 msecs_to_jiffies_timeout(to_wait_ms);
3104 if (time_after(target_jiffies, tmp_jiffies)) {
3105 remaining_jiffies = target_jiffies - tmp_jiffies;
3106 while (remaining_jiffies)
3108 schedule_timeout_uninterruptible(remaining_jiffies);