1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <drm/drm_auth.h>
52 #include "i915_params.h"
55 #include "intel_bios.h"
56 #include "intel_dpll_mgr.h"
57 #include "intel_guc.h"
58 #include "intel_lrc.h"
59 #include "intel_ringbuffer.h"
62 #include "i915_gem_gtt.h"
63 #include "i915_gem_render_state.h"
64 #include "i915_gem_request.h"
66 #include "intel_gvt.h"
68 /* General customization:
71 #define DRIVER_NAME "i915"
72 #define DRIVER_DESC "Intel Graphics"
73 #define DRIVER_DATE "20160919"
76 /* Many gcc seem to no see through this and fall over :( */
78 #define WARN_ON(x) ({ \
79 bool __i915_warn_cond = (x); \
80 if (__builtin_constant_p(__i915_warn_cond)) \
81 BUILD_BUG_ON(__i915_warn_cond); \
82 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
84 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
88 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
90 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
91 (long) (x), __func__);
93 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
94 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
95 * which may not necessarily be a user visible problem. This will either
96 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
97 * enable distros and users to tailor their preferred amount of i915 abrt
100 #define I915_STATE_WARN(condition, format...) ({ \
101 int __ret_warn_on = !!(condition); \
102 if (unlikely(__ret_warn_on)) \
103 if (!WARN(i915.verbose_state_checks, format)) \
105 unlikely(__ret_warn_on); \
108 #define I915_STATE_WARN_ON(x) \
109 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
111 bool __i915_inject_load_failure(const char *func, int line);
112 #define i915_inject_load_failure() \
113 __i915_inject_load_failure(__func__, __LINE__)
115 static inline const char *yesno(bool v)
117 return v ? "yes" : "no";
120 static inline const char *onoff(bool v)
122 return v ? "on" : "off";
131 I915_MAX_PIPES = _PIPE_EDP
133 #define pipe_name(p) ((p) + 'A')
145 static inline const char *transcoder_name(enum transcoder transcoder)
147 switch (transcoder) {
156 case TRANSCODER_DSI_A:
158 case TRANSCODER_DSI_C:
165 static inline bool transcoder_is_dsi(enum transcoder transcoder)
167 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
171 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
172 * number of planes per CRTC. Not all platforms really have this many planes,
173 * which means some arrays of size I915_MAX_PLANES may have unused entries
174 * between the topmost sprite plane and the cursor plane.
183 #define plane_name(p) ((p) + 'A')
185 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
195 #define port_name(p) ((p) + 'A')
197 #define I915_NUM_PHYS_VLV 2
209 enum intel_display_power_domain {
213 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
214 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
215 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
216 POWER_DOMAIN_TRANSCODER_A,
217 POWER_DOMAIN_TRANSCODER_B,
218 POWER_DOMAIN_TRANSCODER_C,
219 POWER_DOMAIN_TRANSCODER_EDP,
220 POWER_DOMAIN_TRANSCODER_DSI_A,
221 POWER_DOMAIN_TRANSCODER_DSI_C,
222 POWER_DOMAIN_PORT_DDI_A_LANES,
223 POWER_DOMAIN_PORT_DDI_B_LANES,
224 POWER_DOMAIN_PORT_DDI_C_LANES,
225 POWER_DOMAIN_PORT_DDI_D_LANES,
226 POWER_DOMAIN_PORT_DDI_E_LANES,
227 POWER_DOMAIN_PORT_DSI,
228 POWER_DOMAIN_PORT_CRT,
229 POWER_DOMAIN_PORT_OTHER,
238 POWER_DOMAIN_MODESET,
244 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
245 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
246 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
247 #define POWER_DOMAIN_TRANSCODER(tran) \
248 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
249 (tran) + POWER_DOMAIN_TRANSCODER_A)
253 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
265 #define for_each_hpd_pin(__pin) \
266 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
268 struct i915_hotplug {
269 struct work_struct hotplug_work;
272 unsigned long last_jiffies;
277 HPD_MARK_DISABLED = 2
279 } stats[HPD_NUM_PINS];
281 struct delayed_work reenable_work;
283 struct intel_digital_port *irq_port[I915_MAX_PORTS];
286 struct work_struct dig_port_work;
288 struct work_struct poll_init_work;
292 * if we get a HPD irq from DP and a HPD irq from non-DP
293 * the non-DP HPD could block the workqueue on a mode config
294 * mutex getting, that userspace may have taken. However
295 * userspace is waiting on the DP workqueue to run which is
296 * blocked behind the non-DP one.
298 struct workqueue_struct *dp_wq;
301 #define I915_GEM_GPU_DOMAINS \
302 (I915_GEM_DOMAIN_RENDER | \
303 I915_GEM_DOMAIN_SAMPLER | \
304 I915_GEM_DOMAIN_COMMAND | \
305 I915_GEM_DOMAIN_INSTRUCTION | \
306 I915_GEM_DOMAIN_VERTEX)
308 #define for_each_pipe(__dev_priv, __p) \
309 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
310 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
311 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
312 for_each_if ((__mask) & (1 << (__p)))
313 #define for_each_plane(__dev_priv, __pipe, __p) \
315 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
317 #define for_each_sprite(__dev_priv, __p, __s) \
319 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
322 #define for_each_port_masked(__port, __ports_mask) \
323 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
324 for_each_if ((__ports_mask) & (1 << (__port)))
326 #define for_each_crtc(dev, crtc) \
327 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
329 #define for_each_intel_plane(dev, intel_plane) \
330 list_for_each_entry(intel_plane, \
331 &(dev)->mode_config.plane_list, \
334 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
335 list_for_each_entry(intel_plane, \
336 &(dev)->mode_config.plane_list, \
338 for_each_if ((plane_mask) & \
339 (1 << drm_plane_index(&intel_plane->base)))
341 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
342 list_for_each_entry(intel_plane, \
343 &(dev)->mode_config.plane_list, \
345 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
347 #define for_each_intel_crtc(dev, intel_crtc) \
348 list_for_each_entry(intel_crtc, \
349 &(dev)->mode_config.crtc_list, \
352 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
353 list_for_each_entry(intel_crtc, \
354 &(dev)->mode_config.crtc_list, \
356 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
358 #define for_each_intel_encoder(dev, intel_encoder) \
359 list_for_each_entry(intel_encoder, \
360 &(dev)->mode_config.encoder_list, \
363 #define for_each_intel_connector(dev, intel_connector) \
364 list_for_each_entry(intel_connector, \
365 &(dev)->mode_config.connector_list, \
368 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
369 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
370 for_each_if ((intel_encoder)->base.crtc == (__crtc))
372 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
373 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
374 for_each_if ((intel_connector)->base.encoder == (__encoder))
376 #define for_each_power_domain(domain, mask) \
377 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
378 for_each_if ((1 << (domain)) & (mask))
380 struct drm_i915_private;
381 struct i915_mm_struct;
382 struct i915_mmu_object;
384 struct drm_i915_file_private {
385 struct drm_i915_private *dev_priv;
386 struct drm_file *file;
390 struct list_head request_list;
391 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
392 * chosen to prevent the CPU getting more than a frame ahead of the GPU
393 * (when using lax throttling for the frontbuffer). We also use it to
394 * offer free GPU waitboosts for severely congested workloads.
396 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
398 struct idr context_idr;
400 struct intel_rps_client {
401 struct list_head link;
405 unsigned int bsd_engine;
408 /* Used by dp and fdi links */
409 struct intel_link_m_n {
417 void intel_link_compute_m_n(int bpp, int nlanes,
418 int pixel_clock, int link_clock,
419 struct intel_link_m_n *m_n);
421 /* Interface history:
424 * 1.2: Add Power Management
425 * 1.3: Add vblank support
426 * 1.4: Fix cmdbuffer path, add heap destroy
427 * 1.5: Add vblank pipe configuration
428 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
429 * - Support vertical blank on secondary display pipe
431 #define DRIVER_MAJOR 1
432 #define DRIVER_MINOR 6
433 #define DRIVER_PATCHLEVEL 0
435 struct opregion_header;
436 struct opregion_acpi;
437 struct opregion_swsci;
438 struct opregion_asle;
440 struct intel_opregion {
441 struct opregion_header *header;
442 struct opregion_acpi *acpi;
443 struct opregion_swsci *swsci;
444 u32 swsci_gbda_sub_functions;
445 u32 swsci_sbcb_sub_functions;
446 struct opregion_asle *asle;
451 struct work_struct asle_work;
453 #define OPREGION_SIZE (8*1024)
455 struct intel_overlay;
456 struct intel_overlay_error_state;
458 struct drm_i915_fence_reg {
459 struct list_head link;
460 struct drm_i915_private *i915;
461 struct i915_vma *vma;
465 * Whether the tiling parameters for the currently
466 * associated fence register have changed. Note that
467 * for the purposes of tracking tiling changes we also
468 * treat the unfenced register, the register slot that
469 * the object occupies whilst it executes a fenced
470 * command (such as BLT on gen2/3), as a "fence".
475 struct sdvo_device_mapping {
484 struct intel_connector;
485 struct intel_encoder;
486 struct intel_crtc_state;
487 struct intel_initial_plane_config;
492 struct drm_i915_display_funcs {
493 int (*get_display_clock_speed)(struct drm_device *dev);
494 int (*get_fifo_size)(struct drm_device *dev, int plane);
495 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
496 int (*compute_intermediate_wm)(struct drm_device *dev,
497 struct intel_crtc *intel_crtc,
498 struct intel_crtc_state *newstate);
499 void (*initial_watermarks)(struct intel_crtc_state *cstate);
500 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
501 int (*compute_global_watermarks)(struct drm_atomic_state *state);
502 void (*update_wm)(struct drm_crtc *crtc);
503 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
504 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
505 /* Returns the active state of the crtc, and if the crtc is active,
506 * fills out the pipe-config with the hw state. */
507 bool (*get_pipe_config)(struct intel_crtc *,
508 struct intel_crtc_state *);
509 void (*get_initial_plane_config)(struct intel_crtc *,
510 struct intel_initial_plane_config *);
511 int (*crtc_compute_clock)(struct intel_crtc *crtc,
512 struct intel_crtc_state *crtc_state);
513 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
514 struct drm_atomic_state *old_state);
515 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
516 struct drm_atomic_state *old_state);
517 void (*update_crtcs)(struct drm_atomic_state *state,
518 unsigned int *crtc_vblank_mask);
519 void (*audio_codec_enable)(struct drm_connector *connector,
520 struct intel_encoder *encoder,
521 const struct drm_display_mode *adjusted_mode);
522 void (*audio_codec_disable)(struct intel_encoder *encoder);
523 void (*fdi_link_train)(struct drm_crtc *crtc);
524 void (*init_clock_gating)(struct drm_device *dev);
525 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
526 struct drm_framebuffer *fb,
527 struct drm_i915_gem_object *obj,
528 struct drm_i915_gem_request *req,
530 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
531 /* clock updates for mode set */
533 /* render clock increase/decrease */
534 /* display clock increase/decrease */
535 /* pll clock increase/decrease */
537 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
538 void (*load_luts)(struct drm_crtc_state *crtc_state);
541 enum forcewake_domain_id {
542 FW_DOMAIN_ID_RENDER = 0,
543 FW_DOMAIN_ID_BLITTER,
549 enum forcewake_domains {
550 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
551 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
552 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
553 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
558 #define FW_REG_READ (1)
559 #define FW_REG_WRITE (2)
561 enum forcewake_domains
562 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
563 i915_reg_t reg, unsigned int op);
565 struct intel_uncore_funcs {
566 void (*force_wake_get)(struct drm_i915_private *dev_priv,
567 enum forcewake_domains domains);
568 void (*force_wake_put)(struct drm_i915_private *dev_priv,
569 enum forcewake_domains domains);
571 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
572 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
573 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
574 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
576 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
577 uint8_t val, bool trace);
578 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
579 uint16_t val, bool trace);
580 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
581 uint32_t val, bool trace);
584 struct intel_uncore {
585 spinlock_t lock; /** lock is also taken in irq contexts. */
587 struct intel_uncore_funcs funcs;
590 enum forcewake_domains fw_domains;
592 struct intel_uncore_forcewake_domain {
593 struct drm_i915_private *i915;
594 enum forcewake_domain_id id;
595 enum forcewake_domains mask;
597 struct hrtimer timer;
604 } fw_domain[FW_DOMAIN_ID_COUNT];
606 int unclaimed_mmio_check;
609 /* Iterate over initialised fw domains */
610 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
611 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
612 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
614 for_each_if ((mask__) & (domain__)->mask)
616 #define for_each_fw_domain(domain__, dev_priv__) \
617 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
619 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
620 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
621 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
624 struct work_struct work;
626 uint32_t *dmc_payload;
627 uint32_t dmc_fw_size;
630 i915_reg_t mmioaddr[8];
631 uint32_t mmiodata[8];
633 uint32_t allowed_dc_mask;
636 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
637 func(is_mobile) sep \
640 func(is_i945gm) sep \
642 func(hws_needs_physical) sep \
644 func(is_pineview) sep \
645 func(is_broadwater) sep \
646 func(is_crestline) sep \
647 func(is_ivybridge) sep \
648 func(is_valleyview) sep \
649 func(is_cherryview) sep \
650 func(is_haswell) sep \
651 func(is_broadwell) sep \
652 func(is_skylake) sep \
653 func(is_broxton) sep \
654 func(is_kabylake) sep \
655 func(is_preliminary) sep \
658 func(has_runtime_pm) sep \
660 func(has_resource_streamer) sep \
663 func(has_dp_mst) sep \
664 func(has_gmbus_irq) sep \
665 func(has_hw_contexts) sep \
666 func(has_logical_ring_contexts) sep \
667 func(has_l3_dpf) sep \
668 func(has_gmch_display) sep \
670 func(has_pipe_cxsr) sep \
671 func(has_hotplug) sep \
672 func(cursor_needs_physical) sep \
673 func(has_overlay) sep \
674 func(overlay_needs_physical) sep \
675 func(supports_tv) sep \
677 func(has_snoop) sep \
679 func(has_fpga_dbg) sep \
682 #define DEFINE_FLAG(name) u8 name:1
683 #define SEP_SEMICOLON ;
685 struct sseu_dev_info {
691 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
694 u8 has_subslice_pg:1;
698 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
700 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
703 struct intel_device_info {
704 u32 display_mmio_offset;
707 u8 num_sprites[I915_MAX_PIPES];
710 u8 ring_mask; /* Rings supported by the HW */
712 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
713 u16 ddb_size; /* in blocks */
714 /* Register offsets for the various display pipes and transcoders */
715 int pipe_offsets[I915_MAX_TRANSCODERS];
716 int trans_offsets[I915_MAX_TRANSCODERS];
717 int palette_offsets[I915_MAX_PIPES];
718 int cursor_offsets[I915_MAX_PIPES];
720 /* Slice/subslice/EU info */
721 struct sseu_dev_info sseu;
724 u16 degamma_lut_size;
732 struct intel_display_error_state;
734 struct drm_i915_error_state {
743 struct intel_device_info device_info;
745 /* Generic register state */
753 u32 error; /* gen6+ */
754 u32 err_int; /* gen7 */
755 u32 fault_data0; /* gen8, gen9 */
756 u32 fault_data1; /* gen8, gen9 */
762 u32 extra_instdone[I915_NUM_INSTDONE_REG];
763 u64 fence[I915_MAX_NUM_FENCES];
764 struct intel_overlay_error_state *overlay;
765 struct intel_display_error_state *display;
766 struct drm_i915_error_object *semaphore;
768 struct drm_i915_error_engine {
770 /* Software tracked state */
774 enum intel_engine_hangcheck_action hangcheck_action;
775 struct i915_address_space *vm;
778 /* our own tracking of ring head and tail */
783 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
803 u32 rc_psmi; /* sleep state */
804 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
806 struct drm_i915_error_object {
811 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
813 struct drm_i915_error_object *wa_ctx;
815 struct drm_i915_error_request {
823 struct drm_i915_error_waiter {
824 char comm[TASK_COMM_LEN];
838 char comm[TASK_COMM_LEN];
839 } engine[I915_NUM_ENGINES];
841 struct drm_i915_error_buffer {
844 u32 rseqno[I915_NUM_ENGINES], wseqno;
848 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
855 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
856 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
857 struct i915_address_space *active_vm[I915_NUM_ENGINES];
860 enum i915_cache_level {
862 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
863 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
864 caches, eg sampler/render caches, and the
865 large Last-Level-Cache. LLC is coherent with
866 the CPU, but L3 is only visible to the GPU. */
867 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
870 struct i915_ctx_hang_stats {
871 /* This context had batch pending when hang was declared */
872 unsigned batch_pending;
874 /* This context had batch active when hang was declared */
875 unsigned batch_active;
877 /* Time when this context was last blamed for a GPU reset */
878 unsigned long guilty_ts;
880 /* If the contexts causes a second GPU hang within this time,
881 * it is permanently banned from submitting any more work.
883 unsigned long ban_period_seconds;
885 /* This context is banned to submit more work */
889 /* This must match up with the value previously used for execbuf2.rsvd1. */
890 #define DEFAULT_CONTEXT_HANDLE 0
893 * struct i915_gem_context - as the name implies, represents a context.
894 * @ref: reference count.
895 * @user_handle: userspace tracking identity for this context.
896 * @remap_slice: l3 row remapping information.
897 * @flags: context specific flags:
898 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
899 * @file_priv: filp associated with this context (NULL for global default
901 * @hang_stats: information about the role of this context in possible GPU
903 * @ppgtt: virtual memory space used by this context.
904 * @legacy_hw_ctx: render context backing object and whether it is correctly
905 * initialized (legacy ring submission mechanism only).
906 * @link: link in the global list of contexts.
908 * Contexts are memory images used by the hardware to store copies of their
911 struct i915_gem_context {
913 struct drm_i915_private *i915;
914 struct drm_i915_file_private *file_priv;
915 struct i915_hw_ppgtt *ppgtt;
918 struct i915_ctx_hang_stats hang_stats;
921 #define CONTEXT_NO_ZEROMAP BIT(0)
922 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
924 /* Unique identifier for this context, used by the hw for tracking */
930 struct intel_context {
931 struct i915_vma *state;
932 struct intel_ring *ring;
933 uint32_t *lrc_reg_state;
937 } engine[I915_NUM_ENGINES];
940 struct atomic_notifier_head status_notifier;
941 bool execlists_force_single_submission;
943 struct list_head link;
958 /* This is always the inner lock when overlapping with struct_mutex and
959 * it's the outer lock when overlapping with stolen_lock. */
962 unsigned int possible_framebuffer_bits;
963 unsigned int busy_bits;
964 unsigned int visible_pipes_mask;
965 struct intel_crtc *crtc;
967 struct drm_mm_node compressed_fb;
968 struct drm_mm_node *compressed_llb;
975 struct intel_fbc_state_cache {
977 unsigned int mode_flags;
978 uint32_t hsw_bdw_pixel_rate;
982 unsigned int rotation;
990 uint32_t pixel_format;
993 unsigned int tiling_mode;
997 struct intel_fbc_reg_params {
1001 unsigned int fence_y_offset;
1006 uint32_t pixel_format;
1007 unsigned int stride;
1014 struct intel_fbc_work {
1016 u32 scheduled_vblank;
1017 struct work_struct work;
1020 const char *no_fbc_reason;
1024 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1025 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1026 * parsing for same resolution.
1028 enum drrs_refresh_rate_type {
1031 DRRS_MAX_RR, /* RR count */
1034 enum drrs_support_type {
1035 DRRS_NOT_SUPPORTED = 0,
1036 STATIC_DRRS_SUPPORT = 1,
1037 SEAMLESS_DRRS_SUPPORT = 2
1043 struct delayed_work work;
1044 struct intel_dp *dp;
1045 unsigned busy_frontbuffer_bits;
1046 enum drrs_refresh_rate_type refresh_rate_type;
1047 enum drrs_support_type type;
1054 struct intel_dp *enabled;
1056 struct delayed_work work;
1057 unsigned busy_frontbuffer_bits;
1059 bool aux_frame_sync;
1064 PCH_NONE = 0, /* No PCH present */
1065 PCH_IBX, /* Ibexpeak PCH */
1066 PCH_CPT, /* Cougarpoint PCH */
1067 PCH_LPT, /* Lynxpoint PCH */
1068 PCH_SPT, /* Sunrisepoint PCH */
1069 PCH_KBP, /* Kabypoint PCH */
1073 enum intel_sbi_destination {
1078 #define QUIRK_PIPEA_FORCE (1<<0)
1079 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1080 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1081 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1082 #define QUIRK_PIPEB_FORCE (1<<4)
1083 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1086 struct intel_fbc_work;
1088 struct intel_gmbus {
1089 struct i2c_adapter adapter;
1090 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1093 i915_reg_t gpio_reg;
1094 struct i2c_algo_bit_data bit_algo;
1095 struct drm_i915_private *dev_priv;
1098 struct i915_suspend_saved_registers {
1100 u32 saveFBC_CONTROL;
1101 u32 saveCACHE_MODE_0;
1102 u32 saveMI_ARB_STATE;
1106 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1107 u32 savePCH_PORT_HOTPLUG;
1111 struct vlv_s0ix_state {
1118 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1119 u32 media_max_req_count;
1120 u32 gfx_max_req_count;
1146 u32 rp_down_timeout;
1152 /* Display 1 CZ domain */
1157 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1159 /* GT SA CZ domain */
1166 /* Display 2 CZ domain */
1170 u32 clock_gate_dis2;
1173 struct intel_rps_ei {
1179 struct intel_gen6_power_mgmt {
1181 * work, interrupts_enabled and pm_iir are protected by
1182 * dev_priv->irq_lock
1184 struct work_struct work;
1185 bool interrupts_enabled;
1188 /* PM interrupt bits that should never be masked */
1191 /* Frequencies are stored in potentially platform dependent multiples.
1192 * In other words, *_freq needs to be multiplied by X to be interesting.
1193 * Soft limits are those which are used for the dynamic reclocking done
1194 * by the driver (raise frequencies under heavy loads, and lower for
1195 * lighter loads). Hard limits are those imposed by the hardware.
1197 * A distinction is made for overclocking, which is never enabled by
1198 * default, and is considered to be above the hard limit if it's
1201 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1202 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1203 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1204 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1205 u8 min_freq; /* AKA RPn. Minimum frequency */
1206 u8 boost_freq; /* Frequency to request when wait boosting */
1207 u8 idle_freq; /* Frequency to request when we are idle */
1208 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1209 u8 rp1_freq; /* "less than" RP0 power/freqency */
1210 u8 rp0_freq; /* Non-overclocked max frequency. */
1211 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1213 u8 up_threshold; /* Current %busy required to uplock */
1214 u8 down_threshold; /* Current %busy required to downclock */
1217 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1219 spinlock_t client_lock;
1220 struct list_head clients;
1224 struct delayed_work autoenable_work;
1227 /* manual wa residency calculations */
1228 struct intel_rps_ei up_ei, down_ei;
1231 * Protects RPS/RC6 register access and PCU communication.
1232 * Must be taken after struct_mutex if nested. Note that
1233 * this lock may be held for long periods of time when
1234 * talking to hw - so only take it when talking to hw!
1236 struct mutex hw_lock;
1239 /* defined intel_pm.c */
1240 extern spinlock_t mchdev_lock;
1242 struct intel_ilk_power_mgmt {
1250 unsigned long last_time1;
1251 unsigned long chipset_power;
1254 unsigned long gfx_power;
1261 struct drm_i915_private;
1262 struct i915_power_well;
1264 struct i915_power_well_ops {
1266 * Synchronize the well's hw state to match the current sw state, for
1267 * example enable/disable it based on the current refcount. Called
1268 * during driver init and resume time, possibly after first calling
1269 * the enable/disable handlers.
1271 void (*sync_hw)(struct drm_i915_private *dev_priv,
1272 struct i915_power_well *power_well);
1274 * Enable the well and resources that depend on it (for example
1275 * interrupts located on the well). Called after the 0->1 refcount
1278 void (*enable)(struct drm_i915_private *dev_priv,
1279 struct i915_power_well *power_well);
1281 * Disable the well and resources that depend on it. Called after
1282 * the 1->0 refcount transition.
1284 void (*disable)(struct drm_i915_private *dev_priv,
1285 struct i915_power_well *power_well);
1286 /* Returns the hw enabled state. */
1287 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1288 struct i915_power_well *power_well);
1291 /* Power well structure for haswell */
1292 struct i915_power_well {
1295 /* power well enable/disable usage count */
1297 /* cached hw enabled state */
1299 unsigned long domains;
1301 const struct i915_power_well_ops *ops;
1304 struct i915_power_domains {
1306 * Power wells needed for initialization at driver init and suspend
1307 * time are on. They are kept on until after the first modeset.
1311 int power_well_count;
1314 int domain_use_count[POWER_DOMAIN_NUM];
1315 struct i915_power_well *power_wells;
1318 #define MAX_L3_SLICES 2
1319 struct intel_l3_parity {
1320 u32 *remap_info[MAX_L3_SLICES];
1321 struct work_struct error_work;
1325 struct i915_gem_mm {
1326 /** Memory allocator for GTT stolen memory */
1327 struct drm_mm stolen;
1328 /** Protects the usage of the GTT stolen memory allocator. This is
1329 * always the inner lock when overlapping with struct_mutex. */
1330 struct mutex stolen_lock;
1332 /** List of all objects in gtt_space. Used to restore gtt
1333 * mappings on resume */
1334 struct list_head bound_list;
1336 * List of objects which are not bound to the GTT (thus
1337 * are idle and not used by the GPU) but still have
1338 * (presumably uncached) pages still attached.
1340 struct list_head unbound_list;
1342 /** Usable portion of the GTT for GEM */
1343 unsigned long stolen_base; /* limited to low memory (32-bit) */
1345 /** PPGTT used for aliasing the PPGTT with the GTT */
1346 struct i915_hw_ppgtt *aliasing_ppgtt;
1348 struct notifier_block oom_notifier;
1349 struct notifier_block vmap_notifier;
1350 struct shrinker shrinker;
1352 /** LRU list of objects with fence regs on them. */
1353 struct list_head fence_list;
1356 * Are we in a non-interruptible section of code like
1361 /* the indicator for dispatch video commands on two BSD rings */
1362 atomic_t bsd_engine_dispatch_index;
1364 /** Bit 6 swizzling required for X tiling */
1365 uint32_t bit_6_swizzle_x;
1366 /** Bit 6 swizzling required for Y tiling */
1367 uint32_t bit_6_swizzle_y;
1369 /* accounting, useful for userland debugging */
1370 spinlock_t object_stat_lock;
1371 size_t object_memory;
1375 struct drm_i915_error_state_buf {
1376 struct drm_i915_private *i915;
1385 struct i915_error_state_file_priv {
1386 struct drm_device *dev;
1387 struct drm_i915_error_state *error;
1390 struct i915_gpu_error {
1391 /* For hangcheck timer */
1392 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1393 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1394 /* Hang gpu twice in this window and your context gets banned */
1395 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1397 struct delayed_work hangcheck_work;
1399 /* For reset and error_state handling. */
1401 /* Protected by the above dev->gpu_error.lock. */
1402 struct drm_i915_error_state *first_error;
1404 unsigned long missed_irq_rings;
1407 * State variable controlling the reset flow and count
1409 * This is a counter which gets incremented when reset is triggered,
1411 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1412 * meaning that any waiters holding onto the struct_mutex should
1413 * relinquish the lock immediately in order for the reset to start.
1415 * If reset is not completed succesfully, the I915_WEDGE bit is
1416 * set meaning that hardware is terminally sour and there is no
1417 * recovery. All waiters on the reset_queue will be woken when
1420 * This counter is used by the wait_seqno code to notice that reset
1421 * event happened and it needs to restart the entire ioctl (since most
1422 * likely the seqno it waited for won't ever signal anytime soon).
1424 * This is important for lock-free wait paths, where no contended lock
1425 * naturally enforces the correct ordering between the bail-out of the
1426 * waiter and the gpu reset work code.
1428 unsigned long reset_count;
1430 unsigned long flags;
1431 #define I915_RESET_IN_PROGRESS 0
1432 #define I915_WEDGED (BITS_PER_LONG - 1)
1435 * Waitqueue to signal when a hang is detected. Used to for waiters
1436 * to release the struct_mutex for the reset to procede.
1438 wait_queue_head_t wait_queue;
1441 * Waitqueue to signal when the reset has completed. Used by clients
1442 * that wait for dev_priv->mm.wedged to settle.
1444 wait_queue_head_t reset_queue;
1446 /* For missed irq/seqno simulation. */
1447 unsigned long test_irq_rings;
1450 enum modeset_restore {
1451 MODESET_ON_LID_OPEN,
1456 #define DP_AUX_A 0x40
1457 #define DP_AUX_B 0x10
1458 #define DP_AUX_C 0x20
1459 #define DP_AUX_D 0x30
1461 #define DDC_PIN_B 0x05
1462 #define DDC_PIN_C 0x04
1463 #define DDC_PIN_D 0x06
1465 struct ddi_vbt_port_info {
1467 * This is an index in the HDMI/DVI DDI buffer translation table.
1468 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1469 * populate this field.
1471 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1472 uint8_t hdmi_level_shift;
1474 uint8_t supports_dvi:1;
1475 uint8_t supports_hdmi:1;
1476 uint8_t supports_dp:1;
1478 uint8_t alternate_aux_channel;
1479 uint8_t alternate_ddc_pin;
1481 uint8_t dp_boost_level;
1482 uint8_t hdmi_boost_level;
1485 enum psr_lines_to_wait {
1486 PSR_0_LINES_TO_WAIT = 0,
1488 PSR_4_LINES_TO_WAIT,
1492 struct intel_vbt_data {
1493 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1494 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1497 unsigned int int_tv_support:1;
1498 unsigned int lvds_dither:1;
1499 unsigned int lvds_vbt:1;
1500 unsigned int int_crt_support:1;
1501 unsigned int lvds_use_ssc:1;
1502 unsigned int display_clock_mode:1;
1503 unsigned int fdi_rx_polarity_inverted:1;
1504 unsigned int panel_type:4;
1506 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1508 enum drrs_support_type drrs_type;
1519 struct edp_power_seq pps;
1524 bool require_aux_wakeup;
1526 enum psr_lines_to_wait lines_to_wait;
1527 int tp1_wakeup_time;
1528 int tp2_tp3_wakeup_time;
1534 bool active_low_pwm;
1535 u8 min_brightness; /* min_brightness/255 of max */
1536 enum intel_backlight_type type;
1542 struct mipi_config *config;
1543 struct mipi_pps_data *pps;
1547 const u8 *sequence[MIPI_SEQ_MAX];
1553 union child_device_config *child_dev;
1555 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1556 struct sdvo_device_mapping sdvo_mappings[2];
1559 enum intel_ddb_partitioning {
1561 INTEL_DDB_PART_5_6, /* IVB+ */
1564 struct intel_wm_level {
1572 struct ilk_wm_values {
1573 uint32_t wm_pipe[3];
1575 uint32_t wm_lp_spr[3];
1576 uint32_t wm_linetime[3];
1578 enum intel_ddb_partitioning partitioning;
1581 struct vlv_pipe_wm {
1592 struct vlv_wm_values {
1593 struct vlv_pipe_wm pipe[3];
1594 struct vlv_sr_wm sr;
1604 struct skl_ddb_entry {
1605 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1608 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1610 return entry->end - entry->start;
1613 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1614 const struct skl_ddb_entry *e2)
1616 if (e1->start == e2->start && e1->end == e2->end)
1622 struct skl_ddb_allocation {
1623 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1624 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1625 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1628 struct skl_wm_values {
1629 unsigned dirty_pipes;
1630 struct skl_ddb_allocation ddb;
1631 uint32_t wm_linetime[I915_MAX_PIPES];
1632 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1633 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1636 struct skl_wm_level {
1637 bool plane_en[I915_MAX_PLANES];
1638 uint16_t plane_res_b[I915_MAX_PLANES];
1639 uint8_t plane_res_l[I915_MAX_PLANES];
1643 * This struct helps tracking the state needed for runtime PM, which puts the
1644 * device in PCI D3 state. Notice that when this happens, nothing on the
1645 * graphics device works, even register access, so we don't get interrupts nor
1648 * Every piece of our code that needs to actually touch the hardware needs to
1649 * either call intel_runtime_pm_get or call intel_display_power_get with the
1650 * appropriate power domain.
1652 * Our driver uses the autosuspend delay feature, which means we'll only really
1653 * suspend if we stay with zero refcount for a certain amount of time. The
1654 * default value is currently very conservative (see intel_runtime_pm_enable), but
1655 * it can be changed with the standard runtime PM files from sysfs.
1657 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1658 * goes back to false exactly before we reenable the IRQs. We use this variable
1659 * to check if someone is trying to enable/disable IRQs while they're supposed
1660 * to be disabled. This shouldn't happen and we'll print some error messages in
1663 * For more, read the Documentation/power/runtime_pm.txt.
1665 struct i915_runtime_pm {
1666 atomic_t wakeref_count;
1667 atomic_t atomic_seq;
1672 enum intel_pipe_crc_source {
1673 INTEL_PIPE_CRC_SOURCE_NONE,
1674 INTEL_PIPE_CRC_SOURCE_PLANE1,
1675 INTEL_PIPE_CRC_SOURCE_PLANE2,
1676 INTEL_PIPE_CRC_SOURCE_PF,
1677 INTEL_PIPE_CRC_SOURCE_PIPE,
1678 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1679 INTEL_PIPE_CRC_SOURCE_TV,
1680 INTEL_PIPE_CRC_SOURCE_DP_B,
1681 INTEL_PIPE_CRC_SOURCE_DP_C,
1682 INTEL_PIPE_CRC_SOURCE_DP_D,
1683 INTEL_PIPE_CRC_SOURCE_AUTO,
1684 INTEL_PIPE_CRC_SOURCE_MAX,
1687 struct intel_pipe_crc_entry {
1692 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1693 struct intel_pipe_crc {
1695 bool opened; /* exclusive access to the result file */
1696 struct intel_pipe_crc_entry *entries;
1697 enum intel_pipe_crc_source source;
1699 wait_queue_head_t wq;
1702 struct i915_frontbuffer_tracking {
1706 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1713 struct i915_wa_reg {
1716 /* bitmask representing WA bits */
1721 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1722 * allowing it for RCS as we don't foresee any requirement of having
1723 * a whitelist for other engines. When it is really required for
1724 * other engines then the limit need to be increased.
1726 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1728 struct i915_workarounds {
1729 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1731 u32 hw_whitelist_count[I915_NUM_ENGINES];
1734 struct i915_virtual_gpu {
1738 /* used in computing the new watermarks state */
1739 struct intel_wm_config {
1740 unsigned int num_pipes_active;
1741 bool sprites_enabled;
1742 bool sprites_scaled;
1745 struct drm_i915_private {
1746 struct drm_device drm;
1748 struct kmem_cache *objects;
1749 struct kmem_cache *vmas;
1750 struct kmem_cache *requests;
1752 const struct intel_device_info info;
1754 int relative_constants_mode;
1758 struct intel_uncore uncore;
1760 struct i915_virtual_gpu vgpu;
1762 struct intel_gvt gvt;
1764 struct intel_guc guc;
1766 struct intel_csr csr;
1768 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1770 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1771 * controller on different i2c buses. */
1772 struct mutex gmbus_mutex;
1775 * Base address of the gmbus and gpio block.
1777 uint32_t gpio_mmio_base;
1779 /* MMIO base address for MIPI regs */
1780 uint32_t mipi_mmio_base;
1782 uint32_t psr_mmio_base;
1784 uint32_t pps_mmio_base;
1786 wait_queue_head_t gmbus_wait_queue;
1788 struct pci_dev *bridge_dev;
1789 struct i915_gem_context *kernel_context;
1790 struct intel_engine_cs engine[I915_NUM_ENGINES];
1791 struct i915_vma *semaphore;
1794 struct drm_dma_handle *status_page_dmah;
1795 struct resource mch_res;
1797 /* protects the irq masks */
1798 spinlock_t irq_lock;
1800 /* protects the mmio flip data */
1801 spinlock_t mmio_flip_lock;
1803 bool display_irqs_enabled;
1805 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1806 struct pm_qos_request pm_qos;
1808 /* Sideband mailbox protection */
1809 struct mutex sb_lock;
1811 /** Cached value of IMR to avoid reads in updating the bitfield */
1814 u32 de_irq_mask[I915_MAX_PIPES];
1819 u32 pipestat_irq_mask[I915_MAX_PIPES];
1821 struct i915_hotplug hotplug;
1822 struct intel_fbc fbc;
1823 struct i915_drrs drrs;
1824 struct intel_opregion opregion;
1825 struct intel_vbt_data vbt;
1827 bool preserve_bios_swizzle;
1830 struct intel_overlay *overlay;
1832 /* backlight registers and fields in struct intel_panel */
1833 struct mutex backlight_lock;
1836 bool no_aux_handshake;
1838 /* protects panel power sequencer state */
1839 struct mutex pps_mutex;
1841 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1842 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1844 unsigned int fsb_freq, mem_freq, is_ddr3;
1845 unsigned int skl_preferred_vco_freq;
1846 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1847 unsigned int max_dotclk_freq;
1848 unsigned int rawclk_freq;
1849 unsigned int hpll_freq;
1850 unsigned int czclk_freq;
1853 unsigned int vco, ref;
1857 * wq - Driver workqueue for GEM.
1859 * NOTE: Work items scheduled here are not allowed to grab any modeset
1860 * locks, for otherwise the flushing done in the pageflip code will
1861 * result in deadlocks.
1863 struct workqueue_struct *wq;
1865 /* Display functions */
1866 struct drm_i915_display_funcs display;
1868 /* PCH chipset type */
1869 enum intel_pch pch_type;
1870 unsigned short pch_id;
1872 unsigned long quirks;
1874 enum modeset_restore modeset_restore;
1875 struct mutex modeset_restore_lock;
1876 struct drm_atomic_state *modeset_restore_state;
1877 struct drm_modeset_acquire_ctx reset_ctx;
1879 struct list_head vm_list; /* Global list of all address spaces */
1880 struct i915_ggtt ggtt; /* VM representing the global address space */
1882 struct i915_gem_mm mm;
1883 DECLARE_HASHTABLE(mm_structs, 7);
1884 struct mutex mm_lock;
1886 /* The hw wants to have a stable context identifier for the lifetime
1887 * of the context (for OA, PASID, faults, etc). This is limited
1888 * in execlists to 21 bits.
1890 struct ida context_hw_ida;
1891 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1893 /* Kernel Modesetting */
1895 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1896 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1897 wait_queue_head_t pending_flip_queue;
1899 #ifdef CONFIG_DEBUG_FS
1900 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1903 /* dpll and cdclk state is protected by connection_mutex */
1904 int num_shared_dpll;
1905 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1906 const struct intel_dpll_mgr *dpll_mgr;
1909 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1910 * Must be global rather than per dpll, because on some platforms
1911 * plls share registers.
1913 struct mutex dpll_lock;
1915 unsigned int active_crtcs;
1916 unsigned int min_pixclk[I915_MAX_PIPES];
1918 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1920 struct i915_workarounds workarounds;
1922 struct i915_frontbuffer_tracking fb_tracking;
1926 bool mchbar_need_disable;
1928 struct intel_l3_parity l3_parity;
1930 /* Cannot be determined by PCIID. You must always read a register. */
1933 /* gen6+ rps state */
1934 struct intel_gen6_power_mgmt rps;
1936 /* ilk-only ips/rps state. Everything in here is protected by the global
1937 * mchdev_lock in intel_pm.c */
1938 struct intel_ilk_power_mgmt ips;
1940 struct i915_power_domains power_domains;
1942 struct i915_psr psr;
1944 struct i915_gpu_error gpu_error;
1946 struct drm_i915_gem_object *vlv_pctx;
1948 #ifdef CONFIG_DRM_FBDEV_EMULATION
1949 /* list of fbdev register on this device */
1950 struct intel_fbdev *fbdev;
1951 struct work_struct fbdev_suspend_work;
1954 struct drm_property *broadcast_rgb_property;
1955 struct drm_property *force_audio_property;
1957 /* hda/i915 audio component */
1958 struct i915_audio_component *audio_component;
1959 bool audio_component_registered;
1961 * av_mutex - mutex for audio/video sync
1964 struct mutex av_mutex;
1966 uint32_t hw_context_size;
1967 struct list_head context_list;
1971 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1972 u32 chv_phy_control;
1974 * Shadows for CHV DPLL_MD regs to keep the state
1975 * checker somewhat working in the presence hardware
1976 * crappiness (can't read out DPLL_MD for pipes B & C).
1978 u32 chv_dpll_md[I915_MAX_PIPES];
1982 bool suspended_to_idle;
1983 struct i915_suspend_saved_registers regfile;
1984 struct vlv_s0ix_state vlv_s0ix_state;
1987 I915_SAGV_UNKNOWN = 0,
1990 I915_SAGV_NOT_CONTROLLED
1995 * Raw watermark latency values:
1996 * in 0.1us units for WM0,
1997 * in 0.5us units for WM1+.
2000 uint16_t pri_latency[5];
2002 uint16_t spr_latency[5];
2004 uint16_t cur_latency[5];
2006 * Raw watermark memory latency values
2007 * for SKL for all 8 levels
2010 uint16_t skl_latency[8];
2013 * The skl_wm_values structure is a bit too big for stack
2014 * allocation, so we keep the staging struct where we store
2015 * intermediate results here instead.
2017 struct skl_wm_values skl_results;
2019 /* current hardware state */
2021 struct ilk_wm_values hw;
2022 struct skl_wm_values skl_hw;
2023 struct vlv_wm_values vlv;
2029 * Should be held around atomic WM register writing; also
2030 * protects * intel_crtc->wm.active and
2031 * cstate->wm.need_postvbl_update.
2033 struct mutex wm_mutex;
2036 * Set during HW readout of watermarks/DDB. Some platforms
2037 * need to know when we're still using BIOS-provided values
2038 * (which we don't fully trust).
2040 bool distrust_bios_wm;
2043 struct i915_runtime_pm pm;
2045 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2047 void (*resume)(struct drm_i915_private *);
2048 void (*cleanup_engine)(struct intel_engine_cs *engine);
2051 * Is the GPU currently considered idle, or busy executing
2052 * userspace requests? Whilst idle, we allow runtime power
2053 * management to power down the hardware and display clocks.
2054 * In order to reduce the effect on performance, there
2055 * is a slight delay before we do so.
2057 unsigned int active_engines;
2061 * We leave the user IRQ off as much as possible,
2062 * but this means that requests will finish and never
2063 * be retired once the system goes idle. Set a timer to
2064 * fire periodically while the ring is running. When it
2065 * fires, go retire requests.
2067 struct delayed_work retire_work;
2070 * When we detect an idle GPU, we want to turn on
2071 * powersaving features. So once we see that there
2072 * are no more requests outstanding and no more
2073 * arrive within a small period of time, we fire
2074 * off the idle_work.
2076 struct delayed_work idle_work;
2079 /* perform PHY state sanity checks? */
2080 bool chv_phy_assert[2];
2082 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
2085 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2086 * will be rejected. Instead look for a better place.
2090 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2092 return container_of(dev, struct drm_i915_private, drm);
2095 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2097 return to_i915(dev_get_drvdata(kdev));
2100 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2102 return container_of(guc, struct drm_i915_private, guc);
2105 /* Simple iterator over all initialised engines */
2106 #define for_each_engine(engine__, dev_priv__) \
2107 for ((engine__) = &(dev_priv__)->engine[0]; \
2108 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2110 for_each_if (intel_engine_initialized(engine__))
2112 /* Iterator with engine_id */
2113 #define for_each_engine_id(engine__, dev_priv__, id__) \
2114 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2115 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2117 for_each_if (((id__) = (engine__)->id, \
2118 intel_engine_initialized(engine__)))
2120 #define __mask_next_bit(mask) ({ \
2121 int __idx = ffs(mask) - 1; \
2122 mask &= ~BIT(__idx); \
2126 /* Iterator over subset of engines selected by mask */
2127 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2128 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2129 tmp__ ? (engine__ = &(dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2131 enum hdmi_force_audio {
2132 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2133 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2134 HDMI_AUDIO_AUTO, /* trust EDID */
2135 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2138 #define I915_GTT_OFFSET_NONE ((u32)-1)
2140 struct drm_i915_gem_object_ops {
2142 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2144 /* Interface between the GEM object and its backing storage.
2145 * get_pages() is called once prior to the use of the associated set
2146 * of pages before to binding them into the GTT, and put_pages() is
2147 * called after we no longer need them. As we expect there to be
2148 * associated cost with migrating pages between the backing storage
2149 * and making them available for the GPU (e.g. clflush), we may hold
2150 * onto the pages after they are no longer referenced by the GPU
2151 * in case they may be used again shortly (for example migrating the
2152 * pages to a different memory domain within the GTT). put_pages()
2153 * will therefore most likely be called when the object itself is
2154 * being released or under memory pressure (where we attempt to
2155 * reap pages for the shrinker).
2157 int (*get_pages)(struct drm_i915_gem_object *);
2158 void (*put_pages)(struct drm_i915_gem_object *);
2160 int (*dmabuf_export)(struct drm_i915_gem_object *);
2161 void (*release)(struct drm_i915_gem_object *);
2165 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2166 * considered to be the frontbuffer for the given plane interface-wise. This
2167 * doesn't mean that the hw necessarily already scans it out, but that any
2168 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2170 * We have one bit per pipe and per scanout plane type.
2172 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2173 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2174 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2175 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2176 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2177 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2178 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2179 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2180 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2181 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2182 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2183 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2185 struct drm_i915_gem_object {
2186 struct drm_gem_object base;
2188 const struct drm_i915_gem_object_ops *ops;
2190 /** List of VMAs backed by this object */
2191 struct list_head vma_list;
2193 /** Stolen memory for this object, instead of being backed by shmem. */
2194 struct drm_mm_node *stolen;
2195 struct list_head global_list;
2197 /** Used in execbuf to temporarily hold a ref */
2198 struct list_head obj_exec_link;
2200 struct list_head batch_pool_link;
2202 unsigned long flags;
2204 * This is set if the object is on the active lists (has pending
2205 * rendering and so a non-zero seqno), and is not set if it i s on
2206 * inactive (ready to be unbound) list.
2208 #define I915_BO_ACTIVE_SHIFT 0
2209 #define I915_BO_ACTIVE_MASK ((1 << I915_NUM_ENGINES) - 1)
2210 #define __I915_BO_ACTIVE(bo) \
2211 ((READ_ONCE((bo)->flags) >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK)
2214 * This is set if the object has been written to since last bound
2217 unsigned int dirty:1;
2220 * Advice: are the backing pages purgeable?
2222 unsigned int madv:2;
2225 * Whether the current gtt mapping needs to be mappable (and isn't just
2226 * mappable by accident). Track pin and fault separate for a more
2227 * accurate mappable working set.
2229 unsigned int fault_mappable:1;
2232 * Is the object to be mapped as read-only to the GPU
2233 * Only honoured if hardware has relevant pte bit
2235 unsigned long gt_ro:1;
2236 unsigned int cache_level:3;
2237 unsigned int cache_dirty:1;
2239 atomic_t frontbuffer_bits;
2240 unsigned int frontbuffer_ggtt_origin; /* write once */
2242 /** Current tiling stride for the object, if it's tiled. */
2243 unsigned int tiling_and_stride;
2244 #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
2245 #define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
2246 #define STRIDE_MASK (~TILING_MASK)
2248 /** Count of VMA actually bound by this object */
2249 unsigned int bind_count;
2250 unsigned int pin_display;
2252 struct sg_table *pages;
2253 int pages_pin_count;
2255 struct scatterlist *sg;
2260 /** Breadcrumb of last rendering to the buffer.
2261 * There can only be one writer, but we allow for multiple readers.
2262 * If there is a writer that necessarily implies that all other
2263 * read requests are complete - but we may only be lazily clearing
2264 * the read requests. A read request is naturally the most recent
2265 * request on a ring, so we may have two different write and read
2266 * requests on one ring where the write request is older than the
2267 * read request. This allows for the CPU to read from an active
2268 * buffer by only waiting for the write to complete.
2270 struct i915_gem_active last_read[I915_NUM_ENGINES];
2271 struct i915_gem_active last_write;
2273 /** References from framebuffers, locks out tiling changes. */
2274 unsigned long framebuffer_references;
2276 /** Record of address bit 17 of each page at last unbind. */
2277 unsigned long *bit_17;
2279 struct i915_gem_userptr {
2281 unsigned read_only :1;
2282 unsigned workers :4;
2283 #define I915_GEM_USERPTR_MAX_WORKERS 15
2285 struct i915_mm_struct *mm;
2286 struct i915_mmu_object *mmu_object;
2287 struct work_struct *work;
2290 /** for phys allocated objects */
2291 struct drm_dma_handle *phys_handle;
2294 static inline struct drm_i915_gem_object *
2295 to_intel_bo(struct drm_gem_object *gem)
2297 /* Assert that to_intel_bo(NULL) == NULL */
2298 BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));
2300 return container_of(gem, struct drm_i915_gem_object, base);
2303 static inline struct drm_i915_gem_object *
2304 i915_gem_object_lookup(struct drm_file *file, u32 handle)
2306 return to_intel_bo(drm_gem_object_lookup(file, handle));
2310 extern struct drm_gem_object *
2311 drm_gem_object_lookup(struct drm_file *file, u32 handle);
2313 __attribute__((nonnull))
2314 static inline struct drm_i915_gem_object *
2315 i915_gem_object_get(struct drm_i915_gem_object *obj)
2317 drm_gem_object_reference(&obj->base);
2322 extern void drm_gem_object_reference(struct drm_gem_object *);
2324 __attribute__((nonnull))
2326 i915_gem_object_put(struct drm_i915_gem_object *obj)
2328 drm_gem_object_unreference(&obj->base);
2332 extern void drm_gem_object_unreference(struct drm_gem_object *);
2334 __attribute__((nonnull))
2336 i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj)
2338 drm_gem_object_unreference_unlocked(&obj->base);
2342 extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *);
2345 i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
2347 return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
2350 static inline unsigned long
2351 i915_gem_object_get_active(const struct drm_i915_gem_object *obj)
2353 return (obj->flags >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK;
2357 i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
2359 return i915_gem_object_get_active(obj);
2363 i915_gem_object_set_active(struct drm_i915_gem_object *obj, int engine)
2365 obj->flags |= BIT(engine + I915_BO_ACTIVE_SHIFT);
2369 i915_gem_object_clear_active(struct drm_i915_gem_object *obj, int engine)
2371 obj->flags &= ~BIT(engine + I915_BO_ACTIVE_SHIFT);
2375 i915_gem_object_has_active_engine(const struct drm_i915_gem_object *obj,
2378 return obj->flags & BIT(engine + I915_BO_ACTIVE_SHIFT);
2381 static inline unsigned int
2382 i915_gem_object_get_tiling(struct drm_i915_gem_object *obj)
2384 return obj->tiling_and_stride & TILING_MASK;
2388 i915_gem_object_is_tiled(struct drm_i915_gem_object *obj)
2390 return i915_gem_object_get_tiling(obj) != I915_TILING_NONE;
2393 static inline unsigned int
2394 i915_gem_object_get_stride(struct drm_i915_gem_object *obj)
2396 return obj->tiling_and_stride & STRIDE_MASK;
2399 static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
2401 i915_gem_object_get(vma->obj);
2405 static inline void i915_vma_put(struct i915_vma *vma)
2407 lockdep_assert_held(&vma->vm->dev->struct_mutex);
2408 i915_gem_object_put(vma->obj);
2412 * Optimised SGL iterator for GEM objects
2414 static __always_inline struct sgt_iter {
2415 struct scatterlist *sgp;
2422 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2423 struct sgt_iter s = { .sgp = sgl };
2426 s.max = s.curr = s.sgp->offset;
2427 s.max += s.sgp->length;
2429 s.dma = sg_dma_address(s.sgp);
2431 s.pfn = page_to_pfn(sg_page(s.sgp));
2438 * __sg_next - return the next scatterlist entry in a list
2439 * @sg: The current sg entry
2442 * If the entry is the last, return NULL; otherwise, step to the next
2443 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2444 * otherwise just return the pointer to the current element.
2446 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2448 #ifdef CONFIG_DEBUG_SG
2449 BUG_ON(sg->sg_magic != SG_MAGIC);
2451 return sg_is_last(sg) ? NULL :
2452 likely(!sg_is_chain(++sg)) ? sg :
2457 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2458 * @__dmap: DMA address (output)
2459 * @__iter: 'struct sgt_iter' (iterator state, internal)
2460 * @__sgt: sg_table to iterate over (input)
2462 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2463 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2464 ((__dmap) = (__iter).dma + (__iter).curr); \
2465 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2466 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2469 * for_each_sgt_page - iterate over the pages of the given sg_table
2470 * @__pp: page pointer (output)
2471 * @__iter: 'struct sgt_iter' (iterator state, internal)
2472 * @__sgt: sg_table to iterate over (input)
2474 #define for_each_sgt_page(__pp, __iter, __sgt) \
2475 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2476 ((__pp) = (__iter).pfn == 0 ? NULL : \
2477 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2478 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2479 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2482 * A command that requires special handling by the command parser.
2484 struct drm_i915_cmd_descriptor {
2486 * Flags describing how the command parser processes the command.
2488 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2489 * a length mask if not set
2490 * CMD_DESC_SKIP: The command is allowed but does not follow the
2491 * standard length encoding for the opcode range in
2493 * CMD_DESC_REJECT: The command is never allowed
2494 * CMD_DESC_REGISTER: The command should be checked against the
2495 * register whitelist for the appropriate ring
2496 * CMD_DESC_MASTER: The command is allowed if the submitting process
2500 #define CMD_DESC_FIXED (1<<0)
2501 #define CMD_DESC_SKIP (1<<1)
2502 #define CMD_DESC_REJECT (1<<2)
2503 #define CMD_DESC_REGISTER (1<<3)
2504 #define CMD_DESC_BITMASK (1<<4)
2505 #define CMD_DESC_MASTER (1<<5)
2508 * The command's unique identification bits and the bitmask to get them.
2509 * This isn't strictly the opcode field as defined in the spec and may
2510 * also include type, subtype, and/or subop fields.
2518 * The command's length. The command is either fixed length (i.e. does
2519 * not include a length field) or has a length field mask. The flag
2520 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2521 * a length mask. All command entries in a command table must include
2522 * length information.
2530 * Describes where to find a register address in the command to check
2531 * against the ring's register whitelist. Only valid if flags has the
2532 * CMD_DESC_REGISTER bit set.
2534 * A non-zero step value implies that the command may access multiple
2535 * registers in sequence (e.g. LRI), in that case step gives the
2536 * distance in dwords between individual offset fields.
2544 #define MAX_CMD_DESC_BITMASKS 3
2546 * Describes command checks where a particular dword is masked and
2547 * compared against an expected value. If the command does not match
2548 * the expected value, the parser rejects it. Only valid if flags has
2549 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2552 * If the check specifies a non-zero condition_mask then the parser
2553 * only performs the check when the bits specified by condition_mask
2560 u32 condition_offset;
2562 } bits[MAX_CMD_DESC_BITMASKS];
2566 * A table of commands requiring special handling by the command parser.
2568 * Each engine has an array of tables. Each table consists of an array of
2569 * command descriptors, which must be sorted with command opcodes in
2572 struct drm_i915_cmd_table {
2573 const struct drm_i915_cmd_descriptor *table;
2577 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2578 #define __I915__(p) ({ \
2579 struct drm_i915_private *__p; \
2580 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2581 __p = (struct drm_i915_private *)p; \
2582 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2583 __p = to_i915((struct drm_device *)p); \
2588 #define INTEL_INFO(p) (&__I915__(p)->info)
2589 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2590 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2592 #define REVID_FOREVER 0xff
2593 #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
2595 #define GEN_FOREVER (0)
2597 * Returns true if Gen is in inclusive range [Start, End].
2599 * Use GEN_FOREVER for unbound start and or end.
2601 #define IS_GEN(p, s, e) ({ \
2602 unsigned int __s = (s), __e = (e); \
2603 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2604 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2605 if ((__s) != GEN_FOREVER) \
2607 if ((__e) == GEN_FOREVER) \
2608 __e = BITS_PER_LONG - 1; \
2611 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2615 * Return true if revision is in range [since,until] inclusive.
2617 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2619 #define IS_REVID(p, since, until) \
2620 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2622 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2623 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2624 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2625 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2626 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2627 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2628 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2629 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2630 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2631 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2632 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2633 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2634 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2635 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2636 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2637 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2638 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2639 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2640 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2641 INTEL_DEVID(dev) == 0x0152 || \
2642 INTEL_DEVID(dev) == 0x015a)
2643 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2644 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2645 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2646 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
2647 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2648 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2649 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2650 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2651 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2652 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2653 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2654 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2655 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2656 (INTEL_DEVID(dev) & 0xf) == 0xe))
2657 /* ULX machines are also considered ULT. */
2658 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2659 (INTEL_DEVID(dev) & 0xf) == 0xe)
2660 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2661 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2662 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2663 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2664 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2665 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2666 /* ULX machines are also considered ULT. */
2667 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2668 INTEL_DEVID(dev) == 0x0A1E)
2669 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2670 INTEL_DEVID(dev) == 0x1913 || \
2671 INTEL_DEVID(dev) == 0x1916 || \
2672 INTEL_DEVID(dev) == 0x1921 || \
2673 INTEL_DEVID(dev) == 0x1926)
2674 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2675 INTEL_DEVID(dev) == 0x1915 || \
2676 INTEL_DEVID(dev) == 0x191E)
2677 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2678 INTEL_DEVID(dev) == 0x5913 || \
2679 INTEL_DEVID(dev) == 0x5916 || \
2680 INTEL_DEVID(dev) == 0x5921 || \
2681 INTEL_DEVID(dev) == 0x5926)
2682 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2683 INTEL_DEVID(dev) == 0x5915 || \
2684 INTEL_DEVID(dev) == 0x591E)
2685 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2686 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2687 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2688 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2690 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2692 #define SKL_REVID_A0 0x0
2693 #define SKL_REVID_B0 0x1
2694 #define SKL_REVID_C0 0x2
2695 #define SKL_REVID_D0 0x3
2696 #define SKL_REVID_E0 0x4
2697 #define SKL_REVID_F0 0x5
2698 #define SKL_REVID_G0 0x6
2699 #define SKL_REVID_H0 0x7
2701 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2703 #define BXT_REVID_A0 0x0
2704 #define BXT_REVID_A1 0x1
2705 #define BXT_REVID_B0 0x3
2706 #define BXT_REVID_C0 0x9
2708 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2710 #define KBL_REVID_A0 0x0
2711 #define KBL_REVID_B0 0x1
2712 #define KBL_REVID_C0 0x2
2713 #define KBL_REVID_D0 0x3
2714 #define KBL_REVID_E0 0x4
2716 #define IS_KBL_REVID(p, since, until) \
2717 (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2720 * The genX designation typically refers to the render engine, so render
2721 * capability related checks should use IS_GEN, while display and other checks
2722 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2725 #define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
2726 #define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
2727 #define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
2728 #define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
2729 #define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
2730 #define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
2731 #define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
2732 #define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
2734 #define ENGINE_MASK(id) BIT(id)
2735 #define RENDER_RING ENGINE_MASK(RCS)
2736 #define BSD_RING ENGINE_MASK(VCS)
2737 #define BLT_RING ENGINE_MASK(BCS)
2738 #define VEBOX_RING ENGINE_MASK(VECS)
2739 #define BSD2_RING ENGINE_MASK(VCS2)
2740 #define ALL_ENGINES (~0)
2742 #define HAS_ENGINE(dev_priv, id) \
2743 (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2745 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2746 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2747 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2748 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2750 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2751 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2752 #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2753 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2755 #define HWS_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->hws_needs_physical)
2757 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts)
2758 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->has_logical_ring_contexts)
2759 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2760 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2761 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2763 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2764 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2766 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2767 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2769 /* WaRsDisableCoarsePowerGating:skl,bxt */
2770 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2771 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2772 IS_SKL_GT3(dev_priv) || \
2773 IS_SKL_GT4(dev_priv))
2776 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2777 * even when in MSI mode. This results in spurious interrupt warnings if the
2778 * legacy irq no. is shared with another device. The kernel then disables that
2779 * interrupt source and so prevents the other device from working properly.
2781 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2782 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq)
2784 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2785 * rows, which changed the alignment requirements and fence programming.
2787 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2789 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2790 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2792 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2793 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2794 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2796 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2798 #define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst)
2800 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2801 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2802 #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
2803 #define HAS_RUNTIME_PM(dev) (INTEL_INFO(dev)->has_runtime_pm)
2804 #define HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
2805 #define HAS_RC6p(dev) (INTEL_INFO(dev)->has_rc6p)
2807 #define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr)
2810 * For now, anything with a GuC requires uCode loading, and then supports
2811 * command submission once loaded. But these are logically independent
2812 * properties, so we have separate macros to test them.
2814 #define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc)
2815 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2816 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2818 #define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
2820 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2822 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2823 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2824 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2825 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2826 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2827 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2828 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2829 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2830 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2831 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2832 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2833 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2835 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2836 #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2837 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2838 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2839 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2840 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2841 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2842 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2843 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2844 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2846 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
2848 /* DPF == dynamic parity feature */
2849 #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
2850 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2852 #define GT_FREQUENCY_MULTIPLIER 50
2853 #define GEN9_FREQ_SCALER 3
2855 #include "i915_trace.h"
2857 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2859 #ifdef CONFIG_INTEL_IOMMU
2860 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2866 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2867 extern int i915_resume_switcheroo(struct drm_device *dev);
2869 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2872 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2876 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2877 const char *fmt, ...);
2879 #define i915_report_error(dev_priv, fmt, ...) \
2880 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2882 #ifdef CONFIG_COMPAT
2883 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2886 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2887 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2888 extern void i915_reset(struct drm_i915_private *dev_priv);
2889 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2890 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2891 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2892 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2893 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2894 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2895 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2897 /* intel_hotplug.c */
2898 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2899 u32 pin_mask, u32 long_mask);
2900 void intel_hpd_init(struct drm_i915_private *dev_priv);
2901 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2902 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2903 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2904 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2905 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2908 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2910 unsigned long delay;
2912 if (unlikely(!i915.enable_hangcheck))
2915 /* Don't continually defer the hangcheck so that it is always run at
2916 * least once after work has been scheduled on any ring. Otherwise,
2917 * we will ignore a hung ring if a second ring is kept busy.
2920 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2921 queue_delayed_work(system_long_wq,
2922 &dev_priv->gpu_error.hangcheck_work, delay);
2926 void i915_handle_error(struct drm_i915_private *dev_priv,
2928 const char *fmt, ...);
2930 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2931 int intel_irq_install(struct drm_i915_private *dev_priv);
2932 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2934 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
2935 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2936 bool restore_forcewake);
2937 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2938 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2939 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2940 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
2941 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
2943 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2944 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2945 enum forcewake_domains domains);
2946 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2947 enum forcewake_domains domains);
2948 /* Like above but the caller must manage the uncore.lock itself.
2949 * Must be used with I915_READ_FW and friends.
2951 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2952 enum forcewake_domains domains);
2953 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2954 enum forcewake_domains domains);
2955 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
2957 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2959 int intel_wait_for_register(struct drm_i915_private *dev_priv,
2963 const unsigned long timeout_ms);
2964 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
2968 const unsigned long timeout_ms);
2970 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2972 return dev_priv->gvt.initialized;
2975 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2977 return dev_priv->vgpu.active;
2981 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2985 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2988 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2989 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2990 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2993 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2994 uint32_t interrupt_mask,
2995 uint32_t enabled_irq_mask);
2997 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2999 ilk_update_display_irq(dev_priv, bits, bits);
3002 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3004 ilk_update_display_irq(dev_priv, bits, 0);
3006 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3008 uint32_t interrupt_mask,
3009 uint32_t enabled_irq_mask);
3010 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3011 enum pipe pipe, uint32_t bits)
3013 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3015 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3016 enum pipe pipe, uint32_t bits)
3018 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3020 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3021 uint32_t interrupt_mask,
3022 uint32_t enabled_irq_mask);
3024 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3026 ibx_display_interrupt_update(dev_priv, bits, bits);
3029 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3031 ibx_display_interrupt_update(dev_priv, bits, 0);
3035 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3036 struct drm_file *file_priv);
3037 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3038 struct drm_file *file_priv);
3039 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3040 struct drm_file *file_priv);
3041 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3042 struct drm_file *file_priv);
3043 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3044 struct drm_file *file_priv);
3045 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3046 struct drm_file *file_priv);
3047 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3048 struct drm_file *file_priv);
3049 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3050 struct drm_file *file_priv);
3051 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3052 struct drm_file *file_priv);
3053 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3054 struct drm_file *file_priv);
3055 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3056 struct drm_file *file);
3057 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3058 struct drm_file *file);
3059 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3060 struct drm_file *file_priv);
3061 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3062 struct drm_file *file_priv);
3063 int i915_gem_set_tiling(struct drm_device *dev, void *data,
3064 struct drm_file *file_priv);
3065 int i915_gem_get_tiling(struct drm_device *dev, void *data,
3066 struct drm_file *file_priv);
3067 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3068 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3069 struct drm_file *file);
3070 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3071 struct drm_file *file_priv);
3072 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3073 struct drm_file *file_priv);
3074 void i915_gem_load_init(struct drm_device *dev);
3075 void i915_gem_load_cleanup(struct drm_device *dev);
3076 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3077 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3078 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3080 void *i915_gem_object_alloc(struct drm_device *dev);
3081 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3082 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3083 const struct drm_i915_gem_object_ops *ops);
3084 struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
3086 struct drm_i915_gem_object *i915_gem_object_create_from_data(
3087 struct drm_device *dev, const void *data, size_t size);
3088 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3089 void i915_gem_free_object(struct drm_gem_object *obj);
3091 struct i915_vma * __must_check
3092 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3093 const struct i915_ggtt_view *view,
3098 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3100 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
3101 int __must_check i915_vma_unbind(struct i915_vma *vma);
3102 void i915_vma_close(struct i915_vma *vma);
3103 void i915_vma_destroy(struct i915_vma *vma);
3105 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3106 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
3107 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
3108 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3110 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3112 static inline int __sg_page_count(struct scatterlist *sg)
3114 return sg->length >> PAGE_SHIFT;
3118 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
3120 static inline dma_addr_t
3121 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n)
3123 if (n < obj->get_page.last) {
3124 obj->get_page.sg = obj->pages->sgl;
3125 obj->get_page.last = 0;
3128 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3129 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3130 if (unlikely(sg_is_chain(obj->get_page.sg)))
3131 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3134 return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT);
3137 static inline struct page *
3138 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3140 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
3143 if (n < obj->get_page.last) {
3144 obj->get_page.sg = obj->pages->sgl;
3145 obj->get_page.last = 0;
3148 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3149 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3150 if (unlikely(sg_is_chain(obj->get_page.sg)))
3151 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3154 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3157 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3159 BUG_ON(obj->pages == NULL);
3160 obj->pages_pin_count++;
3163 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3165 BUG_ON(obj->pages_pin_count == 0);
3166 obj->pages_pin_count--;
3169 enum i915_map_type {
3175 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3176 * @obj - the object to map into kernel address space
3177 * @type - the type of mapping, used to select pgprot_t
3179 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3180 * pages and then returns a contiguous mapping of the backing storage into
3181 * the kernel address space. Based on the @type of mapping, the PTE will be
3182 * set to either WriteBack or WriteCombine (via pgprot_t).
3184 * The caller must hold the struct_mutex, and is responsible for calling
3185 * i915_gem_object_unpin_map() when the mapping is no longer required.
3187 * Returns the pointer through which to access the mapped object, or an
3188 * ERR_PTR() on error.
3190 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3191 enum i915_map_type type);
3194 * i915_gem_object_unpin_map - releases an earlier mapping
3195 * @obj - the object to unmap
3197 * After pinning the object and mapping its pages, once you are finished
3198 * with your access, call i915_gem_object_unpin_map() to release the pin
3199 * upon the mapping. Once the pin count reaches zero, that mapping may be
3202 * The caller must hold the struct_mutex.
3204 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3206 lockdep_assert_held(&obj->base.dev->struct_mutex);
3207 i915_gem_object_unpin_pages(obj);
3210 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3211 unsigned int *needs_clflush);
3212 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3213 unsigned int *needs_clflush);
3214 #define CLFLUSH_BEFORE 0x1
3215 #define CLFLUSH_AFTER 0x2
3216 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3219 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3221 i915_gem_object_unpin_pages(obj);
3224 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3225 void i915_vma_move_to_active(struct i915_vma *vma,
3226 struct drm_i915_gem_request *req,
3227 unsigned int flags);
3228 int i915_gem_dumb_create(struct drm_file *file_priv,
3229 struct drm_device *dev,
3230 struct drm_mode_create_dumb *args);
3231 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3232 uint32_t handle, uint64_t *offset);
3233 int i915_gem_mmap_gtt_version(void);
3235 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3236 struct drm_i915_gem_object *new,
3237 unsigned frontbuffer_bits);
3239 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3241 struct drm_i915_gem_request *
3242 i915_gem_find_active_request(struct intel_engine_cs *engine);
3244 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3246 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3248 return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3251 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3253 return unlikely(test_bit(I915_WEDGED, &error->flags));
3256 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3258 return i915_reset_in_progress(error) | i915_terminally_wedged(error);
3261 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3263 return READ_ONCE(error->reset_count);
3266 void i915_gem_reset(struct drm_i915_private *dev_priv);
3267 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3268 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3269 int __must_check i915_gem_init(struct drm_device *dev);
3270 int __must_check i915_gem_init_hw(struct drm_device *dev);
3271 void i915_gem_init_swizzling(struct drm_device *dev);
3272 void i915_gem_cleanup_engines(struct drm_device *dev);
3273 int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3274 unsigned int flags);
3275 int __must_check i915_gem_suspend(struct drm_device *dev);
3276 void i915_gem_resume(struct drm_device *dev);
3277 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3279 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3282 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3285 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3286 struct i915_vma * __must_check
3287 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3289 const struct i915_ggtt_view *view);
3290 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3291 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3293 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3294 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3296 u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
3298 u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
3299 int tiling_mode, bool fenced);
3301 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3302 enum i915_cache_level cache_level);
3304 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3305 struct dma_buf *dma_buf);
3307 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3308 struct drm_gem_object *gem_obj, int flags);
3311 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3312 struct i915_address_space *vm,
3313 const struct i915_ggtt_view *view);
3316 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3317 struct i915_address_space *vm,
3318 const struct i915_ggtt_view *view);
3320 static inline struct i915_hw_ppgtt *
3321 i915_vm_to_ppgtt(struct i915_address_space *vm)
3323 return container_of(vm, struct i915_hw_ppgtt, base);
3326 static inline struct i915_vma *
3327 i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj,
3328 const struct i915_ggtt_view *view)
3330 return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view);
3333 static inline unsigned long
3334 i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o,
3335 const struct i915_ggtt_view *view)
3337 return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view));
3340 /* i915_gem_fence.c */
3341 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3342 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3345 * i915_vma_pin_fence - pin fencing state
3346 * @vma: vma to pin fencing for
3348 * This pins the fencing state (whether tiled or untiled) to make sure the
3349 * vma (and its object) is ready to be used as a scanout target. Fencing
3350 * status must be synchronize first by calling i915_vma_get_fence():
3352 * The resulting fence pin reference must be released again with
3353 * i915_vma_unpin_fence().
3357 * True if the vma has a fence, false otherwise.
3360 i915_vma_pin_fence(struct i915_vma *vma)
3363 vma->fence->pin_count++;
3370 * i915_vma_unpin_fence - unpin fencing state
3371 * @vma: vma to unpin fencing for
3373 * This releases the fence pin reference acquired through
3374 * i915_vma_pin_fence. It will handle both objects with and without an
3375 * attached fence correctly, callers do not need to distinguish this.
3378 i915_vma_unpin_fence(struct i915_vma *vma)
3381 GEM_BUG_ON(vma->fence->pin_count <= 0);
3382 vma->fence->pin_count--;
3386 void i915_gem_restore_fences(struct drm_device *dev);
3388 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3389 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3390 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3392 /* i915_gem_context.c */
3393 int __must_check i915_gem_context_init(struct drm_device *dev);
3394 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3395 void i915_gem_context_fini(struct drm_device *dev);
3396 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3397 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3398 int i915_switch_context(struct drm_i915_gem_request *req);
3399 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3400 void i915_gem_context_free(struct kref *ctx_ref);
3401 struct drm_i915_gem_object *
3402 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3403 struct i915_gem_context *
3404 i915_gem_context_create_gvt(struct drm_device *dev);
3406 static inline struct i915_gem_context *
3407 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3409 struct i915_gem_context *ctx;
3411 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3413 ctx = idr_find(&file_priv->context_idr, id);
3415 return ERR_PTR(-ENOENT);
3420 static inline struct i915_gem_context *
3421 i915_gem_context_get(struct i915_gem_context *ctx)
3423 kref_get(&ctx->ref);
3427 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3429 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3430 kref_put(&ctx->ref, i915_gem_context_free);
3433 static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3435 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3438 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3439 struct drm_file *file);
3440 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3441 struct drm_file *file);
3442 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3443 struct drm_file *file_priv);
3444 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3445 struct drm_file *file_priv);
3446 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
3447 struct drm_file *file);
3449 /* i915_gem_evict.c */
3450 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3451 u64 min_size, u64 alignment,
3452 unsigned cache_level,
3455 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3456 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3458 /* belongs in i915_gem_gtt.h */
3459 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3462 if (INTEL_GEN(dev_priv) < 6)
3463 intel_gtt_chipset_flush();
3466 /* i915_gem_stolen.c */
3467 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3468 struct drm_mm_node *node, u64 size,
3469 unsigned alignment);
3470 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3471 struct drm_mm_node *node, u64 size,
3472 unsigned alignment, u64 start,
3474 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3475 struct drm_mm_node *node);
3476 int i915_gem_init_stolen(struct drm_device *dev);
3477 void i915_gem_cleanup_stolen(struct drm_device *dev);
3478 struct drm_i915_gem_object *
3479 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3480 struct drm_i915_gem_object *
3481 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3486 /* i915_gem_shrinker.c */
3487 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3488 unsigned long target,
3490 #define I915_SHRINK_PURGEABLE 0x1
3491 #define I915_SHRINK_UNBOUND 0x2
3492 #define I915_SHRINK_BOUND 0x4
3493 #define I915_SHRINK_ACTIVE 0x8
3494 #define I915_SHRINK_VMAPS 0x10
3495 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3496 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3497 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3500 /* i915_gem_tiling.c */
3501 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3503 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3505 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3506 i915_gem_object_is_tiled(obj);
3509 /* i915_debugfs.c */
3510 #ifdef CONFIG_DEBUG_FS
3511 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3512 void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3513 int i915_debugfs_connector_add(struct drm_connector *connector);
3514 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3516 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3517 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3518 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3520 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3523 /* i915_gpu_error.c */
3525 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3526 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3527 const struct i915_error_state_file_priv *error);
3528 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3529 struct drm_i915_private *i915,
3530 size_t count, loff_t pos);
3531 static inline void i915_error_state_buf_release(
3532 struct drm_i915_error_state_buf *eb)
3536 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3538 const char *error_msg);
3539 void i915_error_state_get(struct drm_device *dev,
3540 struct i915_error_state_file_priv *error_priv);
3541 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3542 void i915_destroy_error_state(struct drm_device *dev);
3544 void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
3545 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3547 /* i915_cmd_parser.c */
3548 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3549 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3550 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3551 bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine);
3552 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3553 struct drm_i915_gem_object *batch_obj,
3554 struct drm_i915_gem_object *shadow_batch_obj,
3555 u32 batch_start_offset,
3559 /* i915_suspend.c */
3560 extern int i915_save_state(struct drm_device *dev);
3561 extern int i915_restore_state(struct drm_device *dev);
3564 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3565 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3568 extern int intel_setup_gmbus(struct drm_device *dev);
3569 extern void intel_teardown_gmbus(struct drm_device *dev);
3570 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3573 extern struct i2c_adapter *
3574 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3575 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3576 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3577 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3579 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3581 extern void intel_i2c_reset(struct drm_device *dev);
3584 int intel_bios_init(struct drm_i915_private *dev_priv);
3585 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3586 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3587 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3588 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3589 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3590 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3591 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3592 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3595 /* intel_opregion.c */
3597 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3598 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3599 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3600 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3601 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3603 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3605 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3607 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3608 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3609 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3610 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3614 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3619 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3623 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3631 extern void intel_register_dsm_handler(void);
3632 extern void intel_unregister_dsm_handler(void);
3634 static inline void intel_register_dsm_handler(void) { return; }
3635 static inline void intel_unregister_dsm_handler(void) { return; }
3636 #endif /* CONFIG_ACPI */
3638 /* intel_device_info.c */
3639 static inline struct intel_device_info *
3640 mkwrite_device_info(struct drm_i915_private *dev_priv)
3642 return (struct intel_device_info *)&dev_priv->info;
3645 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3646 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3649 extern void intel_modeset_init_hw(struct drm_device *dev);
3650 extern void intel_modeset_init(struct drm_device *dev);
3651 extern void intel_modeset_gem_init(struct drm_device *dev);
3652 extern void intel_modeset_cleanup(struct drm_device *dev);
3653 extern int intel_connector_register(struct drm_connector *);
3654 extern void intel_connector_unregister(struct drm_connector *);
3655 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3656 extern void intel_display_resume(struct drm_device *dev);
3657 extern void i915_redisable_vga(struct drm_device *dev);
3658 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3659 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3660 extern void intel_init_pch_refclk(struct drm_device *dev);
3661 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3662 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3665 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3666 struct drm_file *file);
3669 extern struct intel_overlay_error_state *
3670 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3671 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3672 struct intel_overlay_error_state *error);
3674 extern struct intel_display_error_state *
3675 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3676 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3677 struct drm_device *dev,
3678 struct intel_display_error_state *error);
3680 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3681 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3683 /* intel_sideband.c */
3684 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3685 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3686 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3687 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3688 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3689 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3690 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3691 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3692 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3693 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3694 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3695 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3696 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3697 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3698 enum intel_sbi_destination destination);
3699 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3700 enum intel_sbi_destination destination);
3701 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3702 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3704 /* intel_dpio_phy.c */
3705 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3706 u32 deemph_reg_value, u32 margin_reg_value,
3707 bool uniq_trans_scale);
3708 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3710 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3711 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3712 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3713 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3715 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3716 u32 demph_reg_value, u32 preemph_reg_value,
3717 u32 uniqtranscale_reg_value, u32 tx3_demph);
3718 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3719 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3720 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3722 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3723 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3725 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3726 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3728 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3729 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3730 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3731 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3733 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3734 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3735 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3736 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3738 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3739 * will be implemented using 2 32-bit writes in an arbitrary order with
3740 * an arbitrary delay between them. This can cause the hardware to
3741 * act upon the intermediate value, possibly leading to corruption and
3742 * machine death. For this reason we do not support I915_WRITE64, or
3743 * dev_priv->uncore.funcs.mmio_writeq.
3745 * When reading a 64-bit value as two 32-bit values, the delay may cause
3746 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3747 * occasionally a 64-bit register does not actualy support a full readq
3748 * and must be read using two 32-bit reads.
3750 * You have been warned.
3752 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3754 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3755 u32 upper, lower, old_upper, loop = 0; \
3756 upper = I915_READ(upper_reg); \
3758 old_upper = upper; \
3759 lower = I915_READ(lower_reg); \
3760 upper = I915_READ(upper_reg); \
3761 } while (upper != old_upper && loop++ < 2); \
3762 (u64)upper << 32 | lower; })
3764 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3765 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3767 #define __raw_read(x, s) \
3768 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3771 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3774 #define __raw_write(x, s) \
3775 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3776 i915_reg_t reg, uint##x##_t val) \
3778 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3793 /* These are untraced mmio-accessors that are only valid to be used inside
3794 * critical sections inside IRQ handlers where forcewake is explicitly
3796 * Think twice, and think again, before using these.
3797 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3798 * intel_uncore_forcewake_irqunlock().
3800 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3801 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3802 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3803 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3805 /* "Broadcast RGB" property */
3806 #define INTEL_BROADCAST_RGB_AUTO 0
3807 #define INTEL_BROADCAST_RGB_FULL 1
3808 #define INTEL_BROADCAST_RGB_LIMITED 2
3810 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3812 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3813 return VLV_VGACNTRL;
3814 else if (INTEL_INFO(dev)->gen >= 5)
3815 return CPU_VGACNTRL;
3820 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3822 unsigned long j = msecs_to_jiffies(m);
3824 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3827 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3829 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3832 static inline unsigned long
3833 timespec_to_jiffies_timeout(const struct timespec *value)
3835 unsigned long j = timespec_to_jiffies(value);
3837 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3841 * If you need to wait X milliseconds between events A and B, but event B
3842 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3843 * when event A happened, then just before event B you call this function and
3844 * pass the timestamp as the first argument, and X as the second argument.
3847 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3849 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3852 * Don't re-read the value of "jiffies" every time since it may change
3853 * behind our back and break the math.
3855 tmp_jiffies = jiffies;
3856 target_jiffies = timestamp_jiffies +
3857 msecs_to_jiffies_timeout(to_wait_ms);
3859 if (time_after(target_jiffies, tmp_jiffies)) {
3860 remaining_jiffies = target_jiffies - tmp_jiffies;
3861 while (remaining_jiffies)
3863 schedule_timeout_uninterruptible(remaining_jiffies);
3868 __i915_request_irq_complete(struct drm_i915_gem_request *req)
3870 struct intel_engine_cs *engine = req->engine;
3872 /* Before we do the heavier coherent read of the seqno,
3873 * check the value (hopefully) in the CPU cacheline.
3875 if (i915_gem_request_completed(req))
3878 /* Ensure our read of the seqno is coherent so that we
3879 * do not "miss an interrupt" (i.e. if this is the last
3880 * request and the seqno write from the GPU is not visible
3881 * by the time the interrupt fires, we will see that the
3882 * request is incomplete and go back to sleep awaiting
3883 * another interrupt that will never come.)
3885 * Strictly, we only need to do this once after an interrupt,
3886 * but it is easier and safer to do it every time the waiter
3889 if (engine->irq_seqno_barrier &&
3890 rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
3891 cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
3892 struct task_struct *tsk;
3894 /* The ordering of irq_posted versus applying the barrier
3895 * is crucial. The clearing of the current irq_posted must
3896 * be visible before we perform the barrier operation,
3897 * such that if a subsequent interrupt arrives, irq_posted
3898 * is reasserted and our task rewoken (which causes us to
3899 * do another __i915_request_irq_complete() immediately
3900 * and reapply the barrier). Conversely, if the clear
3901 * occurs after the barrier, then an interrupt that arrived
3902 * whilst we waited on the barrier would not trigger a
3903 * barrier on the next pass, and the read may not see the
3906 engine->irq_seqno_barrier(engine);
3908 /* If we consume the irq, but we are no longer the bottom-half,
3909 * the real bottom-half may not have serialised their own
3910 * seqno check with the irq-barrier (i.e. may have inspected
3911 * the seqno before we believe it coherent since they see
3912 * irq_posted == false but we are still running).
3915 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
3916 if (tsk && tsk != current)
3917 /* Note that if the bottom-half is changed as we
3918 * are sending the wake-up, the new bottom-half will
3919 * be woken by whomever made the change. We only have
3920 * to worry about when we steal the irq-posted for
3923 wake_up_process(tsk);
3926 if (i915_gem_request_completed(req))
3933 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3934 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3937 int remap_io_mapping(struct vm_area_struct *vma,
3938 unsigned long addr, unsigned long pfn, unsigned long size,
3939 struct io_mapping *iomap);
3941 #define ptr_mask_bits(ptr) ({ \
3942 unsigned long __v = (unsigned long)(ptr); \
3943 (typeof(ptr))(__v & PAGE_MASK); \
3946 #define ptr_unpack_bits(ptr, bits) ({ \
3947 unsigned long __v = (unsigned long)(ptr); \
3948 (bits) = __v & ~PAGE_MASK; \
3949 (typeof(ptr))(__v & PAGE_MASK); \
3952 #define ptr_pack_bits(ptr, bits) \
3953 ((typeof(ptr))((unsigned long)(ptr) | (bits)))
3955 #define fetch_and_zero(ptr) ({ \
3956 typeof(*ptr) __T = *(ptr); \
3957 *(ptr) = (typeof(*ptr))0; \