1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <drm/drm_auth.h>
52 #include "i915_params.h"
55 #include "intel_bios.h"
56 #include "intel_dpll_mgr.h"
57 #include "intel_guc.h"
58 #include "intel_lrc.h"
59 #include "intel_ringbuffer.h"
62 #include "i915_gem_gtt.h"
63 #include "i915_gem_render_state.h"
64 #include "i915_gem_request.h"
66 #include "intel_gvt.h"
68 /* General customization:
71 #define DRIVER_NAME "i915"
72 #define DRIVER_DESC "Intel Graphics"
73 #define DRIVER_DATE "20161024"
74 #define DRIVER_TIMESTAMP 1477290335
77 /* Many gcc seem to no see through this and fall over :( */
79 #define WARN_ON(x) ({ \
80 bool __i915_warn_cond = (x); \
81 if (__builtin_constant_p(__i915_warn_cond)) \
82 BUILD_BUG_ON(__i915_warn_cond); \
83 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
85 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
89 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
91 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
92 (long) (x), __func__);
94 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
95 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
96 * which may not necessarily be a user visible problem. This will either
97 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
98 * enable distros and users to tailor their preferred amount of i915 abrt
101 #define I915_STATE_WARN(condition, format...) ({ \
102 int __ret_warn_on = !!(condition); \
103 if (unlikely(__ret_warn_on)) \
104 if (!WARN(i915.verbose_state_checks, format)) \
106 unlikely(__ret_warn_on); \
109 #define I915_STATE_WARN_ON(x) \
110 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
112 bool __i915_inject_load_failure(const char *func, int line);
113 #define i915_inject_load_failure() \
114 __i915_inject_load_failure(__func__, __LINE__)
116 static inline const char *yesno(bool v)
118 return v ? "yes" : "no";
121 static inline const char *onoff(bool v)
123 return v ? "on" : "off";
132 I915_MAX_PIPES = _PIPE_EDP
134 #define pipe_name(p) ((p) + 'A')
146 static inline const char *transcoder_name(enum transcoder transcoder)
148 switch (transcoder) {
157 case TRANSCODER_DSI_A:
159 case TRANSCODER_DSI_C:
166 static inline bool transcoder_is_dsi(enum transcoder transcoder)
168 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
172 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
173 * number of planes per CRTC. Not all platforms really have this many planes,
174 * which means some arrays of size I915_MAX_PLANES may have unused entries
175 * between the topmost sprite plane and the cursor plane.
184 #define plane_name(p) ((p) + 'A')
186 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
197 #define port_name(p) ((p) + 'A')
199 #define I915_NUM_PHYS_VLV 2
211 enum intel_display_power_domain {
215 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
216 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
217 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
218 POWER_DOMAIN_TRANSCODER_A,
219 POWER_DOMAIN_TRANSCODER_B,
220 POWER_DOMAIN_TRANSCODER_C,
221 POWER_DOMAIN_TRANSCODER_EDP,
222 POWER_DOMAIN_TRANSCODER_DSI_A,
223 POWER_DOMAIN_TRANSCODER_DSI_C,
224 POWER_DOMAIN_PORT_DDI_A_LANES,
225 POWER_DOMAIN_PORT_DDI_B_LANES,
226 POWER_DOMAIN_PORT_DDI_C_LANES,
227 POWER_DOMAIN_PORT_DDI_D_LANES,
228 POWER_DOMAIN_PORT_DDI_E_LANES,
229 POWER_DOMAIN_PORT_DSI,
230 POWER_DOMAIN_PORT_CRT,
231 POWER_DOMAIN_PORT_OTHER,
240 POWER_DOMAIN_MODESET,
246 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
247 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
248 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
249 #define POWER_DOMAIN_TRANSCODER(tran) \
250 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
251 (tran) + POWER_DOMAIN_TRANSCODER_A)
255 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
267 #define for_each_hpd_pin(__pin) \
268 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
270 struct i915_hotplug {
271 struct work_struct hotplug_work;
274 unsigned long last_jiffies;
279 HPD_MARK_DISABLED = 2
281 } stats[HPD_NUM_PINS];
283 struct delayed_work reenable_work;
285 struct intel_digital_port *irq_port[I915_MAX_PORTS];
288 struct work_struct dig_port_work;
290 struct work_struct poll_init_work;
294 * if we get a HPD irq from DP and a HPD irq from non-DP
295 * the non-DP HPD could block the workqueue on a mode config
296 * mutex getting, that userspace may have taken. However
297 * userspace is waiting on the DP workqueue to run which is
298 * blocked behind the non-DP one.
300 struct workqueue_struct *dp_wq;
303 #define I915_GEM_GPU_DOMAINS \
304 (I915_GEM_DOMAIN_RENDER | \
305 I915_GEM_DOMAIN_SAMPLER | \
306 I915_GEM_DOMAIN_COMMAND | \
307 I915_GEM_DOMAIN_INSTRUCTION | \
308 I915_GEM_DOMAIN_VERTEX)
310 #define for_each_pipe(__dev_priv, __p) \
311 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
312 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
313 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
314 for_each_if ((__mask) & (1 << (__p)))
315 #define for_each_plane(__dev_priv, __pipe, __p) \
317 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
319 #define for_each_sprite(__dev_priv, __p, __s) \
321 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
324 #define for_each_port_masked(__port, __ports_mask) \
325 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
326 for_each_if ((__ports_mask) & (1 << (__port)))
328 #define for_each_crtc(dev, crtc) \
329 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
331 #define for_each_intel_plane(dev, intel_plane) \
332 list_for_each_entry(intel_plane, \
333 &(dev)->mode_config.plane_list, \
336 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
337 list_for_each_entry(intel_plane, \
338 &(dev)->mode_config.plane_list, \
340 for_each_if ((plane_mask) & \
341 (1 << drm_plane_index(&intel_plane->base)))
343 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
344 list_for_each_entry(intel_plane, \
345 &(dev)->mode_config.plane_list, \
347 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
349 #define for_each_intel_crtc(dev, intel_crtc) \
350 list_for_each_entry(intel_crtc, \
351 &(dev)->mode_config.crtc_list, \
354 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
355 list_for_each_entry(intel_crtc, \
356 &(dev)->mode_config.crtc_list, \
358 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
360 #define for_each_intel_encoder(dev, intel_encoder) \
361 list_for_each_entry(intel_encoder, \
362 &(dev)->mode_config.encoder_list, \
365 #define for_each_intel_connector(dev, intel_connector) \
366 list_for_each_entry(intel_connector, \
367 &(dev)->mode_config.connector_list, \
370 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
371 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
372 for_each_if ((intel_encoder)->base.crtc == (__crtc))
374 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
375 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
376 for_each_if ((intel_connector)->base.encoder == (__encoder))
378 #define for_each_power_domain(domain, mask) \
379 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
380 for_each_if ((1 << (domain)) & (mask))
382 struct drm_i915_private;
383 struct i915_mm_struct;
384 struct i915_mmu_object;
386 struct drm_i915_file_private {
387 struct drm_i915_private *dev_priv;
388 struct drm_file *file;
392 struct list_head request_list;
393 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
394 * chosen to prevent the CPU getting more than a frame ahead of the GPU
395 * (when using lax throttling for the frontbuffer). We also use it to
396 * offer free GPU waitboosts for severely congested workloads.
398 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
400 struct idr context_idr;
402 struct intel_rps_client {
403 struct list_head link;
407 unsigned int bsd_engine;
410 /* Used by dp and fdi links */
411 struct intel_link_m_n {
419 void intel_link_compute_m_n(int bpp, int nlanes,
420 int pixel_clock, int link_clock,
421 struct intel_link_m_n *m_n);
423 /* Interface history:
426 * 1.2: Add Power Management
427 * 1.3: Add vblank support
428 * 1.4: Fix cmdbuffer path, add heap destroy
429 * 1.5: Add vblank pipe configuration
430 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
431 * - Support vertical blank on secondary display pipe
433 #define DRIVER_MAJOR 1
434 #define DRIVER_MINOR 6
435 #define DRIVER_PATCHLEVEL 0
437 struct opregion_header;
438 struct opregion_acpi;
439 struct opregion_swsci;
440 struct opregion_asle;
442 struct intel_opregion {
443 struct opregion_header *header;
444 struct opregion_acpi *acpi;
445 struct opregion_swsci *swsci;
446 u32 swsci_gbda_sub_functions;
447 u32 swsci_sbcb_sub_functions;
448 struct opregion_asle *asle;
453 struct work_struct asle_work;
455 #define OPREGION_SIZE (8*1024)
457 struct intel_overlay;
458 struct intel_overlay_error_state;
460 struct drm_i915_fence_reg {
461 struct list_head link;
462 struct drm_i915_private *i915;
463 struct i915_vma *vma;
467 * Whether the tiling parameters for the currently
468 * associated fence register have changed. Note that
469 * for the purposes of tracking tiling changes we also
470 * treat the unfenced register, the register slot that
471 * the object occupies whilst it executes a fenced
472 * command (such as BLT on gen2/3), as a "fence".
477 struct sdvo_device_mapping {
486 struct intel_connector;
487 struct intel_encoder;
488 struct intel_crtc_state;
489 struct intel_initial_plane_config;
494 struct drm_i915_display_funcs {
495 int (*get_display_clock_speed)(struct drm_device *dev);
496 int (*get_fifo_size)(struct drm_device *dev, int plane);
497 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
498 int (*compute_intermediate_wm)(struct drm_device *dev,
499 struct intel_crtc *intel_crtc,
500 struct intel_crtc_state *newstate);
501 void (*initial_watermarks)(struct intel_crtc_state *cstate);
502 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
503 int (*compute_global_watermarks)(struct drm_atomic_state *state);
504 void (*update_wm)(struct drm_crtc *crtc);
505 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
506 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
507 /* Returns the active state of the crtc, and if the crtc is active,
508 * fills out the pipe-config with the hw state. */
509 bool (*get_pipe_config)(struct intel_crtc *,
510 struct intel_crtc_state *);
511 void (*get_initial_plane_config)(struct intel_crtc *,
512 struct intel_initial_plane_config *);
513 int (*crtc_compute_clock)(struct intel_crtc *crtc,
514 struct intel_crtc_state *crtc_state);
515 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
516 struct drm_atomic_state *old_state);
517 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
518 struct drm_atomic_state *old_state);
519 void (*update_crtcs)(struct drm_atomic_state *state,
520 unsigned int *crtc_vblank_mask);
521 void (*audio_codec_enable)(struct drm_connector *connector,
522 struct intel_encoder *encoder,
523 const struct drm_display_mode *adjusted_mode);
524 void (*audio_codec_disable)(struct intel_encoder *encoder);
525 void (*fdi_link_train)(struct drm_crtc *crtc);
526 void (*init_clock_gating)(struct drm_device *dev);
527 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
528 struct drm_framebuffer *fb,
529 struct drm_i915_gem_object *obj,
530 struct drm_i915_gem_request *req,
532 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
533 /* clock updates for mode set */
535 /* render clock increase/decrease */
536 /* display clock increase/decrease */
537 /* pll clock increase/decrease */
539 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
540 void (*load_luts)(struct drm_crtc_state *crtc_state);
543 enum forcewake_domain_id {
544 FW_DOMAIN_ID_RENDER = 0,
545 FW_DOMAIN_ID_BLITTER,
551 enum forcewake_domains {
552 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
553 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
554 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
555 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
560 #define FW_REG_READ (1)
561 #define FW_REG_WRITE (2)
563 enum forcewake_domains
564 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
565 i915_reg_t reg, unsigned int op);
567 struct intel_uncore_funcs {
568 void (*force_wake_get)(struct drm_i915_private *dev_priv,
569 enum forcewake_domains domains);
570 void (*force_wake_put)(struct drm_i915_private *dev_priv,
571 enum forcewake_domains domains);
573 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
574 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
575 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
576 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
578 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
579 uint8_t val, bool trace);
580 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
581 uint16_t val, bool trace);
582 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
583 uint32_t val, bool trace);
586 struct intel_forcewake_range {
590 enum forcewake_domains domains;
593 struct intel_uncore {
594 spinlock_t lock; /** lock is also taken in irq contexts. */
596 const struct intel_forcewake_range *fw_domains_table;
597 unsigned int fw_domains_table_entries;
599 struct intel_uncore_funcs funcs;
603 enum forcewake_domains fw_domains;
604 enum forcewake_domains fw_domains_active;
606 struct intel_uncore_forcewake_domain {
607 struct drm_i915_private *i915;
608 enum forcewake_domain_id id;
609 enum forcewake_domains mask;
611 struct hrtimer timer;
618 } fw_domain[FW_DOMAIN_ID_COUNT];
620 int unclaimed_mmio_check;
623 /* Iterate over initialised fw domains */
624 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
625 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
626 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
628 for_each_if ((mask__) & (domain__)->mask)
630 #define for_each_fw_domain(domain__, dev_priv__) \
631 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
633 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
634 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
635 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
638 struct work_struct work;
640 uint32_t *dmc_payload;
641 uint32_t dmc_fw_size;
644 i915_reg_t mmioaddr[8];
645 uint32_t mmiodata[8];
647 uint32_t allowed_dc_mask;
650 #define DEV_INFO_FOR_EACH_FLAG(func) \
651 /* Keep is_* in chronological order */ \
659 func(is_broadwater); \
660 func(is_crestline); \
661 func(is_ivybridge); \
662 func(is_valleyview); \
663 func(is_cherryview); \
665 func(is_broadwell); \
669 func(is_preliminary); \
670 /* Keep has_* in alphabetical order */ \
675 func(has_fpga_dbg); \
676 func(has_gmbus_irq); \
677 func(has_gmch_display); \
680 func(has_hw_contexts); \
683 func(has_logical_ring_contexts); \
685 func(has_pipe_cxsr); \
686 func(has_pooled_eu); \
690 func(has_resource_streamer); \
691 func(has_runtime_pm); \
693 func(cursor_needs_physical); \
694 func(hws_needs_physical); \
695 func(overlay_needs_physical); \
698 struct sseu_dev_info {
704 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
707 u8 has_subslice_pg:1;
711 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
713 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
716 struct intel_device_info {
717 u32 display_mmio_offset;
720 u8 num_sprites[I915_MAX_PIPES];
723 u8 ring_mask; /* Rings supported by the HW */
725 #define DEFINE_FLAG(name) u8 name:1
726 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
728 u16 ddb_size; /* in blocks */
729 /* Register offsets for the various display pipes and transcoders */
730 int pipe_offsets[I915_MAX_TRANSCODERS];
731 int trans_offsets[I915_MAX_TRANSCODERS];
732 int palette_offsets[I915_MAX_PIPES];
733 int cursor_offsets[I915_MAX_PIPES];
735 /* Slice/subslice/EU info */
736 struct sseu_dev_info sseu;
739 u16 degamma_lut_size;
744 struct intel_display_error_state;
746 struct drm_i915_error_state {
750 struct drm_i915_private *i915;
757 struct intel_device_info device_info;
759 /* Generic register state */
767 u32 error; /* gen6+ */
768 u32 err_int; /* gen7 */
769 u32 fault_data0; /* gen8, gen9 */
770 u32 fault_data1; /* gen8, gen9 */
777 u64 fence[I915_MAX_NUM_FENCES];
778 struct intel_overlay_error_state *overlay;
779 struct intel_display_error_state *display;
780 struct drm_i915_error_object *semaphore;
782 struct drm_i915_error_engine {
784 /* Software tracked state */
788 enum intel_engine_hangcheck_action hangcheck_action;
789 struct i915_address_space *vm;
792 /* position of active request inside the ring */
793 u32 rq_head, rq_post, rq_tail;
795 /* our own tracking of ring head and tail */
800 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
819 u32 rc_psmi; /* sleep state */
820 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
821 struct intel_instdone instdone;
823 struct drm_i915_error_object {
829 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
831 struct drm_i915_error_object *wa_ctx;
833 struct drm_i915_error_request {
840 } *requests, execlist[2];
842 struct drm_i915_error_waiter {
843 char comm[TASK_COMM_LEN];
857 char comm[TASK_COMM_LEN];
858 } engine[I915_NUM_ENGINES];
860 struct drm_i915_error_buffer {
863 u32 rseqno[I915_NUM_ENGINES], wseqno;
867 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
874 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
875 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
876 struct i915_address_space *active_vm[I915_NUM_ENGINES];
879 enum i915_cache_level {
881 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
882 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
883 caches, eg sampler/render caches, and the
884 large Last-Level-Cache. LLC is coherent with
885 the CPU, but L3 is only visible to the GPU. */
886 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
889 struct i915_ctx_hang_stats {
890 /* This context had batch pending when hang was declared */
891 unsigned batch_pending;
893 /* This context had batch active when hang was declared */
894 unsigned batch_active;
896 /* Time when this context was last blamed for a GPU reset */
897 unsigned long guilty_ts;
899 /* If the contexts causes a second GPU hang within this time,
900 * it is permanently banned from submitting any more work.
902 unsigned long ban_period_seconds;
904 /* This context is banned to submit more work */
908 /* This must match up with the value previously used for execbuf2.rsvd1. */
909 #define DEFAULT_CONTEXT_HANDLE 0
912 * struct i915_gem_context - as the name implies, represents a context.
913 * @ref: reference count.
914 * @user_handle: userspace tracking identity for this context.
915 * @remap_slice: l3 row remapping information.
916 * @flags: context specific flags:
917 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
918 * @file_priv: filp associated with this context (NULL for global default
920 * @hang_stats: information about the role of this context in possible GPU
922 * @ppgtt: virtual memory space used by this context.
923 * @legacy_hw_ctx: render context backing object and whether it is correctly
924 * initialized (legacy ring submission mechanism only).
925 * @link: link in the global list of contexts.
927 * Contexts are memory images used by the hardware to store copies of their
930 struct i915_gem_context {
932 struct drm_i915_private *i915;
933 struct drm_i915_file_private *file_priv;
934 struct i915_hw_ppgtt *ppgtt;
937 struct i915_ctx_hang_stats hang_stats;
940 #define CONTEXT_NO_ZEROMAP BIT(0)
941 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
943 /* Unique identifier for this context, used by the hw for tracking */
949 struct intel_context {
950 struct i915_vma *state;
951 struct intel_ring *ring;
952 uint32_t *lrc_reg_state;
956 } engine[I915_NUM_ENGINES];
959 struct atomic_notifier_head status_notifier;
960 bool execlists_force_single_submission;
962 struct list_head link;
977 /* This is always the inner lock when overlapping with struct_mutex and
978 * it's the outer lock when overlapping with stolen_lock. */
981 unsigned int possible_framebuffer_bits;
982 unsigned int busy_bits;
983 unsigned int visible_pipes_mask;
984 struct intel_crtc *crtc;
986 struct drm_mm_node compressed_fb;
987 struct drm_mm_node *compressed_llb;
994 bool underrun_detected;
995 struct work_struct underrun_work;
997 struct intel_fbc_state_cache {
999 unsigned int mode_flags;
1000 uint32_t hsw_bdw_pixel_rate;
1004 unsigned int rotation;
1011 u64 ilk_ggtt_offset;
1012 uint32_t pixel_format;
1013 unsigned int stride;
1015 unsigned int tiling_mode;
1019 struct intel_fbc_reg_params {
1023 unsigned int fence_y_offset;
1028 uint32_t pixel_format;
1029 unsigned int stride;
1036 struct intel_fbc_work {
1038 u32 scheduled_vblank;
1039 struct work_struct work;
1042 const char *no_fbc_reason;
1046 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1047 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1048 * parsing for same resolution.
1050 enum drrs_refresh_rate_type {
1053 DRRS_MAX_RR, /* RR count */
1056 enum drrs_support_type {
1057 DRRS_NOT_SUPPORTED = 0,
1058 STATIC_DRRS_SUPPORT = 1,
1059 SEAMLESS_DRRS_SUPPORT = 2
1065 struct delayed_work work;
1066 struct intel_dp *dp;
1067 unsigned busy_frontbuffer_bits;
1068 enum drrs_refresh_rate_type refresh_rate_type;
1069 enum drrs_support_type type;
1076 struct intel_dp *enabled;
1078 struct delayed_work work;
1079 unsigned busy_frontbuffer_bits;
1081 bool aux_frame_sync;
1086 PCH_NONE = 0, /* No PCH present */
1087 PCH_IBX, /* Ibexpeak PCH */
1088 PCH_CPT, /* Cougarpoint PCH */
1089 PCH_LPT, /* Lynxpoint PCH */
1090 PCH_SPT, /* Sunrisepoint PCH */
1091 PCH_KBP, /* Kabypoint PCH */
1095 enum intel_sbi_destination {
1100 #define QUIRK_PIPEA_FORCE (1<<0)
1101 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1102 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1103 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1104 #define QUIRK_PIPEB_FORCE (1<<4)
1105 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1108 struct intel_fbc_work;
1110 struct intel_gmbus {
1111 struct i2c_adapter adapter;
1112 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1115 i915_reg_t gpio_reg;
1116 struct i2c_algo_bit_data bit_algo;
1117 struct drm_i915_private *dev_priv;
1120 struct i915_suspend_saved_registers {
1122 u32 saveFBC_CONTROL;
1123 u32 saveCACHE_MODE_0;
1124 u32 saveMI_ARB_STATE;
1128 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1129 u32 savePCH_PORT_HOTPLUG;
1133 struct vlv_s0ix_state {
1140 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1141 u32 media_max_req_count;
1142 u32 gfx_max_req_count;
1168 u32 rp_down_timeout;
1174 /* Display 1 CZ domain */
1179 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1181 /* GT SA CZ domain */
1188 /* Display 2 CZ domain */
1192 u32 clock_gate_dis2;
1195 struct intel_rps_ei {
1201 struct intel_gen6_power_mgmt {
1203 * work, interrupts_enabled and pm_iir are protected by
1204 * dev_priv->irq_lock
1206 struct work_struct work;
1207 bool interrupts_enabled;
1210 /* PM interrupt bits that should never be masked */
1213 /* Frequencies are stored in potentially platform dependent multiples.
1214 * In other words, *_freq needs to be multiplied by X to be interesting.
1215 * Soft limits are those which are used for the dynamic reclocking done
1216 * by the driver (raise frequencies under heavy loads, and lower for
1217 * lighter loads). Hard limits are those imposed by the hardware.
1219 * A distinction is made for overclocking, which is never enabled by
1220 * default, and is considered to be above the hard limit if it's
1223 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1224 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1225 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1226 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1227 u8 min_freq; /* AKA RPn. Minimum frequency */
1228 u8 boost_freq; /* Frequency to request when wait boosting */
1229 u8 idle_freq; /* Frequency to request when we are idle */
1230 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1231 u8 rp1_freq; /* "less than" RP0 power/freqency */
1232 u8 rp0_freq; /* Non-overclocked max frequency. */
1233 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1235 u8 up_threshold; /* Current %busy required to uplock */
1236 u8 down_threshold; /* Current %busy required to downclock */
1239 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1241 spinlock_t client_lock;
1242 struct list_head clients;
1246 struct delayed_work autoenable_work;
1249 /* manual wa residency calculations */
1250 struct intel_rps_ei up_ei, down_ei;
1253 * Protects RPS/RC6 register access and PCU communication.
1254 * Must be taken after struct_mutex if nested. Note that
1255 * this lock may be held for long periods of time when
1256 * talking to hw - so only take it when talking to hw!
1258 struct mutex hw_lock;
1261 /* defined intel_pm.c */
1262 extern spinlock_t mchdev_lock;
1264 struct intel_ilk_power_mgmt {
1272 unsigned long last_time1;
1273 unsigned long chipset_power;
1276 unsigned long gfx_power;
1283 struct drm_i915_private;
1284 struct i915_power_well;
1286 struct i915_power_well_ops {
1288 * Synchronize the well's hw state to match the current sw state, for
1289 * example enable/disable it based on the current refcount. Called
1290 * during driver init and resume time, possibly after first calling
1291 * the enable/disable handlers.
1293 void (*sync_hw)(struct drm_i915_private *dev_priv,
1294 struct i915_power_well *power_well);
1296 * Enable the well and resources that depend on it (for example
1297 * interrupts located on the well). Called after the 0->1 refcount
1300 void (*enable)(struct drm_i915_private *dev_priv,
1301 struct i915_power_well *power_well);
1303 * Disable the well and resources that depend on it. Called after
1304 * the 1->0 refcount transition.
1306 void (*disable)(struct drm_i915_private *dev_priv,
1307 struct i915_power_well *power_well);
1308 /* Returns the hw enabled state. */
1309 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1310 struct i915_power_well *power_well);
1313 /* Power well structure for haswell */
1314 struct i915_power_well {
1317 /* power well enable/disable usage count */
1319 /* cached hw enabled state */
1321 unsigned long domains;
1323 const struct i915_power_well_ops *ops;
1326 struct i915_power_domains {
1328 * Power wells needed for initialization at driver init and suspend
1329 * time are on. They are kept on until after the first modeset.
1333 int power_well_count;
1336 int domain_use_count[POWER_DOMAIN_NUM];
1337 struct i915_power_well *power_wells;
1340 #define MAX_L3_SLICES 2
1341 struct intel_l3_parity {
1342 u32 *remap_info[MAX_L3_SLICES];
1343 struct work_struct error_work;
1347 struct i915_gem_mm {
1348 /** Memory allocator for GTT stolen memory */
1349 struct drm_mm stolen;
1350 /** Protects the usage of the GTT stolen memory allocator. This is
1351 * always the inner lock when overlapping with struct_mutex. */
1352 struct mutex stolen_lock;
1354 /** List of all objects in gtt_space. Used to restore gtt
1355 * mappings on resume */
1356 struct list_head bound_list;
1358 * List of objects which are not bound to the GTT (thus
1359 * are idle and not used by the GPU) but still have
1360 * (presumably uncached) pages still attached.
1362 struct list_head unbound_list;
1364 /** List of all objects in gtt_space, currently mmaped by userspace.
1365 * All objects within this list must also be on bound_list.
1367 struct list_head userfault_list;
1369 /** Usable portion of the GTT for GEM */
1370 unsigned long stolen_base; /* limited to low memory (32-bit) */
1372 /** PPGTT used for aliasing the PPGTT with the GTT */
1373 struct i915_hw_ppgtt *aliasing_ppgtt;
1375 struct notifier_block oom_notifier;
1376 struct notifier_block vmap_notifier;
1377 struct shrinker shrinker;
1379 /** LRU list of objects with fence regs on them. */
1380 struct list_head fence_list;
1383 * Are we in a non-interruptible section of code like
1388 /* the indicator for dispatch video commands on two BSD rings */
1389 atomic_t bsd_engine_dispatch_index;
1391 /** Bit 6 swizzling required for X tiling */
1392 uint32_t bit_6_swizzle_x;
1393 /** Bit 6 swizzling required for Y tiling */
1394 uint32_t bit_6_swizzle_y;
1396 /* accounting, useful for userland debugging */
1397 spinlock_t object_stat_lock;
1402 struct drm_i915_error_state_buf {
1403 struct drm_i915_private *i915;
1412 struct i915_error_state_file_priv {
1413 struct drm_device *dev;
1414 struct drm_i915_error_state *error;
1417 struct i915_gpu_error {
1418 /* For hangcheck timer */
1419 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1420 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1421 /* Hang gpu twice in this window and your context gets banned */
1422 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1424 struct delayed_work hangcheck_work;
1426 /* For reset and error_state handling. */
1428 /* Protected by the above dev->gpu_error.lock. */
1429 struct drm_i915_error_state *first_error;
1431 unsigned long missed_irq_rings;
1434 * State variable controlling the reset flow and count
1436 * This is a counter which gets incremented when reset is triggered,
1438 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1439 * meaning that any waiters holding onto the struct_mutex should
1440 * relinquish the lock immediately in order for the reset to start.
1442 * If reset is not completed succesfully, the I915_WEDGE bit is
1443 * set meaning that hardware is terminally sour and there is no
1444 * recovery. All waiters on the reset_queue will be woken when
1447 * This counter is used by the wait_seqno code to notice that reset
1448 * event happened and it needs to restart the entire ioctl (since most
1449 * likely the seqno it waited for won't ever signal anytime soon).
1451 * This is important for lock-free wait paths, where no contended lock
1452 * naturally enforces the correct ordering between the bail-out of the
1453 * waiter and the gpu reset work code.
1455 unsigned long reset_count;
1457 unsigned long flags;
1458 #define I915_RESET_IN_PROGRESS 0
1459 #define I915_WEDGED (BITS_PER_LONG - 1)
1462 * Waitqueue to signal when a hang is detected. Used to for waiters
1463 * to release the struct_mutex for the reset to procede.
1465 wait_queue_head_t wait_queue;
1468 * Waitqueue to signal when the reset has completed. Used by clients
1469 * that wait for dev_priv->mm.wedged to settle.
1471 wait_queue_head_t reset_queue;
1473 /* For missed irq/seqno simulation. */
1474 unsigned long test_irq_rings;
1477 enum modeset_restore {
1478 MODESET_ON_LID_OPEN,
1483 #define DP_AUX_A 0x40
1484 #define DP_AUX_B 0x10
1485 #define DP_AUX_C 0x20
1486 #define DP_AUX_D 0x30
1488 #define DDC_PIN_B 0x05
1489 #define DDC_PIN_C 0x04
1490 #define DDC_PIN_D 0x06
1492 struct ddi_vbt_port_info {
1494 * This is an index in the HDMI/DVI DDI buffer translation table.
1495 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1496 * populate this field.
1498 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1499 uint8_t hdmi_level_shift;
1501 uint8_t supports_dvi:1;
1502 uint8_t supports_hdmi:1;
1503 uint8_t supports_dp:1;
1505 uint8_t alternate_aux_channel;
1506 uint8_t alternate_ddc_pin;
1508 uint8_t dp_boost_level;
1509 uint8_t hdmi_boost_level;
1512 enum psr_lines_to_wait {
1513 PSR_0_LINES_TO_WAIT = 0,
1515 PSR_4_LINES_TO_WAIT,
1519 struct intel_vbt_data {
1520 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1521 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1524 unsigned int int_tv_support:1;
1525 unsigned int lvds_dither:1;
1526 unsigned int lvds_vbt:1;
1527 unsigned int int_crt_support:1;
1528 unsigned int lvds_use_ssc:1;
1529 unsigned int display_clock_mode:1;
1530 unsigned int fdi_rx_polarity_inverted:1;
1531 unsigned int panel_type:4;
1533 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1535 enum drrs_support_type drrs_type;
1546 struct edp_power_seq pps;
1551 bool require_aux_wakeup;
1553 enum psr_lines_to_wait lines_to_wait;
1554 int tp1_wakeup_time;
1555 int tp2_tp3_wakeup_time;
1561 bool active_low_pwm;
1562 u8 min_brightness; /* min_brightness/255 of max */
1563 enum intel_backlight_type type;
1569 struct mipi_config *config;
1570 struct mipi_pps_data *pps;
1574 const u8 *sequence[MIPI_SEQ_MAX];
1580 union child_device_config *child_dev;
1582 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1583 struct sdvo_device_mapping sdvo_mappings[2];
1586 enum intel_ddb_partitioning {
1588 INTEL_DDB_PART_5_6, /* IVB+ */
1591 struct intel_wm_level {
1599 struct ilk_wm_values {
1600 uint32_t wm_pipe[3];
1602 uint32_t wm_lp_spr[3];
1603 uint32_t wm_linetime[3];
1605 enum intel_ddb_partitioning partitioning;
1608 struct vlv_pipe_wm {
1619 struct vlv_wm_values {
1620 struct vlv_pipe_wm pipe[3];
1621 struct vlv_sr_wm sr;
1631 struct skl_ddb_entry {
1632 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1635 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1637 return entry->end - entry->start;
1640 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1641 const struct skl_ddb_entry *e2)
1643 if (e1->start == e2->start && e1->end == e2->end)
1649 struct skl_ddb_allocation {
1650 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1651 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1654 struct skl_wm_values {
1655 unsigned dirty_pipes;
1656 struct skl_ddb_allocation ddb;
1659 struct skl_wm_level {
1661 uint16_t plane_res_b;
1662 uint8_t plane_res_l;
1666 * This struct helps tracking the state needed for runtime PM, which puts the
1667 * device in PCI D3 state. Notice that when this happens, nothing on the
1668 * graphics device works, even register access, so we don't get interrupts nor
1671 * Every piece of our code that needs to actually touch the hardware needs to
1672 * either call intel_runtime_pm_get or call intel_display_power_get with the
1673 * appropriate power domain.
1675 * Our driver uses the autosuspend delay feature, which means we'll only really
1676 * suspend if we stay with zero refcount for a certain amount of time. The
1677 * default value is currently very conservative (see intel_runtime_pm_enable), but
1678 * it can be changed with the standard runtime PM files from sysfs.
1680 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1681 * goes back to false exactly before we reenable the IRQs. We use this variable
1682 * to check if someone is trying to enable/disable IRQs while they're supposed
1683 * to be disabled. This shouldn't happen and we'll print some error messages in
1686 * For more, read the Documentation/power/runtime_pm.txt.
1688 struct i915_runtime_pm {
1689 atomic_t wakeref_count;
1694 enum intel_pipe_crc_source {
1695 INTEL_PIPE_CRC_SOURCE_NONE,
1696 INTEL_PIPE_CRC_SOURCE_PLANE1,
1697 INTEL_PIPE_CRC_SOURCE_PLANE2,
1698 INTEL_PIPE_CRC_SOURCE_PF,
1699 INTEL_PIPE_CRC_SOURCE_PIPE,
1700 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1701 INTEL_PIPE_CRC_SOURCE_TV,
1702 INTEL_PIPE_CRC_SOURCE_DP_B,
1703 INTEL_PIPE_CRC_SOURCE_DP_C,
1704 INTEL_PIPE_CRC_SOURCE_DP_D,
1705 INTEL_PIPE_CRC_SOURCE_AUTO,
1706 INTEL_PIPE_CRC_SOURCE_MAX,
1709 struct intel_pipe_crc_entry {
1714 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1715 struct intel_pipe_crc {
1717 bool opened; /* exclusive access to the result file */
1718 struct intel_pipe_crc_entry *entries;
1719 enum intel_pipe_crc_source source;
1721 wait_queue_head_t wq;
1724 struct i915_frontbuffer_tracking {
1728 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1735 struct i915_wa_reg {
1738 /* bitmask representing WA bits */
1743 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1744 * allowing it for RCS as we don't foresee any requirement of having
1745 * a whitelist for other engines. When it is really required for
1746 * other engines then the limit need to be increased.
1748 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1750 struct i915_workarounds {
1751 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1753 u32 hw_whitelist_count[I915_NUM_ENGINES];
1756 struct i915_virtual_gpu {
1760 /* used in computing the new watermarks state */
1761 struct intel_wm_config {
1762 unsigned int num_pipes_active;
1763 bool sprites_enabled;
1764 bool sprites_scaled;
1767 struct drm_i915_private {
1768 struct drm_device drm;
1770 struct kmem_cache *objects;
1771 struct kmem_cache *vmas;
1772 struct kmem_cache *requests;
1774 const struct intel_device_info info;
1776 int relative_constants_mode;
1780 struct intel_uncore uncore;
1782 struct i915_virtual_gpu vgpu;
1784 struct intel_gvt *gvt;
1786 struct intel_guc guc;
1788 struct intel_csr csr;
1790 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1792 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1793 * controller on different i2c buses. */
1794 struct mutex gmbus_mutex;
1797 * Base address of the gmbus and gpio block.
1799 uint32_t gpio_mmio_base;
1801 /* MMIO base address for MIPI regs */
1802 uint32_t mipi_mmio_base;
1804 uint32_t psr_mmio_base;
1806 uint32_t pps_mmio_base;
1808 wait_queue_head_t gmbus_wait_queue;
1810 struct pci_dev *bridge_dev;
1811 struct i915_gem_context *kernel_context;
1812 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1813 struct i915_vma *semaphore;
1816 struct drm_dma_handle *status_page_dmah;
1817 struct resource mch_res;
1819 /* protects the irq masks */
1820 spinlock_t irq_lock;
1822 /* protects the mmio flip data */
1823 spinlock_t mmio_flip_lock;
1825 bool display_irqs_enabled;
1827 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1828 struct pm_qos_request pm_qos;
1830 /* Sideband mailbox protection */
1831 struct mutex sb_lock;
1833 /** Cached value of IMR to avoid reads in updating the bitfield */
1836 u32 de_irq_mask[I915_MAX_PIPES];
1842 u32 pipestat_irq_mask[I915_MAX_PIPES];
1844 struct i915_hotplug hotplug;
1845 struct intel_fbc fbc;
1846 struct i915_drrs drrs;
1847 struct intel_opregion opregion;
1848 struct intel_vbt_data vbt;
1850 bool preserve_bios_swizzle;
1853 struct intel_overlay *overlay;
1855 /* backlight registers and fields in struct intel_panel */
1856 struct mutex backlight_lock;
1859 bool no_aux_handshake;
1861 /* protects panel power sequencer state */
1862 struct mutex pps_mutex;
1864 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1865 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1867 unsigned int fsb_freq, mem_freq, is_ddr3;
1868 unsigned int skl_preferred_vco_freq;
1869 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1870 unsigned int max_dotclk_freq;
1871 unsigned int rawclk_freq;
1872 unsigned int hpll_freq;
1873 unsigned int czclk_freq;
1876 unsigned int vco, ref;
1880 * wq - Driver workqueue for GEM.
1882 * NOTE: Work items scheduled here are not allowed to grab any modeset
1883 * locks, for otherwise the flushing done in the pageflip code will
1884 * result in deadlocks.
1886 struct workqueue_struct *wq;
1888 /* Display functions */
1889 struct drm_i915_display_funcs display;
1891 /* PCH chipset type */
1892 enum intel_pch pch_type;
1893 unsigned short pch_id;
1895 unsigned long quirks;
1897 enum modeset_restore modeset_restore;
1898 struct mutex modeset_restore_lock;
1899 struct drm_atomic_state *modeset_restore_state;
1900 struct drm_modeset_acquire_ctx reset_ctx;
1902 struct list_head vm_list; /* Global list of all address spaces */
1903 struct i915_ggtt ggtt; /* VM representing the global address space */
1905 struct i915_gem_mm mm;
1906 DECLARE_HASHTABLE(mm_structs, 7);
1907 struct mutex mm_lock;
1909 /* The hw wants to have a stable context identifier for the lifetime
1910 * of the context (for OA, PASID, faults, etc). This is limited
1911 * in execlists to 21 bits.
1913 struct ida context_hw_ida;
1914 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1916 /* Kernel Modesetting */
1918 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1919 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1920 wait_queue_head_t pending_flip_queue;
1922 #ifdef CONFIG_DEBUG_FS
1923 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1926 /* dpll and cdclk state is protected by connection_mutex */
1927 int num_shared_dpll;
1928 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1929 const struct intel_dpll_mgr *dpll_mgr;
1932 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1933 * Must be global rather than per dpll, because on some platforms
1934 * plls share registers.
1936 struct mutex dpll_lock;
1938 unsigned int active_crtcs;
1939 unsigned int min_pixclk[I915_MAX_PIPES];
1941 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1943 struct i915_workarounds workarounds;
1945 struct i915_frontbuffer_tracking fb_tracking;
1949 bool mchbar_need_disable;
1951 struct intel_l3_parity l3_parity;
1953 /* Cannot be determined by PCIID. You must always read a register. */
1956 /* gen6+ rps state */
1957 struct intel_gen6_power_mgmt rps;
1959 /* ilk-only ips/rps state. Everything in here is protected by the global
1960 * mchdev_lock in intel_pm.c */
1961 struct intel_ilk_power_mgmt ips;
1963 struct i915_power_domains power_domains;
1965 struct i915_psr psr;
1967 struct i915_gpu_error gpu_error;
1969 struct drm_i915_gem_object *vlv_pctx;
1971 #ifdef CONFIG_DRM_FBDEV_EMULATION
1972 /* list of fbdev register on this device */
1973 struct intel_fbdev *fbdev;
1974 struct work_struct fbdev_suspend_work;
1977 struct drm_property *broadcast_rgb_property;
1978 struct drm_property *force_audio_property;
1980 /* hda/i915 audio component */
1981 struct i915_audio_component *audio_component;
1982 bool audio_component_registered;
1984 * av_mutex - mutex for audio/video sync
1987 struct mutex av_mutex;
1989 uint32_t hw_context_size;
1990 struct list_head context_list;
1994 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1995 u32 chv_phy_control;
1997 * Shadows for CHV DPLL_MD regs to keep the state
1998 * checker somewhat working in the presence hardware
1999 * crappiness (can't read out DPLL_MD for pipes B & C).
2001 u32 chv_dpll_md[I915_MAX_PIPES];
2005 bool suspended_to_idle;
2006 struct i915_suspend_saved_registers regfile;
2007 struct vlv_s0ix_state vlv_s0ix_state;
2010 I915_SAGV_UNKNOWN = 0,
2013 I915_SAGV_NOT_CONTROLLED
2018 * Raw watermark latency values:
2019 * in 0.1us units for WM0,
2020 * in 0.5us units for WM1+.
2023 uint16_t pri_latency[5];
2025 uint16_t spr_latency[5];
2027 uint16_t cur_latency[5];
2029 * Raw watermark memory latency values
2030 * for SKL for all 8 levels
2033 uint16_t skl_latency[8];
2036 * The skl_wm_values structure is a bit too big for stack
2037 * allocation, so we keep the staging struct where we store
2038 * intermediate results here instead.
2040 struct skl_wm_values skl_results;
2042 /* current hardware state */
2044 struct ilk_wm_values hw;
2045 struct skl_wm_values skl_hw;
2046 struct vlv_wm_values vlv;
2052 * Should be held around atomic WM register writing; also
2053 * protects * intel_crtc->wm.active and
2054 * cstate->wm.need_postvbl_update.
2056 struct mutex wm_mutex;
2059 * Set during HW readout of watermarks/DDB. Some platforms
2060 * need to know when we're still using BIOS-provided values
2061 * (which we don't fully trust).
2063 bool distrust_bios_wm;
2066 struct i915_runtime_pm pm;
2068 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2070 void (*resume)(struct drm_i915_private *);
2071 void (*cleanup_engine)(struct intel_engine_cs *engine);
2074 * Is the GPU currently considered idle, or busy executing
2075 * userspace requests? Whilst idle, we allow runtime power
2076 * management to power down the hardware and display clocks.
2077 * In order to reduce the effect on performance, there
2078 * is a slight delay before we do so.
2080 unsigned int active_engines;
2084 * We leave the user IRQ off as much as possible,
2085 * but this means that requests will finish and never
2086 * be retired once the system goes idle. Set a timer to
2087 * fire periodically while the ring is running. When it
2088 * fires, go retire requests.
2090 struct delayed_work retire_work;
2093 * When we detect an idle GPU, we want to turn on
2094 * powersaving features. So once we see that there
2095 * are no more requests outstanding and no more
2096 * arrive within a small period of time, we fire
2097 * off the idle_work.
2099 struct delayed_work idle_work;
2102 /* perform PHY state sanity checks? */
2103 bool chv_phy_assert[2];
2105 /* Used to save the pipe-to-encoder mapping for audio */
2106 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2109 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2110 * will be rejected. Instead look for a better place.
2114 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2116 return container_of(dev, struct drm_i915_private, drm);
2119 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2121 return to_i915(dev_get_drvdata(kdev));
2124 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2126 return container_of(guc, struct drm_i915_private, guc);
2129 /* Simple iterator over all initialised engines */
2130 #define for_each_engine(engine__, dev_priv__, id__) \
2132 (id__) < I915_NUM_ENGINES; \
2134 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2136 #define __mask_next_bit(mask) ({ \
2137 int __idx = ffs(mask) - 1; \
2138 mask &= ~BIT(__idx); \
2142 /* Iterator over subset of engines selected by mask */
2143 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2144 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2145 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2147 enum hdmi_force_audio {
2148 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2149 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2150 HDMI_AUDIO_AUTO, /* trust EDID */
2151 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2154 #define I915_GTT_OFFSET_NONE ((u32)-1)
2156 struct drm_i915_gem_object_ops {
2158 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2160 /* Interface between the GEM object and its backing storage.
2161 * get_pages() is called once prior to the use of the associated set
2162 * of pages before to binding them into the GTT, and put_pages() is
2163 * called after we no longer need them. As we expect there to be
2164 * associated cost with migrating pages between the backing storage
2165 * and making them available for the GPU (e.g. clflush), we may hold
2166 * onto the pages after they are no longer referenced by the GPU
2167 * in case they may be used again shortly (for example migrating the
2168 * pages to a different memory domain within the GTT). put_pages()
2169 * will therefore most likely be called when the object itself is
2170 * being released or under memory pressure (where we attempt to
2171 * reap pages for the shrinker).
2173 int (*get_pages)(struct drm_i915_gem_object *);
2174 void (*put_pages)(struct drm_i915_gem_object *);
2176 int (*dmabuf_export)(struct drm_i915_gem_object *);
2177 void (*release)(struct drm_i915_gem_object *);
2181 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2182 * considered to be the frontbuffer for the given plane interface-wise. This
2183 * doesn't mean that the hw necessarily already scans it out, but that any
2184 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2186 * We have one bit per pipe and per scanout plane type.
2188 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2189 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2190 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2191 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2192 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2193 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2194 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2195 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2196 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2197 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2198 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2199 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2201 struct drm_i915_gem_object {
2202 struct drm_gem_object base;
2204 const struct drm_i915_gem_object_ops *ops;
2206 /** List of VMAs backed by this object */
2207 struct list_head vma_list;
2209 /** Stolen memory for this object, instead of being backed by shmem. */
2210 struct drm_mm_node *stolen;
2211 struct list_head global_list;
2214 * Whether the object is currently in the GGTT mmap.
2216 struct list_head userfault_link;
2218 /** Used in execbuf to temporarily hold a ref */
2219 struct list_head obj_exec_link;
2221 struct list_head batch_pool_link;
2223 unsigned long flags;
2225 * This is set if the object is on the active lists (has pending
2226 * rendering and so a non-zero seqno), and is not set if it i s on
2227 * inactive (ready to be unbound) list.
2229 #define I915_BO_ACTIVE_SHIFT 0
2230 #define I915_BO_ACTIVE_MASK ((1 << I915_NUM_ENGINES) - 1)
2231 #define __I915_BO_ACTIVE(bo) \
2232 ((READ_ONCE((bo)->flags) >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK)
2235 * This is set if the object has been written to since last bound
2238 unsigned int dirty:1;
2241 * Advice: are the backing pages purgeable?
2243 unsigned int madv:2;
2246 * Is the object to be mapped as read-only to the GPU
2247 * Only honoured if hardware has relevant pte bit
2249 unsigned long gt_ro:1;
2250 unsigned int cache_level:3;
2251 unsigned int cache_dirty:1;
2253 atomic_t frontbuffer_bits;
2254 unsigned int frontbuffer_ggtt_origin; /* write once */
2256 /** Current tiling stride for the object, if it's tiled. */
2257 unsigned int tiling_and_stride;
2258 #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
2259 #define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
2260 #define STRIDE_MASK (~TILING_MASK)
2262 /** Count of VMA actually bound by this object */
2263 unsigned int bind_count;
2264 unsigned int pin_display;
2266 struct sg_table *pages;
2267 int pages_pin_count;
2269 struct scatterlist *sg;
2274 /** Breadcrumb of last rendering to the buffer.
2275 * There can only be one writer, but we allow for multiple readers.
2276 * If there is a writer that necessarily implies that all other
2277 * read requests are complete - but we may only be lazily clearing
2278 * the read requests. A read request is naturally the most recent
2279 * request on a ring, so we may have two different write and read
2280 * requests on one ring where the write request is older than the
2281 * read request. This allows for the CPU to read from an active
2282 * buffer by only waiting for the write to complete.
2284 struct i915_gem_active last_read[I915_NUM_ENGINES];
2285 struct i915_gem_active last_write;
2287 /** References from framebuffers, locks out tiling changes. */
2288 unsigned long framebuffer_references;
2290 /** Record of address bit 17 of each page at last unbind. */
2291 unsigned long *bit_17;
2293 struct i915_gem_userptr {
2295 unsigned read_only :1;
2296 unsigned workers :4;
2297 #define I915_GEM_USERPTR_MAX_WORKERS 15
2299 struct i915_mm_struct *mm;
2300 struct i915_mmu_object *mmu_object;
2301 struct work_struct *work;
2304 /** for phys allocated objects */
2305 struct drm_dma_handle *phys_handle;
2308 static inline struct drm_i915_gem_object *
2309 to_intel_bo(struct drm_gem_object *gem)
2311 /* Assert that to_intel_bo(NULL) == NULL */
2312 BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));
2314 return container_of(gem, struct drm_i915_gem_object, base);
2317 static inline struct drm_i915_gem_object *
2318 i915_gem_object_lookup(struct drm_file *file, u32 handle)
2320 return to_intel_bo(drm_gem_object_lookup(file, handle));
2324 extern struct drm_gem_object *
2325 drm_gem_object_lookup(struct drm_file *file, u32 handle);
2327 __attribute__((nonnull))
2328 static inline struct drm_i915_gem_object *
2329 i915_gem_object_get(struct drm_i915_gem_object *obj)
2331 drm_gem_object_reference(&obj->base);
2336 extern void drm_gem_object_reference(struct drm_gem_object *);
2338 __attribute__((nonnull))
2340 i915_gem_object_put(struct drm_i915_gem_object *obj)
2342 drm_gem_object_unreference(&obj->base);
2346 extern void drm_gem_object_unreference(struct drm_gem_object *);
2348 __attribute__((nonnull))
2350 i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj)
2352 drm_gem_object_unreference_unlocked(&obj->base);
2356 extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *);
2359 i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
2361 return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
2364 static inline unsigned long
2365 i915_gem_object_get_active(const struct drm_i915_gem_object *obj)
2367 return (obj->flags >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK;
2371 i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
2373 return i915_gem_object_get_active(obj);
2377 i915_gem_object_set_active(struct drm_i915_gem_object *obj, int engine)
2379 obj->flags |= BIT(engine + I915_BO_ACTIVE_SHIFT);
2383 i915_gem_object_clear_active(struct drm_i915_gem_object *obj, int engine)
2385 obj->flags &= ~BIT(engine + I915_BO_ACTIVE_SHIFT);
2389 i915_gem_object_has_active_engine(const struct drm_i915_gem_object *obj,
2392 return obj->flags & BIT(engine + I915_BO_ACTIVE_SHIFT);
2395 static inline unsigned int
2396 i915_gem_object_get_tiling(struct drm_i915_gem_object *obj)
2398 return obj->tiling_and_stride & TILING_MASK;
2402 i915_gem_object_is_tiled(struct drm_i915_gem_object *obj)
2404 return i915_gem_object_get_tiling(obj) != I915_TILING_NONE;
2407 static inline unsigned int
2408 i915_gem_object_get_stride(struct drm_i915_gem_object *obj)
2410 return obj->tiling_and_stride & STRIDE_MASK;
2413 static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
2415 i915_gem_object_get(vma->obj);
2419 static inline void i915_vma_put(struct i915_vma *vma)
2421 lockdep_assert_held(&vma->vm->dev->struct_mutex);
2422 i915_gem_object_put(vma->obj);
2426 * Optimised SGL iterator for GEM objects
2428 static __always_inline struct sgt_iter {
2429 struct scatterlist *sgp;
2436 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2437 struct sgt_iter s = { .sgp = sgl };
2440 s.max = s.curr = s.sgp->offset;
2441 s.max += s.sgp->length;
2443 s.dma = sg_dma_address(s.sgp);
2445 s.pfn = page_to_pfn(sg_page(s.sgp));
2452 * __sg_next - return the next scatterlist entry in a list
2453 * @sg: The current sg entry
2456 * If the entry is the last, return NULL; otherwise, step to the next
2457 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2458 * otherwise just return the pointer to the current element.
2460 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2462 #ifdef CONFIG_DEBUG_SG
2463 BUG_ON(sg->sg_magic != SG_MAGIC);
2465 return sg_is_last(sg) ? NULL :
2466 likely(!sg_is_chain(++sg)) ? sg :
2471 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2472 * @__dmap: DMA address (output)
2473 * @__iter: 'struct sgt_iter' (iterator state, internal)
2474 * @__sgt: sg_table to iterate over (input)
2476 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2477 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2478 ((__dmap) = (__iter).dma + (__iter).curr); \
2479 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2480 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2483 * for_each_sgt_page - iterate over the pages of the given sg_table
2484 * @__pp: page pointer (output)
2485 * @__iter: 'struct sgt_iter' (iterator state, internal)
2486 * @__sgt: sg_table to iterate over (input)
2488 #define for_each_sgt_page(__pp, __iter, __sgt) \
2489 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2490 ((__pp) = (__iter).pfn == 0 ? NULL : \
2491 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2492 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2493 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2496 * A command that requires special handling by the command parser.
2498 struct drm_i915_cmd_descriptor {
2500 * Flags describing how the command parser processes the command.
2502 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2503 * a length mask if not set
2504 * CMD_DESC_SKIP: The command is allowed but does not follow the
2505 * standard length encoding for the opcode range in
2507 * CMD_DESC_REJECT: The command is never allowed
2508 * CMD_DESC_REGISTER: The command should be checked against the
2509 * register whitelist for the appropriate ring
2510 * CMD_DESC_MASTER: The command is allowed if the submitting process
2514 #define CMD_DESC_FIXED (1<<0)
2515 #define CMD_DESC_SKIP (1<<1)
2516 #define CMD_DESC_REJECT (1<<2)
2517 #define CMD_DESC_REGISTER (1<<3)
2518 #define CMD_DESC_BITMASK (1<<4)
2519 #define CMD_DESC_MASTER (1<<5)
2522 * The command's unique identification bits and the bitmask to get them.
2523 * This isn't strictly the opcode field as defined in the spec and may
2524 * also include type, subtype, and/or subop fields.
2532 * The command's length. The command is either fixed length (i.e. does
2533 * not include a length field) or has a length field mask. The flag
2534 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2535 * a length mask. All command entries in a command table must include
2536 * length information.
2544 * Describes where to find a register address in the command to check
2545 * against the ring's register whitelist. Only valid if flags has the
2546 * CMD_DESC_REGISTER bit set.
2548 * A non-zero step value implies that the command may access multiple
2549 * registers in sequence (e.g. LRI), in that case step gives the
2550 * distance in dwords between individual offset fields.
2558 #define MAX_CMD_DESC_BITMASKS 3
2560 * Describes command checks where a particular dword is masked and
2561 * compared against an expected value. If the command does not match
2562 * the expected value, the parser rejects it. Only valid if flags has
2563 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2566 * If the check specifies a non-zero condition_mask then the parser
2567 * only performs the check when the bits specified by condition_mask
2574 u32 condition_offset;
2576 } bits[MAX_CMD_DESC_BITMASKS];
2580 * A table of commands requiring special handling by the command parser.
2582 * Each engine has an array of tables. Each table consists of an array of
2583 * command descriptors, which must be sorted with command opcodes in
2586 struct drm_i915_cmd_table {
2587 const struct drm_i915_cmd_descriptor *table;
2591 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2592 #define __I915__(p) ({ \
2593 struct drm_i915_private *__p; \
2594 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2595 __p = (struct drm_i915_private *)p; \
2596 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2597 __p = to_i915((struct drm_device *)p); \
2602 #define INTEL_INFO(p) (&__I915__(p)->info)
2604 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2605 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2607 #define REVID_FOREVER 0xff
2608 #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
2610 #define GEN_FOREVER (0)
2612 * Returns true if Gen is in inclusive range [Start, End].
2614 * Use GEN_FOREVER for unbound start and or end.
2616 #define IS_GEN(dev_priv, s, e) ({ \
2617 unsigned int __s = (s), __e = (e); \
2618 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2619 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2620 if ((__s) != GEN_FOREVER) \
2622 if ((__e) == GEN_FOREVER) \
2623 __e = BITS_PER_LONG - 1; \
2626 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2630 * Return true if revision is in range [since,until] inclusive.
2632 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2634 #define IS_REVID(p, since, until) \
2635 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2637 #define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577)
2638 #define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562)
2639 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2640 #define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572)
2641 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2642 #define IS_I915GM(dev_priv) (INTEL_DEVID(dev_priv) == 0x2592)
2643 #define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772)
2644 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2645 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2646 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2647 #define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
2648 #define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x)
2649 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2650 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2651 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2652 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2653 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2654 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.is_ivybridge)
2655 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2656 INTEL_DEVID(dev_priv) == 0x0152 || \
2657 INTEL_DEVID(dev_priv) == 0x015a)
2658 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.is_valleyview)
2659 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview)
2660 #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
2661 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
2662 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
2663 #define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
2664 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
2665 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2666 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2667 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2668 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2669 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2670 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2671 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2672 /* ULX machines are also considered ULT. */
2673 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2674 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2675 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2676 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2677 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2678 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2679 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2680 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2681 /* ULX machines are also considered ULT. */
2682 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2683 INTEL_DEVID(dev_priv) == 0x0A1E)
2684 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2685 INTEL_DEVID(dev_priv) == 0x1913 || \
2686 INTEL_DEVID(dev_priv) == 0x1916 || \
2687 INTEL_DEVID(dev_priv) == 0x1921 || \
2688 INTEL_DEVID(dev_priv) == 0x1926)
2689 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2690 INTEL_DEVID(dev_priv) == 0x1915 || \
2691 INTEL_DEVID(dev_priv) == 0x191E)
2692 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2693 INTEL_DEVID(dev_priv) == 0x5913 || \
2694 INTEL_DEVID(dev_priv) == 0x5916 || \
2695 INTEL_DEVID(dev_priv) == 0x5921 || \
2696 INTEL_DEVID(dev_priv) == 0x5926)
2697 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2698 INTEL_DEVID(dev_priv) == 0x5915 || \
2699 INTEL_DEVID(dev_priv) == 0x591E)
2700 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2701 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2702 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2703 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2705 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2707 #define SKL_REVID_A0 0x0
2708 #define SKL_REVID_B0 0x1
2709 #define SKL_REVID_C0 0x2
2710 #define SKL_REVID_D0 0x3
2711 #define SKL_REVID_E0 0x4
2712 #define SKL_REVID_F0 0x5
2713 #define SKL_REVID_G0 0x6
2714 #define SKL_REVID_H0 0x7
2716 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2718 #define BXT_REVID_A0 0x0
2719 #define BXT_REVID_A1 0x1
2720 #define BXT_REVID_B0 0x3
2721 #define BXT_REVID_C0 0x9
2723 #define IS_BXT_REVID(dev_priv, since, until) \
2724 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2726 #define KBL_REVID_A0 0x0
2727 #define KBL_REVID_B0 0x1
2728 #define KBL_REVID_C0 0x2
2729 #define KBL_REVID_D0 0x3
2730 #define KBL_REVID_E0 0x4
2732 #define IS_KBL_REVID(dev_priv, since, until) \
2733 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2736 * The genX designation typically refers to the render engine, so render
2737 * capability related checks should use IS_GEN, while display and other checks
2738 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2741 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2742 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2743 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2744 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2745 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2746 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2747 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2748 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2750 #define ENGINE_MASK(id) BIT(id)
2751 #define RENDER_RING ENGINE_MASK(RCS)
2752 #define BSD_RING ENGINE_MASK(VCS)
2753 #define BLT_RING ENGINE_MASK(BCS)
2754 #define VEBOX_RING ENGINE_MASK(VECS)
2755 #define BSD2_RING ENGINE_MASK(VCS2)
2756 #define ALL_ENGINES (~0)
2758 #define HAS_ENGINE(dev_priv, id) \
2759 (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2761 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2762 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2763 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2764 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2766 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2767 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2768 #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2769 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2770 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2771 #define HWS_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->hws_needs_physical)
2773 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts)
2774 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->has_logical_ring_contexts)
2775 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2776 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2777 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2779 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2780 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2782 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2783 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv))
2785 /* WaRsDisableCoarsePowerGating:skl,bxt */
2786 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2787 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2788 IS_SKL_GT3(dev_priv) || \
2789 IS_SKL_GT4(dev_priv))
2792 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2793 * even when in MSI mode. This results in spurious interrupt warnings if the
2794 * legacy irq no. is shared with another device. The kernel then disables that
2795 * interrupt source and so prevents the other device from working properly.
2797 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2798 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq)
2800 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2801 * rows, which changed the alignment requirements and fence programming.
2803 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2804 !(IS_I915G(dev_priv) || \
2805 IS_I915GM(dev_priv)))
2806 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2807 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2809 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2810 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2811 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2813 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2815 #define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst)
2817 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2818 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2819 #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
2820 #define HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
2821 #define HAS_RC6p(dev) (INTEL_INFO(dev)->has_rc6p)
2823 #define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr)
2825 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2827 * For now, anything with a GuC requires uCode loading, and then supports
2828 * command submission once loaded. But these are logically independent
2829 * properties, so we have separate macros to test them.
2831 #define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc)
2832 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2833 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2835 #define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
2837 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2839 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2840 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2841 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2842 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2843 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2844 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2845 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2846 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2847 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2848 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2849 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2850 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2852 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2853 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2854 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2855 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2856 #define HAS_PCH_LPT_LP(dev_priv) \
2857 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2858 #define HAS_PCH_LPT_H(dev_priv) \
2859 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2860 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2861 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2862 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2863 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2865 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2867 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2869 /* DPF == dynamic parity feature */
2870 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2871 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2872 2 : HAS_L3_DPF(dev_priv))
2874 #define GT_FREQUENCY_MULTIPLIER 50
2875 #define GEN9_FREQ_SCALER 3
2877 #include "i915_trace.h"
2879 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2881 #ifdef CONFIG_INTEL_IOMMU
2882 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2888 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2889 extern int i915_resume_switcheroo(struct drm_device *dev);
2891 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2894 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);
2898 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2899 const char *fmt, ...);
2901 #define i915_report_error(dev_priv, fmt, ...) \
2902 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2904 #ifdef CONFIG_COMPAT
2905 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2908 extern const struct dev_pm_ops i915_pm_ops;
2910 extern int i915_driver_load(struct pci_dev *pdev,
2911 const struct pci_device_id *ent);
2912 extern void i915_driver_unload(struct drm_device *dev);
2913 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2914 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2915 extern void i915_reset(struct drm_i915_private *dev_priv);
2916 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2917 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2918 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2919 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2920 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2921 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2922 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2924 /* intel_hotplug.c */
2925 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2926 u32 pin_mask, u32 long_mask);
2927 void intel_hpd_init(struct drm_i915_private *dev_priv);
2928 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2929 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2930 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2931 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2932 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2935 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2937 unsigned long delay;
2939 if (unlikely(!i915.enable_hangcheck))
2942 /* Don't continually defer the hangcheck so that it is always run at
2943 * least once after work has been scheduled on any ring. Otherwise,
2944 * we will ignore a hung ring if a second ring is kept busy.
2947 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2948 queue_delayed_work(system_long_wq,
2949 &dev_priv->gpu_error.hangcheck_work, delay);
2953 void i915_handle_error(struct drm_i915_private *dev_priv,
2955 const char *fmt, ...);
2957 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2958 int intel_irq_install(struct drm_i915_private *dev_priv);
2959 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2961 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
2962 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2963 bool restore_forcewake);
2964 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2965 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2966 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2967 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
2968 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
2970 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2971 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2972 enum forcewake_domains domains);
2973 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2974 enum forcewake_domains domains);
2975 /* Like above but the caller must manage the uncore.lock itself.
2976 * Must be used with I915_READ_FW and friends.
2978 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2979 enum forcewake_domains domains);
2980 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2981 enum forcewake_domains domains);
2982 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
2984 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2986 int intel_wait_for_register(struct drm_i915_private *dev_priv,
2990 const unsigned long timeout_ms);
2991 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
2995 const unsigned long timeout_ms);
2997 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2999 return dev_priv->gvt;
3002 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3004 return dev_priv->vgpu.active;
3008 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3012 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3015 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3016 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3017 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3020 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3021 uint32_t interrupt_mask,
3022 uint32_t enabled_irq_mask);
3024 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3026 ilk_update_display_irq(dev_priv, bits, bits);
3029 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3031 ilk_update_display_irq(dev_priv, bits, 0);
3033 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3035 uint32_t interrupt_mask,
3036 uint32_t enabled_irq_mask);
3037 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3038 enum pipe pipe, uint32_t bits)
3040 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3042 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3043 enum pipe pipe, uint32_t bits)
3045 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3047 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3048 uint32_t interrupt_mask,
3049 uint32_t enabled_irq_mask);
3051 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3053 ibx_display_interrupt_update(dev_priv, bits, bits);
3056 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3058 ibx_display_interrupt_update(dev_priv, bits, 0);
3062 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3063 struct drm_file *file_priv);
3064 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3065 struct drm_file *file_priv);
3066 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3067 struct drm_file *file_priv);
3068 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3069 struct drm_file *file_priv);
3070 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3071 struct drm_file *file_priv);
3072 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3073 struct drm_file *file_priv);
3074 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3075 struct drm_file *file_priv);
3076 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3077 struct drm_file *file_priv);
3078 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3079 struct drm_file *file_priv);
3080 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3081 struct drm_file *file_priv);
3082 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3083 struct drm_file *file);
3084 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3085 struct drm_file *file);
3086 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3087 struct drm_file *file_priv);
3088 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3089 struct drm_file *file_priv);
3090 int i915_gem_set_tiling(struct drm_device *dev, void *data,
3091 struct drm_file *file_priv);
3092 int i915_gem_get_tiling(struct drm_device *dev, void *data,
3093 struct drm_file *file_priv);
3094 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3095 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3096 struct drm_file *file);
3097 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3098 struct drm_file *file_priv);
3099 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3100 struct drm_file *file_priv);
3101 void i915_gem_load_init(struct drm_device *dev);
3102 void i915_gem_load_cleanup(struct drm_device *dev);
3103 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3104 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3105 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3107 void *i915_gem_object_alloc(struct drm_device *dev);
3108 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3109 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3110 const struct drm_i915_gem_object_ops *ops);
3111 struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
3113 struct drm_i915_gem_object *i915_gem_object_create_from_data(
3114 struct drm_device *dev, const void *data, size_t size);
3115 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3116 void i915_gem_free_object(struct drm_gem_object *obj);
3118 struct i915_vma * __must_check
3119 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3120 const struct i915_ggtt_view *view,
3125 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3127 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
3128 int __must_check i915_vma_unbind(struct i915_vma *vma);
3129 void i915_vma_close(struct i915_vma *vma);
3130 void i915_vma_destroy(struct i915_vma *vma);
3132 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3133 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
3134 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3136 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3138 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3140 static inline int __sg_page_count(struct scatterlist *sg)
3142 return sg->length >> PAGE_SHIFT;
3146 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
3148 static inline dma_addr_t
3149 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n)
3151 if (n < obj->get_page.last) {
3152 obj->get_page.sg = obj->pages->sgl;
3153 obj->get_page.last = 0;
3156 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3157 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3158 if (unlikely(sg_is_chain(obj->get_page.sg)))
3159 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3162 return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT);
3165 static inline struct page *
3166 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3168 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
3171 if (n < obj->get_page.last) {
3172 obj->get_page.sg = obj->pages->sgl;
3173 obj->get_page.last = 0;
3176 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3177 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3178 if (unlikely(sg_is_chain(obj->get_page.sg)))
3179 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3182 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3185 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3187 GEM_BUG_ON(obj->pages == NULL);
3188 obj->pages_pin_count++;
3191 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3193 GEM_BUG_ON(obj->pages_pin_count == 0);
3194 obj->pages_pin_count--;
3195 GEM_BUG_ON(obj->pages_pin_count < obj->bind_count);
3198 enum i915_map_type {
3204 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3205 * @obj - the object to map into kernel address space
3206 * @type - the type of mapping, used to select pgprot_t
3208 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3209 * pages and then returns a contiguous mapping of the backing storage into
3210 * the kernel address space. Based on the @type of mapping, the PTE will be
3211 * set to either WriteBack or WriteCombine (via pgprot_t).
3213 * The caller must hold the struct_mutex, and is responsible for calling
3214 * i915_gem_object_unpin_map() when the mapping is no longer required.
3216 * Returns the pointer through which to access the mapped object, or an
3217 * ERR_PTR() on error.
3219 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3220 enum i915_map_type type);
3223 * i915_gem_object_unpin_map - releases an earlier mapping
3224 * @obj - the object to unmap
3226 * After pinning the object and mapping its pages, once you are finished
3227 * with your access, call i915_gem_object_unpin_map() to release the pin
3228 * upon the mapping. Once the pin count reaches zero, that mapping may be
3231 * The caller must hold the struct_mutex.
3233 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3235 lockdep_assert_held(&obj->base.dev->struct_mutex);
3236 i915_gem_object_unpin_pages(obj);
3239 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3240 unsigned int *needs_clflush);
3241 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3242 unsigned int *needs_clflush);
3243 #define CLFLUSH_BEFORE 0x1
3244 #define CLFLUSH_AFTER 0x2
3245 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3248 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3250 i915_gem_object_unpin_pages(obj);
3253 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3254 void i915_vma_move_to_active(struct i915_vma *vma,
3255 struct drm_i915_gem_request *req,
3256 unsigned int flags);
3257 int i915_gem_dumb_create(struct drm_file *file_priv,
3258 struct drm_device *dev,
3259 struct drm_mode_create_dumb *args);
3260 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3261 uint32_t handle, uint64_t *offset);
3262 int i915_gem_mmap_gtt_version(void);
3264 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3265 struct drm_i915_gem_object *new,
3266 unsigned frontbuffer_bits);
3268 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3270 struct drm_i915_gem_request *
3271 i915_gem_find_active_request(struct intel_engine_cs *engine);
3273 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3275 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3277 return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3280 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3282 return unlikely(test_bit(I915_WEDGED, &error->flags));
3285 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3287 return i915_reset_in_progress(error) | i915_terminally_wedged(error);
3290 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3292 return READ_ONCE(error->reset_count);
3295 void i915_gem_reset(struct drm_i915_private *dev_priv);
3296 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3297 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3298 int __must_check i915_gem_init(struct drm_device *dev);
3299 int __must_check i915_gem_init_hw(struct drm_device *dev);
3300 void i915_gem_init_swizzling(struct drm_device *dev);
3301 void i915_gem_cleanup_engines(struct drm_device *dev);
3302 int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3303 unsigned int flags);
3304 int __must_check i915_gem_suspend(struct drm_device *dev);
3305 void i915_gem_resume(struct drm_device *dev);
3306 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3308 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3311 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3314 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3315 struct i915_vma * __must_check
3316 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3318 const struct i915_ggtt_view *view);
3319 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3320 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3322 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3323 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3325 u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
3327 u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
3328 int tiling_mode, bool fenced);
3330 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3331 enum i915_cache_level cache_level);
3333 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3334 struct dma_buf *dma_buf);
3336 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3337 struct drm_gem_object *gem_obj, int flags);
3340 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3341 struct i915_address_space *vm,
3342 const struct i915_ggtt_view *view);
3345 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3346 struct i915_address_space *vm,
3347 const struct i915_ggtt_view *view);
3349 static inline struct i915_hw_ppgtt *
3350 i915_vm_to_ppgtt(struct i915_address_space *vm)
3352 return container_of(vm, struct i915_hw_ppgtt, base);
3355 static inline struct i915_vma *
3356 i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj,
3357 const struct i915_ggtt_view *view)
3359 return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view);
3362 static inline unsigned long
3363 i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o,
3364 const struct i915_ggtt_view *view)
3366 return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view));
3369 /* i915_gem_fence.c */
3370 int __must_check i915_vma_get_fence(struct i915_vma *vma);
3371 int __must_check i915_vma_put_fence(struct i915_vma *vma);
3374 * i915_vma_pin_fence - pin fencing state
3375 * @vma: vma to pin fencing for
3377 * This pins the fencing state (whether tiled or untiled) to make sure the
3378 * vma (and its object) is ready to be used as a scanout target. Fencing
3379 * status must be synchronize first by calling i915_vma_get_fence():
3381 * The resulting fence pin reference must be released again with
3382 * i915_vma_unpin_fence().
3386 * True if the vma has a fence, false otherwise.
3389 i915_vma_pin_fence(struct i915_vma *vma)
3392 vma->fence->pin_count++;
3399 * i915_vma_unpin_fence - unpin fencing state
3400 * @vma: vma to unpin fencing for
3402 * This releases the fence pin reference acquired through
3403 * i915_vma_pin_fence. It will handle both objects with and without an
3404 * attached fence correctly, callers do not need to distinguish this.
3407 i915_vma_unpin_fence(struct i915_vma *vma)
3410 GEM_BUG_ON(vma->fence->pin_count <= 0);
3411 vma->fence->pin_count--;
3415 void i915_gem_restore_fences(struct drm_device *dev);
3417 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3418 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3419 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3421 /* i915_gem_context.c */
3422 int __must_check i915_gem_context_init(struct drm_device *dev);
3423 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3424 void i915_gem_context_fini(struct drm_device *dev);
3425 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3426 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3427 int i915_switch_context(struct drm_i915_gem_request *req);
3428 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3429 void i915_gem_context_free(struct kref *ctx_ref);
3430 struct drm_i915_gem_object *
3431 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3432 struct i915_gem_context *
3433 i915_gem_context_create_gvt(struct drm_device *dev);
3435 static inline struct i915_gem_context *
3436 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3438 struct i915_gem_context *ctx;
3440 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3442 ctx = idr_find(&file_priv->context_idr, id);
3444 return ERR_PTR(-ENOENT);
3449 static inline struct i915_gem_context *
3450 i915_gem_context_get(struct i915_gem_context *ctx)
3452 kref_get(&ctx->ref);
3456 static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3458 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3459 kref_put(&ctx->ref, i915_gem_context_free);
3462 static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3464 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3467 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3468 struct drm_file *file);
3469 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3470 struct drm_file *file);
3471 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3472 struct drm_file *file_priv);
3473 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3474 struct drm_file *file_priv);
3475 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
3476 struct drm_file *file);
3478 /* i915_gem_evict.c */
3479 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3480 u64 min_size, u64 alignment,
3481 unsigned cache_level,
3484 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3485 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3487 /* belongs in i915_gem_gtt.h */
3488 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3491 if (INTEL_GEN(dev_priv) < 6)
3492 intel_gtt_chipset_flush();
3495 /* i915_gem_stolen.c */
3496 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3497 struct drm_mm_node *node, u64 size,
3498 unsigned alignment);
3499 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3500 struct drm_mm_node *node, u64 size,
3501 unsigned alignment, u64 start,
3503 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3504 struct drm_mm_node *node);
3505 int i915_gem_init_stolen(struct drm_device *dev);
3506 void i915_gem_cleanup_stolen(struct drm_device *dev);
3507 struct drm_i915_gem_object *
3508 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3509 struct drm_i915_gem_object *
3510 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3515 /* i915_gem_shrinker.c */
3516 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3517 unsigned long target,
3519 #define I915_SHRINK_PURGEABLE 0x1
3520 #define I915_SHRINK_UNBOUND 0x2
3521 #define I915_SHRINK_BOUND 0x4
3522 #define I915_SHRINK_ACTIVE 0x8
3523 #define I915_SHRINK_VMAPS 0x10
3524 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3525 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3526 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3529 /* i915_gem_tiling.c */
3530 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3532 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3534 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3535 i915_gem_object_is_tiled(obj);
3538 /* i915_debugfs.c */
3539 #ifdef CONFIG_DEBUG_FS
3540 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3541 void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3542 int i915_debugfs_connector_add(struct drm_connector *connector);
3543 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3545 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3546 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3547 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3549 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3552 /* i915_gpu_error.c */
3553 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3556 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3557 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3558 const struct i915_error_state_file_priv *error);
3559 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3560 struct drm_i915_private *i915,
3561 size_t count, loff_t pos);
3562 static inline void i915_error_state_buf_release(
3563 struct drm_i915_error_state_buf *eb)
3567 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3569 const char *error_msg);
3570 void i915_error_state_get(struct drm_device *dev,
3571 struct i915_error_state_file_priv *error_priv);
3572 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3573 void i915_destroy_error_state(struct drm_device *dev);
3577 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3579 const char *error_msg)
3583 static inline void i915_destroy_error_state(struct drm_device *dev)
3589 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3591 /* i915_cmd_parser.c */
3592 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3593 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3594 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3595 bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine);
3596 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3597 struct drm_i915_gem_object *batch_obj,
3598 struct drm_i915_gem_object *shadow_batch_obj,
3599 u32 batch_start_offset,
3603 /* i915_suspend.c */
3604 extern int i915_save_state(struct drm_device *dev);
3605 extern int i915_restore_state(struct drm_device *dev);
3608 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3609 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3612 extern int intel_setup_gmbus(struct drm_device *dev);
3613 extern void intel_teardown_gmbus(struct drm_device *dev);
3614 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3617 extern struct i2c_adapter *
3618 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3619 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3620 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3621 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3623 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3625 extern void intel_i2c_reset(struct drm_device *dev);
3628 int intel_bios_init(struct drm_i915_private *dev_priv);
3629 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3630 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3631 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3632 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3633 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3634 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3635 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3636 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3638 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3642 /* intel_opregion.c */
3644 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3645 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3646 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3647 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3648 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3650 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3652 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3654 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3655 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3656 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3657 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3661 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3666 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3670 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3678 extern void intel_register_dsm_handler(void);
3679 extern void intel_unregister_dsm_handler(void);
3681 static inline void intel_register_dsm_handler(void) { return; }
3682 static inline void intel_unregister_dsm_handler(void) { return; }
3683 #endif /* CONFIG_ACPI */
3685 /* intel_device_info.c */
3686 static inline struct intel_device_info *
3687 mkwrite_device_info(struct drm_i915_private *dev_priv)
3689 return (struct intel_device_info *)&dev_priv->info;
3692 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3693 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3696 extern void intel_modeset_init_hw(struct drm_device *dev);
3697 extern void intel_modeset_init(struct drm_device *dev);
3698 extern void intel_modeset_gem_init(struct drm_device *dev);
3699 extern void intel_modeset_cleanup(struct drm_device *dev);
3700 extern int intel_connector_register(struct drm_connector *);
3701 extern void intel_connector_unregister(struct drm_connector *);
3702 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3703 extern void intel_display_resume(struct drm_device *dev);
3704 extern void i915_redisable_vga(struct drm_device *dev);
3705 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3706 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3707 extern void intel_init_pch_refclk(struct drm_device *dev);
3708 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3709 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3712 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3713 struct drm_file *file);
3716 extern struct intel_overlay_error_state *
3717 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3718 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3719 struct intel_overlay_error_state *error);
3721 extern struct intel_display_error_state *
3722 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3723 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3724 struct drm_device *dev,
3725 struct intel_display_error_state *error);
3727 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3728 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3730 /* intel_sideband.c */
3731 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3732 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3733 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3734 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3735 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3736 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3737 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3738 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3739 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3740 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3741 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3742 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3743 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3744 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3745 enum intel_sbi_destination destination);
3746 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3747 enum intel_sbi_destination destination);
3748 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3749 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3751 /* intel_dpio_phy.c */
3752 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3753 u32 deemph_reg_value, u32 margin_reg_value,
3754 bool uniq_trans_scale);
3755 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3757 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3758 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3759 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3760 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3762 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3763 u32 demph_reg_value, u32 preemph_reg_value,
3764 u32 uniqtranscale_reg_value, u32 tx3_demph);
3765 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3766 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3767 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3769 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3770 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3772 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3773 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3775 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3776 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3777 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3778 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3780 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3781 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3782 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3783 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3785 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3786 * will be implemented using 2 32-bit writes in an arbitrary order with
3787 * an arbitrary delay between them. This can cause the hardware to
3788 * act upon the intermediate value, possibly leading to corruption and
3789 * machine death. For this reason we do not support I915_WRITE64, or
3790 * dev_priv->uncore.funcs.mmio_writeq.
3792 * When reading a 64-bit value as two 32-bit values, the delay may cause
3793 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3794 * occasionally a 64-bit register does not actualy support a full readq
3795 * and must be read using two 32-bit reads.
3797 * You have been warned.
3799 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3801 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3802 u32 upper, lower, old_upper, loop = 0; \
3803 upper = I915_READ(upper_reg); \
3805 old_upper = upper; \
3806 lower = I915_READ(lower_reg); \
3807 upper = I915_READ(upper_reg); \
3808 } while (upper != old_upper && loop++ < 2); \
3809 (u64)upper << 32 | lower; })
3811 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3812 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3814 #define __raw_read(x, s) \
3815 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3818 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3821 #define __raw_write(x, s) \
3822 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3823 i915_reg_t reg, uint##x##_t val) \
3825 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3840 /* These are untraced mmio-accessors that are only valid to be used inside
3841 * critical sections inside IRQ handlers where forcewake is explicitly
3843 * Think twice, and think again, before using these.
3844 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3845 * intel_uncore_forcewake_irqunlock().
3847 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3848 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3849 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3850 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3852 /* "Broadcast RGB" property */
3853 #define INTEL_BROADCAST_RGB_AUTO 0
3854 #define INTEL_BROADCAST_RGB_FULL 1
3855 #define INTEL_BROADCAST_RGB_LIMITED 2
3857 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3859 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3860 return VLV_VGACNTRL;
3861 else if (INTEL_GEN(dev_priv) >= 5)
3862 return CPU_VGACNTRL;
3867 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3869 unsigned long j = msecs_to_jiffies(m);
3871 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3874 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3876 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3879 static inline unsigned long
3880 timespec_to_jiffies_timeout(const struct timespec *value)
3882 unsigned long j = timespec_to_jiffies(value);
3884 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3888 * If you need to wait X milliseconds between events A and B, but event B
3889 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3890 * when event A happened, then just before event B you call this function and
3891 * pass the timestamp as the first argument, and X as the second argument.
3894 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3896 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3899 * Don't re-read the value of "jiffies" every time since it may change
3900 * behind our back and break the math.
3902 tmp_jiffies = jiffies;
3903 target_jiffies = timestamp_jiffies +
3904 msecs_to_jiffies_timeout(to_wait_ms);
3906 if (time_after(target_jiffies, tmp_jiffies)) {
3907 remaining_jiffies = target_jiffies - tmp_jiffies;
3908 while (remaining_jiffies)
3910 schedule_timeout_uninterruptible(remaining_jiffies);
3915 __i915_request_irq_complete(struct drm_i915_gem_request *req)
3917 struct intel_engine_cs *engine = req->engine;
3919 /* Before we do the heavier coherent read of the seqno,
3920 * check the value (hopefully) in the CPU cacheline.
3922 if (i915_gem_request_completed(req))
3925 /* Ensure our read of the seqno is coherent so that we
3926 * do not "miss an interrupt" (i.e. if this is the last
3927 * request and the seqno write from the GPU is not visible
3928 * by the time the interrupt fires, we will see that the
3929 * request is incomplete and go back to sleep awaiting
3930 * another interrupt that will never come.)
3932 * Strictly, we only need to do this once after an interrupt,
3933 * but it is easier and safer to do it every time the waiter
3936 if (engine->irq_seqno_barrier &&
3937 rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
3938 cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
3939 struct task_struct *tsk;
3941 /* The ordering of irq_posted versus applying the barrier
3942 * is crucial. The clearing of the current irq_posted must
3943 * be visible before we perform the barrier operation,
3944 * such that if a subsequent interrupt arrives, irq_posted
3945 * is reasserted and our task rewoken (which causes us to
3946 * do another __i915_request_irq_complete() immediately
3947 * and reapply the barrier). Conversely, if the clear
3948 * occurs after the barrier, then an interrupt that arrived
3949 * whilst we waited on the barrier would not trigger a
3950 * barrier on the next pass, and the read may not see the
3953 engine->irq_seqno_barrier(engine);
3955 /* If we consume the irq, but we are no longer the bottom-half,
3956 * the real bottom-half may not have serialised their own
3957 * seqno check with the irq-barrier (i.e. may have inspected
3958 * the seqno before we believe it coherent since they see
3959 * irq_posted == false but we are still running).
3962 tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
3963 if (tsk && tsk != current)
3964 /* Note that if the bottom-half is changed as we
3965 * are sending the wake-up, the new bottom-half will
3966 * be woken by whomever made the change. We only have
3967 * to worry about when we steal the irq-posted for
3970 wake_up_process(tsk);
3973 if (i915_gem_request_completed(req))
3980 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3981 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3984 int remap_io_mapping(struct vm_area_struct *vma,
3985 unsigned long addr, unsigned long pfn, unsigned long size,
3986 struct io_mapping *iomap);
3988 #define ptr_mask_bits(ptr) ({ \
3989 unsigned long __v = (unsigned long)(ptr); \
3990 (typeof(ptr))(__v & PAGE_MASK); \
3993 #define ptr_unpack_bits(ptr, bits) ({ \
3994 unsigned long __v = (unsigned long)(ptr); \
3995 (bits) = __v & ~PAGE_MASK; \
3996 (typeof(ptr))(__v & PAGE_MASK); \
3999 #define ptr_pack_bits(ptr, bits) \
4000 ((typeof(ptr))((unsigned long)(ptr) | (bits)))
4002 #define fetch_and_zero(ptr) ({ \
4003 typeof(*ptr) __T = *(ptr); \
4004 *(ptr) = (typeof(*ptr))0; \