2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
46 i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
48 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
50 static bool cpu_cache_is_coherent(struct drm_device *dev,
51 enum i915_cache_level level)
53 return HAS_LLC(dev) || level != I915_CACHE_NONE;
56 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
58 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
61 return obj->pin_display;
64 /* some bookkeeping */
65 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
68 spin_lock(&dev_priv->mm.object_stat_lock);
69 dev_priv->mm.object_count++;
70 dev_priv->mm.object_memory += size;
71 spin_unlock(&dev_priv->mm.object_stat_lock);
74 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
77 spin_lock(&dev_priv->mm.object_stat_lock);
78 dev_priv->mm.object_count--;
79 dev_priv->mm.object_memory -= size;
80 spin_unlock(&dev_priv->mm.object_stat_lock);
84 i915_gem_wait_for_error(struct i915_gpu_error *error)
88 #define EXIT_COND (!i915_reset_in_progress(error) || \
89 i915_terminally_wedged(error))
94 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
95 * userspace. If it takes that long something really bad is going on and
96 * we should simply try to bail out and fail as gracefully as possible.
98 ret = wait_event_interruptible_timeout(error->reset_queue,
102 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
104 } else if (ret < 0) {
112 int i915_mutex_lock_interruptible(struct drm_device *dev)
114 struct drm_i915_private *dev_priv = dev->dev_private;
117 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
121 ret = mutex_lock_interruptible(&dev->struct_mutex);
125 WARN_ON(i915_verify_lists(dev));
130 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
131 struct drm_file *file)
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 struct drm_i915_gem_get_aperture *args = data;
135 struct i915_gtt *ggtt = &dev_priv->gtt;
136 struct i915_vma *vma;
140 mutex_lock(&dev->struct_mutex);
141 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
143 pinned += vma->node.size;
144 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
146 pinned += vma->node.size;
147 mutex_unlock(&dev->struct_mutex);
149 args->aper_size = dev_priv->gtt.base.total;
150 args->aper_available_size = args->aper_size - pinned;
156 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
158 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
159 char *vaddr = obj->phys_handle->vaddr;
161 struct scatterlist *sg;
164 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
167 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
171 page = shmem_read_mapping_page(mapping, i);
173 return PTR_ERR(page);
175 src = kmap_atomic(page);
176 memcpy(vaddr, src, PAGE_SIZE);
177 drm_clflush_virt_range(vaddr, PAGE_SIZE);
180 page_cache_release(page);
184 i915_gem_chipset_flush(obj->base.dev);
186 st = kmalloc(sizeof(*st), GFP_KERNEL);
190 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
197 sg->length = obj->base.size;
199 sg_dma_address(sg) = obj->phys_handle->busaddr;
200 sg_dma_len(sg) = obj->base.size;
207 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
211 BUG_ON(obj->madv == __I915_MADV_PURGED);
213 ret = i915_gem_object_set_to_cpu_domain(obj, true);
215 /* In the event of a disaster, abandon all caches and
218 WARN_ON(ret != -EIO);
219 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
222 if (obj->madv == I915_MADV_DONTNEED)
226 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
227 char *vaddr = obj->phys_handle->vaddr;
230 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
234 page = shmem_read_mapping_page(mapping, i);
238 dst = kmap_atomic(page);
239 drm_clflush_virt_range(vaddr, PAGE_SIZE);
240 memcpy(dst, vaddr, PAGE_SIZE);
243 set_page_dirty(page);
244 if (obj->madv == I915_MADV_WILLNEED)
245 mark_page_accessed(page);
246 page_cache_release(page);
252 sg_free_table(obj->pages);
257 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
259 drm_pci_free(obj->base.dev, obj->phys_handle);
262 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
263 .get_pages = i915_gem_object_get_pages_phys,
264 .put_pages = i915_gem_object_put_pages_phys,
265 .release = i915_gem_object_release_phys,
269 drop_pages(struct drm_i915_gem_object *obj)
271 struct i915_vma *vma, *next;
274 drm_gem_object_reference(&obj->base);
275 list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link)
276 if (i915_vma_unbind(vma))
279 ret = i915_gem_object_put_pages(obj);
280 drm_gem_object_unreference(&obj->base);
286 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
289 drm_dma_handle_t *phys;
292 if (obj->phys_handle) {
293 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
299 if (obj->madv != I915_MADV_WILLNEED)
302 if (obj->base.filp == NULL)
305 ret = drop_pages(obj);
309 /* create a new object */
310 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
314 obj->phys_handle = phys;
315 obj->ops = &i915_gem_phys_ops;
317 return i915_gem_object_get_pages(obj);
321 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
322 struct drm_i915_gem_pwrite *args,
323 struct drm_file *file_priv)
325 struct drm_device *dev = obj->base.dev;
326 void *vaddr = obj->phys_handle->vaddr + args->offset;
327 char __user *user_data = to_user_ptr(args->data_ptr);
330 /* We manually control the domain here and pretend that it
331 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
333 ret = i915_gem_object_wait_rendering(obj, false);
337 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
338 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
339 unsigned long unwritten;
341 /* The physical object once assigned is fixed for the lifetime
342 * of the obj, so we can safely drop the lock and continue
345 mutex_unlock(&dev->struct_mutex);
346 unwritten = copy_from_user(vaddr, user_data, args->size);
347 mutex_lock(&dev->struct_mutex);
354 drm_clflush_virt_range(vaddr, args->size);
355 i915_gem_chipset_flush(dev);
358 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
362 void *i915_gem_object_alloc(struct drm_device *dev)
364 struct drm_i915_private *dev_priv = dev->dev_private;
365 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
368 void i915_gem_object_free(struct drm_i915_gem_object *obj)
370 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
371 kmem_cache_free(dev_priv->objects, obj);
375 i915_gem_create(struct drm_file *file,
376 struct drm_device *dev,
380 struct drm_i915_gem_object *obj;
384 size = roundup(size, PAGE_SIZE);
388 /* Allocate the new object */
389 obj = i915_gem_alloc_object(dev, size);
393 ret = drm_gem_handle_create(file, &obj->base, &handle);
394 /* drop reference from allocate - handle holds it now */
395 drm_gem_object_unreference_unlocked(&obj->base);
404 i915_gem_dumb_create(struct drm_file *file,
405 struct drm_device *dev,
406 struct drm_mode_create_dumb *args)
408 /* have to work out size/pitch and return them */
409 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
410 args->size = args->pitch * args->height;
411 return i915_gem_create(file, dev,
412 args->size, &args->handle);
416 * Creates a new mm object and returns a handle to it.
419 i915_gem_create_ioctl(struct drm_device *dev, void *data,
420 struct drm_file *file)
422 struct drm_i915_gem_create *args = data;
424 return i915_gem_create(file, dev,
425 args->size, &args->handle);
429 __copy_to_user_swizzled(char __user *cpu_vaddr,
430 const char *gpu_vaddr, int gpu_offset,
433 int ret, cpu_offset = 0;
436 int cacheline_end = ALIGN(gpu_offset + 1, 64);
437 int this_length = min(cacheline_end - gpu_offset, length);
438 int swizzled_gpu_offset = gpu_offset ^ 64;
440 ret = __copy_to_user(cpu_vaddr + cpu_offset,
441 gpu_vaddr + swizzled_gpu_offset,
446 cpu_offset += this_length;
447 gpu_offset += this_length;
448 length -= this_length;
455 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
456 const char __user *cpu_vaddr,
459 int ret, cpu_offset = 0;
462 int cacheline_end = ALIGN(gpu_offset + 1, 64);
463 int this_length = min(cacheline_end - gpu_offset, length);
464 int swizzled_gpu_offset = gpu_offset ^ 64;
466 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
467 cpu_vaddr + cpu_offset,
472 cpu_offset += this_length;
473 gpu_offset += this_length;
474 length -= this_length;
481 * Pins the specified object's pages and synchronizes the object with
482 * GPU accesses. Sets needs_clflush to non-zero if the caller should
483 * flush the object from the CPU cache.
485 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
492 if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0))
495 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
496 /* If we're not in the cpu read domain, set ourself into the gtt
497 * read domain and manually flush cachelines (if required). This
498 * optimizes for the case when the gpu will dirty the data
499 * anyway again before the next pread happens. */
500 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
502 ret = i915_gem_object_wait_rendering(obj, true);
507 ret = i915_gem_object_get_pages(obj);
511 i915_gem_object_pin_pages(obj);
516 /* Per-page copy function for the shmem pread fastpath.
517 * Flushes invalid cachelines before reading the target if
518 * needs_clflush is set. */
520 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
521 char __user *user_data,
522 bool page_do_bit17_swizzling, bool needs_clflush)
527 if (unlikely(page_do_bit17_swizzling))
530 vaddr = kmap_atomic(page);
532 drm_clflush_virt_range(vaddr + shmem_page_offset,
534 ret = __copy_to_user_inatomic(user_data,
535 vaddr + shmem_page_offset,
537 kunmap_atomic(vaddr);
539 return ret ? -EFAULT : 0;
543 shmem_clflush_swizzled_range(char *addr, unsigned long length,
546 if (unlikely(swizzled)) {
547 unsigned long start = (unsigned long) addr;
548 unsigned long end = (unsigned long) addr + length;
550 /* For swizzling simply ensure that we always flush both
551 * channels. Lame, but simple and it works. Swizzled
552 * pwrite/pread is far from a hotpath - current userspace
553 * doesn't use it at all. */
554 start = round_down(start, 128);
555 end = round_up(end, 128);
557 drm_clflush_virt_range((void *)start, end - start);
559 drm_clflush_virt_range(addr, length);
564 /* Only difference to the fast-path function is that this can handle bit17
565 * and uses non-atomic copy and kmap functions. */
567 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
568 char __user *user_data,
569 bool page_do_bit17_swizzling, bool needs_clflush)
576 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
578 page_do_bit17_swizzling);
580 if (page_do_bit17_swizzling)
581 ret = __copy_to_user_swizzled(user_data,
582 vaddr, shmem_page_offset,
585 ret = __copy_to_user(user_data,
586 vaddr + shmem_page_offset,
590 return ret ? - EFAULT : 0;
594 i915_gem_shmem_pread(struct drm_device *dev,
595 struct drm_i915_gem_object *obj,
596 struct drm_i915_gem_pread *args,
597 struct drm_file *file)
599 char __user *user_data;
602 int shmem_page_offset, page_length, ret = 0;
603 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
605 int needs_clflush = 0;
606 struct sg_page_iter sg_iter;
608 user_data = to_user_ptr(args->data_ptr);
611 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
613 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
617 offset = args->offset;
619 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
620 offset >> PAGE_SHIFT) {
621 struct page *page = sg_page_iter_page(&sg_iter);
626 /* Operation in this page
628 * shmem_page_offset = offset within page in shmem file
629 * page_length = bytes to copy for this page
631 shmem_page_offset = offset_in_page(offset);
632 page_length = remain;
633 if ((shmem_page_offset + page_length) > PAGE_SIZE)
634 page_length = PAGE_SIZE - shmem_page_offset;
636 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
637 (page_to_phys(page) & (1 << 17)) != 0;
639 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
640 user_data, page_do_bit17_swizzling,
645 mutex_unlock(&dev->struct_mutex);
647 if (likely(!i915.prefault_disable) && !prefaulted) {
648 ret = fault_in_multipages_writeable(user_data, remain);
649 /* Userspace is tricking us, but we've already clobbered
650 * its pages with the prefault and promised to write the
651 * data up to the first fault. Hence ignore any errors
652 * and just continue. */
657 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
658 user_data, page_do_bit17_swizzling,
661 mutex_lock(&dev->struct_mutex);
667 remain -= page_length;
668 user_data += page_length;
669 offset += page_length;
673 i915_gem_object_unpin_pages(obj);
679 * Reads data from the object referenced by handle.
681 * On error, the contents of *data are undefined.
684 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
685 struct drm_file *file)
687 struct drm_i915_gem_pread *args = data;
688 struct drm_i915_gem_object *obj;
694 if (!access_ok(VERIFY_WRITE,
695 to_user_ptr(args->data_ptr),
699 ret = i915_mutex_lock_interruptible(dev);
703 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
704 if (&obj->base == NULL) {
709 /* Bounds check source. */
710 if (args->offset > obj->base.size ||
711 args->size > obj->base.size - args->offset) {
716 /* prime objects have no backing filp to GEM pread/pwrite
719 if (!obj->base.filp) {
724 trace_i915_gem_object_pread(obj, args->offset, args->size);
726 ret = i915_gem_shmem_pread(dev, obj, args, file);
729 drm_gem_object_unreference(&obj->base);
731 mutex_unlock(&dev->struct_mutex);
735 /* This is the fast write path which cannot handle
736 * page faults in the source data
740 fast_user_write(struct io_mapping *mapping,
741 loff_t page_base, int page_offset,
742 char __user *user_data,
745 void __iomem *vaddr_atomic;
747 unsigned long unwritten;
749 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
750 /* We can use the cpu mem copy function because this is X86. */
751 vaddr = (void __force*)vaddr_atomic + page_offset;
752 unwritten = __copy_from_user_inatomic_nocache(vaddr,
754 io_mapping_unmap_atomic(vaddr_atomic);
759 * This is the fast pwrite path, where we copy the data directly from the
760 * user into the GTT, uncached.
763 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
764 struct drm_i915_gem_object *obj,
765 struct drm_i915_gem_pwrite *args,
766 struct drm_file *file)
768 struct drm_i915_private *dev_priv = dev->dev_private;
770 loff_t offset, page_base;
771 char __user *user_data;
772 int page_offset, page_length, ret;
774 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
778 ret = i915_gem_object_set_to_gtt_domain(obj, true);
782 ret = i915_gem_object_put_fence(obj);
786 user_data = to_user_ptr(args->data_ptr);
789 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
791 intel_fb_obj_invalidate(obj, ORIGIN_GTT);
794 /* Operation in this page
796 * page_base = page offset within aperture
797 * page_offset = offset within page
798 * page_length = bytes to copy for this page
800 page_base = offset & PAGE_MASK;
801 page_offset = offset_in_page(offset);
802 page_length = remain;
803 if ((page_offset + remain) > PAGE_SIZE)
804 page_length = PAGE_SIZE - page_offset;
806 /* If we get a fault while copying data, then (presumably) our
807 * source page isn't available. Return the error and we'll
808 * retry in the slow path.
810 if (fast_user_write(dev_priv->gtt.mappable, page_base,
811 page_offset, user_data, page_length)) {
816 remain -= page_length;
817 user_data += page_length;
818 offset += page_length;
822 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
824 i915_gem_object_ggtt_unpin(obj);
829 /* Per-page copy function for the shmem pwrite fastpath.
830 * Flushes invalid cachelines before writing to the target if
831 * needs_clflush_before is set and flushes out any written cachelines after
832 * writing if needs_clflush is set. */
834 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
835 char __user *user_data,
836 bool page_do_bit17_swizzling,
837 bool needs_clflush_before,
838 bool needs_clflush_after)
843 if (unlikely(page_do_bit17_swizzling))
846 vaddr = kmap_atomic(page);
847 if (needs_clflush_before)
848 drm_clflush_virt_range(vaddr + shmem_page_offset,
850 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
851 user_data, page_length);
852 if (needs_clflush_after)
853 drm_clflush_virt_range(vaddr + shmem_page_offset,
855 kunmap_atomic(vaddr);
857 return ret ? -EFAULT : 0;
860 /* Only difference to the fast-path function is that this can handle bit17
861 * and uses non-atomic copy and kmap functions. */
863 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
864 char __user *user_data,
865 bool page_do_bit17_swizzling,
866 bool needs_clflush_before,
867 bool needs_clflush_after)
873 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
874 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
876 page_do_bit17_swizzling);
877 if (page_do_bit17_swizzling)
878 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
882 ret = __copy_from_user(vaddr + shmem_page_offset,
885 if (needs_clflush_after)
886 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
888 page_do_bit17_swizzling);
891 return ret ? -EFAULT : 0;
895 i915_gem_shmem_pwrite(struct drm_device *dev,
896 struct drm_i915_gem_object *obj,
897 struct drm_i915_gem_pwrite *args,
898 struct drm_file *file)
902 char __user *user_data;
903 int shmem_page_offset, page_length, ret = 0;
904 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
905 int hit_slowpath = 0;
906 int needs_clflush_after = 0;
907 int needs_clflush_before = 0;
908 struct sg_page_iter sg_iter;
910 user_data = to_user_ptr(args->data_ptr);
913 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
915 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
916 /* If we're not in the cpu write domain, set ourself into the gtt
917 * write domain and manually flush cachelines (if required). This
918 * optimizes for the case when the gpu will use the data
919 * right away and we therefore have to clflush anyway. */
920 needs_clflush_after = cpu_write_needs_clflush(obj);
921 ret = i915_gem_object_wait_rendering(obj, false);
925 /* Same trick applies to invalidate partially written cachelines read
927 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
928 needs_clflush_before =
929 !cpu_cache_is_coherent(dev, obj->cache_level);
931 ret = i915_gem_object_get_pages(obj);
935 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
937 i915_gem_object_pin_pages(obj);
939 offset = args->offset;
942 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
943 offset >> PAGE_SHIFT) {
944 struct page *page = sg_page_iter_page(&sg_iter);
945 int partial_cacheline_write;
950 /* Operation in this page
952 * shmem_page_offset = offset within page in shmem file
953 * page_length = bytes to copy for this page
955 shmem_page_offset = offset_in_page(offset);
957 page_length = remain;
958 if ((shmem_page_offset + page_length) > PAGE_SIZE)
959 page_length = PAGE_SIZE - shmem_page_offset;
961 /* If we don't overwrite a cacheline completely we need to be
962 * careful to have up-to-date data by first clflushing. Don't
963 * overcomplicate things and flush the entire patch. */
964 partial_cacheline_write = needs_clflush_before &&
965 ((shmem_page_offset | page_length)
966 & (boot_cpu_data.x86_clflush_size - 1));
968 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
969 (page_to_phys(page) & (1 << 17)) != 0;
971 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
972 user_data, page_do_bit17_swizzling,
973 partial_cacheline_write,
974 needs_clflush_after);
979 mutex_unlock(&dev->struct_mutex);
980 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
981 user_data, page_do_bit17_swizzling,
982 partial_cacheline_write,
983 needs_clflush_after);
985 mutex_lock(&dev->struct_mutex);
991 remain -= page_length;
992 user_data += page_length;
993 offset += page_length;
997 i915_gem_object_unpin_pages(obj);
1001 * Fixup: Flush cpu caches in case we didn't flush the dirty
1002 * cachelines in-line while writing and the object moved
1003 * out of the cpu write domain while we've dropped the lock.
1005 if (!needs_clflush_after &&
1006 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1007 if (i915_gem_clflush_object(obj, obj->pin_display))
1008 needs_clflush_after = true;
1012 if (needs_clflush_after)
1013 i915_gem_chipset_flush(dev);
1015 obj->cache_dirty = true;
1017 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1022 * Writes data to the object referenced by handle.
1024 * On error, the contents of the buffer that were to be modified are undefined.
1027 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1028 struct drm_file *file)
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 struct drm_i915_gem_pwrite *args = data;
1032 struct drm_i915_gem_object *obj;
1035 if (args->size == 0)
1038 if (!access_ok(VERIFY_READ,
1039 to_user_ptr(args->data_ptr),
1043 if (likely(!i915.prefault_disable)) {
1044 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1050 intel_runtime_pm_get(dev_priv);
1052 ret = i915_mutex_lock_interruptible(dev);
1056 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1057 if (&obj->base == NULL) {
1062 /* Bounds check destination. */
1063 if (args->offset > obj->base.size ||
1064 args->size > obj->base.size - args->offset) {
1069 /* prime objects have no backing filp to GEM pread/pwrite
1072 if (!obj->base.filp) {
1077 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1080 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1081 * it would end up going through the fenced access, and we'll get
1082 * different detiling behavior between reading and writing.
1083 * pread/pwrite currently are reading and writing from the CPU
1084 * perspective, requiring manual detiling by the client.
1086 if (obj->tiling_mode == I915_TILING_NONE &&
1087 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1088 cpu_write_needs_clflush(obj)) {
1089 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1090 /* Note that the gtt paths might fail with non-page-backed user
1091 * pointers (e.g. gtt mappings when moving data between
1092 * textures). Fallback to the shmem path in that case. */
1095 if (ret == -EFAULT || ret == -ENOSPC) {
1096 if (obj->phys_handle)
1097 ret = i915_gem_phys_pwrite(obj, args, file);
1099 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1103 drm_gem_object_unreference(&obj->base);
1105 mutex_unlock(&dev->struct_mutex);
1107 intel_runtime_pm_put(dev_priv);
1113 i915_gem_check_wedge(struct i915_gpu_error *error,
1116 if (i915_reset_in_progress(error)) {
1117 /* Non-interruptible callers can't handle -EAGAIN, hence return
1118 * -EIO unconditionally for these. */
1122 /* Recovery complete, but the reset failed ... */
1123 if (i915_terminally_wedged(error))
1127 * Check if GPU Reset is in progress - we need intel_ring_begin
1128 * to work properly to reinit the hw state while the gpu is
1129 * still marked as reset-in-progress. Handle this with a flag.
1131 if (!error->reload_in_reset)
1138 static void fake_irq(unsigned long data)
1140 wake_up_process((struct task_struct *)data);
1143 static bool missed_irq(struct drm_i915_private *dev_priv,
1144 struct intel_engine_cs *engine)
1146 return test_bit(engine->id, &dev_priv->gpu_error.missed_irq_rings);
1149 static unsigned long local_clock_us(unsigned *cpu)
1153 /* Cheaply and approximately convert from nanoseconds to microseconds.
1154 * The result and subsequent calculations are also defined in the same
1155 * approximate microseconds units. The principal source of timing
1156 * error here is from the simple truncation.
1158 * Note that local_clock() is only defined wrt to the current CPU;
1159 * the comparisons are no longer valid if we switch CPUs. Instead of
1160 * blocking preemption for the entire busywait, we can detect the CPU
1161 * switch and use that as indicator of system load and a reason to
1162 * stop busywaiting, see busywait_stop().
1165 t = local_clock() >> 10;
1171 static bool busywait_stop(unsigned long timeout, unsigned cpu)
1175 if (time_after(local_clock_us(&this_cpu), timeout))
1178 return this_cpu != cpu;
1181 static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
1183 unsigned long timeout;
1186 /* When waiting for high frequency requests, e.g. during synchronous
1187 * rendering split between the CPU and GPU, the finite amount of time
1188 * required to set up the irq and wait upon it limits the response
1189 * rate. By busywaiting on the request completion for a short while we
1190 * can service the high frequency waits as quick as possible. However,
1191 * if it is a slow request, we want to sleep as quickly as possible.
1192 * The tradeoff between waiting and sleeping is roughly the time it
1193 * takes to sleep on a request, on the order of a microsecond.
1196 if (req->engine->irq_refcount)
1199 /* Only spin if we know the GPU is processing this request */
1200 if (!i915_gem_request_started(req, true))
1203 timeout = local_clock_us(&cpu) + 5;
1204 while (!need_resched()) {
1205 if (i915_gem_request_completed(req, true))
1208 if (signal_pending_state(state, current))
1211 if (busywait_stop(timeout, cpu))
1214 cpu_relax_lowlatency();
1217 if (i915_gem_request_completed(req, false))
1224 * __i915_wait_request - wait until execution of request has finished
1226 * @reset_counter: reset sequence associated with the given request
1227 * @interruptible: do an interruptible wait (normally yes)
1228 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1230 * Note: It is of utmost importance that the passed in seqno and reset_counter
1231 * values have been read by the caller in an smp safe manner. Where read-side
1232 * locks are involved, it is sufficient to read the reset_counter before
1233 * unlocking the lock that protects the seqno. For lockless tricks, the
1234 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1237 * Returns 0 if the request was found within the alloted time. Else returns the
1238 * errno with remaining time filled in timeout argument.
1240 int __i915_wait_request(struct drm_i915_gem_request *req,
1241 unsigned reset_counter,
1244 struct intel_rps_client *rps)
1246 struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
1247 struct drm_device *dev = engine->dev;
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 const bool irq_test_in_progress =
1250 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine);
1251 int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1253 unsigned long timeout_expire;
1254 s64 before = 0; /* Only to silence a compiler warning. */
1257 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1259 if (list_empty(&req->list))
1262 if (i915_gem_request_completed(req, true))
1267 if (WARN_ON(*timeout < 0))
1273 timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout);
1276 * Record current time in case interrupted by signal, or wedged.
1278 before = ktime_get_raw_ns();
1281 if (INTEL_INFO(dev_priv)->gen >= 6)
1282 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);
1284 trace_i915_gem_request_wait_begin(req);
1286 /* Optimistic spin for the next jiffie before touching IRQs */
1287 ret = __i915_spin_request(req, state);
1291 if (!irq_test_in_progress && WARN_ON(!engine->irq_get(engine))) {
1297 struct timer_list timer;
1299 prepare_to_wait(&engine->irq_queue, &wait, state);
1301 /* We need to check whether any gpu reset happened in between
1302 * the caller grabbing the seqno and now ... */
1303 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1304 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1305 * is truely gone. */
1306 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1312 if (i915_gem_request_completed(req, false)) {
1317 if (signal_pending_state(state, current)) {
1322 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1327 timer.function = NULL;
1328 if (timeout || missed_irq(dev_priv, engine)) {
1329 unsigned long expire;
1331 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1332 expire = missed_irq(dev_priv, engine) ? jiffies + 1 : timeout_expire;
1333 mod_timer(&timer, expire);
1338 if (timer.function) {
1339 del_singleshot_timer_sync(&timer);
1340 destroy_timer_on_stack(&timer);
1343 if (!irq_test_in_progress)
1344 engine->irq_put(engine);
1346 finish_wait(&engine->irq_queue, &wait);
1349 trace_i915_gem_request_wait_end(req);
1352 s64 tres = *timeout - (ktime_get_raw_ns() - before);
1354 *timeout = tres < 0 ? 0 : tres;
1357 * Apparently ktime isn't accurate enough and occasionally has a
1358 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1359 * things up to make the test happy. We allow up to 1 jiffy.
1361 * This is a regrssion from the timespec->ktime conversion.
1363 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1370 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
1371 struct drm_file *file)
1373 struct drm_i915_private *dev_private;
1374 struct drm_i915_file_private *file_priv;
1376 WARN_ON(!req || !file || req->file_priv);
1384 dev_private = req->engine->dev->dev_private;
1385 file_priv = file->driver_priv;
1387 spin_lock(&file_priv->mm.lock);
1388 req->file_priv = file_priv;
1389 list_add_tail(&req->client_list, &file_priv->mm.request_list);
1390 spin_unlock(&file_priv->mm.lock);
1392 req->pid = get_pid(task_pid(current));
1398 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1400 struct drm_i915_file_private *file_priv = request->file_priv;
1405 spin_lock(&file_priv->mm.lock);
1406 list_del(&request->client_list);
1407 request->file_priv = NULL;
1408 spin_unlock(&file_priv->mm.lock);
1410 put_pid(request->pid);
1411 request->pid = NULL;
1414 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
1416 trace_i915_gem_request_retire(request);
1418 /* We know the GPU must have read the request to have
1419 * sent us the seqno + interrupt, so use the position
1420 * of tail of the request to update the last known position
1423 * Note this requires that we are always called in request
1426 request->ringbuf->last_retired_head = request->postfix;
1428 list_del_init(&request->list);
1429 i915_gem_request_remove_from_client(request);
1431 i915_gem_request_unreference(request);
1435 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
1437 struct intel_engine_cs *engine = req->engine;
1438 struct drm_i915_gem_request *tmp;
1440 lockdep_assert_held(&engine->dev->struct_mutex);
1442 if (list_empty(&req->list))
1446 tmp = list_first_entry(&engine->request_list,
1447 typeof(*tmp), list);
1449 i915_gem_request_retire(tmp);
1450 } while (tmp != req);
1452 WARN_ON(i915_verify_lists(engine->dev));
1456 * Waits for a request to be signaled, and cleans up the
1457 * request and object lists appropriately for that event.
1460 i915_wait_request(struct drm_i915_gem_request *req)
1462 struct drm_device *dev;
1463 struct drm_i915_private *dev_priv;
1467 BUG_ON(req == NULL);
1469 dev = req->engine->dev;
1470 dev_priv = dev->dev_private;
1471 interruptible = dev_priv->mm.interruptible;
1473 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1475 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1479 ret = __i915_wait_request(req,
1480 atomic_read(&dev_priv->gpu_error.reset_counter),
1481 interruptible, NULL, NULL);
1485 __i915_gem_request_retire__upto(req);
1490 * Ensures that all rendering to the object has completed and the object is
1491 * safe to unbind from the GTT or access from the CPU.
1494 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1503 if (obj->last_write_req != NULL) {
1504 ret = i915_wait_request(obj->last_write_req);
1508 i = obj->last_write_req->engine->id;
1509 if (obj->last_read_req[i] == obj->last_write_req)
1510 i915_gem_object_retire__read(obj, i);
1512 i915_gem_object_retire__write(obj);
1515 for (i = 0; i < I915_NUM_ENGINES; i++) {
1516 if (obj->last_read_req[i] == NULL)
1519 ret = i915_wait_request(obj->last_read_req[i]);
1523 i915_gem_object_retire__read(obj, i);
1525 RQ_BUG_ON(obj->active);
1532 i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
1533 struct drm_i915_gem_request *req)
1535 int ring = req->engine->id;
1537 if (obj->last_read_req[ring] == req)
1538 i915_gem_object_retire__read(obj, ring);
1539 else if (obj->last_write_req == req)
1540 i915_gem_object_retire__write(obj);
1542 __i915_gem_request_retire__upto(req);
1545 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1546 * as the object state may change during this call.
1548 static __must_check int
1549 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1550 struct intel_rps_client *rps,
1553 struct drm_device *dev = obj->base.dev;
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
1556 unsigned reset_counter;
1559 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1560 BUG_ON(!dev_priv->mm.interruptible);
1565 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1569 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1572 struct drm_i915_gem_request *req;
1574 req = obj->last_write_req;
1578 requests[n++] = i915_gem_request_reference(req);
1580 for (i = 0; i < I915_NUM_ENGINES; i++) {
1581 struct drm_i915_gem_request *req;
1583 req = obj->last_read_req[i];
1587 requests[n++] = i915_gem_request_reference(req);
1591 mutex_unlock(&dev->struct_mutex);
1592 for (i = 0; ret == 0 && i < n; i++)
1593 ret = __i915_wait_request(requests[i], reset_counter, true,
1595 mutex_lock(&dev->struct_mutex);
1597 for (i = 0; i < n; i++) {
1599 i915_gem_object_retire_request(obj, requests[i]);
1600 i915_gem_request_unreference(requests[i]);
1606 static struct intel_rps_client *to_rps_client(struct drm_file *file)
1608 struct drm_i915_file_private *fpriv = file->driver_priv;
1613 * Called when user space prepares to use an object with the CPU, either
1614 * through the mmap ioctl's mapping or a GTT mapping.
1617 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1618 struct drm_file *file)
1620 struct drm_i915_gem_set_domain *args = data;
1621 struct drm_i915_gem_object *obj;
1622 uint32_t read_domains = args->read_domains;
1623 uint32_t write_domain = args->write_domain;
1626 /* Only handle setting domains to types used by the CPU. */
1627 if (write_domain & I915_GEM_GPU_DOMAINS)
1630 if (read_domains & I915_GEM_GPU_DOMAINS)
1633 /* Having something in the write domain implies it's in the read
1634 * domain, and only that read domain. Enforce that in the request.
1636 if (write_domain != 0 && read_domains != write_domain)
1639 ret = i915_mutex_lock_interruptible(dev);
1643 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1644 if (&obj->base == NULL) {
1649 /* Try to flush the object off the GPU without holding the lock.
1650 * We will repeat the flush holding the lock in the normal manner
1651 * to catch cases where we are gazumped.
1653 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1654 to_rps_client(file),
1659 if (read_domains & I915_GEM_DOMAIN_GTT)
1660 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1662 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1664 if (write_domain != 0)
1665 intel_fb_obj_invalidate(obj,
1666 write_domain == I915_GEM_DOMAIN_GTT ?
1667 ORIGIN_GTT : ORIGIN_CPU);
1670 drm_gem_object_unreference(&obj->base);
1672 mutex_unlock(&dev->struct_mutex);
1677 * Called when user space has done writes to this buffer
1680 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1681 struct drm_file *file)
1683 struct drm_i915_gem_sw_finish *args = data;
1684 struct drm_i915_gem_object *obj;
1687 ret = i915_mutex_lock_interruptible(dev);
1691 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1692 if (&obj->base == NULL) {
1697 /* Pinned buffers may be scanout, so flush the cache */
1698 if (obj->pin_display)
1699 i915_gem_object_flush_cpu_write_domain(obj);
1701 drm_gem_object_unreference(&obj->base);
1703 mutex_unlock(&dev->struct_mutex);
1708 * Maps the contents of an object, returning the address it is mapped
1711 * While the mapping holds a reference on the contents of the object, it doesn't
1712 * imply a ref on the object itself.
1716 * DRM driver writers who look a this function as an example for how to do GEM
1717 * mmap support, please don't implement mmap support like here. The modern way
1718 * to implement DRM mmap support is with an mmap offset ioctl (like
1719 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1720 * That way debug tooling like valgrind will understand what's going on, hiding
1721 * the mmap call in a driver private ioctl will break that. The i915 driver only
1722 * does cpu mmaps this way because we didn't know better.
1725 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1726 struct drm_file *file)
1728 struct drm_i915_gem_mmap *args = data;
1729 struct drm_gem_object *obj;
1732 if (args->flags & ~(I915_MMAP_WC))
1735 if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1738 obj = drm_gem_object_lookup(dev, file, args->handle);
1742 /* prime objects have no backing filp to GEM mmap
1746 drm_gem_object_unreference_unlocked(obj);
1750 addr = vm_mmap(obj->filp, 0, args->size,
1751 PROT_READ | PROT_WRITE, MAP_SHARED,
1753 if (args->flags & I915_MMAP_WC) {
1754 struct mm_struct *mm = current->mm;
1755 struct vm_area_struct *vma;
1757 down_write(&mm->mmap_sem);
1758 vma = find_vma(mm, addr);
1761 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1764 up_write(&mm->mmap_sem);
1766 drm_gem_object_unreference_unlocked(obj);
1767 if (IS_ERR((void *)addr))
1770 args->addr_ptr = (uint64_t) addr;
1776 * i915_gem_fault - fault a page into the GTT
1777 * @vma: VMA in question
1780 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1781 * from userspace. The fault handler takes care of binding the object to
1782 * the GTT (if needed), allocating and programming a fence register (again,
1783 * only if needed based on whether the old reg is still valid or the object
1784 * is tiled) and inserting a new PTE into the faulting process.
1786 * Note that the faulting process may involve evicting existing objects
1787 * from the GTT and/or fence registers to make room. So performance may
1788 * suffer if the GTT working set is large or there are few fence registers
1791 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1793 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1794 struct drm_device *dev = obj->base.dev;
1795 struct drm_i915_private *dev_priv = dev->dev_private;
1796 struct i915_ggtt_view view = i915_ggtt_view_normal;
1797 pgoff_t page_offset;
1800 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1802 intel_runtime_pm_get(dev_priv);
1804 /* We don't use vmf->pgoff since that has the fake offset */
1805 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1808 ret = i915_mutex_lock_interruptible(dev);
1812 trace_i915_gem_object_fault(obj, page_offset, true, write);
1814 /* Try to flush the object off the GPU first without holding the lock.
1815 * Upon reacquiring the lock, we will perform our sanity checks and then
1816 * repeat the flush holding the lock in the normal manner to catch cases
1817 * where we are gazumped.
1819 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1823 /* Access to snoopable pages through the GTT is incoherent. */
1824 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1829 /* Use a partial view if the object is bigger than the aperture. */
1830 if (obj->base.size >= dev_priv->gtt.mappable_end &&
1831 obj->tiling_mode == I915_TILING_NONE) {
1832 static const unsigned int chunk_size = 256; // 1 MiB
1834 memset(&view, 0, sizeof(view));
1835 view.type = I915_GGTT_VIEW_PARTIAL;
1836 view.params.partial.offset = rounddown(page_offset, chunk_size);
1837 view.params.partial.size =
1840 (vma->vm_end - vma->vm_start)/PAGE_SIZE -
1841 view.params.partial.offset);
1844 /* Now pin it into the GTT if needed */
1845 ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
1849 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1853 ret = i915_gem_object_get_fence(obj);
1857 /* Finally, remap it using the new GTT offset */
1858 pfn = dev_priv->gtt.mappable_base +
1859 i915_gem_obj_ggtt_offset_view(obj, &view);
1862 if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
1863 /* Overriding existing pages in partial view does not cause
1864 * us any trouble as TLBs are still valid because the fault
1865 * is due to userspace losing part of the mapping or never
1866 * having accessed it before (at this partials' range).
1868 unsigned long base = vma->vm_start +
1869 (view.params.partial.offset << PAGE_SHIFT);
1872 for (i = 0; i < view.params.partial.size; i++) {
1873 ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
1878 obj->fault_mappable = true;
1880 if (!obj->fault_mappable) {
1881 unsigned long size = min_t(unsigned long,
1882 vma->vm_end - vma->vm_start,
1886 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1887 ret = vm_insert_pfn(vma,
1888 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1894 obj->fault_mappable = true;
1896 ret = vm_insert_pfn(vma,
1897 (unsigned long)vmf->virtual_address,
1901 i915_gem_object_ggtt_unpin_view(obj, &view);
1903 mutex_unlock(&dev->struct_mutex);
1908 * We eat errors when the gpu is terminally wedged to avoid
1909 * userspace unduly crashing (gl has no provisions for mmaps to
1910 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1911 * and so needs to be reported.
1913 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1914 ret = VM_FAULT_SIGBUS;
1919 * EAGAIN means the gpu is hung and we'll wait for the error
1920 * handler to reset everything when re-faulting in
1921 * i915_mutex_lock_interruptible.
1928 * EBUSY is ok: this just means that another thread
1929 * already did the job.
1931 ret = VM_FAULT_NOPAGE;
1938 ret = VM_FAULT_SIGBUS;
1941 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1942 ret = VM_FAULT_SIGBUS;
1946 intel_runtime_pm_put(dev_priv);
1951 * i915_gem_release_mmap - remove physical page mappings
1952 * @obj: obj in question
1954 * Preserve the reservation of the mmapping with the DRM core code, but
1955 * relinquish ownership of the pages back to the system.
1957 * It is vital that we remove the page mapping if we have mapped a tiled
1958 * object through the GTT and then lose the fence register due to
1959 * resource pressure. Similarly if the object has been moved out of the
1960 * aperture, than pages mapped into userspace must be revoked. Removing the
1961 * mapping will then trigger a page fault on the next user access, allowing
1962 * fixup by i915_gem_fault().
1965 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1967 if (!obj->fault_mappable)
1970 drm_vma_node_unmap(&obj->base.vma_node,
1971 obj->base.dev->anon_inode->i_mapping);
1972 obj->fault_mappable = false;
1976 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1978 struct drm_i915_gem_object *obj;
1980 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1981 i915_gem_release_mmap(obj);
1985 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1989 if (INTEL_INFO(dev)->gen >= 4 ||
1990 tiling_mode == I915_TILING_NONE)
1993 /* Previous chips need a power-of-two fence region when tiling */
1994 if (INTEL_INFO(dev)->gen == 3)
1995 gtt_size = 1024*1024;
1997 gtt_size = 512*1024;
1999 while (gtt_size < size)
2006 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2007 * @obj: object to check
2009 * Return the required GTT alignment for an object, taking into account
2010 * potential fence register mapping.
2013 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2014 int tiling_mode, bool fenced)
2017 * Minimum alignment is 4k (GTT page size), but might be greater
2018 * if a fence register is needed for the object.
2020 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
2021 tiling_mode == I915_TILING_NONE)
2025 * Previous chips need to be aligned to the size of the smallest
2026 * fence register that can contain the object.
2028 return i915_gem_get_gtt_size(dev, size, tiling_mode);
2031 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2033 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2036 if (drm_vma_node_has_offset(&obj->base.vma_node))
2039 dev_priv->mm.shrinker_no_lock_stealing = true;
2041 ret = drm_gem_create_mmap_offset(&obj->base);
2045 /* Badly fragmented mmap space? The only way we can recover
2046 * space is by destroying unwanted objects. We can't randomly release
2047 * mmap_offsets as userspace expects them to be persistent for the
2048 * lifetime of the objects. The closest we can is to release the
2049 * offsets on purgeable objects by truncating it and marking it purged,
2050 * which prevents userspace from ever using that object again.
2052 i915_gem_shrink(dev_priv,
2053 obj->base.size >> PAGE_SHIFT,
2055 I915_SHRINK_UNBOUND |
2056 I915_SHRINK_PURGEABLE);
2057 ret = drm_gem_create_mmap_offset(&obj->base);
2061 i915_gem_shrink_all(dev_priv);
2062 ret = drm_gem_create_mmap_offset(&obj->base);
2064 dev_priv->mm.shrinker_no_lock_stealing = false;
2069 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2071 drm_gem_free_mmap_offset(&obj->base);
2075 i915_gem_mmap_gtt(struct drm_file *file,
2076 struct drm_device *dev,
2080 struct drm_i915_gem_object *obj;
2083 ret = i915_mutex_lock_interruptible(dev);
2087 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
2088 if (&obj->base == NULL) {
2093 if (obj->madv != I915_MADV_WILLNEED) {
2094 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2099 ret = i915_gem_object_create_mmap_offset(obj);
2103 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2106 drm_gem_object_unreference(&obj->base);
2108 mutex_unlock(&dev->struct_mutex);
2113 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2115 * @data: GTT mapping ioctl data
2116 * @file: GEM object info
2118 * Simply returns the fake offset to userspace so it can mmap it.
2119 * The mmap call will end up in drm_gem_mmap(), which will set things
2120 * up so we can get faults in the handler above.
2122 * The fault handler will take care of binding the object into the GTT
2123 * (since it may have been evicted to make room for something), allocating
2124 * a fence register, and mapping the appropriate aperture address into
2128 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2129 struct drm_file *file)
2131 struct drm_i915_gem_mmap_gtt *args = data;
2133 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2136 /* Immediately discard the backing storage */
2138 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2140 i915_gem_object_free_mmap_offset(obj);
2142 if (obj->base.filp == NULL)
2145 /* Our goal here is to return as much of the memory as
2146 * is possible back to the system as we are called from OOM.
2147 * To do this we must instruct the shmfs to drop all of its
2148 * backing pages, *now*.
2150 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2151 obj->madv = __I915_MADV_PURGED;
2154 /* Try to discard unwanted pages */
2156 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2158 struct address_space *mapping;
2160 switch (obj->madv) {
2161 case I915_MADV_DONTNEED:
2162 i915_gem_object_truncate(obj);
2163 case __I915_MADV_PURGED:
2167 if (obj->base.filp == NULL)
2170 mapping = file_inode(obj->base.filp)->i_mapping,
2171 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2175 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2177 struct sg_page_iter sg_iter;
2180 BUG_ON(obj->madv == __I915_MADV_PURGED);
2182 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2184 /* In the event of a disaster, abandon all caches and
2185 * hope for the best.
2187 WARN_ON(ret != -EIO);
2188 i915_gem_clflush_object(obj, true);
2189 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2192 i915_gem_gtt_finish_object(obj);
2194 if (i915_gem_object_needs_bit17_swizzle(obj))
2195 i915_gem_object_save_bit_17_swizzle(obj);
2197 if (obj->madv == I915_MADV_DONTNEED)
2200 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2201 struct page *page = sg_page_iter_page(&sg_iter);
2204 set_page_dirty(page);
2206 if (obj->madv == I915_MADV_WILLNEED)
2207 mark_page_accessed(page);
2209 page_cache_release(page);
2213 sg_free_table(obj->pages);
2218 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2220 const struct drm_i915_gem_object_ops *ops = obj->ops;
2222 if (obj->pages == NULL)
2225 if (obj->pages_pin_count)
2228 BUG_ON(i915_gem_obj_bound_any(obj));
2230 /* ->put_pages might need to allocate memory for the bit17 swizzle
2231 * array, hence protect them from being reaped by removing them from gtt
2233 list_del(&obj->global_list);
2235 ops->put_pages(obj);
2238 i915_gem_object_invalidate(obj);
2244 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2246 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2248 struct address_space *mapping;
2249 struct sg_table *st;
2250 struct scatterlist *sg;
2251 struct sg_page_iter sg_iter;
2253 unsigned long last_pfn = 0; /* suppress gcc warning */
2257 /* Assert that the object is not currently in any GPU domain. As it
2258 * wasn't in the GTT, there shouldn't be any way it could have been in
2261 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2262 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2264 st = kmalloc(sizeof(*st), GFP_KERNEL);
2268 page_count = obj->base.size / PAGE_SIZE;
2269 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2274 /* Get the list of pages out of our struct file. They'll be pinned
2275 * at this point until we release them.
2277 * Fail silently without starting the shrinker
2279 mapping = file_inode(obj->base.filp)->i_mapping;
2280 gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2281 gfp |= __GFP_NORETRY | __GFP_NOWARN;
2284 for (i = 0; i < page_count; i++) {
2285 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2287 i915_gem_shrink(dev_priv,
2290 I915_SHRINK_UNBOUND |
2291 I915_SHRINK_PURGEABLE);
2292 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2295 /* We've tried hard to allocate the memory by reaping
2296 * our own buffer, now let the real VM do its job and
2297 * go down in flames if truly OOM.
2299 i915_gem_shrink_all(dev_priv);
2300 page = shmem_read_mapping_page(mapping, i);
2302 ret = PTR_ERR(page);
2306 #ifdef CONFIG_SWIOTLB
2307 if (swiotlb_nr_tbl()) {
2309 sg_set_page(sg, page, PAGE_SIZE, 0);
2314 if (!i || page_to_pfn(page) != last_pfn + 1) {
2318 sg_set_page(sg, page, PAGE_SIZE, 0);
2320 sg->length += PAGE_SIZE;
2322 last_pfn = page_to_pfn(page);
2324 /* Check that the i965g/gm workaround works. */
2325 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2327 #ifdef CONFIG_SWIOTLB
2328 if (!swiotlb_nr_tbl())
2333 ret = i915_gem_gtt_prepare_object(obj);
2337 if (i915_gem_object_needs_bit17_swizzle(obj))
2338 i915_gem_object_do_bit_17_swizzle(obj);
2340 if (obj->tiling_mode != I915_TILING_NONE &&
2341 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2342 i915_gem_object_pin_pages(obj);
2348 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2349 page_cache_release(sg_page_iter_page(&sg_iter));
2353 /* shmemfs first checks if there is enough memory to allocate the page
2354 * and reports ENOSPC should there be insufficient, along with the usual
2355 * ENOMEM for a genuine allocation failure.
2357 * We use ENOSPC in our driver to mean that we have run out of aperture
2358 * space and so want to translate the error from shmemfs back to our
2359 * usual understanding of ENOMEM.
2367 /* Ensure that the associated pages are gathered from the backing storage
2368 * and pinned into our object. i915_gem_object_get_pages() may be called
2369 * multiple times before they are released by a single call to
2370 * i915_gem_object_put_pages() - once the pages are no longer referenced
2371 * either as a result of memory pressure (reaping pages under the shrinker)
2372 * or as the object is itself released.
2375 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2377 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2378 const struct drm_i915_gem_object_ops *ops = obj->ops;
2384 if (obj->madv != I915_MADV_WILLNEED) {
2385 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2389 BUG_ON(obj->pages_pin_count);
2391 ret = ops->get_pages(obj);
2395 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2397 obj->get_page.sg = obj->pages->sgl;
2398 obj->get_page.last = 0;
2403 void i915_vma_move_to_active(struct i915_vma *vma,
2404 struct drm_i915_gem_request *req)
2406 struct drm_i915_gem_object *obj = vma->obj;
2407 struct intel_engine_cs *engine;
2409 engine = i915_gem_request_get_engine(req);
2411 /* Add a reference if we're newly entering the active list. */
2412 if (obj->active == 0)
2413 drm_gem_object_reference(&obj->base);
2414 obj->active |= intel_engine_flag(engine);
2416 list_move_tail(&obj->ring_list[engine->id], &engine->active_list);
2417 i915_gem_request_assign(&obj->last_read_req[engine->id], req);
2419 list_move_tail(&vma->vm_link, &vma->vm->active_list);
2423 i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
2425 RQ_BUG_ON(obj->last_write_req == NULL);
2426 RQ_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine)));
2428 i915_gem_request_assign(&obj->last_write_req, NULL);
2429 intel_fb_obj_flush(obj, true, ORIGIN_CS);
2433 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
2435 struct i915_vma *vma;
2437 RQ_BUG_ON(obj->last_read_req[ring] == NULL);
2438 RQ_BUG_ON(!(obj->active & (1 << ring)));
2440 list_del_init(&obj->ring_list[ring]);
2441 i915_gem_request_assign(&obj->last_read_req[ring], NULL);
2443 if (obj->last_write_req && obj->last_write_req->engine->id == ring)
2444 i915_gem_object_retire__write(obj);
2446 obj->active &= ~(1 << ring);
2450 /* Bump our place on the bound list to keep it roughly in LRU order
2451 * so that we don't steal from recently used but inactive objects
2452 * (unless we are forced to ofc!)
2454 list_move_tail(&obj->global_list,
2455 &to_i915(obj->base.dev)->mm.bound_list);
2457 list_for_each_entry(vma, &obj->vma_list, obj_link) {
2458 if (!list_empty(&vma->vm_link))
2459 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
2462 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2463 drm_gem_object_unreference(&obj->base);
2467 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2469 struct drm_i915_private *dev_priv = dev->dev_private;
2470 struct intel_engine_cs *engine;
2473 /* Carefully retire all requests without writing to the rings */
2474 for_each_engine(engine, dev_priv, i) {
2475 ret = intel_engine_idle(engine);
2479 i915_gem_retire_requests(dev);
2481 /* Finally reset hw state */
2482 for_each_engine(engine, dev_priv, i) {
2483 intel_ring_init_seqno(engine, seqno);
2485 for (j = 0; j < ARRAY_SIZE(engine->semaphore.sync_seqno); j++)
2486 engine->semaphore.sync_seqno[j] = 0;
2492 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2494 struct drm_i915_private *dev_priv = dev->dev_private;
2500 /* HWS page needs to be set less than what we
2501 * will inject to ring
2503 ret = i915_gem_init_seqno(dev, seqno - 1);
2507 /* Carefully set the last_seqno value so that wrap
2508 * detection still works
2510 dev_priv->next_seqno = seqno;
2511 dev_priv->last_seqno = seqno - 1;
2512 if (dev_priv->last_seqno == 0)
2513 dev_priv->last_seqno--;
2519 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2521 struct drm_i915_private *dev_priv = dev->dev_private;
2523 /* reserve 0 for non-seqno */
2524 if (dev_priv->next_seqno == 0) {
2525 int ret = i915_gem_init_seqno(dev, 0);
2529 dev_priv->next_seqno = 1;
2532 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2537 * NB: This function is not allowed to fail. Doing so would mean the the
2538 * request is not being tracked for completion but the work itself is
2539 * going to happen on the hardware. This would be a Bad Thing(tm).
2541 void __i915_add_request(struct drm_i915_gem_request *request,
2542 struct drm_i915_gem_object *obj,
2545 struct intel_engine_cs *engine;
2546 struct drm_i915_private *dev_priv;
2547 struct intel_ringbuffer *ringbuf;
2551 if (WARN_ON(request == NULL))
2554 engine = request->engine;
2555 dev_priv = engine->dev->dev_private;
2556 ringbuf = request->ringbuf;
2559 * To ensure that this call will not fail, space for its emissions
2560 * should already have been reserved in the ring buffer. Let the ring
2561 * know that it is time to use that space up.
2563 intel_ring_reserved_space_use(ringbuf);
2565 request_start = intel_ring_get_tail(ringbuf);
2567 * Emit any outstanding flushes - execbuf can fail to emit the flush
2568 * after having emitted the batchbuffer command. Hence we need to fix
2569 * things up similar to emitting the lazy request. The difference here
2570 * is that the flush _must_ happen before the next request, no matter
2574 if (i915.enable_execlists)
2575 ret = logical_ring_flush_all_caches(request);
2577 ret = intel_ring_flush_all_caches(request);
2578 /* Not allowed to fail! */
2579 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
2582 /* Record the position of the start of the request so that
2583 * should we detect the updated seqno part-way through the
2584 * GPU processing the request, we never over-estimate the
2585 * position of the head.
2587 request->postfix = intel_ring_get_tail(ringbuf);
2589 if (i915.enable_execlists)
2590 ret = engine->emit_request(request);
2592 ret = engine->add_request(request);
2594 request->tail = intel_ring_get_tail(ringbuf);
2596 /* Not allowed to fail! */
2597 WARN(ret, "emit|add_request failed: %d!\n", ret);
2599 request->head = request_start;
2601 /* Whilst this request exists, batch_obj will be on the
2602 * active_list, and so will hold the active reference. Only when this
2603 * request is retired will the the batch_obj be moved onto the
2604 * inactive_list and lose its active reference. Hence we do not need
2605 * to explicitly hold another reference here.
2607 request->batch_obj = obj;
2609 request->emitted_jiffies = jiffies;
2610 request->previous_seqno = engine->last_submitted_seqno;
2611 engine->last_submitted_seqno = request->seqno;
2612 list_add_tail(&request->list, &engine->request_list);
2614 trace_i915_gem_request_add(request);
2616 i915_queue_hangcheck(engine->dev);
2618 queue_delayed_work(dev_priv->wq,
2619 &dev_priv->mm.retire_work,
2620 round_jiffies_up_relative(HZ));
2621 intel_mark_busy(dev_priv->dev);
2623 /* Sanity check that the reserved size was large enough. */
2624 intel_ring_reserved_space_end(ringbuf);
2627 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2628 const struct intel_context *ctx)
2630 unsigned long elapsed;
2632 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2634 if (ctx->hang_stats.banned)
2637 if (ctx->hang_stats.ban_period_seconds &&
2638 elapsed <= ctx->hang_stats.ban_period_seconds) {
2639 if (!i915_gem_context_is_default(ctx)) {
2640 DRM_DEBUG("context hanging too fast, banning!\n");
2642 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2643 if (i915_stop_ring_allow_warn(dev_priv))
2644 DRM_ERROR("gpu hanging too fast, banning!\n");
2652 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2653 struct intel_context *ctx,
2656 struct i915_ctx_hang_stats *hs;
2661 hs = &ctx->hang_stats;
2664 hs->banned = i915_context_is_banned(dev_priv, ctx);
2666 hs->guilty_ts = get_seconds();
2668 hs->batch_pending++;
2672 void i915_gem_request_free(struct kref *req_ref)
2674 struct drm_i915_gem_request *req = container_of(req_ref,
2676 struct intel_context *ctx = req->ctx;
2679 i915_gem_request_remove_from_client(req);
2682 if (i915.enable_execlists && ctx != req->i915->kernel_context)
2683 intel_lr_context_unpin(ctx, req->engine);
2685 i915_gem_context_unreference(ctx);
2688 kmem_cache_free(req->i915->requests, req);
2692 __i915_gem_request_alloc(struct intel_engine_cs *engine,
2693 struct intel_context *ctx,
2694 struct drm_i915_gem_request **req_out)
2696 struct drm_i915_private *dev_priv = to_i915(engine->dev);
2697 struct drm_i915_gem_request *req;
2705 req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
2709 ret = i915_gem_get_seqno(engine->dev, &req->seqno);
2713 kref_init(&req->ref);
2714 req->i915 = dev_priv;
2715 req->engine = engine;
2717 i915_gem_context_reference(req->ctx);
2719 if (i915.enable_execlists)
2720 ret = intel_logical_ring_alloc_request_extras(req);
2722 ret = intel_ring_alloc_request_extras(req);
2724 i915_gem_context_unreference(req->ctx);
2729 * Reserve space in the ring buffer for all the commands required to
2730 * eventually emit this request. This is to guarantee that the
2731 * i915_add_request() call can't fail. Note that the reserve may need
2732 * to be redone if the request is not actually submitted straight
2733 * away, e.g. because a GPU scheduler has deferred it.
2735 if (i915.enable_execlists)
2736 ret = intel_logical_ring_reserve_space(req);
2738 ret = intel_ring_reserve_space(req);
2741 * At this point, the request is fully allocated even if not
2742 * fully prepared. Thus it can be cleaned up using the proper
2745 i915_gem_request_cancel(req);
2753 kmem_cache_free(dev_priv->requests, req);
2758 * i915_gem_request_alloc - allocate a request structure
2760 * @engine: engine that we wish to issue the request on.
2761 * @ctx: context that the request will be associated with.
2762 * This can be NULL if the request is not directly related to
2763 * any specific user context, in which case this function will
2764 * choose an appropriate context to use.
2766 * Returns a pointer to the allocated request if successful,
2767 * or an error code if not.
2769 struct drm_i915_gem_request *
2770 i915_gem_request_alloc(struct intel_engine_cs *engine,
2771 struct intel_context *ctx)
2773 struct drm_i915_gem_request *req;
2777 ctx = to_i915(engine->dev)->kernel_context;
2778 err = __i915_gem_request_alloc(engine, ctx, &req);
2779 return err ? ERR_PTR(err) : req;
2782 void i915_gem_request_cancel(struct drm_i915_gem_request *req)
2784 intel_ring_reserved_space_cancel(req->ringbuf);
2786 i915_gem_request_unreference(req);
2789 struct drm_i915_gem_request *
2790 i915_gem_find_active_request(struct intel_engine_cs *engine)
2792 struct drm_i915_gem_request *request;
2794 list_for_each_entry(request, &engine->request_list, list) {
2795 if (i915_gem_request_completed(request, false))
2804 static void i915_gem_reset_engine_status(struct drm_i915_private *dev_priv,
2805 struct intel_engine_cs *engine)
2807 struct drm_i915_gem_request *request;
2810 request = i915_gem_find_active_request(engine);
2812 if (request == NULL)
2815 ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2817 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2819 list_for_each_entry_continue(request, &engine->request_list, list)
2820 i915_set_reset_status(dev_priv, request->ctx, false);
2823 static void i915_gem_reset_engine_cleanup(struct drm_i915_private *dev_priv,
2824 struct intel_engine_cs *engine)
2826 struct intel_ringbuffer *buffer;
2828 while (!list_empty(&engine->active_list)) {
2829 struct drm_i915_gem_object *obj;
2831 obj = list_first_entry(&engine->active_list,
2832 struct drm_i915_gem_object,
2833 ring_list[engine->id]);
2835 i915_gem_object_retire__read(obj, engine->id);
2839 * Clear the execlists queue up before freeing the requests, as those
2840 * are the ones that keep the context and ringbuffer backing objects
2844 if (i915.enable_execlists) {
2845 spin_lock_irq(&engine->execlist_lock);
2847 /* list_splice_tail_init checks for empty lists */
2848 list_splice_tail_init(&engine->execlist_queue,
2849 &engine->execlist_retired_req_list);
2851 spin_unlock_irq(&engine->execlist_lock);
2852 intel_execlists_retire_requests(engine);
2856 * We must free the requests after all the corresponding objects have
2857 * been moved off active lists. Which is the same order as the normal
2858 * retire_requests function does. This is important if object hold
2859 * implicit references on things like e.g. ppgtt address spaces through
2862 while (!list_empty(&engine->request_list)) {
2863 struct drm_i915_gem_request *request;
2865 request = list_first_entry(&engine->request_list,
2866 struct drm_i915_gem_request,
2869 i915_gem_request_retire(request);
2872 /* Having flushed all requests from all queues, we know that all
2873 * ringbuffers must now be empty. However, since we do not reclaim
2874 * all space when retiring the request (to prevent HEADs colliding
2875 * with rapid ringbuffer wraparound) the amount of available space
2876 * upon reset is less than when we start. Do one more pass over
2877 * all the ringbuffers to reset last_retired_head.
2879 list_for_each_entry(buffer, &engine->buffers, link) {
2880 buffer->last_retired_head = buffer->tail;
2881 intel_ring_update_space(buffer);
2885 void i915_gem_reset(struct drm_device *dev)
2887 struct drm_i915_private *dev_priv = dev->dev_private;
2888 struct intel_engine_cs *engine;
2892 * Before we free the objects from the requests, we need to inspect
2893 * them for finding the guilty party. As the requests only borrow
2894 * their reference to the objects, the inspection must be done first.
2896 for_each_engine(engine, dev_priv, i)
2897 i915_gem_reset_engine_status(dev_priv, engine);
2899 for_each_engine(engine, dev_priv, i)
2900 i915_gem_reset_engine_cleanup(dev_priv, engine);
2902 i915_gem_context_reset(dev);
2904 i915_gem_restore_fences(dev);
2906 WARN_ON(i915_verify_lists(dev));
2910 * This function clears the request list as sequence numbers are passed.
2913 i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
2915 WARN_ON(i915_verify_lists(engine->dev));
2917 /* Retire requests first as we use it above for the early return.
2918 * If we retire requests last, we may use a later seqno and so clear
2919 * the requests lists without clearing the active list, leading to
2922 while (!list_empty(&engine->request_list)) {
2923 struct drm_i915_gem_request *request;
2925 request = list_first_entry(&engine->request_list,
2926 struct drm_i915_gem_request,
2929 if (!i915_gem_request_completed(request, true))
2932 i915_gem_request_retire(request);
2935 /* Move any buffers on the active list that are no longer referenced
2936 * by the ringbuffer to the flushing/inactive lists as appropriate,
2937 * before we free the context associated with the requests.
2939 while (!list_empty(&engine->active_list)) {
2940 struct drm_i915_gem_object *obj;
2942 obj = list_first_entry(&engine->active_list,
2943 struct drm_i915_gem_object,
2944 ring_list[engine->id]);
2946 if (!list_empty(&obj->last_read_req[engine->id]->list))
2949 i915_gem_object_retire__read(obj, engine->id);
2952 if (unlikely(engine->trace_irq_req &&
2953 i915_gem_request_completed(engine->trace_irq_req, true))) {
2954 engine->irq_put(engine);
2955 i915_gem_request_assign(&engine->trace_irq_req, NULL);
2958 WARN_ON(i915_verify_lists(engine->dev));
2962 i915_gem_retire_requests(struct drm_device *dev)
2964 struct drm_i915_private *dev_priv = dev->dev_private;
2965 struct intel_engine_cs *engine;
2969 for_each_engine(engine, dev_priv, i) {
2970 i915_gem_retire_requests_ring(engine);
2971 idle &= list_empty(&engine->request_list);
2972 if (i915.enable_execlists) {
2973 spin_lock_irq(&engine->execlist_lock);
2974 idle &= list_empty(&engine->execlist_queue);
2975 spin_unlock_irq(&engine->execlist_lock);
2977 intel_execlists_retire_requests(engine);
2982 mod_delayed_work(dev_priv->wq,
2983 &dev_priv->mm.idle_work,
2984 msecs_to_jiffies(100));
2990 i915_gem_retire_work_handler(struct work_struct *work)
2992 struct drm_i915_private *dev_priv =
2993 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2994 struct drm_device *dev = dev_priv->dev;
2997 /* Come back later if the device is busy... */
2999 if (mutex_trylock(&dev->struct_mutex)) {
3000 idle = i915_gem_retire_requests(dev);
3001 mutex_unlock(&dev->struct_mutex);
3004 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
3005 round_jiffies_up_relative(HZ));
3009 i915_gem_idle_work_handler(struct work_struct *work)
3011 struct drm_i915_private *dev_priv =
3012 container_of(work, typeof(*dev_priv), mm.idle_work.work);
3013 struct drm_device *dev = dev_priv->dev;
3014 struct intel_engine_cs *ring;
3017 for_each_engine(ring, dev_priv, i)
3018 if (!list_empty(&ring->request_list))
3021 /* we probably should sync with hangcheck here, using cancel_work_sync.
3022 * Also locking seems to be fubar here, ring->request_list is protected
3023 * by dev->struct_mutex. */
3025 intel_mark_idle(dev);
3027 if (mutex_trylock(&dev->struct_mutex)) {
3028 struct intel_engine_cs *engine;
3031 for_each_engine(engine, dev_priv, i)
3032 i915_gem_batch_pool_fini(&engine->batch_pool);
3034 mutex_unlock(&dev->struct_mutex);
3039 * Ensures that an object will eventually get non-busy by flushing any required
3040 * write domains, emitting any outstanding lazy request and retiring and
3041 * completed requests.
3044 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
3051 for (i = 0; i < I915_NUM_ENGINES; i++) {
3052 struct drm_i915_gem_request *req;
3054 req = obj->last_read_req[i];
3058 if (list_empty(&req->list))
3061 if (i915_gem_request_completed(req, true)) {
3062 __i915_gem_request_retire__upto(req);
3064 i915_gem_object_retire__read(obj, i);
3072 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3073 * @DRM_IOCTL_ARGS: standard ioctl arguments
3075 * Returns 0 if successful, else an error is returned with the remaining time in
3076 * the timeout parameter.
3077 * -ETIME: object is still busy after timeout
3078 * -ERESTARTSYS: signal interrupted the wait
3079 * -ENONENT: object doesn't exist
3080 * Also possible, but rare:
3081 * -EAGAIN: GPU wedged
3083 * -ENODEV: Internal IRQ fail
3084 * -E?: The add request failed
3086 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3087 * non-zero timeout parameter the wait ioctl will wait for the given number of
3088 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3089 * without holding struct_mutex the object may become re-busied before this
3090 * function completes. A similar but shorter * race condition exists in the busy
3094 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3096 struct drm_i915_private *dev_priv = dev->dev_private;
3097 struct drm_i915_gem_wait *args = data;
3098 struct drm_i915_gem_object *obj;
3099 struct drm_i915_gem_request *req[I915_NUM_ENGINES];
3100 unsigned reset_counter;
3104 if (args->flags != 0)
3107 ret = i915_mutex_lock_interruptible(dev);
3111 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
3112 if (&obj->base == NULL) {
3113 mutex_unlock(&dev->struct_mutex);
3117 /* Need to make sure the object gets inactive eventually. */
3118 ret = i915_gem_object_flush_active(obj);
3125 /* Do this after OLR check to make sure we make forward progress polling
3126 * on this IOCTL with a timeout == 0 (like busy ioctl)
3128 if (args->timeout_ns == 0) {
3133 drm_gem_object_unreference(&obj->base);
3134 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3136 for (i = 0; i < I915_NUM_ENGINES; i++) {
3137 if (obj->last_read_req[i] == NULL)
3140 req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
3143 mutex_unlock(&dev->struct_mutex);
3145 for (i = 0; i < n; i++) {
3147 ret = __i915_wait_request(req[i], reset_counter, true,
3148 args->timeout_ns > 0 ? &args->timeout_ns : NULL,
3149 to_rps_client(file));
3150 i915_gem_request_unreference__unlocked(req[i]);
3155 drm_gem_object_unreference(&obj->base);
3156 mutex_unlock(&dev->struct_mutex);
3161 __i915_gem_object_sync(struct drm_i915_gem_object *obj,
3162 struct intel_engine_cs *to,
3163 struct drm_i915_gem_request *from_req,
3164 struct drm_i915_gem_request **to_req)
3166 struct intel_engine_cs *from;
3169 from = i915_gem_request_get_engine(from_req);
3173 if (i915_gem_request_completed(from_req, true))
3176 if (!i915_semaphore_is_enabled(obj->base.dev)) {
3177 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3178 ret = __i915_wait_request(from_req,
3179 atomic_read(&i915->gpu_error.reset_counter),
3180 i915->mm.interruptible,
3182 &i915->rps.semaphores);
3186 i915_gem_object_retire_request(obj, from_req);
3188 int idx = intel_ring_sync_index(from, to);
3189 u32 seqno = i915_gem_request_get_seqno(from_req);
3193 if (seqno <= from->semaphore.sync_seqno[idx])
3196 if (*to_req == NULL) {
3197 struct drm_i915_gem_request *req;
3199 req = i915_gem_request_alloc(to, NULL);
3201 return PTR_ERR(req);
3206 trace_i915_gem_ring_sync_to(*to_req, from, from_req);
3207 ret = to->semaphore.sync_to(*to_req, from, seqno);
3211 /* We use last_read_req because sync_to()
3212 * might have just caused seqno wrap under
3215 from->semaphore.sync_seqno[idx] =
3216 i915_gem_request_get_seqno(obj->last_read_req[from->id]);
3223 * i915_gem_object_sync - sync an object to a ring.
3225 * @obj: object which may be in use on another ring.
3226 * @to: ring we wish to use the object on. May be NULL.
3227 * @to_req: request we wish to use the object for. See below.
3228 * This will be allocated and returned if a request is
3229 * required but not passed in.
3231 * This code is meant to abstract object synchronization with the GPU.
3232 * Calling with NULL implies synchronizing the object with the CPU
3233 * rather than a particular GPU ring. Conceptually we serialise writes
3234 * between engines inside the GPU. We only allow one engine to write
3235 * into a buffer at any time, but multiple readers. To ensure each has
3236 * a coherent view of memory, we must:
3238 * - If there is an outstanding write request to the object, the new
3239 * request must wait for it to complete (either CPU or in hw, requests
3240 * on the same ring will be naturally ordered).
3242 * - If we are a write request (pending_write_domain is set), the new
3243 * request must wait for outstanding read requests to complete.
3245 * For CPU synchronisation (NULL to) no request is required. For syncing with
3246 * rings to_req must be non-NULL. However, a request does not have to be
3247 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3248 * request will be allocated automatically and returned through *to_req. Note
3249 * that it is not guaranteed that commands will be emitted (because the system
3250 * might already be idle). Hence there is no need to create a request that
3251 * might never have any work submitted. Note further that if a request is
3252 * returned in *to_req, it is the responsibility of the caller to submit
3253 * that request (after potentially adding more work to it).
3255 * Returns 0 if successful, else propagates up the lower layer error.
3258 i915_gem_object_sync(struct drm_i915_gem_object *obj,
3259 struct intel_engine_cs *to,
3260 struct drm_i915_gem_request **to_req)
3262 const bool readonly = obj->base.pending_write_domain == 0;
3263 struct drm_i915_gem_request *req[I915_NUM_ENGINES];
3270 return i915_gem_object_wait_rendering(obj, readonly);
3274 if (obj->last_write_req)
3275 req[n++] = obj->last_write_req;
3277 for (i = 0; i < I915_NUM_ENGINES; i++)
3278 if (obj->last_read_req[i])
3279 req[n++] = obj->last_read_req[i];
3281 for (i = 0; i < n; i++) {
3282 ret = __i915_gem_object_sync(obj, to, req[i], to_req);
3290 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3292 u32 old_write_domain, old_read_domains;
3294 /* Force a pagefault for domain tracking on next user access */
3295 i915_gem_release_mmap(obj);
3297 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3300 /* Wait for any direct GTT access to complete */
3303 old_read_domains = obj->base.read_domains;
3304 old_write_domain = obj->base.write_domain;
3306 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3307 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3309 trace_i915_gem_object_change_domain(obj,
3314 static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
3316 struct drm_i915_gem_object *obj = vma->obj;
3317 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3320 if (list_empty(&vma->obj_link))
3323 if (!drm_mm_node_allocated(&vma->node)) {
3324 i915_gem_vma_destroy(vma);
3331 BUG_ON(obj->pages == NULL);
3334 ret = i915_gem_object_wait_rendering(obj, false);
3339 if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3340 i915_gem_object_finish_gtt(obj);
3342 /* release the fence reg _after_ flushing */
3343 ret = i915_gem_object_put_fence(obj);
3348 trace_i915_vma_unbind(vma);
3350 vma->vm->unbind_vma(vma);
3353 list_del_init(&vma->vm_link);
3355 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3356 obj->map_and_fenceable = false;
3357 } else if (vma->ggtt_view.pages) {
3358 sg_free_table(vma->ggtt_view.pages);
3359 kfree(vma->ggtt_view.pages);
3361 vma->ggtt_view.pages = NULL;
3364 drm_mm_remove_node(&vma->node);
3365 i915_gem_vma_destroy(vma);
3367 /* Since the unbound list is global, only move to that list if
3368 * no more VMAs exist. */
3369 if (list_empty(&obj->vma_list))
3370 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3372 /* And finally now the object is completely decoupled from this vma,
3373 * we can drop its hold on the backing storage and allow it to be
3374 * reaped by the shrinker.
3376 i915_gem_object_unpin_pages(obj);
3381 int i915_vma_unbind(struct i915_vma *vma)
3383 return __i915_vma_unbind(vma, true);
3386 int __i915_vma_unbind_no_wait(struct i915_vma *vma)
3388 return __i915_vma_unbind(vma, false);
3391 int i915_gpu_idle(struct drm_device *dev)
3393 struct drm_i915_private *dev_priv = dev->dev_private;
3394 struct intel_engine_cs *engine;
3397 /* Flush everything onto the inactive list. */
3398 for_each_engine(engine, dev_priv, i) {
3399 if (!i915.enable_execlists) {
3400 struct drm_i915_gem_request *req;
3402 req = i915_gem_request_alloc(engine, NULL);
3404 return PTR_ERR(req);
3406 ret = i915_switch_context(req);
3408 i915_gem_request_cancel(req);
3412 i915_add_request_no_flush(req);
3415 ret = intel_engine_idle(engine);
3420 WARN_ON(i915_verify_lists(dev));
3424 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3425 unsigned long cache_level)
3427 struct drm_mm_node *gtt_space = &vma->node;
3428 struct drm_mm_node *other;
3431 * On some machines we have to be careful when putting differing types
3432 * of snoopable memory together to avoid the prefetcher crossing memory
3433 * domains and dying. During vm initialisation, we decide whether or not
3434 * these constraints apply and set the drm_mm.color_adjust
3437 if (vma->vm->mm.color_adjust == NULL)
3440 if (!drm_mm_node_allocated(gtt_space))
3443 if (list_empty(>t_space->node_list))
3446 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3447 if (other->allocated && !other->hole_follows && other->color != cache_level)
3450 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3451 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3458 * Finds free space in the GTT aperture and binds the object or a view of it
3461 static struct i915_vma *
3462 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3463 struct i915_address_space *vm,
3464 const struct i915_ggtt_view *ggtt_view,
3468 struct drm_device *dev = obj->base.dev;
3469 struct drm_i915_private *dev_priv = dev->dev_private;
3470 u32 fence_alignment, unfenced_alignment;
3471 u32 search_flag, alloc_flag;
3473 u64 size, fence_size;
3474 struct i915_vma *vma;
3477 if (i915_is_ggtt(vm)) {
3480 if (WARN_ON(!ggtt_view))
3481 return ERR_PTR(-EINVAL);
3483 view_size = i915_ggtt_view_size(obj, ggtt_view);
3485 fence_size = i915_gem_get_gtt_size(dev,
3488 fence_alignment = i915_gem_get_gtt_alignment(dev,
3492 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3496 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3498 fence_size = i915_gem_get_gtt_size(dev,
3501 fence_alignment = i915_gem_get_gtt_alignment(dev,
3505 unfenced_alignment =
3506 i915_gem_get_gtt_alignment(dev,
3510 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3513 start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3515 if (flags & PIN_MAPPABLE)
3516 end = min_t(u64, end, dev_priv->gtt.mappable_end);
3517 if (flags & PIN_ZONE_4G)
3518 end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE);
3521 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3523 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3524 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3525 ggtt_view ? ggtt_view->type : 0,
3527 return ERR_PTR(-EINVAL);
3530 /* If binding the object/GGTT view requires more space than the entire
3531 * aperture has, reject it early before evicting everything in a vain
3532 * attempt to find space.
3535 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3536 ggtt_view ? ggtt_view->type : 0,
3538 flags & PIN_MAPPABLE ? "mappable" : "total",
3540 return ERR_PTR(-E2BIG);
3543 ret = i915_gem_object_get_pages(obj);
3545 return ERR_PTR(ret);
3547 i915_gem_object_pin_pages(obj);
3549 vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3550 i915_gem_obj_lookup_or_create_vma(obj, vm);
3555 if (flags & PIN_OFFSET_FIXED) {
3556 uint64_t offset = flags & PIN_OFFSET_MASK;
3558 if (offset & (alignment - 1) || offset + size > end) {
3562 vma->node.start = offset;
3563 vma->node.size = size;
3564 vma->node.color = obj->cache_level;
3565 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3567 ret = i915_gem_evict_for_vma(vma);
3569 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3574 if (flags & PIN_HIGH) {
3575 search_flag = DRM_MM_SEARCH_BELOW;
3576 alloc_flag = DRM_MM_CREATE_TOP;
3578 search_flag = DRM_MM_SEARCH_DEFAULT;
3579 alloc_flag = DRM_MM_CREATE_DEFAULT;
3583 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3590 ret = i915_gem_evict_something(dev, vm, size, alignment,
3600 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3602 goto err_remove_node;
3605 trace_i915_vma_bind(vma, flags);
3606 ret = i915_vma_bind(vma, obj->cache_level, flags);
3608 goto err_remove_node;
3610 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3611 list_add_tail(&vma->vm_link, &vm->inactive_list);
3616 drm_mm_remove_node(&vma->node);
3618 i915_gem_vma_destroy(vma);
3621 i915_gem_object_unpin_pages(obj);
3626 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3629 /* If we don't have a page list set up, then we're not pinned
3630 * to GPU, and we can ignore the cache flush because it'll happen
3631 * again at bind time.
3633 if (obj->pages == NULL)
3637 * Stolen memory is always coherent with the GPU as it is explicitly
3638 * marked as wc by the system, or the system is cache-coherent.
3640 if (obj->stolen || obj->phys_handle)
3643 /* If the GPU is snooping the contents of the CPU cache,
3644 * we do not need to manually clear the CPU cache lines. However,
3645 * the caches are only snooped when the render cache is
3646 * flushed/invalidated. As we always have to emit invalidations
3647 * and flushes when moving into and out of the RENDER domain, correct
3648 * snooping behaviour occurs naturally as the result of our domain
3651 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3652 obj->cache_dirty = true;
3656 trace_i915_gem_object_clflush(obj);
3657 drm_clflush_sg(obj->pages);
3658 obj->cache_dirty = false;
3663 /** Flushes the GTT write domain for the object if it's dirty. */
3665 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3667 uint32_t old_write_domain;
3669 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3672 /* No actual flushing is required for the GTT write domain. Writes
3673 * to it immediately go to main memory as far as we know, so there's
3674 * no chipset flush. It also doesn't land in render cache.
3676 * However, we do have to enforce the order so that all writes through
3677 * the GTT land before any writes to the device, such as updates to
3682 old_write_domain = obj->base.write_domain;
3683 obj->base.write_domain = 0;
3685 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
3687 trace_i915_gem_object_change_domain(obj,
3688 obj->base.read_domains,
3692 /** Flushes the CPU write domain for the object if it's dirty. */
3694 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3696 uint32_t old_write_domain;
3698 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3701 if (i915_gem_clflush_object(obj, obj->pin_display))
3702 i915_gem_chipset_flush(obj->base.dev);
3704 old_write_domain = obj->base.write_domain;
3705 obj->base.write_domain = 0;
3707 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3709 trace_i915_gem_object_change_domain(obj,
3710 obj->base.read_domains,
3715 * Moves a single object to the GTT read, and possibly write domain.
3717 * This function returns when the move is complete, including waiting on
3721 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3723 uint32_t old_write_domain, old_read_domains;
3724 struct i915_vma *vma;
3727 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3730 ret = i915_gem_object_wait_rendering(obj, !write);
3734 /* Flush and acquire obj->pages so that we are coherent through
3735 * direct access in memory with previous cached writes through
3736 * shmemfs and that our cache domain tracking remains valid.
3737 * For example, if the obj->filp was moved to swap without us
3738 * being notified and releasing the pages, we would mistakenly
3739 * continue to assume that the obj remained out of the CPU cached
3742 ret = i915_gem_object_get_pages(obj);
3746 i915_gem_object_flush_cpu_write_domain(obj);
3748 /* Serialise direct access to this object with the barriers for
3749 * coherent writes from the GPU, by effectively invalidating the
3750 * GTT domain upon first access.
3752 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3755 old_write_domain = obj->base.write_domain;
3756 old_read_domains = obj->base.read_domains;
3758 /* It should now be out of any other write domains, and we can update
3759 * the domain values for our changes.
3761 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3762 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3764 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3765 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3769 trace_i915_gem_object_change_domain(obj,
3773 /* And bump the LRU for this access */
3774 vma = i915_gem_obj_to_ggtt(obj);
3775 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3776 list_move_tail(&vma->vm_link,
3777 &to_i915(obj->base.dev)->gtt.base.inactive_list);
3783 * Changes the cache-level of an object across all VMA.
3785 * After this function returns, the object will be in the new cache-level
3786 * across all GTT and the contents of the backing storage will be coherent,
3787 * with respect to the new cache-level. In order to keep the backing storage
3788 * coherent for all users, we only allow a single cache level to be set
3789 * globally on the object and prevent it from being changed whilst the
3790 * hardware is reading from the object. That is if the object is currently
3791 * on the scanout it will be set to uncached (or equivalent display
3792 * cache coherency) and all non-MOCS GPU access will also be uncached so
3793 * that all direct access to the scanout remains coherent.
3795 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3796 enum i915_cache_level cache_level)
3798 struct drm_device *dev = obj->base.dev;
3799 struct i915_vma *vma, *next;
3803 if (obj->cache_level == cache_level)
3806 /* Inspect the list of currently bound VMA and unbind any that would
3807 * be invalid given the new cache-level. This is principally to
3808 * catch the issue of the CS prefetch crossing page boundaries and
3809 * reading an invalid PTE on older architectures.
3811 list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
3812 if (!drm_mm_node_allocated(&vma->node))
3815 if (vma->pin_count) {
3816 DRM_DEBUG("can not change the cache level of pinned objects\n");
3820 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3821 ret = i915_vma_unbind(vma);
3828 /* We can reuse the existing drm_mm nodes but need to change the
3829 * cache-level on the PTE. We could simply unbind them all and
3830 * rebind with the correct cache-level on next use. However since
3831 * we already have a valid slot, dma mapping, pages etc, we may as
3832 * rewrite the PTE in the belief that doing so tramples upon less
3833 * state and so involves less work.
3836 /* Before we change the PTE, the GPU must not be accessing it.
3837 * If we wait upon the object, we know that all the bound
3838 * VMA are no longer active.
3840 ret = i915_gem_object_wait_rendering(obj, false);
3844 if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) {
3845 /* Access to snoopable pages through the GTT is
3846 * incoherent and on some machines causes a hard
3847 * lockup. Relinquish the CPU mmaping to force
3848 * userspace to refault in the pages and we can
3849 * then double check if the GTT mapping is still
3850 * valid for that pointer access.
3852 i915_gem_release_mmap(obj);
3854 /* As we no longer need a fence for GTT access,
3855 * we can relinquish it now (and so prevent having
3856 * to steal a fence from someone else on the next
3857 * fence request). Note GPU activity would have
3858 * dropped the fence as all snoopable access is
3859 * supposed to be linear.
3861 ret = i915_gem_object_put_fence(obj);
3865 /* We either have incoherent backing store and
3866 * so no GTT access or the architecture is fully
3867 * coherent. In such cases, existing GTT mmaps
3868 * ignore the cache bit in the PTE and we can
3869 * rewrite it without confusing the GPU or having
3870 * to force userspace to fault back in its mmaps.
3874 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3875 if (!drm_mm_node_allocated(&vma->node))
3878 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3884 list_for_each_entry(vma, &obj->vma_list, obj_link)
3885 vma->node.color = cache_level;
3886 obj->cache_level = cache_level;
3889 /* Flush the dirty CPU caches to the backing storage so that the
3890 * object is now coherent at its new cache level (with respect
3891 * to the access domain).
3893 if (obj->cache_dirty &&
3894 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3895 cpu_write_needs_clflush(obj)) {
3896 if (i915_gem_clflush_object(obj, true))
3897 i915_gem_chipset_flush(obj->base.dev);
3903 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3904 struct drm_file *file)
3906 struct drm_i915_gem_caching *args = data;
3907 struct drm_i915_gem_object *obj;
3909 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3910 if (&obj->base == NULL)
3913 switch (obj->cache_level) {
3914 case I915_CACHE_LLC:
3915 case I915_CACHE_L3_LLC:
3916 args->caching = I915_CACHING_CACHED;
3920 args->caching = I915_CACHING_DISPLAY;
3924 args->caching = I915_CACHING_NONE;
3928 drm_gem_object_unreference_unlocked(&obj->base);
3932 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3933 struct drm_file *file)
3935 struct drm_i915_private *dev_priv = dev->dev_private;
3936 struct drm_i915_gem_caching *args = data;
3937 struct drm_i915_gem_object *obj;
3938 enum i915_cache_level level;
3941 switch (args->caching) {
3942 case I915_CACHING_NONE:
3943 level = I915_CACHE_NONE;
3945 case I915_CACHING_CACHED:
3947 * Due to a HW issue on BXT A stepping, GPU stores via a
3948 * snooped mapping may leave stale data in a corresponding CPU
3949 * cacheline, whereas normally such cachelines would get
3952 if (!HAS_LLC(dev) && !HAS_SNOOP(dev))
3955 level = I915_CACHE_LLC;
3957 case I915_CACHING_DISPLAY:
3958 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3964 intel_runtime_pm_get(dev_priv);
3966 ret = i915_mutex_lock_interruptible(dev);
3970 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3971 if (&obj->base == NULL) {
3976 ret = i915_gem_object_set_cache_level(obj, level);
3978 drm_gem_object_unreference(&obj->base);
3980 mutex_unlock(&dev->struct_mutex);
3982 intel_runtime_pm_put(dev_priv);
3988 * Prepare buffer for display plane (scanout, cursors, etc).
3989 * Can be called from an uninterruptible phase (modesetting) and allows
3990 * any flushes to be pipelined (for pageflips).
3993 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3995 const struct i915_ggtt_view *view)
3997 u32 old_read_domains, old_write_domain;
4000 /* Mark the pin_display early so that we account for the
4001 * display coherency whilst setting up the cache domains.
4005 /* The display engine is not coherent with the LLC cache on gen6. As
4006 * a result, we make sure that the pinning that is about to occur is
4007 * done with uncached PTEs. This is lowest common denominator for all
4010 * However for gen6+, we could do better by using the GFDT bit instead
4011 * of uncaching, which would allow us to flush all the LLC-cached data
4012 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4014 ret = i915_gem_object_set_cache_level(obj,
4015 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
4017 goto err_unpin_display;
4019 /* As the user may map the buffer once pinned in the display plane
4020 * (e.g. libkms for the bootup splash), we have to ensure that we
4021 * always use map_and_fenceable for all scanout buffers.
4023 ret = i915_gem_object_ggtt_pin(obj, view, alignment,
4024 view->type == I915_GGTT_VIEW_NORMAL ?
4027 goto err_unpin_display;
4029 i915_gem_object_flush_cpu_write_domain(obj);
4031 old_write_domain = obj->base.write_domain;
4032 old_read_domains = obj->base.read_domains;
4034 /* It should now be out of any other write domains, and we can update
4035 * the domain values for our changes.
4037 obj->base.write_domain = 0;
4038 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4040 trace_i915_gem_object_change_domain(obj,
4052 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
4053 const struct i915_ggtt_view *view)
4055 if (WARN_ON(obj->pin_display == 0))
4058 i915_gem_object_ggtt_unpin_view(obj, view);
4064 * Moves a single object to the CPU read, and possibly write domain.
4066 * This function returns when the move is complete, including waiting on
4070 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4072 uint32_t old_write_domain, old_read_domains;
4075 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4078 ret = i915_gem_object_wait_rendering(obj, !write);
4082 i915_gem_object_flush_gtt_write_domain(obj);
4084 old_write_domain = obj->base.write_domain;
4085 old_read_domains = obj->base.read_domains;
4087 /* Flush the CPU cache if it's still invalid. */
4088 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4089 i915_gem_clflush_object(obj, false);
4091 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4094 /* It should now be out of any other write domains, and we can update
4095 * the domain values for our changes.
4097 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4099 /* If we're writing through the CPU, then the GPU read domains will
4100 * need to be invalidated at next use.
4103 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4104 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4107 trace_i915_gem_object_change_domain(obj,
4114 /* Throttle our rendering by waiting until the ring has completed our requests
4115 * emitted over 20 msec ago.
4117 * Note that if we were to use the current jiffies each time around the loop,
4118 * we wouldn't escape the function with any frames outstanding if the time to
4119 * render a frame was over 20ms.
4121 * This should get us reasonable parallelism between CPU and GPU but also
4122 * relatively low latency when blocking on a particular request to finish.
4125 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4127 struct drm_i915_private *dev_priv = dev->dev_private;
4128 struct drm_i915_file_private *file_priv = file->driver_priv;
4129 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4130 struct drm_i915_gem_request *request, *target = NULL;
4131 unsigned reset_counter;
4134 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4138 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4142 spin_lock(&file_priv->mm.lock);
4143 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4144 if (time_after_eq(request->emitted_jiffies, recent_enough))
4148 * Note that the request might not have been submitted yet.
4149 * In which case emitted_jiffies will be zero.
4151 if (!request->emitted_jiffies)
4156 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4158 i915_gem_request_reference(target);
4159 spin_unlock(&file_priv->mm.lock);
4164 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4166 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4168 i915_gem_request_unreference__unlocked(target);
4174 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4176 struct drm_i915_gem_object *obj = vma->obj;
4179 vma->node.start & (alignment - 1))
4182 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4185 if (flags & PIN_OFFSET_BIAS &&
4186 vma->node.start < (flags & PIN_OFFSET_MASK))
4189 if (flags & PIN_OFFSET_FIXED &&
4190 vma->node.start != (flags & PIN_OFFSET_MASK))
4196 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
4198 struct drm_i915_gem_object *obj = vma->obj;
4199 bool mappable, fenceable;
4200 u32 fence_size, fence_alignment;
4202 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4205 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4210 fenceable = (vma->node.size == fence_size &&
4211 (vma->node.start & (fence_alignment - 1)) == 0);
4213 mappable = (vma->node.start + fence_size <=
4214 to_i915(obj->base.dev)->gtt.mappable_end);
4216 obj->map_and_fenceable = mappable && fenceable;
4220 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4221 struct i915_address_space *vm,
4222 const struct i915_ggtt_view *ggtt_view,
4226 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4227 struct i915_vma *vma;
4231 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4234 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4237 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4240 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4243 vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4244 i915_gem_obj_to_vma(obj, vm);
4247 return PTR_ERR(vma);
4250 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4253 if (i915_vma_misplaced(vma, alignment, flags)) {
4254 WARN(vma->pin_count,
4255 "bo is already pinned in %s with incorrect alignment:"
4256 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4257 " obj->map_and_fenceable=%d\n",
4258 ggtt_view ? "ggtt" : "ppgtt",
4259 upper_32_bits(vma->node.start),
4260 lower_32_bits(vma->node.start),
4262 !!(flags & PIN_MAPPABLE),
4263 obj->map_and_fenceable);
4264 ret = i915_vma_unbind(vma);
4272 bound = vma ? vma->bound : 0;
4273 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4274 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4277 return PTR_ERR(vma);
4279 ret = i915_vma_bind(vma, obj->cache_level, flags);
4284 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4285 (bound ^ vma->bound) & GLOBAL_BIND) {
4286 __i915_vma_set_map_and_fenceable(vma);
4287 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4295 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4296 struct i915_address_space *vm,
4300 return i915_gem_object_do_pin(obj, vm,
4301 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4306 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4307 const struct i915_ggtt_view *view,
4311 if (WARN_ONCE(!view, "no view specified"))
4314 return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view,
4315 alignment, flags | PIN_GLOBAL);
4319 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4320 const struct i915_ggtt_view *view)
4322 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4325 WARN_ON(vma->pin_count == 0);
4326 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4332 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4333 struct drm_file *file)
4335 struct drm_i915_gem_busy *args = data;
4336 struct drm_i915_gem_object *obj;
4339 ret = i915_mutex_lock_interruptible(dev);
4343 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4344 if (&obj->base == NULL) {
4349 /* Count all active objects as busy, even if they are currently not used
4350 * by the gpu. Users of this interface expect objects to eventually
4351 * become non-busy without any further actions, therefore emit any
4352 * necessary flushes here.
4354 ret = i915_gem_object_flush_active(obj);
4362 for (i = 0; i < I915_NUM_ENGINES; i++) {
4363 struct drm_i915_gem_request *req;
4365 req = obj->last_read_req[i];
4367 args->busy |= 1 << (16 + req->engine->exec_id);
4369 if (obj->last_write_req)
4370 args->busy |= obj->last_write_req->engine->exec_id;
4374 drm_gem_object_unreference(&obj->base);
4376 mutex_unlock(&dev->struct_mutex);
4381 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4382 struct drm_file *file_priv)
4384 return i915_gem_ring_throttle(dev, file_priv);
4388 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4389 struct drm_file *file_priv)
4391 struct drm_i915_private *dev_priv = dev->dev_private;
4392 struct drm_i915_gem_madvise *args = data;
4393 struct drm_i915_gem_object *obj;
4396 switch (args->madv) {
4397 case I915_MADV_DONTNEED:
4398 case I915_MADV_WILLNEED:
4404 ret = i915_mutex_lock_interruptible(dev);
4408 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4409 if (&obj->base == NULL) {
4414 if (i915_gem_obj_is_pinned(obj)) {
4420 obj->tiling_mode != I915_TILING_NONE &&
4421 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4422 if (obj->madv == I915_MADV_WILLNEED)
4423 i915_gem_object_unpin_pages(obj);
4424 if (args->madv == I915_MADV_WILLNEED)
4425 i915_gem_object_pin_pages(obj);
4428 if (obj->madv != __I915_MADV_PURGED)
4429 obj->madv = args->madv;
4431 /* if the object is no longer attached, discard its backing storage */
4432 if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4433 i915_gem_object_truncate(obj);
4435 args->retained = obj->madv != __I915_MADV_PURGED;
4438 drm_gem_object_unreference(&obj->base);
4440 mutex_unlock(&dev->struct_mutex);
4444 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4445 const struct drm_i915_gem_object_ops *ops)
4449 INIT_LIST_HEAD(&obj->global_list);
4450 for (i = 0; i < I915_NUM_ENGINES; i++)
4451 INIT_LIST_HEAD(&obj->ring_list[i]);
4452 INIT_LIST_HEAD(&obj->obj_exec_link);
4453 INIT_LIST_HEAD(&obj->vma_list);
4454 INIT_LIST_HEAD(&obj->batch_pool_link);
4458 obj->fence_reg = I915_FENCE_REG_NONE;
4459 obj->madv = I915_MADV_WILLNEED;
4461 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4464 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4465 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE,
4466 .get_pages = i915_gem_object_get_pages_gtt,
4467 .put_pages = i915_gem_object_put_pages_gtt,
4470 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4473 struct drm_i915_gem_object *obj;
4474 struct address_space *mapping;
4477 obj = i915_gem_object_alloc(dev);
4481 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4482 i915_gem_object_free(obj);
4486 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4487 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4488 /* 965gm cannot relocate objects above 4GiB. */
4489 mask &= ~__GFP_HIGHMEM;
4490 mask |= __GFP_DMA32;
4493 mapping = file_inode(obj->base.filp)->i_mapping;
4494 mapping_set_gfp_mask(mapping, mask);
4496 i915_gem_object_init(obj, &i915_gem_object_ops);
4498 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4499 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4502 /* On some devices, we can have the GPU use the LLC (the CPU
4503 * cache) for about a 10% performance improvement
4504 * compared to uncached. Graphics requests other than
4505 * display scanout are coherent with the CPU in
4506 * accessing this cache. This means in this mode we
4507 * don't need to clflush on the CPU side, and on the
4508 * GPU side we only need to flush internal caches to
4509 * get data visible to the CPU.
4511 * However, we maintain the display planes as UC, and so
4512 * need to rebind when first used as such.
4514 obj->cache_level = I915_CACHE_LLC;
4516 obj->cache_level = I915_CACHE_NONE;
4518 trace_i915_gem_object_create(obj);
4523 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4525 /* If we are the last user of the backing storage (be it shmemfs
4526 * pages or stolen etc), we know that the pages are going to be
4527 * immediately released. In this case, we can then skip copying
4528 * back the contents from the GPU.
4531 if (obj->madv != I915_MADV_WILLNEED)
4534 if (obj->base.filp == NULL)
4537 /* At first glance, this looks racy, but then again so would be
4538 * userspace racing mmap against close. However, the first external
4539 * reference to the filp can only be obtained through the
4540 * i915_gem_mmap_ioctl() which safeguards us against the user
4541 * acquiring such a reference whilst we are in the middle of
4542 * freeing the object.
4544 return atomic_long_read(&obj->base.filp->f_count) == 1;
4547 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4549 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4550 struct drm_device *dev = obj->base.dev;
4551 struct drm_i915_private *dev_priv = dev->dev_private;
4552 struct i915_vma *vma, *next;
4554 intel_runtime_pm_get(dev_priv);
4556 trace_i915_gem_object_destroy(obj);
4558 list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
4562 ret = i915_vma_unbind(vma);
4563 if (WARN_ON(ret == -ERESTARTSYS)) {
4564 bool was_interruptible;
4566 was_interruptible = dev_priv->mm.interruptible;
4567 dev_priv->mm.interruptible = false;
4569 WARN_ON(i915_vma_unbind(vma));
4571 dev_priv->mm.interruptible = was_interruptible;
4575 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4576 * before progressing. */
4578 i915_gem_object_unpin_pages(obj);
4580 WARN_ON(obj->frontbuffer_bits);
4582 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4583 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4584 obj->tiling_mode != I915_TILING_NONE)
4585 i915_gem_object_unpin_pages(obj);
4587 if (WARN_ON(obj->pages_pin_count))
4588 obj->pages_pin_count = 0;
4589 if (discard_backing_storage(obj))
4590 obj->madv = I915_MADV_DONTNEED;
4591 i915_gem_object_put_pages(obj);
4592 i915_gem_object_free_mmap_offset(obj);
4596 if (obj->base.import_attach)
4597 drm_prime_gem_destroy(&obj->base, NULL);
4599 if (obj->ops->release)
4600 obj->ops->release(obj);
4602 drm_gem_object_release(&obj->base);
4603 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4606 i915_gem_object_free(obj);
4608 intel_runtime_pm_put(dev_priv);
4611 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4612 struct i915_address_space *vm)
4614 struct i915_vma *vma;
4615 list_for_each_entry(vma, &obj->vma_list, obj_link) {
4616 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL &&
4623 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4624 const struct i915_ggtt_view *view)
4626 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
4627 struct i915_vma *vma;
4629 if (WARN_ONCE(!view, "no view specified"))
4630 return ERR_PTR(-EINVAL);
4632 list_for_each_entry(vma, &obj->vma_list, obj_link)
4633 if (vma->vm == ggtt &&
4634 i915_ggtt_view_equal(&vma->ggtt_view, view))
4639 void i915_gem_vma_destroy(struct i915_vma *vma)
4641 WARN_ON(vma->node.allocated);
4643 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4644 if (!list_empty(&vma->exec_list))
4648 i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm));
4650 list_del(&vma->obj_link);
4652 kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4656 i915_gem_stop_ringbuffers(struct drm_device *dev)
4658 struct drm_i915_private *dev_priv = dev->dev_private;
4659 struct intel_engine_cs *engine;
4662 for_each_engine(engine, dev_priv, i)
4663 dev_priv->gt.stop_ring(engine);
4667 i915_gem_suspend(struct drm_device *dev)
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4672 mutex_lock(&dev->struct_mutex);
4673 ret = i915_gpu_idle(dev);
4677 i915_gem_retire_requests(dev);
4679 i915_gem_stop_ringbuffers(dev);
4680 mutex_unlock(&dev->struct_mutex);
4682 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4683 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4684 flush_delayed_work(&dev_priv->mm.idle_work);
4686 /* Assert that we sucessfully flushed all the work and
4687 * reset the GPU back to its idle, low power state.
4689 WARN_ON(dev_priv->mm.busy);
4694 mutex_unlock(&dev->struct_mutex);
4698 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
4700 struct intel_engine_cs *engine = req->engine;
4701 struct drm_device *dev = engine->dev;
4702 struct drm_i915_private *dev_priv = dev->dev_private;
4703 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4706 if (!HAS_L3_DPF(dev) || !remap_info)
4709 ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);
4714 * Note: We do not worry about the concurrent register cacheline hang
4715 * here because no other code should access these registers other than
4716 * at initialization time.
4718 for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) {
4719 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
4720 intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i));
4721 intel_ring_emit(engine, remap_info[i]);
4724 intel_ring_advance(engine);
4729 void i915_gem_init_swizzling(struct drm_device *dev)
4731 struct drm_i915_private *dev_priv = dev->dev_private;
4733 if (INTEL_INFO(dev)->gen < 5 ||
4734 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4737 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4738 DISP_TILE_SURFACE_SWIZZLING);
4743 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4745 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4746 else if (IS_GEN7(dev))
4747 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4748 else if (IS_GEN8(dev))
4749 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4754 static void init_unused_ring(struct drm_device *dev, u32 base)
4756 struct drm_i915_private *dev_priv = dev->dev_private;
4758 I915_WRITE(RING_CTL(base), 0);
4759 I915_WRITE(RING_HEAD(base), 0);
4760 I915_WRITE(RING_TAIL(base), 0);
4761 I915_WRITE(RING_START(base), 0);
4764 static void init_unused_rings(struct drm_device *dev)
4767 init_unused_ring(dev, PRB1_BASE);
4768 init_unused_ring(dev, SRB0_BASE);
4769 init_unused_ring(dev, SRB1_BASE);
4770 init_unused_ring(dev, SRB2_BASE);
4771 init_unused_ring(dev, SRB3_BASE);
4772 } else if (IS_GEN2(dev)) {
4773 init_unused_ring(dev, SRB0_BASE);
4774 init_unused_ring(dev, SRB1_BASE);
4775 } else if (IS_GEN3(dev)) {
4776 init_unused_ring(dev, PRB1_BASE);
4777 init_unused_ring(dev, PRB2_BASE);
4781 int i915_gem_init_rings(struct drm_device *dev)
4783 struct drm_i915_private *dev_priv = dev->dev_private;
4786 ret = intel_init_render_ring_buffer(dev);
4791 ret = intel_init_bsd_ring_buffer(dev);
4793 goto cleanup_render_ring;
4797 ret = intel_init_blt_ring_buffer(dev);
4799 goto cleanup_bsd_ring;
4802 if (HAS_VEBOX(dev)) {
4803 ret = intel_init_vebox_ring_buffer(dev);
4805 goto cleanup_blt_ring;
4808 if (HAS_BSD2(dev)) {
4809 ret = intel_init_bsd2_ring_buffer(dev);
4811 goto cleanup_vebox_ring;
4817 intel_cleanup_ring_buffer(&dev_priv->engine[VECS]);
4819 intel_cleanup_ring_buffer(&dev_priv->engine[BCS]);
4821 intel_cleanup_ring_buffer(&dev_priv->engine[VCS]);
4822 cleanup_render_ring:
4823 intel_cleanup_ring_buffer(&dev_priv->engine[RCS]);
4829 i915_gem_init_hw(struct drm_device *dev)
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832 struct intel_engine_cs *engine;
4835 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4838 /* Double layer security blanket, see i915_gem_init() */
4839 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4841 if (dev_priv->ellc_size)
4842 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4844 if (IS_HASWELL(dev))
4845 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4846 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4848 if (HAS_PCH_NOP(dev)) {
4849 if (IS_IVYBRIDGE(dev)) {
4850 u32 temp = I915_READ(GEN7_MSG_CTL);
4851 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4852 I915_WRITE(GEN7_MSG_CTL, temp);
4853 } else if (INTEL_INFO(dev)->gen >= 7) {
4854 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4855 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4856 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4860 i915_gem_init_swizzling(dev);
4863 * At least 830 can leave some of the unused rings
4864 * "active" (ie. head != tail) after resume which
4865 * will prevent c3 entry. Makes sure all unused rings
4868 init_unused_rings(dev);
4870 BUG_ON(!dev_priv->kernel_context);
4872 ret = i915_ppgtt_init_hw(dev);
4874 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4878 /* Need to do basic initialisation of all rings first: */
4879 for_each_engine(engine, dev_priv, i) {
4880 ret = engine->init_hw(engine);
4885 /* We can't enable contexts until all firmware is loaded */
4886 if (HAS_GUC_UCODE(dev)) {
4887 ret = intel_guc_ucode_load(dev);
4889 DRM_ERROR("Failed to initialize GuC, error %d\n", ret);
4896 * Increment the next seqno by 0x100 so we have a visible break
4897 * on re-initialisation
4899 ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100);
4903 /* Now it is safe to go back round and do everything else: */
4904 for_each_engine(engine, dev_priv, i) {
4905 struct drm_i915_gem_request *req;
4907 req = i915_gem_request_alloc(engine, NULL);
4910 i915_gem_cleanup_ringbuffer(dev);
4914 if (engine->id == RCS) {
4915 for (j = 0; j < NUM_L3_SLICES(dev); j++)
4916 i915_gem_l3_remap(req, j);
4919 ret = i915_ppgtt_init_ring(req);
4920 if (ret && ret != -EIO) {
4921 DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret);
4922 i915_gem_request_cancel(req);
4923 i915_gem_cleanup_ringbuffer(dev);
4927 ret = i915_gem_context_enable(req);
4928 if (ret && ret != -EIO) {
4929 DRM_ERROR("Context enable ring #%d failed %d\n", i, ret);
4930 i915_gem_request_cancel(req);
4931 i915_gem_cleanup_ringbuffer(dev);
4935 i915_add_request_no_flush(req);
4939 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4943 int i915_gem_init(struct drm_device *dev)
4945 struct drm_i915_private *dev_priv = dev->dev_private;
4948 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4949 i915.enable_execlists);
4951 mutex_lock(&dev->struct_mutex);
4953 if (!i915.enable_execlists) {
4954 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
4955 dev_priv->gt.init_rings = i915_gem_init_rings;
4956 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4957 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4959 dev_priv->gt.execbuf_submit = intel_execlists_submission;
4960 dev_priv->gt.init_rings = intel_logical_rings_init;
4961 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4962 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4965 /* This is just a security blanket to placate dragons.
4966 * On some systems, we very sporadically observe that the first TLBs
4967 * used by the CS may be stale, despite us poking the TLB reset. If
4968 * we hold the forcewake during initialisation these problems
4969 * just magically go away.
4971 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4973 ret = i915_gem_init_userptr(dev);
4977 i915_gem_init_global_gtt(dev);
4979 ret = i915_gem_context_init(dev);
4983 ret = dev_priv->gt.init_rings(dev);
4987 ret = i915_gem_init_hw(dev);
4989 /* Allow ring initialisation to fail by marking the GPU as
4990 * wedged. But we only want to do this where the GPU is angry,
4991 * for all other failure, such as an allocation failure, bail.
4993 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4994 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4999 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5000 mutex_unlock(&dev->struct_mutex);
5006 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
5008 struct drm_i915_private *dev_priv = dev->dev_private;
5009 struct intel_engine_cs *engine;
5012 for_each_engine(engine, dev_priv, i)
5013 dev_priv->gt.cleanup_ring(engine);
5015 if (i915.enable_execlists)
5017 * Neither the BIOS, ourselves or any other kernel
5018 * expects the system to be in execlists mode on startup,
5019 * so we need to reset the GPU back to legacy mode.
5021 intel_gpu_reset(dev);
5025 init_engine_lists(struct intel_engine_cs *engine)
5027 INIT_LIST_HEAD(&engine->active_list);
5028 INIT_LIST_HEAD(&engine->request_list);
5032 i915_gem_load_init(struct drm_device *dev)
5034 struct drm_i915_private *dev_priv = dev->dev_private;
5038 kmem_cache_create("i915_gem_object",
5039 sizeof(struct drm_i915_gem_object), 0,
5043 kmem_cache_create("i915_gem_vma",
5044 sizeof(struct i915_vma), 0,
5047 dev_priv->requests =
5048 kmem_cache_create("i915_gem_request",
5049 sizeof(struct drm_i915_gem_request), 0,
5053 INIT_LIST_HEAD(&dev_priv->vm_list);
5054 INIT_LIST_HEAD(&dev_priv->context_list);
5055 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5056 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5057 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5058 for (i = 0; i < I915_NUM_ENGINES; i++)
5059 init_engine_lists(&dev_priv->engine[i]);
5060 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5061 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5062 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5063 i915_gem_retire_work_handler);
5064 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5065 i915_gem_idle_work_handler);
5066 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5068 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5070 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
5071 dev_priv->num_fence_regs = 32;
5072 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5073 dev_priv->num_fence_regs = 16;
5075 dev_priv->num_fence_regs = 8;
5077 if (intel_vgpu_active(dev))
5078 dev_priv->num_fence_regs =
5079 I915_READ(vgtif_reg(avail_rs.fence_num));
5082 * Set initial sequence number for requests.
5083 * Using this number allows the wraparound to happen early,
5084 * catching any obvious problems.
5086 dev_priv->next_seqno = ((u32)~0 - 0x1100);
5087 dev_priv->last_seqno = ((u32)~0 - 0x1101);
5089 /* Initialize fence registers to zero */
5090 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5091 i915_gem_restore_fences(dev);
5093 i915_gem_detect_bit_6_swizzle(dev);
5094 init_waitqueue_head(&dev_priv->pending_flip_queue);
5096 dev_priv->mm.interruptible = true;
5098 mutex_init(&dev_priv->fb_tracking.lock);
5101 void i915_gem_load_cleanup(struct drm_device *dev)
5103 struct drm_i915_private *dev_priv = to_i915(dev);
5105 kmem_cache_destroy(dev_priv->requests);
5106 kmem_cache_destroy(dev_priv->vmas);
5107 kmem_cache_destroy(dev_priv->objects);
5110 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5112 struct drm_i915_file_private *file_priv = file->driver_priv;
5114 /* Clean up our request list when the client is going away, so that
5115 * later retire_requests won't dereference our soon-to-be-gone
5118 spin_lock(&file_priv->mm.lock);
5119 while (!list_empty(&file_priv->mm.request_list)) {
5120 struct drm_i915_gem_request *request;
5122 request = list_first_entry(&file_priv->mm.request_list,
5123 struct drm_i915_gem_request,
5125 list_del(&request->client_list);
5126 request->file_priv = NULL;
5128 spin_unlock(&file_priv->mm.lock);
5130 if (!list_empty(&file_priv->rps.link)) {
5131 spin_lock(&to_i915(dev)->rps.client_lock);
5132 list_del(&file_priv->rps.link);
5133 spin_unlock(&to_i915(dev)->rps.client_lock);
5137 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5139 struct drm_i915_file_private *file_priv;
5142 DRM_DEBUG_DRIVER("\n");
5144 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5148 file->driver_priv = file_priv;
5149 file_priv->dev_priv = dev->dev_private;
5150 file_priv->file = file;
5151 INIT_LIST_HEAD(&file_priv->rps.link);
5153 spin_lock_init(&file_priv->mm.lock);
5154 INIT_LIST_HEAD(&file_priv->mm.request_list);
5156 file_priv->bsd_ring = -1;
5158 ret = i915_gem_context_open(dev, file);
5166 * i915_gem_track_fb - update frontbuffer tracking
5167 * @old: current GEM buffer for the frontbuffer slots
5168 * @new: new GEM buffer for the frontbuffer slots
5169 * @frontbuffer_bits: bitmask of frontbuffer slots
5171 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5172 * from @old and setting them in @new. Both @old and @new can be NULL.
5174 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5175 struct drm_i915_gem_object *new,
5176 unsigned frontbuffer_bits)
5179 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5180 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5181 old->frontbuffer_bits &= ~frontbuffer_bits;
5185 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5186 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5187 new->frontbuffer_bits |= frontbuffer_bits;
5191 /* All the new VM stuff */
5192 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5193 struct i915_address_space *vm)
5195 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5196 struct i915_vma *vma;
5198 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5200 list_for_each_entry(vma, &o->vma_list, obj_link) {
5202 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5205 return vma->node.start;
5208 WARN(1, "%s vma for this object not found.\n",
5209 i915_is_ggtt(vm) ? "global" : "ppgtt");
5213 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5214 const struct i915_ggtt_view *view)
5216 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5217 struct i915_vma *vma;
5219 list_for_each_entry(vma, &o->vma_list, obj_link)
5220 if (vma->vm == ggtt &&
5221 i915_ggtt_view_equal(&vma->ggtt_view, view))
5222 return vma->node.start;
5224 WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5228 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5229 struct i915_address_space *vm)
5231 struct i915_vma *vma;
5233 list_for_each_entry(vma, &o->vma_list, obj_link) {
5235 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5237 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5244 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5245 const struct i915_ggtt_view *view)
5247 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5248 struct i915_vma *vma;
5250 list_for_each_entry(vma, &o->vma_list, obj_link)
5251 if (vma->vm == ggtt &&
5252 i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5253 drm_mm_node_allocated(&vma->node))
5259 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5261 struct i915_vma *vma;
5263 list_for_each_entry(vma, &o->vma_list, obj_link)
5264 if (drm_mm_node_allocated(&vma->node))
5270 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5271 struct i915_address_space *vm)
5273 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5274 struct i915_vma *vma;
5276 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5278 BUG_ON(list_empty(&o->vma_list));
5280 list_for_each_entry(vma, &o->vma_list, obj_link) {
5282 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5285 return vma->node.size;
5290 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5292 struct i915_vma *vma;
5293 list_for_each_entry(vma, &obj->vma_list, obj_link)
5294 if (vma->pin_count > 0)
5300 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5302 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n)
5306 /* Only default objects have per-page dirty tracking */
5307 if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0))
5310 page = i915_gem_object_get_page(obj, n);
5311 set_page_dirty(page);
5315 /* Allocate a new GEM object and fill it with the supplied data */
5316 struct drm_i915_gem_object *
5317 i915_gem_object_create_from_data(struct drm_device *dev,
5318 const void *data, size_t size)
5320 struct drm_i915_gem_object *obj;
5321 struct sg_table *sg;
5325 obj = i915_gem_alloc_object(dev, round_up(size, PAGE_SIZE));
5326 if (IS_ERR_OR_NULL(obj))
5329 ret = i915_gem_object_set_to_cpu_domain(obj, true);
5333 ret = i915_gem_object_get_pages(obj);
5337 i915_gem_object_pin_pages(obj);
5339 bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
5340 obj->dirty = 1; /* Backing store is now out of date */
5341 i915_gem_object_unpin_pages(obj);
5343 if (WARN_ON(bytes != size)) {
5344 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
5352 drm_gem_object_unreference(&obj->base);
5353 return ERR_PTR(ret);