drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/intel-gtt.h>
  38
  39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
  40
  41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
  42                                                   bool pipelined);
  43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  46                                              int write);
  47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  48                                                      uint64_t offset,
  49                                                      uint64_t size);
  50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  51 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
  52                                           bool interruptible);
  53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
  54                                            unsigned alignment);
  55 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
  56 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  57                                 struct drm_i915_gem_pwrite *args,
  58                                 struct drm_file *file_priv);
  59 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
  60
  61 static int
  62 i915_gem_object_get_pages(struct drm_gem_object *obj,
  63                           gfp_t gfpmask);
  64
  65 static void
  66 i915_gem_object_put_pages(struct drm_gem_object *obj);
  67
  68 static LIST_HEAD(shrink_list);
  69 static DEFINE_SPINLOCK(shrink_list_lock);
  70
  71 /* some bookkeeping */
  72 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  73                                   size_t size)
  74 {
  75         dev_priv->mm.object_count++;
  76         dev_priv->mm.object_memory += size;
  77 }
  78
  79 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  80                                      size_t size)
  81 {
  82         dev_priv->mm.object_count--;
  83         dev_priv->mm.object_memory -= size;
  84 }
  85
  86 static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv,
  87                                   size_t size)
  88 {
  89         dev_priv->mm.gtt_count++;
  90         dev_priv->mm.gtt_memory += size;
  91 }
  92
  93 static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv,
  94                                      size_t size)
  95 {
  96         dev_priv->mm.gtt_count--;
  97         dev_priv->mm.gtt_memory -= size;
  98 }
  99
 100 static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv,
 101                                   size_t size)
 102 {
 103         dev_priv->mm.pin_count++;
 104         dev_priv->mm.pin_memory += size;
 105 }
 106
 107 static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv,
 108                                      size_t size)
 109 {
 110         dev_priv->mm.pin_count--;
 111         dev_priv->mm.pin_memory -= size;
 112 }
 113
 114 int
 115 i915_gem_check_is_wedged(struct drm_device *dev)
 116 {
 117         struct drm_i915_private *dev_priv = dev->dev_private;
 118         struct completion *x = &dev_priv->error_completion;
 119         unsigned long flags;
 120         int ret;
 121
 122         if (!atomic_read(&dev_priv->mm.wedged))
 123                 return 0;
 124
 125         ret = wait_for_completion_interruptible(x);
 126         if (ret)
 127                 return ret;
 128
 129         /* Success, we reset the GPU! */
 130         if (!atomic_read(&dev_priv->mm.wedged))
 131                 return 0;
 132
 133         /* GPU is hung, bump the completion count to account for
 134          * the token we just consumed so that we never hit zero and
 135          * end up waiting upon a subsequent completion event that
 136          * will never happen.
 137          */
 138         spin_lock_irqsave(&x->wait.lock, flags);
 139         x->done++;
 140         spin_unlock_irqrestore(&x->wait.lock, flags);
 141         return -EIO;
 142 }
 143
 144 static int i915_mutex_lock_interruptible(struct drm_device *dev)
 145 {
 146         struct drm_i915_private *dev_priv = dev->dev_private;
 147         int ret;
 148
 149         ret = i915_gem_check_is_wedged(dev);
 150         if (ret)
 151                 return ret;
 152
 153         ret = mutex_lock_interruptible(&dev->struct_mutex);
 154         if (ret)
 155                 return ret;
 156
 157         if (atomic_read(&dev_priv->mm.wedged)) {
 158                 mutex_unlock(&dev->struct_mutex);
 159                 return -EAGAIN;
 160         }
 161
 162         WARN_ON(i915_verify_lists(dev));
 163         return 0;
 164 }
 165
 166 static inline bool
 167 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
 168 {
 169         return obj_priv->gtt_space &&
 170                 !obj_priv->active &&
 171                 obj_priv->pin_count == 0;
 172 }
 173
 174 int i915_gem_do_init(struct drm_device *dev,
 175                      unsigned long start,
 176                      unsigned long end)
 177 {
 178         drm_i915_private_t *dev_priv = dev->dev_private;
 179
 180         if (start >= end ||
 181             (start & (PAGE_SIZE - 1)) != 0 ||
 182             (end & (PAGE_SIZE - 1)) != 0) {
 183                 return -EINVAL;
 184         }
 185
 186         drm_mm_init(&dev_priv->mm.gtt_space, start,
 187                     end - start);
 188
 189         dev_priv->mm.gtt_total = end - start;
 190
 191         return 0;
 192 }
 193
 194 int
 195 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 196                     struct drm_file *file_priv)
 197 {
 198         struct drm_i915_gem_init *args = data;
 199         int ret;
 200
 201         mutex_lock(&dev->struct_mutex);
 202         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
 203         mutex_unlock(&dev->struct_mutex);
 204
 205         return ret;
 206 }
 207
 208 int
 209 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 210                             struct drm_file *file_priv)
 211 {
 212         struct drm_i915_private *dev_priv = dev->dev_private;
 213         struct drm_i915_gem_get_aperture *args = data;
 214
 215         if (!(dev->driver->driver_features & DRIVER_GEM))
 216                 return -ENODEV;
 217
 218         mutex_lock(&dev->struct_mutex);
 219         args->aper_size = dev_priv->mm.gtt_total;
 220         args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory;
 221         mutex_unlock(&dev->struct_mutex);
 222
 223         return 0;
 224 }
 225
 226
 227 /**
 228  * Creates a new mm object and returns a handle to it.
 229  */
 230 int
 231 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 232                       struct drm_file *file_priv)
 233 {
 234         struct drm_i915_gem_create *args = data;
 235         struct drm_gem_object *obj;
 236         int ret;
 237         u32 handle;
 238
 239         args->size = roundup(args->size, PAGE_SIZE);
 240
 241         /* Allocate the new object */
 242         obj = i915_gem_alloc_object(dev, args->size);
 243         if (obj == NULL)
 244                 return -ENOMEM;
 245
 246         ret = drm_gem_handle_create(file_priv, obj, &handle);
 247         if (ret) {
 248                 drm_gem_object_release(obj);
 249                 i915_gem_info_remove_obj(dev->dev_private, obj->size);
 250                 kfree(obj);
 251                 return ret;
 252         }
 253
 254         /* drop reference from allocate - handle holds it now */
 255         drm_gem_object_unreference(obj);
 256         trace_i915_gem_object_create(obj);
 257
 258         args->handle = handle;
 259         return 0;
 260 }
 261
 262 static inline int
 263 fast_shmem_read(struct page **pages,
 264                 loff_t page_base, int page_offset,
 265                 char __user *data,
 266                 int length)
 267 {
 268         int unwritten;
 269         char *vaddr;
 270
 271         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 272         unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
 273         kunmap_atomic(vaddr, KM_USER0);
 274
 275         return unwritten ? -EFAULT : 0;
 276 }
 277
 278 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
 279 {
 280         drm_i915_private_t *dev_priv = obj->dev->dev_private;
 281         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 282
 283         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 284                 obj_priv->tiling_mode != I915_TILING_NONE;
 285 }
 286
 287 static inline void
 288 slow_shmem_copy(struct page *dst_page,
 289                 int dst_offset,
 290                 struct page *src_page,
 291                 int src_offset,
 292                 int length)
 293 {
 294         char *dst_vaddr, *src_vaddr;
 295
 296         dst_vaddr = kmap(dst_page);
 297         src_vaddr = kmap(src_page);
 298
 299         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 300
 301         kunmap(src_page);
 302         kunmap(dst_page);
 303 }
 304
 305 static inline void
 306 slow_shmem_bit17_copy(struct page *gpu_page,
 307                       int gpu_offset,
 308                       struct page *cpu_page,
 309                       int cpu_offset,
 310                       int length,
 311                       int is_read)
 312 {
 313         char *gpu_vaddr, *cpu_vaddr;
 314
 315         /* Use the unswizzled path if this page isn't affected. */
 316         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 317                 if (is_read)
 318                         return slow_shmem_copy(cpu_page, cpu_offset,
 319                                                gpu_page, gpu_offset, length);
 320                 else
 321                         return slow_shmem_copy(gpu_page, gpu_offset,
 322                                                cpu_page, cpu_offset, length);
 323         }
 324
 325         gpu_vaddr = kmap(gpu_page);
 326         cpu_vaddr = kmap(cpu_page);
 327
 328         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 329          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 330          */
 331         while (length > 0) {
 332                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 333                 int this_length = min(cacheline_end - gpu_offset, length);
 334                 int swizzled_gpu_offset = gpu_offset ^ 64;
 335
 336                 if (is_read) {
 337                         memcpy(cpu_vaddr + cpu_offset,
 338                                gpu_vaddr + swizzled_gpu_offset,
 339                                this_length);
 340                 } else {
 341                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 342                                cpu_vaddr + cpu_offset,
 343                                this_length);
 344                 }
 345                 cpu_offset += this_length;
 346                 gpu_offset += this_length;
 347                 length -= this_length;
 348         }
 349
 350         kunmap(cpu_page);
 351         kunmap(gpu_page);
 352 }
 353
 354 /**
 355  * This is the fast shmem pread path, which attempts to copy_from_user directly
 356  * from the backing pages of the object to the user's address space.  On a
 357  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 358  */
 359 static int
 360 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
 361                           struct drm_i915_gem_pread *args,
 362                           struct drm_file *file_priv)
 363 {
 364         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 365         ssize_t remain;
 366         loff_t offset, page_base;
 367         char __user *user_data;
 368         int page_offset, page_length;
 369         int ret;
 370
 371         user_data = (char __user *) (uintptr_t) args->data_ptr;
 372         remain = args->size;
 373
 374         ret = i915_mutex_lock_interruptible(dev);
 375         if (ret)
 376                 return ret;
 377
 378         ret = i915_gem_object_get_pages(obj, 0);
 379         if (ret != 0)
 380                 goto fail_unlock;
 381
 382         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 383                                                         args->size);
 384         if (ret != 0)
 385                 goto fail_put_pages;
 386
 387         obj_priv = to_intel_bo(obj);
 388         offset = args->offset;
 389
 390         while (remain > 0) {
 391                 /* Operation in this page
 392                  *
 393                  * page_base = page offset within aperture
 394                  * page_offset = offset within page
 395                  * page_length = bytes to copy for this page
 396                  */
 397                 page_base = (offset & ~(PAGE_SIZE-1));
 398                 page_offset = offset & (PAGE_SIZE-1);
 399                 page_length = remain;
 400                 if ((page_offset + remain) > PAGE_SIZE)
 401                         page_length = PAGE_SIZE - page_offset;
 402
 403                 ret = fast_shmem_read(obj_priv->pages,
 404                                       page_base, page_offset,
 405                                       user_data, page_length);
 406                 if (ret)
 407                         goto fail_put_pages;
 408
 409                 remain -= page_length;
 410                 user_data += page_length;
 411                 offset += page_length;
 412         }
 413
 414 fail_put_pages:
 415         i915_gem_object_put_pages(obj);
 416 fail_unlock:
 417         mutex_unlock(&dev->struct_mutex);
 418
 419         return ret;
 420 }
 421
 422 static int
 423 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
 424 {
 425         int ret;
 426
 427         ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
 428
 429         /* If we've insufficient memory to map in the pages, attempt
 430          * to make some space by throwing out some old buffers.
 431          */
 432         if (ret == -ENOMEM) {
 433                 struct drm_device *dev = obj->dev;
 434
 435                 ret = i915_gem_evict_something(dev, obj->size,
 436                                                i915_gem_get_gtt_alignment(obj));
 437                 if (ret)
 438                         return ret;
 439
 440                 ret = i915_gem_object_get_pages(obj, 0);
 441         }
 442
 443         return ret;
 444 }
 445
 446 /**
 447  * This is the fallback shmem pread path, which allocates temporary storage
 448  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 449  * can copy out of the object's backing pages while holding the struct mutex
 450  * and not take page faults.
 451  */
 452 static int
 453 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
 454                           struct drm_i915_gem_pread *args,
 455                           struct drm_file *file_priv)
 456 {
 457         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 458         struct mm_struct *mm = current->mm;
 459         struct page **user_pages;
 460         ssize_t remain;
 461         loff_t offset, pinned_pages, i;
 462         loff_t first_data_page, last_data_page, num_pages;
 463         int shmem_page_index, shmem_page_offset;
 464         int data_page_index,  data_page_offset;
 465         int page_length;
 466         int ret;
 467         uint64_t data_ptr = args->data_ptr;
 468         int do_bit17_swizzling;
 469
 470         remain = args->size;
 471
 472         /* Pin the user pages containing the data.  We can't fault while
 473          * holding the struct mutex, yet we want to hold it while
 474          * dereferencing the user data.
 475          */
 476         first_data_page = data_ptr / PAGE_SIZE;
 477         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 478         num_pages = last_data_page - first_data_page + 1;
 479
 480         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 481         if (user_pages == NULL)
 482                 return -ENOMEM;
 483
 484         down_read(&mm->mmap_sem);
 485         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 486                                       num_pages, 1, 0, user_pages, NULL);
 487         up_read(&mm->mmap_sem);
 488         if (pinned_pages < num_pages) {
 489                 ret = -EFAULT;
 490                 goto fail_put_user_pages;
 491         }
 492
 493         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 494
 495         ret = i915_mutex_lock_interruptible(dev);
 496         if (ret)
 497                 goto fail_put_user_pages;
 498
 499         ret = i915_gem_object_get_pages_or_evict(obj);
 500         if (ret)
 501                 goto fail_unlock;
 502
 503         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 504                                                         args->size);
 505         if (ret != 0)
 506                 goto fail_put_pages;
 507
 508         obj_priv = to_intel_bo(obj);
 509         offset = args->offset;
 510
 511         while (remain > 0) {
 512                 /* Operation in this page
 513                  *
 514                  * shmem_page_index = page number within shmem file
 515                  * shmem_page_offset = offset within page in shmem file
 516                  * data_page_index = page number in get_user_pages return
 517                  * data_page_offset = offset with data_page_index page.
 518                  * page_length = bytes to copy for this page
 519                  */
 520                 shmem_page_index = offset / PAGE_SIZE;
 521                 shmem_page_offset = offset & ~PAGE_MASK;
 522                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 523                 data_page_offset = data_ptr & ~PAGE_MASK;
 524
 525                 page_length = remain;
 526                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 527                         page_length = PAGE_SIZE - shmem_page_offset;
 528                 if ((data_page_offset + page_length) > PAGE_SIZE)
 529                         page_length = PAGE_SIZE - data_page_offset;
 530
 531                 if (do_bit17_swizzling) {
 532                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 533                                               shmem_page_offset,
 534                                               user_pages[data_page_index],
 535                                               data_page_offset,
 536                                               page_length,
 537                                               1);
 538                 } else {
 539                         slow_shmem_copy(user_pages[data_page_index],
 540                                         data_page_offset,
 541                                         obj_priv->pages[shmem_page_index],
 542                                         shmem_page_offset,
 543                                         page_length);
 544                 }
 545
 546                 remain -= page_length;
 547                 data_ptr += page_length;
 548                 offset += page_length;
 549         }
 550
 551 fail_put_pages:
 552         i915_gem_object_put_pages(obj);
 553 fail_unlock:
 554         mutex_unlock(&dev->struct_mutex);
 555 fail_put_user_pages:
 556         for (i = 0; i < pinned_pages; i++) {
 557                 SetPageDirty(user_pages[i]);
 558                 page_cache_release(user_pages[i]);
 559         }
 560         drm_free_large(user_pages);
 561
 562         return ret;
 563 }
 564
 565 /**
 566  * Reads data from the object referenced by handle.
 567  *
 568  * On error, the contents of *data are undefined.
 569  */
 570 int
 571 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 572                      struct drm_file *file_priv)
 573 {
 574         struct drm_i915_gem_pread *args = data;
 575         struct drm_gem_object *obj;
 576         struct drm_i915_gem_object *obj_priv;
 577         int ret = 0;
 578
 579         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 580         if (obj == NULL)
 581                 return -ENOENT;
 582         obj_priv = to_intel_bo(obj);
 583
 584         /* Bounds check source.  */
 585         if (args->offset > obj->size || args->size > obj->size - args->offset) {
 586                 ret = -EINVAL;
 587                 goto out;
 588         }
 589
 590         if (args->size == 0)
 591                 goto out;
 592
 593         if (!access_ok(VERIFY_WRITE,
 594                        (char __user *)(uintptr_t)args->data_ptr,
 595                        args->size)) {
 596                 ret = -EFAULT;
 597                 goto out;
 598         }
 599
 600         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 601                                        args->size);
 602         if (ret) {
 603                 ret = -EFAULT;
 604                 goto out;
 605         }
 606
 607         if (i915_gem_object_needs_bit17_swizzle(obj)) {
 608                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
 609         } else {
 610                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
 611                 if (ret != 0)
 612                         ret = i915_gem_shmem_pread_slow(dev, obj, args,
 613                                                         file_priv);
 614         }
 615
 616 out:
 617         drm_gem_object_unreference_unlocked(obj);
 618         return ret;
 619 }
 620
 621 /* This is the fast write path which cannot handle
 622  * page faults in the source data
 623  */
 624
 625 static inline int
 626 fast_user_write(struct io_mapping *mapping,
 627                 loff_t page_base, int page_offset,
 628                 char __user *user_data,
 629                 int length)
 630 {
 631         char *vaddr_atomic;
 632         unsigned long unwritten;
 633
 634         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
 635         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 636                                                       user_data, length);
 637         io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
 638         return unwritten;
 639 }
 640
 641 /* Here's the write path which can sleep for
 642  * page faults
 643  */
 644
 645 static inline void
 646 slow_kernel_write(struct io_mapping *mapping,
 647                   loff_t gtt_base, int gtt_offset,
 648                   struct page *user_page, int user_offset,
 649                   int length)
 650 {
 651         char __iomem *dst_vaddr;
 652         char *src_vaddr;
 653
 654         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 655         src_vaddr = kmap(user_page);
 656
 657         memcpy_toio(dst_vaddr + gtt_offset,
 658                     src_vaddr + user_offset,
 659                     length);
 660
 661         kunmap(user_page);
 662         io_mapping_unmap(dst_vaddr);
 663 }
 664
 665 static inline int
 666 fast_shmem_write(struct page **pages,
 667                  loff_t page_base, int page_offset,
 668                  char __user *data,
 669                  int length)
 670 {
 671         char *vaddr;
 672         int ret;
 673
 674         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 675         ret = __copy_from_user_inatomic(vaddr + page_offset, data, length);
 676         kunmap_atomic(vaddr, KM_USER0);
 677
 678         return ret;
 679 }
 680
 681 /**
 682  * This is the fast pwrite path, where we copy the data directly from the
 683  * user into the GTT, uncached.
 684  */
 685 static int
 686 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 687                          struct drm_i915_gem_pwrite *args,
 688                          struct drm_file *file_priv)
 689 {
 690         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 691         drm_i915_private_t *dev_priv = dev->dev_private;
 692         ssize_t remain;
 693         loff_t offset, page_base;
 694         char __user *user_data;
 695         int page_offset, page_length;
 696
 697         user_data = (char __user *) (uintptr_t) args->data_ptr;
 698         remain = args->size;
 699
 700         obj_priv = to_intel_bo(obj);
 701         offset = obj_priv->gtt_offset + args->offset;
 702
 703         while (remain > 0) {
 704                 /* Operation in this page
 705                  *
 706                  * page_base = page offset within aperture
 707                  * page_offset = offset within page
 708                  * page_length = bytes to copy for this page
 709                  */
 710                 page_base = (offset & ~(PAGE_SIZE-1));
 711                 page_offset = offset & (PAGE_SIZE-1);
 712                 page_length = remain;
 713                 if ((page_offset + remain) > PAGE_SIZE)
 714                         page_length = PAGE_SIZE - page_offset;
 715
 716                 /* If we get a fault while copying data, then (presumably) our
 717                  * source page isn't available.  Return the error and we'll
 718                  * retry in the slow path.
 719                  */
 720                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 721                                     page_offset, user_data, page_length))
 722
 723                         return -EFAULT;
 724
 725                 remain -= page_length;
 726                 user_data += page_length;
 727                 offset += page_length;
 728         }
 729
 730         return 0;
 731 }
 732
 733 /**
 734  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 735  * the memory and maps it using kmap_atomic for copying.
 736  *
 737  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 738  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 739  */
 740 static int
 741 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 742                          struct drm_i915_gem_pwrite *args,
 743                          struct drm_file *file_priv)
 744 {
 745         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 746         drm_i915_private_t *dev_priv = dev->dev_private;
 747         ssize_t remain;
 748         loff_t gtt_page_base, offset;
 749         loff_t first_data_page, last_data_page, num_pages;
 750         loff_t pinned_pages, i;
 751         struct page **user_pages;
 752         struct mm_struct *mm = current->mm;
 753         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 754         int ret;
 755         uint64_t data_ptr = args->data_ptr;
 756
 757         remain = args->size;
 758
 759         /* Pin the user pages containing the data.  We can't fault while
 760          * holding the struct mutex, and all of the pwrite implementations
 761          * want to hold it while dereferencing the user data.
 762          */
 763         first_data_page = data_ptr / PAGE_SIZE;
 764         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 765         num_pages = last_data_page - first_data_page + 1;
 766
 767         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 768         if (user_pages == NULL)
 769                 return -ENOMEM;
 770
 771         mutex_unlock(&dev->struct_mutex);
 772         down_read(&mm->mmap_sem);
 773         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 774                                       num_pages, 0, 0, user_pages, NULL);
 775         up_read(&mm->mmap_sem);
 776         mutex_lock(&dev->struct_mutex);
 777         if (pinned_pages < num_pages) {
 778                 ret = -EFAULT;
 779                 goto out_unpin_pages;
 780         }
 781
 782         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 783         if (ret)
 784                 goto out_unpin_pages;
 785
 786         obj_priv = to_intel_bo(obj);
 787         offset = obj_priv->gtt_offset + args->offset;
 788
 789         while (remain > 0) {
 790                 /* Operation in this page
 791                  *
 792                  * gtt_page_base = page offset within aperture
 793                  * gtt_page_offset = offset within page in aperture
 794                  * data_page_index = page number in get_user_pages return
 795                  * data_page_offset = offset with data_page_index page.
 796                  * page_length = bytes to copy for this page
 797                  */
 798                 gtt_page_base = offset & PAGE_MASK;
 799                 gtt_page_offset = offset & ~PAGE_MASK;
 800                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 801                 data_page_offset = data_ptr & ~PAGE_MASK;
 802
 803                 page_length = remain;
 804                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 805                         page_length = PAGE_SIZE - gtt_page_offset;
 806                 if ((data_page_offset + page_length) > PAGE_SIZE)
 807                         page_length = PAGE_SIZE - data_page_offset;
 808
 809                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 810                                   gtt_page_base, gtt_page_offset,
 811                                   user_pages[data_page_index],
 812                                   data_page_offset,
 813                                   page_length);
 814
 815                 remain -= page_length;
 816                 offset += page_length;
 817                 data_ptr += page_length;
 818         }
 819
 820 out_unpin_pages:
 821         for (i = 0; i < pinned_pages; i++)
 822                 page_cache_release(user_pages[i]);
 823         drm_free_large(user_pages);
 824
 825         return ret;
 826 }
 827
 828 /**
 829  * This is the fast shmem pwrite path, which attempts to directly
 830  * copy_from_user into the kmapped pages backing the object.
 831  */
 832 static int
 833 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 834                            struct drm_i915_gem_pwrite *args,
 835                            struct drm_file *file_priv)
 836 {
 837         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 838         ssize_t remain;
 839         loff_t offset, page_base;
 840         char __user *user_data;
 841         int page_offset, page_length;
 842
 843         user_data = (char __user *) (uintptr_t) args->data_ptr;
 844         remain = args->size;
 845
 846         obj_priv = to_intel_bo(obj);
 847         offset = args->offset;
 848         obj_priv->dirty = 1;
 849
 850         while (remain > 0) {
 851                 /* Operation in this page
 852                  *
 853                  * page_base = page offset within aperture
 854                  * page_offset = offset within page
 855                  * page_length = bytes to copy for this page
 856                  */
 857                 page_base = (offset & ~(PAGE_SIZE-1));
 858                 page_offset = offset & (PAGE_SIZE-1);
 859                 page_length = remain;
 860                 if ((page_offset + remain) > PAGE_SIZE)
 861                         page_length = PAGE_SIZE - page_offset;
 862
 863                 if (fast_shmem_write(obj_priv->pages,
 864                                        page_base, page_offset,
 865                                        user_data, page_length))
 866                         return -EFAULT;
 867
 868                 remain -= page_length;
 869                 user_data += page_length;
 870                 offset += page_length;
 871         }
 872
 873         return 0;
 874 }
 875
 876 /**
 877  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 878  * the memory and maps it using kmap_atomic for copying.
 879  *
 880  * This avoids taking mmap_sem for faulting on the user's address while the
 881  * struct_mutex is held.
 882  */
 883 static int
 884 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 885                            struct drm_i915_gem_pwrite *args,
 886                            struct drm_file *file_priv)
 887 {
 888         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 889         struct mm_struct *mm = current->mm;
 890         struct page **user_pages;
 891         ssize_t remain;
 892         loff_t offset, pinned_pages, i;
 893         loff_t first_data_page, last_data_page, num_pages;
 894         int shmem_page_index, shmem_page_offset;
 895         int data_page_index,  data_page_offset;
 896         int page_length;
 897         int ret;
 898         uint64_t data_ptr = args->data_ptr;
 899         int do_bit17_swizzling;
 900
 901         remain = args->size;
 902
 903         /* Pin the user pages containing the data.  We can't fault while
 904          * holding the struct mutex, and all of the pwrite implementations
 905          * want to hold it while dereferencing the user data.
 906          */
 907         first_data_page = data_ptr / PAGE_SIZE;
 908         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 909         num_pages = last_data_page - first_data_page + 1;
 910
 911         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 912         if (user_pages == NULL)
 913                 return -ENOMEM;
 914
 915         mutex_unlock(&dev->struct_mutex);
 916         down_read(&mm->mmap_sem);
 917         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 918                                       num_pages, 0, 0, user_pages, NULL);
 919         up_read(&mm->mmap_sem);
 920         mutex_lock(&dev->struct_mutex);
 921         if (pinned_pages < num_pages) {
 922                 ret = -EFAULT;
 923                 goto out;
 924         }
 925
 926         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 927         if (ret)
 928                 goto out;
 929
 930         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 931
 932         obj_priv = to_intel_bo(obj);
 933         offset = args->offset;
 934         obj_priv->dirty = 1;
 935
 936         while (remain > 0) {
 937                 /* Operation in this page
 938                  *
 939                  * shmem_page_index = page number within shmem file
 940                  * shmem_page_offset = offset within page in shmem file
 941                  * data_page_index = page number in get_user_pages return
 942                  * data_page_offset = offset with data_page_index page.
 943                  * page_length = bytes to copy for this page
 944                  */
 945                 shmem_page_index = offset / PAGE_SIZE;
 946                 shmem_page_offset = offset & ~PAGE_MASK;
 947                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 948                 data_page_offset = data_ptr & ~PAGE_MASK;
 949
 950                 page_length = remain;
 951                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 952                         page_length = PAGE_SIZE - shmem_page_offset;
 953                 if ((data_page_offset + page_length) > PAGE_SIZE)
 954                         page_length = PAGE_SIZE - data_page_offset;
 955
 956                 if (do_bit17_swizzling) {
 957                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 958                                               shmem_page_offset,
 959                                               user_pages[data_page_index],
 960                                               data_page_offset,
 961                                               page_length,
 962                                               0);
 963                 } else {
 964                         slow_shmem_copy(obj_priv->pages[shmem_page_index],
 965                                         shmem_page_offset,
 966                                         user_pages[data_page_index],
 967                                         data_page_offset,
 968                                         page_length);
 969                 }
 970
 971                 remain -= page_length;
 972                 data_ptr += page_length;
 973                 offset += page_length;
 974         }
 975
 976 out:
 977         for (i = 0; i < pinned_pages; i++)
 978                 page_cache_release(user_pages[i]);
 979         drm_free_large(user_pages);
 980
 981         return ret;
 982 }
 983
 984 /**
 985  * Writes data to the object referenced by handle.
 986  *
 987  * On error, the contents of the buffer that were to be modified are undefined.
 988  */
 989 int
 990 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 991                       struct drm_file *file)
 992 {
 993         struct drm_i915_gem_pwrite *args = data;
 994         struct drm_gem_object *obj;
 995         struct drm_i915_gem_object *obj_priv;
 996         int ret = 0;
 997
 998         obj = drm_gem_object_lookup(dev, file, args->handle);
 999         if (obj == NULL)
1000                 return -ENOENT;
1001         obj_priv = to_intel_bo(obj);
1002
1003         ret = i915_mutex_lock_interruptible(dev);
1004         if (ret) {
1005                 drm_gem_object_unreference_unlocked(obj);
1006                 return ret;
1007         }
1008
1009         /* Bounds check destination. */
1010         if (args->offset > obj->size || args->size > obj->size - args->offset) {
1011                 ret = -EINVAL;
1012                 goto out;
1013         }
1014
1015         if (args->size == 0)
1016                 goto out;
1017
1018         if (!access_ok(VERIFY_READ,
1019                        (char __user *)(uintptr_t)args->data_ptr,
1020                        args->size)) {
1021                 ret = -EFAULT;
1022                 goto out;
1023         }
1024
1025         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
1026                                       args->size);
1027         if (ret) {
1028                 ret = -EFAULT;
1029                 goto out;
1030         }
1031
1032         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1033          * it would end up going through the fenced access, and we'll get
1034          * different detiling behavior between reading and writing.
1035          * pread/pwrite currently are reading and writing from the CPU
1036          * perspective, requiring manual detiling by the client.
1037          */
1038         if (obj_priv->phys_obj)
1039                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
1040         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
1041                  obj_priv->gtt_space &&
1042                  obj->write_domain != I915_GEM_DOMAIN_CPU) {
1043                 ret = i915_gem_object_pin(obj, 0);
1044                 if (ret)
1045                         goto out;
1046
1047                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1048                 if (ret)
1049                         goto out_unpin;
1050
1051                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1052                 if (ret == -EFAULT)
1053                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1054
1055 out_unpin:
1056                 i915_gem_object_unpin(obj);
1057         } else {
1058                 ret = i915_gem_object_get_pages_or_evict(obj);
1059                 if (ret)
1060                         goto out;
1061
1062                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1063                 if (ret)
1064                         goto out_put;
1065
1066                 ret = -EFAULT;
1067                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1068                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1069                 if (ret == -EFAULT)
1070                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1071
1072 out_put:
1073                 i915_gem_object_put_pages(obj);
1074         }
1075
1076 out:
1077         drm_gem_object_unreference(obj);
1078         mutex_unlock(&dev->struct_mutex);
1079         return ret;
1080 }
1081
1082 /**
1083  * Called when user space prepares to use an object with the CPU, either
1084  * through the mmap ioctl's mapping or a GTT mapping.
1085  */
1086 int
1087 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1088                           struct drm_file *file_priv)
1089 {
1090         struct drm_i915_private *dev_priv = dev->dev_private;
1091         struct drm_i915_gem_set_domain *args = data;
1092         struct drm_gem_object *obj;
1093         struct drm_i915_gem_object *obj_priv;
1094         uint32_t read_domains = args->read_domains;
1095         uint32_t write_domain = args->write_domain;
1096         int ret;
1097
1098         if (!(dev->driver->driver_features & DRIVER_GEM))
1099                 return -ENODEV;
1100
1101         /* Only handle setting domains to types used by the CPU. */
1102         if (write_domain & I915_GEM_GPU_DOMAINS)
1103                 return -EINVAL;
1104
1105         if (read_domains & I915_GEM_GPU_DOMAINS)
1106                 return -EINVAL;
1107
1108         /* Having something in the write domain implies it's in the read
1109          * domain, and only that read domain.  Enforce that in the request.
1110          */
1111         if (write_domain != 0 && read_domains != write_domain)
1112                 return -EINVAL;
1113
1114         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1115         if (obj == NULL)
1116                 return -ENOENT;
1117         obj_priv = to_intel_bo(obj);
1118
1119         ret = i915_mutex_lock_interruptible(dev);
1120         if (ret) {
1121                 drm_gem_object_unreference_unlocked(obj);
1122                 return ret;
1123         }
1124
1125         intel_mark_busy(dev, obj);
1126
1127         if (read_domains & I915_GEM_DOMAIN_GTT) {
1128                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1129
1130                 /* Update the LRU on the fence for the CPU access that's
1131                  * about to occur.
1132                  */
1133                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1134                         struct drm_i915_fence_reg *reg =
1135                                 &dev_priv->fence_regs[obj_priv->fence_reg];
1136                         list_move_tail(&reg->lru_list,
1137                                        &dev_priv->mm.fence_list);
1138                 }
1139
1140                 /* Silently promote "you're not bound, there was nothing to do"
1141                  * to success, since the client was just asking us to
1142                  * make sure everything was done.
1143                  */
1144                 if (ret == -EINVAL)
1145                         ret = 0;
1146         } else {
1147                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1148         }
1149
1150         /* Maintain LRU order of "inactive" objects */
1151         if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1152                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1153
1154         drm_gem_object_unreference(obj);
1155         mutex_unlock(&dev->struct_mutex);
1156         return ret;
1157 }
1158
1159 /**
1160  * Called when user space has done writes to this buffer
1161  */
1162 int
1163 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1164                       struct drm_file *file_priv)
1165 {
1166         struct drm_i915_gem_sw_finish *args = data;
1167         struct drm_gem_object *obj;
1168         int ret = 0;
1169
1170         if (!(dev->driver->driver_features & DRIVER_GEM))
1171                 return -ENODEV;
1172
1173         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1174         if (obj == NULL)
1175                 return -ENOENT;
1176
1177         ret = i915_mutex_lock_interruptible(dev);
1178         if (ret) {
1179                 drm_gem_object_unreference_unlocked(obj);
1180                 return ret;
1181         }
1182
1183         /* Pinned buffers may be scanout, so flush the cache */
1184         if (to_intel_bo(obj)->pin_count)
1185                 i915_gem_object_flush_cpu_write_domain(obj);
1186
1187         drm_gem_object_unreference(obj);
1188         mutex_unlock(&dev->struct_mutex);
1189         return ret;
1190 }
1191
1192 /**
1193  * Maps the contents of an object, returning the address it is mapped
1194  * into.
1195  *
1196  * While the mapping holds a reference on the contents of the object, it doesn't
1197  * imply a ref on the object itself.
1198  */
1199 int
1200 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1201                    struct drm_file *file_priv)
1202 {
1203         struct drm_i915_gem_mmap *args = data;
1204         struct drm_gem_object *obj;
1205         loff_t offset;
1206         unsigned long addr;
1207
1208         if (!(dev->driver->driver_features & DRIVER_GEM))
1209                 return -ENODEV;
1210
1211         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1212         if (obj == NULL)
1213                 return -ENOENT;
1214
1215         offset = args->offset;
1216
1217         down_write(&current->mm->mmap_sem);
1218         addr = do_mmap(obj->filp, 0, args->size,
1219                        PROT_READ | PROT_WRITE, MAP_SHARED,
1220                        args->offset);
1221         up_write(&current->mm->mmap_sem);
1222         drm_gem_object_unreference_unlocked(obj);
1223         if (IS_ERR((void *)addr))
1224                 return addr;
1225
1226         args->addr_ptr = (uint64_t) addr;
1227
1228         return 0;
1229 }
1230
1231 /**
1232  * i915_gem_fault - fault a page into the GTT
1233  * vma: VMA in question
1234  * vmf: fault info
1235  *
1236  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1237  * from userspace.  The fault handler takes care of binding the object to
1238  * the GTT (if needed), allocating and programming a fence register (again,
1239  * only if needed based on whether the old reg is still valid or the object
1240  * is tiled) and inserting a new PTE into the faulting process.
1241  *
1242  * Note that the faulting process may involve evicting existing objects
1243  * from the GTT and/or fence registers to make room.  So performance may
1244  * suffer if the GTT working set is large or there are few fence registers
1245  * left.
1246  */
1247 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1248 {
1249         struct drm_gem_object *obj = vma->vm_private_data;
1250         struct drm_device *dev = obj->dev;
1251         drm_i915_private_t *dev_priv = dev->dev_private;
1252         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1253         pgoff_t page_offset;
1254         unsigned long pfn;
1255         int ret = 0;
1256         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1257
1258         /* We don't use vmf->pgoff since that has the fake offset */
1259         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1260                 PAGE_SHIFT;
1261
1262         /* Now bind it into the GTT if needed */
1263         mutex_lock(&dev->struct_mutex);
1264         if (!obj_priv->gtt_space) {
1265                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1266                 if (ret)
1267                         goto unlock;
1268
1269                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1270                 if (ret)
1271                         goto unlock;
1272         }
1273
1274         /* Need a new fence register? */
1275         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1276                 ret = i915_gem_object_get_fence_reg(obj, true);
1277                 if (ret)
1278                         goto unlock;
1279         }
1280
1281         if (i915_gem_object_is_inactive(obj_priv))
1282                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1283
1284         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1285                 page_offset;
1286
1287         /* Finally, remap it using the new GTT offset */
1288         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1289 unlock:
1290         mutex_unlock(&dev->struct_mutex);
1291
1292         switch (ret) {
1293         case 0:
1294         case -ERESTARTSYS:
1295                 return VM_FAULT_NOPAGE;
1296         case -ENOMEM:
1297         case -EAGAIN:
1298                 return VM_FAULT_OOM;
1299         default:
1300                 return VM_FAULT_SIGBUS;
1301         }
1302 }
1303
1304 /**
1305  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1306  * @obj: obj in question
1307  *
1308  * GEM memory mapping works by handing back to userspace a fake mmap offset
1309  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1310  * up the object based on the offset and sets up the various memory mapping
1311  * structures.
1312  *
1313  * This routine allocates and attaches a fake offset for @obj.
1314  */
1315 static int
1316 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1317 {
1318         struct drm_device *dev = obj->dev;
1319         struct drm_gem_mm *mm = dev->mm_private;
1320         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1321         struct drm_map_list *list;
1322         struct drm_local_map *map;
1323         int ret = 0;
1324
1325         /* Set the object up for mmap'ing */
1326         list = &obj->map_list;
1327         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1328         if (!list->map)
1329                 return -ENOMEM;
1330
1331         map = list->map;
1332         map->type = _DRM_GEM;
1333         map->size = obj->size;
1334         map->handle = obj;
1335
1336         /* Get a DRM GEM mmap offset allocated... */
1337         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1338                                                     obj->size / PAGE_SIZE, 0, 0);
1339         if (!list->file_offset_node) {
1340                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1341                 ret = -ENOSPC;
1342                 goto out_free_list;
1343         }
1344
1345         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1346                                                   obj->size / PAGE_SIZE, 0);
1347         if (!list->file_offset_node) {
1348                 ret = -ENOMEM;
1349                 goto out_free_list;
1350         }
1351
1352         list->hash.key = list->file_offset_node->start;
1353         ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1354         if (ret) {
1355                 DRM_ERROR("failed to add to map hash\n");
1356                 goto out_free_mm;
1357         }
1358
1359         /* By now we should be all set, any drm_mmap request on the offset
1360          * below will get to our mmap & fault handler */
1361         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1362
1363         return 0;
1364
1365 out_free_mm:
1366         drm_mm_put_block(list->file_offset_node);
1367 out_free_list:
1368         kfree(list->map);
1369
1370         return ret;
1371 }
1372
1373 /**
1374  * i915_gem_release_mmap - remove physical page mappings
1375  * @obj: obj in question
1376  *
1377  * Preserve the reservation of the mmapping with the DRM core code, but
1378  * relinquish ownership of the pages back to the system.
1379  *
1380  * It is vital that we remove the page mapping if we have mapped a tiled
1381  * object through the GTT and then lose the fence register due to
1382  * resource pressure. Similarly if the object has been moved out of the
1383  * aperture, than pages mapped into userspace must be revoked. Removing the
1384  * mapping will then trigger a page fault on the next user access, allowing
1385  * fixup by i915_gem_fault().
1386  */
1387 void
1388 i915_gem_release_mmap(struct drm_gem_object *obj)
1389 {
1390         struct drm_device *dev = obj->dev;
1391         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1392
1393         if (dev->dev_mapping)
1394                 unmap_mapping_range(dev->dev_mapping,
1395                                     obj_priv->mmap_offset, obj->size, 1);
1396 }
1397
1398 static void
1399 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1400 {
1401         struct drm_device *dev = obj->dev;
1402         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1403         struct drm_gem_mm *mm = dev->mm_private;
1404         struct drm_map_list *list;
1405
1406         list = &obj->map_list;
1407         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1408
1409         if (list->file_offset_node) {
1410                 drm_mm_put_block(list->file_offset_node);
1411                 list->file_offset_node = NULL;
1412         }
1413
1414         if (list->map) {
1415                 kfree(list->map);
1416                 list->map = NULL;
1417         }
1418
1419         obj_priv->mmap_offset = 0;
1420 }
1421
1422 /**
1423  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1424  * @obj: object to check
1425  *
1426  * Return the required GTT alignment for an object, taking into account
1427  * potential fence register mapping if needed.
1428  */
1429 static uint32_t
1430 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1431 {
1432         struct drm_device *dev = obj->dev;
1433         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1434         int start, i;
1435
1436         /*
1437          * Minimum alignment is 4k (GTT page size), but might be greater
1438          * if a fence register is needed for the object.
1439          */
1440         if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE)
1441                 return 4096;
1442
1443         /*
1444          * Previous chips need to be aligned to the size of the smallest
1445          * fence register that can contain the object.
1446          */
1447         if (INTEL_INFO(dev)->gen == 3)
1448                 start = 1024*1024;
1449         else
1450                 start = 512*1024;
1451
1452         for (i = start; i < obj->size; i <<= 1)
1453                 ;
1454
1455         return i;
1456 }
1457
1458 /**
1459  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1460  * @dev: DRM device
1461  * @data: GTT mapping ioctl data
1462  * @file_priv: GEM object info
1463  *
1464  * Simply returns the fake offset to userspace so it can mmap it.
1465  * The mmap call will end up in drm_gem_mmap(), which will set things
1466  * up so we can get faults in the handler above.
1467  *
1468  * The fault handler will take care of binding the object into the GTT
1469  * (since it may have been evicted to make room for something), allocating
1470  * a fence register, and mapping the appropriate aperture address into
1471  * userspace.
1472  */
1473 int
1474 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1475                         struct drm_file *file_priv)
1476 {
1477         struct drm_i915_gem_mmap_gtt *args = data;
1478         struct drm_gem_object *obj;
1479         struct drm_i915_gem_object *obj_priv;
1480         int ret;
1481
1482         if (!(dev->driver->driver_features & DRIVER_GEM))
1483                 return -ENODEV;
1484
1485         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1486         if (obj == NULL)
1487                 return -ENOENT;
1488
1489         ret = i915_mutex_lock_interruptible(dev);
1490         if (ret) {
1491                 drm_gem_object_unreference_unlocked(obj);
1492                 return ret;
1493         }
1494
1495         obj_priv = to_intel_bo(obj);
1496
1497         if (obj_priv->madv != I915_MADV_WILLNEED) {
1498                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1499                 drm_gem_object_unreference(obj);
1500                 mutex_unlock(&dev->struct_mutex);
1501                 return -EINVAL;
1502         }
1503
1504
1505         if (!obj_priv->mmap_offset) {
1506                 ret = i915_gem_create_mmap_offset(obj);
1507                 if (ret) {
1508                         drm_gem_object_unreference(obj);
1509                         mutex_unlock(&dev->struct_mutex);
1510                         return ret;
1511                 }
1512         }
1513
1514         args->offset = obj_priv->mmap_offset;
1515
1516         /*
1517          * Pull it into the GTT so that we have a page list (makes the
1518          * initial fault faster and any subsequent flushing possible).
1519          */
1520         if (!obj_priv->agp_mem) {
1521                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1522                 if (ret) {
1523                         drm_gem_object_unreference(obj);
1524                         mutex_unlock(&dev->struct_mutex);
1525                         return ret;
1526                 }
1527         }
1528
1529         drm_gem_object_unreference(obj);
1530         mutex_unlock(&dev->struct_mutex);
1531
1532         return 0;
1533 }
1534
1535 static void
1536 i915_gem_object_put_pages(struct drm_gem_object *obj)
1537 {
1538         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1539         int page_count = obj->size / PAGE_SIZE;
1540         int i;
1541
1542         BUG_ON(obj_priv->pages_refcount == 0);
1543         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1544
1545         if (--obj_priv->pages_refcount != 0)
1546                 return;
1547
1548         if (obj_priv->tiling_mode != I915_TILING_NONE)
1549                 i915_gem_object_save_bit_17_swizzle(obj);
1550
1551         if (obj_priv->madv == I915_MADV_DONTNEED)
1552                 obj_priv->dirty = 0;
1553
1554         for (i = 0; i < page_count; i++) {
1555                 if (obj_priv->dirty)
1556                         set_page_dirty(obj_priv->pages[i]);
1557
1558                 if (obj_priv->madv == I915_MADV_WILLNEED)
1559                         mark_page_accessed(obj_priv->pages[i]);
1560
1561                 page_cache_release(obj_priv->pages[i]);
1562         }
1563         obj_priv->dirty = 0;
1564
1565         drm_free_large(obj_priv->pages);
1566         obj_priv->pages = NULL;
1567 }
1568
1569 static uint32_t
1570 i915_gem_next_request_seqno(struct drm_device *dev,
1571                             struct intel_ring_buffer *ring)
1572 {
1573         drm_i915_private_t *dev_priv = dev->dev_private;
1574
1575         ring->outstanding_lazy_request = true;
1576         return dev_priv->next_seqno;
1577 }
1578
1579 static void
1580 i915_gem_object_move_to_active(struct drm_gem_object *obj,
1581                                struct intel_ring_buffer *ring)
1582 {
1583         struct drm_device *dev = obj->dev;
1584         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1585         uint32_t seqno = i915_gem_next_request_seqno(dev, ring);
1586
1587         BUG_ON(ring == NULL);
1588         obj_priv->ring = ring;
1589
1590         /* Add a reference if we're newly entering the active list. */
1591         if (!obj_priv->active) {
1592                 drm_gem_object_reference(obj);
1593                 obj_priv->active = 1;
1594         }
1595
1596         /* Move from whatever list we were on to the tail of execution. */
1597         list_move_tail(&obj_priv->list, &ring->active_list);
1598         obj_priv->last_rendering_seqno = seqno;
1599 }
1600
1601 static void
1602 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1603 {
1604         struct drm_device *dev = obj->dev;
1605         drm_i915_private_t *dev_priv = dev->dev_private;
1606         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1607
1608         BUG_ON(!obj_priv->active);
1609         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1610         obj_priv->last_rendering_seqno = 0;
1611 }
1612
1613 /* Immediately discard the backing storage */
1614 static void
1615 i915_gem_object_truncate(struct drm_gem_object *obj)
1616 {
1617         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1618         struct inode *inode;
1619
1620         /* Our goal here is to return as much of the memory as
1621          * is possible back to the system as we are called from OOM.
1622          * To do this we must instruct the shmfs to drop all of its
1623          * backing pages, *now*. Here we mirror the actions taken
1624          * when by shmem_delete_inode() to release the backing store.
1625          */
1626         inode = obj->filp->f_path.dentry->d_inode;
1627         truncate_inode_pages(inode->i_mapping, 0);
1628         if (inode->i_op->truncate_range)
1629                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1630
1631         obj_priv->madv = __I915_MADV_PURGED;
1632 }
1633
1634 static inline int
1635 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1636 {
1637         return obj_priv->madv == I915_MADV_DONTNEED;
1638 }
1639
1640 static void
1641 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1642 {
1643         struct drm_device *dev = obj->dev;
1644         drm_i915_private_t *dev_priv = dev->dev_private;
1645         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1646
1647         if (obj_priv->pin_count != 0)
1648                 list_move_tail(&obj_priv->list, &dev_priv->mm.pinned_list);
1649         else
1650                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1651
1652         BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1653
1654         obj_priv->last_rendering_seqno = 0;
1655         obj_priv->ring = NULL;
1656         if (obj_priv->active) {
1657                 obj_priv->active = 0;
1658                 drm_gem_object_unreference(obj);
1659         }
1660         WARN_ON(i915_verify_lists(dev));
1661 }
1662
1663 static void
1664 i915_gem_process_flushing_list(struct drm_device *dev,
1665                                uint32_t flush_domains,
1666                                struct intel_ring_buffer *ring)
1667 {
1668         drm_i915_private_t *dev_priv = dev->dev_private;
1669         struct drm_i915_gem_object *obj_priv, *next;
1670
1671         list_for_each_entry_safe(obj_priv, next,
1672                                  &dev_priv->mm.gpu_write_list,
1673                                  gpu_write_list) {
1674                 struct drm_gem_object *obj = &obj_priv->base;
1675
1676                 if (obj->write_domain & flush_domains &&
1677                     obj_priv->ring == ring) {
1678                         uint32_t old_write_domain = obj->write_domain;
1679
1680                         obj->write_domain = 0;
1681                         list_del_init(&obj_priv->gpu_write_list);
1682                         i915_gem_object_move_to_active(obj, ring);
1683
1684                         /* update the fence lru list */
1685                         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1686                                 struct drm_i915_fence_reg *reg =
1687                                         &dev_priv->fence_regs[obj_priv->fence_reg];
1688                                 list_move_tail(&reg->lru_list,
1689                                                 &dev_priv->mm.fence_list);
1690                         }
1691
1692                         trace_i915_gem_object_change_domain(obj,
1693                                                             obj->read_domains,
1694                                                             old_write_domain);
1695                 }
1696         }
1697 }
1698
1699 uint32_t
1700 i915_add_request(struct drm_device *dev,
1701                  struct drm_file *file,
1702                  struct drm_i915_gem_request *request,
1703                  struct intel_ring_buffer *ring)
1704 {
1705         drm_i915_private_t *dev_priv = dev->dev_private;
1706         struct drm_i915_file_private *file_priv = NULL;
1707         uint32_t seqno;
1708         int was_empty;
1709
1710         if (file != NULL)
1711                 file_priv = file->driver_priv;
1712
1713         if (request == NULL) {
1714                 request = kzalloc(sizeof(*request), GFP_KERNEL);
1715                 if (request == NULL)
1716                         return 0;
1717         }
1718
1719         seqno = ring->add_request(dev, ring, 0);
1720         ring->outstanding_lazy_request = false;
1721
1722         request->seqno = seqno;
1723         request->ring = ring;
1724         request->emitted_jiffies = jiffies;
1725         was_empty = list_empty(&ring->request_list);
1726         list_add_tail(&request->list, &ring->request_list);
1727
1728         if (file_priv) {
1729                 spin_lock(&file_priv->mm.lock);
1730                 request->file_priv = file_priv;
1731                 list_add_tail(&request->client_list,
1732                               &file_priv->mm.request_list);
1733                 spin_unlock(&file_priv->mm.lock);
1734         }
1735
1736         if (!dev_priv->mm.suspended) {
1737                 mod_timer(&dev_priv->hangcheck_timer,
1738                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1739                 if (was_empty)
1740                         queue_delayed_work(dev_priv->wq,
1741                                            &dev_priv->mm.retire_work, HZ);
1742         }
1743         return seqno;
1744 }
1745
1746 /**
1747  * Command execution barrier
1748  *
1749  * Ensures that all commands in the ring are finished
1750  * before signalling the CPU
1751  */
1752 static void
1753 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1754 {
1755         uint32_t flush_domains = 0;
1756
1757         /* The sampler always gets flushed on i965 (sigh) */
1758         if (INTEL_INFO(dev)->gen >= 4)
1759                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1760
1761         ring->flush(dev, ring,
1762                         I915_GEM_DOMAIN_COMMAND, flush_domains);
1763 }
1764
1765 static inline void
1766 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1767 {
1768         struct drm_i915_file_private *file_priv = request->file_priv;
1769
1770         if (!file_priv)
1771                 return;
1772
1773         spin_lock(&file_priv->mm.lock);
1774         list_del(&request->client_list);
1775         request->file_priv = NULL;
1776         spin_unlock(&file_priv->mm.lock);
1777 }
1778
1779 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1780                                       struct intel_ring_buffer *ring)
1781 {
1782         while (!list_empty(&ring->request_list)) {
1783                 struct drm_i915_gem_request *request;
1784
1785                 request = list_first_entry(&ring->request_list,
1786                                            struct drm_i915_gem_request,
1787                                            list);
1788
1789                 list_del(&request->list);
1790                 i915_gem_request_remove_from_client(request);
1791                 kfree(request);
1792         }
1793
1794         while (!list_empty(&ring->active_list)) {
1795                 struct drm_i915_gem_object *obj_priv;
1796
1797                 obj_priv = list_first_entry(&ring->active_list,
1798                                             struct drm_i915_gem_object,
1799                                             list);
1800
1801                 obj_priv->base.write_domain = 0;
1802                 list_del_init(&obj_priv->gpu_write_list);
1803                 i915_gem_object_move_to_inactive(&obj_priv->base);
1804         }
1805 }
1806
1807 void i915_gem_reset(struct drm_device *dev)
1808 {
1809         struct drm_i915_private *dev_priv = dev->dev_private;
1810         struct drm_i915_gem_object *obj_priv;
1811         int i;
1812
1813         i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring);
1814         if (HAS_BSD(dev))
1815                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring);
1816
1817         /* Remove anything from the flushing lists. The GPU cache is likely
1818          * to be lost on reset along with the data, so simply move the
1819          * lost bo to the inactive list.
1820          */
1821         while (!list_empty(&dev_priv->mm.flushing_list)) {
1822                 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1823                                             struct drm_i915_gem_object,
1824                                             list);
1825
1826                 obj_priv->base.write_domain = 0;
1827                 list_del_init(&obj_priv->gpu_write_list);
1828                 i915_gem_object_move_to_inactive(&obj_priv->base);
1829         }
1830
1831         /* Move everything out of the GPU domains to ensure we do any
1832          * necessary invalidation upon reuse.
1833          */
1834         list_for_each_entry(obj_priv,
1835                             &dev_priv->mm.inactive_list,
1836                             list)
1837         {
1838                 obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1839         }
1840
1841         /* The fence registers are invalidated so clear them out */
1842         for (i = 0; i < 16; i++) {
1843                 struct drm_i915_fence_reg *reg;
1844
1845                 reg = &dev_priv->fence_regs[i];
1846                 if (!reg->obj)
1847                         continue;
1848
1849                 i915_gem_clear_fence_reg(reg->obj);
1850         }
1851 }
1852
1853 /**
1854  * This function clears the request list as sequence numbers are passed.
1855  */
1856 static void
1857 i915_gem_retire_requests_ring(struct drm_device *dev,
1858                               struct intel_ring_buffer *ring)
1859 {
1860         drm_i915_private_t *dev_priv = dev->dev_private;
1861         uint32_t seqno;
1862
1863         if (!ring->status_page.page_addr ||
1864             list_empty(&ring->request_list))
1865                 return;
1866
1867         WARN_ON(i915_verify_lists(dev));
1868
1869         seqno = ring->get_seqno(dev, ring);
1870         while (!list_empty(&ring->request_list)) {
1871                 struct drm_i915_gem_request *request;
1872
1873                 request = list_first_entry(&ring->request_list,
1874                                            struct drm_i915_gem_request,
1875                                            list);
1876
1877                 if (!i915_seqno_passed(seqno, request->seqno))
1878                         break;
1879
1880                 trace_i915_gem_request_retire(dev, request->seqno);
1881
1882                 list_del(&request->list);
1883                 i915_gem_request_remove_from_client(request);
1884                 kfree(request);
1885         }
1886
1887         /* Move any buffers on the active list that are no longer referenced
1888          * by the ringbuffer to the flushing/inactive lists as appropriate.
1889          */
1890         while (!list_empty(&ring->active_list)) {
1891                 struct drm_gem_object *obj;
1892                 struct drm_i915_gem_object *obj_priv;
1893
1894                 obj_priv = list_first_entry(&ring->active_list,
1895                                             struct drm_i915_gem_object,
1896                                             list);
1897
1898                 if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno))
1899                         break;
1900
1901                 obj = &obj_priv->base;
1902                 if (obj->write_domain != 0)
1903                         i915_gem_object_move_to_flushing(obj);
1904                 else
1905                         i915_gem_object_move_to_inactive(obj);
1906         }
1907
1908         if (unlikely (dev_priv->trace_irq_seqno &&
1909                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1910                 ring->user_irq_put(dev, ring);
1911                 dev_priv->trace_irq_seqno = 0;
1912         }
1913
1914         WARN_ON(i915_verify_lists(dev));
1915 }
1916
1917 void
1918 i915_gem_retire_requests(struct drm_device *dev)
1919 {
1920         drm_i915_private_t *dev_priv = dev->dev_private;
1921
1922         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1923             struct drm_i915_gem_object *obj_priv, *tmp;
1924
1925             /* We must be careful that during unbind() we do not
1926              * accidentally infinitely recurse into retire requests.
1927              * Currently:
1928              *   retire -> free -> unbind -> wait -> retire_ring
1929              */
1930             list_for_each_entry_safe(obj_priv, tmp,
1931                                      &dev_priv->mm.deferred_free_list,
1932                                      list)
1933                     i915_gem_free_object_tail(&obj_priv->base);
1934         }
1935
1936         i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1937         if (HAS_BSD(dev))
1938                 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1939 }
1940
1941 static void
1942 i915_gem_retire_work_handler(struct work_struct *work)
1943 {
1944         drm_i915_private_t *dev_priv;
1945         struct drm_device *dev;
1946
1947         dev_priv = container_of(work, drm_i915_private_t,
1948                                 mm.retire_work.work);
1949         dev = dev_priv->dev;
1950
1951         /* Come back later if the device is busy... */
1952         if (!mutex_trylock(&dev->struct_mutex)) {
1953                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1954                 return;
1955         }
1956
1957         i915_gem_retire_requests(dev);
1958
1959         if (!dev_priv->mm.suspended &&
1960                 (!list_empty(&dev_priv->render_ring.request_list) ||
1961                         (HAS_BSD(dev) &&
1962                          !list_empty(&dev_priv->bsd_ring.request_list))))
1963                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1964         mutex_unlock(&dev->struct_mutex);
1965 }
1966
1967 int
1968 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1969                      bool interruptible, struct intel_ring_buffer *ring)
1970 {
1971         drm_i915_private_t *dev_priv = dev->dev_private;
1972         u32 ier;
1973         int ret = 0;
1974
1975         BUG_ON(seqno == 0);
1976
1977         if (atomic_read(&dev_priv->mm.wedged))
1978                 return -EAGAIN;
1979
1980         if (ring->outstanding_lazy_request) {
1981                 seqno = i915_add_request(dev, NULL, NULL, ring);
1982                 if (seqno == 0)
1983                         return -ENOMEM;
1984         }
1985         BUG_ON(seqno == dev_priv->next_seqno);
1986
1987         if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) {
1988                 if (HAS_PCH_SPLIT(dev))
1989                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1990                 else
1991                         ier = I915_READ(IER);
1992                 if (!ier) {
1993                         DRM_ERROR("something (likely vbetool) disabled "
1994                                   "interrupts, re-enabling\n");
1995                         i915_driver_irq_preinstall(dev);
1996                         i915_driver_irq_postinstall(dev);
1997                 }
1998
1999                 trace_i915_gem_request_wait_begin(dev, seqno);
2000
2001                 ring->waiting_gem_seqno = seqno;
2002                 ring->user_irq_get(dev, ring);
2003                 if (interruptible)
2004                         ret = wait_event_interruptible(ring->irq_queue,
2005                                 i915_seqno_passed(
2006                                         ring->get_seqno(dev, ring), seqno)
2007                                 || atomic_read(&dev_priv->mm.wedged));
2008                 else
2009                         wait_event(ring->irq_queue,
2010                                 i915_seqno_passed(
2011                                         ring->get_seqno(dev, ring), seqno)
2012                                 || atomic_read(&dev_priv->mm.wedged));
2013
2014                 ring->user_irq_put(dev, ring);
2015                 ring->waiting_gem_seqno = 0;
2016
2017                 trace_i915_gem_request_wait_end(dev, seqno);
2018         }
2019         if (atomic_read(&dev_priv->mm.wedged))
2020                 ret = -EAGAIN;
2021
2022         if (ret && ret != -ERESTARTSYS)
2023                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2024                           __func__, ret, seqno, ring->get_seqno(dev, ring),
2025                           dev_priv->next_seqno);
2026
2027         /* Directly dispatch request retiring.  While we have the work queue
2028          * to handle this, the waiter on a request often wants an associated
2029          * buffer to have made it to the inactive list, and we would need
2030          * a separate wait queue to handle that.
2031          */
2032         if (ret == 0)
2033                 i915_gem_retire_requests_ring(dev, ring);
2034
2035         return ret;
2036 }
2037
2038 /**
2039  * Waits for a sequence number to be signaled, and cleans up the
2040  * request and object lists appropriately for that event.
2041  */
2042 static int
2043 i915_wait_request(struct drm_device *dev, uint32_t seqno,
2044                   struct intel_ring_buffer *ring)
2045 {
2046         return i915_do_wait_request(dev, seqno, 1, ring);
2047 }
2048
2049 static void
2050 i915_gem_flush_ring(struct drm_device *dev,
2051                     struct drm_file *file_priv,
2052                     struct intel_ring_buffer *ring,
2053                     uint32_t invalidate_domains,
2054                     uint32_t flush_domains)
2055 {
2056         ring->flush(dev, ring, invalidate_domains, flush_domains);
2057         i915_gem_process_flushing_list(dev, flush_domains, ring);
2058 }
2059
2060 static void
2061 i915_gem_flush(struct drm_device *dev,
2062                struct drm_file *file_priv,
2063                uint32_t invalidate_domains,
2064                uint32_t flush_domains,
2065                uint32_t flush_rings)
2066 {
2067         drm_i915_private_t *dev_priv = dev->dev_private;
2068
2069         if (flush_domains & I915_GEM_DOMAIN_CPU)
2070                 drm_agp_chipset_flush(dev);
2071
2072         if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
2073                 if (flush_rings & RING_RENDER)
2074                         i915_gem_flush_ring(dev, file_priv,
2075                                             &dev_priv->render_ring,
2076                                             invalidate_domains, flush_domains);
2077                 if (flush_rings & RING_BSD)
2078                         i915_gem_flush_ring(dev, file_priv,
2079                                             &dev_priv->bsd_ring,
2080                                             invalidate_domains, flush_domains);
2081         }
2082 }
2083
2084 /**
2085  * Ensures that all rendering to the object has completed and the object is
2086  * safe to unbind from the GTT or access from the CPU.
2087  */
2088 static int
2089 i915_gem_object_wait_rendering(struct drm_gem_object *obj,
2090                                bool interruptible)
2091 {
2092         struct drm_device *dev = obj->dev;
2093         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2094         int ret;
2095
2096         /* This function only exists to support waiting for existing rendering,
2097          * not for emitting required flushes.
2098          */
2099         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
2100
2101         /* If there is rendering queued on the buffer being evicted, wait for
2102          * it.
2103          */
2104         if (obj_priv->active) {
2105                 ret = i915_do_wait_request(dev,
2106                                            obj_priv->last_rendering_seqno,
2107                                            interruptible,
2108                                            obj_priv->ring);
2109                 if (ret)
2110                         return ret;
2111         }
2112
2113         return 0;
2114 }
2115
2116 /**
2117  * Unbinds an object from the GTT aperture.
2118  */
2119 int
2120 i915_gem_object_unbind(struct drm_gem_object *obj)
2121 {
2122         struct drm_device *dev = obj->dev;
2123         struct drm_i915_private *dev_priv = dev->dev_private;
2124         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2125         int ret = 0;
2126
2127         if (obj_priv->gtt_space == NULL)
2128                 return 0;
2129
2130         if (obj_priv->pin_count != 0) {
2131                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2132                 return -EINVAL;
2133         }
2134
2135         /* blow away mappings if mapped through GTT */
2136         i915_gem_release_mmap(obj);
2137
2138         /* Move the object to the CPU domain to ensure that
2139          * any possible CPU writes while it's not in the GTT
2140          * are flushed when we go to remap it. This will
2141          * also ensure that all pending GPU writes are finished
2142          * before we unbind.
2143          */
2144         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2145         if (ret == -ERESTARTSYS)
2146                 return ret;
2147         /* Continue on if we fail due to EIO, the GPU is hung so we
2148          * should be safe and we need to cleanup or else we might
2149          * cause memory corruption through use-after-free.
2150          */
2151         if (ret) {
2152                 i915_gem_clflush_object(obj);
2153                 obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU;
2154         }
2155
2156         /* release the fence reg _after_ flushing */
2157         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2158                 i915_gem_clear_fence_reg(obj);
2159
2160         drm_unbind_agp(obj_priv->agp_mem);
2161         drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2162
2163         i915_gem_object_put_pages(obj);
2164         BUG_ON(obj_priv->pages_refcount);
2165
2166         i915_gem_info_remove_gtt(dev_priv, obj->size);
2167         list_del_init(&obj_priv->list);
2168
2169         drm_mm_put_block(obj_priv->gtt_space);
2170         obj_priv->gtt_space = NULL;
2171
2172         if (i915_gem_object_is_purgeable(obj_priv))
2173                 i915_gem_object_truncate(obj);
2174
2175         trace_i915_gem_object_unbind(obj);
2176
2177         return ret;
2178 }
2179
2180 static int i915_ring_idle(struct drm_device *dev,
2181                           struct intel_ring_buffer *ring)
2182 {
2183         i915_gem_flush_ring(dev, NULL, ring,
2184                             I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2185         return i915_wait_request(dev,
2186                                  i915_gem_next_request_seqno(dev, ring),
2187                                  ring);
2188 }
2189
2190 int
2191 i915_gpu_idle(struct drm_device *dev)
2192 {
2193         drm_i915_private_t *dev_priv = dev->dev_private;
2194         bool lists_empty;
2195         int ret;
2196
2197         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2198                        list_empty(&dev_priv->render_ring.active_list) &&
2199                        (!HAS_BSD(dev) ||
2200                         list_empty(&dev_priv->bsd_ring.active_list)));
2201         if (lists_empty)
2202                 return 0;
2203
2204         /* Flush everything onto the inactive list. */
2205         ret = i915_ring_idle(dev, &dev_priv->render_ring);
2206         if (ret)
2207                 return ret;
2208
2209         if (HAS_BSD(dev)) {
2210                 ret = i915_ring_idle(dev, &dev_priv->bsd_ring);
2211                 if (ret)
2212                         return ret;
2213         }
2214
2215         return 0;
2216 }
2217
2218 static int
2219 i915_gem_object_get_pages(struct drm_gem_object *obj,
2220                           gfp_t gfpmask)
2221 {
2222         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2223         int page_count, i;
2224         struct address_space *mapping;
2225         struct inode *inode;
2226         struct page *page;
2227
2228         BUG_ON(obj_priv->pages_refcount
2229                         == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2230
2231         if (obj_priv->pages_refcount++ != 0)
2232                 return 0;
2233
2234         /* Get the list of pages out of our struct file.  They'll be pinned
2235          * at this point until we release them.
2236          */
2237         page_count = obj->size / PAGE_SIZE;
2238         BUG_ON(obj_priv->pages != NULL);
2239         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2240         if (obj_priv->pages == NULL) {
2241                 obj_priv->pages_refcount--;
2242                 return -ENOMEM;
2243         }
2244
2245         inode = obj->filp->f_path.dentry->d_inode;
2246         mapping = inode->i_mapping;
2247         for (i = 0; i < page_count; i++) {
2248                 page = read_cache_page_gfp(mapping, i,
2249                                            GFP_HIGHUSER |
2250                                            __GFP_COLD |
2251                                            __GFP_RECLAIMABLE |
2252                                            gfpmask);
2253                 if (IS_ERR(page))
2254                         goto err_pages;
2255
2256                 obj_priv->pages[i] = page;
2257         }
2258
2259         if (obj_priv->tiling_mode != I915_TILING_NONE)
2260                 i915_gem_object_do_bit_17_swizzle(obj);
2261
2262         return 0;
2263
2264 err_pages:
2265         while (i--)
2266                 page_cache_release(obj_priv->pages[i]);
2267
2268         drm_free_large(obj_priv->pages);
2269         obj_priv->pages = NULL;
2270         obj_priv->pages_refcount--;
2271         return PTR_ERR(page);
2272 }
2273
2274 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2275 {
2276         struct drm_gem_object *obj = reg->obj;
2277         struct drm_device *dev = obj->dev;
2278         drm_i915_private_t *dev_priv = dev->dev_private;
2279         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2280         int regnum = obj_priv->fence_reg;
2281         uint64_t val;
2282
2283         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2284                     0xfffff000) << 32;
2285         val |= obj_priv->gtt_offset & 0xfffff000;
2286         val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2287                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2288
2289         if (obj_priv->tiling_mode == I915_TILING_Y)
2290                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2291         val |= I965_FENCE_REG_VALID;
2292
2293         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2294 }
2295
2296 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2297 {
2298         struct drm_gem_object *obj = reg->obj;
2299         struct drm_device *dev = obj->dev;
2300         drm_i915_private_t *dev_priv = dev->dev_private;
2301         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2302         int regnum = obj_priv->fence_reg;
2303         uint64_t val;
2304
2305         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2306                     0xfffff000) << 32;
2307         val |= obj_priv->gtt_offset & 0xfffff000;
2308         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2309         if (obj_priv->tiling_mode == I915_TILING_Y)
2310                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2311         val |= I965_FENCE_REG_VALID;
2312
2313         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2314 }
2315
2316 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2317 {
2318         struct drm_gem_object *obj = reg->obj;
2319         struct drm_device *dev = obj->dev;
2320         drm_i915_private_t *dev_priv = dev->dev_private;
2321         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2322         int regnum = obj_priv->fence_reg;
2323         int tile_width;
2324         uint32_t fence_reg, val;
2325         uint32_t pitch_val;
2326
2327         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2328             (obj_priv->gtt_offset & (obj->size - 1))) {
2329                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2330                      __func__, obj_priv->gtt_offset, obj->size);
2331                 return;
2332         }
2333
2334         if (obj_priv->tiling_mode == I915_TILING_Y &&
2335             HAS_128_BYTE_Y_TILING(dev))
2336                 tile_width = 128;
2337         else
2338                 tile_width = 512;
2339
2340         /* Note: pitch better be a power of two tile widths */
2341         pitch_val = obj_priv->stride / tile_width;
2342         pitch_val = ffs(pitch_val) - 1;
2343
2344         if (obj_priv->tiling_mode == I915_TILING_Y &&
2345             HAS_128_BYTE_Y_TILING(dev))
2346                 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2347         else
2348                 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2349
2350         val = obj_priv->gtt_offset;
2351         if (obj_priv->tiling_mode == I915_TILING_Y)
2352                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2353         val |= I915_FENCE_SIZE_BITS(obj->size);
2354         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2355         val |= I830_FENCE_REG_VALID;
2356
2357         if (regnum < 8)
2358                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2359         else
2360                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2361         I915_WRITE(fence_reg, val);
2362 }
2363
2364 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2365 {
2366         struct drm_gem_object *obj = reg->obj;
2367         struct drm_device *dev = obj->dev;
2368         drm_i915_private_t *dev_priv = dev->dev_private;
2369         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2370         int regnum = obj_priv->fence_reg;
2371         uint32_t val;
2372         uint32_t pitch_val;
2373         uint32_t fence_size_bits;
2374
2375         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2376             (obj_priv->gtt_offset & (obj->size - 1))) {
2377                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2378                      __func__, obj_priv->gtt_offset);
2379                 return;
2380         }
2381
2382         pitch_val = obj_priv->stride / 128;
2383         pitch_val = ffs(pitch_val) - 1;
2384         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2385
2386         val = obj_priv->gtt_offset;
2387         if (obj_priv->tiling_mode == I915_TILING_Y)
2388                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2389         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2390         WARN_ON(fence_size_bits & ~0x00000f00);
2391         val |= fence_size_bits;
2392         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2393         val |= I830_FENCE_REG_VALID;
2394
2395         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2396 }
2397
2398 static int i915_find_fence_reg(struct drm_device *dev,
2399                                bool interruptible)
2400 {
2401         struct drm_i915_fence_reg *reg = NULL;
2402         struct drm_i915_gem_object *obj_priv = NULL;
2403         struct drm_i915_private *dev_priv = dev->dev_private;
2404         struct drm_gem_object *obj = NULL;
2405         int i, avail, ret;
2406
2407         /* First try to find a free reg */
2408         avail = 0;
2409         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2410                 reg = &dev_priv->fence_regs[i];
2411                 if (!reg->obj)
2412                         return i;
2413
2414                 obj_priv = to_intel_bo(reg->obj);
2415                 if (!obj_priv->pin_count)
2416                     avail++;
2417         }
2418
2419         if (avail == 0)
2420                 return -ENOSPC;
2421
2422         /* None available, try to steal one or wait for a user to finish */
2423         i = I915_FENCE_REG_NONE;
2424         list_for_each_entry(reg, &dev_priv->mm.fence_list,
2425                             lru_list) {
2426                 obj = reg->obj;
2427                 obj_priv = to_intel_bo(obj);
2428
2429                 if (obj_priv->pin_count)
2430                         continue;
2431
2432                 /* found one! */
2433                 i = obj_priv->fence_reg;
2434                 break;
2435         }
2436
2437         BUG_ON(i == I915_FENCE_REG_NONE);
2438
2439         /* We only have a reference on obj from the active list. put_fence_reg
2440          * might drop that one, causing a use-after-free in it. So hold a
2441          * private reference to obj like the other callers of put_fence_reg
2442          * (set_tiling ioctl) do. */
2443         drm_gem_object_reference(obj);
2444         ret = i915_gem_object_put_fence_reg(obj, interruptible);
2445         drm_gem_object_unreference(obj);
2446         if (ret != 0)
2447                 return ret;
2448
2449         return i;
2450 }
2451
2452 /**
2453  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2454  * @obj: object to map through a fence reg
2455  *
2456  * When mapping objects through the GTT, userspace wants to be able to write
2457  * to them without having to worry about swizzling if the object is tiled.
2458  *
2459  * This function walks the fence regs looking for a free one for @obj,
2460  * stealing one if it can't find any.
2461  *
2462  * It then sets up the reg based on the object's properties: address, pitch
2463  * and tiling format.
2464  */
2465 int
2466 i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
2467                               bool interruptible)
2468 {
2469         struct drm_device *dev = obj->dev;
2470         struct drm_i915_private *dev_priv = dev->dev_private;
2471         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2472         struct drm_i915_fence_reg *reg = NULL;
2473         int ret;
2474
2475         /* Just update our place in the LRU if our fence is getting used. */
2476         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2477                 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2478                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2479                 return 0;
2480         }
2481
2482         switch (obj_priv->tiling_mode) {
2483         case I915_TILING_NONE:
2484                 WARN(1, "allocating a fence for non-tiled object?\n");
2485                 break;
2486         case I915_TILING_X:
2487                 if (!obj_priv->stride)
2488                         return -EINVAL;
2489                 WARN((obj_priv->stride & (512 - 1)),
2490                      "object 0x%08x is X tiled but has non-512B pitch\n",
2491                      obj_priv->gtt_offset);
2492                 break;
2493         case I915_TILING_Y:
2494                 if (!obj_priv->stride)
2495                         return -EINVAL;
2496                 WARN((obj_priv->stride & (128 - 1)),
2497                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2498                      obj_priv->gtt_offset);
2499                 break;
2500         }
2501
2502         ret = i915_find_fence_reg(dev, interruptible);
2503         if (ret < 0)
2504                 return ret;
2505
2506         obj_priv->fence_reg = ret;
2507         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2508         list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2509
2510         reg->obj = obj;
2511
2512         switch (INTEL_INFO(dev)->gen) {
2513         case 6:
2514                 sandybridge_write_fence_reg(reg);
2515                 break;
2516         case 5:
2517         case 4:
2518                 i965_write_fence_reg(reg);
2519                 break;
2520         case 3:
2521                 i915_write_fence_reg(reg);
2522                 break;
2523         case 2:
2524                 i830_write_fence_reg(reg);
2525                 break;
2526         }
2527
2528         trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2529                         obj_priv->tiling_mode);
2530
2531         return 0;
2532 }
2533
2534 /**
2535  * i915_gem_clear_fence_reg - clear out fence register info
2536  * @obj: object to clear
2537  *
2538  * Zeroes out the fence register itself and clears out the associated
2539  * data structures in dev_priv and obj_priv.
2540  */
2541 static void
2542 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2543 {
2544         struct drm_device *dev = obj->dev;
2545         drm_i915_private_t *dev_priv = dev->dev_private;
2546         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2547         struct drm_i915_fence_reg *reg =
2548                 &dev_priv->fence_regs[obj_priv->fence_reg];
2549         uint32_t fence_reg;
2550
2551         switch (INTEL_INFO(dev)->gen) {
2552         case 6:
2553                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2554                              (obj_priv->fence_reg * 8), 0);
2555                 break;
2556         case 5:
2557         case 4:
2558                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2559                 break;
2560         case 3:
2561                 if (obj_priv->fence_reg >= 8)
2562                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
2563                 else
2564         case 2:
2565                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2566
2567                 I915_WRITE(fence_reg, 0);
2568                 break;
2569         }
2570
2571         reg->obj = NULL;
2572         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2573         list_del_init(&reg->lru_list);
2574 }
2575
2576 /**
2577  * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2578  * to the buffer to finish, and then resets the fence register.
2579  * @obj: tiled object holding a fence register.
2580  * @bool: whether the wait upon the fence is interruptible
2581  *
2582  * Zeroes out the fence register itself and clears out the associated
2583  * data structures in dev_priv and obj_priv.
2584  */
2585 int
2586 i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
2587                               bool interruptible)
2588 {
2589         struct drm_device *dev = obj->dev;
2590         struct drm_i915_private *dev_priv = dev->dev_private;
2591         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2592         struct drm_i915_fence_reg *reg;
2593
2594         if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2595                 return 0;
2596
2597         /* If we've changed tiling, GTT-mappings of the object
2598          * need to re-fault to ensure that the correct fence register
2599          * setup is in place.
2600          */
2601         i915_gem_release_mmap(obj);
2602
2603         /* On the i915, GPU access to tiled buffers is via a fence,
2604          * therefore we must wait for any outstanding access to complete
2605          * before clearing the fence.
2606          */
2607         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2608         if (reg->gpu) {
2609                 int ret;
2610
2611                 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2612                 if (ret)
2613                         return ret;
2614
2615                 ret = i915_gem_object_wait_rendering(obj, interruptible);
2616                 if (ret)
2617                         return ret;
2618
2619                 reg->gpu = false;
2620         }
2621
2622         i915_gem_object_flush_gtt_write_domain(obj);
2623         i915_gem_clear_fence_reg(obj);
2624
2625         return 0;
2626 }
2627
2628 /**
2629  * Finds free space in the GTT aperture and binds the object there.
2630  */
2631 static int
2632 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2633 {
2634         struct drm_device *dev = obj->dev;
2635         drm_i915_private_t *dev_priv = dev->dev_private;
2636         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2637         struct drm_mm_node *free_space;
2638         gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
2639         int ret;
2640
2641         if (obj_priv->madv != I915_MADV_WILLNEED) {
2642                 DRM_ERROR("Attempting to bind a purgeable object\n");
2643                 return -EINVAL;
2644         }
2645
2646         if (alignment == 0)
2647                 alignment = i915_gem_get_gtt_alignment(obj);
2648         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2649                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2650                 return -EINVAL;
2651         }
2652
2653         /* If the object is bigger than the entire aperture, reject it early
2654          * before evicting everything in a vain attempt to find space.
2655          */
2656         if (obj->size > dev_priv->mm.gtt_total) {
2657                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2658                 return -E2BIG;
2659         }
2660
2661  search_free:
2662         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2663                                         obj->size, alignment, 0);
2664         if (free_space != NULL) {
2665                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2666                                                        alignment);
2667                 if (obj_priv->gtt_space != NULL)
2668                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2669         }
2670         if (obj_priv->gtt_space == NULL) {
2671                 /* If the gtt is empty and we're still having trouble
2672                  * fitting our object in, we're out of memory.
2673                  */
2674                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2675                 if (ret)
2676                         return ret;
2677
2678                 goto search_free;
2679         }
2680
2681         ret = i915_gem_object_get_pages(obj, gfpmask);
2682         if (ret) {
2683                 drm_mm_put_block(obj_priv->gtt_space);
2684                 obj_priv->gtt_space = NULL;
2685
2686                 if (ret == -ENOMEM) {
2687                         /* first try to clear up some space from the GTT */
2688                         ret = i915_gem_evict_something(dev, obj->size,
2689                                                        alignment);
2690                         if (ret) {
2691                                 /* now try to shrink everyone else */
2692                                 if (gfpmask) {
2693                                         gfpmask = 0;
2694                                         goto search_free;
2695                                 }
2696
2697                                 return ret;
2698                         }
2699
2700                         goto search_free;
2701                 }
2702
2703                 return ret;
2704         }
2705
2706         /* Create an AGP memory structure pointing at our pages, and bind it
2707          * into the GTT.
2708          */
2709         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2710                                                obj_priv->pages,
2711                                                obj->size >> PAGE_SHIFT,
2712                                                obj_priv->gtt_offset,
2713                                                obj_priv->agp_type);
2714         if (obj_priv->agp_mem == NULL) {
2715                 i915_gem_object_put_pages(obj);
2716                 drm_mm_put_block(obj_priv->gtt_space);
2717                 obj_priv->gtt_space = NULL;
2718
2719                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2720                 if (ret)
2721                         return ret;
2722
2723                 goto search_free;
2724         }
2725
2726         /* keep track of bounds object by adding it to the inactive list */
2727         list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
2728         i915_gem_info_add_gtt(dev_priv, obj->size);
2729
2730         /* Assert that the object is not currently in any GPU domain. As it
2731          * wasn't in the GTT, there shouldn't be any way it could have been in
2732          * a GPU cache
2733          */
2734         BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2735         BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2736
2737         trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2738
2739         return 0;
2740 }
2741
2742 void
2743 i915_gem_clflush_object(struct drm_gem_object *obj)
2744 {
2745         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
2746
2747         /* If we don't have a page list set up, then we're not pinned
2748          * to GPU, and we can ignore the cache flush because it'll happen
2749          * again at bind time.
2750          */
2751         if (obj_priv->pages == NULL)
2752                 return;
2753
2754         trace_i915_gem_object_clflush(obj);
2755
2756         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2757 }
2758
2759 /** Flushes any GPU write domain for the object if it's dirty. */
2760 static int
2761 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
2762                                        bool pipelined)
2763 {
2764         struct drm_device *dev = obj->dev;
2765         uint32_t old_write_domain;
2766
2767         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2768                 return 0;
2769
2770         /* Queue the GPU write cache flushing we need. */
2771         old_write_domain = obj->write_domain;
2772         i915_gem_flush_ring(dev, NULL,
2773                             to_intel_bo(obj)->ring,
2774                             0, obj->write_domain);
2775         BUG_ON(obj->write_domain);
2776
2777         trace_i915_gem_object_change_domain(obj,
2778                                             obj->read_domains,
2779                                             old_write_domain);
2780
2781         if (pipelined)
2782                 return 0;
2783
2784         return i915_gem_object_wait_rendering(obj, true);
2785 }
2786
2787 /** Flushes the GTT write domain for the object if it's dirty. */
2788 static void
2789 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2790 {
2791         uint32_t old_write_domain;
2792
2793         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2794                 return;
2795
2796         /* No actual flushing is required for the GTT write domain.   Writes
2797          * to it immediately go to main memory as far as we know, so there's
2798          * no chipset flush.  It also doesn't land in render cache.
2799          */
2800         old_write_domain = obj->write_domain;
2801         obj->write_domain = 0;
2802
2803         trace_i915_gem_object_change_domain(obj,
2804                                             obj->read_domains,
2805                                             old_write_domain);
2806 }
2807
2808 /** Flushes the CPU write domain for the object if it's dirty. */
2809 static void
2810 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2811 {
2812         struct drm_device *dev = obj->dev;
2813         uint32_t old_write_domain;
2814
2815         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2816                 return;
2817
2818         i915_gem_clflush_object(obj);
2819         drm_agp_chipset_flush(dev);
2820         old_write_domain = obj->write_domain;
2821         obj->write_domain = 0;
2822
2823         trace_i915_gem_object_change_domain(obj,
2824                                             obj->read_domains,
2825                                             old_write_domain);
2826 }
2827
2828 /**
2829  * Moves a single object to the GTT read, and possibly write domain.
2830  *
2831  * This function returns when the move is complete, including waiting on
2832  * flushes to occur.
2833  */
2834 int
2835 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2836 {
2837         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2838         uint32_t old_write_domain, old_read_domains;
2839         int ret;
2840
2841         /* Not valid to be called on unbound objects. */
2842         if (obj_priv->gtt_space == NULL)
2843                 return -EINVAL;
2844
2845         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2846         if (ret != 0)
2847                 return ret;
2848
2849         i915_gem_object_flush_cpu_write_domain(obj);
2850
2851         if (write) {
2852                 ret = i915_gem_object_wait_rendering(obj, true);
2853                 if (ret)
2854                         return ret;
2855         }
2856
2857         old_write_domain = obj->write_domain;
2858         old_read_domains = obj->read_domains;
2859
2860         /* It should now be out of any other write domains, and we can update
2861          * the domain values for our changes.
2862          */
2863         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2864         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2865         if (write) {
2866                 obj->read_domains = I915_GEM_DOMAIN_GTT;
2867                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2868                 obj_priv->dirty = 1;
2869         }
2870
2871         trace_i915_gem_object_change_domain(obj,
2872                                             old_read_domains,
2873                                             old_write_domain);
2874
2875         return 0;
2876 }
2877
2878 /*
2879  * Prepare buffer for display plane. Use uninterruptible for possible flush
2880  * wait, as in modesetting process we're not supposed to be interrupted.
2881  */
2882 int
2883 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
2884                                      bool pipelined)
2885 {
2886         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2887         uint32_t old_read_domains;
2888         int ret;
2889
2890         /* Not valid to be called on unbound objects. */
2891         if (obj_priv->gtt_space == NULL)
2892                 return -EINVAL;
2893
2894         ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2895         if (ret)
2896                 return ret;
2897
2898         /* Currently, we are always called from an non-interruptible context. */
2899         if (!pipelined) {
2900                 ret = i915_gem_object_wait_rendering(obj, false);
2901                 if (ret)
2902                         return ret;
2903         }
2904
2905         i915_gem_object_flush_cpu_write_domain(obj);
2906
2907         old_read_domains = obj->read_domains;
2908         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2909
2910         trace_i915_gem_object_change_domain(obj,
2911                                             old_read_domains,
2912                                             obj->write_domain);
2913
2914         return 0;
2915 }
2916
2917 /**
2918  * Moves a single object to the CPU read, and possibly write domain.
2919  *
2920  * This function returns when the move is complete, including waiting on
2921  * flushes to occur.
2922  */
2923 static int
2924 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2925 {
2926         uint32_t old_write_domain, old_read_domains;
2927         int ret;
2928
2929         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2930         if (ret != 0)
2931                 return ret;
2932
2933         i915_gem_object_flush_gtt_write_domain(obj);
2934
2935         /* If we have a partially-valid cache of the object in the CPU,
2936          * finish invalidating it and free the per-page flags.
2937          */
2938         i915_gem_object_set_to_full_cpu_read_domain(obj);
2939
2940         if (write) {
2941                 ret = i915_gem_object_wait_rendering(obj, true);
2942                 if (ret)
2943                         return ret;
2944         }
2945
2946         old_write_domain = obj->write_domain;
2947         old_read_domains = obj->read_domains;
2948
2949         /* Flush the CPU cache if it's still invalid. */
2950         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2951                 i915_gem_clflush_object(obj);
2952
2953                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2954         }
2955
2956         /* It should now be out of any other write domains, and we can update
2957          * the domain values for our changes.
2958          */
2959         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2960
2961         /* If we're writing through the CPU, then the GPU read domains will
2962          * need to be invalidated at next use.
2963          */
2964         if (write) {
2965                 obj->read_domains = I915_GEM_DOMAIN_CPU;
2966                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2967         }
2968
2969         trace_i915_gem_object_change_domain(obj,
2970                                             old_read_domains,
2971                                             old_write_domain);
2972
2973         return 0;
2974 }
2975
2976 /*
2977  * Set the next domain for the specified object. This
2978  * may not actually perform the necessary flushing/invaliding though,
2979  * as that may want to be batched with other set_domain operations
2980  *
2981  * This is (we hope) the only really tricky part of gem. The goal
2982  * is fairly simple -- track which caches hold bits of the object
2983  * and make sure they remain coherent. A few concrete examples may
2984  * help to explain how it works. For shorthand, we use the notation
2985  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2986  * a pair of read and write domain masks.
2987  *
2988  * Case 1: the batch buffer
2989  *
2990  *      1. Allocated
2991  *      2. Written by CPU
2992  *      3. Mapped to GTT
2993  *      4. Read by GPU
2994  *      5. Unmapped from GTT
2995  *      6. Freed
2996  *
2997  *      Let's take these a step at a time
2998  *
2999  *      1. Allocated
3000  *              Pages allocated from the kernel may still have
3001  *              cache contents, so we set them to (CPU, CPU) always.
3002  *      2. Written by CPU (using pwrite)
3003  *              The pwrite function calls set_domain (CPU, CPU) and
3004  *              this function does nothing (as nothing changes)
3005  *      3. Mapped by GTT
3006  *              This function asserts that the object is not
3007  *              currently in any GPU-based read or write domains
3008  *      4. Read by GPU
3009  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
3010  *              As write_domain is zero, this function adds in the
3011  *              current read domains (CPU+COMMAND, 0).
3012  *              flush_domains is set to CPU.
3013  *              invalidate_domains is set to COMMAND
3014  *              clflush is run to get data out of the CPU caches
3015  *              then i915_dev_set_domain calls i915_gem_flush to
3016  *              emit an MI_FLUSH and drm_agp_chipset_flush
3017  *      5. Unmapped from GTT
3018  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
3019  *              flush_domains and invalidate_domains end up both zero
3020  *              so no flushing/invalidating happens
3021  *      6. Freed
3022  *              yay, done
3023  *
3024  * Case 2: The shared render buffer
3025  *
3026  *      1. Allocated
3027  *      2. Mapped to GTT
3028  *      3. Read/written by GPU
3029  *      4. set_domain to (CPU,CPU)
3030  *      5. Read/written by CPU
3031  *      6. Read/written by GPU
3032  *
3033  *      1. Allocated
3034  *              Same as last example, (CPU, CPU)
3035  *      2. Mapped to GTT
3036  *              Nothing changes (assertions find that it is not in the GPU)
3037  *      3. Read/written by GPU
3038  *              execbuffer calls set_domain (RENDER, RENDER)
3039  *              flush_domains gets CPU
3040  *              invalidate_domains gets GPU
3041  *              clflush (obj)
3042  *              MI_FLUSH and drm_agp_chipset_flush
3043  *      4. set_domain (CPU, CPU)
3044  *              flush_domains gets GPU
3045  *              invalidate_domains gets CPU
3046  *              wait_rendering (obj) to make sure all drawing is complete.
3047  *              This will include an MI_FLUSH to get the data from GPU
3048  *              to memory
3049  *              clflush (obj) to invalidate the CPU cache
3050  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3051  *      5. Read/written by CPU
3052  *              cache lines are loaded and dirtied
3053  *      6. Read written by GPU
3054  *              Same as last GPU access
3055  *
3056  * Case 3: The constant buffer
3057  *
3058  *      1. Allocated
3059  *      2. Written by CPU
3060  *      3. Read by GPU
3061  *      4. Updated (written) by CPU again
3062  *      5. Read by GPU
3063  *
3064  *      1. Allocated
3065  *              (CPU, CPU)
3066  *      2. Written by CPU
3067  *              (CPU, CPU)
3068  *      3. Read by GPU
3069  *              (CPU+RENDER, 0)
3070  *              flush_domains = CPU
3071  *              invalidate_domains = RENDER
3072  *              clflush (obj)
3073  *              MI_FLUSH
3074  *              drm_agp_chipset_flush
3075  *      4. Updated (written) by CPU again
3076  *              (CPU, CPU)
3077  *              flush_domains = 0 (no previous write domain)
3078  *              invalidate_domains = 0 (no new read domains)
3079  *      5. Read by GPU
3080  *              (CPU+RENDER, 0)
3081  *              flush_domains = CPU
3082  *              invalidate_domains = RENDER
3083  *              clflush (obj)
3084  *              MI_FLUSH
3085  *              drm_agp_chipset_flush
3086  */
3087 static void
3088 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3089 {
3090         struct drm_device               *dev = obj->dev;
3091         struct drm_i915_private         *dev_priv = dev->dev_private;
3092         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
3093         uint32_t                        invalidate_domains = 0;
3094         uint32_t                        flush_domains = 0;
3095         uint32_t                        old_read_domains;
3096
3097         intel_mark_busy(dev, obj);
3098
3099         /*
3100          * If the object isn't moving to a new write domain,
3101          * let the object stay in multiple read domains
3102          */
3103         if (obj->pending_write_domain == 0)
3104                 obj->pending_read_domains |= obj->read_domains;
3105         else
3106                 obj_priv->dirty = 1;
3107
3108         /*
3109          * Flush the current write domain if
3110          * the new read domains don't match. Invalidate
3111          * any read domains which differ from the old
3112          * write domain
3113          */
3114         if (obj->write_domain &&
3115             obj->write_domain != obj->pending_read_domains) {
3116                 flush_domains |= obj->write_domain;
3117                 invalidate_domains |=
3118                         obj->pending_read_domains & ~obj->write_domain;
3119         }
3120         /*
3121          * Invalidate any read caches which may have
3122          * stale data. That is, any new read domains.
3123          */
3124         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3125         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
3126                 i915_gem_clflush_object(obj);
3127
3128         old_read_domains = obj->read_domains;
3129
3130         /* The actual obj->write_domain will be updated with
3131          * pending_write_domain after we emit the accumulated flush for all
3132          * of our domain changes in execbuffers (which clears objects'
3133          * write_domains).  So if we have a current write domain that we
3134          * aren't changing, set pending_write_domain to that.
3135          */
3136         if (flush_domains == 0 && obj->pending_write_domain == 0)
3137                 obj->pending_write_domain = obj->write_domain;
3138         obj->read_domains = obj->pending_read_domains;
3139
3140         dev->invalidate_domains |= invalidate_domains;
3141         dev->flush_domains |= flush_domains;
3142         if (obj_priv->ring)
3143                 dev_priv->mm.flush_rings |= obj_priv->ring->id;
3144
3145         trace_i915_gem_object_change_domain(obj,
3146                                             old_read_domains,
3147                                             obj->write_domain);
3148 }
3149
3150 /**
3151  * Moves the object from a partially CPU read to a full one.
3152  *
3153  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3154  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3155  */
3156 static void
3157 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3158 {
3159         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3160
3161         if (!obj_priv->page_cpu_valid)
3162                 return;
3163
3164         /* If we're partially in the CPU read domain, finish moving it in.
3165          */
3166         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3167                 int i;
3168
3169                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3170                         if (obj_priv->page_cpu_valid[i])
3171                                 continue;
3172                         drm_clflush_pages(obj_priv->pages + i, 1);
3173                 }
3174         }
3175
3176         /* Free the page_cpu_valid mappings which are now stale, whether
3177          * or not we've got I915_GEM_DOMAIN_CPU.
3178          */
3179         kfree(obj_priv->page_cpu_valid);
3180         obj_priv->page_cpu_valid = NULL;
3181 }
3182
3183 /**
3184  * Set the CPU read domain on a range of the object.
3185  *
3186  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3187  * not entirely valid.  The page_cpu_valid member of the object flags which
3188  * pages have been flushed, and will be respected by
3189  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3190  * of the whole object.
3191  *
3192  * This function returns when the move is complete, including waiting on
3193  * flushes to occur.
3194  */
3195 static int
3196 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3197                                           uint64_t offset, uint64_t size)
3198 {
3199         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3200         uint32_t old_read_domains;
3201         int i, ret;
3202
3203         if (offset == 0 && size == obj->size)
3204                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3205
3206         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
3207         if (ret != 0)
3208                 return ret;
3209         i915_gem_object_flush_gtt_write_domain(obj);
3210
3211         /* If we're already fully in the CPU read domain, we're done. */
3212         if (obj_priv->page_cpu_valid == NULL &&
3213             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3214                 return 0;
3215
3216         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3217          * newly adding I915_GEM_DOMAIN_CPU
3218          */
3219         if (obj_priv->page_cpu_valid == NULL) {
3220                 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3221                                                    GFP_KERNEL);
3222                 if (obj_priv->page_cpu_valid == NULL)
3223                         return -ENOMEM;
3224         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3225                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3226
3227         /* Flush the cache on any pages that are still invalid from the CPU's
3228          * perspective.
3229          */
3230         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3231              i++) {
3232                 if (obj_priv->page_cpu_valid[i])
3233                         continue;
3234
3235                 drm_clflush_pages(obj_priv->pages + i, 1);
3236
3237                 obj_priv->page_cpu_valid[i] = 1;
3238         }
3239
3240         /* It should now be out of any other write domains, and we can update
3241          * the domain values for our changes.
3242          */
3243         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3244
3245         old_read_domains = obj->read_domains;
3246         obj->read_domains |= I915_GEM_DOMAIN_CPU;
3247
3248         trace_i915_gem_object_change_domain(obj,
3249                                             old_read_domains,
3250                                             obj->write_domain);
3251
3252         return 0;
3253 }
3254
3255 /**
3256  * Pin an object to the GTT and evaluate the relocations landing in it.
3257  */
3258 static int
3259 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3260                                  struct drm_file *file_priv,
3261                                  struct drm_i915_gem_exec_object2 *entry)
3262 {
3263         struct drm_device *dev = obj->dev;
3264         drm_i915_private_t *dev_priv = dev->dev_private;
3265         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3266         struct drm_i915_gem_relocation_entry __user *user_relocs;
3267         int i, ret;
3268         bool need_fence;
3269
3270         need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3271                      obj_priv->tiling_mode != I915_TILING_NONE;
3272
3273         /* Check fence reg constraints and rebind if necessary */
3274         if (need_fence &&
3275             !i915_gem_object_fence_offset_ok(obj,
3276                                              obj_priv->tiling_mode)) {
3277                 ret = i915_gem_object_unbind(obj);
3278                 if (ret)
3279                         return ret;
3280         }
3281
3282         /* Choose the GTT offset for our buffer and put it there. */
3283         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3284         if (ret)
3285                 return ret;
3286
3287         /*
3288          * Pre-965 chips need a fence register set up in order to
3289          * properly handle blits to/from tiled surfaces.
3290          */
3291         if (need_fence) {
3292                 ret = i915_gem_object_get_fence_reg(obj, true);
3293                 if (ret != 0) {
3294                         i915_gem_object_unpin(obj);
3295                         return ret;
3296                 }
3297
3298                 dev_priv->fence_regs[obj_priv->fence_reg].gpu = true;
3299         }
3300
3301         entry->offset = obj_priv->gtt_offset;
3302
3303         /* Apply the relocations, using the GTT aperture to avoid cache
3304          * flushing requirements.
3305          */
3306         user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
3307         for (i = 0; i < entry->relocation_count; i++) {
3308                 struct drm_i915_gem_relocation_entry reloc;
3309                 struct drm_gem_object *target_obj;
3310                 struct drm_i915_gem_object *target_obj_priv;
3311
3312                 ret = __copy_from_user_inatomic(&reloc,
3313                                                 user_relocs+i,
3314                                                 sizeof(reloc));
3315                 if (ret) {
3316                         i915_gem_object_unpin(obj);
3317                         return -EFAULT;
3318                 }
3319
3320                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3321                                                    reloc.target_handle);
3322                 if (target_obj == NULL) {
3323                         i915_gem_object_unpin(obj);
3324                         return -ENOENT;
3325                 }
3326                 target_obj_priv = to_intel_bo(target_obj);
3327
3328 #if WATCH_RELOC
3329                 DRM_INFO("%s: obj %p offset %08x target %d "
3330                          "read %08x write %08x gtt %08x "
3331                          "presumed %08x delta %08x\n",
3332                          __func__,
3333                          obj,
3334                          (int) reloc.offset,
3335                          (int) reloc.target_handle,
3336                          (int) reloc.read_domains,
3337                          (int) reloc.write_domain,
3338                          (int) target_obj_priv->gtt_offset,
3339                          (int) reloc.presumed_offset,
3340                          reloc.delta);
3341 #endif
3342
3343                 /* The target buffer should have appeared before us in the
3344                  * exec_object list, so it should have a GTT space bound by now.
3345                  */
3346                 if (target_obj_priv->gtt_space == NULL) {
3347                         DRM_ERROR("No GTT space found for object %d\n",
3348                                   reloc.target_handle);
3349                         drm_gem_object_unreference(target_obj);
3350                         i915_gem_object_unpin(obj);
3351                         return -EINVAL;
3352                 }
3353
3354                 /* Validate that the target is in a valid r/w GPU domain */
3355                 if (reloc.write_domain & (reloc.write_domain - 1)) {
3356                         DRM_ERROR("reloc with multiple write domains: "
3357                                   "obj %p target %d offset %d "
3358                                   "read %08x write %08x",
3359                                   obj, reloc.target_handle,
3360                                   (int) reloc.offset,
3361                                   reloc.read_domains,
3362                                   reloc.write_domain);
3363                         drm_gem_object_unreference(target_obj);
3364                         i915_gem_object_unpin(obj);
3365                         return -EINVAL;
3366                 }
3367                 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
3368                     reloc.read_domains & I915_GEM_DOMAIN_CPU) {
3369                         DRM_ERROR("reloc with read/write CPU domains: "
3370                                   "obj %p target %d offset %d "
3371                                   "read %08x write %08x",
3372                                   obj, reloc.target_handle,
3373                                   (int) reloc.offset,
3374                                   reloc.read_domains,
3375                                   reloc.write_domain);
3376                         drm_gem_object_unreference(target_obj);
3377                         i915_gem_object_unpin(obj);
3378                         return -EINVAL;
3379                 }
3380                 if (reloc.write_domain && target_obj->pending_write_domain &&
3381                     reloc.write_domain != target_obj->pending_write_domain) {
3382                         DRM_ERROR("Write domain conflict: "
3383                                   "obj %p target %d offset %d "
3384                                   "new %08x old %08x\n",
3385                                   obj, reloc.target_handle,
3386                                   (int) reloc.offset,
3387                                   reloc.write_domain,
3388                                   target_obj->pending_write_domain);
3389                         drm_gem_object_unreference(target_obj);
3390                         i915_gem_object_unpin(obj);
3391                         return -EINVAL;
3392                 }
3393
3394                 target_obj->pending_read_domains |= reloc.read_domains;
3395                 target_obj->pending_write_domain |= reloc.write_domain;
3396
3397                 /* If the relocation already has the right value in it, no
3398                  * more work needs to be done.
3399                  */
3400                 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
3401                         drm_gem_object_unreference(target_obj);
3402                         continue;
3403                 }
3404
3405                 /* Check that the relocation address is valid... */
3406                 if (reloc.offset > obj->size - 4) {
3407                         DRM_ERROR("Relocation beyond object bounds: "
3408                                   "obj %p target %d offset %d size %d.\n",
3409                                   obj, reloc.target_handle,
3410                                   (int) reloc.offset, (int) obj->size);
3411                         drm_gem_object_unreference(target_obj);
3412                         i915_gem_object_unpin(obj);
3413                         return -EINVAL;
3414                 }
3415                 if (reloc.offset & 3) {
3416                         DRM_ERROR("Relocation not 4-byte aligned: "
3417                                   "obj %p target %d offset %d.\n",
3418                                   obj, reloc.target_handle,
3419                                   (int) reloc.offset);
3420                         drm_gem_object_unreference(target_obj);
3421                         i915_gem_object_unpin(obj);
3422                         return -EINVAL;
3423                 }
3424
3425                 /* and points to somewhere within the target object. */
3426                 if (reloc.delta >= target_obj->size) {
3427                         DRM_ERROR("Relocation beyond target object bounds: "
3428                                   "obj %p target %d delta %d size %d.\n",
3429                                   obj, reloc.target_handle,
3430                                   (int) reloc.delta, (int) target_obj->size);
3431                         drm_gem_object_unreference(target_obj);
3432                         i915_gem_object_unpin(obj);
3433                         return -EINVAL;
3434                 }
3435
3436                 reloc.delta += target_obj_priv->gtt_offset;
3437                 if (obj->write_domain == I915_GEM_DOMAIN_CPU) {
3438                         uint32_t page_offset = reloc.offset & ~PAGE_MASK;
3439                         char *vaddr;
3440
3441                         vaddr = kmap_atomic(obj_priv->pages[reloc.offset >> PAGE_SHIFT], KM_USER0);
3442                         *(uint32_t *)(vaddr + page_offset) = reloc.delta;
3443                         kunmap_atomic(vaddr, KM_USER0);
3444                 } else {
3445                         uint32_t __iomem *reloc_entry;
3446                         void __iomem *reloc_page;
3447                         int ret;
3448
3449                         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3450                         if (ret) {
3451                                 drm_gem_object_unreference(target_obj);
3452                                 i915_gem_object_unpin(obj);
3453                                 return ret;
3454                         }
3455
3456                         /* Map the page containing the relocation we're going to perform.  */
3457                         reloc.offset += obj_priv->gtt_offset;
3458                         reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3459                                                               reloc.offset & PAGE_MASK,
3460                                                               KM_USER0);
3461                         reloc_entry = (uint32_t __iomem *)
3462                                 (reloc_page + (reloc.offset & ~PAGE_MASK));
3463                         iowrite32(reloc.delta, reloc_entry);
3464                         io_mapping_unmap_atomic(reloc_page, KM_USER0);
3465                 }
3466
3467                 drm_gem_object_unreference(target_obj);
3468         }
3469
3470         return 0;
3471 }
3472
3473 /* Throttle our rendering by waiting until the ring has completed our requests
3474  * emitted over 20 msec ago.
3475  *
3476  * Note that if we were to use the current jiffies each time around the loop,
3477  * we wouldn't escape the function with any frames outstanding if the time to
3478  * render a frame was over 20ms.
3479  *
3480  * This should get us reasonable parallelism between CPU and GPU but also
3481  * relatively low latency when blocking on a particular request to finish.
3482  */
3483 static int
3484 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3485 {
3486         struct drm_i915_private *dev_priv = dev->dev_private;
3487         struct drm_i915_file_private *file_priv = file->driver_priv;
3488         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3489         struct drm_i915_gem_request *request;
3490         struct intel_ring_buffer *ring = NULL;
3491         u32 seqno = 0;
3492         int ret;
3493
3494         spin_lock(&file_priv->mm.lock);
3495         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3496                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3497                         break;
3498
3499                 ring = request->ring;
3500                 seqno = request->seqno;
3501         }
3502         spin_unlock(&file_priv->mm.lock);
3503
3504         if (seqno == 0)
3505                 return 0;
3506
3507         ret = 0;
3508         if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) {
3509                 /* And wait for the seqno passing without holding any locks and
3510                  * causing extra latency for others. This is safe as the irq
3511                  * generation is designed to be run atomically and so is
3512                  * lockless.
3513                  */
3514                 ring->user_irq_get(dev, ring);
3515                 ret = wait_event_interruptible(ring->irq_queue,
3516                                                i915_seqno_passed(ring->get_seqno(dev, ring), seqno)
3517                                                || atomic_read(&dev_priv->mm.wedged));
3518                 ring->user_irq_put(dev, ring);
3519
3520                 if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3521                         ret = -EIO;
3522         }
3523
3524         if (ret == 0)
3525                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3526
3527         return ret;
3528 }
3529
3530 static int
3531 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec,
3532                           uint64_t exec_offset)
3533 {
3534         uint32_t exec_start, exec_len;
3535
3536         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3537         exec_len = (uint32_t) exec->batch_len;
3538
3539         if ((exec_start | exec_len) & 0x7)
3540                 return -EINVAL;
3541
3542         if (!exec_start)
3543                 return -EINVAL;
3544
3545         return 0;
3546 }
3547
3548 static int
3549 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
3550                    int count)
3551 {
3552         int i;
3553
3554         for (i = 0; i < count; i++) {
3555                 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
3556                 size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry);
3557
3558                 if (!access_ok(VERIFY_READ, ptr, length))
3559                         return -EFAULT;
3560
3561                 if (fault_in_pages_readable(ptr, length))
3562                         return -EFAULT;
3563         }
3564
3565         return 0;
3566 }
3567
3568 static int
3569 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3570                        struct drm_file *file_priv,
3571                        struct drm_i915_gem_execbuffer2 *args,
3572                        struct drm_i915_gem_exec_object2 *exec_list)
3573 {
3574         drm_i915_private_t *dev_priv = dev->dev_private;
3575         struct drm_gem_object **object_list = NULL;
3576         struct drm_gem_object *batch_obj;
3577         struct drm_i915_gem_object *obj_priv;
3578         struct drm_clip_rect *cliprects = NULL;
3579         struct drm_i915_gem_request *request = NULL;
3580         int ret, i, pinned = 0;
3581         uint64_t exec_offset;
3582         int pin_tries, flips;
3583
3584         struct intel_ring_buffer *ring = NULL;
3585
3586         ret = i915_gem_check_is_wedged(dev);
3587         if (ret)
3588                 return ret;
3589
3590         ret = validate_exec_list(exec_list, args->buffer_count);
3591         if (ret)
3592                 return ret;
3593
3594 #if WATCH_EXEC
3595         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3596                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3597 #endif
3598         if (args->flags & I915_EXEC_BSD) {
3599                 if (!HAS_BSD(dev)) {
3600                         DRM_ERROR("execbuf with wrong flag\n");
3601                         return -EINVAL;
3602                 }
3603                 ring = &dev_priv->bsd_ring;
3604         } else {
3605                 ring = &dev_priv->render_ring;
3606         }
3607
3608         if (args->buffer_count < 1) {
3609                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3610                 return -EINVAL;
3611         }
3612         object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3613         if (object_list == NULL) {
3614                 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3615                           args->buffer_count);
3616                 ret = -ENOMEM;
3617                 goto pre_mutex_err;
3618         }
3619
3620         if (args->num_cliprects != 0) {
3621                 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3622                                     GFP_KERNEL);
3623                 if (cliprects == NULL) {
3624                         ret = -ENOMEM;
3625                         goto pre_mutex_err;
3626                 }
3627
3628                 ret = copy_from_user(cliprects,
3629                                      (struct drm_clip_rect __user *)
3630                                      (uintptr_t) args->cliprects_ptr,
3631                                      sizeof(*cliprects) * args->num_cliprects);
3632                 if (ret != 0) {
3633                         DRM_ERROR("copy %d cliprects failed: %d\n",
3634                                   args->num_cliprects, ret);
3635                         ret = -EFAULT;
3636                         goto pre_mutex_err;
3637                 }
3638         }
3639
3640         request = kzalloc(sizeof(*request), GFP_KERNEL);
3641         if (request == NULL) {
3642                 ret = -ENOMEM;
3643                 goto pre_mutex_err;
3644         }
3645
3646         ret = i915_mutex_lock_interruptible(dev);
3647         if (ret)
3648                 goto pre_mutex_err;
3649
3650         if (dev_priv->mm.suspended) {
3651                 mutex_unlock(&dev->struct_mutex);
3652                 ret = -EBUSY;
3653                 goto pre_mutex_err;
3654         }
3655
3656         /* Look up object handles */
3657         for (i = 0; i < args->buffer_count; i++) {
3658                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3659                                                        exec_list[i].handle);
3660                 if (object_list[i] == NULL) {
3661                         DRM_ERROR("Invalid object handle %d at index %d\n",
3662                                    exec_list[i].handle, i);
3663                         /* prevent error path from reading uninitialized data */
3664                         args->buffer_count = i + 1;
3665                         ret = -ENOENT;
3666                         goto err;
3667                 }
3668
3669                 obj_priv = to_intel_bo(object_list[i]);
3670                 if (obj_priv->in_execbuffer) {
3671                         DRM_ERROR("Object %p appears more than once in object list\n",
3672                                    object_list[i]);
3673                         /* prevent error path from reading uninitialized data */
3674                         args->buffer_count = i + 1;
3675                         ret = -EINVAL;
3676                         goto err;
3677                 }
3678                 obj_priv->in_execbuffer = true;
3679         }
3680
3681         /* Pin and relocate */
3682         for (pin_tries = 0; ; pin_tries++) {
3683                 ret = 0;
3684
3685                 for (i = 0; i < args->buffer_count; i++) {
3686                         object_list[i]->pending_read_domains = 0;
3687                         object_list[i]->pending_write_domain = 0;
3688                         ret = i915_gem_object_pin_and_relocate(object_list[i],
3689                                                                file_priv,
3690                                                                &exec_list[i]);
3691                         if (ret)
3692                                 break;
3693                         pinned = i + 1;
3694                 }
3695                 /* success */
3696                 if (ret == 0)
3697                         break;
3698
3699                 /* error other than GTT full, or we've already tried again */
3700                 if (ret != -ENOSPC || pin_tries >= 1) {
3701                         if (ret != -ERESTARTSYS) {
3702                                 unsigned long long total_size = 0;
3703                                 int num_fences = 0;
3704                                 for (i = 0; i < args->buffer_count; i++) {
3705                                         obj_priv = to_intel_bo(object_list[i]);
3706
3707                                         total_size += object_list[i]->size;
3708                                         num_fences +=
3709                                                 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3710                                                 obj_priv->tiling_mode != I915_TILING_NONE;
3711                                 }
3712                                 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3713                                           pinned+1, args->buffer_count,
3714                                           total_size, num_fences,
3715                                           ret);
3716                                 DRM_ERROR("%u objects [%u pinned, %u GTT], "
3717                                           "%zu object bytes [%zu pinned], "
3718                                           "%zu /%zu gtt bytes\n",
3719                                           dev_priv->mm.object_count,
3720                                           dev_priv->mm.pin_count,
3721                                           dev_priv->mm.gtt_count,
3722                                           dev_priv->mm.object_memory,
3723                                           dev_priv->mm.pin_memory,
3724                                           dev_priv->mm.gtt_memory,
3725                                           dev_priv->mm.gtt_total);
3726                         }
3727                         goto err;
3728                 }
3729
3730                 /* unpin all of our buffers */
3731                 for (i = 0; i < pinned; i++)
3732                         i915_gem_object_unpin(object_list[i]);
3733                 pinned = 0;
3734
3735                 /* evict everyone we can from the aperture */
3736                 ret = i915_gem_evict_everything(dev);
3737                 if (ret && ret != -ENOSPC)
3738                         goto err;
3739         }
3740
3741         /* Set the pending read domains for the batch buffer to COMMAND */
3742         batch_obj = object_list[args->buffer_count-1];
3743         if (batch_obj->pending_write_domain) {
3744                 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3745                 ret = -EINVAL;
3746                 goto err;
3747         }
3748         batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3749
3750         /* Sanity check the batch buffer, prior to moving objects */
3751         exec_offset = exec_list[args->buffer_count - 1].offset;
3752         ret = i915_gem_check_execbuffer (args, exec_offset);
3753         if (ret != 0) {
3754                 DRM_ERROR("execbuf with invalid offset/length\n");
3755                 goto err;
3756         }
3757
3758         /* Zero the global flush/invalidate flags. These
3759          * will be modified as new domains are computed
3760          * for each object
3761          */
3762         dev->invalidate_domains = 0;
3763         dev->flush_domains = 0;
3764         dev_priv->mm.flush_rings = 0;
3765
3766         for (i = 0; i < args->buffer_count; i++) {
3767                 struct drm_gem_object *obj = object_list[i];
3768
3769                 /* Compute new gpu domains and update invalidate/flush */
3770                 i915_gem_object_set_to_gpu_domain(obj);
3771         }
3772
3773         if (dev->invalidate_domains | dev->flush_domains) {
3774 #if WATCH_EXEC
3775                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3776                           __func__,
3777                          dev->invalidate_domains,
3778                          dev->flush_domains);
3779 #endif
3780                 i915_gem_flush(dev, file_priv,
3781                                dev->invalidate_domains,
3782                                dev->flush_domains,
3783                                dev_priv->mm.flush_rings);
3784         }
3785
3786         for (i = 0; i < args->buffer_count; i++) {
3787                 struct drm_gem_object *obj = object_list[i];
3788                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3789                 uint32_t old_write_domain = obj->write_domain;
3790
3791                 obj->write_domain = obj->pending_write_domain;
3792                 if (obj->write_domain)
3793                         list_move_tail(&obj_priv->gpu_write_list,
3794                                        &dev_priv->mm.gpu_write_list);
3795
3796                 trace_i915_gem_object_change_domain(obj,
3797                                                     obj->read_domains,
3798                                                     old_write_domain);
3799         }
3800
3801 #if WATCH_COHERENCY
3802         for (i = 0; i < args->buffer_count; i++) {
3803                 i915_gem_object_check_coherency(object_list[i],
3804                                                 exec_list[i].handle);
3805         }
3806 #endif
3807
3808 #if WATCH_EXEC
3809         i915_gem_dump_object(batch_obj,
3810                               args->batch_len,
3811                               __func__,
3812                               ~0);
3813 #endif
3814
3815         /* Check for any pending flips. As we only maintain a flip queue depth
3816          * of 1, we can simply insert a WAIT for the next display flip prior
3817          * to executing the batch and avoid stalling the CPU.
3818          */
3819         flips = 0;
3820         for (i = 0; i < args->buffer_count; i++) {
3821                 if (object_list[i]->write_domain)
3822                         flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip);
3823         }
3824         if (flips) {
3825                 int plane, flip_mask;
3826
3827                 for (plane = 0; flips >> plane; plane++) {
3828                         if (((flips >> plane) & 1) == 0)
3829                                 continue;
3830
3831                         if (plane)
3832                                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
3833                         else
3834                                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
3835
3836                         intel_ring_begin(dev, ring, 2);
3837                         intel_ring_emit(dev, ring,
3838                                         MI_WAIT_FOR_EVENT | flip_mask);
3839                         intel_ring_emit(dev, ring, MI_NOOP);
3840                         intel_ring_advance(dev, ring);
3841                 }
3842         }
3843
3844         /* Exec the batchbuffer */
3845         ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3846                                             cliprects, exec_offset);
3847         if (ret) {
3848                 DRM_ERROR("dispatch failed %d\n", ret);
3849                 goto err;
3850         }
3851
3852         /*
3853          * Ensure that the commands in the batch buffer are
3854          * finished before the interrupt fires
3855          */
3856         i915_retire_commands(dev, ring);
3857
3858         for (i = 0; i < args->buffer_count; i++) {
3859                 struct drm_gem_object *obj = object_list[i];
3860                 obj_priv = to_intel_bo(obj);
3861
3862                 i915_gem_object_move_to_active(obj, ring);
3863         }
3864
3865         i915_add_request(dev, file_priv, request, ring);
3866         request = NULL;
3867
3868 err:
3869         for (i = 0; i < pinned; i++)
3870                 i915_gem_object_unpin(object_list[i]);
3871
3872         for (i = 0; i < args->buffer_count; i++) {
3873                 if (object_list[i]) {
3874                         obj_priv = to_intel_bo(object_list[i]);
3875                         obj_priv->in_execbuffer = false;
3876                 }
3877                 drm_gem_object_unreference(object_list[i]);
3878         }
3879
3880         mutex_unlock(&dev->struct_mutex);
3881
3882 pre_mutex_err:
3883         drm_free_large(object_list);
3884         kfree(cliprects);
3885         kfree(request);
3886
3887         return ret;
3888 }
3889
3890 /*
3891  * Legacy execbuffer just creates an exec2 list from the original exec object
3892  * list array and passes it to the real function.
3893  */
3894 int
3895 i915_gem_execbuffer(struct drm_device *dev, void *data,
3896                     struct drm_file *file_priv)
3897 {
3898         struct drm_i915_gem_execbuffer *args = data;
3899         struct drm_i915_gem_execbuffer2 exec2;
3900         struct drm_i915_gem_exec_object *exec_list = NULL;
3901         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3902         int ret, i;
3903
3904 #if WATCH_EXEC
3905         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3906                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3907 #endif
3908
3909         if (args->buffer_count < 1) {
3910                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3911                 return -EINVAL;
3912         }
3913
3914         /* Copy in the exec list from userland */
3915         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3916         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3917         if (exec_list == NULL || exec2_list == NULL) {
3918                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3919                           args->buffer_count);
3920                 drm_free_large(exec_list);
3921                 drm_free_large(exec2_list);
3922                 return -ENOMEM;
3923         }
3924         ret = copy_from_user(exec_list,
3925                              (struct drm_i915_relocation_entry __user *)
3926                              (uintptr_t) args->buffers_ptr,
3927                              sizeof(*exec_list) * args->buffer_count);
3928         if (ret != 0) {
3929                 DRM_ERROR("copy %d exec entries failed %d\n",
3930                           args->buffer_count, ret);
3931                 drm_free_large(exec_list);
3932                 drm_free_large(exec2_list);
3933                 return -EFAULT;
3934         }
3935
3936         for (i = 0; i < args->buffer_count; i++) {
3937                 exec2_list[i].handle = exec_list[i].handle;
3938                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3939                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3940                 exec2_list[i].alignment = exec_list[i].alignment;
3941                 exec2_list[i].offset = exec_list[i].offset;
3942                 if (INTEL_INFO(dev)->gen < 4)
3943                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3944                 else
3945                         exec2_list[i].flags = 0;
3946         }
3947
3948         exec2.buffers_ptr = args->buffers_ptr;
3949         exec2.buffer_count = args->buffer_count;
3950         exec2.batch_start_offset = args->batch_start_offset;
3951         exec2.batch_len = args->batch_len;
3952         exec2.DR1 = args->DR1;
3953         exec2.DR4 = args->DR4;
3954         exec2.num_cliprects = args->num_cliprects;
3955         exec2.cliprects_ptr = args->cliprects_ptr;
3956         exec2.flags = I915_EXEC_RENDER;
3957
3958         ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3959         if (!ret) {
3960                 /* Copy the new buffer offsets back to the user's exec list. */
3961                 for (i = 0; i < args->buffer_count; i++)
3962                         exec_list[i].offset = exec2_list[i].offset;
3963                 /* ... and back out to userspace */
3964                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3965                                    (uintptr_t) args->buffers_ptr,
3966                                    exec_list,
3967                                    sizeof(*exec_list) * args->buffer_count);
3968                 if (ret) {
3969                         ret = -EFAULT;
3970                         DRM_ERROR("failed to copy %d exec entries "
3971                                   "back to user (%d)\n",
3972                                   args->buffer_count, ret);
3973                 }
3974         }
3975
3976         drm_free_large(exec_list);
3977         drm_free_large(exec2_list);
3978         return ret;
3979 }
3980
3981 int
3982 i915_gem_execbuffer2(struct drm_device *dev, void *data,
3983                      struct drm_file *file_priv)
3984 {
3985         struct drm_i915_gem_execbuffer2 *args = data;
3986         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3987         int ret;
3988
3989 #if WATCH_EXEC
3990         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3991                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3992 #endif
3993
3994         if (args->buffer_count < 1) {
3995                 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
3996                 return -EINVAL;
3997         }
3998
3999         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4000         if (exec2_list == NULL) {
4001                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4002                           args->buffer_count);
4003                 return -ENOMEM;
4004         }
4005         ret = copy_from_user(exec2_list,
4006                              (struct drm_i915_relocation_entry __user *)
4007                              (uintptr_t) args->buffers_ptr,
4008                              sizeof(*exec2_list) * args->buffer_count);
4009         if (ret != 0) {
4010                 DRM_ERROR("copy %d exec entries failed %d\n",
4011                           args->buffer_count, ret);
4012                 drm_free_large(exec2_list);
4013                 return -EFAULT;
4014         }
4015
4016         ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4017         if (!ret) {
4018                 /* Copy the new buffer offsets back to the user's exec list. */
4019                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4020                                    (uintptr_t) args->buffers_ptr,
4021                                    exec2_list,
4022                                    sizeof(*exec2_list) * args->buffer_count);
4023                 if (ret) {
4024                         ret = -EFAULT;
4025                         DRM_ERROR("failed to copy %d exec entries "
4026                                   "back to user (%d)\n",
4027                                   args->buffer_count, ret);
4028                 }
4029         }
4030
4031         drm_free_large(exec2_list);
4032         return ret;
4033 }
4034
4035 int
4036 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4037 {
4038         struct drm_device *dev = obj->dev;
4039         struct drm_i915_private *dev_priv = dev->dev_private;
4040         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4041         int ret;
4042
4043         BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4044         WARN_ON(i915_verify_lists(dev));
4045
4046         if (obj_priv->gtt_space != NULL) {
4047                 if (alignment == 0)
4048                         alignment = i915_gem_get_gtt_alignment(obj);
4049                 if (obj_priv->gtt_offset & (alignment - 1)) {
4050                         WARN(obj_priv->pin_count,
4051                              "bo is already pinned with incorrect alignment:"
4052                              " offset=%x, req.alignment=%x\n",
4053                              obj_priv->gtt_offset, alignment);
4054                         ret = i915_gem_object_unbind(obj);
4055                         if (ret)
4056                                 return ret;
4057                 }
4058         }
4059
4060         if (obj_priv->gtt_space == NULL) {
4061                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4062                 if (ret)
4063                         return ret;
4064         }
4065
4066         obj_priv->pin_count++;
4067
4068         /* If the object is not active and not pending a flush,
4069          * remove it from the inactive list
4070          */
4071         if (obj_priv->pin_count == 1) {
4072                 i915_gem_info_add_pin(dev_priv, obj->size);
4073                 if (!obj_priv->active)
4074                         list_move_tail(&obj_priv->list,
4075                                        &dev_priv->mm.pinned_list);
4076         }
4077
4078         WARN_ON(i915_verify_lists(dev));
4079         return 0;
4080 }
4081
4082 void
4083 i915_gem_object_unpin(struct drm_gem_object *obj)
4084 {
4085         struct drm_device *dev = obj->dev;
4086         drm_i915_private_t *dev_priv = dev->dev_private;
4087         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4088
4089         WARN_ON(i915_verify_lists(dev));
4090         obj_priv->pin_count--;
4091         BUG_ON(obj_priv->pin_count < 0);
4092         BUG_ON(obj_priv->gtt_space == NULL);
4093
4094         /* If the object is no longer pinned, and is
4095          * neither active nor being flushed, then stick it on
4096          * the inactive list
4097          */
4098         if (obj_priv->pin_count == 0) {
4099                 if (!obj_priv->active)
4100                         list_move_tail(&obj_priv->list,
4101                                        &dev_priv->mm.inactive_list);
4102                 i915_gem_info_remove_pin(dev_priv, obj->size);
4103         }
4104         WARN_ON(i915_verify_lists(dev));
4105 }
4106
4107 int
4108 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4109                    struct drm_file *file_priv)
4110 {
4111         struct drm_i915_gem_pin *args = data;
4112         struct drm_gem_object *obj;
4113         struct drm_i915_gem_object *obj_priv;
4114         int ret;
4115
4116         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4117         if (obj == NULL) {
4118                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4119                           args->handle);
4120                 return -ENOENT;
4121         }
4122         obj_priv = to_intel_bo(obj);
4123
4124         ret = i915_mutex_lock_interruptible(dev);
4125         if (ret) {
4126                 drm_gem_object_unreference_unlocked(obj);
4127                 return ret;
4128         }
4129
4130         if (obj_priv->madv != I915_MADV_WILLNEED) {
4131                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4132                 drm_gem_object_unreference(obj);
4133                 mutex_unlock(&dev->struct_mutex);
4134                 return -EINVAL;
4135         }
4136
4137         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4138                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4139                           args->handle);
4140                 drm_gem_object_unreference(obj);
4141                 mutex_unlock(&dev->struct_mutex);
4142                 return -EINVAL;
4143         }
4144
4145         obj_priv->user_pin_count++;
4146         obj_priv->pin_filp = file_priv;
4147         if (obj_priv->user_pin_count == 1) {
4148                 ret = i915_gem_object_pin(obj, args->alignment);
4149                 if (ret != 0) {
4150                         drm_gem_object_unreference(obj);
4151                         mutex_unlock(&dev->struct_mutex);
4152                         return ret;
4153                 }
4154         }
4155
4156         /* XXX - flush the CPU caches for pinned objects
4157          * as the X server doesn't manage domains yet
4158          */
4159         i915_gem_object_flush_cpu_write_domain(obj);
4160         args->offset = obj_priv->gtt_offset;
4161         drm_gem_object_unreference(obj);
4162         mutex_unlock(&dev->struct_mutex);
4163
4164         return 0;
4165 }
4166
4167 int
4168 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4169                      struct drm_file *file_priv)
4170 {
4171         struct drm_i915_gem_pin *args = data;
4172         struct drm_gem_object *obj;
4173         struct drm_i915_gem_object *obj_priv;
4174         int ret;
4175
4176         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4177         if (obj == NULL) {
4178                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4179                           args->handle);
4180                 return -ENOENT;
4181         }
4182
4183         obj_priv = to_intel_bo(obj);
4184
4185         ret = i915_mutex_lock_interruptible(dev);
4186         if (ret) {
4187                 drm_gem_object_unreference_unlocked(obj);
4188                 return ret;
4189         }
4190
4191         if (obj_priv->pin_filp != file_priv) {
4192                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4193                           args->handle);
4194                 drm_gem_object_unreference(obj);
4195                 mutex_unlock(&dev->struct_mutex);
4196                 return -EINVAL;
4197         }
4198         obj_priv->user_pin_count--;
4199         if (obj_priv->user_pin_count == 0) {
4200                 obj_priv->pin_filp = NULL;
4201                 i915_gem_object_unpin(obj);
4202         }
4203
4204         drm_gem_object_unreference(obj);
4205         mutex_unlock(&dev->struct_mutex);
4206         return 0;
4207 }
4208
4209 int
4210 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4211                     struct drm_file *file_priv)
4212 {
4213         struct drm_i915_gem_busy *args = data;
4214         struct drm_gem_object *obj;
4215         struct drm_i915_gem_object *obj_priv;
4216         int ret;
4217
4218         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4219         if (obj == NULL) {
4220                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4221                           args->handle);
4222                 return -ENOENT;
4223         }
4224
4225         ret = i915_mutex_lock_interruptible(dev);
4226         if (ret) {
4227                 drm_gem_object_unreference_unlocked(obj);
4228                 return ret;
4229         }
4230
4231         /* Count all active objects as busy, even if they are currently not used
4232          * by the gpu. Users of this interface expect objects to eventually
4233          * become non-busy without any further actions, therefore emit any
4234          * necessary flushes here.
4235          */
4236         obj_priv = to_intel_bo(obj);
4237         args->busy = obj_priv->active;
4238         if (args->busy) {
4239                 /* Unconditionally flush objects, even when the gpu still uses this
4240                  * object. Userspace calling this function indicates that it wants to
4241                  * use this buffer rather sooner than later, so issuing the required
4242                  * flush earlier is beneficial.
4243                  */
4244                 if (obj->write_domain & I915_GEM_GPU_DOMAINS)
4245                         i915_gem_flush_ring(dev, file_priv,
4246                                             obj_priv->ring,
4247                                             0, obj->write_domain);
4248
4249                 /* Update the active list for the hardware's current position.
4250                  * Otherwise this only updates on a delayed timer or when irqs
4251                  * are actually unmasked, and our working set ends up being
4252                  * larger than required.
4253                  */
4254                 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4255
4256                 args->busy = obj_priv->active;
4257         }
4258
4259         drm_gem_object_unreference(obj);
4260         mutex_unlock(&dev->struct_mutex);
4261         return 0;
4262 }
4263
4264 int
4265 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4266                         struct drm_file *file_priv)
4267 {
4268     return i915_gem_ring_throttle(dev, file_priv);
4269 }
4270
4271 int
4272 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4273                        struct drm_file *file_priv)
4274 {
4275         struct drm_i915_gem_madvise *args = data;
4276         struct drm_gem_object *obj;
4277         struct drm_i915_gem_object *obj_priv;
4278         int ret;
4279
4280         switch (args->madv) {
4281         case I915_MADV_DONTNEED:
4282         case I915_MADV_WILLNEED:
4283             break;
4284         default:
4285             return -EINVAL;
4286         }
4287
4288         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4289         if (obj == NULL) {
4290                 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4291                           args->handle);
4292                 return -ENOENT;
4293         }
4294         obj_priv = to_intel_bo(obj);
4295
4296         ret = i915_mutex_lock_interruptible(dev);
4297         if (ret) {
4298                 drm_gem_object_unreference_unlocked(obj);
4299                 return ret;
4300         }
4301
4302         if (obj_priv->pin_count) {
4303                 drm_gem_object_unreference(obj);
4304                 mutex_unlock(&dev->struct_mutex);
4305
4306                 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4307                 return -EINVAL;
4308         }
4309
4310         if (obj_priv->madv != __I915_MADV_PURGED)
4311                 obj_priv->madv = args->madv;
4312
4313         /* if the object is no longer bound, discard its backing storage */
4314         if (i915_gem_object_is_purgeable(obj_priv) &&
4315             obj_priv->gtt_space == NULL)
4316                 i915_gem_object_truncate(obj);
4317
4318         args->retained = obj_priv->madv != __I915_MADV_PURGED;
4319
4320         drm_gem_object_unreference(obj);
4321         mutex_unlock(&dev->struct_mutex);
4322
4323         return 0;
4324 }
4325
4326 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4327                                               size_t size)
4328 {
4329         struct drm_i915_private *dev_priv = dev->dev_private;
4330         struct drm_i915_gem_object *obj;
4331
4332         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4333         if (obj == NULL)
4334                 return NULL;
4335
4336         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4337                 kfree(obj);
4338                 return NULL;
4339         }
4340
4341         i915_gem_info_add_obj(dev_priv, size);
4342
4343         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4344         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4345
4346         obj->agp_type = AGP_USER_MEMORY;
4347         obj->base.driver_private = NULL;
4348         obj->fence_reg = I915_FENCE_REG_NONE;
4349         INIT_LIST_HEAD(&obj->list);
4350         INIT_LIST_HEAD(&obj->gpu_write_list);
4351         obj->madv = I915_MADV_WILLNEED;
4352
4353         return &obj->base;
4354 }
4355
4356 int i915_gem_init_object(struct drm_gem_object *obj)
4357 {
4358         BUG();
4359
4360         return 0;
4361 }
4362
4363 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4364 {
4365         struct drm_device *dev = obj->dev;
4366         drm_i915_private_t *dev_priv = dev->dev_private;
4367         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4368         int ret;
4369
4370         ret = i915_gem_object_unbind(obj);
4371         if (ret == -ERESTARTSYS) {
4372                 list_move(&obj_priv->list,
4373                           &dev_priv->mm.deferred_free_list);
4374                 return;
4375         }
4376
4377         if (obj_priv->mmap_offset)
4378                 i915_gem_free_mmap_offset(obj);
4379
4380         drm_gem_object_release(obj);
4381         i915_gem_info_remove_obj(dev_priv, obj->size);
4382
4383         kfree(obj_priv->page_cpu_valid);
4384         kfree(obj_priv->bit_17);
4385         kfree(obj_priv);
4386 }
4387
4388 void i915_gem_free_object(struct drm_gem_object *obj)
4389 {
4390         struct drm_device *dev = obj->dev;
4391         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4392
4393         trace_i915_gem_object_destroy(obj);
4394
4395         while (obj_priv->pin_count > 0)
4396                 i915_gem_object_unpin(obj);
4397
4398         if (obj_priv->phys_obj)
4399                 i915_gem_detach_phys_object(dev, obj);
4400
4401         i915_gem_free_object_tail(obj);
4402 }
4403
4404 int
4405 i915_gem_idle(struct drm_device *dev)
4406 {
4407         drm_i915_private_t *dev_priv = dev->dev_private;
4408         int ret;
4409
4410         mutex_lock(&dev->struct_mutex);
4411
4412         if (dev_priv->mm.suspended ||
4413                         (dev_priv->render_ring.gem_object == NULL) ||
4414                         (HAS_BSD(dev) &&
4415                          dev_priv->bsd_ring.gem_object == NULL)) {
4416                 mutex_unlock(&dev->struct_mutex);
4417                 return 0;
4418         }
4419
4420         ret = i915_gpu_idle(dev);
4421         if (ret) {
4422                 mutex_unlock(&dev->struct_mutex);
4423                 return ret;
4424         }
4425
4426         /* Under UMS, be paranoid and evict. */
4427         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4428                 ret = i915_gem_evict_inactive(dev);
4429                 if (ret) {
4430                         mutex_unlock(&dev->struct_mutex);
4431                         return ret;
4432                 }
4433         }
4434
4435         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4436          * We need to replace this with a semaphore, or something.
4437          * And not confound mm.suspended!
4438          */
4439         dev_priv->mm.suspended = 1;
4440         del_timer_sync(&dev_priv->hangcheck_timer);
4441
4442         i915_kernel_lost_context(dev);
4443         i915_gem_cleanup_ringbuffer(dev);
4444
4445         mutex_unlock(&dev->struct_mutex);
4446
4447         /* Cancel the retire work handler, which should be idle now. */
4448         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4449
4450         return 0;
4451 }
4452
4453 /*
4454  * 965+ support PIPE_CONTROL commands, which provide finer grained control
4455  * over cache flushing.
4456  */
4457 static int
4458 i915_gem_init_pipe_control(struct drm_device *dev)
4459 {
4460         drm_i915_private_t *dev_priv = dev->dev_private;
4461         struct drm_gem_object *obj;
4462         struct drm_i915_gem_object *obj_priv;
4463         int ret;
4464
4465         obj = i915_gem_alloc_object(dev, 4096);
4466         if (obj == NULL) {
4467                 DRM_ERROR("Failed to allocate seqno page\n");
4468                 ret = -ENOMEM;
4469                 goto err;
4470         }
4471         obj_priv = to_intel_bo(obj);
4472         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4473
4474         ret = i915_gem_object_pin(obj, 4096);
4475         if (ret)
4476                 goto err_unref;
4477
4478         dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4479         dev_priv->seqno_page =  kmap(obj_priv->pages[0]);
4480         if (dev_priv->seqno_page == NULL)
4481                 goto err_unpin;
4482
4483         dev_priv->seqno_obj = obj;
4484         memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4485
4486         return 0;
4487
4488 err_unpin:
4489         i915_gem_object_unpin(obj);
4490 err_unref:
4491         drm_gem_object_unreference(obj);
4492 err:
4493         return ret;
4494 }
4495
4496
4497 static void
4498 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4499 {
4500         drm_i915_private_t *dev_priv = dev->dev_private;
4501         struct drm_gem_object *obj;
4502         struct drm_i915_gem_object *obj_priv;
4503
4504         obj = dev_priv->seqno_obj;
4505         obj_priv = to_intel_bo(obj);
4506         kunmap(obj_priv->pages[0]);
4507         i915_gem_object_unpin(obj);
4508         drm_gem_object_unreference(obj);
4509         dev_priv->seqno_obj = NULL;
4510
4511         dev_priv->seqno_page = NULL;
4512 }
4513
4514 int
4515 i915_gem_init_ringbuffer(struct drm_device *dev)
4516 {
4517         drm_i915_private_t *dev_priv = dev->dev_private;
4518         int ret;
4519
4520         if (HAS_PIPE_CONTROL(dev)) {
4521                 ret = i915_gem_init_pipe_control(dev);
4522                 if (ret)
4523                         return ret;
4524         }
4525
4526         ret = intel_init_render_ring_buffer(dev);
4527         if (ret)
4528                 goto cleanup_pipe_control;
4529
4530         if (HAS_BSD(dev)) {
4531                 ret = intel_init_bsd_ring_buffer(dev);
4532                 if (ret)
4533                         goto cleanup_render_ring;
4534         }
4535
4536         dev_priv->next_seqno = 1;
4537
4538         return 0;
4539
4540 cleanup_render_ring:
4541         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4542 cleanup_pipe_control:
4543         if (HAS_PIPE_CONTROL(dev))
4544                 i915_gem_cleanup_pipe_control(dev);
4545         return ret;
4546 }
4547
4548 void
4549 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4550 {
4551         drm_i915_private_t *dev_priv = dev->dev_private;
4552
4553         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4554         if (HAS_BSD(dev))
4555                 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4556         if (HAS_PIPE_CONTROL(dev))
4557                 i915_gem_cleanup_pipe_control(dev);
4558 }
4559
4560 int
4561 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4562                        struct drm_file *file_priv)
4563 {
4564         drm_i915_private_t *dev_priv = dev->dev_private;
4565         int ret;
4566
4567         if (drm_core_check_feature(dev, DRIVER_MODESET))
4568                 return 0;
4569
4570         if (atomic_read(&dev_priv->mm.wedged)) {
4571                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4572                 atomic_set(&dev_priv->mm.wedged, 0);
4573         }
4574
4575         mutex_lock(&dev->struct_mutex);
4576         dev_priv->mm.suspended = 0;
4577
4578         ret = i915_gem_init_ringbuffer(dev);
4579         if (ret != 0) {
4580                 mutex_unlock(&dev->struct_mutex);
4581                 return ret;
4582         }
4583
4584         BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4585         BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
4586         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4587         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4588         BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4589         BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
4590         mutex_unlock(&dev->struct_mutex);
4591
4592         ret = drm_irq_install(dev);
4593         if (ret)
4594                 goto cleanup_ringbuffer;
4595
4596         return 0;
4597
4598 cleanup_ringbuffer:
4599         mutex_lock(&dev->struct_mutex);
4600         i915_gem_cleanup_ringbuffer(dev);
4601         dev_priv->mm.suspended = 1;
4602         mutex_unlock(&dev->struct_mutex);
4603
4604         return ret;
4605 }
4606
4607 int
4608 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4609                        struct drm_file *file_priv)
4610 {
4611         if (drm_core_check_feature(dev, DRIVER_MODESET))
4612                 return 0;
4613
4614         drm_irq_uninstall(dev);
4615         return i915_gem_idle(dev);
4616 }
4617
4618 void
4619 i915_gem_lastclose(struct drm_device *dev)
4620 {
4621         int ret;
4622
4623         if (drm_core_check_feature(dev, DRIVER_MODESET))
4624                 return;
4625
4626         ret = i915_gem_idle(dev);
4627         if (ret)
4628                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4629 }
4630
4631 void
4632 i915_gem_load(struct drm_device *dev)
4633 {
4634         int i;
4635         drm_i915_private_t *dev_priv = dev->dev_private;
4636
4637         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4638         INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4639         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4640         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
4641         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4642         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4643         INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4644         INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4645         if (HAS_BSD(dev)) {
4646                 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4647                 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4648         }
4649         for (i = 0; i < 16; i++)
4650                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4651         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4652                           i915_gem_retire_work_handler);
4653         init_completion(&dev_priv->error_completion);
4654         spin_lock(&shrink_list_lock);
4655         list_add(&dev_priv->mm.shrink_list, &shrink_list);
4656         spin_unlock(&shrink_list_lock);
4657
4658         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4659         if (IS_GEN3(dev)) {
4660                 u32 tmp = I915_READ(MI_ARB_STATE);
4661                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4662                         /* arb state is a masked write, so set bit + bit in mask */
4663                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4664                         I915_WRITE(MI_ARB_STATE, tmp);
4665                 }
4666         }
4667
4668         /* Old X drivers will take 0-2 for front, back, depth buffers */
4669         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4670                 dev_priv->fence_reg_start = 3;
4671
4672         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4673                 dev_priv->num_fence_regs = 16;
4674         else
4675                 dev_priv->num_fence_regs = 8;
4676
4677         /* Initialize fence registers to zero */
4678         switch (INTEL_INFO(dev)->gen) {
4679         case 6:
4680                 for (i = 0; i < 16; i++)
4681                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
4682                 break;
4683         case 5:
4684         case 4:
4685                 for (i = 0; i < 16; i++)
4686                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4687                 break;
4688         case 3:
4689                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4690                         for (i = 0; i < 8; i++)
4691                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4692         case 2:
4693                 for (i = 0; i < 8; i++)
4694                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4695                 break;
4696         }
4697         i915_gem_detect_bit_6_swizzle(dev);
4698         init_waitqueue_head(&dev_priv->pending_flip_queue);
4699 }
4700
4701 /*
4702  * Create a physically contiguous memory object for this object
4703  * e.g. for cursor + overlay regs
4704  */
4705 static int i915_gem_init_phys_object(struct drm_device *dev,
4706                                      int id, int size, int align)
4707 {
4708         drm_i915_private_t *dev_priv = dev->dev_private;
4709         struct drm_i915_gem_phys_object *phys_obj;
4710         int ret;
4711
4712         if (dev_priv->mm.phys_objs[id - 1] || !size)
4713                 return 0;
4714
4715         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4716         if (!phys_obj)
4717                 return -ENOMEM;
4718
4719         phys_obj->id = id;
4720
4721         phys_obj->handle = drm_pci_alloc(dev, size, align);
4722         if (!phys_obj->handle) {
4723                 ret = -ENOMEM;
4724                 goto kfree_obj;
4725         }
4726 #ifdef CONFIG_X86
4727         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4728 #endif
4729
4730         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4731
4732         return 0;
4733 kfree_obj:
4734         kfree(phys_obj);
4735         return ret;
4736 }
4737
4738 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4739 {
4740         drm_i915_private_t *dev_priv = dev->dev_private;
4741         struct drm_i915_gem_phys_object *phys_obj;
4742
4743         if (!dev_priv->mm.phys_objs[id - 1])
4744                 return;
4745
4746         phys_obj = dev_priv->mm.phys_objs[id - 1];
4747         if (phys_obj->cur_obj) {
4748                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4749         }
4750
4751 #ifdef CONFIG_X86
4752         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4753 #endif
4754         drm_pci_free(dev, phys_obj->handle);
4755         kfree(phys_obj);
4756         dev_priv->mm.phys_objs[id - 1] = NULL;
4757 }
4758
4759 void i915_gem_free_all_phys_object(struct drm_device *dev)
4760 {
4761         int i;
4762
4763         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4764                 i915_gem_free_phys_object(dev, i);
4765 }
4766
4767 void i915_gem_detach_phys_object(struct drm_device *dev,
4768                                  struct drm_gem_object *obj)
4769 {
4770         struct drm_i915_gem_object *obj_priv;
4771         int i;
4772         int ret;
4773         int page_count;
4774
4775         obj_priv = to_intel_bo(obj);
4776         if (!obj_priv->phys_obj)
4777                 return;
4778
4779         ret = i915_gem_object_get_pages(obj, 0);
4780         if (ret)
4781                 goto out;
4782
4783         page_count = obj->size / PAGE_SIZE;
4784
4785         for (i = 0; i < page_count; i++) {
4786                 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4787                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4788
4789                 memcpy(dst, src, PAGE_SIZE);
4790                 kunmap_atomic(dst, KM_USER0);
4791         }
4792         drm_clflush_pages(obj_priv->pages, page_count);
4793         drm_agp_chipset_flush(dev);
4794
4795         i915_gem_object_put_pages(obj);
4796 out:
4797         obj_priv->phys_obj->cur_obj = NULL;
4798         obj_priv->phys_obj = NULL;
4799 }
4800
4801 int
4802 i915_gem_attach_phys_object(struct drm_device *dev,
4803                             struct drm_gem_object *obj,
4804                             int id,
4805                             int align)
4806 {
4807         drm_i915_private_t *dev_priv = dev->dev_private;
4808         struct drm_i915_gem_object *obj_priv;
4809         int ret = 0;
4810         int page_count;
4811         int i;
4812
4813         if (id > I915_MAX_PHYS_OBJECT)
4814                 return -EINVAL;
4815
4816         obj_priv = to_intel_bo(obj);
4817
4818         if (obj_priv->phys_obj) {
4819                 if (obj_priv->phys_obj->id == id)
4820                         return 0;
4821                 i915_gem_detach_phys_object(dev, obj);
4822         }
4823
4824         /* create a new object */
4825         if (!dev_priv->mm.phys_objs[id - 1]) {
4826                 ret = i915_gem_init_phys_object(dev, id,
4827                                                 obj->size, align);
4828                 if (ret) {
4829                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4830                         goto out;
4831                 }
4832         }
4833
4834         /* bind to the object */
4835         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4836         obj_priv->phys_obj->cur_obj = obj;
4837
4838         ret = i915_gem_object_get_pages(obj, 0);
4839         if (ret) {
4840                 DRM_ERROR("failed to get page list\n");
4841                 goto out;
4842         }
4843
4844         page_count = obj->size / PAGE_SIZE;
4845
4846         for (i = 0; i < page_count; i++) {
4847                 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4848                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4849
4850                 memcpy(dst, src, PAGE_SIZE);
4851                 kunmap_atomic(src, KM_USER0);
4852         }
4853
4854         i915_gem_object_put_pages(obj);
4855
4856         return 0;
4857 out:
4858         return ret;
4859 }
4860
4861 static int
4862 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4863                      struct drm_i915_gem_pwrite *args,
4864                      struct drm_file *file_priv)
4865 {
4866         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4867         void *obj_addr;
4868         int ret;
4869         char __user *user_data;
4870
4871         user_data = (char __user *) (uintptr_t) args->data_ptr;
4872         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4873
4874         DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4875         ret = copy_from_user(obj_addr, user_data, args->size);
4876         if (ret)
4877                 return -EFAULT;
4878
4879         drm_agp_chipset_flush(dev);
4880         return 0;
4881 }
4882
4883 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4884 {
4885         struct drm_i915_file_private *file_priv = file->driver_priv;
4886
4887         /* Clean up our request list when the client is going away, so that
4888          * later retire_requests won't dereference our soon-to-be-gone
4889          * file_priv.
4890          */
4891         spin_lock(&file_priv->mm.lock);
4892         while (!list_empty(&file_priv->mm.request_list)) {
4893                 struct drm_i915_gem_request *request;
4894
4895                 request = list_first_entry(&file_priv->mm.request_list,
4896                                            struct drm_i915_gem_request,
4897                                            client_list);
4898                 list_del(&request->client_list);
4899                 request->file_priv = NULL;
4900         }
4901         spin_unlock(&file_priv->mm.lock);
4902 }
4903
4904 static int
4905 i915_gpu_is_active(struct drm_device *dev)
4906 {
4907         drm_i915_private_t *dev_priv = dev->dev_private;
4908         int lists_empty;
4909
4910         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4911                       list_empty(&dev_priv->render_ring.active_list);
4912         if (HAS_BSD(dev))
4913                 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
4914
4915         return !lists_empty;
4916 }
4917
4918 static int
4919 i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
4920 {
4921         drm_i915_private_t *dev_priv, *next_dev;
4922         struct drm_i915_gem_object *obj_priv, *next_obj;
4923         int cnt = 0;
4924         int would_deadlock = 1;
4925
4926         /* "fast-path" to count number of available objects */
4927         if (nr_to_scan == 0) {
4928                 spin_lock(&shrink_list_lock);
4929                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4930                         struct drm_device *dev = dev_priv->dev;
4931
4932                         if (mutex_trylock(&dev->struct_mutex)) {
4933                                 list_for_each_entry(obj_priv,
4934                                                     &dev_priv->mm.inactive_list,
4935                                                     list)
4936                                         cnt++;
4937                                 mutex_unlock(&dev->struct_mutex);
4938                         }
4939                 }
4940                 spin_unlock(&shrink_list_lock);
4941
4942                 return (cnt / 100) * sysctl_vfs_cache_pressure;
4943         }
4944
4945         spin_lock(&shrink_list_lock);
4946
4947 rescan:
4948         /* first scan for clean buffers */
4949         list_for_each_entry_safe(dev_priv, next_dev,
4950                                  &shrink_list, mm.shrink_list) {
4951                 struct drm_device *dev = dev_priv->dev;
4952
4953                 if (! mutex_trylock(&dev->struct_mutex))
4954                         continue;
4955
4956                 spin_unlock(&shrink_list_lock);
4957                 i915_gem_retire_requests(dev);
4958
4959                 list_for_each_entry_safe(obj_priv, next_obj,
4960                                          &dev_priv->mm.inactive_list,
4961                                          list) {
4962                         if (i915_gem_object_is_purgeable(obj_priv)) {
4963                                 i915_gem_object_unbind(&obj_priv->base);
4964                                 if (--nr_to_scan <= 0)
4965                                         break;
4966                         }
4967                 }
4968
4969                 spin_lock(&shrink_list_lock);
4970                 mutex_unlock(&dev->struct_mutex);
4971
4972                 would_deadlock = 0;
4973
4974                 if (nr_to_scan <= 0)
4975                         break;
4976         }
4977
4978         /* second pass, evict/count anything still on the inactive list */
4979         list_for_each_entry_safe(dev_priv, next_dev,
4980                                  &shrink_list, mm.shrink_list) {
4981                 struct drm_device *dev = dev_priv->dev;
4982
4983                 if (! mutex_trylock(&dev->struct_mutex))
4984                         continue;
4985
4986                 spin_unlock(&shrink_list_lock);
4987
4988                 list_for_each_entry_safe(obj_priv, next_obj,
4989                                          &dev_priv->mm.inactive_list,
4990                                          list) {
4991                         if (nr_to_scan > 0) {
4992                                 i915_gem_object_unbind(&obj_priv->base);
4993                                 nr_to_scan--;
4994                         } else
4995                                 cnt++;
4996                 }
4997
4998                 spin_lock(&shrink_list_lock);
4999                 mutex_unlock(&dev->struct_mutex);
5000
5001                 would_deadlock = 0;
5002         }
5003
5004         if (nr_to_scan) {
5005                 int active = 0;
5006
5007                 /*
5008                  * We are desperate for pages, so as a last resort, wait
5009                  * for the GPU to finish and discard whatever we can.
5010                  * This has a dramatic impact to reduce the number of
5011                  * OOM-killer events whilst running the GPU aggressively.
5012                  */
5013                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5014                         struct drm_device *dev = dev_priv->dev;
5015
5016                         if (!mutex_trylock(&dev->struct_mutex))
5017                                 continue;
5018
5019                         spin_unlock(&shrink_list_lock);
5020
5021                         if (i915_gpu_is_active(dev)) {
5022                                 i915_gpu_idle(dev);
5023                                 active++;
5024                         }
5025
5026                         spin_lock(&shrink_list_lock);
5027                         mutex_unlock(&dev->struct_mutex);
5028                 }
5029
5030                 if (active)
5031                         goto rescan;
5032         }
5033
5034         spin_unlock(&shrink_list_lock);
5035
5036         if (would_deadlock)
5037                 return -1;
5038         else if (cnt > 0)
5039                 return (cnt / 100) * sysctl_vfs_cache_pressure;
5040         else
5041                 return 0;
5042 }
5043
5044 static struct shrinker shrinker = {
5045         .shrink = i915_gem_shrink,
5046         .seeks = DEFAULT_SEEKS,
5047 };
5048
5049 __init void
5050 i915_gem_shrinker_init(void)
5051 {
5052     register_shrinker(&shrinker);
5053 }
5054
5055 __exit void
5056 i915_gem_shrinker_exit(void)
5057 {
5058     unregister_shrinker(&shrinker);
5059 }