drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/intel-gtt.h>
  38
  39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
  40
  41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
  42                                                   bool pipelined);
  43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  46                                              int write);
  47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  48                                                      uint64_t offset,
  49                                                      uint64_t size);
  50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  51 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
  52                                           bool interruptible);
  53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
  54                                            unsigned alignment);
  55 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
  56 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  57                                 struct drm_i915_gem_pwrite *args,
  58                                 struct drm_file *file_priv);
  59 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
  60
  61 static int
  62 i915_gem_object_get_pages(struct drm_gem_object *obj,
  63                           gfp_t gfpmask);
  64
  65 static void
  66 i915_gem_object_put_pages(struct drm_gem_object *obj);
  67
  68 static LIST_HEAD(shrink_list);
  69 static DEFINE_SPINLOCK(shrink_list_lock);
  70
  71 /* some bookkeeping */
  72 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  73                                   size_t size)
  74 {
  75         dev_priv->mm.object_count++;
  76         dev_priv->mm.object_memory += size;
  77 }
  78
  79 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  80                                      size_t size)
  81 {
  82         dev_priv->mm.object_count--;
  83         dev_priv->mm.object_memory -= size;
  84 }
  85
  86 static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv,
  87                                   size_t size)
  88 {
  89         dev_priv->mm.gtt_count++;
  90         dev_priv->mm.gtt_memory += size;
  91 }
  92
  93 static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv,
  94                                      size_t size)
  95 {
  96         dev_priv->mm.gtt_count--;
  97         dev_priv->mm.gtt_memory -= size;
  98 }
  99
 100 static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv,
 101                                   size_t size)
 102 {
 103         dev_priv->mm.pin_count++;
 104         dev_priv->mm.pin_memory += size;
 105 }
 106
 107 static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv,
 108                                      size_t size)
 109 {
 110         dev_priv->mm.pin_count--;
 111         dev_priv->mm.pin_memory -= size;
 112 }
 113
 114 int
 115 i915_gem_check_is_wedged(struct drm_device *dev)
 116 {
 117         struct drm_i915_private *dev_priv = dev->dev_private;
 118         struct completion *x = &dev_priv->error_completion;
 119         unsigned long flags;
 120         int ret;
 121
 122         if (!atomic_read(&dev_priv->mm.wedged))
 123                 return 0;
 124
 125         ret = wait_for_completion_interruptible(x);
 126         if (ret)
 127                 return ret;
 128
 129         /* Success, we reset the GPU! */
 130         if (!atomic_read(&dev_priv->mm.wedged))
 131                 return 0;
 132
 133         /* GPU is hung, bump the completion count to account for
 134          * the token we just consumed so that we never hit zero and
 135          * end up waiting upon a subsequent completion event that
 136          * will never happen.
 137          */
 138         spin_lock_irqsave(&x->wait.lock, flags);
 139         x->done++;
 140         spin_unlock_irqrestore(&x->wait.lock, flags);
 141         return -EIO;
 142 }
 143
 144 static int i915_mutex_lock_interruptible(struct drm_device *dev)
 145 {
 146         struct drm_i915_private *dev_priv = dev->dev_private;
 147         int ret;
 148
 149         ret = i915_gem_check_is_wedged(dev);
 150         if (ret)
 151                 return ret;
 152
 153         ret = mutex_lock_interruptible(&dev->struct_mutex);
 154         if (ret)
 155                 return ret;
 156
 157         if (atomic_read(&dev_priv->mm.wedged)) {
 158                 mutex_unlock(&dev->struct_mutex);
 159                 return -EAGAIN;
 160         }
 161
 162         WARN_ON(i915_verify_lists(dev));
 163         return 0;
 164 }
 165
 166 static inline bool
 167 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
 168 {
 169         return obj_priv->gtt_space &&
 170                 !obj_priv->active &&
 171                 obj_priv->pin_count == 0;
 172 }
 173
 174 int i915_gem_do_init(struct drm_device *dev,
 175                      unsigned long start,
 176                      unsigned long end)
 177 {
 178         drm_i915_private_t *dev_priv = dev->dev_private;
 179
 180         if (start >= end ||
 181             (start & (PAGE_SIZE - 1)) != 0 ||
 182             (end & (PAGE_SIZE - 1)) != 0) {
 183                 return -EINVAL;
 184         }
 185
 186         drm_mm_init(&dev_priv->mm.gtt_space, start,
 187                     end - start);
 188
 189         dev_priv->mm.gtt_total = end - start;
 190
 191         return 0;
 192 }
 193
 194 int
 195 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 196                     struct drm_file *file_priv)
 197 {
 198         struct drm_i915_gem_init *args = data;
 199         int ret;
 200
 201         mutex_lock(&dev->struct_mutex);
 202         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
 203         mutex_unlock(&dev->struct_mutex);
 204
 205         return ret;
 206 }
 207
 208 int
 209 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 210                             struct drm_file *file_priv)
 211 {
 212         struct drm_i915_private *dev_priv = dev->dev_private;
 213         struct drm_i915_gem_get_aperture *args = data;
 214
 215         if (!(dev->driver->driver_features & DRIVER_GEM))
 216                 return -ENODEV;
 217
 218         mutex_lock(&dev->struct_mutex);
 219         args->aper_size = dev_priv->mm.gtt_total;
 220         args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory;
 221         mutex_unlock(&dev->struct_mutex);
 222
 223         return 0;
 224 }
 225
 226
 227 /**
 228  * Creates a new mm object and returns a handle to it.
 229  */
 230 int
 231 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 232                       struct drm_file *file_priv)
 233 {
 234         struct drm_i915_gem_create *args = data;
 235         struct drm_gem_object *obj;
 236         int ret;
 237         u32 handle;
 238
 239         args->size = roundup(args->size, PAGE_SIZE);
 240
 241         /* Allocate the new object */
 242         obj = i915_gem_alloc_object(dev, args->size);
 243         if (obj == NULL)
 244                 return -ENOMEM;
 245
 246         ret = drm_gem_handle_create(file_priv, obj, &handle);
 247         if (ret) {
 248                 drm_gem_object_release(obj);
 249                 i915_gem_info_remove_obj(dev->dev_private, obj->size);
 250                 kfree(obj);
 251                 return ret;
 252         }
 253
 254         /* drop reference from allocate - handle holds it now */
 255         drm_gem_object_unreference(obj);
 256         trace_i915_gem_object_create(obj);
 257
 258         args->handle = handle;
 259         return 0;
 260 }
 261
 262 static inline int
 263 fast_shmem_read(struct page **pages,
 264                 loff_t page_base, int page_offset,
 265                 char __user *data,
 266                 int length)
 267 {
 268         char *vaddr;
 269         int ret;
 270
 271         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]);
 272         ret = __copy_to_user_inatomic(data, vaddr + page_offset, length);
 273         kunmap_atomic(vaddr);
 274
 275         return ret;
 276 }
 277
 278 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
 279 {
 280         drm_i915_private_t *dev_priv = obj->dev->dev_private;
 281         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 282
 283         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 284                 obj_priv->tiling_mode != I915_TILING_NONE;
 285 }
 286
 287 static inline void
 288 slow_shmem_copy(struct page *dst_page,
 289                 int dst_offset,
 290                 struct page *src_page,
 291                 int src_offset,
 292                 int length)
 293 {
 294         char *dst_vaddr, *src_vaddr;
 295
 296         dst_vaddr = kmap(dst_page);
 297         src_vaddr = kmap(src_page);
 298
 299         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 300
 301         kunmap(src_page);
 302         kunmap(dst_page);
 303 }
 304
 305 static inline void
 306 slow_shmem_bit17_copy(struct page *gpu_page,
 307                       int gpu_offset,
 308                       struct page *cpu_page,
 309                       int cpu_offset,
 310                       int length,
 311                       int is_read)
 312 {
 313         char *gpu_vaddr, *cpu_vaddr;
 314
 315         /* Use the unswizzled path if this page isn't affected. */
 316         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 317                 if (is_read)
 318                         return slow_shmem_copy(cpu_page, cpu_offset,
 319                                                gpu_page, gpu_offset, length);
 320                 else
 321                         return slow_shmem_copy(gpu_page, gpu_offset,
 322                                                cpu_page, cpu_offset, length);
 323         }
 324
 325         gpu_vaddr = kmap(gpu_page);
 326         cpu_vaddr = kmap(cpu_page);
 327
 328         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 329          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 330          */
 331         while (length > 0) {
 332                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 333                 int this_length = min(cacheline_end - gpu_offset, length);
 334                 int swizzled_gpu_offset = gpu_offset ^ 64;
 335
 336                 if (is_read) {
 337                         memcpy(cpu_vaddr + cpu_offset,
 338                                gpu_vaddr + swizzled_gpu_offset,
 339                                this_length);
 340                 } else {
 341                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 342                                cpu_vaddr + cpu_offset,
 343                                this_length);
 344                 }
 345                 cpu_offset += this_length;
 346                 gpu_offset += this_length;
 347                 length -= this_length;
 348         }
 349
 350         kunmap(cpu_page);
 351         kunmap(gpu_page);
 352 }
 353
 354 /**
 355  * This is the fast shmem pread path, which attempts to copy_from_user directly
 356  * from the backing pages of the object to the user's address space.  On a
 357  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 358  */
 359 static int
 360 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
 361                           struct drm_i915_gem_pread *args,
 362                           struct drm_file *file_priv)
 363 {
 364         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 365         ssize_t remain;
 366         loff_t offset, page_base;
 367         char __user *user_data;
 368         int page_offset, page_length;
 369
 370         user_data = (char __user *) (uintptr_t) args->data_ptr;
 371         remain = args->size;
 372
 373         obj_priv = to_intel_bo(obj);
 374         offset = args->offset;
 375
 376         while (remain > 0) {
 377                 /* Operation in this page
 378                  *
 379                  * page_base = page offset within aperture
 380                  * page_offset = offset within page
 381                  * page_length = bytes to copy for this page
 382                  */
 383                 page_base = (offset & ~(PAGE_SIZE-1));
 384                 page_offset = offset & (PAGE_SIZE-1);
 385                 page_length = remain;
 386                 if ((page_offset + remain) > PAGE_SIZE)
 387                         page_length = PAGE_SIZE - page_offset;
 388
 389                 if (fast_shmem_read(obj_priv->pages,
 390                                     page_base, page_offset,
 391                                     user_data, page_length))
 392                         return -EFAULT;
 393
 394                 remain -= page_length;
 395                 user_data += page_length;
 396                 offset += page_length;
 397         }
 398
 399         return 0;
 400 }
 401
 402 static int
 403 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
 404 {
 405         int ret;
 406
 407         ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
 408
 409         /* If we've insufficient memory to map in the pages, attempt
 410          * to make some space by throwing out some old buffers.
 411          */
 412         if (ret == -ENOMEM) {
 413                 struct drm_device *dev = obj->dev;
 414
 415                 ret = i915_gem_evict_something(dev, obj->size,
 416                                                i915_gem_get_gtt_alignment(obj));
 417                 if (ret)
 418                         return ret;
 419
 420                 ret = i915_gem_object_get_pages(obj, 0);
 421         }
 422
 423         return ret;
 424 }
 425
 426 /**
 427  * This is the fallback shmem pread path, which allocates temporary storage
 428  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 429  * can copy out of the object's backing pages while holding the struct mutex
 430  * and not take page faults.
 431  */
 432 static int
 433 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
 434                           struct drm_i915_gem_pread *args,
 435                           struct drm_file *file_priv)
 436 {
 437         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 438         struct mm_struct *mm = current->mm;
 439         struct page **user_pages;
 440         ssize_t remain;
 441         loff_t offset, pinned_pages, i;
 442         loff_t first_data_page, last_data_page, num_pages;
 443         int shmem_page_index, shmem_page_offset;
 444         int data_page_index,  data_page_offset;
 445         int page_length;
 446         int ret;
 447         uint64_t data_ptr = args->data_ptr;
 448         int do_bit17_swizzling;
 449
 450         remain = args->size;
 451
 452         /* Pin the user pages containing the data.  We can't fault while
 453          * holding the struct mutex, yet we want to hold it while
 454          * dereferencing the user data.
 455          */
 456         first_data_page = data_ptr / PAGE_SIZE;
 457         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 458         num_pages = last_data_page - first_data_page + 1;
 459
 460         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 461         if (user_pages == NULL)
 462                 return -ENOMEM;
 463
 464         mutex_unlock(&dev->struct_mutex);
 465         down_read(&mm->mmap_sem);
 466         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 467                                       num_pages, 1, 0, user_pages, NULL);
 468         up_read(&mm->mmap_sem);
 469         mutex_lock(&dev->struct_mutex);
 470         if (pinned_pages < num_pages) {
 471                 ret = -EFAULT;
 472                 goto out;
 473         }
 474
 475         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 476                                                         args->offset,
 477                                                         args->size);
 478         if (ret)
 479                 goto out;
 480
 481         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 482
 483         obj_priv = to_intel_bo(obj);
 484         offset = args->offset;
 485
 486         while (remain > 0) {
 487                 /* Operation in this page
 488                  *
 489                  * shmem_page_index = page number within shmem file
 490                  * shmem_page_offset = offset within page in shmem file
 491                  * data_page_index = page number in get_user_pages return
 492                  * data_page_offset = offset with data_page_index page.
 493                  * page_length = bytes to copy for this page
 494                  */
 495                 shmem_page_index = offset / PAGE_SIZE;
 496                 shmem_page_offset = offset & ~PAGE_MASK;
 497                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 498                 data_page_offset = data_ptr & ~PAGE_MASK;
 499
 500                 page_length = remain;
 501                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 502                         page_length = PAGE_SIZE - shmem_page_offset;
 503                 if ((data_page_offset + page_length) > PAGE_SIZE)
 504                         page_length = PAGE_SIZE - data_page_offset;
 505
 506                 if (do_bit17_swizzling) {
 507                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 508                                               shmem_page_offset,
 509                                               user_pages[data_page_index],
 510                                               data_page_offset,
 511                                               page_length,
 512                                               1);
 513                 } else {
 514                         slow_shmem_copy(user_pages[data_page_index],
 515                                         data_page_offset,
 516                                         obj_priv->pages[shmem_page_index],
 517                                         shmem_page_offset,
 518                                         page_length);
 519                 }
 520
 521                 remain -= page_length;
 522                 data_ptr += page_length;
 523                 offset += page_length;
 524         }
 525
 526 out:
 527         for (i = 0; i < pinned_pages; i++) {
 528                 SetPageDirty(user_pages[i]);
 529                 page_cache_release(user_pages[i]);
 530         }
 531         drm_free_large(user_pages);
 532
 533         return ret;
 534 }
 535
 536 /**
 537  * Reads data from the object referenced by handle.
 538  *
 539  * On error, the contents of *data are undefined.
 540  */
 541 int
 542 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 543                      struct drm_file *file_priv)
 544 {
 545         struct drm_i915_gem_pread *args = data;
 546         struct drm_gem_object *obj;
 547         struct drm_i915_gem_object *obj_priv;
 548         int ret = 0;
 549
 550         if (args->size == 0)
 551                 return 0;
 552
 553         if (!access_ok(VERIFY_WRITE,
 554                        (char __user *)(uintptr_t)args->data_ptr,
 555                        args->size))
 556                 return -EFAULT;
 557
 558         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 559                                        args->size);
 560         if (ret)
 561                 return -EFAULT;
 562
 563         ret = i915_mutex_lock_interruptible(dev);
 564         if (ret)
 565                 return ret;
 566
 567         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 568         if (obj == NULL) {
 569                 ret = -ENOENT;
 570                 goto unlock;
 571         }
 572         obj_priv = to_intel_bo(obj);
 573
 574         /* Bounds check source.  */
 575         if (args->offset > obj->size || args->size > obj->size - args->offset) {
 576                 ret = -EINVAL;
 577                 goto out;
 578         }
 579
 580         ret = i915_gem_object_get_pages_or_evict(obj);
 581         if (ret)
 582                 goto out;
 583
 584         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 585                                                         args->offset,
 586                                                         args->size);
 587         if (ret)
 588                 goto out_put;
 589
 590         ret = -EFAULT;
 591         if (!i915_gem_object_needs_bit17_swizzle(obj))
 592                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
 593         if (ret == -EFAULT)
 594                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
 595
 596 out_put:
 597         i915_gem_object_put_pages(obj);
 598 out:
 599         drm_gem_object_unreference(obj);
 600 unlock:
 601         mutex_unlock(&dev->struct_mutex);
 602         return ret;
 603 }
 604
 605 /* This is the fast write path which cannot handle
 606  * page faults in the source data
 607  */
 608
 609 static inline int
 610 fast_user_write(struct io_mapping *mapping,
 611                 loff_t page_base, int page_offset,
 612                 char __user *user_data,
 613                 int length)
 614 {
 615         char *vaddr_atomic;
 616         unsigned long unwritten;
 617
 618         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 619         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 620                                                       user_data, length);
 621         io_mapping_unmap_atomic(vaddr_atomic);
 622         return unwritten;
 623 }
 624
 625 /* Here's the write path which can sleep for
 626  * page faults
 627  */
 628
 629 static inline void
 630 slow_kernel_write(struct io_mapping *mapping,
 631                   loff_t gtt_base, int gtt_offset,
 632                   struct page *user_page, int user_offset,
 633                   int length)
 634 {
 635         char __iomem *dst_vaddr;
 636         char *src_vaddr;
 637
 638         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 639         src_vaddr = kmap(user_page);
 640
 641         memcpy_toio(dst_vaddr + gtt_offset,
 642                     src_vaddr + user_offset,
 643                     length);
 644
 645         kunmap(user_page);
 646         io_mapping_unmap(dst_vaddr);
 647 }
 648
 649 static inline int
 650 fast_shmem_write(struct page **pages,
 651                  loff_t page_base, int page_offset,
 652                  char __user *data,
 653                  int length)
 654 {
 655         char *vaddr;
 656         int ret;
 657
 658         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]);
 659         ret = __copy_from_user_inatomic(vaddr + page_offset, data, length);
 660         kunmap_atomic(vaddr);
 661
 662         return ret;
 663 }
 664
 665 /**
 666  * This is the fast pwrite path, where we copy the data directly from the
 667  * user into the GTT, uncached.
 668  */
 669 static int
 670 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 671                          struct drm_i915_gem_pwrite *args,
 672                          struct drm_file *file_priv)
 673 {
 674         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 675         drm_i915_private_t *dev_priv = dev->dev_private;
 676         ssize_t remain;
 677         loff_t offset, page_base;
 678         char __user *user_data;
 679         int page_offset, page_length;
 680
 681         user_data = (char __user *) (uintptr_t) args->data_ptr;
 682         remain = args->size;
 683
 684         obj_priv = to_intel_bo(obj);
 685         offset = obj_priv->gtt_offset + args->offset;
 686
 687         while (remain > 0) {
 688                 /* Operation in this page
 689                  *
 690                  * page_base = page offset within aperture
 691                  * page_offset = offset within page
 692                  * page_length = bytes to copy for this page
 693                  */
 694                 page_base = (offset & ~(PAGE_SIZE-1));
 695                 page_offset = offset & (PAGE_SIZE-1);
 696                 page_length = remain;
 697                 if ((page_offset + remain) > PAGE_SIZE)
 698                         page_length = PAGE_SIZE - page_offset;
 699
 700                 /* If we get a fault while copying data, then (presumably) our
 701                  * source page isn't available.  Return the error and we'll
 702                  * retry in the slow path.
 703                  */
 704                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 705                                     page_offset, user_data, page_length))
 706
 707                         return -EFAULT;
 708
 709                 remain -= page_length;
 710                 user_data += page_length;
 711                 offset += page_length;
 712         }
 713
 714         return 0;
 715 }
 716
 717 /**
 718  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 719  * the memory and maps it using kmap_atomic for copying.
 720  *
 721  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 722  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 723  */
 724 static int
 725 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 726                          struct drm_i915_gem_pwrite *args,
 727                          struct drm_file *file_priv)
 728 {
 729         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 730         drm_i915_private_t *dev_priv = dev->dev_private;
 731         ssize_t remain;
 732         loff_t gtt_page_base, offset;
 733         loff_t first_data_page, last_data_page, num_pages;
 734         loff_t pinned_pages, i;
 735         struct page **user_pages;
 736         struct mm_struct *mm = current->mm;
 737         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 738         int ret;
 739         uint64_t data_ptr = args->data_ptr;
 740
 741         remain = args->size;
 742
 743         /* Pin the user pages containing the data.  We can't fault while
 744          * holding the struct mutex, and all of the pwrite implementations
 745          * want to hold it while dereferencing the user data.
 746          */
 747         first_data_page = data_ptr / PAGE_SIZE;
 748         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 749         num_pages = last_data_page - first_data_page + 1;
 750
 751         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 752         if (user_pages == NULL)
 753                 return -ENOMEM;
 754
 755         mutex_unlock(&dev->struct_mutex);
 756         down_read(&mm->mmap_sem);
 757         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 758                                       num_pages, 0, 0, user_pages, NULL);
 759         up_read(&mm->mmap_sem);
 760         mutex_lock(&dev->struct_mutex);
 761         if (pinned_pages < num_pages) {
 762                 ret = -EFAULT;
 763                 goto out_unpin_pages;
 764         }
 765
 766         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 767         if (ret)
 768                 goto out_unpin_pages;
 769
 770         obj_priv = to_intel_bo(obj);
 771         offset = obj_priv->gtt_offset + args->offset;
 772
 773         while (remain > 0) {
 774                 /* Operation in this page
 775                  *
 776                  * gtt_page_base = page offset within aperture
 777                  * gtt_page_offset = offset within page in aperture
 778                  * data_page_index = page number in get_user_pages return
 779                  * data_page_offset = offset with data_page_index page.
 780                  * page_length = bytes to copy for this page
 781                  */
 782                 gtt_page_base = offset & PAGE_MASK;
 783                 gtt_page_offset = offset & ~PAGE_MASK;
 784                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 785                 data_page_offset = data_ptr & ~PAGE_MASK;
 786
 787                 page_length = remain;
 788                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 789                         page_length = PAGE_SIZE - gtt_page_offset;
 790                 if ((data_page_offset + page_length) > PAGE_SIZE)
 791                         page_length = PAGE_SIZE - data_page_offset;
 792
 793                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 794                                   gtt_page_base, gtt_page_offset,
 795                                   user_pages[data_page_index],
 796                                   data_page_offset,
 797                                   page_length);
 798
 799                 remain -= page_length;
 800                 offset += page_length;
 801                 data_ptr += page_length;
 802         }
 803
 804 out_unpin_pages:
 805         for (i = 0; i < pinned_pages; i++)
 806                 page_cache_release(user_pages[i]);
 807         drm_free_large(user_pages);
 808
 809         return ret;
 810 }
 811
 812 /**
 813  * This is the fast shmem pwrite path, which attempts to directly
 814  * copy_from_user into the kmapped pages backing the object.
 815  */
 816 static int
 817 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 818                            struct drm_i915_gem_pwrite *args,
 819                            struct drm_file *file_priv)
 820 {
 821         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 822         ssize_t remain;
 823         loff_t offset, page_base;
 824         char __user *user_data;
 825         int page_offset, page_length;
 826
 827         user_data = (char __user *) (uintptr_t) args->data_ptr;
 828         remain = args->size;
 829
 830         obj_priv = to_intel_bo(obj);
 831         offset = args->offset;
 832         obj_priv->dirty = 1;
 833
 834         while (remain > 0) {
 835                 /* Operation in this page
 836                  *
 837                  * page_base = page offset within aperture
 838                  * page_offset = offset within page
 839                  * page_length = bytes to copy for this page
 840                  */
 841                 page_base = (offset & ~(PAGE_SIZE-1));
 842                 page_offset = offset & (PAGE_SIZE-1);
 843                 page_length = remain;
 844                 if ((page_offset + remain) > PAGE_SIZE)
 845                         page_length = PAGE_SIZE - page_offset;
 846
 847                 if (fast_shmem_write(obj_priv->pages,
 848                                        page_base, page_offset,
 849                                        user_data, page_length))
 850                         return -EFAULT;
 851
 852                 remain -= page_length;
 853                 user_data += page_length;
 854                 offset += page_length;
 855         }
 856
 857         return 0;
 858 }
 859
 860 /**
 861  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 862  * the memory and maps it using kmap_atomic for copying.
 863  *
 864  * This avoids taking mmap_sem for faulting on the user's address while the
 865  * struct_mutex is held.
 866  */
 867 static int
 868 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 869                            struct drm_i915_gem_pwrite *args,
 870                            struct drm_file *file_priv)
 871 {
 872         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 873         struct mm_struct *mm = current->mm;
 874         struct page **user_pages;
 875         ssize_t remain;
 876         loff_t offset, pinned_pages, i;
 877         loff_t first_data_page, last_data_page, num_pages;
 878         int shmem_page_index, shmem_page_offset;
 879         int data_page_index,  data_page_offset;
 880         int page_length;
 881         int ret;
 882         uint64_t data_ptr = args->data_ptr;
 883         int do_bit17_swizzling;
 884
 885         remain = args->size;
 886
 887         /* Pin the user pages containing the data.  We can't fault while
 888          * holding the struct mutex, and all of the pwrite implementations
 889          * want to hold it while dereferencing the user data.
 890          */
 891         first_data_page = data_ptr / PAGE_SIZE;
 892         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 893         num_pages = last_data_page - first_data_page + 1;
 894
 895         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 896         if (user_pages == NULL)
 897                 return -ENOMEM;
 898
 899         mutex_unlock(&dev->struct_mutex);
 900         down_read(&mm->mmap_sem);
 901         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 902                                       num_pages, 0, 0, user_pages, NULL);
 903         up_read(&mm->mmap_sem);
 904         mutex_lock(&dev->struct_mutex);
 905         if (pinned_pages < num_pages) {
 906                 ret = -EFAULT;
 907                 goto out;
 908         }
 909
 910         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 911         if (ret)
 912                 goto out;
 913
 914         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 915
 916         obj_priv = to_intel_bo(obj);
 917         offset = args->offset;
 918         obj_priv->dirty = 1;
 919
 920         while (remain > 0) {
 921                 /* Operation in this page
 922                  *
 923                  * shmem_page_index = page number within shmem file
 924                  * shmem_page_offset = offset within page in shmem file
 925                  * data_page_index = page number in get_user_pages return
 926                  * data_page_offset = offset with data_page_index page.
 927                  * page_length = bytes to copy for this page
 928                  */
 929                 shmem_page_index = offset / PAGE_SIZE;
 930                 shmem_page_offset = offset & ~PAGE_MASK;
 931                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 932                 data_page_offset = data_ptr & ~PAGE_MASK;
 933
 934                 page_length = remain;
 935                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 936                         page_length = PAGE_SIZE - shmem_page_offset;
 937                 if ((data_page_offset + page_length) > PAGE_SIZE)
 938                         page_length = PAGE_SIZE - data_page_offset;
 939
 940                 if (do_bit17_swizzling) {
 941                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 942                                               shmem_page_offset,
 943                                               user_pages[data_page_index],
 944                                               data_page_offset,
 945                                               page_length,
 946                                               0);
 947                 } else {
 948                         slow_shmem_copy(obj_priv->pages[shmem_page_index],
 949                                         shmem_page_offset,
 950                                         user_pages[data_page_index],
 951                                         data_page_offset,
 952                                         page_length);
 953                 }
 954
 955                 remain -= page_length;
 956                 data_ptr += page_length;
 957                 offset += page_length;
 958         }
 959
 960 out:
 961         for (i = 0; i < pinned_pages; i++)
 962                 page_cache_release(user_pages[i]);
 963         drm_free_large(user_pages);
 964
 965         return ret;
 966 }
 967
 968 /**
 969  * Writes data to the object referenced by handle.
 970  *
 971  * On error, the contents of the buffer that were to be modified are undefined.
 972  */
 973 int
 974 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 975                       struct drm_file *file)
 976 {
 977         struct drm_i915_gem_pwrite *args = data;
 978         struct drm_gem_object *obj;
 979         struct drm_i915_gem_object *obj_priv;
 980         int ret;
 981
 982         if (args->size == 0)
 983                 return 0;
 984
 985         if (!access_ok(VERIFY_READ,
 986                        (char __user *)(uintptr_t)args->data_ptr,
 987                        args->size))
 988                 return -EFAULT;
 989
 990         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
 991                                       args->size);
 992         if (ret)
 993                 return -EFAULT;
 994
 995         ret = i915_mutex_lock_interruptible(dev);
 996         if (ret)
 997                 return ret;
 998
 999         obj = drm_gem_object_lookup(dev, file, args->handle);
1000         if (obj == NULL) {
1001                 ret = -ENOENT;
1002                 goto unlock;
1003         }
1004         obj_priv = to_intel_bo(obj);
1005
1006         /* Bounds check destination. */
1007         if (args->offset > obj->size || args->size > obj->size - args->offset) {
1008                 ret = -EINVAL;
1009                 goto out;
1010         }
1011
1012         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1013          * it would end up going through the fenced access, and we'll get
1014          * different detiling behavior between reading and writing.
1015          * pread/pwrite currently are reading and writing from the CPU
1016          * perspective, requiring manual detiling by the client.
1017          */
1018         if (obj_priv->phys_obj)
1019                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
1020         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
1021                  obj_priv->gtt_space &&
1022                  obj->write_domain != I915_GEM_DOMAIN_CPU) {
1023                 ret = i915_gem_object_pin(obj, 0);
1024                 if (ret)
1025                         goto out;
1026
1027                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1028                 if (ret)
1029                         goto out_unpin;
1030
1031                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1032                 if (ret == -EFAULT)
1033                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1034
1035 out_unpin:
1036                 i915_gem_object_unpin(obj);
1037         } else {
1038                 ret = i915_gem_object_get_pages_or_evict(obj);
1039                 if (ret)
1040                         goto out;
1041
1042                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1043                 if (ret)
1044                         goto out_put;
1045
1046                 ret = -EFAULT;
1047                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1048                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1049                 if (ret == -EFAULT)
1050                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1051
1052 out_put:
1053                 i915_gem_object_put_pages(obj);
1054         }
1055
1056 out:
1057         drm_gem_object_unreference(obj);
1058 unlock:
1059         mutex_unlock(&dev->struct_mutex);
1060         return ret;
1061 }
1062
1063 /**
1064  * Called when user space prepares to use an object with the CPU, either
1065  * through the mmap ioctl's mapping or a GTT mapping.
1066  */
1067 int
1068 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1069                           struct drm_file *file_priv)
1070 {
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072         struct drm_i915_gem_set_domain *args = data;
1073         struct drm_gem_object *obj;
1074         struct drm_i915_gem_object *obj_priv;
1075         uint32_t read_domains = args->read_domains;
1076         uint32_t write_domain = args->write_domain;
1077         int ret;
1078
1079         if (!(dev->driver->driver_features & DRIVER_GEM))
1080                 return -ENODEV;
1081
1082         /* Only handle setting domains to types used by the CPU. */
1083         if (write_domain & I915_GEM_GPU_DOMAINS)
1084                 return -EINVAL;
1085
1086         if (read_domains & I915_GEM_GPU_DOMAINS)
1087                 return -EINVAL;
1088
1089         /* Having something in the write domain implies it's in the read
1090          * domain, and only that read domain.  Enforce that in the request.
1091          */
1092         if (write_domain != 0 && read_domains != write_domain)
1093                 return -EINVAL;
1094
1095         ret = i915_mutex_lock_interruptible(dev);
1096         if (ret)
1097                 return ret;
1098
1099         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1100         if (obj == NULL) {
1101                 ret = -ENOENT;
1102                 goto unlock;
1103         }
1104         obj_priv = to_intel_bo(obj);
1105
1106         intel_mark_busy(dev, obj);
1107
1108         if (read_domains & I915_GEM_DOMAIN_GTT) {
1109                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1110
1111                 /* Update the LRU on the fence for the CPU access that's
1112                  * about to occur.
1113                  */
1114                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1115                         struct drm_i915_fence_reg *reg =
1116                                 &dev_priv->fence_regs[obj_priv->fence_reg];
1117                         list_move_tail(&reg->lru_list,
1118                                        &dev_priv->mm.fence_list);
1119                 }
1120
1121                 /* Silently promote "you're not bound, there was nothing to do"
1122                  * to success, since the client was just asking us to
1123                  * make sure everything was done.
1124                  */
1125                 if (ret == -EINVAL)
1126                         ret = 0;
1127         } else {
1128                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1129         }
1130
1131         /* Maintain LRU order of "inactive" objects */
1132         if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1133                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1134
1135         drm_gem_object_unreference(obj);
1136 unlock:
1137         mutex_unlock(&dev->struct_mutex);
1138         return ret;
1139 }
1140
1141 /**
1142  * Called when user space has done writes to this buffer
1143  */
1144 int
1145 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1146                       struct drm_file *file_priv)
1147 {
1148         struct drm_i915_gem_sw_finish *args = data;
1149         struct drm_gem_object *obj;
1150         int ret = 0;
1151
1152         if (!(dev->driver->driver_features & DRIVER_GEM))
1153                 return -ENODEV;
1154
1155         ret = i915_mutex_lock_interruptible(dev);
1156         if (ret)
1157                 return ret;
1158
1159         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1160         if (obj == NULL) {
1161                 ret = -ENOENT;
1162                 goto unlock;
1163         }
1164
1165         /* Pinned buffers may be scanout, so flush the cache */
1166         if (to_intel_bo(obj)->pin_count)
1167                 i915_gem_object_flush_cpu_write_domain(obj);
1168
1169         drm_gem_object_unreference(obj);
1170 unlock:
1171         mutex_unlock(&dev->struct_mutex);
1172         return ret;
1173 }
1174
1175 /**
1176  * Maps the contents of an object, returning the address it is mapped
1177  * into.
1178  *
1179  * While the mapping holds a reference on the contents of the object, it doesn't
1180  * imply a ref on the object itself.
1181  */
1182 int
1183 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1184                    struct drm_file *file_priv)
1185 {
1186         struct drm_i915_gem_mmap *args = data;
1187         struct drm_gem_object *obj;
1188         loff_t offset;
1189         unsigned long addr;
1190
1191         if (!(dev->driver->driver_features & DRIVER_GEM))
1192                 return -ENODEV;
1193
1194         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1195         if (obj == NULL)
1196                 return -ENOENT;
1197
1198         offset = args->offset;
1199
1200         down_write(&current->mm->mmap_sem);
1201         addr = do_mmap(obj->filp, 0, args->size,
1202                        PROT_READ | PROT_WRITE, MAP_SHARED,
1203                        args->offset);
1204         up_write(&current->mm->mmap_sem);
1205         drm_gem_object_unreference_unlocked(obj);
1206         if (IS_ERR((void *)addr))
1207                 return addr;
1208
1209         args->addr_ptr = (uint64_t) addr;
1210
1211         return 0;
1212 }
1213
1214 /**
1215  * i915_gem_fault - fault a page into the GTT
1216  * vma: VMA in question
1217  * vmf: fault info
1218  *
1219  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1220  * from userspace.  The fault handler takes care of binding the object to
1221  * the GTT (if needed), allocating and programming a fence register (again,
1222  * only if needed based on whether the old reg is still valid or the object
1223  * is tiled) and inserting a new PTE into the faulting process.
1224  *
1225  * Note that the faulting process may involve evicting existing objects
1226  * from the GTT and/or fence registers to make room.  So performance may
1227  * suffer if the GTT working set is large or there are few fence registers
1228  * left.
1229  */
1230 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1231 {
1232         struct drm_gem_object *obj = vma->vm_private_data;
1233         struct drm_device *dev = obj->dev;
1234         drm_i915_private_t *dev_priv = dev->dev_private;
1235         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1236         pgoff_t page_offset;
1237         unsigned long pfn;
1238         int ret = 0;
1239         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1240
1241         /* We don't use vmf->pgoff since that has the fake offset */
1242         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1243                 PAGE_SHIFT;
1244
1245         /* Now bind it into the GTT if needed */
1246         mutex_lock(&dev->struct_mutex);
1247         if (!obj_priv->gtt_space) {
1248                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1249                 if (ret)
1250                         goto unlock;
1251
1252                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1253                 if (ret)
1254                         goto unlock;
1255         }
1256
1257         /* Need a new fence register? */
1258         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1259                 ret = i915_gem_object_get_fence_reg(obj, true);
1260                 if (ret)
1261                         goto unlock;
1262         }
1263
1264         if (i915_gem_object_is_inactive(obj_priv))
1265                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1266
1267         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1268                 page_offset;
1269
1270         /* Finally, remap it using the new GTT offset */
1271         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1272 unlock:
1273         mutex_unlock(&dev->struct_mutex);
1274
1275         switch (ret) {
1276         case 0:
1277         case -ERESTARTSYS:
1278                 return VM_FAULT_NOPAGE;
1279         case -ENOMEM:
1280         case -EAGAIN:
1281                 return VM_FAULT_OOM;
1282         default:
1283                 return VM_FAULT_SIGBUS;
1284         }
1285 }
1286
1287 /**
1288  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1289  * @obj: obj in question
1290  *
1291  * GEM memory mapping works by handing back to userspace a fake mmap offset
1292  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1293  * up the object based on the offset and sets up the various memory mapping
1294  * structures.
1295  *
1296  * This routine allocates and attaches a fake offset for @obj.
1297  */
1298 static int
1299 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1300 {
1301         struct drm_device *dev = obj->dev;
1302         struct drm_gem_mm *mm = dev->mm_private;
1303         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1304         struct drm_map_list *list;
1305         struct drm_local_map *map;
1306         int ret = 0;
1307
1308         /* Set the object up for mmap'ing */
1309         list = &obj->map_list;
1310         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1311         if (!list->map)
1312                 return -ENOMEM;
1313
1314         map = list->map;
1315         map->type = _DRM_GEM;
1316         map->size = obj->size;
1317         map->handle = obj;
1318
1319         /* Get a DRM GEM mmap offset allocated... */
1320         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1321                                                     obj->size / PAGE_SIZE, 0, 0);
1322         if (!list->file_offset_node) {
1323                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1324                 ret = -ENOSPC;
1325                 goto out_free_list;
1326         }
1327
1328         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1329                                                   obj->size / PAGE_SIZE, 0);
1330         if (!list->file_offset_node) {
1331                 ret = -ENOMEM;
1332                 goto out_free_list;
1333         }
1334
1335         list->hash.key = list->file_offset_node->start;
1336         ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1337         if (ret) {
1338                 DRM_ERROR("failed to add to map hash\n");
1339                 goto out_free_mm;
1340         }
1341
1342         /* By now we should be all set, any drm_mmap request on the offset
1343          * below will get to our mmap & fault handler */
1344         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1345
1346         return 0;
1347
1348 out_free_mm:
1349         drm_mm_put_block(list->file_offset_node);
1350 out_free_list:
1351         kfree(list->map);
1352
1353         return ret;
1354 }
1355
1356 /**
1357  * i915_gem_release_mmap - remove physical page mappings
1358  * @obj: obj in question
1359  *
1360  * Preserve the reservation of the mmapping with the DRM core code, but
1361  * relinquish ownership of the pages back to the system.
1362  *
1363  * It is vital that we remove the page mapping if we have mapped a tiled
1364  * object through the GTT and then lose the fence register due to
1365  * resource pressure. Similarly if the object has been moved out of the
1366  * aperture, than pages mapped into userspace must be revoked. Removing the
1367  * mapping will then trigger a page fault on the next user access, allowing
1368  * fixup by i915_gem_fault().
1369  */
1370 void
1371 i915_gem_release_mmap(struct drm_gem_object *obj)
1372 {
1373         struct drm_device *dev = obj->dev;
1374         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1375
1376         if (dev->dev_mapping)
1377                 unmap_mapping_range(dev->dev_mapping,
1378                                     obj_priv->mmap_offset, obj->size, 1);
1379 }
1380
1381 static void
1382 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1383 {
1384         struct drm_device *dev = obj->dev;
1385         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1386         struct drm_gem_mm *mm = dev->mm_private;
1387         struct drm_map_list *list;
1388
1389         list = &obj->map_list;
1390         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1391
1392         if (list->file_offset_node) {
1393                 drm_mm_put_block(list->file_offset_node);
1394                 list->file_offset_node = NULL;
1395         }
1396
1397         if (list->map) {
1398                 kfree(list->map);
1399                 list->map = NULL;
1400         }
1401
1402         obj_priv->mmap_offset = 0;
1403 }
1404
1405 /**
1406  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1407  * @obj: object to check
1408  *
1409  * Return the required GTT alignment for an object, taking into account
1410  * potential fence register mapping if needed.
1411  */
1412 static uint32_t
1413 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1414 {
1415         struct drm_device *dev = obj->dev;
1416         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1417         int start, i;
1418
1419         /*
1420          * Minimum alignment is 4k (GTT page size), but might be greater
1421          * if a fence register is needed for the object.
1422          */
1423         if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE)
1424                 return 4096;
1425
1426         /*
1427          * Previous chips need to be aligned to the size of the smallest
1428          * fence register that can contain the object.
1429          */
1430         if (INTEL_INFO(dev)->gen == 3)
1431                 start = 1024*1024;
1432         else
1433                 start = 512*1024;
1434
1435         for (i = start; i < obj->size; i <<= 1)
1436                 ;
1437
1438         return i;
1439 }
1440
1441 /**
1442  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1443  * @dev: DRM device
1444  * @data: GTT mapping ioctl data
1445  * @file_priv: GEM object info
1446  *
1447  * Simply returns the fake offset to userspace so it can mmap it.
1448  * The mmap call will end up in drm_gem_mmap(), which will set things
1449  * up so we can get faults in the handler above.
1450  *
1451  * The fault handler will take care of binding the object into the GTT
1452  * (since it may have been evicted to make room for something), allocating
1453  * a fence register, and mapping the appropriate aperture address into
1454  * userspace.
1455  */
1456 int
1457 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1458                         struct drm_file *file_priv)
1459 {
1460         struct drm_i915_gem_mmap_gtt *args = data;
1461         struct drm_gem_object *obj;
1462         struct drm_i915_gem_object *obj_priv;
1463         int ret;
1464
1465         if (!(dev->driver->driver_features & DRIVER_GEM))
1466                 return -ENODEV;
1467
1468         ret = i915_mutex_lock_interruptible(dev);
1469         if (ret)
1470                 return ret;
1471
1472         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1473         if (obj == NULL) {
1474                 ret = -ENOENT;
1475                 goto unlock;
1476         }
1477         obj_priv = to_intel_bo(obj);
1478
1479         if (obj_priv->madv != I915_MADV_WILLNEED) {
1480                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1481                 ret = -EINVAL;
1482                 goto out;
1483         }
1484
1485         if (!obj_priv->mmap_offset) {
1486                 ret = i915_gem_create_mmap_offset(obj);
1487                 if (ret)
1488                         goto out;
1489         }
1490
1491         args->offset = obj_priv->mmap_offset;
1492
1493         /*
1494          * Pull it into the GTT so that we have a page list (makes the
1495          * initial fault faster and any subsequent flushing possible).
1496          */
1497         if (!obj_priv->agp_mem) {
1498                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1499                 if (ret)
1500                         goto out;
1501         }
1502
1503 out:
1504         drm_gem_object_unreference(obj);
1505 unlock:
1506         mutex_unlock(&dev->struct_mutex);
1507         return ret;
1508 }
1509
1510 static void
1511 i915_gem_object_put_pages(struct drm_gem_object *obj)
1512 {
1513         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1514         int page_count = obj->size / PAGE_SIZE;
1515         int i;
1516
1517         BUG_ON(obj_priv->pages_refcount == 0);
1518         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1519
1520         if (--obj_priv->pages_refcount != 0)
1521                 return;
1522
1523         if (obj_priv->tiling_mode != I915_TILING_NONE)
1524                 i915_gem_object_save_bit_17_swizzle(obj);
1525
1526         if (obj_priv->madv == I915_MADV_DONTNEED)
1527                 obj_priv->dirty = 0;
1528
1529         for (i = 0; i < page_count; i++) {
1530                 if (obj_priv->dirty)
1531                         set_page_dirty(obj_priv->pages[i]);
1532
1533                 if (obj_priv->madv == I915_MADV_WILLNEED)
1534                         mark_page_accessed(obj_priv->pages[i]);
1535
1536                 page_cache_release(obj_priv->pages[i]);
1537         }
1538         obj_priv->dirty = 0;
1539
1540         drm_free_large(obj_priv->pages);
1541         obj_priv->pages = NULL;
1542 }
1543
1544 static uint32_t
1545 i915_gem_next_request_seqno(struct drm_device *dev,
1546                             struct intel_ring_buffer *ring)
1547 {
1548         drm_i915_private_t *dev_priv = dev->dev_private;
1549
1550         ring->outstanding_lazy_request = true;
1551         return dev_priv->next_seqno;
1552 }
1553
1554 static void
1555 i915_gem_object_move_to_active(struct drm_gem_object *obj,
1556                                struct intel_ring_buffer *ring)
1557 {
1558         struct drm_device *dev = obj->dev;
1559         struct drm_i915_private *dev_priv = dev->dev_private;
1560         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1561         uint32_t seqno = i915_gem_next_request_seqno(dev, ring);
1562
1563         BUG_ON(ring == NULL);
1564         obj_priv->ring = ring;
1565
1566         /* Add a reference if we're newly entering the active list. */
1567         if (!obj_priv->active) {
1568                 drm_gem_object_reference(obj);
1569                 obj_priv->active = 1;
1570         }
1571
1572         /* Move from whatever list we were on to the tail of execution. */
1573         list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list);
1574         list_move_tail(&obj_priv->ring_list, &ring->active_list);
1575         obj_priv->last_rendering_seqno = seqno;
1576 }
1577
1578 static void
1579 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1580 {
1581         struct drm_device *dev = obj->dev;
1582         drm_i915_private_t *dev_priv = dev->dev_private;
1583         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1584
1585         BUG_ON(!obj_priv->active);
1586         list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list);
1587         list_del_init(&obj_priv->ring_list);
1588         obj_priv->last_rendering_seqno = 0;
1589 }
1590
1591 /* Immediately discard the backing storage */
1592 static void
1593 i915_gem_object_truncate(struct drm_gem_object *obj)
1594 {
1595         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1596         struct inode *inode;
1597
1598         /* Our goal here is to return as much of the memory as
1599          * is possible back to the system as we are called from OOM.
1600          * To do this we must instruct the shmfs to drop all of its
1601          * backing pages, *now*. Here we mirror the actions taken
1602          * when by shmem_delete_inode() to release the backing store.
1603          */
1604         inode = obj->filp->f_path.dentry->d_inode;
1605         truncate_inode_pages(inode->i_mapping, 0);
1606         if (inode->i_op->truncate_range)
1607                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1608
1609         obj_priv->madv = __I915_MADV_PURGED;
1610 }
1611
1612 static inline int
1613 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1614 {
1615         return obj_priv->madv == I915_MADV_DONTNEED;
1616 }
1617
1618 static void
1619 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1620 {
1621         struct drm_device *dev = obj->dev;
1622         drm_i915_private_t *dev_priv = dev->dev_private;
1623         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1624
1625         if (obj_priv->pin_count != 0)
1626                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list);
1627         else
1628                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1629         list_del_init(&obj_priv->ring_list);
1630
1631         BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1632
1633         obj_priv->last_rendering_seqno = 0;
1634         obj_priv->ring = NULL;
1635         if (obj_priv->active) {
1636                 obj_priv->active = 0;
1637                 drm_gem_object_unreference(obj);
1638         }
1639         WARN_ON(i915_verify_lists(dev));
1640 }
1641
1642 static void
1643 i915_gem_process_flushing_list(struct drm_device *dev,
1644                                uint32_t flush_domains,
1645                                struct intel_ring_buffer *ring)
1646 {
1647         drm_i915_private_t *dev_priv = dev->dev_private;
1648         struct drm_i915_gem_object *obj_priv, *next;
1649
1650         list_for_each_entry_safe(obj_priv, next,
1651                                  &ring->gpu_write_list,
1652                                  gpu_write_list) {
1653                 struct drm_gem_object *obj = &obj_priv->base;
1654
1655                 if (obj->write_domain & flush_domains) {
1656                         uint32_t old_write_domain = obj->write_domain;
1657
1658                         obj->write_domain = 0;
1659                         list_del_init(&obj_priv->gpu_write_list);
1660                         i915_gem_object_move_to_active(obj, ring);
1661
1662                         /* update the fence lru list */
1663                         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1664                                 struct drm_i915_fence_reg *reg =
1665                                         &dev_priv->fence_regs[obj_priv->fence_reg];
1666                                 list_move_tail(&reg->lru_list,
1667                                                 &dev_priv->mm.fence_list);
1668                         }
1669
1670                         trace_i915_gem_object_change_domain(obj,
1671                                                             obj->read_domains,
1672                                                             old_write_domain);
1673                 }
1674         }
1675 }
1676
1677 uint32_t
1678 i915_add_request(struct drm_device *dev,
1679                  struct drm_file *file,
1680                  struct drm_i915_gem_request *request,
1681                  struct intel_ring_buffer *ring)
1682 {
1683         drm_i915_private_t *dev_priv = dev->dev_private;
1684         struct drm_i915_file_private *file_priv = NULL;
1685         uint32_t seqno;
1686         int was_empty;
1687
1688         if (file != NULL)
1689                 file_priv = file->driver_priv;
1690
1691         if (request == NULL) {
1692                 request = kzalloc(sizeof(*request), GFP_KERNEL);
1693                 if (request == NULL)
1694                         return 0;
1695         }
1696
1697         seqno = ring->add_request(dev, ring, 0);
1698         ring->outstanding_lazy_request = false;
1699
1700         request->seqno = seqno;
1701         request->ring = ring;
1702         request->emitted_jiffies = jiffies;
1703         was_empty = list_empty(&ring->request_list);
1704         list_add_tail(&request->list, &ring->request_list);
1705
1706         if (file_priv) {
1707                 spin_lock(&file_priv->mm.lock);
1708                 request->file_priv = file_priv;
1709                 list_add_tail(&request->client_list,
1710                               &file_priv->mm.request_list);
1711                 spin_unlock(&file_priv->mm.lock);
1712         }
1713
1714         if (!dev_priv->mm.suspended) {
1715                 mod_timer(&dev_priv->hangcheck_timer,
1716                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1717                 if (was_empty)
1718                         queue_delayed_work(dev_priv->wq,
1719                                            &dev_priv->mm.retire_work, HZ);
1720         }
1721         return seqno;
1722 }
1723
1724 /**
1725  * Command execution barrier
1726  *
1727  * Ensures that all commands in the ring are finished
1728  * before signalling the CPU
1729  */
1730 static void
1731 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1732 {
1733         uint32_t flush_domains = 0;
1734
1735         /* The sampler always gets flushed on i965 (sigh) */
1736         if (INTEL_INFO(dev)->gen >= 4)
1737                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1738
1739         ring->flush(dev, ring,
1740                         I915_GEM_DOMAIN_COMMAND, flush_domains);
1741 }
1742
1743 static inline void
1744 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1745 {
1746         struct drm_i915_file_private *file_priv = request->file_priv;
1747
1748         if (!file_priv)
1749                 return;
1750
1751         spin_lock(&file_priv->mm.lock);
1752         list_del(&request->client_list);
1753         request->file_priv = NULL;
1754         spin_unlock(&file_priv->mm.lock);
1755 }
1756
1757 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1758                                       struct intel_ring_buffer *ring)
1759 {
1760         while (!list_empty(&ring->request_list)) {
1761                 struct drm_i915_gem_request *request;
1762
1763                 request = list_first_entry(&ring->request_list,
1764                                            struct drm_i915_gem_request,
1765                                            list);
1766
1767                 list_del(&request->list);
1768                 i915_gem_request_remove_from_client(request);
1769                 kfree(request);
1770         }
1771
1772         while (!list_empty(&ring->active_list)) {
1773                 struct drm_i915_gem_object *obj_priv;
1774
1775                 obj_priv = list_first_entry(&ring->active_list,
1776                                             struct drm_i915_gem_object,
1777                                             ring_list);
1778
1779                 obj_priv->base.write_domain = 0;
1780                 list_del_init(&obj_priv->gpu_write_list);
1781                 i915_gem_object_move_to_inactive(&obj_priv->base);
1782         }
1783 }
1784
1785 void i915_gem_reset(struct drm_device *dev)
1786 {
1787         struct drm_i915_private *dev_priv = dev->dev_private;
1788         struct drm_i915_gem_object *obj_priv;
1789         int i;
1790
1791         i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring);
1792         i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring);
1793         i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring);
1794
1795         /* Remove anything from the flushing lists. The GPU cache is likely
1796          * to be lost on reset along with the data, so simply move the
1797          * lost bo to the inactive list.
1798          */
1799         while (!list_empty(&dev_priv->mm.flushing_list)) {
1800                 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1801                                             struct drm_i915_gem_object,
1802                                             mm_list);
1803
1804                 obj_priv->base.write_domain = 0;
1805                 list_del_init(&obj_priv->gpu_write_list);
1806                 i915_gem_object_move_to_inactive(&obj_priv->base);
1807         }
1808
1809         /* Move everything out of the GPU domains to ensure we do any
1810          * necessary invalidation upon reuse.
1811          */
1812         list_for_each_entry(obj_priv,
1813                             &dev_priv->mm.inactive_list,
1814                             mm_list)
1815         {
1816                 obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1817         }
1818
1819         /* The fence registers are invalidated so clear them out */
1820         for (i = 0; i < 16; i++) {
1821                 struct drm_i915_fence_reg *reg;
1822
1823                 reg = &dev_priv->fence_regs[i];
1824                 if (!reg->obj)
1825                         continue;
1826
1827                 i915_gem_clear_fence_reg(reg->obj);
1828         }
1829 }
1830
1831 /**
1832  * This function clears the request list as sequence numbers are passed.
1833  */
1834 static void
1835 i915_gem_retire_requests_ring(struct drm_device *dev,
1836                               struct intel_ring_buffer *ring)
1837 {
1838         drm_i915_private_t *dev_priv = dev->dev_private;
1839         uint32_t seqno;
1840
1841         if (!ring->status_page.page_addr ||
1842             list_empty(&ring->request_list))
1843                 return;
1844
1845         WARN_ON(i915_verify_lists(dev));
1846
1847         seqno = ring->get_seqno(dev, ring);
1848         while (!list_empty(&ring->request_list)) {
1849                 struct drm_i915_gem_request *request;
1850
1851                 request = list_first_entry(&ring->request_list,
1852                                            struct drm_i915_gem_request,
1853                                            list);
1854
1855                 if (!i915_seqno_passed(seqno, request->seqno))
1856                         break;
1857
1858                 trace_i915_gem_request_retire(dev, request->seqno);
1859
1860                 list_del(&request->list);
1861                 i915_gem_request_remove_from_client(request);
1862                 kfree(request);
1863         }
1864
1865         /* Move any buffers on the active list that are no longer referenced
1866          * by the ringbuffer to the flushing/inactive lists as appropriate.
1867          */
1868         while (!list_empty(&ring->active_list)) {
1869                 struct drm_gem_object *obj;
1870                 struct drm_i915_gem_object *obj_priv;
1871
1872                 obj_priv = list_first_entry(&ring->active_list,
1873                                             struct drm_i915_gem_object,
1874                                             ring_list);
1875
1876                 if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno))
1877                         break;
1878
1879                 obj = &obj_priv->base;
1880                 if (obj->write_domain != 0)
1881                         i915_gem_object_move_to_flushing(obj);
1882                 else
1883                         i915_gem_object_move_to_inactive(obj);
1884         }
1885
1886         if (unlikely (dev_priv->trace_irq_seqno &&
1887                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1888                 ring->user_irq_put(dev, ring);
1889                 dev_priv->trace_irq_seqno = 0;
1890         }
1891
1892         WARN_ON(i915_verify_lists(dev));
1893 }
1894
1895 void
1896 i915_gem_retire_requests(struct drm_device *dev)
1897 {
1898         drm_i915_private_t *dev_priv = dev->dev_private;
1899
1900         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1901             struct drm_i915_gem_object *obj_priv, *tmp;
1902
1903             /* We must be careful that during unbind() we do not
1904              * accidentally infinitely recurse into retire requests.
1905              * Currently:
1906              *   retire -> free -> unbind -> wait -> retire_ring
1907              */
1908             list_for_each_entry_safe(obj_priv, tmp,
1909                                      &dev_priv->mm.deferred_free_list,
1910                                      mm_list)
1911                     i915_gem_free_object_tail(&obj_priv->base);
1912         }
1913
1914         i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1915         i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1916         i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring);
1917 }
1918
1919 static void
1920 i915_gem_retire_work_handler(struct work_struct *work)
1921 {
1922         drm_i915_private_t *dev_priv;
1923         struct drm_device *dev;
1924
1925         dev_priv = container_of(work, drm_i915_private_t,
1926                                 mm.retire_work.work);
1927         dev = dev_priv->dev;
1928
1929         /* Come back later if the device is busy... */
1930         if (!mutex_trylock(&dev->struct_mutex)) {
1931                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1932                 return;
1933         }
1934
1935         i915_gem_retire_requests(dev);
1936
1937         if (!dev_priv->mm.suspended &&
1938                 (!list_empty(&dev_priv->render_ring.request_list) ||
1939                  !list_empty(&dev_priv->bsd_ring.request_list) ||
1940                  !list_empty(&dev_priv->blt_ring.request_list)))
1941                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1942         mutex_unlock(&dev->struct_mutex);
1943 }
1944
1945 int
1946 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1947                      bool interruptible, struct intel_ring_buffer *ring)
1948 {
1949         drm_i915_private_t *dev_priv = dev->dev_private;
1950         u32 ier;
1951         int ret = 0;
1952
1953         BUG_ON(seqno == 0);
1954
1955         if (atomic_read(&dev_priv->mm.wedged))
1956                 return -EAGAIN;
1957
1958         if (ring->outstanding_lazy_request) {
1959                 seqno = i915_add_request(dev, NULL, NULL, ring);
1960                 if (seqno == 0)
1961                         return -ENOMEM;
1962         }
1963         BUG_ON(seqno == dev_priv->next_seqno);
1964
1965         if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) {
1966                 if (HAS_PCH_SPLIT(dev))
1967                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1968                 else
1969                         ier = I915_READ(IER);
1970                 if (!ier) {
1971                         DRM_ERROR("something (likely vbetool) disabled "
1972                                   "interrupts, re-enabling\n");
1973                         i915_driver_irq_preinstall(dev);
1974                         i915_driver_irq_postinstall(dev);
1975                 }
1976
1977                 trace_i915_gem_request_wait_begin(dev, seqno);
1978
1979                 ring->waiting_gem_seqno = seqno;
1980                 ring->user_irq_get(dev, ring);
1981                 if (interruptible)
1982                         ret = wait_event_interruptible(ring->irq_queue,
1983                                 i915_seqno_passed(
1984                                         ring->get_seqno(dev, ring), seqno)
1985                                 || atomic_read(&dev_priv->mm.wedged));
1986                 else
1987                         wait_event(ring->irq_queue,
1988                                 i915_seqno_passed(
1989                                         ring->get_seqno(dev, ring), seqno)
1990                                 || atomic_read(&dev_priv->mm.wedged));
1991
1992                 ring->user_irq_put(dev, ring);
1993                 ring->waiting_gem_seqno = 0;
1994
1995                 trace_i915_gem_request_wait_end(dev, seqno);
1996         }
1997         if (atomic_read(&dev_priv->mm.wedged))
1998                 ret = -EAGAIN;
1999
2000         if (ret && ret != -ERESTARTSYS)
2001                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2002                           __func__, ret, seqno, ring->get_seqno(dev, ring),
2003                           dev_priv->next_seqno);
2004
2005         /* Directly dispatch request retiring.  While we have the work queue
2006          * to handle this, the waiter on a request often wants an associated
2007          * buffer to have made it to the inactive list, and we would need
2008          * a separate wait queue to handle that.
2009          */
2010         if (ret == 0)
2011                 i915_gem_retire_requests_ring(dev, ring);
2012
2013         return ret;
2014 }
2015
2016 /**
2017  * Waits for a sequence number to be signaled, and cleans up the
2018  * request and object lists appropriately for that event.
2019  */
2020 static int
2021 i915_wait_request(struct drm_device *dev, uint32_t seqno,
2022                   struct intel_ring_buffer *ring)
2023 {
2024         return i915_do_wait_request(dev, seqno, 1, ring);
2025 }
2026
2027 static void
2028 i915_gem_flush_ring(struct drm_device *dev,
2029                     struct drm_file *file_priv,
2030                     struct intel_ring_buffer *ring,
2031                     uint32_t invalidate_domains,
2032                     uint32_t flush_domains)
2033 {
2034         ring->flush(dev, ring, invalidate_domains, flush_domains);
2035         i915_gem_process_flushing_list(dev, flush_domains, ring);
2036 }
2037
2038 static void
2039 i915_gem_flush(struct drm_device *dev,
2040                struct drm_file *file_priv,
2041                uint32_t invalidate_domains,
2042                uint32_t flush_domains,
2043                uint32_t flush_rings)
2044 {
2045         drm_i915_private_t *dev_priv = dev->dev_private;
2046
2047         if (flush_domains & I915_GEM_DOMAIN_CPU)
2048                 drm_agp_chipset_flush(dev);
2049
2050         if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
2051                 if (flush_rings & RING_RENDER)
2052                         i915_gem_flush_ring(dev, file_priv,
2053                                             &dev_priv->render_ring,
2054                                             invalidate_domains, flush_domains);
2055                 if (flush_rings & RING_BSD)
2056                         i915_gem_flush_ring(dev, file_priv,
2057                                             &dev_priv->bsd_ring,
2058                                             invalidate_domains, flush_domains);
2059                 if (flush_rings & RING_BLT)
2060                         i915_gem_flush_ring(dev, file_priv,
2061                                             &dev_priv->blt_ring,
2062                                             invalidate_domains, flush_domains);
2063         }
2064 }
2065
2066 /**
2067  * Ensures that all rendering to the object has completed and the object is
2068  * safe to unbind from the GTT or access from the CPU.
2069  */
2070 static int
2071 i915_gem_object_wait_rendering(struct drm_gem_object *obj,
2072                                bool interruptible)
2073 {
2074         struct drm_device *dev = obj->dev;
2075         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2076         int ret;
2077
2078         /* This function only exists to support waiting for existing rendering,
2079          * not for emitting required flushes.
2080          */
2081         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
2082
2083         /* If there is rendering queued on the buffer being evicted, wait for
2084          * it.
2085          */
2086         if (obj_priv->active) {
2087                 ret = i915_do_wait_request(dev,
2088                                            obj_priv->last_rendering_seqno,
2089                                            interruptible,
2090                                            obj_priv->ring);
2091                 if (ret)
2092                         return ret;
2093         }
2094
2095         return 0;
2096 }
2097
2098 /**
2099  * Unbinds an object from the GTT aperture.
2100  */
2101 int
2102 i915_gem_object_unbind(struct drm_gem_object *obj)
2103 {
2104         struct drm_device *dev = obj->dev;
2105         struct drm_i915_private *dev_priv = dev->dev_private;
2106         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2107         int ret = 0;
2108
2109         if (obj_priv->gtt_space == NULL)
2110                 return 0;
2111
2112         if (obj_priv->pin_count != 0) {
2113                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2114                 return -EINVAL;
2115         }
2116
2117         /* blow away mappings if mapped through GTT */
2118         i915_gem_release_mmap(obj);
2119
2120         /* Move the object to the CPU domain to ensure that
2121          * any possible CPU writes while it's not in the GTT
2122          * are flushed when we go to remap it. This will
2123          * also ensure that all pending GPU writes are finished
2124          * before we unbind.
2125          */
2126         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2127         if (ret == -ERESTARTSYS)
2128                 return ret;
2129         /* Continue on if we fail due to EIO, the GPU is hung so we
2130          * should be safe and we need to cleanup or else we might
2131          * cause memory corruption through use-after-free.
2132          */
2133         if (ret) {
2134                 i915_gem_clflush_object(obj);
2135                 obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU;
2136         }
2137
2138         /* release the fence reg _after_ flushing */
2139         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2140                 i915_gem_clear_fence_reg(obj);
2141
2142         drm_unbind_agp(obj_priv->agp_mem);
2143         drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2144
2145         i915_gem_object_put_pages(obj);
2146         BUG_ON(obj_priv->pages_refcount);
2147
2148         i915_gem_info_remove_gtt(dev_priv, obj->size);
2149         list_del_init(&obj_priv->mm_list);
2150
2151         drm_mm_put_block(obj_priv->gtt_space);
2152         obj_priv->gtt_space = NULL;
2153         obj_priv->gtt_offset = 0;
2154
2155         if (i915_gem_object_is_purgeable(obj_priv))
2156                 i915_gem_object_truncate(obj);
2157
2158         trace_i915_gem_object_unbind(obj);
2159
2160         return ret;
2161 }
2162
2163 static int i915_ring_idle(struct drm_device *dev,
2164                           struct intel_ring_buffer *ring)
2165 {
2166         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2167                 return 0;
2168
2169         i915_gem_flush_ring(dev, NULL, ring,
2170                             I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2171         return i915_wait_request(dev,
2172                                  i915_gem_next_request_seqno(dev, ring),
2173                                  ring);
2174 }
2175
2176 int
2177 i915_gpu_idle(struct drm_device *dev)
2178 {
2179         drm_i915_private_t *dev_priv = dev->dev_private;
2180         bool lists_empty;
2181         int ret;
2182
2183         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2184                        list_empty(&dev_priv->mm.active_list));
2185         if (lists_empty)
2186                 return 0;
2187
2188         /* Flush everything onto the inactive list. */
2189         ret = i915_ring_idle(dev, &dev_priv->render_ring);
2190         if (ret)
2191                 return ret;
2192
2193         ret = i915_ring_idle(dev, &dev_priv->bsd_ring);
2194         if (ret)
2195                 return ret;
2196
2197         ret = i915_ring_idle(dev, &dev_priv->blt_ring);
2198         if (ret)
2199                 return ret;
2200
2201         return 0;
2202 }
2203
2204 static int
2205 i915_gem_object_get_pages(struct drm_gem_object *obj,
2206                           gfp_t gfpmask)
2207 {
2208         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2209         int page_count, i;
2210         struct address_space *mapping;
2211         struct inode *inode;
2212         struct page *page;
2213
2214         BUG_ON(obj_priv->pages_refcount
2215                         == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2216
2217         if (obj_priv->pages_refcount++ != 0)
2218                 return 0;
2219
2220         /* Get the list of pages out of our struct file.  They'll be pinned
2221          * at this point until we release them.
2222          */
2223         page_count = obj->size / PAGE_SIZE;
2224         BUG_ON(obj_priv->pages != NULL);
2225         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2226         if (obj_priv->pages == NULL) {
2227                 obj_priv->pages_refcount--;
2228                 return -ENOMEM;
2229         }
2230
2231         inode = obj->filp->f_path.dentry->d_inode;
2232         mapping = inode->i_mapping;
2233         for (i = 0; i < page_count; i++) {
2234                 page = read_cache_page_gfp(mapping, i,
2235                                            GFP_HIGHUSER |
2236                                            __GFP_COLD |
2237                                            __GFP_RECLAIMABLE |
2238                                            gfpmask);
2239                 if (IS_ERR(page))
2240                         goto err_pages;
2241
2242                 obj_priv->pages[i] = page;
2243         }
2244
2245         if (obj_priv->tiling_mode != I915_TILING_NONE)
2246                 i915_gem_object_do_bit_17_swizzle(obj);
2247
2248         return 0;
2249
2250 err_pages:
2251         while (i--)
2252                 page_cache_release(obj_priv->pages[i]);
2253
2254         drm_free_large(obj_priv->pages);
2255         obj_priv->pages = NULL;
2256         obj_priv->pages_refcount--;
2257         return PTR_ERR(page);
2258 }
2259
2260 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2261 {
2262         struct drm_gem_object *obj = reg->obj;
2263         struct drm_device *dev = obj->dev;
2264         drm_i915_private_t *dev_priv = dev->dev_private;
2265         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2266         int regnum = obj_priv->fence_reg;
2267         uint64_t val;
2268
2269         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2270                     0xfffff000) << 32;
2271         val |= obj_priv->gtt_offset & 0xfffff000;
2272         val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2273                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2274
2275         if (obj_priv->tiling_mode == I915_TILING_Y)
2276                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2277         val |= I965_FENCE_REG_VALID;
2278
2279         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2280 }
2281
2282 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2283 {
2284         struct drm_gem_object *obj = reg->obj;
2285         struct drm_device *dev = obj->dev;
2286         drm_i915_private_t *dev_priv = dev->dev_private;
2287         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2288         int regnum = obj_priv->fence_reg;
2289         uint64_t val;
2290
2291         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2292                     0xfffff000) << 32;
2293         val |= obj_priv->gtt_offset & 0xfffff000;
2294         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2295         if (obj_priv->tiling_mode == I915_TILING_Y)
2296                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2297         val |= I965_FENCE_REG_VALID;
2298
2299         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2300 }
2301
2302 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2303 {
2304         struct drm_gem_object *obj = reg->obj;
2305         struct drm_device *dev = obj->dev;
2306         drm_i915_private_t *dev_priv = dev->dev_private;
2307         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2308         int regnum = obj_priv->fence_reg;
2309         int tile_width;
2310         uint32_t fence_reg, val;
2311         uint32_t pitch_val;
2312
2313         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2314             (obj_priv->gtt_offset & (obj->size - 1))) {
2315                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2316                      __func__, obj_priv->gtt_offset, obj->size);
2317                 return;
2318         }
2319
2320         if (obj_priv->tiling_mode == I915_TILING_Y &&
2321             HAS_128_BYTE_Y_TILING(dev))
2322                 tile_width = 128;
2323         else
2324                 tile_width = 512;
2325
2326         /* Note: pitch better be a power of two tile widths */
2327         pitch_val = obj_priv->stride / tile_width;
2328         pitch_val = ffs(pitch_val) - 1;
2329
2330         if (obj_priv->tiling_mode == I915_TILING_Y &&
2331             HAS_128_BYTE_Y_TILING(dev))
2332                 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2333         else
2334                 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2335
2336         val = obj_priv->gtt_offset;
2337         if (obj_priv->tiling_mode == I915_TILING_Y)
2338                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2339         val |= I915_FENCE_SIZE_BITS(obj->size);
2340         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2341         val |= I830_FENCE_REG_VALID;
2342
2343         if (regnum < 8)
2344                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2345         else
2346                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2347         I915_WRITE(fence_reg, val);
2348 }
2349
2350 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2351 {
2352         struct drm_gem_object *obj = reg->obj;
2353         struct drm_device *dev = obj->dev;
2354         drm_i915_private_t *dev_priv = dev->dev_private;
2355         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2356         int regnum = obj_priv->fence_reg;
2357         uint32_t val;
2358         uint32_t pitch_val;
2359         uint32_t fence_size_bits;
2360
2361         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2362             (obj_priv->gtt_offset & (obj->size - 1))) {
2363                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2364                      __func__, obj_priv->gtt_offset);
2365                 return;
2366         }
2367
2368         pitch_val = obj_priv->stride / 128;
2369         pitch_val = ffs(pitch_val) - 1;
2370         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2371
2372         val = obj_priv->gtt_offset;
2373         if (obj_priv->tiling_mode == I915_TILING_Y)
2374                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2375         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2376         WARN_ON(fence_size_bits & ~0x00000f00);
2377         val |= fence_size_bits;
2378         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2379         val |= I830_FENCE_REG_VALID;
2380
2381         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2382 }
2383
2384 static int i915_find_fence_reg(struct drm_device *dev,
2385                                bool interruptible)
2386 {
2387         struct drm_i915_fence_reg *reg = NULL;
2388         struct drm_i915_gem_object *obj_priv = NULL;
2389         struct drm_i915_private *dev_priv = dev->dev_private;
2390         struct drm_gem_object *obj = NULL;
2391         int i, avail, ret;
2392
2393         /* First try to find a free reg */
2394         avail = 0;
2395         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2396                 reg = &dev_priv->fence_regs[i];
2397                 if (!reg->obj)
2398                         return i;
2399
2400                 obj_priv = to_intel_bo(reg->obj);
2401                 if (!obj_priv->pin_count)
2402                     avail++;
2403         }
2404
2405         if (avail == 0)
2406                 return -ENOSPC;
2407
2408         /* None available, try to steal one or wait for a user to finish */
2409         i = I915_FENCE_REG_NONE;
2410         list_for_each_entry(reg, &dev_priv->mm.fence_list,
2411                             lru_list) {
2412                 obj = reg->obj;
2413                 obj_priv = to_intel_bo(obj);
2414
2415                 if (obj_priv->pin_count)
2416                         continue;
2417
2418                 /* found one! */
2419                 i = obj_priv->fence_reg;
2420                 break;
2421         }
2422
2423         BUG_ON(i == I915_FENCE_REG_NONE);
2424
2425         /* We only have a reference on obj from the active list. put_fence_reg
2426          * might drop that one, causing a use-after-free in it. So hold a
2427          * private reference to obj like the other callers of put_fence_reg
2428          * (set_tiling ioctl) do. */
2429         drm_gem_object_reference(obj);
2430         ret = i915_gem_object_put_fence_reg(obj, interruptible);
2431         drm_gem_object_unreference(obj);
2432         if (ret != 0)
2433                 return ret;
2434
2435         return i;
2436 }
2437
2438 /**
2439  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2440  * @obj: object to map through a fence reg
2441  *
2442  * When mapping objects through the GTT, userspace wants to be able to write
2443  * to them without having to worry about swizzling if the object is tiled.
2444  *
2445  * This function walks the fence regs looking for a free one for @obj,
2446  * stealing one if it can't find any.
2447  *
2448  * It then sets up the reg based on the object's properties: address, pitch
2449  * and tiling format.
2450  */
2451 int
2452 i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
2453                               bool interruptible)
2454 {
2455         struct drm_device *dev = obj->dev;
2456         struct drm_i915_private *dev_priv = dev->dev_private;
2457         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2458         struct drm_i915_fence_reg *reg = NULL;
2459         int ret;
2460
2461         /* Just update our place in the LRU if our fence is getting used. */
2462         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2463                 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2464                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2465                 return 0;
2466         }
2467
2468         switch (obj_priv->tiling_mode) {
2469         case I915_TILING_NONE:
2470                 WARN(1, "allocating a fence for non-tiled object?\n");
2471                 break;
2472         case I915_TILING_X:
2473                 if (!obj_priv->stride)
2474                         return -EINVAL;
2475                 WARN((obj_priv->stride & (512 - 1)),
2476                      "object 0x%08x is X tiled but has non-512B pitch\n",
2477                      obj_priv->gtt_offset);
2478                 break;
2479         case I915_TILING_Y:
2480                 if (!obj_priv->stride)
2481                         return -EINVAL;
2482                 WARN((obj_priv->stride & (128 - 1)),
2483                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2484                      obj_priv->gtt_offset);
2485                 break;
2486         }
2487
2488         ret = i915_find_fence_reg(dev, interruptible);
2489         if (ret < 0)
2490                 return ret;
2491
2492         obj_priv->fence_reg = ret;
2493         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2494         list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2495
2496         reg->obj = obj;
2497
2498         switch (INTEL_INFO(dev)->gen) {
2499         case 6:
2500                 sandybridge_write_fence_reg(reg);
2501                 break;
2502         case 5:
2503         case 4:
2504                 i965_write_fence_reg(reg);
2505                 break;
2506         case 3:
2507                 i915_write_fence_reg(reg);
2508                 break;
2509         case 2:
2510                 i830_write_fence_reg(reg);
2511                 break;
2512         }
2513
2514         trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2515                         obj_priv->tiling_mode);
2516
2517         return 0;
2518 }
2519
2520 /**
2521  * i915_gem_clear_fence_reg - clear out fence register info
2522  * @obj: object to clear
2523  *
2524  * Zeroes out the fence register itself and clears out the associated
2525  * data structures in dev_priv and obj_priv.
2526  */
2527 static void
2528 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2529 {
2530         struct drm_device *dev = obj->dev;
2531         drm_i915_private_t *dev_priv = dev->dev_private;
2532         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2533         struct drm_i915_fence_reg *reg =
2534                 &dev_priv->fence_regs[obj_priv->fence_reg];
2535         uint32_t fence_reg;
2536
2537         switch (INTEL_INFO(dev)->gen) {
2538         case 6:
2539                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2540                              (obj_priv->fence_reg * 8), 0);
2541                 break;
2542         case 5:
2543         case 4:
2544                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2545                 break;
2546         case 3:
2547                 if (obj_priv->fence_reg >= 8)
2548                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
2549                 else
2550         case 2:
2551                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2552
2553                 I915_WRITE(fence_reg, 0);
2554                 break;
2555         }
2556
2557         reg->obj = NULL;
2558         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2559         list_del_init(&reg->lru_list);
2560 }
2561
2562 /**
2563  * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2564  * to the buffer to finish, and then resets the fence register.
2565  * @obj: tiled object holding a fence register.
2566  * @bool: whether the wait upon the fence is interruptible
2567  *
2568  * Zeroes out the fence register itself and clears out the associated
2569  * data structures in dev_priv and obj_priv.
2570  */
2571 int
2572 i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
2573                               bool interruptible)
2574 {
2575         struct drm_device *dev = obj->dev;
2576         struct drm_i915_private *dev_priv = dev->dev_private;
2577         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2578         struct drm_i915_fence_reg *reg;
2579
2580         if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2581                 return 0;
2582
2583         /* If we've changed tiling, GTT-mappings of the object
2584          * need to re-fault to ensure that the correct fence register
2585          * setup is in place.
2586          */
2587         i915_gem_release_mmap(obj);
2588
2589         /* On the i915, GPU access to tiled buffers is via a fence,
2590          * therefore we must wait for any outstanding access to complete
2591          * before clearing the fence.
2592          */
2593         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2594         if (reg->gpu) {
2595                 int ret;
2596
2597                 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2598                 if (ret)
2599                         return ret;
2600
2601                 ret = i915_gem_object_wait_rendering(obj, interruptible);
2602                 if (ret)
2603                         return ret;
2604
2605                 reg->gpu = false;
2606         }
2607
2608         i915_gem_object_flush_gtt_write_domain(obj);
2609         i915_gem_clear_fence_reg(obj);
2610
2611         return 0;
2612 }
2613
2614 /**
2615  * Finds free space in the GTT aperture and binds the object there.
2616  */
2617 static int
2618 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2619 {
2620         struct drm_device *dev = obj->dev;
2621         drm_i915_private_t *dev_priv = dev->dev_private;
2622         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2623         struct drm_mm_node *free_space;
2624         gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
2625         int ret;
2626
2627         if (obj_priv->madv != I915_MADV_WILLNEED) {
2628                 DRM_ERROR("Attempting to bind a purgeable object\n");
2629                 return -EINVAL;
2630         }
2631
2632         if (alignment == 0)
2633                 alignment = i915_gem_get_gtt_alignment(obj);
2634         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2635                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2636                 return -EINVAL;
2637         }
2638
2639         /* If the object is bigger than the entire aperture, reject it early
2640          * before evicting everything in a vain attempt to find space.
2641          */
2642         if (obj->size > dev_priv->mm.gtt_total) {
2643                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2644                 return -E2BIG;
2645         }
2646
2647  search_free:
2648         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2649                                         obj->size, alignment, 0);
2650         if (free_space != NULL)
2651                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2652                                                        alignment);
2653         if (obj_priv->gtt_space == NULL) {
2654                 /* If the gtt is empty and we're still having trouble
2655                  * fitting our object in, we're out of memory.
2656                  */
2657                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2658                 if (ret)
2659                         return ret;
2660
2661                 goto search_free;
2662         }
2663
2664         ret = i915_gem_object_get_pages(obj, gfpmask);
2665         if (ret) {
2666                 drm_mm_put_block(obj_priv->gtt_space);
2667                 obj_priv->gtt_space = NULL;
2668
2669                 if (ret == -ENOMEM) {
2670                         /* first try to clear up some space from the GTT */
2671                         ret = i915_gem_evict_something(dev, obj->size,
2672                                                        alignment);
2673                         if (ret) {
2674                                 /* now try to shrink everyone else */
2675                                 if (gfpmask) {
2676                                         gfpmask = 0;
2677                                         goto search_free;
2678                                 }
2679
2680                                 return ret;
2681                         }
2682
2683                         goto search_free;
2684                 }
2685
2686                 return ret;
2687         }
2688
2689         /* Create an AGP memory structure pointing at our pages, and bind it
2690          * into the GTT.
2691          */
2692         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2693                                                obj_priv->pages,
2694                                                obj->size >> PAGE_SHIFT,
2695                                                obj_priv->gtt_space->start,
2696                                                obj_priv->agp_type);
2697         if (obj_priv->agp_mem == NULL) {
2698                 i915_gem_object_put_pages(obj);
2699                 drm_mm_put_block(obj_priv->gtt_space);
2700                 obj_priv->gtt_space = NULL;
2701
2702                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2703                 if (ret)
2704                         return ret;
2705
2706                 goto search_free;
2707         }
2708
2709         /* keep track of bounds object by adding it to the inactive list */
2710         list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
2711         i915_gem_info_add_gtt(dev_priv, obj->size);
2712
2713         /* Assert that the object is not currently in any GPU domain. As it
2714          * wasn't in the GTT, there shouldn't be any way it could have been in
2715          * a GPU cache
2716          */
2717         BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2718         BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2719
2720         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2721         trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2722
2723         return 0;
2724 }
2725
2726 void
2727 i915_gem_clflush_object(struct drm_gem_object *obj)
2728 {
2729         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
2730
2731         /* If we don't have a page list set up, then we're not pinned
2732          * to GPU, and we can ignore the cache flush because it'll happen
2733          * again at bind time.
2734          */
2735         if (obj_priv->pages == NULL)
2736                 return;
2737
2738         trace_i915_gem_object_clflush(obj);
2739
2740         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2741 }
2742
2743 /** Flushes any GPU write domain for the object if it's dirty. */
2744 static int
2745 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
2746                                        bool pipelined)
2747 {
2748         struct drm_device *dev = obj->dev;
2749         uint32_t old_write_domain;
2750
2751         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2752                 return 0;
2753
2754         /* Queue the GPU write cache flushing we need. */
2755         old_write_domain = obj->write_domain;
2756         i915_gem_flush_ring(dev, NULL,
2757                             to_intel_bo(obj)->ring,
2758                             0, obj->write_domain);
2759         BUG_ON(obj->write_domain);
2760
2761         trace_i915_gem_object_change_domain(obj,
2762                                             obj->read_domains,
2763                                             old_write_domain);
2764
2765         if (pipelined)
2766                 return 0;
2767
2768         return i915_gem_object_wait_rendering(obj, true);
2769 }
2770
2771 /** Flushes the GTT write domain for the object if it's dirty. */
2772 static void
2773 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2774 {
2775         uint32_t old_write_domain;
2776
2777         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2778                 return;
2779
2780         /* No actual flushing is required for the GTT write domain.   Writes
2781          * to it immediately go to main memory as far as we know, so there's
2782          * no chipset flush.  It also doesn't land in render cache.
2783          */
2784         old_write_domain = obj->write_domain;
2785         obj->write_domain = 0;
2786
2787         trace_i915_gem_object_change_domain(obj,
2788                                             obj->read_domains,
2789                                             old_write_domain);
2790 }
2791
2792 /** Flushes the CPU write domain for the object if it's dirty. */
2793 static void
2794 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2795 {
2796         struct drm_device *dev = obj->dev;
2797         uint32_t old_write_domain;
2798
2799         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2800                 return;
2801
2802         i915_gem_clflush_object(obj);
2803         drm_agp_chipset_flush(dev);
2804         old_write_domain = obj->write_domain;
2805         obj->write_domain = 0;
2806
2807         trace_i915_gem_object_change_domain(obj,
2808                                             obj->read_domains,
2809                                             old_write_domain);
2810 }
2811
2812 /**
2813  * Moves a single object to the GTT read, and possibly write domain.
2814  *
2815  * This function returns when the move is complete, including waiting on
2816  * flushes to occur.
2817  */
2818 int
2819 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2820 {
2821         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2822         uint32_t old_write_domain, old_read_domains;
2823         int ret;
2824
2825         /* Not valid to be called on unbound objects. */
2826         if (obj_priv->gtt_space == NULL)
2827                 return -EINVAL;
2828
2829         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2830         if (ret != 0)
2831                 return ret;
2832
2833         i915_gem_object_flush_cpu_write_domain(obj);
2834
2835         if (write) {
2836                 ret = i915_gem_object_wait_rendering(obj, true);
2837                 if (ret)
2838                         return ret;
2839         }
2840
2841         old_write_domain = obj->write_domain;
2842         old_read_domains = obj->read_domains;
2843
2844         /* It should now be out of any other write domains, and we can update
2845          * the domain values for our changes.
2846          */
2847         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2848         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2849         if (write) {
2850                 obj->read_domains = I915_GEM_DOMAIN_GTT;
2851                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2852                 obj_priv->dirty = 1;
2853         }
2854
2855         trace_i915_gem_object_change_domain(obj,
2856                                             old_read_domains,
2857                                             old_write_domain);
2858
2859         return 0;
2860 }
2861
2862 /*
2863  * Prepare buffer for display plane. Use uninterruptible for possible flush
2864  * wait, as in modesetting process we're not supposed to be interrupted.
2865  */
2866 int
2867 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
2868                                      bool pipelined)
2869 {
2870         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2871         uint32_t old_read_domains;
2872         int ret;
2873
2874         /* Not valid to be called on unbound objects. */
2875         if (obj_priv->gtt_space == NULL)
2876                 return -EINVAL;
2877
2878         ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2879         if (ret)
2880                 return ret;
2881
2882         /* Currently, we are always called from an non-interruptible context. */
2883         if (!pipelined) {
2884                 ret = i915_gem_object_wait_rendering(obj, false);
2885                 if (ret)
2886                         return ret;
2887         }
2888
2889         i915_gem_object_flush_cpu_write_domain(obj);
2890
2891         old_read_domains = obj->read_domains;
2892         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2893
2894         trace_i915_gem_object_change_domain(obj,
2895                                             old_read_domains,
2896                                             obj->write_domain);
2897
2898         return 0;
2899 }
2900
2901 int
2902 i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
2903                           bool interruptible)
2904 {
2905         if (!obj->active)
2906                 return 0;
2907
2908         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS)
2909                 i915_gem_flush_ring(obj->base.dev, NULL, obj->ring,
2910                                     0, obj->base.write_domain);
2911
2912         return i915_gem_object_wait_rendering(&obj->base, interruptible);
2913 }
2914
2915 /**
2916  * Moves a single object to the CPU read, and possibly write domain.
2917  *
2918  * This function returns when the move is complete, including waiting on
2919  * flushes to occur.
2920  */
2921 static int
2922 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2923 {
2924         uint32_t old_write_domain, old_read_domains;
2925         int ret;
2926
2927         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2928         if (ret != 0)
2929                 return ret;
2930
2931         i915_gem_object_flush_gtt_write_domain(obj);
2932
2933         /* If we have a partially-valid cache of the object in the CPU,
2934          * finish invalidating it and free the per-page flags.
2935          */
2936         i915_gem_object_set_to_full_cpu_read_domain(obj);
2937
2938         if (write) {
2939                 ret = i915_gem_object_wait_rendering(obj, true);
2940                 if (ret)
2941                         return ret;
2942         }
2943
2944         old_write_domain = obj->write_domain;
2945         old_read_domains = obj->read_domains;
2946
2947         /* Flush the CPU cache if it's still invalid. */
2948         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2949                 i915_gem_clflush_object(obj);
2950
2951                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2952         }
2953
2954         /* It should now be out of any other write domains, and we can update
2955          * the domain values for our changes.
2956          */
2957         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2958
2959         /* If we're writing through the CPU, then the GPU read domains will
2960          * need to be invalidated at next use.
2961          */
2962         if (write) {
2963                 obj->read_domains = I915_GEM_DOMAIN_CPU;
2964                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2965         }
2966
2967         trace_i915_gem_object_change_domain(obj,
2968                                             old_read_domains,
2969                                             old_write_domain);
2970
2971         return 0;
2972 }
2973
2974 /*
2975  * Set the next domain for the specified object. This
2976  * may not actually perform the necessary flushing/invaliding though,
2977  * as that may want to be batched with other set_domain operations
2978  *
2979  * This is (we hope) the only really tricky part of gem. The goal
2980  * is fairly simple -- track which caches hold bits of the object
2981  * and make sure they remain coherent. A few concrete examples may
2982  * help to explain how it works. For shorthand, we use the notation
2983  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2984  * a pair of read and write domain masks.
2985  *
2986  * Case 1: the batch buffer
2987  *
2988  *      1. Allocated
2989  *      2. Written by CPU
2990  *      3. Mapped to GTT
2991  *      4. Read by GPU
2992  *      5. Unmapped from GTT
2993  *      6. Freed
2994  *
2995  *      Let's take these a step at a time
2996  *
2997  *      1. Allocated
2998  *              Pages allocated from the kernel may still have
2999  *              cache contents, so we set them to (CPU, CPU) always.
3000  *      2. Written by CPU (using pwrite)
3001  *              The pwrite function calls set_domain (CPU, CPU) and
3002  *              this function does nothing (as nothing changes)
3003  *      3. Mapped by GTT
3004  *              This function asserts that the object is not
3005  *              currently in any GPU-based read or write domains
3006  *      4. Read by GPU
3007  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
3008  *              As write_domain is zero, this function adds in the
3009  *              current read domains (CPU+COMMAND, 0).
3010  *              flush_domains is set to CPU.
3011  *              invalidate_domains is set to COMMAND
3012  *              clflush is run to get data out of the CPU caches
3013  *              then i915_dev_set_domain calls i915_gem_flush to
3014  *              emit an MI_FLUSH and drm_agp_chipset_flush
3015  *      5. Unmapped from GTT
3016  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
3017  *              flush_domains and invalidate_domains end up both zero
3018  *              so no flushing/invalidating happens
3019  *      6. Freed
3020  *              yay, done
3021  *
3022  * Case 2: The shared render buffer
3023  *
3024  *      1. Allocated
3025  *      2. Mapped to GTT
3026  *      3. Read/written by GPU
3027  *      4. set_domain to (CPU,CPU)
3028  *      5. Read/written by CPU
3029  *      6. Read/written by GPU
3030  *
3031  *      1. Allocated
3032  *              Same as last example, (CPU, CPU)
3033  *      2. Mapped to GTT
3034  *              Nothing changes (assertions find that it is not in the GPU)
3035  *      3. Read/written by GPU
3036  *              execbuffer calls set_domain (RENDER, RENDER)
3037  *              flush_domains gets CPU
3038  *              invalidate_domains gets GPU
3039  *              clflush (obj)
3040  *              MI_FLUSH and drm_agp_chipset_flush
3041  *      4. set_domain (CPU, CPU)
3042  *              flush_domains gets GPU
3043  *              invalidate_domains gets CPU
3044  *              wait_rendering (obj) to make sure all drawing is complete.
3045  *              This will include an MI_FLUSH to get the data from GPU
3046  *              to memory
3047  *              clflush (obj) to invalidate the CPU cache
3048  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3049  *      5. Read/written by CPU
3050  *              cache lines are loaded and dirtied
3051  *      6. Read written by GPU
3052  *              Same as last GPU access
3053  *
3054  * Case 3: The constant buffer
3055  *
3056  *      1. Allocated
3057  *      2. Written by CPU
3058  *      3. Read by GPU
3059  *      4. Updated (written) by CPU again
3060  *      5. Read by GPU
3061  *
3062  *      1. Allocated
3063  *              (CPU, CPU)
3064  *      2. Written by CPU
3065  *              (CPU, CPU)
3066  *      3. Read by GPU
3067  *              (CPU+RENDER, 0)
3068  *              flush_domains = CPU
3069  *              invalidate_domains = RENDER
3070  *              clflush (obj)
3071  *              MI_FLUSH
3072  *              drm_agp_chipset_flush
3073  *      4. Updated (written) by CPU again
3074  *              (CPU, CPU)
3075  *              flush_domains = 0 (no previous write domain)
3076  *              invalidate_domains = 0 (no new read domains)
3077  *      5. Read by GPU
3078  *              (CPU+RENDER, 0)
3079  *              flush_domains = CPU
3080  *              invalidate_domains = RENDER
3081  *              clflush (obj)
3082  *              MI_FLUSH
3083  *              drm_agp_chipset_flush
3084  */
3085 static void
3086 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
3087                                   struct intel_ring_buffer *ring)
3088 {
3089         struct drm_device               *dev = obj->dev;
3090         struct drm_i915_private         *dev_priv = dev->dev_private;
3091         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
3092         uint32_t                        invalidate_domains = 0;
3093         uint32_t                        flush_domains = 0;
3094         uint32_t                        old_read_domains;
3095
3096         intel_mark_busy(dev, obj);
3097
3098         /*
3099          * If the object isn't moving to a new write domain,
3100          * let the object stay in multiple read domains
3101          */
3102         if (obj->pending_write_domain == 0)
3103                 obj->pending_read_domains |= obj->read_domains;
3104         else
3105                 obj_priv->dirty = 1;
3106
3107         /*
3108          * Flush the current write domain if
3109          * the new read domains don't match. Invalidate
3110          * any read domains which differ from the old
3111          * write domain
3112          */
3113         if (obj->write_domain &&
3114             (obj->write_domain != obj->pending_read_domains ||
3115              obj_priv->ring != ring)) {
3116                 flush_domains |= obj->write_domain;
3117                 invalidate_domains |=
3118                         obj->pending_read_domains & ~obj->write_domain;
3119         }
3120         /*
3121          * Invalidate any read caches which may have
3122          * stale data. That is, any new read domains.
3123          */
3124         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3125         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
3126                 i915_gem_clflush_object(obj);
3127
3128         old_read_domains = obj->read_domains;
3129
3130         /* The actual obj->write_domain will be updated with
3131          * pending_write_domain after we emit the accumulated flush for all
3132          * of our domain changes in execbuffers (which clears objects'
3133          * write_domains).  So if we have a current write domain that we
3134          * aren't changing, set pending_write_domain to that.
3135          */
3136         if (flush_domains == 0 && obj->pending_write_domain == 0)
3137                 obj->pending_write_domain = obj->write_domain;
3138         obj->read_domains = obj->pending_read_domains;
3139
3140         dev->invalidate_domains |= invalidate_domains;
3141         dev->flush_domains |= flush_domains;
3142         if (flush_domains & I915_GEM_GPU_DOMAINS)
3143                 dev_priv->mm.flush_rings |= obj_priv->ring->id;
3144         if (invalidate_domains & I915_GEM_GPU_DOMAINS)
3145                 dev_priv->mm.flush_rings |= ring->id;
3146
3147         trace_i915_gem_object_change_domain(obj,
3148                                             old_read_domains,
3149                                             obj->write_domain);
3150 }
3151
3152 /**
3153  * Moves the object from a partially CPU read to a full one.
3154  *
3155  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3156  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3157  */
3158 static void
3159 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3160 {
3161         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3162
3163         if (!obj_priv->page_cpu_valid)
3164                 return;
3165
3166         /* If we're partially in the CPU read domain, finish moving it in.
3167          */
3168         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3169                 int i;
3170
3171                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3172                         if (obj_priv->page_cpu_valid[i])
3173                                 continue;
3174                         drm_clflush_pages(obj_priv->pages + i, 1);
3175                 }
3176         }
3177
3178         /* Free the page_cpu_valid mappings which are now stale, whether
3179          * or not we've got I915_GEM_DOMAIN_CPU.
3180          */
3181         kfree(obj_priv->page_cpu_valid);
3182         obj_priv->page_cpu_valid = NULL;
3183 }
3184
3185 /**
3186  * Set the CPU read domain on a range of the object.
3187  *
3188  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3189  * not entirely valid.  The page_cpu_valid member of the object flags which
3190  * pages have been flushed, and will be respected by
3191  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3192  * of the whole object.
3193  *
3194  * This function returns when the move is complete, including waiting on
3195  * flushes to occur.
3196  */
3197 static int
3198 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3199                                           uint64_t offset, uint64_t size)
3200 {
3201         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3202         uint32_t old_read_domains;
3203         int i, ret;
3204
3205         if (offset == 0 && size == obj->size)
3206                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3207
3208         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
3209         if (ret != 0)
3210                 return ret;
3211         i915_gem_object_flush_gtt_write_domain(obj);
3212
3213         /* If we're already fully in the CPU read domain, we're done. */
3214         if (obj_priv->page_cpu_valid == NULL &&
3215             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3216                 return 0;
3217
3218         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3219          * newly adding I915_GEM_DOMAIN_CPU
3220          */
3221         if (obj_priv->page_cpu_valid == NULL) {
3222                 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3223                                                    GFP_KERNEL);
3224                 if (obj_priv->page_cpu_valid == NULL)
3225                         return -ENOMEM;
3226         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3227                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3228
3229         /* Flush the cache on any pages that are still invalid from the CPU's
3230          * perspective.
3231          */
3232         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3233              i++) {
3234                 if (obj_priv->page_cpu_valid[i])
3235                         continue;
3236
3237                 drm_clflush_pages(obj_priv->pages + i, 1);
3238
3239                 obj_priv->page_cpu_valid[i] = 1;
3240         }
3241
3242         /* It should now be out of any other write domains, and we can update
3243          * the domain values for our changes.
3244          */
3245         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3246
3247         old_read_domains = obj->read_domains;
3248         obj->read_domains |= I915_GEM_DOMAIN_CPU;
3249
3250         trace_i915_gem_object_change_domain(obj,
3251                                             old_read_domains,
3252                                             obj->write_domain);
3253
3254         return 0;
3255 }
3256
3257 /**
3258  * Pin an object to the GTT and evaluate the relocations landing in it.
3259  */
3260 static int
3261 i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj,
3262                              struct drm_file *file_priv,
3263                              struct drm_i915_gem_exec_object2 *entry)
3264 {
3265         struct drm_device *dev = obj->base.dev;
3266         drm_i915_private_t *dev_priv = dev->dev_private;
3267         struct drm_i915_gem_relocation_entry __user *user_relocs;
3268         struct drm_gem_object *target_obj = NULL;
3269         uint32_t target_handle = 0;
3270         int i, ret = 0;
3271
3272         user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
3273         for (i = 0; i < entry->relocation_count; i++) {
3274                 struct drm_i915_gem_relocation_entry reloc;
3275                 uint32_t target_offset;
3276
3277                 if (__copy_from_user_inatomic(&reloc,
3278                                               user_relocs+i,
3279                                               sizeof(reloc))) {
3280                         ret = -EFAULT;
3281                         break;
3282                 }
3283
3284                 if (reloc.target_handle != target_handle) {
3285                         drm_gem_object_unreference(target_obj);
3286
3287                         target_obj = drm_gem_object_lookup(dev, file_priv,
3288                                                            reloc.target_handle);
3289                         if (target_obj == NULL) {
3290                                 ret = -ENOENT;
3291                                 break;
3292                         }
3293
3294                         target_handle = reloc.target_handle;
3295                 }
3296                 target_offset = to_intel_bo(target_obj)->gtt_offset;
3297
3298 #if WATCH_RELOC
3299                 DRM_INFO("%s: obj %p offset %08x target %d "
3300                          "read %08x write %08x gtt %08x "
3301                          "presumed %08x delta %08x\n",
3302                          __func__,
3303                          obj,
3304                          (int) reloc.offset,
3305                          (int) reloc.target_handle,
3306                          (int) reloc.read_domains,
3307                          (int) reloc.write_domain,
3308                          (int) target_offset,
3309                          (int) reloc.presumed_offset,
3310                          reloc.delta);
3311 #endif
3312
3313                 /* The target buffer should have appeared before us in the
3314                  * exec_object list, so it should have a GTT space bound by now.
3315                  */
3316                 if (target_offset == 0) {
3317                         DRM_ERROR("No GTT space found for object %d\n",
3318                                   reloc.target_handle);
3319                         ret = -EINVAL;
3320                         break;
3321                 }
3322
3323                 /* Validate that the target is in a valid r/w GPU domain */
3324                 if (reloc.write_domain & (reloc.write_domain - 1)) {
3325                         DRM_ERROR("reloc with multiple write domains: "
3326                                   "obj %p target %d offset %d "
3327                                   "read %08x write %08x",
3328                                   obj, reloc.target_handle,
3329                                   (int) reloc.offset,
3330                                   reloc.read_domains,
3331                                   reloc.write_domain);
3332                         ret = -EINVAL;
3333                         break;
3334                 }
3335                 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
3336                     reloc.read_domains & I915_GEM_DOMAIN_CPU) {
3337                         DRM_ERROR("reloc with read/write CPU domains: "
3338                                   "obj %p target %d offset %d "
3339                                   "read %08x write %08x",
3340                                   obj, reloc.target_handle,
3341                                   (int) reloc.offset,
3342                                   reloc.read_domains,
3343                                   reloc.write_domain);
3344                         ret = -EINVAL;
3345                         break;
3346                 }
3347                 if (reloc.write_domain && target_obj->pending_write_domain &&
3348                     reloc.write_domain != target_obj->pending_write_domain) {
3349                         DRM_ERROR("Write domain conflict: "
3350                                   "obj %p target %d offset %d "
3351                                   "new %08x old %08x\n",
3352                                   obj, reloc.target_handle,
3353                                   (int) reloc.offset,
3354                                   reloc.write_domain,
3355                                   target_obj->pending_write_domain);
3356                         ret = -EINVAL;
3357                         break;
3358                 }
3359
3360                 target_obj->pending_read_domains |= reloc.read_domains;
3361                 target_obj->pending_write_domain |= reloc.write_domain;
3362
3363                 /* If the relocation already has the right value in it, no
3364                  * more work needs to be done.
3365                  */
3366                 if (target_offset == reloc.presumed_offset)
3367                         continue;
3368
3369                 /* Check that the relocation address is valid... */
3370                 if (reloc.offset > obj->base.size - 4) {
3371                         DRM_ERROR("Relocation beyond object bounds: "
3372                                   "obj %p target %d offset %d size %d.\n",
3373                                   obj, reloc.target_handle,
3374                                   (int) reloc.offset, (int) obj->base.size);
3375                         ret = -EINVAL;
3376                         break;
3377                 }
3378                 if (reloc.offset & 3) {
3379                         DRM_ERROR("Relocation not 4-byte aligned: "
3380                                   "obj %p target %d offset %d.\n",
3381                                   obj, reloc.target_handle,
3382                                   (int) reloc.offset);
3383                         ret = -EINVAL;
3384                         break;
3385                 }
3386
3387                 /* and points to somewhere within the target object. */
3388                 if (reloc.delta >= target_obj->size) {
3389                         DRM_ERROR("Relocation beyond target object bounds: "
3390                                   "obj %p target %d delta %d size %d.\n",
3391                                   obj, reloc.target_handle,
3392                                   (int) reloc.delta, (int) target_obj->size);
3393                         ret = -EINVAL;
3394                         break;
3395                 }
3396
3397                 reloc.delta += target_offset;
3398                 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
3399                         uint32_t page_offset = reloc.offset & ~PAGE_MASK;
3400                         char *vaddr;
3401
3402                         vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]);
3403                         *(uint32_t *)(vaddr + page_offset) = reloc.delta;
3404                         kunmap_atomic(vaddr);
3405                 } else {
3406                         uint32_t __iomem *reloc_entry;
3407                         void __iomem *reloc_page;
3408
3409                         ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1);
3410                         if (ret)
3411                                 break;
3412
3413                         /* Map the page containing the relocation we're going to perform.  */
3414                         reloc.offset += obj->gtt_offset;
3415                         reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3416                                                               reloc.offset & PAGE_MASK);
3417                         reloc_entry = (uint32_t __iomem *)
3418                                 (reloc_page + (reloc.offset & ~PAGE_MASK));
3419                         iowrite32(reloc.delta, reloc_entry);
3420                         io_mapping_unmap_atomic(reloc_page);
3421                 }
3422
3423                 /* and update the user's relocation entry */
3424                 reloc.presumed_offset = target_offset;
3425                 if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset,
3426                                               &reloc.presumed_offset,
3427                                               sizeof(reloc.presumed_offset))) {
3428                     ret = -EFAULT;
3429                     break;
3430                 }
3431         }
3432
3433         drm_gem_object_unreference(target_obj);
3434         return ret;
3435 }
3436
3437 static int
3438 i915_gem_execbuffer_pin(struct drm_device *dev,
3439                         struct drm_file *file,
3440                         struct drm_gem_object **object_list,
3441                         struct drm_i915_gem_exec_object2 *exec_list,
3442                         int count)
3443 {
3444         struct drm_i915_private *dev_priv = dev->dev_private;
3445         int ret, i, retry;
3446
3447         /* attempt to pin all of the buffers into the GTT */
3448         for (retry = 0; retry < 2; retry++) {
3449                 ret = 0;
3450                 for (i = 0; i < count; i++) {
3451                         struct drm_i915_gem_exec_object2 *entry = &exec_list[i];
3452                         struct drm_i915_gem_object *obj= to_intel_bo(object_list[i]);
3453                         bool need_fence =
3454                                 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3455                                 obj->tiling_mode != I915_TILING_NONE;
3456
3457                         /* Check fence reg constraints and rebind if necessary */
3458                         if (need_fence &&
3459                             !i915_gem_object_fence_offset_ok(&obj->base,
3460                                                              obj->tiling_mode)) {
3461                                 ret = i915_gem_object_unbind(&obj->base);
3462                                 if (ret)
3463                                         break;
3464                         }
3465
3466                         ret = i915_gem_object_pin(&obj->base, entry->alignment);
3467                         if (ret)
3468                                 break;
3469
3470                         /*
3471                          * Pre-965 chips need a fence register set up in order
3472                          * to properly handle blits to/from tiled surfaces.
3473                          */
3474                         if (need_fence) {
3475                                 ret = i915_gem_object_get_fence_reg(&obj->base, true);
3476                                 if (ret) {
3477                                         i915_gem_object_unpin(&obj->base);
3478                                         break;
3479                                 }
3480
3481                                 dev_priv->fence_regs[obj->fence_reg].gpu = true;
3482                         }
3483
3484                         entry->offset = obj->gtt_offset;
3485                 }
3486
3487                 while (i--)
3488                         i915_gem_object_unpin(object_list[i]);
3489
3490                 if (ret == 0)
3491                         break;
3492
3493                 if (ret != -ENOSPC || retry)
3494                         return ret;
3495
3496                 ret = i915_gem_evict_everything(dev);
3497                 if (ret)
3498                         return ret;
3499         }
3500
3501         return 0;
3502 }
3503
3504 static int
3505 i915_gem_execbuffer_move_to_gpu(struct drm_device *dev,
3506                                 struct drm_file *file,
3507                                 struct intel_ring_buffer *ring,
3508                                 struct drm_gem_object **objects,
3509                                 int count)
3510 {
3511         struct drm_i915_private *dev_priv = dev->dev_private;
3512         int ret, i;
3513
3514         /* Zero the global flush/invalidate flags. These
3515          * will be modified as new domains are computed
3516          * for each object
3517          */
3518         dev->invalidate_domains = 0;
3519         dev->flush_domains = 0;
3520         dev_priv->mm.flush_rings = 0;
3521         for (i = 0; i < count; i++)
3522                 i915_gem_object_set_to_gpu_domain(objects[i], ring);
3523
3524         if (dev->invalidate_domains | dev->flush_domains) {
3525 #if WATCH_EXEC
3526                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3527                           __func__,
3528                          dev->invalidate_domains,
3529                          dev->flush_domains);
3530 #endif
3531                 i915_gem_flush(dev, file,
3532                                dev->invalidate_domains,
3533                                dev->flush_domains,
3534                                dev_priv->mm.flush_rings);
3535         }
3536
3537         for (i = 0; i < count; i++) {
3538                 struct drm_i915_gem_object *obj = to_intel_bo(objects[i]);
3539                 /* XXX replace with semaphores */
3540                 if (obj->ring && ring != obj->ring) {
3541                         ret = i915_gem_object_wait_rendering(&obj->base, true);
3542                         if (ret)
3543                                 return ret;
3544                 }
3545         }
3546
3547         return 0;
3548 }
3549
3550 /* Throttle our rendering by waiting until the ring has completed our requests
3551  * emitted over 20 msec ago.
3552  *
3553  * Note that if we were to use the current jiffies each time around the loop,
3554  * we wouldn't escape the function with any frames outstanding if the time to
3555  * render a frame was over 20ms.
3556  *
3557  * This should get us reasonable parallelism between CPU and GPU but also
3558  * relatively low latency when blocking on a particular request to finish.
3559  */
3560 static int
3561 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3562 {
3563         struct drm_i915_private *dev_priv = dev->dev_private;
3564         struct drm_i915_file_private *file_priv = file->driver_priv;
3565         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3566         struct drm_i915_gem_request *request;
3567         struct intel_ring_buffer *ring = NULL;
3568         u32 seqno = 0;
3569         int ret;
3570
3571         spin_lock(&file_priv->mm.lock);
3572         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3573                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3574                         break;
3575
3576                 ring = request->ring;
3577                 seqno = request->seqno;
3578         }
3579         spin_unlock(&file_priv->mm.lock);
3580
3581         if (seqno == 0)
3582                 return 0;
3583
3584         ret = 0;
3585         if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) {
3586                 /* And wait for the seqno passing without holding any locks and
3587                  * causing extra latency for others. This is safe as the irq
3588                  * generation is designed to be run atomically and so is
3589                  * lockless.
3590                  */
3591                 ring->user_irq_get(dev, ring);
3592                 ret = wait_event_interruptible(ring->irq_queue,
3593                                                i915_seqno_passed(ring->get_seqno(dev, ring), seqno)
3594                                                || atomic_read(&dev_priv->mm.wedged));
3595                 ring->user_irq_put(dev, ring);
3596
3597                 if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3598                         ret = -EIO;
3599         }
3600
3601         if (ret == 0)
3602                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3603
3604         return ret;
3605 }
3606
3607 static int
3608 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec,
3609                           uint64_t exec_offset)
3610 {
3611         uint32_t exec_start, exec_len;
3612
3613         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3614         exec_len = (uint32_t) exec->batch_len;
3615
3616         if ((exec_start | exec_len) & 0x7)
3617                 return -EINVAL;
3618
3619         if (!exec_start)
3620                 return -EINVAL;
3621
3622         return 0;
3623 }
3624
3625 static int
3626 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
3627                    int count)
3628 {
3629         int i;
3630
3631         for (i = 0; i < count; i++) {
3632                 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
3633                 size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry);
3634
3635                 if (!access_ok(VERIFY_READ, ptr, length))
3636                         return -EFAULT;
3637
3638                 /* we may also need to update the presumed offsets */
3639                 if (!access_ok(VERIFY_WRITE, ptr, length))
3640                         return -EFAULT;
3641
3642                 if (fault_in_pages_readable(ptr, length))
3643                         return -EFAULT;
3644         }
3645
3646         return 0;
3647 }
3648
3649 static int
3650 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3651                        struct drm_file *file,
3652                        struct drm_i915_gem_execbuffer2 *args,
3653                        struct drm_i915_gem_exec_object2 *exec_list)
3654 {
3655         drm_i915_private_t *dev_priv = dev->dev_private;
3656         struct drm_gem_object **object_list = NULL;
3657         struct drm_gem_object *batch_obj;
3658         struct drm_i915_gem_object *obj_priv;
3659         struct drm_clip_rect *cliprects = NULL;
3660         struct drm_i915_gem_request *request = NULL;
3661         int ret, i, flips;
3662         uint64_t exec_offset;
3663
3664         struct intel_ring_buffer *ring = NULL;
3665
3666         ret = i915_gem_check_is_wedged(dev);
3667         if (ret)
3668                 return ret;
3669
3670         ret = validate_exec_list(exec_list, args->buffer_count);
3671         if (ret)
3672                 return ret;
3673
3674 #if WATCH_EXEC
3675         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3676                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3677 #endif
3678         switch (args->flags & I915_EXEC_RING_MASK) {
3679         case I915_EXEC_DEFAULT:
3680         case I915_EXEC_RENDER:
3681                 ring = &dev_priv->render_ring;
3682                 break;
3683         case I915_EXEC_BSD:
3684                 if (!HAS_BSD(dev)) {
3685                         DRM_ERROR("execbuf with invalid ring (BSD)\n");
3686                         return -EINVAL;
3687                 }
3688                 ring = &dev_priv->bsd_ring;
3689                 break;
3690         case I915_EXEC_BLT:
3691                 if (!HAS_BLT(dev)) {
3692                         DRM_ERROR("execbuf with invalid ring (BLT)\n");
3693                         return -EINVAL;
3694                 }
3695                 ring = &dev_priv->blt_ring;
3696                 break;
3697         default:
3698                 DRM_ERROR("execbuf with unknown ring: %d\n",
3699                           (int)(args->flags & I915_EXEC_RING_MASK));
3700                 return -EINVAL;
3701         }
3702
3703         if (args->buffer_count < 1) {
3704                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3705                 return -EINVAL;
3706         }
3707         object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3708         if (object_list == NULL) {
3709                 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3710                           args->buffer_count);
3711                 ret = -ENOMEM;
3712                 goto pre_mutex_err;
3713         }
3714
3715         if (args->num_cliprects != 0) {
3716                 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3717                                     GFP_KERNEL);
3718                 if (cliprects == NULL) {
3719                         ret = -ENOMEM;
3720                         goto pre_mutex_err;
3721                 }
3722
3723                 ret = copy_from_user(cliprects,
3724                                      (struct drm_clip_rect __user *)
3725                                      (uintptr_t) args->cliprects_ptr,
3726                                      sizeof(*cliprects) * args->num_cliprects);
3727                 if (ret != 0) {
3728                         DRM_ERROR("copy %d cliprects failed: %d\n",
3729                                   args->num_cliprects, ret);
3730                         ret = -EFAULT;
3731                         goto pre_mutex_err;
3732                 }
3733         }
3734
3735         request = kzalloc(sizeof(*request), GFP_KERNEL);
3736         if (request == NULL) {
3737                 ret = -ENOMEM;
3738                 goto pre_mutex_err;
3739         }
3740
3741         ret = i915_mutex_lock_interruptible(dev);
3742         if (ret)
3743                 goto pre_mutex_err;
3744
3745         if (dev_priv->mm.suspended) {
3746                 mutex_unlock(&dev->struct_mutex);
3747                 ret = -EBUSY;
3748                 goto pre_mutex_err;
3749         }
3750
3751         /* Look up object handles */
3752         for (i = 0; i < args->buffer_count; i++) {
3753                 object_list[i] = drm_gem_object_lookup(dev, file,
3754                                                        exec_list[i].handle);
3755                 if (object_list[i] == NULL) {
3756                         DRM_ERROR("Invalid object handle %d at index %d\n",
3757                                    exec_list[i].handle, i);
3758                         /* prevent error path from reading uninitialized data */
3759                         args->buffer_count = i + 1;
3760                         ret = -ENOENT;
3761                         goto err;
3762                 }
3763
3764                 obj_priv = to_intel_bo(object_list[i]);
3765                 if (obj_priv->in_execbuffer) {
3766                         DRM_ERROR("Object %p appears more than once in object list\n",
3767                                    object_list[i]);
3768                         /* prevent error path from reading uninitialized data */
3769                         args->buffer_count = i + 1;
3770                         ret = -EINVAL;
3771                         goto err;
3772                 }
3773                 obj_priv->in_execbuffer = true;
3774         }
3775
3776         /* Move the objects en-masse into the GTT, evicting if necessary. */
3777         ret = i915_gem_execbuffer_pin(dev, file,
3778                                       object_list, exec_list,
3779                                       args->buffer_count);
3780         if (ret)
3781                 goto err;
3782
3783         /* The objects are in their final locations, apply the relocations. */
3784         for (i = 0; i < args->buffer_count; i++) {
3785                 struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]);
3786                 obj->base.pending_read_domains = 0;
3787                 obj->base.pending_write_domain = 0;
3788                 ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]);
3789                 if (ret)
3790                         goto err;
3791         }
3792
3793         /* Set the pending read domains for the batch buffer to COMMAND */
3794         batch_obj = object_list[args->buffer_count-1];
3795         if (batch_obj->pending_write_domain) {
3796                 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3797                 ret = -EINVAL;
3798                 goto err;
3799         }
3800         batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3801
3802         /* Sanity check the batch buffer */
3803         exec_offset = to_intel_bo(batch_obj)->gtt_offset;
3804         ret = i915_gem_check_execbuffer(args, exec_offset);
3805         if (ret != 0) {
3806                 DRM_ERROR("execbuf with invalid offset/length\n");
3807                 goto err;
3808         }
3809
3810         ret = i915_gem_execbuffer_move_to_gpu(dev, file, ring,
3811                                               object_list, args->buffer_count);
3812         if (ret)
3813                 goto err;
3814
3815         for (i = 0; i < args->buffer_count; i++) {
3816                 struct drm_gem_object *obj = object_list[i];
3817                 uint32_t old_write_domain = obj->write_domain;
3818                 obj->write_domain = obj->pending_write_domain;
3819                 trace_i915_gem_object_change_domain(obj,
3820                                                     obj->read_domains,
3821                                                     old_write_domain);
3822         }
3823
3824 #if WATCH_COHERENCY
3825         for (i = 0; i < args->buffer_count; i++) {
3826                 i915_gem_object_check_coherency(object_list[i],
3827                                                 exec_list[i].handle);
3828         }
3829 #endif
3830
3831 #if WATCH_EXEC
3832         i915_gem_dump_object(batch_obj,
3833                               args->batch_len,
3834                               __func__,
3835                               ~0);
3836 #endif
3837
3838         /* Check for any pending flips. As we only maintain a flip queue depth
3839          * of 1, we can simply insert a WAIT for the next display flip prior
3840          * to executing the batch and avoid stalling the CPU.
3841          */
3842         flips = 0;
3843         for (i = 0; i < args->buffer_count; i++) {
3844                 if (object_list[i]->write_domain)
3845                         flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip);
3846         }
3847         if (flips) {
3848                 int plane, flip_mask;
3849
3850                 for (plane = 0; flips >> plane; plane++) {
3851                         if (((flips >> plane) & 1) == 0)
3852                                 continue;
3853
3854                         if (plane)
3855                                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
3856                         else
3857                                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
3858
3859                         intel_ring_begin(dev, ring, 2);
3860                         intel_ring_emit(dev, ring,
3861                                         MI_WAIT_FOR_EVENT | flip_mask);
3862                         intel_ring_emit(dev, ring, MI_NOOP);
3863                         intel_ring_advance(dev, ring);
3864                 }
3865         }
3866
3867         /* Exec the batchbuffer */
3868         ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3869                                             cliprects, exec_offset);
3870         if (ret) {
3871                 DRM_ERROR("dispatch failed %d\n", ret);
3872                 goto err;
3873         }
3874
3875         /*
3876          * Ensure that the commands in the batch buffer are
3877          * finished before the interrupt fires
3878          */
3879         i915_retire_commands(dev, ring);
3880
3881         for (i = 0; i < args->buffer_count; i++) {
3882                 struct drm_gem_object *obj = object_list[i];
3883
3884                 i915_gem_object_move_to_active(obj, ring);
3885                 if (obj->write_domain)
3886                         list_move_tail(&to_intel_bo(obj)->gpu_write_list,
3887                                        &ring->gpu_write_list);
3888         }
3889
3890         i915_add_request(dev, file, request, ring);
3891         request = NULL;
3892
3893 err:
3894         for (i = 0; i < args->buffer_count; i++) {
3895                 if (object_list[i]) {
3896                         obj_priv = to_intel_bo(object_list[i]);
3897                         obj_priv->in_execbuffer = false;
3898                 }
3899                 drm_gem_object_unreference(object_list[i]);
3900         }
3901
3902         mutex_unlock(&dev->struct_mutex);
3903
3904 pre_mutex_err:
3905         drm_free_large(object_list);
3906         kfree(cliprects);
3907         kfree(request);
3908
3909         return ret;
3910 }
3911
3912 /*
3913  * Legacy execbuffer just creates an exec2 list from the original exec object
3914  * list array and passes it to the real function.
3915  */
3916 int
3917 i915_gem_execbuffer(struct drm_device *dev, void *data,
3918                     struct drm_file *file_priv)
3919 {
3920         struct drm_i915_gem_execbuffer *args = data;
3921         struct drm_i915_gem_execbuffer2 exec2;
3922         struct drm_i915_gem_exec_object *exec_list = NULL;
3923         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3924         int ret, i;
3925
3926 #if WATCH_EXEC
3927         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3928                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3929 #endif
3930
3931         if (args->buffer_count < 1) {
3932                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3933                 return -EINVAL;
3934         }
3935
3936         /* Copy in the exec list from userland */
3937         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3938         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3939         if (exec_list == NULL || exec2_list == NULL) {
3940                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3941                           args->buffer_count);
3942                 drm_free_large(exec_list);
3943                 drm_free_large(exec2_list);
3944                 return -ENOMEM;
3945         }
3946         ret = copy_from_user(exec_list,
3947                              (struct drm_i915_relocation_entry __user *)
3948                              (uintptr_t) args->buffers_ptr,
3949                              sizeof(*exec_list) * args->buffer_count);
3950         if (ret != 0) {
3951                 DRM_ERROR("copy %d exec entries failed %d\n",
3952                           args->buffer_count, ret);
3953                 drm_free_large(exec_list);
3954                 drm_free_large(exec2_list);
3955                 return -EFAULT;
3956         }
3957
3958         for (i = 0; i < args->buffer_count; i++) {
3959                 exec2_list[i].handle = exec_list[i].handle;
3960                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3961                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3962                 exec2_list[i].alignment = exec_list[i].alignment;
3963                 exec2_list[i].offset = exec_list[i].offset;
3964                 if (INTEL_INFO(dev)->gen < 4)
3965                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3966                 else
3967                         exec2_list[i].flags = 0;
3968         }
3969
3970         exec2.buffers_ptr = args->buffers_ptr;
3971         exec2.buffer_count = args->buffer_count;
3972         exec2.batch_start_offset = args->batch_start_offset;
3973         exec2.batch_len = args->batch_len;
3974         exec2.DR1 = args->DR1;
3975         exec2.DR4 = args->DR4;
3976         exec2.num_cliprects = args->num_cliprects;
3977         exec2.cliprects_ptr = args->cliprects_ptr;
3978         exec2.flags = I915_EXEC_RENDER;
3979
3980         ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3981         if (!ret) {
3982                 /* Copy the new buffer offsets back to the user's exec list. */
3983                 for (i = 0; i < args->buffer_count; i++)
3984                         exec_list[i].offset = exec2_list[i].offset;
3985                 /* ... and back out to userspace */
3986                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3987                                    (uintptr_t) args->buffers_ptr,
3988                                    exec_list,
3989                                    sizeof(*exec_list) * args->buffer_count);
3990                 if (ret) {
3991                         ret = -EFAULT;
3992                         DRM_ERROR("failed to copy %d exec entries "
3993                                   "back to user (%d)\n",
3994                                   args->buffer_count, ret);
3995                 }
3996         }
3997
3998         drm_free_large(exec_list);
3999         drm_free_large(exec2_list);
4000         return ret;
4001 }
4002
4003 int
4004 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4005                      struct drm_file *file_priv)
4006 {
4007         struct drm_i915_gem_execbuffer2 *args = data;
4008         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4009         int ret;
4010
4011 #if WATCH_EXEC
4012         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4013                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4014 #endif
4015
4016         if (args->buffer_count < 1) {
4017                 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4018                 return -EINVAL;
4019         }
4020
4021         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4022         if (exec2_list == NULL) {
4023                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4024                           args->buffer_count);
4025                 return -ENOMEM;
4026         }
4027         ret = copy_from_user(exec2_list,
4028                              (struct drm_i915_relocation_entry __user *)
4029                              (uintptr_t) args->buffers_ptr,
4030                              sizeof(*exec2_list) * args->buffer_count);
4031         if (ret != 0) {
4032                 DRM_ERROR("copy %d exec entries failed %d\n",
4033                           args->buffer_count, ret);
4034                 drm_free_large(exec2_list);
4035                 return -EFAULT;
4036         }
4037
4038         ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4039         if (!ret) {
4040                 /* Copy the new buffer offsets back to the user's exec list. */
4041                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4042                                    (uintptr_t) args->buffers_ptr,
4043                                    exec2_list,
4044                                    sizeof(*exec2_list) * args->buffer_count);
4045                 if (ret) {
4046                         ret = -EFAULT;
4047                         DRM_ERROR("failed to copy %d exec entries "
4048                                   "back to user (%d)\n",
4049                                   args->buffer_count, ret);
4050                 }
4051         }
4052
4053         drm_free_large(exec2_list);
4054         return ret;
4055 }
4056
4057 int
4058 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4059 {
4060         struct drm_device *dev = obj->dev;
4061         struct drm_i915_private *dev_priv = dev->dev_private;
4062         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4063         int ret;
4064
4065         BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4066         WARN_ON(i915_verify_lists(dev));
4067
4068         if (obj_priv->gtt_space != NULL) {
4069                 if (alignment == 0)
4070                         alignment = i915_gem_get_gtt_alignment(obj);
4071                 if (obj_priv->gtt_offset & (alignment - 1)) {
4072                         WARN(obj_priv->pin_count,
4073                              "bo is already pinned with incorrect alignment: offset=%x, req.alignment=%x\n",
4074                              obj_priv->gtt_offset, alignment);
4075                         ret = i915_gem_object_unbind(obj);
4076                         if (ret)
4077                                 return ret;
4078                 }
4079         }
4080
4081         if (obj_priv->gtt_space == NULL) {
4082                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4083                 if (ret)
4084                         return ret;
4085         }
4086
4087         obj_priv->pin_count++;
4088
4089         /* If the object is not active and not pending a flush,
4090          * remove it from the inactive list
4091          */
4092         if (obj_priv->pin_count == 1) {
4093                 i915_gem_info_add_pin(dev_priv, obj->size);
4094                 if (!obj_priv->active)
4095                         list_move_tail(&obj_priv->mm_list,
4096                                        &dev_priv->mm.pinned_list);
4097         }
4098
4099         WARN_ON(i915_verify_lists(dev));
4100         return 0;
4101 }
4102
4103 void
4104 i915_gem_object_unpin(struct drm_gem_object *obj)
4105 {
4106         struct drm_device *dev = obj->dev;
4107         drm_i915_private_t *dev_priv = dev->dev_private;
4108         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4109
4110         WARN_ON(i915_verify_lists(dev));
4111         obj_priv->pin_count--;
4112         BUG_ON(obj_priv->pin_count < 0);
4113         BUG_ON(obj_priv->gtt_space == NULL);
4114
4115         /* If the object is no longer pinned, and is
4116          * neither active nor being flushed, then stick it on
4117          * the inactive list
4118          */
4119         if (obj_priv->pin_count == 0) {
4120                 if (!obj_priv->active)
4121                         list_move_tail(&obj_priv->mm_list,
4122                                        &dev_priv->mm.inactive_list);
4123                 i915_gem_info_remove_pin(dev_priv, obj->size);
4124         }
4125         WARN_ON(i915_verify_lists(dev));
4126 }
4127
4128 int
4129 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4130                    struct drm_file *file_priv)
4131 {
4132         struct drm_i915_gem_pin *args = data;
4133         struct drm_gem_object *obj;
4134         struct drm_i915_gem_object *obj_priv;
4135         int ret;
4136
4137         ret = i915_mutex_lock_interruptible(dev);
4138         if (ret)
4139                 return ret;
4140
4141         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4142         if (obj == NULL) {
4143                 ret = -ENOENT;
4144                 goto unlock;
4145         }
4146         obj_priv = to_intel_bo(obj);
4147
4148         if (obj_priv->madv != I915_MADV_WILLNEED) {
4149                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4150                 ret = -EINVAL;
4151                 goto out;
4152         }
4153
4154         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4155                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4156                           args->handle);
4157                 ret = -EINVAL;
4158                 goto out;
4159         }
4160
4161         obj_priv->user_pin_count++;
4162         obj_priv->pin_filp = file_priv;
4163         if (obj_priv->user_pin_count == 1) {
4164                 ret = i915_gem_object_pin(obj, args->alignment);
4165                 if (ret)
4166                         goto out;
4167         }
4168
4169         /* XXX - flush the CPU caches for pinned objects
4170          * as the X server doesn't manage domains yet
4171          */
4172         i915_gem_object_flush_cpu_write_domain(obj);
4173         args->offset = obj_priv->gtt_offset;
4174 out:
4175         drm_gem_object_unreference(obj);
4176 unlock:
4177         mutex_unlock(&dev->struct_mutex);
4178         return ret;
4179 }
4180
4181 int
4182 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4183                      struct drm_file *file_priv)
4184 {
4185         struct drm_i915_gem_pin *args = data;
4186         struct drm_gem_object *obj;
4187         struct drm_i915_gem_object *obj_priv;
4188         int ret;
4189
4190         ret = i915_mutex_lock_interruptible(dev);
4191         if (ret)
4192                 return ret;
4193
4194         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4195         if (obj == NULL) {
4196                 ret = -ENOENT;
4197                 goto unlock;
4198         }
4199         obj_priv = to_intel_bo(obj);
4200
4201         if (obj_priv->pin_filp != file_priv) {
4202                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4203                           args->handle);
4204                 ret = -EINVAL;
4205                 goto out;
4206         }
4207         obj_priv->user_pin_count--;
4208         if (obj_priv->user_pin_count == 0) {
4209                 obj_priv->pin_filp = NULL;
4210                 i915_gem_object_unpin(obj);
4211         }
4212
4213 out:
4214         drm_gem_object_unreference(obj);
4215 unlock:
4216         mutex_unlock(&dev->struct_mutex);
4217         return ret;
4218 }
4219
4220 int
4221 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4222                     struct drm_file *file_priv)
4223 {
4224         struct drm_i915_gem_busy *args = data;
4225         struct drm_gem_object *obj;
4226         struct drm_i915_gem_object *obj_priv;
4227         int ret;
4228
4229         ret = i915_mutex_lock_interruptible(dev);
4230         if (ret)
4231                 return ret;
4232
4233         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4234         if (obj == NULL) {
4235                 ret = -ENOENT;
4236                 goto unlock;
4237         }
4238         obj_priv = to_intel_bo(obj);
4239
4240         /* Count all active objects as busy, even if they are currently not used
4241          * by the gpu. Users of this interface expect objects to eventually
4242          * become non-busy without any further actions, therefore emit any
4243          * necessary flushes here.
4244          */
4245         args->busy = obj_priv->active;
4246         if (args->busy) {
4247                 /* Unconditionally flush objects, even when the gpu still uses this
4248                  * object. Userspace calling this function indicates that it wants to
4249                  * use this buffer rather sooner than later, so issuing the required
4250                  * flush earlier is beneficial.
4251                  */
4252                 if (obj->write_domain & I915_GEM_GPU_DOMAINS)
4253                         i915_gem_flush_ring(dev, file_priv,
4254                                             obj_priv->ring,
4255                                             0, obj->write_domain);
4256
4257                 /* Update the active list for the hardware's current position.
4258                  * Otherwise this only updates on a delayed timer or when irqs
4259                  * are actually unmasked, and our working set ends up being
4260                  * larger than required.
4261                  */
4262                 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4263
4264                 args->busy = obj_priv->active;
4265         }
4266
4267         drm_gem_object_unreference(obj);
4268 unlock:
4269         mutex_unlock(&dev->struct_mutex);
4270         return ret;
4271 }
4272
4273 int
4274 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4275                         struct drm_file *file_priv)
4276 {
4277     return i915_gem_ring_throttle(dev, file_priv);
4278 }
4279
4280 int
4281 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4282                        struct drm_file *file_priv)
4283 {
4284         struct drm_i915_gem_madvise *args = data;
4285         struct drm_gem_object *obj;
4286         struct drm_i915_gem_object *obj_priv;
4287         int ret;
4288
4289         switch (args->madv) {
4290         case I915_MADV_DONTNEED:
4291         case I915_MADV_WILLNEED:
4292             break;
4293         default:
4294             return -EINVAL;
4295         }
4296
4297         ret = i915_mutex_lock_interruptible(dev);
4298         if (ret)
4299                 return ret;
4300
4301         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4302         if (obj == NULL) {
4303                 ret = -ENOENT;
4304                 goto unlock;
4305         }
4306         obj_priv = to_intel_bo(obj);
4307
4308         if (obj_priv->pin_count) {
4309                 ret = -EINVAL;
4310                 goto out;
4311         }
4312
4313         if (obj_priv->madv != __I915_MADV_PURGED)
4314                 obj_priv->madv = args->madv;
4315
4316         /* if the object is no longer bound, discard its backing storage */
4317         if (i915_gem_object_is_purgeable(obj_priv) &&
4318             obj_priv->gtt_space == NULL)
4319                 i915_gem_object_truncate(obj);
4320
4321         args->retained = obj_priv->madv != __I915_MADV_PURGED;
4322
4323 out:
4324         drm_gem_object_unreference(obj);
4325 unlock:
4326         mutex_unlock(&dev->struct_mutex);
4327         return ret;
4328 }
4329
4330 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4331                                               size_t size)
4332 {
4333         struct drm_i915_private *dev_priv = dev->dev_private;
4334         struct drm_i915_gem_object *obj;
4335
4336         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4337         if (obj == NULL)
4338                 return NULL;
4339
4340         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4341                 kfree(obj);
4342                 return NULL;
4343         }
4344
4345         i915_gem_info_add_obj(dev_priv, size);
4346
4347         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4348         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4349
4350         obj->agp_type = AGP_USER_MEMORY;
4351         obj->base.driver_private = NULL;
4352         obj->fence_reg = I915_FENCE_REG_NONE;
4353         INIT_LIST_HEAD(&obj->mm_list);
4354         INIT_LIST_HEAD(&obj->ring_list);
4355         INIT_LIST_HEAD(&obj->gpu_write_list);
4356         obj->madv = I915_MADV_WILLNEED;
4357
4358         return &obj->base;
4359 }
4360
4361 int i915_gem_init_object(struct drm_gem_object *obj)
4362 {
4363         BUG();
4364
4365         return 0;
4366 }
4367
4368 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4369 {
4370         struct drm_device *dev = obj->dev;
4371         drm_i915_private_t *dev_priv = dev->dev_private;
4372         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4373         int ret;
4374
4375         ret = i915_gem_object_unbind(obj);
4376         if (ret == -ERESTARTSYS) {
4377                 list_move(&obj_priv->mm_list,
4378                           &dev_priv->mm.deferred_free_list);
4379                 return;
4380         }
4381
4382         if (obj_priv->mmap_offset)
4383                 i915_gem_free_mmap_offset(obj);
4384
4385         drm_gem_object_release(obj);
4386         i915_gem_info_remove_obj(dev_priv, obj->size);
4387
4388         kfree(obj_priv->page_cpu_valid);
4389         kfree(obj_priv->bit_17);
4390         kfree(obj_priv);
4391 }
4392
4393 void i915_gem_free_object(struct drm_gem_object *obj)
4394 {
4395         struct drm_device *dev = obj->dev;
4396         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4397
4398         trace_i915_gem_object_destroy(obj);
4399
4400         while (obj_priv->pin_count > 0)
4401                 i915_gem_object_unpin(obj);
4402
4403         if (obj_priv->phys_obj)
4404                 i915_gem_detach_phys_object(dev, obj);
4405
4406         i915_gem_free_object_tail(obj);
4407 }
4408
4409 int
4410 i915_gem_idle(struct drm_device *dev)
4411 {
4412         drm_i915_private_t *dev_priv = dev->dev_private;
4413         int ret;
4414
4415         mutex_lock(&dev->struct_mutex);
4416
4417         if (dev_priv->mm.suspended) {
4418                 mutex_unlock(&dev->struct_mutex);
4419                 return 0;
4420         }
4421
4422         ret = i915_gpu_idle(dev);
4423         if (ret) {
4424                 mutex_unlock(&dev->struct_mutex);
4425                 return ret;
4426         }
4427
4428         /* Under UMS, be paranoid and evict. */
4429         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4430                 ret = i915_gem_evict_inactive(dev);
4431                 if (ret) {
4432                         mutex_unlock(&dev->struct_mutex);
4433                         return ret;
4434                 }
4435         }
4436
4437         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4438          * We need to replace this with a semaphore, or something.
4439          * And not confound mm.suspended!
4440          */
4441         dev_priv->mm.suspended = 1;
4442         del_timer_sync(&dev_priv->hangcheck_timer);
4443
4444         i915_kernel_lost_context(dev);
4445         i915_gem_cleanup_ringbuffer(dev);
4446
4447         mutex_unlock(&dev->struct_mutex);
4448
4449         /* Cancel the retire work handler, which should be idle now. */
4450         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4451
4452         return 0;
4453 }
4454
4455 /*
4456  * 965+ support PIPE_CONTROL commands, which provide finer grained control
4457  * over cache flushing.
4458  */
4459 static int
4460 i915_gem_init_pipe_control(struct drm_device *dev)
4461 {
4462         drm_i915_private_t *dev_priv = dev->dev_private;
4463         struct drm_gem_object *obj;
4464         struct drm_i915_gem_object *obj_priv;
4465         int ret;
4466
4467         obj = i915_gem_alloc_object(dev, 4096);
4468         if (obj == NULL) {
4469                 DRM_ERROR("Failed to allocate seqno page\n");
4470                 ret = -ENOMEM;
4471                 goto err;
4472         }
4473         obj_priv = to_intel_bo(obj);
4474         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4475
4476         ret = i915_gem_object_pin(obj, 4096);
4477         if (ret)
4478                 goto err_unref;
4479
4480         dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4481         dev_priv->seqno_page =  kmap(obj_priv->pages[0]);
4482         if (dev_priv->seqno_page == NULL)
4483                 goto err_unpin;
4484
4485         dev_priv->seqno_obj = obj;
4486         memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4487
4488         return 0;
4489
4490 err_unpin:
4491         i915_gem_object_unpin(obj);
4492 err_unref:
4493         drm_gem_object_unreference(obj);
4494 err:
4495         return ret;
4496 }
4497
4498
4499 static void
4500 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4501 {
4502         drm_i915_private_t *dev_priv = dev->dev_private;
4503         struct drm_gem_object *obj;
4504         struct drm_i915_gem_object *obj_priv;
4505
4506         obj = dev_priv->seqno_obj;
4507         obj_priv = to_intel_bo(obj);
4508         kunmap(obj_priv->pages[0]);
4509         i915_gem_object_unpin(obj);
4510         drm_gem_object_unreference(obj);
4511         dev_priv->seqno_obj = NULL;
4512
4513         dev_priv->seqno_page = NULL;
4514 }
4515
4516 int
4517 i915_gem_init_ringbuffer(struct drm_device *dev)
4518 {
4519         drm_i915_private_t *dev_priv = dev->dev_private;
4520         int ret;
4521
4522         if (HAS_PIPE_CONTROL(dev)) {
4523                 ret = i915_gem_init_pipe_control(dev);
4524                 if (ret)
4525                         return ret;
4526         }
4527
4528         ret = intel_init_render_ring_buffer(dev);
4529         if (ret)
4530                 goto cleanup_pipe_control;
4531
4532         if (HAS_BSD(dev)) {
4533                 ret = intel_init_bsd_ring_buffer(dev);
4534                 if (ret)
4535                         goto cleanup_render_ring;
4536         }
4537
4538         if (HAS_BLT(dev)) {
4539                 ret = intel_init_blt_ring_buffer(dev);
4540                 if (ret)
4541                         goto cleanup_bsd_ring;
4542         }
4543
4544         dev_priv->next_seqno = 1;
4545
4546         return 0;
4547
4548 cleanup_bsd_ring:
4549         intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4550 cleanup_render_ring:
4551         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4552 cleanup_pipe_control:
4553         if (HAS_PIPE_CONTROL(dev))
4554                 i915_gem_cleanup_pipe_control(dev);
4555         return ret;
4556 }
4557
4558 void
4559 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4560 {
4561         drm_i915_private_t *dev_priv = dev->dev_private;
4562
4563         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4564         intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4565         intel_cleanup_ring_buffer(dev, &dev_priv->blt_ring);
4566         if (HAS_PIPE_CONTROL(dev))
4567                 i915_gem_cleanup_pipe_control(dev);
4568 }
4569
4570 int
4571 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4572                        struct drm_file *file_priv)
4573 {
4574         drm_i915_private_t *dev_priv = dev->dev_private;
4575         int ret;
4576
4577         if (drm_core_check_feature(dev, DRIVER_MODESET))
4578                 return 0;
4579
4580         if (atomic_read(&dev_priv->mm.wedged)) {
4581                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4582                 atomic_set(&dev_priv->mm.wedged, 0);
4583         }
4584
4585         mutex_lock(&dev->struct_mutex);
4586         dev_priv->mm.suspended = 0;
4587
4588         ret = i915_gem_init_ringbuffer(dev);
4589         if (ret != 0) {
4590                 mutex_unlock(&dev->struct_mutex);
4591                 return ret;
4592         }
4593
4594         BUG_ON(!list_empty(&dev_priv->mm.active_list));
4595         BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4596         BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list));
4597         BUG_ON(!list_empty(&dev_priv->blt_ring.active_list));
4598         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4599         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4600         BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4601         BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list));
4602         BUG_ON(!list_empty(&dev_priv->blt_ring.request_list));
4603         mutex_unlock(&dev->struct_mutex);
4604
4605         ret = drm_irq_install(dev);
4606         if (ret)
4607                 goto cleanup_ringbuffer;
4608
4609         return 0;
4610
4611 cleanup_ringbuffer:
4612         mutex_lock(&dev->struct_mutex);
4613         i915_gem_cleanup_ringbuffer(dev);
4614         dev_priv->mm.suspended = 1;
4615         mutex_unlock(&dev->struct_mutex);
4616
4617         return ret;
4618 }
4619
4620 int
4621 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4622                        struct drm_file *file_priv)
4623 {
4624         if (drm_core_check_feature(dev, DRIVER_MODESET))
4625                 return 0;
4626
4627         drm_irq_uninstall(dev);
4628         return i915_gem_idle(dev);
4629 }
4630
4631 void
4632 i915_gem_lastclose(struct drm_device *dev)
4633 {
4634         int ret;
4635
4636         if (drm_core_check_feature(dev, DRIVER_MODESET))
4637                 return;
4638
4639         ret = i915_gem_idle(dev);
4640         if (ret)
4641                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4642 }
4643
4644 static void
4645 init_ring_lists(struct intel_ring_buffer *ring)
4646 {
4647         INIT_LIST_HEAD(&ring->active_list);
4648         INIT_LIST_HEAD(&ring->request_list);
4649         INIT_LIST_HEAD(&ring->gpu_write_list);
4650 }
4651
4652 void
4653 i915_gem_load(struct drm_device *dev)
4654 {
4655         int i;
4656         drm_i915_private_t *dev_priv = dev->dev_private;
4657
4658         INIT_LIST_HEAD(&dev_priv->mm.active_list);
4659         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4660         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4661         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
4662         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4663         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4664         init_ring_lists(&dev_priv->render_ring);
4665         init_ring_lists(&dev_priv->bsd_ring);
4666         init_ring_lists(&dev_priv->blt_ring);
4667         for (i = 0; i < 16; i++)
4668                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4669         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4670                           i915_gem_retire_work_handler);
4671         init_completion(&dev_priv->error_completion);
4672         spin_lock(&shrink_list_lock);
4673         list_add(&dev_priv->mm.shrink_list, &shrink_list);
4674         spin_unlock(&shrink_list_lock);
4675
4676         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4677         if (IS_GEN3(dev)) {
4678                 u32 tmp = I915_READ(MI_ARB_STATE);
4679                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4680                         /* arb state is a masked write, so set bit + bit in mask */
4681                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4682                         I915_WRITE(MI_ARB_STATE, tmp);
4683                 }
4684         }
4685
4686         /* Old X drivers will take 0-2 for front, back, depth buffers */
4687         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4688                 dev_priv->fence_reg_start = 3;
4689
4690         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4691                 dev_priv->num_fence_regs = 16;
4692         else
4693                 dev_priv->num_fence_regs = 8;
4694
4695         /* Initialize fence registers to zero */
4696         switch (INTEL_INFO(dev)->gen) {
4697         case 6:
4698                 for (i = 0; i < 16; i++)
4699                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
4700                 break;
4701         case 5:
4702         case 4:
4703                 for (i = 0; i < 16; i++)
4704                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4705                 break;
4706         case 3:
4707                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4708                         for (i = 0; i < 8; i++)
4709                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4710         case 2:
4711                 for (i = 0; i < 8; i++)
4712                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4713                 break;
4714         }
4715         i915_gem_detect_bit_6_swizzle(dev);
4716         init_waitqueue_head(&dev_priv->pending_flip_queue);
4717 }
4718
4719 /*
4720  * Create a physically contiguous memory object for this object
4721  * e.g. for cursor + overlay regs
4722  */
4723 static int i915_gem_init_phys_object(struct drm_device *dev,
4724                                      int id, int size, int align)
4725 {
4726         drm_i915_private_t *dev_priv = dev->dev_private;
4727         struct drm_i915_gem_phys_object *phys_obj;
4728         int ret;
4729
4730         if (dev_priv->mm.phys_objs[id - 1] || !size)
4731                 return 0;
4732
4733         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4734         if (!phys_obj)
4735                 return -ENOMEM;
4736
4737         phys_obj->id = id;
4738
4739         phys_obj->handle = drm_pci_alloc(dev, size, align);
4740         if (!phys_obj->handle) {
4741                 ret = -ENOMEM;
4742                 goto kfree_obj;
4743         }
4744 #ifdef CONFIG_X86
4745         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4746 #endif
4747
4748         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4749
4750         return 0;
4751 kfree_obj:
4752         kfree(phys_obj);
4753         return ret;
4754 }
4755
4756 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4757 {
4758         drm_i915_private_t *dev_priv = dev->dev_private;
4759         struct drm_i915_gem_phys_object *phys_obj;
4760
4761         if (!dev_priv->mm.phys_objs[id - 1])
4762                 return;
4763
4764         phys_obj = dev_priv->mm.phys_objs[id - 1];
4765         if (phys_obj->cur_obj) {
4766                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4767         }
4768
4769 #ifdef CONFIG_X86
4770         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4771 #endif
4772         drm_pci_free(dev, phys_obj->handle);
4773         kfree(phys_obj);
4774         dev_priv->mm.phys_objs[id - 1] = NULL;
4775 }
4776
4777 void i915_gem_free_all_phys_object(struct drm_device *dev)
4778 {
4779         int i;
4780
4781         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4782                 i915_gem_free_phys_object(dev, i);
4783 }
4784
4785 void i915_gem_detach_phys_object(struct drm_device *dev,
4786                                  struct drm_gem_object *obj)
4787 {
4788         struct drm_i915_gem_object *obj_priv;
4789         int i;
4790         int ret;
4791         int page_count;
4792
4793         obj_priv = to_intel_bo(obj);
4794         if (!obj_priv->phys_obj)
4795                 return;
4796
4797         ret = i915_gem_object_get_pages(obj, 0);
4798         if (ret)
4799                 goto out;
4800
4801         page_count = obj->size / PAGE_SIZE;
4802
4803         for (i = 0; i < page_count; i++) {
4804                 char *dst = kmap_atomic(obj_priv->pages[i]);
4805                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4806
4807                 memcpy(dst, src, PAGE_SIZE);
4808                 kunmap_atomic(dst);
4809         }
4810         drm_clflush_pages(obj_priv->pages, page_count);
4811         drm_agp_chipset_flush(dev);
4812
4813         i915_gem_object_put_pages(obj);
4814 out:
4815         obj_priv->phys_obj->cur_obj = NULL;
4816         obj_priv->phys_obj = NULL;
4817 }
4818
4819 int
4820 i915_gem_attach_phys_object(struct drm_device *dev,
4821                             struct drm_gem_object *obj,
4822                             int id,
4823                             int align)
4824 {
4825         drm_i915_private_t *dev_priv = dev->dev_private;
4826         struct drm_i915_gem_object *obj_priv;
4827         int ret = 0;
4828         int page_count;
4829         int i;
4830
4831         if (id > I915_MAX_PHYS_OBJECT)
4832                 return -EINVAL;
4833
4834         obj_priv = to_intel_bo(obj);
4835
4836         if (obj_priv->phys_obj) {
4837                 if (obj_priv->phys_obj->id == id)
4838                         return 0;
4839                 i915_gem_detach_phys_object(dev, obj);
4840         }
4841
4842         /* create a new object */
4843         if (!dev_priv->mm.phys_objs[id - 1]) {
4844                 ret = i915_gem_init_phys_object(dev, id,
4845                                                 obj->size, align);
4846                 if (ret) {
4847                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4848                         goto out;
4849                 }
4850         }
4851
4852         /* bind to the object */
4853         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4854         obj_priv->phys_obj->cur_obj = obj;
4855
4856         ret = i915_gem_object_get_pages(obj, 0);
4857         if (ret) {
4858                 DRM_ERROR("failed to get page list\n");
4859                 goto out;
4860         }
4861
4862         page_count = obj->size / PAGE_SIZE;
4863
4864         for (i = 0; i < page_count; i++) {
4865                 char *src = kmap_atomic(obj_priv->pages[i]);
4866                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4867
4868                 memcpy(dst, src, PAGE_SIZE);
4869                 kunmap_atomic(src);
4870         }
4871
4872         i915_gem_object_put_pages(obj);
4873
4874         return 0;
4875 out:
4876         return ret;
4877 }
4878
4879 static int
4880 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4881                      struct drm_i915_gem_pwrite *args,
4882                      struct drm_file *file_priv)
4883 {
4884         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4885         void *vaddr = obj_priv->phys_obj->handle->vaddr + args->offset;
4886         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4887
4888         DRM_DEBUG_DRIVER("vaddr %p, %lld\n", vaddr, args->size);
4889
4890         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4891                 unsigned long unwritten;
4892
4893                 /* The physical object once assigned is fixed for the lifetime
4894                  * of the obj, so we can safely drop the lock and continue
4895                  * to access vaddr.
4896                  */
4897                 mutex_unlock(&dev->struct_mutex);
4898                 unwritten = copy_from_user(vaddr, user_data, args->size);
4899                 mutex_lock(&dev->struct_mutex);
4900                 if (unwritten)
4901                         return -EFAULT;
4902         }
4903
4904         drm_agp_chipset_flush(dev);
4905         return 0;
4906 }
4907
4908 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4909 {
4910         struct drm_i915_file_private *file_priv = file->driver_priv;
4911
4912         /* Clean up our request list when the client is going away, so that
4913          * later retire_requests won't dereference our soon-to-be-gone
4914          * file_priv.
4915          */
4916         spin_lock(&file_priv->mm.lock);
4917         while (!list_empty(&file_priv->mm.request_list)) {
4918                 struct drm_i915_gem_request *request;
4919
4920                 request = list_first_entry(&file_priv->mm.request_list,
4921                                            struct drm_i915_gem_request,
4922                                            client_list);
4923                 list_del(&request->client_list);
4924                 request->file_priv = NULL;
4925         }
4926         spin_unlock(&file_priv->mm.lock);
4927 }
4928
4929 static int
4930 i915_gpu_is_active(struct drm_device *dev)
4931 {
4932         drm_i915_private_t *dev_priv = dev->dev_private;
4933         int lists_empty;
4934
4935         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4936                       list_empty(&dev_priv->mm.active_list);
4937
4938         return !lists_empty;
4939 }
4940
4941 static int
4942 i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
4943 {
4944         drm_i915_private_t *dev_priv, *next_dev;
4945         struct drm_i915_gem_object *obj_priv, *next_obj;
4946         int cnt = 0;
4947         int would_deadlock = 1;
4948
4949         /* "fast-path" to count number of available objects */
4950         if (nr_to_scan == 0) {
4951                 spin_lock(&shrink_list_lock);
4952                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4953                         struct drm_device *dev = dev_priv->dev;
4954
4955                         if (mutex_trylock(&dev->struct_mutex)) {
4956                                 list_for_each_entry(obj_priv,
4957                                                     &dev_priv->mm.inactive_list,
4958                                                     mm_list)
4959                                         cnt++;
4960                                 mutex_unlock(&dev->struct_mutex);
4961                         }
4962                 }
4963                 spin_unlock(&shrink_list_lock);
4964
4965                 return (cnt / 100) * sysctl_vfs_cache_pressure;
4966         }
4967
4968         spin_lock(&shrink_list_lock);
4969
4970 rescan:
4971         /* first scan for clean buffers */
4972         list_for_each_entry_safe(dev_priv, next_dev,
4973                                  &shrink_list, mm.shrink_list) {
4974                 struct drm_device *dev = dev_priv->dev;
4975
4976                 if (! mutex_trylock(&dev->struct_mutex))
4977                         continue;
4978
4979                 spin_unlock(&shrink_list_lock);
4980                 i915_gem_retire_requests(dev);
4981
4982                 list_for_each_entry_safe(obj_priv, next_obj,
4983                                          &dev_priv->mm.inactive_list,
4984                                          mm_list) {
4985                         if (i915_gem_object_is_purgeable(obj_priv)) {
4986                                 i915_gem_object_unbind(&obj_priv->base);
4987                                 if (--nr_to_scan <= 0)
4988                                         break;
4989                         }
4990                 }
4991
4992                 spin_lock(&shrink_list_lock);
4993                 mutex_unlock(&dev->struct_mutex);
4994
4995                 would_deadlock = 0;
4996
4997                 if (nr_to_scan <= 0)
4998                         break;
4999         }
5000
5001         /* second pass, evict/count anything still on the inactive list */
5002         list_for_each_entry_safe(dev_priv, next_dev,
5003                                  &shrink_list, mm.shrink_list) {
5004                 struct drm_device *dev = dev_priv->dev;
5005
5006                 if (! mutex_trylock(&dev->struct_mutex))
5007                         continue;
5008
5009                 spin_unlock(&shrink_list_lock);
5010
5011                 list_for_each_entry_safe(obj_priv, next_obj,
5012                                          &dev_priv->mm.inactive_list,
5013                                          mm_list) {
5014                         if (nr_to_scan > 0) {
5015                                 i915_gem_object_unbind(&obj_priv->base);
5016                                 nr_to_scan--;
5017                         } else
5018                                 cnt++;
5019                 }
5020
5021                 spin_lock(&shrink_list_lock);
5022                 mutex_unlock(&dev->struct_mutex);
5023
5024                 would_deadlock = 0;
5025         }
5026
5027         if (nr_to_scan) {
5028                 int active = 0;
5029
5030                 /*
5031                  * We are desperate for pages, so as a last resort, wait
5032                  * for the GPU to finish and discard whatever we can.
5033                  * This has a dramatic impact to reduce the number of
5034                  * OOM-killer events whilst running the GPU aggressively.
5035                  */
5036                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5037                         struct drm_device *dev = dev_priv->dev;
5038
5039                         if (!mutex_trylock(&dev->struct_mutex))
5040                                 continue;
5041
5042                         spin_unlock(&shrink_list_lock);
5043
5044                         if (i915_gpu_is_active(dev)) {
5045                                 i915_gpu_idle(dev);
5046                                 active++;
5047                         }
5048
5049                         spin_lock(&shrink_list_lock);
5050                         mutex_unlock(&dev->struct_mutex);
5051                 }
5052
5053                 if (active)
5054                         goto rescan;
5055         }
5056
5057         spin_unlock(&shrink_list_lock);
5058
5059         if (would_deadlock)
5060                 return -1;
5061         else if (cnt > 0)
5062                 return (cnt / 100) * sysctl_vfs_cache_pressure;
5063         else
5064                 return 0;
5065 }
5066
5067 static struct shrinker shrinker = {
5068         .shrink = i915_gem_shrink,
5069         .seeks = DEFAULT_SEEKS,
5070 };
5071
5072 __init void
5073 i915_gem_shrinker_init(void)
5074 {
5075     register_shrinker(&shrinker);
5076 }
5077
5078 __exit void
5079 i915_gem_shrinker_exit(void)
5080 {
5081     unregister_shrinker(&shrinker);
5082 }