drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/shmem_fs.h>
  35 #include <linux/slab.h>
  36 #include <linux/swap.h>
  37 #include <linux/pci.h>
  38
  39 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  42 static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  43                                                           bool write);
  44 static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
  45                                                                   uint64_t offset,
  46                                                                   uint64_t size);
  47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
  48 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  49                                                     unsigned alignment,
  50                                                     bool map_and_fenceable);
  51 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  52                                      struct drm_i915_fence_reg *reg);
  53 static int i915_gem_phys_pwrite(struct drm_device *dev,
  54                                 struct drm_i915_gem_object *obj,
  55                                 struct drm_i915_gem_pwrite *args,
  56                                 struct drm_file *file);
  57 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
  58
  59 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  60                                     struct shrink_control *sc);
  61 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  62
  63 /* some bookkeeping */
  64 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  65                                   size_t size)
  66 {
  67         dev_priv->mm.object_count++;
  68         dev_priv->mm.object_memory += size;
  69 }
  70
  71 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  72                                      size_t size)
  73 {
  74         dev_priv->mm.object_count--;
  75         dev_priv->mm.object_memory -= size;
  76 }
  77
  78 static int
  79 i915_gem_wait_for_error(struct drm_device *dev)
  80 {
  81         struct drm_i915_private *dev_priv = dev->dev_private;
  82         struct completion *x = &dev_priv->error_completion;
  83         unsigned long flags;
  84         int ret;
  85
  86         if (!atomic_read(&dev_priv->mm.wedged))
  87                 return 0;
  88
  89         ret = wait_for_completion_interruptible(x);
  90         if (ret)
  91                 return ret;
  92
  93         if (atomic_read(&dev_priv->mm.wedged)) {
  94                 /* GPU is hung, bump the completion count to account for
  95                  * the token we just consumed so that we never hit zero and
  96                  * end up waiting upon a subsequent completion event that
  97                  * will never happen.
  98                  */
  99                 spin_lock_irqsave(&x->wait.lock, flags);
 100                 x->done++;
 101                 spin_unlock_irqrestore(&x->wait.lock, flags);
 102         }
 103         return 0;
 104 }
 105
 106 int i915_mutex_lock_interruptible(struct drm_device *dev)
 107 {
 108         int ret;
 109
 110         ret = i915_gem_wait_for_error(dev);
 111         if (ret)
 112                 return ret;
 113
 114         ret = mutex_lock_interruptible(&dev->struct_mutex);
 115         if (ret)
 116                 return ret;
 117
 118         WARN_ON(i915_verify_lists(dev));
 119         return 0;
 120 }
 121
 122 static inline bool
 123 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 124 {
 125         return obj->gtt_space && !obj->active && obj->pin_count == 0;
 126 }
 127
 128 void i915_gem_do_init(struct drm_device *dev,
 129                       unsigned long start,
 130                       unsigned long mappable_end,
 131                       unsigned long end)
 132 {
 133         drm_i915_private_t *dev_priv = dev->dev_private;
 134
 135         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 136
 137         dev_priv->mm.gtt_start = start;
 138         dev_priv->mm.gtt_mappable_end = mappable_end;
 139         dev_priv->mm.gtt_end = end;
 140         dev_priv->mm.gtt_total = end - start;
 141         dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
 142
 143         /* Take over this portion of the GTT */
 144         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 145 }
 146
 147 int
 148 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 149                     struct drm_file *file)
 150 {
 151         struct drm_i915_gem_init *args = data;
 152
 153         if (args->gtt_start >= args->gtt_end ||
 154             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 155                 return -EINVAL;
 156
 157         mutex_lock(&dev->struct_mutex);
 158         i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
 159         mutex_unlock(&dev->struct_mutex);
 160
 161         return 0;
 162 }
 163
 164 int
 165 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 166                             struct drm_file *file)
 167 {
 168         struct drm_i915_private *dev_priv = dev->dev_private;
 169         struct drm_i915_gem_get_aperture *args = data;
 170         struct drm_i915_gem_object *obj;
 171         size_t pinned;
 172
 173         if (!(dev->driver->driver_features & DRIVER_GEM))
 174                 return -ENODEV;
 175
 176         pinned = 0;
 177         mutex_lock(&dev->struct_mutex);
 178         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 179                 pinned += obj->gtt_space->size;
 180         mutex_unlock(&dev->struct_mutex);
 181
 182         args->aper_size = dev_priv->mm.gtt_total;
 183         args->aper_available_size = args->aper_size - pinned;
 184
 185         return 0;
 186 }
 187
 188 static int
 189 i915_gem_create(struct drm_file *file,
 190                 struct drm_device *dev,
 191                 uint64_t size,
 192                 uint32_t *handle_p)
 193 {
 194         struct drm_i915_gem_object *obj;
 195         int ret;
 196         u32 handle;
 197
 198         size = roundup(size, PAGE_SIZE);
 199         if (size == 0)
 200                 return -EINVAL;
 201
 202         /* Allocate the new object */
 203         obj = i915_gem_alloc_object(dev, size);
 204         if (obj == NULL)
 205                 return -ENOMEM;
 206
 207         ret = drm_gem_handle_create(file, &obj->base, &handle);
 208         if (ret) {
 209                 drm_gem_object_release(&obj->base);
 210                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 211                 kfree(obj);
 212                 return ret;
 213         }
 214
 215         /* drop reference from allocate - handle holds it now */
 216         drm_gem_object_unreference(&obj->base);
 217         trace_i915_gem_object_create(obj);
 218
 219         *handle_p = handle;
 220         return 0;
 221 }
 222
 223 int
 224 i915_gem_dumb_create(struct drm_file *file,
 225                      struct drm_device *dev,
 226                      struct drm_mode_create_dumb *args)
 227 {
 228         /* have to work out size/pitch and return them */
 229         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 230         args->size = args->pitch * args->height;
 231         return i915_gem_create(file, dev,
 232                                args->size, &args->handle);
 233 }
 234
 235 int i915_gem_dumb_destroy(struct drm_file *file,
 236                           struct drm_device *dev,
 237                           uint32_t handle)
 238 {
 239         return drm_gem_handle_delete(file, handle);
 240 }
 241
 242 /**
 243  * Creates a new mm object and returns a handle to it.
 244  */
 245 int
 246 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 247                       struct drm_file *file)
 248 {
 249         struct drm_i915_gem_create *args = data;
 250         return i915_gem_create(file, dev,
 251                                args->size, &args->handle);
 252 }
 253
 254 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
 255 {
 256         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 257
 258         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 259                 obj->tiling_mode != I915_TILING_NONE;
 260 }
 261
 262 /**
 263  * This is the fast shmem pread path, which attempts to copy_from_user directly
 264  * from the backing pages of the object to the user's address space.  On a
 265  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 266  */
 267 static int
 268 i915_gem_shmem_pread_fast(struct drm_device *dev,
 269                           struct drm_i915_gem_object *obj,
 270                           struct drm_i915_gem_pread *args,
 271                           struct drm_file *file)
 272 {
 273         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 274         ssize_t remain;
 275         loff_t offset;
 276         char __user *user_data;
 277         int page_offset, page_length;
 278
 279         user_data = (char __user *) (uintptr_t) args->data_ptr;
 280         remain = args->size;
 281
 282         offset = args->offset;
 283
 284         while (remain > 0) {
 285                 struct page *page;
 286                 char *vaddr;
 287                 int ret;
 288
 289                 /* Operation in this page
 290                  *
 291                  * page_offset = offset within page
 292                  * page_length = bytes to copy for this page
 293                  */
 294                 page_offset = offset_in_page(offset);
 295                 page_length = remain;
 296                 if ((page_offset + remain) > PAGE_SIZE)
 297                         page_length = PAGE_SIZE - page_offset;
 298
 299                 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
 300                 if (IS_ERR(page))
 301                         return PTR_ERR(page);
 302
 303                 vaddr = kmap_atomic(page);
 304                 ret = __copy_to_user_inatomic(user_data,
 305                                               vaddr + page_offset,
 306                                               page_length);
 307                 kunmap_atomic(vaddr);
 308
 309                 mark_page_accessed(page);
 310                 page_cache_release(page);
 311                 if (ret)
 312                         return -EFAULT;
 313
 314                 remain -= page_length;
 315                 user_data += page_length;
 316                 offset += page_length;
 317         }
 318
 319         return 0;
 320 }
 321
 322 static inline int
 323 __copy_to_user_swizzled(char __user *cpu_vaddr,
 324                         const char *gpu_vaddr, int gpu_offset,
 325                         int length)
 326 {
 327         int ret, cpu_offset = 0;
 328
 329         while (length > 0) {
 330                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 331                 int this_length = min(cacheline_end - gpu_offset, length);
 332                 int swizzled_gpu_offset = gpu_offset ^ 64;
 333
 334                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 335                                      gpu_vaddr + swizzled_gpu_offset,
 336                                      this_length);
 337                 if (ret)
 338                         return ret + length;
 339
 340                 cpu_offset += this_length;
 341                 gpu_offset += this_length;
 342                 length -= this_length;
 343         }
 344
 345         return 0;
 346 }
 347
 348 static inline int
 349 __copy_from_user_swizzled(char __user *gpu_vaddr, int gpu_offset,
 350                           const char *cpu_vaddr,
 351                           int length)
 352 {
 353         int ret, cpu_offset = 0;
 354
 355         while (length > 0) {
 356                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 357                 int this_length = min(cacheline_end - gpu_offset, length);
 358                 int swizzled_gpu_offset = gpu_offset ^ 64;
 359
 360                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 361                                        cpu_vaddr + cpu_offset,
 362                                        this_length);
 363                 if (ret)
 364                         return ret + length;
 365
 366                 cpu_offset += this_length;
 367                 gpu_offset += this_length;
 368                 length -= this_length;
 369         }
 370
 371         return 0;
 372 }
 373
 374 /**
 375  * This is the fallback shmem pread path, which allocates temporary storage
 376  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 377  * can copy out of the object's backing pages while holding the struct mutex
 378  * and not take page faults.
 379  */
 380 static int
 381 i915_gem_shmem_pread_slow(struct drm_device *dev,
 382                           struct drm_i915_gem_object *obj,
 383                           struct drm_i915_gem_pread *args,
 384                           struct drm_file *file)
 385 {
 386         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 387         char __user *user_data;
 388         ssize_t remain;
 389         loff_t offset;
 390         int shmem_page_offset, page_length, ret;
 391         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 392
 393         user_data = (char __user *) (uintptr_t) args->data_ptr;
 394         remain = args->size;
 395
 396         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 397
 398         offset = args->offset;
 399
 400         mutex_unlock(&dev->struct_mutex);
 401
 402         while (remain > 0) {
 403                 struct page *page;
 404                 char *vaddr;
 405
 406                 /* Operation in this page
 407                  *
 408                  * shmem_page_offset = offset within page in shmem file
 409                  * page_length = bytes to copy for this page
 410                  */
 411                 shmem_page_offset = offset_in_page(offset);
 412                 page_length = remain;
 413                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 414                         page_length = PAGE_SIZE - shmem_page_offset;
 415
 416                 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
 417                 if (IS_ERR(page)) {
 418                         ret = PTR_ERR(page);
 419                         goto out;
 420                 }
 421
 422                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 423                         (page_to_phys(page) & (1 << 17)) != 0;
 424
 425                 vaddr = kmap(page);
 426                 if (page_do_bit17_swizzling)
 427                         ret = __copy_to_user_swizzled(user_data,
 428                                                       vaddr, shmem_page_offset,
 429                                                       page_length);
 430                 else
 431                         ret = __copy_to_user(user_data,
 432                                              vaddr + shmem_page_offset,
 433                                              page_length);
 434                 kunmap(page);
 435
 436                 mark_page_accessed(page);
 437                 page_cache_release(page);
 438
 439                 if (ret) {
 440                         ret = -EFAULT;
 441                         goto out;
 442                 }
 443
 444                 remain -= page_length;
 445                 user_data += page_length;
 446                 offset += page_length;
 447         }
 448
 449 out:
 450         mutex_lock(&dev->struct_mutex);
 451         /* Fixup: Kill any reinstated backing storage pages */
 452         if (obj->madv == __I915_MADV_PURGED)
 453                 i915_gem_object_truncate(obj);
 454
 455         return ret;
 456 }
 457
 458 /**
 459  * Reads data from the object referenced by handle.
 460  *
 461  * On error, the contents of *data are undefined.
 462  */
 463 int
 464 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 465                      struct drm_file *file)
 466 {
 467         struct drm_i915_gem_pread *args = data;
 468         struct drm_i915_gem_object *obj;
 469         int ret = 0;
 470
 471         if (args->size == 0)
 472                 return 0;
 473
 474         if (!access_ok(VERIFY_WRITE,
 475                        (char __user *)(uintptr_t)args->data_ptr,
 476                        args->size))
 477                 return -EFAULT;
 478
 479         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 480                                        args->size);
 481         if (ret)
 482                 return -EFAULT;
 483
 484         ret = i915_mutex_lock_interruptible(dev);
 485         if (ret)
 486                 return ret;
 487
 488         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 489         if (&obj->base == NULL) {
 490                 ret = -ENOENT;
 491                 goto unlock;
 492         }
 493
 494         /* Bounds check source.  */
 495         if (args->offset > obj->base.size ||
 496             args->size > obj->base.size - args->offset) {
 497                 ret = -EINVAL;
 498                 goto out;
 499         }
 500
 501         trace_i915_gem_object_pread(obj, args->offset, args->size);
 502
 503         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 504                                                         args->offset,
 505                                                         args->size);
 506         if (ret)
 507                 goto out;
 508
 509         ret = -EFAULT;
 510         if (!i915_gem_object_needs_bit17_swizzle(obj))
 511                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
 512         if (ret == -EFAULT)
 513                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
 514
 515 out:
 516         drm_gem_object_unreference(&obj->base);
 517 unlock:
 518         mutex_unlock(&dev->struct_mutex);
 519         return ret;
 520 }
 521
 522 /* This is the fast write path which cannot handle
 523  * page faults in the source data
 524  */
 525
 526 static inline int
 527 fast_user_write(struct io_mapping *mapping,
 528                 loff_t page_base, int page_offset,
 529                 char __user *user_data,
 530                 int length)
 531 {
 532         char *vaddr_atomic;
 533         unsigned long unwritten;
 534
 535         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 536         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 537                                                       user_data, length);
 538         io_mapping_unmap_atomic(vaddr_atomic);
 539         return unwritten;
 540 }
 541
 542 /* Here's the write path which can sleep for
 543  * page faults
 544  */
 545
 546 static inline void
 547 slow_kernel_write(struct io_mapping *mapping,
 548                   loff_t gtt_base, int gtt_offset,
 549                   struct page *user_page, int user_offset,
 550                   int length)
 551 {
 552         char __iomem *dst_vaddr;
 553         char *src_vaddr;
 554
 555         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 556         src_vaddr = kmap(user_page);
 557
 558         memcpy_toio(dst_vaddr + gtt_offset,
 559                     src_vaddr + user_offset,
 560                     length);
 561
 562         kunmap(user_page);
 563         io_mapping_unmap(dst_vaddr);
 564 }
 565
 566 /**
 567  * This is the fast pwrite path, where we copy the data directly from the
 568  * user into the GTT, uncached.
 569  */
 570 static int
 571 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 572                          struct drm_i915_gem_object *obj,
 573                          struct drm_i915_gem_pwrite *args,
 574                          struct drm_file *file)
 575 {
 576         drm_i915_private_t *dev_priv = dev->dev_private;
 577         ssize_t remain;
 578         loff_t offset, page_base;
 579         char __user *user_data;
 580         int page_offset, page_length;
 581
 582         user_data = (char __user *) (uintptr_t) args->data_ptr;
 583         remain = args->size;
 584
 585         offset = obj->gtt_offset + args->offset;
 586
 587         while (remain > 0) {
 588                 /* Operation in this page
 589                  *
 590                  * page_base = page offset within aperture
 591                  * page_offset = offset within page
 592                  * page_length = bytes to copy for this page
 593                  */
 594                 page_base = offset & PAGE_MASK;
 595                 page_offset = offset_in_page(offset);
 596                 page_length = remain;
 597                 if ((page_offset + remain) > PAGE_SIZE)
 598                         page_length = PAGE_SIZE - page_offset;
 599
 600                 /* If we get a fault while copying data, then (presumably) our
 601                  * source page isn't available.  Return the error and we'll
 602                  * retry in the slow path.
 603                  */
 604                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 605                                     page_offset, user_data, page_length))
 606                         return -EFAULT;
 607
 608                 remain -= page_length;
 609                 user_data += page_length;
 610                 offset += page_length;
 611         }
 612
 613         return 0;
 614 }
 615
 616 /**
 617  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 618  * the memory and maps it using kmap_atomic for copying.
 619  *
 620  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 621  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 622  */
 623 static int
 624 i915_gem_gtt_pwrite_slow(struct drm_device *dev,
 625                          struct drm_i915_gem_object *obj,
 626                          struct drm_i915_gem_pwrite *args,
 627                          struct drm_file *file)
 628 {
 629         drm_i915_private_t *dev_priv = dev->dev_private;
 630         ssize_t remain;
 631         loff_t gtt_page_base, offset;
 632         loff_t first_data_page, last_data_page, num_pages;
 633         loff_t pinned_pages, i;
 634         struct page **user_pages;
 635         struct mm_struct *mm = current->mm;
 636         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 637         int ret;
 638         uint64_t data_ptr = args->data_ptr;
 639
 640         remain = args->size;
 641
 642         /* Pin the user pages containing the data.  We can't fault while
 643          * holding the struct mutex, and all of the pwrite implementations
 644          * want to hold it while dereferencing the user data.
 645          */
 646         first_data_page = data_ptr / PAGE_SIZE;
 647         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 648         num_pages = last_data_page - first_data_page + 1;
 649
 650         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 651         if (user_pages == NULL)
 652                 return -ENOMEM;
 653
 654         mutex_unlock(&dev->struct_mutex);
 655         down_read(&mm->mmap_sem);
 656         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 657                                       num_pages, 0, 0, user_pages, NULL);
 658         up_read(&mm->mmap_sem);
 659         mutex_lock(&dev->struct_mutex);
 660         if (pinned_pages < num_pages) {
 661                 ret = -EFAULT;
 662                 goto out_unpin_pages;
 663         }
 664
 665         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 666         if (ret)
 667                 goto out_unpin_pages;
 668
 669         ret = i915_gem_object_put_fence(obj);
 670         if (ret)
 671                 goto out_unpin_pages;
 672
 673         offset = obj->gtt_offset + args->offset;
 674
 675         while (remain > 0) {
 676                 /* Operation in this page
 677                  *
 678                  * gtt_page_base = page offset within aperture
 679                  * gtt_page_offset = offset within page in aperture
 680                  * data_page_index = page number in get_user_pages return
 681                  * data_page_offset = offset with data_page_index page.
 682                  * page_length = bytes to copy for this page
 683                  */
 684                 gtt_page_base = offset & PAGE_MASK;
 685                 gtt_page_offset = offset_in_page(offset);
 686                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 687                 data_page_offset = offset_in_page(data_ptr);
 688
 689                 page_length = remain;
 690                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 691                         page_length = PAGE_SIZE - gtt_page_offset;
 692                 if ((data_page_offset + page_length) > PAGE_SIZE)
 693                         page_length = PAGE_SIZE - data_page_offset;
 694
 695                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 696                                   gtt_page_base, gtt_page_offset,
 697                                   user_pages[data_page_index],
 698                                   data_page_offset,
 699                                   page_length);
 700
 701                 remain -= page_length;
 702                 offset += page_length;
 703                 data_ptr += page_length;
 704         }
 705
 706 out_unpin_pages:
 707         for (i = 0; i < pinned_pages; i++)
 708                 page_cache_release(user_pages[i]);
 709         drm_free_large(user_pages);
 710
 711         return ret;
 712 }
 713
 714 /**
 715  * This is the fast shmem pwrite path, which attempts to directly
 716  * copy_from_user into the kmapped pages backing the object.
 717  */
 718 static int
 719 i915_gem_shmem_pwrite_fast(struct drm_device *dev,
 720                            struct drm_i915_gem_object *obj,
 721                            struct drm_i915_gem_pwrite *args,
 722                            struct drm_file *file)
 723 {
 724         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 725         ssize_t remain;
 726         loff_t offset;
 727         char __user *user_data;
 728         int page_offset, page_length;
 729
 730         user_data = (char __user *) (uintptr_t) args->data_ptr;
 731         remain = args->size;
 732
 733         offset = args->offset;
 734         obj->dirty = 1;
 735
 736         while (remain > 0) {
 737                 struct page *page;
 738                 char *vaddr;
 739                 int ret;
 740
 741                 /* Operation in this page
 742                  *
 743                  * page_offset = offset within page
 744                  * page_length = bytes to copy for this page
 745                  */
 746                 page_offset = offset_in_page(offset);
 747                 page_length = remain;
 748                 if ((page_offset + remain) > PAGE_SIZE)
 749                         page_length = PAGE_SIZE - page_offset;
 750
 751                 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
 752                 if (IS_ERR(page))
 753                         return PTR_ERR(page);
 754
 755                 vaddr = kmap_atomic(page);
 756                 ret = __copy_from_user_inatomic(vaddr + page_offset,
 757                                                 user_data,
 758                                                 page_length);
 759                 kunmap_atomic(vaddr);
 760
 761                 set_page_dirty(page);
 762                 mark_page_accessed(page);
 763                 page_cache_release(page);
 764
 765                 /* If we get a fault while copying data, then (presumably) our
 766                  * source page isn't available.  Return the error and we'll
 767                  * retry in the slow path.
 768                  */
 769                 if (ret)
 770                         return -EFAULT;
 771
 772                 remain -= page_length;
 773                 user_data += page_length;
 774                 offset += page_length;
 775         }
 776
 777         return 0;
 778 }
 779
 780 /**
 781  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 782  * the memory and maps it using kmap_atomic for copying.
 783  *
 784  * This avoids taking mmap_sem for faulting on the user's address while the
 785  * struct_mutex is held.
 786  */
 787 static int
 788 i915_gem_shmem_pwrite_slow(struct drm_device *dev,
 789                            struct drm_i915_gem_object *obj,
 790                            struct drm_i915_gem_pwrite *args,
 791                            struct drm_file *file)
 792 {
 793         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 794         ssize_t remain;
 795         loff_t offset;
 796         char __user *user_data;
 797         int shmem_page_offset, page_length, ret;
 798         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 799
 800         user_data = (char __user *) (uintptr_t) args->data_ptr;
 801         remain = args->size;
 802
 803         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 804
 805         offset = args->offset;
 806         obj->dirty = 1;
 807
 808         mutex_unlock(&dev->struct_mutex);
 809
 810         while (remain > 0) {
 811                 struct page *page;
 812                 char *vaddr;
 813
 814                 /* Operation in this page
 815                  *
 816                  * shmem_page_offset = offset within page in shmem file
 817                  * page_length = bytes to copy for this page
 818                  */
 819                 shmem_page_offset = offset_in_page(offset);
 820
 821                 page_length = remain;
 822                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 823                         page_length = PAGE_SIZE - shmem_page_offset;
 824
 825                 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
 826                 if (IS_ERR(page)) {
 827                         ret = PTR_ERR(page);
 828                         goto out;
 829                 }
 830
 831                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 832                         (page_to_phys(page) & (1 << 17)) != 0;
 833
 834                 vaddr = kmap(page);
 835                 if (page_do_bit17_swizzling)
 836                         ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 837                                                         user_data,
 838                                                         page_length);
 839                 else
 840                         ret = __copy_from_user(vaddr + shmem_page_offset,
 841                                                user_data,
 842                                                page_length);
 843                 kunmap(page);
 844
 845                 set_page_dirty(page);
 846                 mark_page_accessed(page);
 847                 page_cache_release(page);
 848
 849                 if (ret) {
 850                         ret = -EFAULT;
 851                         goto out;
 852                 }
 853
 854                 remain -= page_length;
 855                 user_data += page_length;
 856                 offset += page_length;
 857         }
 858
 859 out:
 860         mutex_lock(&dev->struct_mutex);
 861         /* Fixup: Kill any reinstated backing storage pages */
 862         if (obj->madv == __I915_MADV_PURGED)
 863                 i915_gem_object_truncate(obj);
 864         /* and flush dirty cachelines in case the object isn't in the cpu write
 865          * domain anymore. */
 866         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 867                 i915_gem_clflush_object(obj);
 868                 intel_gtt_chipset_flush();
 869         }
 870
 871         return ret;
 872 }
 873
 874 /**
 875  * Writes data to the object referenced by handle.
 876  *
 877  * On error, the contents of the buffer that were to be modified are undefined.
 878  */
 879 int
 880 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 881                       struct drm_file *file)
 882 {
 883         struct drm_i915_gem_pwrite *args = data;
 884         struct drm_i915_gem_object *obj;
 885         int ret;
 886
 887         if (args->size == 0)
 888                 return 0;
 889
 890         if (!access_ok(VERIFY_READ,
 891                        (char __user *)(uintptr_t)args->data_ptr,
 892                        args->size))
 893                 return -EFAULT;
 894
 895         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
 896                                       args->size);
 897         if (ret)
 898                 return -EFAULT;
 899
 900         ret = i915_mutex_lock_interruptible(dev);
 901         if (ret)
 902                 return ret;
 903
 904         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 905         if (&obj->base == NULL) {
 906                 ret = -ENOENT;
 907                 goto unlock;
 908         }
 909
 910         /* Bounds check destination. */
 911         if (args->offset > obj->base.size ||
 912             args->size > obj->base.size - args->offset) {
 913                 ret = -EINVAL;
 914                 goto out;
 915         }
 916
 917         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 918
 919         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 920          * it would end up going through the fenced access, and we'll get
 921          * different detiling behavior between reading and writing.
 922          * pread/pwrite currently are reading and writing from the CPU
 923          * perspective, requiring manual detiling by the client.
 924          */
 925         if (obj->phys_obj) {
 926                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 927                 goto out;
 928         }
 929
 930         if (obj->gtt_space &&
 931             obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 932                 ret = i915_gem_object_pin(obj, 0, true);
 933                 if (ret)
 934                         goto out;
 935
 936                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
 937                 if (ret)
 938                         goto out_unpin;
 939
 940                 ret = i915_gem_object_put_fence(obj);
 941                 if (ret)
 942                         goto out_unpin;
 943
 944                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
 945                 if (ret == -EFAULT)
 946                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
 947
 948 out_unpin:
 949                 i915_gem_object_unpin(obj);
 950
 951                 if (ret != -EFAULT)
 952                         goto out;
 953                 /* Fall through to the shmfs paths because the gtt paths might
 954                  * fail with non-page-backed user pointers (e.g. gtt mappings
 955                  * when moving data between textures). */
 956         }
 957
 958         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 959         if (ret)
 960                 goto out;
 961
 962         ret = -EFAULT;
 963         if (!i915_gem_object_needs_bit17_swizzle(obj))
 964                 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
 965         if (ret == -EFAULT)
 966                 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
 967
 968 out:
 969         drm_gem_object_unreference(&obj->base);
 970 unlock:
 971         mutex_unlock(&dev->struct_mutex);
 972         return ret;
 973 }
 974
 975 /**
 976  * Called when user space prepares to use an object with the CPU, either
 977  * through the mmap ioctl's mapping or a GTT mapping.
 978  */
 979 int
 980 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 981                           struct drm_file *file)
 982 {
 983         struct drm_i915_gem_set_domain *args = data;
 984         struct drm_i915_gem_object *obj;
 985         uint32_t read_domains = args->read_domains;
 986         uint32_t write_domain = args->write_domain;
 987         int ret;
 988
 989         if (!(dev->driver->driver_features & DRIVER_GEM))
 990                 return -ENODEV;
 991
 992         /* Only handle setting domains to types used by the CPU. */
 993         if (write_domain & I915_GEM_GPU_DOMAINS)
 994                 return -EINVAL;
 995
 996         if (read_domains & I915_GEM_GPU_DOMAINS)
 997                 return -EINVAL;
 998
 999         /* Having something in the write domain implies it's in the read
1000          * domain, and only that read domain.  Enforce that in the request.
1001          */
1002         if (write_domain != 0 && read_domains != write_domain)
1003                 return -EINVAL;
1004
1005         ret = i915_mutex_lock_interruptible(dev);
1006         if (ret)
1007                 return ret;
1008
1009         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1010         if (&obj->base == NULL) {
1011                 ret = -ENOENT;
1012                 goto unlock;
1013         }
1014
1015         if (read_domains & I915_GEM_DOMAIN_GTT) {
1016                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1017
1018                 /* Silently promote "you're not bound, there was nothing to do"
1019                  * to success, since the client was just asking us to
1020                  * make sure everything was done.
1021                  */
1022                 if (ret == -EINVAL)
1023                         ret = 0;
1024         } else {
1025                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1026         }
1027
1028         drm_gem_object_unreference(&obj->base);
1029 unlock:
1030         mutex_unlock(&dev->struct_mutex);
1031         return ret;
1032 }
1033
1034 /**
1035  * Called when user space has done writes to this buffer
1036  */
1037 int
1038 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1039                          struct drm_file *file)
1040 {
1041         struct drm_i915_gem_sw_finish *args = data;
1042         struct drm_i915_gem_object *obj;
1043         int ret = 0;
1044
1045         if (!(dev->driver->driver_features & DRIVER_GEM))
1046                 return -ENODEV;
1047
1048         ret = i915_mutex_lock_interruptible(dev);
1049         if (ret)
1050                 return ret;
1051
1052         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1053         if (&obj->base == NULL) {
1054                 ret = -ENOENT;
1055                 goto unlock;
1056         }
1057
1058         /* Pinned buffers may be scanout, so flush the cache */
1059         if (obj->pin_count)
1060                 i915_gem_object_flush_cpu_write_domain(obj);
1061
1062         drm_gem_object_unreference(&obj->base);
1063 unlock:
1064         mutex_unlock(&dev->struct_mutex);
1065         return ret;
1066 }
1067
1068 /**
1069  * Maps the contents of an object, returning the address it is mapped
1070  * into.
1071  *
1072  * While the mapping holds a reference on the contents of the object, it doesn't
1073  * imply a ref on the object itself.
1074  */
1075 int
1076 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1077                     struct drm_file *file)
1078 {
1079         struct drm_i915_gem_mmap *args = data;
1080         struct drm_gem_object *obj;
1081         unsigned long addr;
1082
1083         if (!(dev->driver->driver_features & DRIVER_GEM))
1084                 return -ENODEV;
1085
1086         obj = drm_gem_object_lookup(dev, file, args->handle);
1087         if (obj == NULL)
1088                 return -ENOENT;
1089
1090         down_write(&current->mm->mmap_sem);
1091         addr = do_mmap(obj->filp, 0, args->size,
1092                        PROT_READ | PROT_WRITE, MAP_SHARED,
1093                        args->offset);
1094         up_write(&current->mm->mmap_sem);
1095         drm_gem_object_unreference_unlocked(obj);
1096         if (IS_ERR((void *)addr))
1097                 return addr;
1098
1099         args->addr_ptr = (uint64_t) addr;
1100
1101         return 0;
1102 }
1103
1104 /**
1105  * i915_gem_fault - fault a page into the GTT
1106  * vma: VMA in question
1107  * vmf: fault info
1108  *
1109  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1110  * from userspace.  The fault handler takes care of binding the object to
1111  * the GTT (if needed), allocating and programming a fence register (again,
1112  * only if needed based on whether the old reg is still valid or the object
1113  * is tiled) and inserting a new PTE into the faulting process.
1114  *
1115  * Note that the faulting process may involve evicting existing objects
1116  * from the GTT and/or fence registers to make room.  So performance may
1117  * suffer if the GTT working set is large or there are few fence registers
1118  * left.
1119  */
1120 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1121 {
1122         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1123         struct drm_device *dev = obj->base.dev;
1124         drm_i915_private_t *dev_priv = dev->dev_private;
1125         pgoff_t page_offset;
1126         unsigned long pfn;
1127         int ret = 0;
1128         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1129
1130         /* We don't use vmf->pgoff since that has the fake offset */
1131         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1132                 PAGE_SHIFT;
1133
1134         ret = i915_mutex_lock_interruptible(dev);
1135         if (ret)
1136                 goto out;
1137
1138         trace_i915_gem_object_fault(obj, page_offset, true, write);
1139
1140         /* Now bind it into the GTT if needed */
1141         if (!obj->map_and_fenceable) {
1142                 ret = i915_gem_object_unbind(obj);
1143                 if (ret)
1144                         goto unlock;
1145         }
1146         if (!obj->gtt_space) {
1147                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1148                 if (ret)
1149                         goto unlock;
1150
1151                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1152                 if (ret)
1153                         goto unlock;
1154         }
1155
1156         if (obj->tiling_mode == I915_TILING_NONE)
1157                 ret = i915_gem_object_put_fence(obj);
1158         else
1159                 ret = i915_gem_object_get_fence(obj, NULL);
1160         if (ret)
1161                 goto unlock;
1162
1163         if (i915_gem_object_is_inactive(obj))
1164                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1165
1166         obj->fault_mappable = true;
1167
1168         pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1169                 page_offset;
1170
1171         /* Finally, remap it using the new GTT offset */
1172         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1173 unlock:
1174         mutex_unlock(&dev->struct_mutex);
1175 out:
1176         switch (ret) {
1177         case -EIO:
1178         case -EAGAIN:
1179                 /* Give the error handler a chance to run and move the
1180                  * objects off the GPU active list. Next time we service the
1181                  * fault, we should be able to transition the page into the
1182                  * GTT without touching the GPU (and so avoid further
1183                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1184                  * with coherency, just lost writes.
1185                  */
1186                 set_need_resched();
1187         case 0:
1188         case -ERESTARTSYS:
1189         case -EINTR:
1190                 return VM_FAULT_NOPAGE;
1191         case -ENOMEM:
1192                 return VM_FAULT_OOM;
1193         default:
1194                 return VM_FAULT_SIGBUS;
1195         }
1196 }
1197
1198 /**
1199  * i915_gem_release_mmap - remove physical page mappings
1200  * @obj: obj in question
1201  *
1202  * Preserve the reservation of the mmapping with the DRM core code, but
1203  * relinquish ownership of the pages back to the system.
1204  *
1205  * It is vital that we remove the page mapping if we have mapped a tiled
1206  * object through the GTT and then lose the fence register due to
1207  * resource pressure. Similarly if the object has been moved out of the
1208  * aperture, than pages mapped into userspace must be revoked. Removing the
1209  * mapping will then trigger a page fault on the next user access, allowing
1210  * fixup by i915_gem_fault().
1211  */
1212 void
1213 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1214 {
1215         if (!obj->fault_mappable)
1216                 return;
1217
1218         if (obj->base.dev->dev_mapping)
1219                 unmap_mapping_range(obj->base.dev->dev_mapping,
1220                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1221                                     obj->base.size, 1);
1222
1223         obj->fault_mappable = false;
1224 }
1225
1226 static uint32_t
1227 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1228 {
1229         uint32_t gtt_size;
1230
1231         if (INTEL_INFO(dev)->gen >= 4 ||
1232             tiling_mode == I915_TILING_NONE)
1233                 return size;
1234
1235         /* Previous chips need a power-of-two fence region when tiling */
1236         if (INTEL_INFO(dev)->gen == 3)
1237                 gtt_size = 1024*1024;
1238         else
1239                 gtt_size = 512*1024;
1240
1241         while (gtt_size < size)
1242                 gtt_size <<= 1;
1243
1244         return gtt_size;
1245 }
1246
1247 /**
1248  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1249  * @obj: object to check
1250  *
1251  * Return the required GTT alignment for an object, taking into account
1252  * potential fence register mapping.
1253  */
1254 static uint32_t
1255 i915_gem_get_gtt_alignment(struct drm_device *dev,
1256                            uint32_t size,
1257                            int tiling_mode)
1258 {
1259         /*
1260          * Minimum alignment is 4k (GTT page size), but might be greater
1261          * if a fence register is needed for the object.
1262          */
1263         if (INTEL_INFO(dev)->gen >= 4 ||
1264             tiling_mode == I915_TILING_NONE)
1265                 return 4096;
1266
1267         /*
1268          * Previous chips need to be aligned to the size of the smallest
1269          * fence register that can contain the object.
1270          */
1271         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1272 }
1273
1274 /**
1275  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1276  *                                       unfenced object
1277  * @dev: the device
1278  * @size: size of the object
1279  * @tiling_mode: tiling mode of the object
1280  *
1281  * Return the required GTT alignment for an object, only taking into account
1282  * unfenced tiled surface requirements.
1283  */
1284 uint32_t
1285 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1286                                     uint32_t size,
1287                                     int tiling_mode)
1288 {
1289         /*
1290          * Minimum alignment is 4k (GTT page size) for sane hw.
1291          */
1292         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1293             tiling_mode == I915_TILING_NONE)
1294                 return 4096;
1295
1296         /* Previous hardware however needs to be aligned to a power-of-two
1297          * tile height. The simplest method for determining this is to reuse
1298          * the power-of-tile object size.
1299          */
1300         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1301 }
1302
1303 int
1304 i915_gem_mmap_gtt(struct drm_file *file,
1305                   struct drm_device *dev,
1306                   uint32_t handle,
1307                   uint64_t *offset)
1308 {
1309         struct drm_i915_private *dev_priv = dev->dev_private;
1310         struct drm_i915_gem_object *obj;
1311         int ret;
1312
1313         if (!(dev->driver->driver_features & DRIVER_GEM))
1314                 return -ENODEV;
1315
1316         ret = i915_mutex_lock_interruptible(dev);
1317         if (ret)
1318                 return ret;
1319
1320         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1321         if (&obj->base == NULL) {
1322                 ret = -ENOENT;
1323                 goto unlock;
1324         }
1325
1326         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1327                 ret = -E2BIG;
1328                 goto out;
1329         }
1330
1331         if (obj->madv != I915_MADV_WILLNEED) {
1332                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1333                 ret = -EINVAL;
1334                 goto out;
1335         }
1336
1337         if (!obj->base.map_list.map) {
1338                 ret = drm_gem_create_mmap_offset(&obj->base);
1339                 if (ret)
1340                         goto out;
1341         }
1342
1343         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1344
1345 out:
1346         drm_gem_object_unreference(&obj->base);
1347 unlock:
1348         mutex_unlock(&dev->struct_mutex);
1349         return ret;
1350 }
1351
1352 /**
1353  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1354  * @dev: DRM device
1355  * @data: GTT mapping ioctl data
1356  * @file: GEM object info
1357  *
1358  * Simply returns the fake offset to userspace so it can mmap it.
1359  * The mmap call will end up in drm_gem_mmap(), which will set things
1360  * up so we can get faults in the handler above.
1361  *
1362  * The fault handler will take care of binding the object into the GTT
1363  * (since it may have been evicted to make room for something), allocating
1364  * a fence register, and mapping the appropriate aperture address into
1365  * userspace.
1366  */
1367 int
1368 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1369                         struct drm_file *file)
1370 {
1371         struct drm_i915_gem_mmap_gtt *args = data;
1372
1373         if (!(dev->driver->driver_features & DRIVER_GEM))
1374                 return -ENODEV;
1375
1376         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1377 }
1378
1379
1380 static int
1381 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1382                               gfp_t gfpmask)
1383 {
1384         int page_count, i;
1385         struct address_space *mapping;
1386         struct inode *inode;
1387         struct page *page;
1388
1389         /* Get the list of pages out of our struct file.  They'll be pinned
1390          * at this point until we release them.
1391          */
1392         page_count = obj->base.size / PAGE_SIZE;
1393         BUG_ON(obj->pages != NULL);
1394         obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1395         if (obj->pages == NULL)
1396                 return -ENOMEM;
1397
1398         inode = obj->base.filp->f_path.dentry->d_inode;
1399         mapping = inode->i_mapping;
1400         gfpmask |= mapping_gfp_mask(mapping);
1401
1402         for (i = 0; i < page_count; i++) {
1403                 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
1404                 if (IS_ERR(page))
1405                         goto err_pages;
1406
1407                 obj->pages[i] = page;
1408         }
1409
1410         if (i915_gem_object_needs_bit17_swizzle(obj))
1411                 i915_gem_object_do_bit_17_swizzle(obj);
1412
1413         return 0;
1414
1415 err_pages:
1416         while (i--)
1417                 page_cache_release(obj->pages[i]);
1418
1419         drm_free_large(obj->pages);
1420         obj->pages = NULL;
1421         return PTR_ERR(page);
1422 }
1423
1424 static void
1425 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1426 {
1427         int page_count = obj->base.size / PAGE_SIZE;
1428         int i;
1429
1430         BUG_ON(obj->madv == __I915_MADV_PURGED);
1431
1432         if (i915_gem_object_needs_bit17_swizzle(obj))
1433                 i915_gem_object_save_bit_17_swizzle(obj);
1434
1435         if (obj->madv == I915_MADV_DONTNEED)
1436                 obj->dirty = 0;
1437
1438         for (i = 0; i < page_count; i++) {
1439                 if (obj->dirty)
1440                         set_page_dirty(obj->pages[i]);
1441
1442                 if (obj->madv == I915_MADV_WILLNEED)
1443                         mark_page_accessed(obj->pages[i]);
1444
1445                 page_cache_release(obj->pages[i]);
1446         }
1447         obj->dirty = 0;
1448
1449         drm_free_large(obj->pages);
1450         obj->pages = NULL;
1451 }
1452
1453 void
1454 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1455                                struct intel_ring_buffer *ring,
1456                                u32 seqno)
1457 {
1458         struct drm_device *dev = obj->base.dev;
1459         struct drm_i915_private *dev_priv = dev->dev_private;
1460
1461         BUG_ON(ring == NULL);
1462         obj->ring = ring;
1463
1464         /* Add a reference if we're newly entering the active list. */
1465         if (!obj->active) {
1466                 drm_gem_object_reference(&obj->base);
1467                 obj->active = 1;
1468         }
1469
1470         /* Move from whatever list we were on to the tail of execution. */
1471         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1472         list_move_tail(&obj->ring_list, &ring->active_list);
1473
1474         obj->last_rendering_seqno = seqno;
1475         if (obj->fenced_gpu_access) {
1476                 struct drm_i915_fence_reg *reg;
1477
1478                 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1479
1480                 obj->last_fenced_seqno = seqno;
1481                 obj->last_fenced_ring = ring;
1482
1483                 reg = &dev_priv->fence_regs[obj->fence_reg];
1484                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
1485         }
1486 }
1487
1488 static void
1489 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1490 {
1491         list_del_init(&obj->ring_list);
1492         obj->last_rendering_seqno = 0;
1493 }
1494
1495 static void
1496 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1497 {
1498         struct drm_device *dev = obj->base.dev;
1499         drm_i915_private_t *dev_priv = dev->dev_private;
1500
1501         BUG_ON(!obj->active);
1502         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1503
1504         i915_gem_object_move_off_active(obj);
1505 }
1506
1507 static void
1508 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1509 {
1510         struct drm_device *dev = obj->base.dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512
1513         if (obj->pin_count != 0)
1514                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1515         else
1516                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1517
1518         BUG_ON(!list_empty(&obj->gpu_write_list));
1519         BUG_ON(!obj->active);
1520         obj->ring = NULL;
1521
1522         i915_gem_object_move_off_active(obj);
1523         obj->fenced_gpu_access = false;
1524
1525         obj->active = 0;
1526         obj->pending_gpu_write = false;
1527         drm_gem_object_unreference(&obj->base);
1528
1529         WARN_ON(i915_verify_lists(dev));
1530 }
1531
1532 /* Immediately discard the backing storage */
1533 static void
1534 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1535 {
1536         struct inode *inode;
1537
1538         /* Our goal here is to return as much of the memory as
1539          * is possible back to the system as we are called from OOM.
1540          * To do this we must instruct the shmfs to drop all of its
1541          * backing pages, *now*.
1542          */
1543         inode = obj->base.filp->f_path.dentry->d_inode;
1544         shmem_truncate_range(inode, 0, (loff_t)-1);
1545
1546         obj->madv = __I915_MADV_PURGED;
1547 }
1548
1549 static inline int
1550 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1551 {
1552         return obj->madv == I915_MADV_DONTNEED;
1553 }
1554
1555 static void
1556 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1557                                uint32_t flush_domains)
1558 {
1559         struct drm_i915_gem_object *obj, *next;
1560
1561         list_for_each_entry_safe(obj, next,
1562                                  &ring->gpu_write_list,
1563                                  gpu_write_list) {
1564                 if (obj->base.write_domain & flush_domains) {
1565                         uint32_t old_write_domain = obj->base.write_domain;
1566
1567                         obj->base.write_domain = 0;
1568                         list_del_init(&obj->gpu_write_list);
1569                         i915_gem_object_move_to_active(obj, ring,
1570                                                        i915_gem_next_request_seqno(ring));
1571
1572                         trace_i915_gem_object_change_domain(obj,
1573                                                             obj->base.read_domains,
1574                                                             old_write_domain);
1575                 }
1576         }
1577 }
1578
1579 static u32
1580 i915_gem_get_seqno(struct drm_device *dev)
1581 {
1582         drm_i915_private_t *dev_priv = dev->dev_private;
1583         u32 seqno = dev_priv->next_seqno;
1584
1585         /* reserve 0 for non-seqno */
1586         if (++dev_priv->next_seqno == 0)
1587                 dev_priv->next_seqno = 1;
1588
1589         return seqno;
1590 }
1591
1592 u32
1593 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1594 {
1595         if (ring->outstanding_lazy_request == 0)
1596                 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
1597
1598         return ring->outstanding_lazy_request;
1599 }
1600
1601 int
1602 i915_add_request(struct intel_ring_buffer *ring,
1603                  struct drm_file *file,
1604                  struct drm_i915_gem_request *request)
1605 {
1606         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1607         uint32_t seqno;
1608         u32 request_ring_position;
1609         int was_empty;
1610         int ret;
1611
1612         BUG_ON(request == NULL);
1613         seqno = i915_gem_next_request_seqno(ring);
1614
1615         /* Record the position of the start of the request so that
1616          * should we detect the updated seqno part-way through the
1617          * GPU processing the request, we never over-estimate the
1618          * position of the head.
1619          */
1620         request_ring_position = intel_ring_get_tail(ring);
1621
1622         ret = ring->add_request(ring, &seqno);
1623         if (ret)
1624             return ret;
1625
1626         trace_i915_gem_request_add(ring, seqno);
1627
1628         request->seqno = seqno;
1629         request->ring = ring;
1630         request->tail = request_ring_position;
1631         request->emitted_jiffies = jiffies;
1632         was_empty = list_empty(&ring->request_list);
1633         list_add_tail(&request->list, &ring->request_list);
1634
1635         if (file) {
1636                 struct drm_i915_file_private *file_priv = file->driver_priv;
1637
1638                 spin_lock(&file_priv->mm.lock);
1639                 request->file_priv = file_priv;
1640                 list_add_tail(&request->client_list,
1641                               &file_priv->mm.request_list);
1642                 spin_unlock(&file_priv->mm.lock);
1643         }
1644
1645         ring->outstanding_lazy_request = 0;
1646
1647         if (!dev_priv->mm.suspended) {
1648                 if (i915_enable_hangcheck) {
1649                         mod_timer(&dev_priv->hangcheck_timer,
1650                                   jiffies +
1651                                   msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1652                 }
1653                 if (was_empty)
1654                         queue_delayed_work(dev_priv->wq,
1655                                            &dev_priv->mm.retire_work, HZ);
1656         }
1657         return 0;
1658 }
1659
1660 static inline void
1661 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1662 {
1663         struct drm_i915_file_private *file_priv = request->file_priv;
1664
1665         if (!file_priv)
1666                 return;
1667
1668         spin_lock(&file_priv->mm.lock);
1669         if (request->file_priv) {
1670                 list_del(&request->client_list);
1671                 request->file_priv = NULL;
1672         }
1673         spin_unlock(&file_priv->mm.lock);
1674 }
1675
1676 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1677                                       struct intel_ring_buffer *ring)
1678 {
1679         while (!list_empty(&ring->request_list)) {
1680                 struct drm_i915_gem_request *request;
1681
1682                 request = list_first_entry(&ring->request_list,
1683                                            struct drm_i915_gem_request,
1684                                            list);
1685
1686                 list_del(&request->list);
1687                 i915_gem_request_remove_from_client(request);
1688                 kfree(request);
1689         }
1690
1691         while (!list_empty(&ring->active_list)) {
1692                 struct drm_i915_gem_object *obj;
1693
1694                 obj = list_first_entry(&ring->active_list,
1695                                        struct drm_i915_gem_object,
1696                                        ring_list);
1697
1698                 obj->base.write_domain = 0;
1699                 list_del_init(&obj->gpu_write_list);
1700                 i915_gem_object_move_to_inactive(obj);
1701         }
1702 }
1703
1704 static void i915_gem_reset_fences(struct drm_device *dev)
1705 {
1706         struct drm_i915_private *dev_priv = dev->dev_private;
1707         int i;
1708
1709         for (i = 0; i < dev_priv->num_fence_regs; i++) {
1710                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1711                 struct drm_i915_gem_object *obj = reg->obj;
1712
1713                 if (!obj)
1714                         continue;
1715
1716                 if (obj->tiling_mode)
1717                         i915_gem_release_mmap(obj);
1718
1719                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1720                 reg->obj->fenced_gpu_access = false;
1721                 reg->obj->last_fenced_seqno = 0;
1722                 reg->obj->last_fenced_ring = NULL;
1723                 i915_gem_clear_fence_reg(dev, reg);
1724         }
1725 }
1726
1727 void i915_gem_reset(struct drm_device *dev)
1728 {
1729         struct drm_i915_private *dev_priv = dev->dev_private;
1730         struct drm_i915_gem_object *obj;
1731         int i;
1732
1733         for (i = 0; i < I915_NUM_RINGS; i++)
1734                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1735
1736         /* Remove anything from the flushing lists. The GPU cache is likely
1737          * to be lost on reset along with the data, so simply move the
1738          * lost bo to the inactive list.
1739          */
1740         while (!list_empty(&dev_priv->mm.flushing_list)) {
1741                 obj = list_first_entry(&dev_priv->mm.flushing_list,
1742                                       struct drm_i915_gem_object,
1743                                       mm_list);
1744
1745                 obj->base.write_domain = 0;
1746                 list_del_init(&obj->gpu_write_list);
1747                 i915_gem_object_move_to_inactive(obj);
1748         }
1749
1750         /* Move everything out of the GPU domains to ensure we do any
1751          * necessary invalidation upon reuse.
1752          */
1753         list_for_each_entry(obj,
1754                             &dev_priv->mm.inactive_list,
1755                             mm_list)
1756         {
1757                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1758         }
1759
1760         /* The fence registers are invalidated so clear them out */
1761         i915_gem_reset_fences(dev);
1762 }
1763
1764 /**
1765  * This function clears the request list as sequence numbers are passed.
1766  */
1767 void
1768 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1769 {
1770         uint32_t seqno;
1771         int i;
1772
1773         if (list_empty(&ring->request_list))
1774                 return;
1775
1776         WARN_ON(i915_verify_lists(ring->dev));
1777
1778         seqno = ring->get_seqno(ring);
1779
1780         for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1781                 if (seqno >= ring->sync_seqno[i])
1782                         ring->sync_seqno[i] = 0;
1783
1784         while (!list_empty(&ring->request_list)) {
1785                 struct drm_i915_gem_request *request;
1786
1787                 request = list_first_entry(&ring->request_list,
1788                                            struct drm_i915_gem_request,
1789                                            list);
1790
1791                 if (!i915_seqno_passed(seqno, request->seqno))
1792                         break;
1793
1794                 trace_i915_gem_request_retire(ring, request->seqno);
1795                 /* We know the GPU must have read the request to have
1796                  * sent us the seqno + interrupt, so use the position
1797                  * of tail of the request to update the last known position
1798                  * of the GPU head.
1799                  */
1800                 ring->last_retired_head = request->tail;
1801
1802                 list_del(&request->list);
1803                 i915_gem_request_remove_from_client(request);
1804                 kfree(request);
1805         }
1806
1807         /* Move any buffers on the active list that are no longer referenced
1808          * by the ringbuffer to the flushing/inactive lists as appropriate.
1809          */
1810         while (!list_empty(&ring->active_list)) {
1811                 struct drm_i915_gem_object *obj;
1812
1813                 obj = list_first_entry(&ring->active_list,
1814                                       struct drm_i915_gem_object,
1815                                       ring_list);
1816
1817                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1818                         break;
1819
1820                 if (obj->base.write_domain != 0)
1821                         i915_gem_object_move_to_flushing(obj);
1822                 else
1823                         i915_gem_object_move_to_inactive(obj);
1824         }
1825
1826         if (unlikely(ring->trace_irq_seqno &&
1827                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1828                 ring->irq_put(ring);
1829                 ring->trace_irq_seqno = 0;
1830         }
1831
1832         WARN_ON(i915_verify_lists(ring->dev));
1833 }
1834
1835 void
1836 i915_gem_retire_requests(struct drm_device *dev)
1837 {
1838         drm_i915_private_t *dev_priv = dev->dev_private;
1839         int i;
1840
1841         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1842             struct drm_i915_gem_object *obj, *next;
1843
1844             /* We must be careful that during unbind() we do not
1845              * accidentally infinitely recurse into retire requests.
1846              * Currently:
1847              *   retire -> free -> unbind -> wait -> retire_ring
1848              */
1849             list_for_each_entry_safe(obj, next,
1850                                      &dev_priv->mm.deferred_free_list,
1851                                      mm_list)
1852                     i915_gem_free_object_tail(obj);
1853         }
1854
1855         for (i = 0; i < I915_NUM_RINGS; i++)
1856                 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1857 }
1858
1859 static void
1860 i915_gem_retire_work_handler(struct work_struct *work)
1861 {
1862         drm_i915_private_t *dev_priv;
1863         struct drm_device *dev;
1864         bool idle;
1865         int i;
1866
1867         dev_priv = container_of(work, drm_i915_private_t,
1868                                 mm.retire_work.work);
1869         dev = dev_priv->dev;
1870
1871         /* Come back later if the device is busy... */
1872         if (!mutex_trylock(&dev->struct_mutex)) {
1873                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1874                 return;
1875         }
1876
1877         i915_gem_retire_requests(dev);
1878
1879         /* Send a periodic flush down the ring so we don't hold onto GEM
1880          * objects indefinitely.
1881          */
1882         idle = true;
1883         for (i = 0; i < I915_NUM_RINGS; i++) {
1884                 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1885
1886                 if (!list_empty(&ring->gpu_write_list)) {
1887                         struct drm_i915_gem_request *request;
1888                         int ret;
1889
1890                         ret = i915_gem_flush_ring(ring,
1891                                                   0, I915_GEM_GPU_DOMAINS);
1892                         request = kzalloc(sizeof(*request), GFP_KERNEL);
1893                         if (ret || request == NULL ||
1894                             i915_add_request(ring, NULL, request))
1895                             kfree(request);
1896                 }
1897
1898                 idle &= list_empty(&ring->request_list);
1899         }
1900
1901         if (!dev_priv->mm.suspended && !idle)
1902                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1903
1904         mutex_unlock(&dev->struct_mutex);
1905 }
1906
1907 /**
1908  * Waits for a sequence number to be signaled, and cleans up the
1909  * request and object lists appropriately for that event.
1910  */
1911 int
1912 i915_wait_request(struct intel_ring_buffer *ring,
1913                   uint32_t seqno,
1914                   bool do_retire)
1915 {
1916         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1917         u32 ier;
1918         int ret = 0;
1919
1920         BUG_ON(seqno == 0);
1921
1922         if (atomic_read(&dev_priv->mm.wedged)) {
1923                 struct completion *x = &dev_priv->error_completion;
1924                 bool recovery_complete;
1925                 unsigned long flags;
1926
1927                 /* Give the error handler a chance to run. */
1928                 spin_lock_irqsave(&x->wait.lock, flags);
1929                 recovery_complete = x->done > 0;
1930                 spin_unlock_irqrestore(&x->wait.lock, flags);
1931
1932                 return recovery_complete ? -EIO : -EAGAIN;
1933         }
1934
1935         if (seqno == ring->outstanding_lazy_request) {
1936                 struct drm_i915_gem_request *request;
1937
1938                 request = kzalloc(sizeof(*request), GFP_KERNEL);
1939                 if (request == NULL)
1940                         return -ENOMEM;
1941
1942                 ret = i915_add_request(ring, NULL, request);
1943                 if (ret) {
1944                         kfree(request);
1945                         return ret;
1946                 }
1947
1948                 seqno = request->seqno;
1949         }
1950
1951         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
1952                 if (HAS_PCH_SPLIT(ring->dev))
1953                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1954                 else
1955                         ier = I915_READ(IER);
1956                 if (!ier) {
1957                         DRM_ERROR("something (likely vbetool) disabled "
1958                                   "interrupts, re-enabling\n");
1959                         ring->dev->driver->irq_preinstall(ring->dev);
1960                         ring->dev->driver->irq_postinstall(ring->dev);
1961                 }
1962
1963                 trace_i915_gem_request_wait_begin(ring, seqno);
1964
1965                 ring->waiting_seqno = seqno;
1966                 if (ring->irq_get(ring)) {
1967                         if (dev_priv->mm.interruptible)
1968                                 ret = wait_event_interruptible(ring->irq_queue,
1969                                                                i915_seqno_passed(ring->get_seqno(ring), seqno)
1970                                                                || atomic_read(&dev_priv->mm.wedged));
1971                         else
1972                                 wait_event(ring->irq_queue,
1973                                            i915_seqno_passed(ring->get_seqno(ring), seqno)
1974                                            || atomic_read(&dev_priv->mm.wedged));
1975
1976                         ring->irq_put(ring);
1977                 } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring),
1978                                                              seqno) ||
1979                                            atomic_read(&dev_priv->mm.wedged), 3000))
1980                         ret = -EBUSY;
1981                 ring->waiting_seqno = 0;
1982
1983                 trace_i915_gem_request_wait_end(ring, seqno);
1984         }
1985         if (atomic_read(&dev_priv->mm.wedged))
1986                 ret = -EAGAIN;
1987
1988         /* Directly dispatch request retiring.  While we have the work queue
1989          * to handle this, the waiter on a request often wants an associated
1990          * buffer to have made it to the inactive list, and we would need
1991          * a separate wait queue to handle that.
1992          */
1993         if (ret == 0 && do_retire)
1994                 i915_gem_retire_requests_ring(ring);
1995
1996         return ret;
1997 }
1998
1999 /**
2000  * Ensures that all rendering to the object has completed and the object is
2001  * safe to unbind from the GTT or access from the CPU.
2002  */
2003 int
2004 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2005 {
2006         int ret;
2007
2008         /* This function only exists to support waiting for existing rendering,
2009          * not for emitting required flushes.
2010          */
2011         BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2012
2013         /* If there is rendering queued on the buffer being evicted, wait for
2014          * it.
2015          */
2016         if (obj->active) {
2017                 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno,
2018                                         true);
2019                 if (ret)
2020                         return ret;
2021         }
2022
2023         return 0;
2024 }
2025
2026 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2027 {
2028         u32 old_write_domain, old_read_domains;
2029
2030         /* Act a barrier for all accesses through the GTT */
2031         mb();
2032
2033         /* Force a pagefault for domain tracking on next user access */
2034         i915_gem_release_mmap(obj);
2035
2036         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2037                 return;
2038
2039         old_read_domains = obj->base.read_domains;
2040         old_write_domain = obj->base.write_domain;
2041
2042         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2043         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2044
2045         trace_i915_gem_object_change_domain(obj,
2046                                             old_read_domains,
2047                                             old_write_domain);
2048 }
2049
2050 /**
2051  * Unbinds an object from the GTT aperture.
2052  */
2053 int
2054 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2055 {
2056         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2057         int ret = 0;
2058
2059         if (obj->gtt_space == NULL)
2060                 return 0;
2061
2062         if (obj->pin_count != 0) {
2063                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2064                 return -EINVAL;
2065         }
2066
2067         ret = i915_gem_object_finish_gpu(obj);
2068         if (ret == -ERESTARTSYS)
2069                 return ret;
2070         /* Continue on if we fail due to EIO, the GPU is hung so we
2071          * should be safe and we need to cleanup or else we might
2072          * cause memory corruption through use-after-free.
2073          */
2074
2075         i915_gem_object_finish_gtt(obj);
2076
2077         /* Move the object to the CPU domain to ensure that
2078          * any possible CPU writes while it's not in the GTT
2079          * are flushed when we go to remap it.
2080          */
2081         if (ret == 0)
2082                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2083         if (ret == -ERESTARTSYS)
2084                 return ret;
2085         if (ret) {
2086                 /* In the event of a disaster, abandon all caches and
2087                  * hope for the best.
2088                  */
2089                 i915_gem_clflush_object(obj);
2090                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2091         }
2092
2093         /* release the fence reg _after_ flushing */
2094         ret = i915_gem_object_put_fence(obj);
2095         if (ret == -ERESTARTSYS)
2096                 return ret;
2097
2098         trace_i915_gem_object_unbind(obj);
2099
2100         i915_gem_gtt_unbind_object(obj);
2101         if (obj->has_aliasing_ppgtt_mapping) {
2102                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2103                 obj->has_aliasing_ppgtt_mapping = 0;
2104         }
2105
2106         i915_gem_object_put_pages_gtt(obj);
2107
2108         list_del_init(&obj->gtt_list);
2109         list_del_init(&obj->mm_list);
2110         /* Avoid an unnecessary call to unbind on rebind. */
2111         obj->map_and_fenceable = true;
2112
2113         drm_mm_put_block(obj->gtt_space);
2114         obj->gtt_space = NULL;
2115         obj->gtt_offset = 0;
2116
2117         if (i915_gem_object_is_purgeable(obj))
2118                 i915_gem_object_truncate(obj);
2119
2120         return ret;
2121 }
2122
2123 int
2124 i915_gem_flush_ring(struct intel_ring_buffer *ring,
2125                     uint32_t invalidate_domains,
2126                     uint32_t flush_domains)
2127 {
2128         int ret;
2129
2130         if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2131                 return 0;
2132
2133         trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2134
2135         ret = ring->flush(ring, invalidate_domains, flush_domains);
2136         if (ret)
2137                 return ret;
2138
2139         if (flush_domains & I915_GEM_GPU_DOMAINS)
2140                 i915_gem_process_flushing_list(ring, flush_domains);
2141
2142         return 0;
2143 }
2144
2145 static int i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire)
2146 {
2147         int ret;
2148
2149         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2150                 return 0;
2151
2152         if (!list_empty(&ring->gpu_write_list)) {
2153                 ret = i915_gem_flush_ring(ring,
2154                                     I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2155                 if (ret)
2156                         return ret;
2157         }
2158
2159         return i915_wait_request(ring, i915_gem_next_request_seqno(ring),
2160                                  do_retire);
2161 }
2162
2163 int i915_gpu_idle(struct drm_device *dev, bool do_retire)
2164 {
2165         drm_i915_private_t *dev_priv = dev->dev_private;
2166         int ret, i;
2167
2168         /* Flush everything onto the inactive list. */
2169         for (i = 0; i < I915_NUM_RINGS; i++) {
2170                 ret = i915_ring_idle(&dev_priv->ring[i], do_retire);
2171                 if (ret)
2172                         return ret;
2173         }
2174
2175         return 0;
2176 }
2177
2178 static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2179                                        struct intel_ring_buffer *pipelined)
2180 {
2181         struct drm_device *dev = obj->base.dev;
2182         drm_i915_private_t *dev_priv = dev->dev_private;
2183         u32 size = obj->gtt_space->size;
2184         int regnum = obj->fence_reg;
2185         uint64_t val;
2186
2187         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2188                          0xfffff000) << 32;
2189         val |= obj->gtt_offset & 0xfffff000;
2190         val |= (uint64_t)((obj->stride / 128) - 1) <<
2191                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2192
2193         if (obj->tiling_mode == I915_TILING_Y)
2194                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2195         val |= I965_FENCE_REG_VALID;
2196
2197         if (pipelined) {
2198                 int ret = intel_ring_begin(pipelined, 6);
2199                 if (ret)
2200                         return ret;
2201
2202                 intel_ring_emit(pipelined, MI_NOOP);
2203                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2204                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2205                 intel_ring_emit(pipelined, (u32)val);
2206                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2207                 intel_ring_emit(pipelined, (u32)(val >> 32));
2208                 intel_ring_advance(pipelined);
2209         } else
2210                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2211
2212         return 0;
2213 }
2214
2215 static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2216                                 struct intel_ring_buffer *pipelined)
2217 {
2218         struct drm_device *dev = obj->base.dev;
2219         drm_i915_private_t *dev_priv = dev->dev_private;
2220         u32 size = obj->gtt_space->size;
2221         int regnum = obj->fence_reg;
2222         uint64_t val;
2223
2224         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2225                     0xfffff000) << 32;
2226         val |= obj->gtt_offset & 0xfffff000;
2227         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2228         if (obj->tiling_mode == I915_TILING_Y)
2229                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2230         val |= I965_FENCE_REG_VALID;
2231
2232         if (pipelined) {
2233                 int ret = intel_ring_begin(pipelined, 6);
2234                 if (ret)
2235                         return ret;
2236
2237                 intel_ring_emit(pipelined, MI_NOOP);
2238                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2239                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2240                 intel_ring_emit(pipelined, (u32)val);
2241                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2242                 intel_ring_emit(pipelined, (u32)(val >> 32));
2243                 intel_ring_advance(pipelined);
2244         } else
2245                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2246
2247         return 0;
2248 }
2249
2250 static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2251                                 struct intel_ring_buffer *pipelined)
2252 {
2253         struct drm_device *dev = obj->base.dev;
2254         drm_i915_private_t *dev_priv = dev->dev_private;
2255         u32 size = obj->gtt_space->size;
2256         u32 fence_reg, val, pitch_val;
2257         int tile_width;
2258
2259         if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2260                  (size & -size) != size ||
2261                  (obj->gtt_offset & (size - 1)),
2262                  "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2263                  obj->gtt_offset, obj->map_and_fenceable, size))
2264                 return -EINVAL;
2265
2266         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2267                 tile_width = 128;
2268         else
2269                 tile_width = 512;
2270
2271         /* Note: pitch better be a power of two tile widths */
2272         pitch_val = obj->stride / tile_width;
2273         pitch_val = ffs(pitch_val) - 1;
2274
2275         val = obj->gtt_offset;
2276         if (obj->tiling_mode == I915_TILING_Y)
2277                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2278         val |= I915_FENCE_SIZE_BITS(size);
2279         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2280         val |= I830_FENCE_REG_VALID;
2281
2282         fence_reg = obj->fence_reg;
2283         if (fence_reg < 8)
2284                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2285         else
2286                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2287
2288         if (pipelined) {
2289                 int ret = intel_ring_begin(pipelined, 4);
2290                 if (ret)
2291                         return ret;
2292
2293                 intel_ring_emit(pipelined, MI_NOOP);
2294                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2295                 intel_ring_emit(pipelined, fence_reg);
2296                 intel_ring_emit(pipelined, val);
2297                 intel_ring_advance(pipelined);
2298         } else
2299                 I915_WRITE(fence_reg, val);
2300
2301         return 0;
2302 }
2303
2304 static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2305                                 struct intel_ring_buffer *pipelined)
2306 {
2307         struct drm_device *dev = obj->base.dev;
2308         drm_i915_private_t *dev_priv = dev->dev_private;
2309         u32 size = obj->gtt_space->size;
2310         int regnum = obj->fence_reg;
2311         uint32_t val;
2312         uint32_t pitch_val;
2313
2314         if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2315                  (size & -size) != size ||
2316                  (obj->gtt_offset & (size - 1)),
2317                  "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2318                  obj->gtt_offset, size))
2319                 return -EINVAL;
2320
2321         pitch_val = obj->stride / 128;
2322         pitch_val = ffs(pitch_val) - 1;
2323
2324         val = obj->gtt_offset;
2325         if (obj->tiling_mode == I915_TILING_Y)
2326                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2327         val |= I830_FENCE_SIZE_BITS(size);
2328         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2329         val |= I830_FENCE_REG_VALID;
2330
2331         if (pipelined) {
2332                 int ret = intel_ring_begin(pipelined, 4);
2333                 if (ret)
2334                         return ret;
2335
2336                 intel_ring_emit(pipelined, MI_NOOP);
2337                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2338                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2339                 intel_ring_emit(pipelined, val);
2340                 intel_ring_advance(pipelined);
2341         } else
2342                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2343
2344         return 0;
2345 }
2346
2347 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2348 {
2349         return i915_seqno_passed(ring->get_seqno(ring), seqno);
2350 }
2351
2352 static int
2353 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2354                             struct intel_ring_buffer *pipelined)
2355 {
2356         int ret;
2357
2358         if (obj->fenced_gpu_access) {
2359                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2360                         ret = i915_gem_flush_ring(obj->last_fenced_ring,
2361                                                   0, obj->base.write_domain);
2362                         if (ret)
2363                                 return ret;
2364                 }
2365
2366                 obj->fenced_gpu_access = false;
2367         }
2368
2369         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2370                 if (!ring_passed_seqno(obj->last_fenced_ring,
2371                                        obj->last_fenced_seqno)) {
2372                         ret = i915_wait_request(obj->last_fenced_ring,
2373                                                 obj->last_fenced_seqno,
2374                                                 true);
2375                         if (ret)
2376                                 return ret;
2377                 }
2378
2379                 obj->last_fenced_seqno = 0;
2380                 obj->last_fenced_ring = NULL;
2381         }
2382
2383         /* Ensure that all CPU reads are completed before installing a fence
2384          * and all writes before removing the fence.
2385          */
2386         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2387                 mb();
2388
2389         return 0;
2390 }
2391
2392 int
2393 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2394 {
2395         int ret;
2396
2397         if (obj->tiling_mode)
2398                 i915_gem_release_mmap(obj);
2399
2400         ret = i915_gem_object_flush_fence(obj, NULL);
2401         if (ret)
2402                 return ret;
2403
2404         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2405                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2406
2407                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count);
2408                 i915_gem_clear_fence_reg(obj->base.dev,
2409                                          &dev_priv->fence_regs[obj->fence_reg]);
2410
2411                 obj->fence_reg = I915_FENCE_REG_NONE;
2412         }
2413
2414         return 0;
2415 }
2416
2417 static struct drm_i915_fence_reg *
2418 i915_find_fence_reg(struct drm_device *dev,
2419                     struct intel_ring_buffer *pipelined)
2420 {
2421         struct drm_i915_private *dev_priv = dev->dev_private;
2422         struct drm_i915_fence_reg *reg, *first, *avail;
2423         int i;
2424
2425         /* First try to find a free reg */
2426         avail = NULL;
2427         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2428                 reg = &dev_priv->fence_regs[i];
2429                 if (!reg->obj)
2430                         return reg;
2431
2432                 if (!reg->pin_count)
2433                         avail = reg;
2434         }
2435
2436         if (avail == NULL)
2437                 return NULL;
2438
2439         /* None available, try to steal one or wait for a user to finish */
2440         avail = first = NULL;
2441         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2442                 if (reg->pin_count)
2443                         continue;
2444
2445                 if (first == NULL)
2446                         first = reg;
2447
2448                 if (!pipelined ||
2449                     !reg->obj->last_fenced_ring ||
2450                     reg->obj->last_fenced_ring == pipelined) {
2451                         avail = reg;
2452                         break;
2453                 }
2454         }
2455
2456         if (avail == NULL)
2457                 avail = first;
2458
2459         return avail;
2460 }
2461
2462 /**
2463  * i915_gem_object_get_fence - set up a fence reg for an object
2464  * @obj: object to map through a fence reg
2465  * @pipelined: ring on which to queue the change, or NULL for CPU access
2466  * @interruptible: must we wait uninterruptibly for the register to retire?
2467  *
2468  * When mapping objects through the GTT, userspace wants to be able to write
2469  * to them without having to worry about swizzling if the object is tiled.
2470  *
2471  * This function walks the fence regs looking for a free one for @obj,
2472  * stealing one if it can't find any.
2473  *
2474  * It then sets up the reg based on the object's properties: address, pitch
2475  * and tiling format.
2476  */
2477 int
2478 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2479                           struct intel_ring_buffer *pipelined)
2480 {
2481         struct drm_device *dev = obj->base.dev;
2482         struct drm_i915_private *dev_priv = dev->dev_private;
2483         struct drm_i915_fence_reg *reg;
2484         int ret;
2485
2486         /* XXX disable pipelining. There are bugs. Shocking. */
2487         pipelined = NULL;
2488
2489         /* Just update our place in the LRU if our fence is getting reused. */
2490         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2491                 reg = &dev_priv->fence_regs[obj->fence_reg];
2492                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2493
2494                 if (obj->tiling_changed) {
2495                         ret = i915_gem_object_flush_fence(obj, pipelined);
2496                         if (ret)
2497                                 return ret;
2498
2499                         if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2500                                 pipelined = NULL;
2501
2502                         if (pipelined) {
2503                                 reg->setup_seqno =
2504                                         i915_gem_next_request_seqno(pipelined);
2505                                 obj->last_fenced_seqno = reg->setup_seqno;
2506                                 obj->last_fenced_ring = pipelined;
2507                         }
2508
2509                         goto update;
2510                 }
2511
2512                 if (!pipelined) {
2513                         if (reg->setup_seqno) {
2514                                 if (!ring_passed_seqno(obj->last_fenced_ring,
2515                                                        reg->setup_seqno)) {
2516                                         ret = i915_wait_request(obj->last_fenced_ring,
2517                                                                 reg->setup_seqno,
2518                                                                 true);
2519                                         if (ret)
2520                                                 return ret;
2521                                 }
2522
2523                                 reg->setup_seqno = 0;
2524                         }
2525                 } else if (obj->last_fenced_ring &&
2526                            obj->last_fenced_ring != pipelined) {
2527                         ret = i915_gem_object_flush_fence(obj, pipelined);
2528                         if (ret)
2529                                 return ret;
2530                 }
2531
2532                 return 0;
2533         }
2534
2535         reg = i915_find_fence_reg(dev, pipelined);
2536         if (reg == NULL)
2537                 return -EDEADLK;
2538
2539         ret = i915_gem_object_flush_fence(obj, pipelined);
2540         if (ret)
2541                 return ret;
2542
2543         if (reg->obj) {
2544                 struct drm_i915_gem_object *old = reg->obj;
2545
2546                 drm_gem_object_reference(&old->base);
2547
2548                 if (old->tiling_mode)
2549                         i915_gem_release_mmap(old);
2550
2551                 ret = i915_gem_object_flush_fence(old, pipelined);
2552                 if (ret) {
2553                         drm_gem_object_unreference(&old->base);
2554                         return ret;
2555                 }
2556
2557                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2558                         pipelined = NULL;
2559
2560                 old->fence_reg = I915_FENCE_REG_NONE;
2561                 old->last_fenced_ring = pipelined;
2562                 old->last_fenced_seqno =
2563                         pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2564
2565                 drm_gem_object_unreference(&old->base);
2566         } else if (obj->last_fenced_seqno == 0)
2567                 pipelined = NULL;
2568
2569         reg->obj = obj;
2570         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2571         obj->fence_reg = reg - dev_priv->fence_regs;
2572         obj->last_fenced_ring = pipelined;
2573
2574         reg->setup_seqno =
2575                 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2576         obj->last_fenced_seqno = reg->setup_seqno;
2577
2578 update:
2579         obj->tiling_changed = false;
2580         switch (INTEL_INFO(dev)->gen) {
2581         case 7:
2582         case 6:
2583                 ret = sandybridge_write_fence_reg(obj, pipelined);
2584                 break;
2585         case 5:
2586         case 4:
2587                 ret = i965_write_fence_reg(obj, pipelined);
2588                 break;
2589         case 3:
2590                 ret = i915_write_fence_reg(obj, pipelined);
2591                 break;
2592         case 2:
2593                 ret = i830_write_fence_reg(obj, pipelined);
2594                 break;
2595         }
2596
2597         return ret;
2598 }
2599
2600 /**
2601  * i915_gem_clear_fence_reg - clear out fence register info
2602  * @obj: object to clear
2603  *
2604  * Zeroes out the fence register itself and clears out the associated
2605  * data structures in dev_priv and obj.
2606  */
2607 static void
2608 i915_gem_clear_fence_reg(struct drm_device *dev,
2609                          struct drm_i915_fence_reg *reg)
2610 {
2611         drm_i915_private_t *dev_priv = dev->dev_private;
2612         uint32_t fence_reg = reg - dev_priv->fence_regs;
2613
2614         switch (INTEL_INFO(dev)->gen) {
2615         case 7:
2616         case 6:
2617                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2618                 break;
2619         case 5:
2620         case 4:
2621                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
2622                 break;
2623         case 3:
2624                 if (fence_reg >= 8)
2625                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2626                 else
2627         case 2:
2628                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2629
2630                 I915_WRITE(fence_reg, 0);
2631                 break;
2632         }
2633
2634         list_del_init(&reg->lru_list);
2635         reg->obj = NULL;
2636         reg->setup_seqno = 0;
2637         reg->pin_count = 0;
2638 }
2639
2640 /**
2641  * Finds free space in the GTT aperture and binds the object there.
2642  */
2643 static int
2644 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2645                             unsigned alignment,
2646                             bool map_and_fenceable)
2647 {
2648         struct drm_device *dev = obj->base.dev;
2649         drm_i915_private_t *dev_priv = dev->dev_private;
2650         struct drm_mm_node *free_space;
2651         gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2652         u32 size, fence_size, fence_alignment, unfenced_alignment;
2653         bool mappable, fenceable;
2654         int ret;
2655
2656         if (obj->madv != I915_MADV_WILLNEED) {
2657                 DRM_ERROR("Attempting to bind a purgeable object\n");
2658                 return -EINVAL;
2659         }
2660
2661         fence_size = i915_gem_get_gtt_size(dev,
2662                                            obj->base.size,
2663                                            obj->tiling_mode);
2664         fence_alignment = i915_gem_get_gtt_alignment(dev,
2665                                                      obj->base.size,
2666                                                      obj->tiling_mode);
2667         unfenced_alignment =
2668                 i915_gem_get_unfenced_gtt_alignment(dev,
2669                                                     obj->base.size,
2670                                                     obj->tiling_mode);
2671
2672         if (alignment == 0)
2673                 alignment = map_and_fenceable ? fence_alignment :
2674                                                 unfenced_alignment;
2675         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2676                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2677                 return -EINVAL;
2678         }
2679
2680         size = map_and_fenceable ? fence_size : obj->base.size;
2681
2682         /* If the object is bigger than the entire aperture, reject it early
2683          * before evicting everything in a vain attempt to find space.
2684          */
2685         if (obj->base.size >
2686             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2687                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2688                 return -E2BIG;
2689         }
2690
2691  search_free:
2692         if (map_and_fenceable)
2693                 free_space =
2694                         drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2695                                                     size, alignment, 0,
2696                                                     dev_priv->mm.gtt_mappable_end,
2697                                                     0);
2698         else
2699                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2700                                                 size, alignment, 0);
2701
2702         if (free_space != NULL) {
2703                 if (map_and_fenceable)
2704                         obj->gtt_space =
2705                                 drm_mm_get_block_range_generic(free_space,
2706                                                                size, alignment, 0,
2707                                                                dev_priv->mm.gtt_mappable_end,
2708                                                                0);
2709                 else
2710                         obj->gtt_space =
2711                                 drm_mm_get_block(free_space, size, alignment);
2712         }
2713         if (obj->gtt_space == NULL) {
2714                 /* If the gtt is empty and we're still having trouble
2715                  * fitting our object in, we're out of memory.
2716                  */
2717                 ret = i915_gem_evict_something(dev, size, alignment,
2718                                                map_and_fenceable);
2719                 if (ret)
2720                         return ret;
2721
2722                 goto search_free;
2723         }
2724
2725         ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2726         if (ret) {
2727                 drm_mm_put_block(obj->gtt_space);
2728                 obj->gtt_space = NULL;
2729
2730                 if (ret == -ENOMEM) {
2731                         /* first try to reclaim some memory by clearing the GTT */
2732                         ret = i915_gem_evict_everything(dev, false);
2733                         if (ret) {
2734                                 /* now try to shrink everyone else */
2735                                 if (gfpmask) {
2736                                         gfpmask = 0;
2737                                         goto search_free;
2738                                 }
2739
2740                                 return -ENOMEM;
2741                         }
2742
2743                         goto search_free;
2744                 }
2745
2746                 return ret;
2747         }
2748
2749         ret = i915_gem_gtt_bind_object(obj);
2750         if (ret) {
2751                 i915_gem_object_put_pages_gtt(obj);
2752                 drm_mm_put_block(obj->gtt_space);
2753                 obj->gtt_space = NULL;
2754
2755                 if (i915_gem_evict_everything(dev, false))
2756                         return ret;
2757
2758                 goto search_free;
2759         }
2760
2761         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2762         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2763
2764         /* Assert that the object is not currently in any GPU domain. As it
2765          * wasn't in the GTT, there shouldn't be any way it could have been in
2766          * a GPU cache
2767          */
2768         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2769         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2770
2771         obj->gtt_offset = obj->gtt_space->start;
2772
2773         fenceable =
2774                 obj->gtt_space->size == fence_size &&
2775                 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2776
2777         mappable =
2778                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2779
2780         obj->map_and_fenceable = mappable && fenceable;
2781
2782         trace_i915_gem_object_bind(obj, map_and_fenceable);
2783         return 0;
2784 }
2785
2786 void
2787 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2788 {
2789         /* If we don't have a page list set up, then we're not pinned
2790          * to GPU, and we can ignore the cache flush because it'll happen
2791          * again at bind time.
2792          */
2793         if (obj->pages == NULL)
2794                 return;
2795
2796         /* If the GPU is snooping the contents of the CPU cache,
2797          * we do not need to manually clear the CPU cache lines.  However,
2798          * the caches are only snooped when the render cache is
2799          * flushed/invalidated.  As we always have to emit invalidations
2800          * and flushes when moving into and out of the RENDER domain, correct
2801          * snooping behaviour occurs naturally as the result of our domain
2802          * tracking.
2803          */
2804         if (obj->cache_level != I915_CACHE_NONE)
2805                 return;
2806
2807         trace_i915_gem_object_clflush(obj);
2808
2809         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2810 }
2811
2812 /** Flushes any GPU write domain for the object if it's dirty. */
2813 static int
2814 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2815 {
2816         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2817                 return 0;
2818
2819         /* Queue the GPU write cache flushing we need. */
2820         return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2821 }
2822
2823 /** Flushes the GTT write domain for the object if it's dirty. */
2824 static void
2825 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2826 {
2827         uint32_t old_write_domain;
2828
2829         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2830                 return;
2831
2832         /* No actual flushing is required for the GTT write domain.  Writes
2833          * to it immediately go to main memory as far as we know, so there's
2834          * no chipset flush.  It also doesn't land in render cache.
2835          *
2836          * However, we do have to enforce the order so that all writes through
2837          * the GTT land before any writes to the device, such as updates to
2838          * the GATT itself.
2839          */
2840         wmb();
2841
2842         old_write_domain = obj->base.write_domain;
2843         obj->base.write_domain = 0;
2844
2845         trace_i915_gem_object_change_domain(obj,
2846                                             obj->base.read_domains,
2847                                             old_write_domain);
2848 }
2849
2850 /** Flushes the CPU write domain for the object if it's dirty. */
2851 static void
2852 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2853 {
2854         uint32_t old_write_domain;
2855
2856         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2857                 return;
2858
2859         i915_gem_clflush_object(obj);
2860         intel_gtt_chipset_flush();
2861         old_write_domain = obj->base.write_domain;
2862         obj->base.write_domain = 0;
2863
2864         trace_i915_gem_object_change_domain(obj,
2865                                             obj->base.read_domains,
2866                                             old_write_domain);
2867 }
2868
2869 /**
2870  * Moves a single object to the GTT read, and possibly write domain.
2871  *
2872  * This function returns when the move is complete, including waiting on
2873  * flushes to occur.
2874  */
2875 int
2876 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2877 {
2878         uint32_t old_write_domain, old_read_domains;
2879         int ret;
2880
2881         /* Not valid to be called on unbound objects. */
2882         if (obj->gtt_space == NULL)
2883                 return -EINVAL;
2884
2885         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2886                 return 0;
2887
2888         ret = i915_gem_object_flush_gpu_write_domain(obj);
2889         if (ret)
2890                 return ret;
2891
2892         if (obj->pending_gpu_write || write) {
2893                 ret = i915_gem_object_wait_rendering(obj);
2894                 if (ret)
2895                         return ret;
2896         }
2897
2898         i915_gem_object_flush_cpu_write_domain(obj);
2899
2900         old_write_domain = obj->base.write_domain;
2901         old_read_domains = obj->base.read_domains;
2902
2903         /* It should now be out of any other write domains, and we can update
2904          * the domain values for our changes.
2905          */
2906         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2907         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2908         if (write) {
2909                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2910                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2911                 obj->dirty = 1;
2912         }
2913
2914         trace_i915_gem_object_change_domain(obj,
2915                                             old_read_domains,
2916                                             old_write_domain);
2917
2918         return 0;
2919 }
2920
2921 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2922                                     enum i915_cache_level cache_level)
2923 {
2924         struct drm_device *dev = obj->base.dev;
2925         drm_i915_private_t *dev_priv = dev->dev_private;
2926         int ret;
2927
2928         if (obj->cache_level == cache_level)
2929                 return 0;
2930
2931         if (obj->pin_count) {
2932                 DRM_DEBUG("can not change the cache level of pinned objects\n");
2933                 return -EBUSY;
2934         }
2935
2936         if (obj->gtt_space) {
2937                 ret = i915_gem_object_finish_gpu(obj);
2938                 if (ret)
2939                         return ret;
2940
2941                 i915_gem_object_finish_gtt(obj);
2942
2943                 /* Before SandyBridge, you could not use tiling or fence
2944                  * registers with snooped memory, so relinquish any fences
2945                  * currently pointing to our region in the aperture.
2946                  */
2947                 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2948                         ret = i915_gem_object_put_fence(obj);
2949                         if (ret)
2950                                 return ret;
2951                 }
2952
2953                 i915_gem_gtt_rebind_object(obj, cache_level);
2954                 if (obj->has_aliasing_ppgtt_mapping)
2955                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2956                                                obj, cache_level);
2957         }
2958
2959         if (cache_level == I915_CACHE_NONE) {
2960                 u32 old_read_domains, old_write_domain;
2961
2962                 /* If we're coming from LLC cached, then we haven't
2963                  * actually been tracking whether the data is in the
2964                  * CPU cache or not, since we only allow one bit set
2965                  * in obj->write_domain and have been skipping the clflushes.
2966                  * Just set it to the CPU cache for now.
2967                  */
2968                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
2969                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
2970
2971                 old_read_domains = obj->base.read_domains;
2972                 old_write_domain = obj->base.write_domain;
2973
2974                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2975                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2976
2977                 trace_i915_gem_object_change_domain(obj,
2978                                                     old_read_domains,
2979                                                     old_write_domain);
2980         }
2981
2982         obj->cache_level = cache_level;
2983         return 0;
2984 }
2985
2986 /*
2987  * Prepare buffer for display plane (scanout, cursors, etc).
2988  * Can be called from an uninterruptible phase (modesetting) and allows
2989  * any flushes to be pipelined (for pageflips).
2990  *
2991  * For the display plane, we want to be in the GTT but out of any write
2992  * domains. So in many ways this looks like set_to_gtt_domain() apart from the
2993  * ability to pipeline the waits, pinning and any additional subtleties
2994  * that may differentiate the display plane from ordinary buffers.
2995  */
2996 int
2997 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2998                                      u32 alignment,
2999                                      struct intel_ring_buffer *pipelined)
3000 {
3001         u32 old_read_domains, old_write_domain;
3002         int ret;
3003
3004         ret = i915_gem_object_flush_gpu_write_domain(obj);
3005         if (ret)
3006                 return ret;
3007
3008         if (pipelined != obj->ring) {
3009                 ret = i915_gem_object_wait_rendering(obj);
3010                 if (ret == -ERESTARTSYS)
3011                         return ret;
3012         }
3013
3014         /* The display engine is not coherent with the LLC cache on gen6.  As
3015          * a result, we make sure that the pinning that is about to occur is
3016          * done with uncached PTEs. This is lowest common denominator for all
3017          * chipsets.
3018          *
3019          * However for gen6+, we could do better by using the GFDT bit instead
3020          * of uncaching, which would allow us to flush all the LLC-cached data
3021          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3022          */
3023         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3024         if (ret)
3025                 return ret;
3026
3027         /* As the user may map the buffer once pinned in the display plane
3028          * (e.g. libkms for the bootup splash), we have to ensure that we
3029          * always use map_and_fenceable for all scanout buffers.
3030          */
3031         ret = i915_gem_object_pin(obj, alignment, true);
3032         if (ret)
3033                 return ret;
3034
3035         i915_gem_object_flush_cpu_write_domain(obj);
3036
3037         old_write_domain = obj->base.write_domain;
3038         old_read_domains = obj->base.read_domains;
3039
3040         /* It should now be out of any other write domains, and we can update
3041          * the domain values for our changes.
3042          */
3043         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3044         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3045
3046         trace_i915_gem_object_change_domain(obj,
3047                                             old_read_domains,
3048                                             old_write_domain);
3049
3050         return 0;
3051 }
3052
3053 int
3054 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3055 {
3056         int ret;
3057
3058         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3059                 return 0;
3060
3061         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3062                 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
3063                 if (ret)
3064                         return ret;
3065         }
3066
3067         ret = i915_gem_object_wait_rendering(obj);
3068         if (ret)
3069                 return ret;
3070
3071         /* Ensure that we invalidate the GPU's caches and TLBs. */
3072         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3073         return 0;
3074 }
3075
3076 /**
3077  * Moves a single object to the CPU read, and possibly write domain.
3078  *
3079  * This function returns when the move is complete, including waiting on
3080  * flushes to occur.
3081  */
3082 static int
3083 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3084 {
3085         uint32_t old_write_domain, old_read_domains;
3086         int ret;
3087
3088         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3089                 return 0;
3090
3091         ret = i915_gem_object_flush_gpu_write_domain(obj);
3092         if (ret)
3093                 return ret;
3094
3095         ret = i915_gem_object_wait_rendering(obj);
3096         if (ret)
3097                 return ret;
3098
3099         i915_gem_object_flush_gtt_write_domain(obj);
3100
3101         /* If we have a partially-valid cache of the object in the CPU,
3102          * finish invalidating it and free the per-page flags.
3103          */
3104         i915_gem_object_set_to_full_cpu_read_domain(obj);
3105
3106         old_write_domain = obj->base.write_domain;
3107         old_read_domains = obj->base.read_domains;
3108
3109         /* Flush the CPU cache if it's still invalid. */
3110         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3111                 i915_gem_clflush_object(obj);
3112
3113                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3114         }
3115
3116         /* It should now be out of any other write domains, and we can update
3117          * the domain values for our changes.
3118          */
3119         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3120
3121         /* If we're writing through the CPU, then the GPU read domains will
3122          * need to be invalidated at next use.
3123          */
3124         if (write) {
3125                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3126                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3127         }
3128
3129         trace_i915_gem_object_change_domain(obj,
3130                                             old_read_domains,
3131                                             old_write_domain);
3132
3133         return 0;
3134 }
3135
3136 /**
3137  * Moves the object from a partially CPU read to a full one.
3138  *
3139  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3140  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3141  */
3142 static void
3143 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
3144 {
3145         if (!obj->page_cpu_valid)
3146                 return;
3147
3148         /* If we're partially in the CPU read domain, finish moving it in.
3149          */
3150         if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
3151                 int i;
3152
3153                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3154                         if (obj->page_cpu_valid[i])
3155                                 continue;
3156                         drm_clflush_pages(obj->pages + i, 1);
3157                 }
3158         }
3159
3160         /* Free the page_cpu_valid mappings which are now stale, whether
3161          * or not we've got I915_GEM_DOMAIN_CPU.
3162          */
3163         kfree(obj->page_cpu_valid);
3164         obj->page_cpu_valid = NULL;
3165 }
3166
3167 /**
3168  * Set the CPU read domain on a range of the object.
3169  *
3170  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3171  * not entirely valid.  The page_cpu_valid member of the object flags which
3172  * pages have been flushed, and will be respected by
3173  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3174  * of the whole object.
3175  *
3176  * This function returns when the move is complete, including waiting on
3177  * flushes to occur.
3178  */
3179 static int
3180 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3181                                           uint64_t offset, uint64_t size)
3182 {
3183         uint32_t old_read_domains;
3184         int i, ret;
3185
3186         if (offset == 0 && size == obj->base.size)
3187                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3188
3189         ret = i915_gem_object_flush_gpu_write_domain(obj);
3190         if (ret)
3191                 return ret;
3192
3193         ret = i915_gem_object_wait_rendering(obj);
3194         if (ret)
3195                 return ret;
3196
3197         i915_gem_object_flush_gtt_write_domain(obj);
3198
3199         /* If we're already fully in the CPU read domain, we're done. */
3200         if (obj->page_cpu_valid == NULL &&
3201             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3202                 return 0;
3203
3204         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3205          * newly adding I915_GEM_DOMAIN_CPU
3206          */
3207         if (obj->page_cpu_valid == NULL) {
3208                 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3209                                               GFP_KERNEL);
3210                 if (obj->page_cpu_valid == NULL)
3211                         return -ENOMEM;
3212         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3213                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3214
3215         /* Flush the cache on any pages that are still invalid from the CPU's
3216          * perspective.
3217          */
3218         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3219              i++) {
3220                 if (obj->page_cpu_valid[i])
3221                         continue;
3222
3223                 drm_clflush_pages(obj->pages + i, 1);
3224
3225                 obj->page_cpu_valid[i] = 1;
3226         }
3227
3228         /* It should now be out of any other write domains, and we can update
3229          * the domain values for our changes.
3230          */
3231         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3232
3233         old_read_domains = obj->base.read_domains;
3234         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3235
3236         trace_i915_gem_object_change_domain(obj,
3237                                             old_read_domains,
3238                                             obj->base.write_domain);
3239
3240         return 0;
3241 }
3242
3243 /* Throttle our rendering by waiting until the ring has completed our requests
3244  * emitted over 20 msec ago.
3245  *
3246  * Note that if we were to use the current jiffies each time around the loop,
3247  * we wouldn't escape the function with any frames outstanding if the time to
3248  * render a frame was over 20ms.
3249  *
3250  * This should get us reasonable parallelism between CPU and GPU but also
3251  * relatively low latency when blocking on a particular request to finish.
3252  */
3253 static int
3254 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3255 {
3256         struct drm_i915_private *dev_priv = dev->dev_private;
3257         struct drm_i915_file_private *file_priv = file->driver_priv;
3258         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3259         struct drm_i915_gem_request *request;
3260         struct intel_ring_buffer *ring = NULL;
3261         u32 seqno = 0;
3262         int ret;
3263
3264         if (atomic_read(&dev_priv->mm.wedged))
3265                 return -EIO;
3266
3267         spin_lock(&file_priv->mm.lock);
3268         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3269                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3270                         break;
3271
3272                 ring = request->ring;
3273                 seqno = request->seqno;
3274         }
3275         spin_unlock(&file_priv->mm.lock);
3276
3277         if (seqno == 0)
3278                 return 0;
3279
3280         ret = 0;
3281         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3282                 /* And wait for the seqno passing without holding any locks and
3283                  * causing extra latency for others. This is safe as the irq
3284                  * generation is designed to be run atomically and so is
3285                  * lockless.
3286                  */
3287                 if (ring->irq_get(ring)) {
3288                         ret = wait_event_interruptible(ring->irq_queue,
3289                                                        i915_seqno_passed(ring->get_seqno(ring), seqno)
3290                                                        || atomic_read(&dev_priv->mm.wedged));
3291                         ring->irq_put(ring);
3292
3293                         if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3294                                 ret = -EIO;
3295                 } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring),
3296                                                              seqno) ||
3297                                     atomic_read(&dev_priv->mm.wedged), 3000)) {
3298                         ret = -EBUSY;
3299                 }
3300         }
3301
3302         if (ret == 0)
3303                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3304
3305         return ret;
3306 }
3307
3308 int
3309 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3310                     uint32_t alignment,
3311                     bool map_and_fenceable)
3312 {
3313         struct drm_device *dev = obj->base.dev;
3314         struct drm_i915_private *dev_priv = dev->dev_private;
3315         int ret;
3316
3317         BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3318         WARN_ON(i915_verify_lists(dev));
3319
3320         if (obj->gtt_space != NULL) {
3321                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3322                     (map_and_fenceable && !obj->map_and_fenceable)) {
3323                         WARN(obj->pin_count,
3324                              "bo is already pinned with incorrect alignment:"
3325                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3326                              " obj->map_and_fenceable=%d\n",
3327                              obj->gtt_offset, alignment,
3328                              map_and_fenceable,
3329                              obj->map_and_fenceable);
3330                         ret = i915_gem_object_unbind(obj);
3331                         if (ret)
3332                                 return ret;
3333                 }
3334         }
3335
3336         if (obj->gtt_space == NULL) {
3337                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3338                                                   map_and_fenceable);
3339                 if (ret)
3340                         return ret;
3341         }
3342
3343         if (obj->pin_count++ == 0) {
3344                 if (!obj->active)
3345                         list_move_tail(&obj->mm_list,
3346                                        &dev_priv->mm.pinned_list);
3347         }
3348         obj->pin_mappable |= map_and_fenceable;
3349
3350         WARN_ON(i915_verify_lists(dev));
3351         return 0;
3352 }
3353
3354 void
3355 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3356 {
3357         struct drm_device *dev = obj->base.dev;
3358         drm_i915_private_t *dev_priv = dev->dev_private;
3359
3360         WARN_ON(i915_verify_lists(dev));
3361         BUG_ON(obj->pin_count == 0);
3362         BUG_ON(obj->gtt_space == NULL);
3363
3364         if (--obj->pin_count == 0) {
3365                 if (!obj->active)
3366                         list_move_tail(&obj->mm_list,
3367                                        &dev_priv->mm.inactive_list);
3368                 obj->pin_mappable = false;
3369         }
3370         WARN_ON(i915_verify_lists(dev));
3371 }
3372
3373 int
3374 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3375                    struct drm_file *file)
3376 {
3377         struct drm_i915_gem_pin *args = data;
3378         struct drm_i915_gem_object *obj;
3379         int ret;
3380
3381         ret = i915_mutex_lock_interruptible(dev);
3382         if (ret)
3383                 return ret;
3384
3385         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3386         if (&obj->base == NULL) {
3387                 ret = -ENOENT;
3388                 goto unlock;
3389         }
3390
3391         if (obj->madv != I915_MADV_WILLNEED) {
3392                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3393                 ret = -EINVAL;
3394                 goto out;
3395         }
3396
3397         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3398                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3399                           args->handle);
3400                 ret = -EINVAL;
3401                 goto out;
3402         }
3403
3404         obj->user_pin_count++;
3405         obj->pin_filp = file;
3406         if (obj->user_pin_count == 1) {
3407                 ret = i915_gem_object_pin(obj, args->alignment, true);
3408                 if (ret)
3409                         goto out;
3410         }
3411
3412         /* XXX - flush the CPU caches for pinned objects
3413          * as the X server doesn't manage domains yet
3414          */
3415         i915_gem_object_flush_cpu_write_domain(obj);
3416         args->offset = obj->gtt_offset;
3417 out:
3418         drm_gem_object_unreference(&obj->base);
3419 unlock:
3420         mutex_unlock(&dev->struct_mutex);
3421         return ret;
3422 }
3423
3424 int
3425 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3426                      struct drm_file *file)
3427 {
3428         struct drm_i915_gem_pin *args = data;
3429         struct drm_i915_gem_object *obj;
3430         int ret;
3431
3432         ret = i915_mutex_lock_interruptible(dev);
3433         if (ret)
3434                 return ret;
3435
3436         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3437         if (&obj->base == NULL) {
3438                 ret = -ENOENT;
3439                 goto unlock;
3440         }
3441
3442         if (obj->pin_filp != file) {
3443                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3444                           args->handle);
3445                 ret = -EINVAL;
3446                 goto out;
3447         }
3448         obj->user_pin_count--;
3449         if (obj->user_pin_count == 0) {
3450                 obj->pin_filp = NULL;
3451                 i915_gem_object_unpin(obj);
3452         }
3453
3454 out:
3455         drm_gem_object_unreference(&obj->base);
3456 unlock:
3457         mutex_unlock(&dev->struct_mutex);
3458         return ret;
3459 }
3460
3461 int
3462 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3463                     struct drm_file *file)
3464 {
3465         struct drm_i915_gem_busy *args = data;
3466         struct drm_i915_gem_object *obj;
3467         int ret;
3468
3469         ret = i915_mutex_lock_interruptible(dev);
3470         if (ret)
3471                 return ret;
3472
3473         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3474         if (&obj->base == NULL) {
3475                 ret = -ENOENT;
3476                 goto unlock;
3477         }
3478
3479         /* Count all active objects as busy, even if they are currently not used
3480          * by the gpu. Users of this interface expect objects to eventually
3481          * become non-busy without any further actions, therefore emit any
3482          * necessary flushes here.
3483          */
3484         args->busy = obj->active;
3485         if (args->busy) {
3486                 /* Unconditionally flush objects, even when the gpu still uses this
3487                  * object. Userspace calling this function indicates that it wants to
3488                  * use this buffer rather sooner than later, so issuing the required
3489                  * flush earlier is beneficial.
3490                  */
3491                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3492                         ret = i915_gem_flush_ring(obj->ring,
3493                                                   0, obj->base.write_domain);
3494                 } else if (obj->ring->outstanding_lazy_request ==
3495                            obj->last_rendering_seqno) {
3496                         struct drm_i915_gem_request *request;
3497
3498                         /* This ring is not being cleared by active usage,
3499                          * so emit a request to do so.
3500                          */
3501                         request = kzalloc(sizeof(*request), GFP_KERNEL);
3502                         if (request) {
3503                                 ret = i915_add_request(obj->ring, NULL, request);
3504                                 if (ret)
3505                                         kfree(request);
3506                         } else
3507                                 ret = -ENOMEM;
3508                 }
3509
3510                 /* Update the active list for the hardware's current position.
3511                  * Otherwise this only updates on a delayed timer or when irqs
3512                  * are actually unmasked, and our working set ends up being
3513                  * larger than required.
3514                  */
3515                 i915_gem_retire_requests_ring(obj->ring);
3516
3517                 args->busy = obj->active;
3518         }
3519
3520         drm_gem_object_unreference(&obj->base);
3521 unlock:
3522         mutex_unlock(&dev->struct_mutex);
3523         return ret;
3524 }
3525
3526 int
3527 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3528                         struct drm_file *file_priv)
3529 {
3530         return i915_gem_ring_throttle(dev, file_priv);
3531 }
3532
3533 int
3534 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3535                        struct drm_file *file_priv)
3536 {
3537         struct drm_i915_gem_madvise *args = data;
3538         struct drm_i915_gem_object *obj;
3539         int ret;
3540
3541         switch (args->madv) {
3542         case I915_MADV_DONTNEED:
3543         case I915_MADV_WILLNEED:
3544             break;
3545         default:
3546             return -EINVAL;
3547         }
3548
3549         ret = i915_mutex_lock_interruptible(dev);
3550         if (ret)
3551                 return ret;
3552
3553         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3554         if (&obj->base == NULL) {
3555                 ret = -ENOENT;
3556                 goto unlock;
3557         }
3558
3559         if (obj->pin_count) {
3560                 ret = -EINVAL;
3561                 goto out;
3562         }
3563
3564         if (obj->madv != __I915_MADV_PURGED)
3565                 obj->madv = args->madv;
3566
3567         /* if the object is no longer bound, discard its backing storage */
3568         if (i915_gem_object_is_purgeable(obj) &&
3569             obj->gtt_space == NULL)
3570                 i915_gem_object_truncate(obj);
3571
3572         args->retained = obj->madv != __I915_MADV_PURGED;
3573
3574 out:
3575         drm_gem_object_unreference(&obj->base);
3576 unlock:
3577         mutex_unlock(&dev->struct_mutex);
3578         return ret;
3579 }
3580
3581 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3582                                                   size_t size)
3583 {
3584         struct drm_i915_private *dev_priv = dev->dev_private;
3585         struct drm_i915_gem_object *obj;
3586         struct address_space *mapping;
3587
3588         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3589         if (obj == NULL)
3590                 return NULL;
3591
3592         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3593                 kfree(obj);
3594                 return NULL;
3595         }
3596
3597         mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3598         mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE);
3599
3600         i915_gem_info_add_obj(dev_priv, size);
3601
3602         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3603         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3604
3605         if (HAS_LLC(dev)) {
3606                 /* On some devices, we can have the GPU use the LLC (the CPU
3607                  * cache) for about a 10% performance improvement
3608                  * compared to uncached.  Graphics requests other than
3609                  * display scanout are coherent with the CPU in
3610                  * accessing this cache.  This means in this mode we
3611                  * don't need to clflush on the CPU side, and on the
3612                  * GPU side we only need to flush internal caches to
3613                  * get data visible to the CPU.
3614                  *
3615                  * However, we maintain the display planes as UC, and so
3616                  * need to rebind when first used as such.
3617                  */
3618                 obj->cache_level = I915_CACHE_LLC;
3619         } else
3620                 obj->cache_level = I915_CACHE_NONE;
3621
3622         obj->base.driver_private = NULL;
3623         obj->fence_reg = I915_FENCE_REG_NONE;
3624         INIT_LIST_HEAD(&obj->mm_list);
3625         INIT_LIST_HEAD(&obj->gtt_list);
3626         INIT_LIST_HEAD(&obj->ring_list);
3627         INIT_LIST_HEAD(&obj->exec_list);
3628         INIT_LIST_HEAD(&obj->gpu_write_list);
3629         obj->madv = I915_MADV_WILLNEED;
3630         /* Avoid an unnecessary call to unbind on the first bind. */
3631         obj->map_and_fenceable = true;
3632
3633         return obj;
3634 }
3635
3636 int i915_gem_init_object(struct drm_gem_object *obj)
3637 {
3638         BUG();
3639
3640         return 0;
3641 }
3642
3643 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3644 {
3645         struct drm_device *dev = obj->base.dev;
3646         drm_i915_private_t *dev_priv = dev->dev_private;
3647         int ret;
3648
3649         ret = i915_gem_object_unbind(obj);
3650         if (ret == -ERESTARTSYS) {
3651                 list_move(&obj->mm_list,
3652                           &dev_priv->mm.deferred_free_list);
3653                 return;
3654         }
3655
3656         trace_i915_gem_object_destroy(obj);
3657
3658         if (obj->base.map_list.map)
3659                 drm_gem_free_mmap_offset(&obj->base);
3660
3661         drm_gem_object_release(&obj->base);
3662         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3663
3664         kfree(obj->page_cpu_valid);
3665         kfree(obj->bit_17);
3666         kfree(obj);
3667 }
3668
3669 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3670 {
3671         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3672         struct drm_device *dev = obj->base.dev;
3673
3674         while (obj->pin_count > 0)
3675                 i915_gem_object_unpin(obj);
3676
3677         if (obj->phys_obj)
3678                 i915_gem_detach_phys_object(dev, obj);
3679
3680         i915_gem_free_object_tail(obj);
3681 }
3682
3683 int
3684 i915_gem_idle(struct drm_device *dev)
3685 {
3686         drm_i915_private_t *dev_priv = dev->dev_private;
3687         int ret;
3688
3689         mutex_lock(&dev->struct_mutex);
3690
3691         if (dev_priv->mm.suspended) {
3692                 mutex_unlock(&dev->struct_mutex);
3693                 return 0;
3694         }
3695
3696         ret = i915_gpu_idle(dev, true);
3697         if (ret) {
3698                 mutex_unlock(&dev->struct_mutex);
3699                 return ret;
3700         }
3701
3702         /* Under UMS, be paranoid and evict. */
3703         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3704                 ret = i915_gem_evict_inactive(dev, false);
3705                 if (ret) {
3706                         mutex_unlock(&dev->struct_mutex);
3707                         return ret;
3708                 }
3709         }
3710
3711         i915_gem_reset_fences(dev);
3712
3713         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3714          * We need to replace this with a semaphore, or something.
3715          * And not confound mm.suspended!
3716          */
3717         dev_priv->mm.suspended = 1;
3718         del_timer_sync(&dev_priv->hangcheck_timer);
3719
3720         i915_kernel_lost_context(dev);
3721         i915_gem_cleanup_ringbuffer(dev);
3722
3723         mutex_unlock(&dev->struct_mutex);
3724
3725         /* Cancel the retire work handler, which should be idle now. */
3726         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3727
3728         return 0;
3729 }
3730
3731 void i915_gem_init_swizzling(struct drm_device *dev)
3732 {
3733         drm_i915_private_t *dev_priv = dev->dev_private;
3734
3735         if (INTEL_INFO(dev)->gen < 5 ||
3736             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3737                 return;
3738
3739         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3740                                  DISP_TILE_SURFACE_SWIZZLING);
3741
3742         if (IS_GEN5(dev))
3743                 return;
3744
3745         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3746         if (IS_GEN6(dev))
3747                 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB));
3748         else
3749                 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB));
3750 }
3751
3752 void i915_gem_init_ppgtt(struct drm_device *dev)
3753 {
3754         drm_i915_private_t *dev_priv = dev->dev_private;
3755         uint32_t pd_offset;
3756         struct intel_ring_buffer *ring;
3757         int i;
3758
3759         if (!dev_priv->mm.aliasing_ppgtt)
3760                 return;
3761
3762         pd_offset = dev_priv->mm.aliasing_ppgtt->pd_offset;
3763         pd_offset /= 64; /* in cachelines, */
3764         pd_offset <<= 16;
3765
3766         if (INTEL_INFO(dev)->gen == 6) {
3767                 uint32_t ecochk = I915_READ(GAM_ECOCHK);
3768                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
3769                                        ECOCHK_PPGTT_CACHE64B);
3770                 I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
3771         } else if (INTEL_INFO(dev)->gen >= 7) {
3772                 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
3773                 /* GFX_MODE is per-ring on gen7+ */
3774         }
3775
3776         for (i = 0; i < I915_NUM_RINGS; i++) {
3777                 ring = &dev_priv->ring[i];
3778
3779                 if (INTEL_INFO(dev)->gen >= 7)
3780                         I915_WRITE(RING_MODE_GEN7(ring),
3781                                    GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
3782
3783                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
3784                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
3785         }
3786 }
3787
3788 int
3789 i915_gem_init_hw(struct drm_device *dev)
3790 {
3791         drm_i915_private_t *dev_priv = dev->dev_private;
3792         int ret;
3793
3794         i915_gem_init_swizzling(dev);
3795
3796         ret = intel_init_render_ring_buffer(dev);
3797         if (ret)
3798                 return ret;
3799
3800         if (HAS_BSD(dev)) {
3801                 ret = intel_init_bsd_ring_buffer(dev);
3802                 if (ret)
3803                         goto cleanup_render_ring;
3804         }
3805
3806         if (HAS_BLT(dev)) {
3807                 ret = intel_init_blt_ring_buffer(dev);
3808                 if (ret)
3809                         goto cleanup_bsd_ring;
3810         }
3811
3812         dev_priv->next_seqno = 1;
3813
3814         i915_gem_init_ppgtt(dev);
3815
3816         return 0;
3817
3818 cleanup_bsd_ring:
3819         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3820 cleanup_render_ring:
3821         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3822         return ret;
3823 }
3824
3825 void
3826 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3827 {
3828         drm_i915_private_t *dev_priv = dev->dev_private;
3829         int i;
3830
3831         for (i = 0; i < I915_NUM_RINGS; i++)
3832                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
3833 }
3834
3835 int
3836 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3837                        struct drm_file *file_priv)
3838 {
3839         drm_i915_private_t *dev_priv = dev->dev_private;
3840         int ret, i;
3841
3842         if (drm_core_check_feature(dev, DRIVER_MODESET))
3843                 return 0;
3844
3845         if (atomic_read(&dev_priv->mm.wedged)) {
3846                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3847                 atomic_set(&dev_priv->mm.wedged, 0);
3848         }
3849
3850         mutex_lock(&dev->struct_mutex);
3851         dev_priv->mm.suspended = 0;
3852
3853         ret = i915_gem_init_hw(dev);
3854         if (ret != 0) {
3855                 mutex_unlock(&dev->struct_mutex);
3856                 return ret;
3857         }
3858
3859         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3860         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3861         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3862         for (i = 0; i < I915_NUM_RINGS; i++) {
3863                 BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
3864                 BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
3865         }
3866         mutex_unlock(&dev->struct_mutex);
3867
3868         ret = drm_irq_install(dev);
3869         if (ret)
3870                 goto cleanup_ringbuffer;
3871
3872         return 0;
3873
3874 cleanup_ringbuffer:
3875         mutex_lock(&dev->struct_mutex);
3876         i915_gem_cleanup_ringbuffer(dev);
3877         dev_priv->mm.suspended = 1;
3878         mutex_unlock(&dev->struct_mutex);
3879
3880         return ret;
3881 }
3882
3883 int
3884 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3885                        struct drm_file *file_priv)
3886 {
3887         if (drm_core_check_feature(dev, DRIVER_MODESET))
3888                 return 0;
3889
3890         drm_irq_uninstall(dev);
3891         return i915_gem_idle(dev);
3892 }
3893
3894 void
3895 i915_gem_lastclose(struct drm_device *dev)
3896 {
3897         int ret;
3898
3899         if (drm_core_check_feature(dev, DRIVER_MODESET))
3900                 return;
3901
3902         ret = i915_gem_idle(dev);
3903         if (ret)
3904                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3905 }
3906
3907 static void
3908 init_ring_lists(struct intel_ring_buffer *ring)
3909 {
3910         INIT_LIST_HEAD(&ring->active_list);
3911         INIT_LIST_HEAD(&ring->request_list);
3912         INIT_LIST_HEAD(&ring->gpu_write_list);
3913 }
3914
3915 void
3916 i915_gem_load(struct drm_device *dev)
3917 {
3918         int i;
3919         drm_i915_private_t *dev_priv = dev->dev_private;
3920
3921         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3922         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3923         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3924         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3925         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3926         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3927         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3928         for (i = 0; i < I915_NUM_RINGS; i++)
3929                 init_ring_lists(&dev_priv->ring[i]);
3930         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3931                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3932         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3933                           i915_gem_retire_work_handler);
3934         init_completion(&dev_priv->error_completion);
3935
3936         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3937         if (IS_GEN3(dev)) {
3938                 u32 tmp = I915_READ(MI_ARB_STATE);
3939                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3940                         /* arb state is a masked write, so set bit + bit in mask */
3941                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3942                         I915_WRITE(MI_ARB_STATE, tmp);
3943                 }
3944         }
3945
3946         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3947
3948         /* Old X drivers will take 0-2 for front, back, depth buffers */
3949         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3950                 dev_priv->fence_reg_start = 3;
3951
3952         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3953                 dev_priv->num_fence_regs = 16;
3954         else
3955                 dev_priv->num_fence_regs = 8;
3956
3957         /* Initialize fence registers to zero */
3958         for (i = 0; i < dev_priv->num_fence_regs; i++) {
3959                 i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
3960         }
3961
3962         i915_gem_detect_bit_6_swizzle(dev);
3963         init_waitqueue_head(&dev_priv->pending_flip_queue);
3964
3965         dev_priv->mm.interruptible = true;
3966
3967         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3968         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3969         register_shrinker(&dev_priv->mm.inactive_shrinker);
3970 }
3971
3972 /*
3973  * Create a physically contiguous memory object for this object
3974  * e.g. for cursor + overlay regs
3975  */
3976 static int i915_gem_init_phys_object(struct drm_device *dev,
3977                                      int id, int size, int align)
3978 {
3979         drm_i915_private_t *dev_priv = dev->dev_private;
3980         struct drm_i915_gem_phys_object *phys_obj;
3981         int ret;
3982
3983         if (dev_priv->mm.phys_objs[id - 1] || !size)
3984                 return 0;
3985
3986         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3987         if (!phys_obj)
3988                 return -ENOMEM;
3989
3990         phys_obj->id = id;
3991
3992         phys_obj->handle = drm_pci_alloc(dev, size, align);
3993         if (!phys_obj->handle) {
3994                 ret = -ENOMEM;
3995                 goto kfree_obj;
3996         }
3997 #ifdef CONFIG_X86
3998         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3999 #endif
4000
4001         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4002
4003         return 0;
4004 kfree_obj:
4005         kfree(phys_obj);
4006         return ret;
4007 }
4008
4009 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4010 {
4011         drm_i915_private_t *dev_priv = dev->dev_private;
4012         struct drm_i915_gem_phys_object *phys_obj;
4013
4014         if (!dev_priv->mm.phys_objs[id - 1])
4015                 return;
4016
4017         phys_obj = dev_priv->mm.phys_objs[id - 1];
4018         if (phys_obj->cur_obj) {
4019                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4020         }
4021
4022 #ifdef CONFIG_X86
4023         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4024 #endif
4025         drm_pci_free(dev, phys_obj->handle);
4026         kfree(phys_obj);
4027         dev_priv->mm.phys_objs[id - 1] = NULL;
4028 }
4029
4030 void i915_gem_free_all_phys_object(struct drm_device *dev)
4031 {
4032         int i;
4033
4034         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4035                 i915_gem_free_phys_object(dev, i);
4036 }
4037
4038 void i915_gem_detach_phys_object(struct drm_device *dev,
4039                                  struct drm_i915_gem_object *obj)
4040 {
4041         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4042         char *vaddr;
4043         int i;
4044         int page_count;
4045
4046         if (!obj->phys_obj)
4047                 return;
4048         vaddr = obj->phys_obj->handle->vaddr;
4049
4050         page_count = obj->base.size / PAGE_SIZE;
4051         for (i = 0; i < page_count; i++) {
4052                 struct page *page = shmem_read_mapping_page(mapping, i);
4053                 if (!IS_ERR(page)) {
4054                         char *dst = kmap_atomic(page);
4055                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4056                         kunmap_atomic(dst);
4057
4058                         drm_clflush_pages(&page, 1);
4059
4060                         set_page_dirty(page);
4061                         mark_page_accessed(page);
4062                         page_cache_release(page);
4063                 }
4064         }
4065         intel_gtt_chipset_flush();
4066
4067         obj->phys_obj->cur_obj = NULL;
4068         obj->phys_obj = NULL;
4069 }
4070
4071 int
4072 i915_gem_attach_phys_object(struct drm_device *dev,
4073                             struct drm_i915_gem_object *obj,
4074                             int id,
4075                             int align)
4076 {
4077         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4078         drm_i915_private_t *dev_priv = dev->dev_private;
4079         int ret = 0;
4080         int page_count;
4081         int i;
4082
4083         if (id > I915_MAX_PHYS_OBJECT)
4084                 return -EINVAL;
4085
4086         if (obj->phys_obj) {
4087                 if (obj->phys_obj->id == id)
4088                         return 0;
4089                 i915_gem_detach_phys_object(dev, obj);
4090         }
4091
4092         /* create a new object */
4093         if (!dev_priv->mm.phys_objs[id - 1]) {
4094                 ret = i915_gem_init_phys_object(dev, id,
4095                                                 obj->base.size, align);
4096                 if (ret) {
4097                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4098                                   id, obj->base.size);
4099                         return ret;
4100                 }
4101         }
4102
4103         /* bind to the object */
4104         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4105         obj->phys_obj->cur_obj = obj;
4106
4107         page_count = obj->base.size / PAGE_SIZE;
4108
4109         for (i = 0; i < page_count; i++) {
4110                 struct page *page;
4111                 char *dst, *src;
4112
4113                 page = shmem_read_mapping_page(mapping, i);
4114                 if (IS_ERR(page))
4115                         return PTR_ERR(page);
4116
4117                 src = kmap_atomic(page);
4118                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4119                 memcpy(dst, src, PAGE_SIZE);
4120                 kunmap_atomic(src);
4121
4122                 mark_page_accessed(page);
4123                 page_cache_release(page);
4124         }
4125
4126         return 0;
4127 }
4128
4129 static int
4130 i915_gem_phys_pwrite(struct drm_device *dev,
4131                      struct drm_i915_gem_object *obj,
4132                      struct drm_i915_gem_pwrite *args,
4133                      struct drm_file *file_priv)
4134 {
4135         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4136         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4137
4138         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4139                 unsigned long unwritten;
4140
4141                 /* The physical object once assigned is fixed for the lifetime
4142                  * of the obj, so we can safely drop the lock and continue
4143                  * to access vaddr.
4144                  */
4145                 mutex_unlock(&dev->struct_mutex);
4146                 unwritten = copy_from_user(vaddr, user_data, args->size);
4147                 mutex_lock(&dev->struct_mutex);
4148                 if (unwritten)
4149                         return -EFAULT;
4150         }
4151
4152         intel_gtt_chipset_flush();
4153         return 0;
4154 }
4155
4156 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4157 {
4158         struct drm_i915_file_private *file_priv = file->driver_priv;
4159
4160         /* Clean up our request list when the client is going away, so that
4161          * later retire_requests won't dereference our soon-to-be-gone
4162          * file_priv.
4163          */
4164         spin_lock(&file_priv->mm.lock);
4165         while (!list_empty(&file_priv->mm.request_list)) {
4166                 struct drm_i915_gem_request *request;
4167
4168                 request = list_first_entry(&file_priv->mm.request_list,
4169                                            struct drm_i915_gem_request,
4170                                            client_list);
4171                 list_del(&request->client_list);
4172                 request->file_priv = NULL;
4173         }
4174         spin_unlock(&file_priv->mm.lock);
4175 }
4176
4177 static int
4178 i915_gpu_is_active(struct drm_device *dev)
4179 {
4180         drm_i915_private_t *dev_priv = dev->dev_private;
4181         int lists_empty;
4182
4183         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4184                       list_empty(&dev_priv->mm.active_list);
4185
4186         return !lists_empty;
4187 }
4188
4189 static int
4190 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4191 {
4192         struct drm_i915_private *dev_priv =
4193                 container_of(shrinker,
4194                              struct drm_i915_private,
4195                              mm.inactive_shrinker);
4196         struct drm_device *dev = dev_priv->dev;
4197         struct drm_i915_gem_object *obj, *next;
4198         int nr_to_scan = sc->nr_to_scan;
4199         int cnt;
4200
4201         if (!mutex_trylock(&dev->struct_mutex))
4202                 return 0;
4203
4204         /* "fast-path" to count number of available objects */
4205         if (nr_to_scan == 0) {
4206                 cnt = 0;
4207                 list_for_each_entry(obj,
4208                                     &dev_priv->mm.inactive_list,
4209                                     mm_list)
4210                         cnt++;
4211                 mutex_unlock(&dev->struct_mutex);
4212                 return cnt / 100 * sysctl_vfs_cache_pressure;
4213         }
4214
4215 rescan:
4216         /* first scan for clean buffers */
4217         i915_gem_retire_requests(dev);
4218
4219         list_for_each_entry_safe(obj, next,
4220                                  &dev_priv->mm.inactive_list,
4221                                  mm_list) {
4222                 if (i915_gem_object_is_purgeable(obj)) {
4223                         if (i915_gem_object_unbind(obj) == 0 &&
4224                             --nr_to_scan == 0)
4225                                 break;
4226                 }
4227         }
4228
4229         /* second pass, evict/count anything still on the inactive list */
4230         cnt = 0;
4231         list_for_each_entry_safe(obj, next,
4232                                  &dev_priv->mm.inactive_list,
4233                                  mm_list) {
4234                 if (nr_to_scan &&
4235                     i915_gem_object_unbind(obj) == 0)
4236                         nr_to_scan--;
4237                 else
4238                         cnt++;
4239         }
4240
4241         if (nr_to_scan && i915_gpu_is_active(dev)) {
4242                 /*
4243                  * We are desperate for pages, so as a last resort, wait
4244                  * for the GPU to finish and discard whatever we can.
4245                  * This has a dramatic impact to reduce the number of
4246                  * OOM-killer events whilst running the GPU aggressively.
4247                  */
4248                 if (i915_gpu_idle(dev, true) == 0)
4249                         goto rescan;
4250         }
4251         mutex_unlock(&dev->struct_mutex);
4252         return cnt / 100 * sysctl_vfs_cache_pressure;
4253 }