2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_mocs.h"
36 #include <linux/shmem_fs.h>
37 #include <linux/slab.h>
38 #include <linux/swap.h>
39 #include <linux/pci.h>
40 #include <linux/dma-buf.h>
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
45 i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
47 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
49 static bool cpu_cache_is_coherent(struct drm_device *dev,
50 enum i915_cache_level level)
52 return HAS_LLC(dev) || level != I915_CACHE_NONE;
55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
57 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
60 return obj->pin_display;
63 /* some bookkeeping */
64 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
67 spin_lock(&dev_priv->mm.object_stat_lock);
68 dev_priv->mm.object_count++;
69 dev_priv->mm.object_memory += size;
70 spin_unlock(&dev_priv->mm.object_stat_lock);
73 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
76 spin_lock(&dev_priv->mm.object_stat_lock);
77 dev_priv->mm.object_count--;
78 dev_priv->mm.object_memory -= size;
79 spin_unlock(&dev_priv->mm.object_stat_lock);
83 i915_gem_wait_for_error(struct i915_gpu_error *error)
87 if (!i915_reset_in_progress(error))
91 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
92 * userspace. If it takes that long something really bad is going on and
93 * we should simply try to bail out and fail as gracefully as possible.
95 ret = wait_event_interruptible_timeout(error->reset_queue,
96 !i915_reset_in_progress(error),
99 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
101 } else if (ret < 0) {
108 int i915_mutex_lock_interruptible(struct drm_device *dev)
110 struct drm_i915_private *dev_priv = dev->dev_private;
113 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
117 ret = mutex_lock_interruptible(&dev->struct_mutex);
121 WARN_ON(i915_verify_lists(dev));
126 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
127 struct drm_file *file)
129 struct drm_i915_private *dev_priv = to_i915(dev);
130 struct i915_ggtt *ggtt = &dev_priv->ggtt;
131 struct drm_i915_gem_get_aperture *args = data;
132 struct i915_vma *vma;
136 mutex_lock(&dev->struct_mutex);
137 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
139 pinned += vma->node.size;
140 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
142 pinned += vma->node.size;
143 mutex_unlock(&dev->struct_mutex);
145 args->aper_size = ggtt->base.total;
146 args->aper_available_size = args->aper_size - pinned;
152 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
154 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
155 char *vaddr = obj->phys_handle->vaddr;
157 struct scatterlist *sg;
160 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
163 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
167 page = shmem_read_mapping_page(mapping, i);
169 return PTR_ERR(page);
171 src = kmap_atomic(page);
172 memcpy(vaddr, src, PAGE_SIZE);
173 drm_clflush_virt_range(vaddr, PAGE_SIZE);
180 i915_gem_chipset_flush(obj->base.dev);
182 st = kmalloc(sizeof(*st), GFP_KERNEL);
186 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
193 sg->length = obj->base.size;
195 sg_dma_address(sg) = obj->phys_handle->busaddr;
196 sg_dma_len(sg) = obj->base.size;
203 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
207 BUG_ON(obj->madv == __I915_MADV_PURGED);
209 ret = i915_gem_object_set_to_cpu_domain(obj, true);
211 /* In the event of a disaster, abandon all caches and
214 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
217 if (obj->madv == I915_MADV_DONTNEED)
221 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
222 char *vaddr = obj->phys_handle->vaddr;
225 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
229 page = shmem_read_mapping_page(mapping, i);
233 dst = kmap_atomic(page);
234 drm_clflush_virt_range(vaddr, PAGE_SIZE);
235 memcpy(dst, vaddr, PAGE_SIZE);
238 set_page_dirty(page);
239 if (obj->madv == I915_MADV_WILLNEED)
240 mark_page_accessed(page);
247 sg_free_table(obj->pages);
252 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
254 drm_pci_free(obj->base.dev, obj->phys_handle);
257 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
258 .get_pages = i915_gem_object_get_pages_phys,
259 .put_pages = i915_gem_object_put_pages_phys,
260 .release = i915_gem_object_release_phys,
264 drop_pages(struct drm_i915_gem_object *obj)
266 struct i915_vma *vma, *next;
269 drm_gem_object_reference(&obj->base);
270 list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link)
271 if (i915_vma_unbind(vma))
274 ret = i915_gem_object_put_pages(obj);
275 drm_gem_object_unreference(&obj->base);
281 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
284 drm_dma_handle_t *phys;
287 if (obj->phys_handle) {
288 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
294 if (obj->madv != I915_MADV_WILLNEED)
297 if (obj->base.filp == NULL)
300 ret = drop_pages(obj);
304 /* create a new object */
305 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
309 obj->phys_handle = phys;
310 obj->ops = &i915_gem_phys_ops;
312 return i915_gem_object_get_pages(obj);
316 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
317 struct drm_i915_gem_pwrite *args,
318 struct drm_file *file_priv)
320 struct drm_device *dev = obj->base.dev;
321 void *vaddr = obj->phys_handle->vaddr + args->offset;
322 char __user *user_data = to_user_ptr(args->data_ptr);
325 /* We manually control the domain here and pretend that it
326 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
328 ret = i915_gem_object_wait_rendering(obj, false);
332 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
333 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
334 unsigned long unwritten;
336 /* The physical object once assigned is fixed for the lifetime
337 * of the obj, so we can safely drop the lock and continue
340 mutex_unlock(&dev->struct_mutex);
341 unwritten = copy_from_user(vaddr, user_data, args->size);
342 mutex_lock(&dev->struct_mutex);
349 drm_clflush_virt_range(vaddr, args->size);
350 i915_gem_chipset_flush(dev);
353 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
357 void *i915_gem_object_alloc(struct drm_device *dev)
359 struct drm_i915_private *dev_priv = dev->dev_private;
360 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
363 void i915_gem_object_free(struct drm_i915_gem_object *obj)
365 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
366 kmem_cache_free(dev_priv->objects, obj);
370 i915_gem_create(struct drm_file *file,
371 struct drm_device *dev,
375 struct drm_i915_gem_object *obj;
379 size = roundup(size, PAGE_SIZE);
383 /* Allocate the new object */
384 obj = i915_gem_object_create(dev, size);
388 ret = drm_gem_handle_create(file, &obj->base, &handle);
389 /* drop reference from allocate - handle holds it now */
390 drm_gem_object_unreference_unlocked(&obj->base);
399 i915_gem_dumb_create(struct drm_file *file,
400 struct drm_device *dev,
401 struct drm_mode_create_dumb *args)
403 /* have to work out size/pitch and return them */
404 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
405 args->size = args->pitch * args->height;
406 return i915_gem_create(file, dev,
407 args->size, &args->handle);
411 * Creates a new mm object and returns a handle to it.
414 i915_gem_create_ioctl(struct drm_device *dev, void *data,
415 struct drm_file *file)
417 struct drm_i915_gem_create *args = data;
419 return i915_gem_create(file, dev,
420 args->size, &args->handle);
424 __copy_to_user_swizzled(char __user *cpu_vaddr,
425 const char *gpu_vaddr, int gpu_offset,
428 int ret, cpu_offset = 0;
431 int cacheline_end = ALIGN(gpu_offset + 1, 64);
432 int this_length = min(cacheline_end - gpu_offset, length);
433 int swizzled_gpu_offset = gpu_offset ^ 64;
435 ret = __copy_to_user(cpu_vaddr + cpu_offset,
436 gpu_vaddr + swizzled_gpu_offset,
441 cpu_offset += this_length;
442 gpu_offset += this_length;
443 length -= this_length;
450 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
451 const char __user *cpu_vaddr,
454 int ret, cpu_offset = 0;
457 int cacheline_end = ALIGN(gpu_offset + 1, 64);
458 int this_length = min(cacheline_end - gpu_offset, length);
459 int swizzled_gpu_offset = gpu_offset ^ 64;
461 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
462 cpu_vaddr + cpu_offset,
467 cpu_offset += this_length;
468 gpu_offset += this_length;
469 length -= this_length;
476 * Pins the specified object's pages and synchronizes the object with
477 * GPU accesses. Sets needs_clflush to non-zero if the caller should
478 * flush the object from the CPU cache.
480 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
487 if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0))
490 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
491 /* If we're not in the cpu read domain, set ourself into the gtt
492 * read domain and manually flush cachelines (if required). This
493 * optimizes for the case when the gpu will dirty the data
494 * anyway again before the next pread happens. */
495 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
497 ret = i915_gem_object_wait_rendering(obj, true);
502 ret = i915_gem_object_get_pages(obj);
506 i915_gem_object_pin_pages(obj);
511 /* Per-page copy function for the shmem pread fastpath.
512 * Flushes invalid cachelines before reading the target if
513 * needs_clflush is set. */
515 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
516 char __user *user_data,
517 bool page_do_bit17_swizzling, bool needs_clflush)
522 if (unlikely(page_do_bit17_swizzling))
525 vaddr = kmap_atomic(page);
527 drm_clflush_virt_range(vaddr + shmem_page_offset,
529 ret = __copy_to_user_inatomic(user_data,
530 vaddr + shmem_page_offset,
532 kunmap_atomic(vaddr);
534 return ret ? -EFAULT : 0;
538 shmem_clflush_swizzled_range(char *addr, unsigned long length,
541 if (unlikely(swizzled)) {
542 unsigned long start = (unsigned long) addr;
543 unsigned long end = (unsigned long) addr + length;
545 /* For swizzling simply ensure that we always flush both
546 * channels. Lame, but simple and it works. Swizzled
547 * pwrite/pread is far from a hotpath - current userspace
548 * doesn't use it at all. */
549 start = round_down(start, 128);
550 end = round_up(end, 128);
552 drm_clflush_virt_range((void *)start, end - start);
554 drm_clflush_virt_range(addr, length);
559 /* Only difference to the fast-path function is that this can handle bit17
560 * and uses non-atomic copy and kmap functions. */
562 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
563 char __user *user_data,
564 bool page_do_bit17_swizzling, bool needs_clflush)
571 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
573 page_do_bit17_swizzling);
575 if (page_do_bit17_swizzling)
576 ret = __copy_to_user_swizzled(user_data,
577 vaddr, shmem_page_offset,
580 ret = __copy_to_user(user_data,
581 vaddr + shmem_page_offset,
585 return ret ? - EFAULT : 0;
589 i915_gem_shmem_pread(struct drm_device *dev,
590 struct drm_i915_gem_object *obj,
591 struct drm_i915_gem_pread *args,
592 struct drm_file *file)
594 char __user *user_data;
597 int shmem_page_offset, page_length, ret = 0;
598 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
600 int needs_clflush = 0;
601 struct sg_page_iter sg_iter;
603 user_data = to_user_ptr(args->data_ptr);
606 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
608 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
612 offset = args->offset;
614 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
615 offset >> PAGE_SHIFT) {
616 struct page *page = sg_page_iter_page(&sg_iter);
621 /* Operation in this page
623 * shmem_page_offset = offset within page in shmem file
624 * page_length = bytes to copy for this page
626 shmem_page_offset = offset_in_page(offset);
627 page_length = remain;
628 if ((shmem_page_offset + page_length) > PAGE_SIZE)
629 page_length = PAGE_SIZE - shmem_page_offset;
631 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
632 (page_to_phys(page) & (1 << 17)) != 0;
634 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
635 user_data, page_do_bit17_swizzling,
640 mutex_unlock(&dev->struct_mutex);
642 if (likely(!i915.prefault_disable) && !prefaulted) {
643 ret = fault_in_multipages_writeable(user_data, remain);
644 /* Userspace is tricking us, but we've already clobbered
645 * its pages with the prefault and promised to write the
646 * data up to the first fault. Hence ignore any errors
647 * and just continue. */
652 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
653 user_data, page_do_bit17_swizzling,
656 mutex_lock(&dev->struct_mutex);
662 remain -= page_length;
663 user_data += page_length;
664 offset += page_length;
668 i915_gem_object_unpin_pages(obj);
674 * Reads data from the object referenced by handle.
676 * On error, the contents of *data are undefined.
679 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
680 struct drm_file *file)
682 struct drm_i915_gem_pread *args = data;
683 struct drm_i915_gem_object *obj;
689 if (!access_ok(VERIFY_WRITE,
690 to_user_ptr(args->data_ptr),
694 ret = i915_mutex_lock_interruptible(dev);
698 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
699 if (&obj->base == NULL) {
704 /* Bounds check source. */
705 if (args->offset > obj->base.size ||
706 args->size > obj->base.size - args->offset) {
711 /* prime objects have no backing filp to GEM pread/pwrite
714 if (!obj->base.filp) {
719 trace_i915_gem_object_pread(obj, args->offset, args->size);
721 ret = i915_gem_shmem_pread(dev, obj, args, file);
724 drm_gem_object_unreference(&obj->base);
726 mutex_unlock(&dev->struct_mutex);
730 /* This is the fast write path which cannot handle
731 * page faults in the source data
735 fast_user_write(struct io_mapping *mapping,
736 loff_t page_base, int page_offset,
737 char __user *user_data,
740 void __iomem *vaddr_atomic;
742 unsigned long unwritten;
744 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
745 /* We can use the cpu mem copy function because this is X86. */
746 vaddr = (void __force*)vaddr_atomic + page_offset;
747 unwritten = __copy_from_user_inatomic_nocache(vaddr,
749 io_mapping_unmap_atomic(vaddr_atomic);
754 * This is the fast pwrite path, where we copy the data directly from the
755 * user into the GTT, uncached.
758 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
759 struct drm_i915_gem_object *obj,
760 struct drm_i915_gem_pwrite *args,
761 struct drm_file *file)
763 struct drm_i915_private *dev_priv = to_i915(dev);
764 struct i915_ggtt *ggtt = &dev_priv->ggtt;
766 loff_t offset, page_base;
767 char __user *user_data;
768 int page_offset, page_length, ret;
770 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
774 ret = i915_gem_object_set_to_gtt_domain(obj, true);
778 ret = i915_gem_object_put_fence(obj);
782 user_data = to_user_ptr(args->data_ptr);
785 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
787 intel_fb_obj_invalidate(obj, ORIGIN_GTT);
790 /* Operation in this page
792 * page_base = page offset within aperture
793 * page_offset = offset within page
794 * page_length = bytes to copy for this page
796 page_base = offset & PAGE_MASK;
797 page_offset = offset_in_page(offset);
798 page_length = remain;
799 if ((page_offset + remain) > PAGE_SIZE)
800 page_length = PAGE_SIZE - page_offset;
802 /* If we get a fault while copying data, then (presumably) our
803 * source page isn't available. Return the error and we'll
804 * retry in the slow path.
806 if (fast_user_write(ggtt->mappable, page_base,
807 page_offset, user_data, page_length)) {
812 remain -= page_length;
813 user_data += page_length;
814 offset += page_length;
818 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
820 i915_gem_object_ggtt_unpin(obj);
825 /* Per-page copy function for the shmem pwrite fastpath.
826 * Flushes invalid cachelines before writing to the target if
827 * needs_clflush_before is set and flushes out any written cachelines after
828 * writing if needs_clflush is set. */
830 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
831 char __user *user_data,
832 bool page_do_bit17_swizzling,
833 bool needs_clflush_before,
834 bool needs_clflush_after)
839 if (unlikely(page_do_bit17_swizzling))
842 vaddr = kmap_atomic(page);
843 if (needs_clflush_before)
844 drm_clflush_virt_range(vaddr + shmem_page_offset,
846 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
847 user_data, page_length);
848 if (needs_clflush_after)
849 drm_clflush_virt_range(vaddr + shmem_page_offset,
851 kunmap_atomic(vaddr);
853 return ret ? -EFAULT : 0;
856 /* Only difference to the fast-path function is that this can handle bit17
857 * and uses non-atomic copy and kmap functions. */
859 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
860 char __user *user_data,
861 bool page_do_bit17_swizzling,
862 bool needs_clflush_before,
863 bool needs_clflush_after)
869 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
870 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
872 page_do_bit17_swizzling);
873 if (page_do_bit17_swizzling)
874 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
878 ret = __copy_from_user(vaddr + shmem_page_offset,
881 if (needs_clflush_after)
882 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
884 page_do_bit17_swizzling);
887 return ret ? -EFAULT : 0;
891 i915_gem_shmem_pwrite(struct drm_device *dev,
892 struct drm_i915_gem_object *obj,
893 struct drm_i915_gem_pwrite *args,
894 struct drm_file *file)
898 char __user *user_data;
899 int shmem_page_offset, page_length, ret = 0;
900 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
901 int hit_slowpath = 0;
902 int needs_clflush_after = 0;
903 int needs_clflush_before = 0;
904 struct sg_page_iter sg_iter;
906 user_data = to_user_ptr(args->data_ptr);
909 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
911 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
912 /* If we're not in the cpu write domain, set ourself into the gtt
913 * write domain and manually flush cachelines (if required). This
914 * optimizes for the case when the gpu will use the data
915 * right away and we therefore have to clflush anyway. */
916 needs_clflush_after = cpu_write_needs_clflush(obj);
917 ret = i915_gem_object_wait_rendering(obj, false);
921 /* Same trick applies to invalidate partially written cachelines read
923 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
924 needs_clflush_before =
925 !cpu_cache_is_coherent(dev, obj->cache_level);
927 ret = i915_gem_object_get_pages(obj);
931 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
933 i915_gem_object_pin_pages(obj);
935 offset = args->offset;
938 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
939 offset >> PAGE_SHIFT) {
940 struct page *page = sg_page_iter_page(&sg_iter);
941 int partial_cacheline_write;
946 /* Operation in this page
948 * shmem_page_offset = offset within page in shmem file
949 * page_length = bytes to copy for this page
951 shmem_page_offset = offset_in_page(offset);
953 page_length = remain;
954 if ((shmem_page_offset + page_length) > PAGE_SIZE)
955 page_length = PAGE_SIZE - shmem_page_offset;
957 /* If we don't overwrite a cacheline completely we need to be
958 * careful to have up-to-date data by first clflushing. Don't
959 * overcomplicate things and flush the entire patch. */
960 partial_cacheline_write = needs_clflush_before &&
961 ((shmem_page_offset | page_length)
962 & (boot_cpu_data.x86_clflush_size - 1));
964 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
965 (page_to_phys(page) & (1 << 17)) != 0;
967 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
968 user_data, page_do_bit17_swizzling,
969 partial_cacheline_write,
970 needs_clflush_after);
975 mutex_unlock(&dev->struct_mutex);
976 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
977 user_data, page_do_bit17_swizzling,
978 partial_cacheline_write,
979 needs_clflush_after);
981 mutex_lock(&dev->struct_mutex);
987 remain -= page_length;
988 user_data += page_length;
989 offset += page_length;
993 i915_gem_object_unpin_pages(obj);
997 * Fixup: Flush cpu caches in case we didn't flush the dirty
998 * cachelines in-line while writing and the object moved
999 * out of the cpu write domain while we've dropped the lock.
1001 if (!needs_clflush_after &&
1002 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1003 if (i915_gem_clflush_object(obj, obj->pin_display))
1004 needs_clflush_after = true;
1008 if (needs_clflush_after)
1009 i915_gem_chipset_flush(dev);
1011 obj->cache_dirty = true;
1013 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1018 * Writes data to the object referenced by handle.
1020 * On error, the contents of the buffer that were to be modified are undefined.
1023 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1024 struct drm_file *file)
1026 struct drm_i915_private *dev_priv = dev->dev_private;
1027 struct drm_i915_gem_pwrite *args = data;
1028 struct drm_i915_gem_object *obj;
1031 if (args->size == 0)
1034 if (!access_ok(VERIFY_READ,
1035 to_user_ptr(args->data_ptr),
1039 if (likely(!i915.prefault_disable)) {
1040 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1046 intel_runtime_pm_get(dev_priv);
1048 ret = i915_mutex_lock_interruptible(dev);
1052 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1053 if (&obj->base == NULL) {
1058 /* Bounds check destination. */
1059 if (args->offset > obj->base.size ||
1060 args->size > obj->base.size - args->offset) {
1065 /* prime objects have no backing filp to GEM pread/pwrite
1068 if (!obj->base.filp) {
1073 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1076 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1077 * it would end up going through the fenced access, and we'll get
1078 * different detiling behavior between reading and writing.
1079 * pread/pwrite currently are reading and writing from the CPU
1080 * perspective, requiring manual detiling by the client.
1082 if (obj->tiling_mode == I915_TILING_NONE &&
1083 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1084 cpu_write_needs_clflush(obj)) {
1085 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1086 /* Note that the gtt paths might fail with non-page-backed user
1087 * pointers (e.g. gtt mappings when moving data between
1088 * textures). Fallback to the shmem path in that case. */
1091 if (ret == -EFAULT || ret == -ENOSPC) {
1092 if (obj->phys_handle)
1093 ret = i915_gem_phys_pwrite(obj, args, file);
1095 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1099 drm_gem_object_unreference(&obj->base);
1101 mutex_unlock(&dev->struct_mutex);
1103 intel_runtime_pm_put(dev_priv);
1109 i915_gem_check_wedge(unsigned reset_counter, bool interruptible)
1111 if (__i915_terminally_wedged(reset_counter))
1114 if (__i915_reset_in_progress(reset_counter)) {
1115 /* Non-interruptible callers can't handle -EAGAIN, hence return
1116 * -EIO unconditionally for these. */
1126 static void fake_irq(unsigned long data)
1128 wake_up_process((struct task_struct *)data);
1131 static bool missed_irq(struct drm_i915_private *dev_priv,
1132 struct intel_engine_cs *engine)
1134 return test_bit(engine->id, &dev_priv->gpu_error.missed_irq_rings);
1137 static unsigned long local_clock_us(unsigned *cpu)
1141 /* Cheaply and approximately convert from nanoseconds to microseconds.
1142 * The result and subsequent calculations are also defined in the same
1143 * approximate microseconds units. The principal source of timing
1144 * error here is from the simple truncation.
1146 * Note that local_clock() is only defined wrt to the current CPU;
1147 * the comparisons are no longer valid if we switch CPUs. Instead of
1148 * blocking preemption for the entire busywait, we can detect the CPU
1149 * switch and use that as indicator of system load and a reason to
1150 * stop busywaiting, see busywait_stop().
1153 t = local_clock() >> 10;
1159 static bool busywait_stop(unsigned long timeout, unsigned cpu)
1163 if (time_after(local_clock_us(&this_cpu), timeout))
1166 return this_cpu != cpu;
1169 static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
1171 unsigned long timeout;
1174 /* When waiting for high frequency requests, e.g. during synchronous
1175 * rendering split between the CPU and GPU, the finite amount of time
1176 * required to set up the irq and wait upon it limits the response
1177 * rate. By busywaiting on the request completion for a short while we
1178 * can service the high frequency waits as quick as possible. However,
1179 * if it is a slow request, we want to sleep as quickly as possible.
1180 * The tradeoff between waiting and sleeping is roughly the time it
1181 * takes to sleep on a request, on the order of a microsecond.
1184 if (req->engine->irq_refcount)
1187 /* Only spin if we know the GPU is processing this request */
1188 if (!i915_gem_request_started(req, true))
1191 timeout = local_clock_us(&cpu) + 5;
1192 while (!need_resched()) {
1193 if (i915_gem_request_completed(req, true))
1196 if (signal_pending_state(state, current))
1199 if (busywait_stop(timeout, cpu))
1202 cpu_relax_lowlatency();
1205 if (i915_gem_request_completed(req, false))
1212 * __i915_wait_request - wait until execution of request has finished
1214 * @interruptible: do an interruptible wait (normally yes)
1215 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1217 * Note: It is of utmost importance that the passed in seqno and reset_counter
1218 * values have been read by the caller in an smp safe manner. Where read-side
1219 * locks are involved, it is sufficient to read the reset_counter before
1220 * unlocking the lock that protects the seqno. For lockless tricks, the
1221 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1224 * Returns 0 if the request was found within the alloted time. Else returns the
1225 * errno with remaining time filled in timeout argument.
1227 int __i915_wait_request(struct drm_i915_gem_request *req,
1230 struct intel_rps_client *rps)
1232 struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
1233 struct drm_device *dev = engine->dev;
1234 struct drm_i915_private *dev_priv = dev->dev_private;
1235 const bool irq_test_in_progress =
1236 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine);
1237 int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1239 unsigned long timeout_expire;
1240 s64 before = 0; /* Only to silence a compiler warning. */
1243 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1245 if (list_empty(&req->list))
1248 if (i915_gem_request_completed(req, true))
1253 if (WARN_ON(*timeout < 0))
1259 timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout);
1262 * Record current time in case interrupted by signal, or wedged.
1264 before = ktime_get_raw_ns();
1267 if (INTEL_INFO(dev_priv)->gen >= 6)
1268 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);
1270 trace_i915_gem_request_wait_begin(req);
1272 /* Optimistic spin for the next jiffie before touching IRQs */
1273 ret = __i915_spin_request(req, state);
1277 if (!irq_test_in_progress && WARN_ON(!engine->irq_get(engine))) {
1283 struct timer_list timer;
1285 prepare_to_wait(&engine->irq_queue, &wait, state);
1287 /* We need to check whether any gpu reset happened in between
1288 * the request being submitted and now. If a reset has occurred,
1289 * the request is effectively complete (we either are in the
1290 * process of or have discarded the rendering and completely
1291 * reset the GPU. The results of the request are lost and we
1292 * are free to continue on with the original operation.
1294 if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) {
1299 if (i915_gem_request_completed(req, false)) {
1304 if (signal_pending_state(state, current)) {
1309 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1314 timer.function = NULL;
1315 if (timeout || missed_irq(dev_priv, engine)) {
1316 unsigned long expire;
1318 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1319 expire = missed_irq(dev_priv, engine) ? jiffies + 1 : timeout_expire;
1320 mod_timer(&timer, expire);
1325 if (timer.function) {
1326 del_singleshot_timer_sync(&timer);
1327 destroy_timer_on_stack(&timer);
1330 if (!irq_test_in_progress)
1331 engine->irq_put(engine);
1333 finish_wait(&engine->irq_queue, &wait);
1336 trace_i915_gem_request_wait_end(req);
1339 s64 tres = *timeout - (ktime_get_raw_ns() - before);
1341 *timeout = tres < 0 ? 0 : tres;
1344 * Apparently ktime isn't accurate enough and occasionally has a
1345 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1346 * things up to make the test happy. We allow up to 1 jiffy.
1348 * This is a regrssion from the timespec->ktime conversion.
1350 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1357 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
1358 struct drm_file *file)
1360 struct drm_i915_file_private *file_priv;
1362 WARN_ON(!req || !file || req->file_priv);
1370 file_priv = file->driver_priv;
1372 spin_lock(&file_priv->mm.lock);
1373 req->file_priv = file_priv;
1374 list_add_tail(&req->client_list, &file_priv->mm.request_list);
1375 spin_unlock(&file_priv->mm.lock);
1377 req->pid = get_pid(task_pid(current));
1383 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1385 struct drm_i915_file_private *file_priv = request->file_priv;
1390 spin_lock(&file_priv->mm.lock);
1391 list_del(&request->client_list);
1392 request->file_priv = NULL;
1393 spin_unlock(&file_priv->mm.lock);
1395 put_pid(request->pid);
1396 request->pid = NULL;
1399 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
1401 trace_i915_gem_request_retire(request);
1403 /* We know the GPU must have read the request to have
1404 * sent us the seqno + interrupt, so use the position
1405 * of tail of the request to update the last known position
1408 * Note this requires that we are always called in request
1411 request->ringbuf->last_retired_head = request->postfix;
1413 list_del_init(&request->list);
1414 i915_gem_request_remove_from_client(request);
1416 if (request->previous_context) {
1417 if (i915.enable_execlists)
1418 intel_lr_context_unpin(request->previous_context,
1422 i915_gem_context_unreference(request->ctx);
1423 i915_gem_request_unreference(request);
1427 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
1429 struct intel_engine_cs *engine = req->engine;
1430 struct drm_i915_gem_request *tmp;
1432 lockdep_assert_held(&engine->dev->struct_mutex);
1434 if (list_empty(&req->list))
1438 tmp = list_first_entry(&engine->request_list,
1439 typeof(*tmp), list);
1441 i915_gem_request_retire(tmp);
1442 } while (tmp != req);
1444 WARN_ON(i915_verify_lists(engine->dev));
1448 * Waits for a request to be signaled, and cleans up the
1449 * request and object lists appropriately for that event.
1452 i915_wait_request(struct drm_i915_gem_request *req)
1454 struct drm_i915_private *dev_priv = req->i915;
1458 interruptible = dev_priv->mm.interruptible;
1460 BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
1462 ret = __i915_wait_request(req, interruptible, NULL, NULL);
1466 __i915_gem_request_retire__upto(req);
1471 * Ensures that all rendering to the object has completed and the object is
1472 * safe to unbind from the GTT or access from the CPU.
1475 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1484 if (obj->last_write_req != NULL) {
1485 ret = i915_wait_request(obj->last_write_req);
1489 i = obj->last_write_req->engine->id;
1490 if (obj->last_read_req[i] == obj->last_write_req)
1491 i915_gem_object_retire__read(obj, i);
1493 i915_gem_object_retire__write(obj);
1496 for (i = 0; i < I915_NUM_ENGINES; i++) {
1497 if (obj->last_read_req[i] == NULL)
1500 ret = i915_wait_request(obj->last_read_req[i]);
1504 i915_gem_object_retire__read(obj, i);
1506 GEM_BUG_ON(obj->active);
1513 i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
1514 struct drm_i915_gem_request *req)
1516 int ring = req->engine->id;
1518 if (obj->last_read_req[ring] == req)
1519 i915_gem_object_retire__read(obj, ring);
1520 else if (obj->last_write_req == req)
1521 i915_gem_object_retire__write(obj);
1523 __i915_gem_request_retire__upto(req);
1526 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1527 * as the object state may change during this call.
1529 static __must_check int
1530 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1531 struct intel_rps_client *rps,
1534 struct drm_device *dev = obj->base.dev;
1535 struct drm_i915_private *dev_priv = dev->dev_private;
1536 struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
1539 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1540 BUG_ON(!dev_priv->mm.interruptible);
1546 struct drm_i915_gem_request *req;
1548 req = obj->last_write_req;
1552 requests[n++] = i915_gem_request_reference(req);
1554 for (i = 0; i < I915_NUM_ENGINES; i++) {
1555 struct drm_i915_gem_request *req;
1557 req = obj->last_read_req[i];
1561 requests[n++] = i915_gem_request_reference(req);
1565 mutex_unlock(&dev->struct_mutex);
1567 for (i = 0; ret == 0 && i < n; i++)
1568 ret = __i915_wait_request(requests[i], true, NULL, rps);
1569 mutex_lock(&dev->struct_mutex);
1571 for (i = 0; i < n; i++) {
1573 i915_gem_object_retire_request(obj, requests[i]);
1574 i915_gem_request_unreference(requests[i]);
1580 static struct intel_rps_client *to_rps_client(struct drm_file *file)
1582 struct drm_i915_file_private *fpriv = file->driver_priv;
1587 * Called when user space prepares to use an object with the CPU, either
1588 * through the mmap ioctl's mapping or a GTT mapping.
1591 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1592 struct drm_file *file)
1594 struct drm_i915_gem_set_domain *args = data;
1595 struct drm_i915_gem_object *obj;
1596 uint32_t read_domains = args->read_domains;
1597 uint32_t write_domain = args->write_domain;
1600 /* Only handle setting domains to types used by the CPU. */
1601 if (write_domain & I915_GEM_GPU_DOMAINS)
1604 if (read_domains & I915_GEM_GPU_DOMAINS)
1607 /* Having something in the write domain implies it's in the read
1608 * domain, and only that read domain. Enforce that in the request.
1610 if (write_domain != 0 && read_domains != write_domain)
1613 ret = i915_mutex_lock_interruptible(dev);
1617 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1618 if (&obj->base == NULL) {
1623 /* Try to flush the object off the GPU without holding the lock.
1624 * We will repeat the flush holding the lock in the normal manner
1625 * to catch cases where we are gazumped.
1627 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1628 to_rps_client(file),
1633 if (read_domains & I915_GEM_DOMAIN_GTT)
1634 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1636 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1638 if (write_domain != 0)
1639 intel_fb_obj_invalidate(obj,
1640 write_domain == I915_GEM_DOMAIN_GTT ?
1641 ORIGIN_GTT : ORIGIN_CPU);
1644 drm_gem_object_unreference(&obj->base);
1646 mutex_unlock(&dev->struct_mutex);
1651 * Called when user space has done writes to this buffer
1654 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1655 struct drm_file *file)
1657 struct drm_i915_gem_sw_finish *args = data;
1658 struct drm_i915_gem_object *obj;
1661 ret = i915_mutex_lock_interruptible(dev);
1665 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1666 if (&obj->base == NULL) {
1671 /* Pinned buffers may be scanout, so flush the cache */
1672 if (obj->pin_display)
1673 i915_gem_object_flush_cpu_write_domain(obj);
1675 drm_gem_object_unreference(&obj->base);
1677 mutex_unlock(&dev->struct_mutex);
1682 * Maps the contents of an object, returning the address it is mapped
1685 * While the mapping holds a reference on the contents of the object, it doesn't
1686 * imply a ref on the object itself.
1690 * DRM driver writers who look a this function as an example for how to do GEM
1691 * mmap support, please don't implement mmap support like here. The modern way
1692 * to implement DRM mmap support is with an mmap offset ioctl (like
1693 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1694 * That way debug tooling like valgrind will understand what's going on, hiding
1695 * the mmap call in a driver private ioctl will break that. The i915 driver only
1696 * does cpu mmaps this way because we didn't know better.
1699 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1700 struct drm_file *file)
1702 struct drm_i915_gem_mmap *args = data;
1703 struct drm_gem_object *obj;
1706 if (args->flags & ~(I915_MMAP_WC))
1709 if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1712 obj = drm_gem_object_lookup(dev, file, args->handle);
1716 /* prime objects have no backing filp to GEM mmap
1720 drm_gem_object_unreference_unlocked(obj);
1724 addr = vm_mmap(obj->filp, 0, args->size,
1725 PROT_READ | PROT_WRITE, MAP_SHARED,
1727 if (args->flags & I915_MMAP_WC) {
1728 struct mm_struct *mm = current->mm;
1729 struct vm_area_struct *vma;
1731 down_write(&mm->mmap_sem);
1732 vma = find_vma(mm, addr);
1735 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1738 up_write(&mm->mmap_sem);
1740 drm_gem_object_unreference_unlocked(obj);
1741 if (IS_ERR((void *)addr))
1744 args->addr_ptr = (uint64_t) addr;
1750 * i915_gem_fault - fault a page into the GTT
1751 * @vma: VMA in question
1754 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1755 * from userspace. The fault handler takes care of binding the object to
1756 * the GTT (if needed), allocating and programming a fence register (again,
1757 * only if needed based on whether the old reg is still valid or the object
1758 * is tiled) and inserting a new PTE into the faulting process.
1760 * Note that the faulting process may involve evicting existing objects
1761 * from the GTT and/or fence registers to make room. So performance may
1762 * suffer if the GTT working set is large or there are few fence registers
1765 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1767 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1768 struct drm_device *dev = obj->base.dev;
1769 struct drm_i915_private *dev_priv = to_i915(dev);
1770 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1771 struct i915_ggtt_view view = i915_ggtt_view_normal;
1772 pgoff_t page_offset;
1775 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1777 intel_runtime_pm_get(dev_priv);
1779 /* We don't use vmf->pgoff since that has the fake offset */
1780 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1783 ret = i915_mutex_lock_interruptible(dev);
1787 trace_i915_gem_object_fault(obj, page_offset, true, write);
1789 /* Try to flush the object off the GPU first without holding the lock.
1790 * Upon reacquiring the lock, we will perform our sanity checks and then
1791 * repeat the flush holding the lock in the normal manner to catch cases
1792 * where we are gazumped.
1794 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1798 /* Access to snoopable pages through the GTT is incoherent. */
1799 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1804 /* Use a partial view if the object is bigger than the aperture. */
1805 if (obj->base.size >= ggtt->mappable_end &&
1806 obj->tiling_mode == I915_TILING_NONE) {
1807 static const unsigned int chunk_size = 256; // 1 MiB
1809 memset(&view, 0, sizeof(view));
1810 view.type = I915_GGTT_VIEW_PARTIAL;
1811 view.params.partial.offset = rounddown(page_offset, chunk_size);
1812 view.params.partial.size =
1815 (vma->vm_end - vma->vm_start)/PAGE_SIZE -
1816 view.params.partial.offset);
1819 /* Now pin it into the GTT if needed */
1820 ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
1824 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1828 ret = i915_gem_object_get_fence(obj);
1832 /* Finally, remap it using the new GTT offset */
1833 pfn = ggtt->mappable_base +
1834 i915_gem_obj_ggtt_offset_view(obj, &view);
1837 if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
1838 /* Overriding existing pages in partial view does not cause
1839 * us any trouble as TLBs are still valid because the fault
1840 * is due to userspace losing part of the mapping or never
1841 * having accessed it before (at this partials' range).
1843 unsigned long base = vma->vm_start +
1844 (view.params.partial.offset << PAGE_SHIFT);
1847 for (i = 0; i < view.params.partial.size; i++) {
1848 ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
1853 obj->fault_mappable = true;
1855 if (!obj->fault_mappable) {
1856 unsigned long size = min_t(unsigned long,
1857 vma->vm_end - vma->vm_start,
1861 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1862 ret = vm_insert_pfn(vma,
1863 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1869 obj->fault_mappable = true;
1871 ret = vm_insert_pfn(vma,
1872 (unsigned long)vmf->virtual_address,
1876 i915_gem_object_ggtt_unpin_view(obj, &view);
1878 mutex_unlock(&dev->struct_mutex);
1883 * We eat errors when the gpu is terminally wedged to avoid
1884 * userspace unduly crashing (gl has no provisions for mmaps to
1885 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1886 * and so needs to be reported.
1888 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1889 ret = VM_FAULT_SIGBUS;
1894 * EAGAIN means the gpu is hung and we'll wait for the error
1895 * handler to reset everything when re-faulting in
1896 * i915_mutex_lock_interruptible.
1903 * EBUSY is ok: this just means that another thread
1904 * already did the job.
1906 ret = VM_FAULT_NOPAGE;
1913 ret = VM_FAULT_SIGBUS;
1916 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1917 ret = VM_FAULT_SIGBUS;
1921 intel_runtime_pm_put(dev_priv);
1926 * i915_gem_release_mmap - remove physical page mappings
1927 * @obj: obj in question
1929 * Preserve the reservation of the mmapping with the DRM core code, but
1930 * relinquish ownership of the pages back to the system.
1932 * It is vital that we remove the page mapping if we have mapped a tiled
1933 * object through the GTT and then lose the fence register due to
1934 * resource pressure. Similarly if the object has been moved out of the
1935 * aperture, than pages mapped into userspace must be revoked. Removing the
1936 * mapping will then trigger a page fault on the next user access, allowing
1937 * fixup by i915_gem_fault().
1940 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1942 /* Serialisation between user GTT access and our code depends upon
1943 * revoking the CPU's PTE whilst the mutex is held. The next user
1944 * pagefault then has to wait until we release the mutex.
1946 lockdep_assert_held(&obj->base.dev->struct_mutex);
1948 if (!obj->fault_mappable)
1951 drm_vma_node_unmap(&obj->base.vma_node,
1952 obj->base.dev->anon_inode->i_mapping);
1954 /* Ensure that the CPU's PTE are revoked and there are not outstanding
1955 * memory transactions from userspace before we return. The TLB
1956 * flushing implied above by changing the PTE above *should* be
1957 * sufficient, an extra barrier here just provides us with a bit
1958 * of paranoid documentation about our requirement to serialise
1959 * memory writes before touching registers / GSM.
1963 obj->fault_mappable = false;
1967 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1969 struct drm_i915_gem_object *obj;
1971 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1972 i915_gem_release_mmap(obj);
1976 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1980 if (INTEL_INFO(dev)->gen >= 4 ||
1981 tiling_mode == I915_TILING_NONE)
1984 /* Previous chips need a power-of-two fence region when tiling */
1985 if (INTEL_INFO(dev)->gen == 3)
1986 gtt_size = 1024*1024;
1988 gtt_size = 512*1024;
1990 while (gtt_size < size)
1997 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1998 * @obj: object to check
2000 * Return the required GTT alignment for an object, taking into account
2001 * potential fence register mapping.
2004 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2005 int tiling_mode, bool fenced)
2008 * Minimum alignment is 4k (GTT page size), but might be greater
2009 * if a fence register is needed for the object.
2011 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
2012 tiling_mode == I915_TILING_NONE)
2016 * Previous chips need to be aligned to the size of the smallest
2017 * fence register that can contain the object.
2019 return i915_gem_get_gtt_size(dev, size, tiling_mode);
2022 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2024 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2027 if (drm_vma_node_has_offset(&obj->base.vma_node))
2030 dev_priv->mm.shrinker_no_lock_stealing = true;
2032 ret = drm_gem_create_mmap_offset(&obj->base);
2036 /* Badly fragmented mmap space? The only way we can recover
2037 * space is by destroying unwanted objects. We can't randomly release
2038 * mmap_offsets as userspace expects them to be persistent for the
2039 * lifetime of the objects. The closest we can is to release the
2040 * offsets on purgeable objects by truncating it and marking it purged,
2041 * which prevents userspace from ever using that object again.
2043 i915_gem_shrink(dev_priv,
2044 obj->base.size >> PAGE_SHIFT,
2046 I915_SHRINK_UNBOUND |
2047 I915_SHRINK_PURGEABLE);
2048 ret = drm_gem_create_mmap_offset(&obj->base);
2052 i915_gem_shrink_all(dev_priv);
2053 ret = drm_gem_create_mmap_offset(&obj->base);
2055 dev_priv->mm.shrinker_no_lock_stealing = false;
2060 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2062 drm_gem_free_mmap_offset(&obj->base);
2066 i915_gem_mmap_gtt(struct drm_file *file,
2067 struct drm_device *dev,
2071 struct drm_i915_gem_object *obj;
2074 ret = i915_mutex_lock_interruptible(dev);
2078 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
2079 if (&obj->base == NULL) {
2084 if (obj->madv != I915_MADV_WILLNEED) {
2085 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2090 ret = i915_gem_object_create_mmap_offset(obj);
2094 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2097 drm_gem_object_unreference(&obj->base);
2099 mutex_unlock(&dev->struct_mutex);
2104 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2106 * @data: GTT mapping ioctl data
2107 * @file: GEM object info
2109 * Simply returns the fake offset to userspace so it can mmap it.
2110 * The mmap call will end up in drm_gem_mmap(), which will set things
2111 * up so we can get faults in the handler above.
2113 * The fault handler will take care of binding the object into the GTT
2114 * (since it may have been evicted to make room for something), allocating
2115 * a fence register, and mapping the appropriate aperture address into
2119 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2120 struct drm_file *file)
2122 struct drm_i915_gem_mmap_gtt *args = data;
2124 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2127 /* Immediately discard the backing storage */
2129 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2131 i915_gem_object_free_mmap_offset(obj);
2133 if (obj->base.filp == NULL)
2136 /* Our goal here is to return as much of the memory as
2137 * is possible back to the system as we are called from OOM.
2138 * To do this we must instruct the shmfs to drop all of its
2139 * backing pages, *now*.
2141 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2142 obj->madv = __I915_MADV_PURGED;
2145 /* Try to discard unwanted pages */
2147 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2149 struct address_space *mapping;
2151 switch (obj->madv) {
2152 case I915_MADV_DONTNEED:
2153 i915_gem_object_truncate(obj);
2154 case __I915_MADV_PURGED:
2158 if (obj->base.filp == NULL)
2161 mapping = file_inode(obj->base.filp)->i_mapping,
2162 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2166 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2168 struct sg_page_iter sg_iter;
2171 BUG_ON(obj->madv == __I915_MADV_PURGED);
2173 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2175 /* In the event of a disaster, abandon all caches and
2176 * hope for the best.
2178 i915_gem_clflush_object(obj, true);
2179 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2182 i915_gem_gtt_finish_object(obj);
2184 if (i915_gem_object_needs_bit17_swizzle(obj))
2185 i915_gem_object_save_bit_17_swizzle(obj);
2187 if (obj->madv == I915_MADV_DONTNEED)
2190 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2191 struct page *page = sg_page_iter_page(&sg_iter);
2194 set_page_dirty(page);
2196 if (obj->madv == I915_MADV_WILLNEED)
2197 mark_page_accessed(page);
2203 sg_free_table(obj->pages);
2208 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2210 const struct drm_i915_gem_object_ops *ops = obj->ops;
2212 if (obj->pages == NULL)
2215 if (obj->pages_pin_count)
2218 BUG_ON(i915_gem_obj_bound_any(obj));
2220 /* ->put_pages might need to allocate memory for the bit17 swizzle
2221 * array, hence protect them from being reaped by removing them from gtt
2223 list_del(&obj->global_list);
2226 if (is_vmalloc_addr(obj->mapping))
2227 vunmap(obj->mapping);
2229 kunmap(kmap_to_page(obj->mapping));
2230 obj->mapping = NULL;
2233 ops->put_pages(obj);
2236 i915_gem_object_invalidate(obj);
2242 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2244 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2246 struct address_space *mapping;
2247 struct sg_table *st;
2248 struct scatterlist *sg;
2249 struct sg_page_iter sg_iter;
2251 unsigned long last_pfn = 0; /* suppress gcc warning */
2255 /* Assert that the object is not currently in any GPU domain. As it
2256 * wasn't in the GTT, there shouldn't be any way it could have been in
2259 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2260 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2262 st = kmalloc(sizeof(*st), GFP_KERNEL);
2266 page_count = obj->base.size / PAGE_SIZE;
2267 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2272 /* Get the list of pages out of our struct file. They'll be pinned
2273 * at this point until we release them.
2275 * Fail silently without starting the shrinker
2277 mapping = file_inode(obj->base.filp)->i_mapping;
2278 gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2279 gfp |= __GFP_NORETRY | __GFP_NOWARN;
2282 for (i = 0; i < page_count; i++) {
2283 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2285 i915_gem_shrink(dev_priv,
2288 I915_SHRINK_UNBOUND |
2289 I915_SHRINK_PURGEABLE);
2290 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2293 /* We've tried hard to allocate the memory by reaping
2294 * our own buffer, now let the real VM do its job and
2295 * go down in flames if truly OOM.
2297 i915_gem_shrink_all(dev_priv);
2298 page = shmem_read_mapping_page(mapping, i);
2300 ret = PTR_ERR(page);
2304 #ifdef CONFIG_SWIOTLB
2305 if (swiotlb_nr_tbl()) {
2307 sg_set_page(sg, page, PAGE_SIZE, 0);
2312 if (!i || page_to_pfn(page) != last_pfn + 1) {
2316 sg_set_page(sg, page, PAGE_SIZE, 0);
2318 sg->length += PAGE_SIZE;
2320 last_pfn = page_to_pfn(page);
2322 /* Check that the i965g/gm workaround works. */
2323 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2325 #ifdef CONFIG_SWIOTLB
2326 if (!swiotlb_nr_tbl())
2331 ret = i915_gem_gtt_prepare_object(obj);
2335 if (i915_gem_object_needs_bit17_swizzle(obj))
2336 i915_gem_object_do_bit_17_swizzle(obj);
2338 if (obj->tiling_mode != I915_TILING_NONE &&
2339 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2340 i915_gem_object_pin_pages(obj);
2346 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2347 put_page(sg_page_iter_page(&sg_iter));
2351 /* shmemfs first checks if there is enough memory to allocate the page
2352 * and reports ENOSPC should there be insufficient, along with the usual
2353 * ENOMEM for a genuine allocation failure.
2355 * We use ENOSPC in our driver to mean that we have run out of aperture
2356 * space and so want to translate the error from shmemfs back to our
2357 * usual understanding of ENOMEM.
2365 /* Ensure that the associated pages are gathered from the backing storage
2366 * and pinned into our object. i915_gem_object_get_pages() may be called
2367 * multiple times before they are released by a single call to
2368 * i915_gem_object_put_pages() - once the pages are no longer referenced
2369 * either as a result of memory pressure (reaping pages under the shrinker)
2370 * or as the object is itself released.
2373 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2375 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2376 const struct drm_i915_gem_object_ops *ops = obj->ops;
2382 if (obj->madv != I915_MADV_WILLNEED) {
2383 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2387 BUG_ON(obj->pages_pin_count);
2389 ret = ops->get_pages(obj);
2393 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2395 obj->get_page.sg = obj->pages->sgl;
2396 obj->get_page.last = 0;
2401 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj)
2405 lockdep_assert_held(&obj->base.dev->struct_mutex);
2407 ret = i915_gem_object_get_pages(obj);
2409 return ERR_PTR(ret);
2411 i915_gem_object_pin_pages(obj);
2413 if (obj->mapping == NULL) {
2414 struct page **pages;
2417 if (obj->base.size == PAGE_SIZE)
2418 obj->mapping = kmap(sg_page(obj->pages->sgl));
2420 pages = drm_malloc_gfp(obj->base.size >> PAGE_SHIFT,
2423 if (pages != NULL) {
2424 struct sg_page_iter sg_iter;
2428 for_each_sg_page(obj->pages->sgl, &sg_iter,
2429 obj->pages->nents, 0)
2430 pages[n++] = sg_page_iter_page(&sg_iter);
2432 obj->mapping = vmap(pages, n, 0, PAGE_KERNEL);
2433 drm_free_large(pages);
2435 if (obj->mapping == NULL) {
2436 i915_gem_object_unpin_pages(obj);
2437 return ERR_PTR(-ENOMEM);
2441 return obj->mapping;
2444 void i915_vma_move_to_active(struct i915_vma *vma,
2445 struct drm_i915_gem_request *req)
2447 struct drm_i915_gem_object *obj = vma->obj;
2448 struct intel_engine_cs *engine;
2450 engine = i915_gem_request_get_engine(req);
2452 /* Add a reference if we're newly entering the active list. */
2453 if (obj->active == 0)
2454 drm_gem_object_reference(&obj->base);
2455 obj->active |= intel_engine_flag(engine);
2457 list_move_tail(&obj->engine_list[engine->id], &engine->active_list);
2458 i915_gem_request_assign(&obj->last_read_req[engine->id], req);
2460 list_move_tail(&vma->vm_link, &vma->vm->active_list);
2464 i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
2466 GEM_BUG_ON(obj->last_write_req == NULL);
2467 GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine)));
2469 i915_gem_request_assign(&obj->last_write_req, NULL);
2470 intel_fb_obj_flush(obj, true, ORIGIN_CS);
2474 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
2476 struct i915_vma *vma;
2478 GEM_BUG_ON(obj->last_read_req[ring] == NULL);
2479 GEM_BUG_ON(!(obj->active & (1 << ring)));
2481 list_del_init(&obj->engine_list[ring]);
2482 i915_gem_request_assign(&obj->last_read_req[ring], NULL);
2484 if (obj->last_write_req && obj->last_write_req->engine->id == ring)
2485 i915_gem_object_retire__write(obj);
2487 obj->active &= ~(1 << ring);
2491 /* Bump our place on the bound list to keep it roughly in LRU order
2492 * so that we don't steal from recently used but inactive objects
2493 * (unless we are forced to ofc!)
2495 list_move_tail(&obj->global_list,
2496 &to_i915(obj->base.dev)->mm.bound_list);
2498 list_for_each_entry(vma, &obj->vma_list, obj_link) {
2499 if (!list_empty(&vma->vm_link))
2500 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
2503 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2504 drm_gem_object_unreference(&obj->base);
2508 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2510 struct drm_i915_private *dev_priv = dev->dev_private;
2511 struct intel_engine_cs *engine;
2514 /* Carefully retire all requests without writing to the rings */
2515 for_each_engine(engine, dev_priv) {
2516 ret = intel_engine_idle(engine);
2520 i915_gem_retire_requests(dev);
2522 /* Finally reset hw state */
2523 for_each_engine(engine, dev_priv)
2524 intel_ring_init_seqno(engine, seqno);
2529 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2531 struct drm_i915_private *dev_priv = dev->dev_private;
2537 /* HWS page needs to be set less than what we
2538 * will inject to ring
2540 ret = i915_gem_init_seqno(dev, seqno - 1);
2544 /* Carefully set the last_seqno value so that wrap
2545 * detection still works
2547 dev_priv->next_seqno = seqno;
2548 dev_priv->last_seqno = seqno - 1;
2549 if (dev_priv->last_seqno == 0)
2550 dev_priv->last_seqno--;
2556 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2558 struct drm_i915_private *dev_priv = dev->dev_private;
2560 /* reserve 0 for non-seqno */
2561 if (dev_priv->next_seqno == 0) {
2562 int ret = i915_gem_init_seqno(dev, 0);
2566 dev_priv->next_seqno = 1;
2569 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2574 * NB: This function is not allowed to fail. Doing so would mean the the
2575 * request is not being tracked for completion but the work itself is
2576 * going to happen on the hardware. This would be a Bad Thing(tm).
2578 void __i915_add_request(struct drm_i915_gem_request *request,
2579 struct drm_i915_gem_object *obj,
2582 struct intel_engine_cs *engine;
2583 struct drm_i915_private *dev_priv;
2584 struct intel_ringbuffer *ringbuf;
2589 if (WARN_ON(request == NULL))
2592 engine = request->engine;
2593 dev_priv = request->i915;
2594 ringbuf = request->ringbuf;
2597 * To ensure that this call will not fail, space for its emissions
2598 * should already have been reserved in the ring buffer. Let the ring
2599 * know that it is time to use that space up.
2601 request_start = intel_ring_get_tail(ringbuf);
2602 reserved_tail = request->reserved_space;
2603 request->reserved_space = 0;
2606 * Emit any outstanding flushes - execbuf can fail to emit the flush
2607 * after having emitted the batchbuffer command. Hence we need to fix
2608 * things up similar to emitting the lazy request. The difference here
2609 * is that the flush _must_ happen before the next request, no matter
2613 if (i915.enable_execlists)
2614 ret = logical_ring_flush_all_caches(request);
2616 ret = intel_ring_flush_all_caches(request);
2617 /* Not allowed to fail! */
2618 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
2621 trace_i915_gem_request_add(request);
2623 request->head = request_start;
2625 /* Whilst this request exists, batch_obj will be on the
2626 * active_list, and so will hold the active reference. Only when this
2627 * request is retired will the the batch_obj be moved onto the
2628 * inactive_list and lose its active reference. Hence we do not need
2629 * to explicitly hold another reference here.
2631 request->batch_obj = obj;
2633 /* Seal the request and mark it as pending execution. Note that
2634 * we may inspect this state, without holding any locks, during
2635 * hangcheck. Hence we apply the barrier to ensure that we do not
2636 * see a more recent value in the hws than we are tracking.
2638 request->emitted_jiffies = jiffies;
2639 request->previous_seqno = engine->last_submitted_seqno;
2640 smp_store_mb(engine->last_submitted_seqno, request->seqno);
2641 list_add_tail(&request->list, &engine->request_list);
2643 /* Record the position of the start of the request so that
2644 * should we detect the updated seqno part-way through the
2645 * GPU processing the request, we never over-estimate the
2646 * position of the head.
2648 request->postfix = intel_ring_get_tail(ringbuf);
2650 if (i915.enable_execlists)
2651 ret = engine->emit_request(request);
2653 ret = engine->add_request(request);
2655 request->tail = intel_ring_get_tail(ringbuf);
2657 /* Not allowed to fail! */
2658 WARN(ret, "emit|add_request failed: %d!\n", ret);
2660 i915_queue_hangcheck(engine->dev);
2662 queue_delayed_work(dev_priv->wq,
2663 &dev_priv->mm.retire_work,
2664 round_jiffies_up_relative(HZ));
2665 intel_mark_busy(dev_priv);
2667 /* Sanity check that the reserved size was large enough. */
2668 ret = intel_ring_get_tail(ringbuf) - request_start;
2670 ret += ringbuf->size;
2671 WARN_ONCE(ret > reserved_tail,
2672 "Not enough space reserved (%d bytes) "
2673 "for adding the request (%d bytes)\n",
2674 reserved_tail, ret);
2677 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2678 const struct intel_context *ctx)
2680 unsigned long elapsed;
2682 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2684 if (ctx->hang_stats.banned)
2687 if (ctx->hang_stats.ban_period_seconds &&
2688 elapsed <= ctx->hang_stats.ban_period_seconds) {
2689 if (!i915_gem_context_is_default(ctx)) {
2690 DRM_DEBUG("context hanging too fast, banning!\n");
2692 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2693 if (i915_stop_ring_allow_warn(dev_priv))
2694 DRM_ERROR("gpu hanging too fast, banning!\n");
2702 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2703 struct intel_context *ctx,
2706 struct i915_ctx_hang_stats *hs;
2711 hs = &ctx->hang_stats;
2714 hs->banned = i915_context_is_banned(dev_priv, ctx);
2716 hs->guilty_ts = get_seconds();
2718 hs->batch_pending++;
2722 void i915_gem_request_free(struct kref *req_ref)
2724 struct drm_i915_gem_request *req = container_of(req_ref,
2726 kmem_cache_free(req->i915->requests, req);
2730 __i915_gem_request_alloc(struct intel_engine_cs *engine,
2731 struct intel_context *ctx,
2732 struct drm_i915_gem_request **req_out)
2734 struct drm_i915_private *dev_priv = to_i915(engine->dev);
2735 unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error);
2736 struct drm_i915_gem_request *req;
2744 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2745 * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
2748 ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible);
2752 req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
2756 ret = i915_gem_get_seqno(engine->dev, &req->seqno);
2760 kref_init(&req->ref);
2761 req->i915 = dev_priv;
2762 req->engine = engine;
2763 req->reset_counter = reset_counter;
2765 i915_gem_context_reference(req->ctx);
2768 * Reserve space in the ring buffer for all the commands required to
2769 * eventually emit this request. This is to guarantee that the
2770 * i915_add_request() call can't fail. Note that the reserve may need
2771 * to be redone if the request is not actually submitted straight
2772 * away, e.g. because a GPU scheduler has deferred it.
2774 req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
2776 if (i915.enable_execlists)
2777 ret = intel_logical_ring_alloc_request_extras(req);
2779 ret = intel_ring_alloc_request_extras(req);
2787 i915_gem_context_unreference(ctx);
2789 kmem_cache_free(dev_priv->requests, req);
2794 * i915_gem_request_alloc - allocate a request structure
2796 * @engine: engine that we wish to issue the request on.
2797 * @ctx: context that the request will be associated with.
2798 * This can be NULL if the request is not directly related to
2799 * any specific user context, in which case this function will
2800 * choose an appropriate context to use.
2802 * Returns a pointer to the allocated request if successful,
2803 * or an error code if not.
2805 struct drm_i915_gem_request *
2806 i915_gem_request_alloc(struct intel_engine_cs *engine,
2807 struct intel_context *ctx)
2809 struct drm_i915_gem_request *req;
2813 ctx = to_i915(engine->dev)->kernel_context;
2814 err = __i915_gem_request_alloc(engine, ctx, &req);
2815 return err ? ERR_PTR(err) : req;
2818 struct drm_i915_gem_request *
2819 i915_gem_find_active_request(struct intel_engine_cs *engine)
2821 struct drm_i915_gem_request *request;
2823 list_for_each_entry(request, &engine->request_list, list) {
2824 if (i915_gem_request_completed(request, false))
2833 static void i915_gem_reset_engine_status(struct drm_i915_private *dev_priv,
2834 struct intel_engine_cs *engine)
2836 struct drm_i915_gem_request *request;
2839 request = i915_gem_find_active_request(engine);
2841 if (request == NULL)
2844 ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2846 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2848 list_for_each_entry_continue(request, &engine->request_list, list)
2849 i915_set_reset_status(dev_priv, request->ctx, false);
2852 static void i915_gem_reset_engine_cleanup(struct drm_i915_private *dev_priv,
2853 struct intel_engine_cs *engine)
2855 struct intel_ringbuffer *buffer;
2857 while (!list_empty(&engine->active_list)) {
2858 struct drm_i915_gem_object *obj;
2860 obj = list_first_entry(&engine->active_list,
2861 struct drm_i915_gem_object,
2862 engine_list[engine->id]);
2864 i915_gem_object_retire__read(obj, engine->id);
2868 * Clear the execlists queue up before freeing the requests, as those
2869 * are the ones that keep the context and ringbuffer backing objects
2873 if (i915.enable_execlists) {
2874 /* Ensure irq handler finishes or is cancelled. */
2875 tasklet_kill(&engine->irq_tasklet);
2877 intel_execlists_cancel_requests(engine);
2881 * We must free the requests after all the corresponding objects have
2882 * been moved off active lists. Which is the same order as the normal
2883 * retire_requests function does. This is important if object hold
2884 * implicit references on things like e.g. ppgtt address spaces through
2887 while (!list_empty(&engine->request_list)) {
2888 struct drm_i915_gem_request *request;
2890 request = list_first_entry(&engine->request_list,
2891 struct drm_i915_gem_request,
2894 i915_gem_request_retire(request);
2897 /* Having flushed all requests from all queues, we know that all
2898 * ringbuffers must now be empty. However, since we do not reclaim
2899 * all space when retiring the request (to prevent HEADs colliding
2900 * with rapid ringbuffer wraparound) the amount of available space
2901 * upon reset is less than when we start. Do one more pass over
2902 * all the ringbuffers to reset last_retired_head.
2904 list_for_each_entry(buffer, &engine->buffers, link) {
2905 buffer->last_retired_head = buffer->tail;
2906 intel_ring_update_space(buffer);
2909 intel_ring_init_seqno(engine, engine->last_submitted_seqno);
2912 void i915_gem_reset(struct drm_device *dev)
2914 struct drm_i915_private *dev_priv = dev->dev_private;
2915 struct intel_engine_cs *engine;
2918 * Before we free the objects from the requests, we need to inspect
2919 * them for finding the guilty party. As the requests only borrow
2920 * their reference to the objects, the inspection must be done first.
2922 for_each_engine(engine, dev_priv)
2923 i915_gem_reset_engine_status(dev_priv, engine);
2925 for_each_engine(engine, dev_priv)
2926 i915_gem_reset_engine_cleanup(dev_priv, engine);
2928 i915_gem_context_reset(dev);
2930 i915_gem_restore_fences(dev);
2932 WARN_ON(i915_verify_lists(dev));
2936 * This function clears the request list as sequence numbers are passed.
2939 i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
2941 WARN_ON(i915_verify_lists(engine->dev));
2943 /* Retire requests first as we use it above for the early return.
2944 * If we retire requests last, we may use a later seqno and so clear
2945 * the requests lists without clearing the active list, leading to
2948 while (!list_empty(&engine->request_list)) {
2949 struct drm_i915_gem_request *request;
2951 request = list_first_entry(&engine->request_list,
2952 struct drm_i915_gem_request,
2955 if (!i915_gem_request_completed(request, true))
2958 i915_gem_request_retire(request);
2961 /* Move any buffers on the active list that are no longer referenced
2962 * by the ringbuffer to the flushing/inactive lists as appropriate,
2963 * before we free the context associated with the requests.
2965 while (!list_empty(&engine->active_list)) {
2966 struct drm_i915_gem_object *obj;
2968 obj = list_first_entry(&engine->active_list,
2969 struct drm_i915_gem_object,
2970 engine_list[engine->id]);
2972 if (!list_empty(&obj->last_read_req[engine->id]->list))
2975 i915_gem_object_retire__read(obj, engine->id);
2978 if (unlikely(engine->trace_irq_req &&
2979 i915_gem_request_completed(engine->trace_irq_req, true))) {
2980 engine->irq_put(engine);
2981 i915_gem_request_assign(&engine->trace_irq_req, NULL);
2984 WARN_ON(i915_verify_lists(engine->dev));
2988 i915_gem_retire_requests(struct drm_device *dev)
2990 struct drm_i915_private *dev_priv = dev->dev_private;
2991 struct intel_engine_cs *engine;
2994 for_each_engine(engine, dev_priv) {
2995 i915_gem_retire_requests_ring(engine);
2996 idle &= list_empty(&engine->request_list);
2997 if (i915.enable_execlists) {
2998 spin_lock_bh(&engine->execlist_lock);
2999 idle &= list_empty(&engine->execlist_queue);
3000 spin_unlock_bh(&engine->execlist_lock);
3005 mod_delayed_work(dev_priv->wq,
3006 &dev_priv->mm.idle_work,
3007 msecs_to_jiffies(100));
3013 i915_gem_retire_work_handler(struct work_struct *work)
3015 struct drm_i915_private *dev_priv =
3016 container_of(work, typeof(*dev_priv), mm.retire_work.work);
3017 struct drm_device *dev = dev_priv->dev;
3020 /* Come back later if the device is busy... */
3022 if (mutex_trylock(&dev->struct_mutex)) {
3023 idle = i915_gem_retire_requests(dev);
3024 mutex_unlock(&dev->struct_mutex);
3027 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
3028 round_jiffies_up_relative(HZ));
3032 i915_gem_idle_work_handler(struct work_struct *work)
3034 struct drm_i915_private *dev_priv =
3035 container_of(work, typeof(*dev_priv), mm.idle_work.work);
3036 struct drm_device *dev = dev_priv->dev;
3037 struct intel_engine_cs *engine;
3039 for_each_engine(engine, dev_priv)
3040 if (!list_empty(&engine->request_list))
3043 /* we probably should sync with hangcheck here, using cancel_work_sync.
3044 * Also locking seems to be fubar here, engine->request_list is protected
3045 * by dev->struct_mutex. */
3047 intel_mark_idle(dev_priv);
3049 if (mutex_trylock(&dev->struct_mutex)) {
3050 for_each_engine(engine, dev_priv)
3051 i915_gem_batch_pool_fini(&engine->batch_pool);
3053 mutex_unlock(&dev->struct_mutex);
3058 * Ensures that an object will eventually get non-busy by flushing any required
3059 * write domains, emitting any outstanding lazy request and retiring and
3060 * completed requests.
3063 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
3070 for (i = 0; i < I915_NUM_ENGINES; i++) {
3071 struct drm_i915_gem_request *req;
3073 req = obj->last_read_req[i];
3077 if (list_empty(&req->list))
3080 if (i915_gem_request_completed(req, true)) {
3081 __i915_gem_request_retire__upto(req);
3083 i915_gem_object_retire__read(obj, i);
3091 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3092 * @DRM_IOCTL_ARGS: standard ioctl arguments
3094 * Returns 0 if successful, else an error is returned with the remaining time in
3095 * the timeout parameter.
3096 * -ETIME: object is still busy after timeout
3097 * -ERESTARTSYS: signal interrupted the wait
3098 * -ENONENT: object doesn't exist
3099 * Also possible, but rare:
3100 * -EAGAIN: GPU wedged
3102 * -ENODEV: Internal IRQ fail
3103 * -E?: The add request failed
3105 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3106 * non-zero timeout parameter the wait ioctl will wait for the given number of
3107 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3108 * without holding struct_mutex the object may become re-busied before this
3109 * function completes. A similar but shorter * race condition exists in the busy
3113 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3115 struct drm_i915_gem_wait *args = data;
3116 struct drm_i915_gem_object *obj;
3117 struct drm_i915_gem_request *req[I915_NUM_ENGINES];
3121 if (args->flags != 0)
3124 ret = i915_mutex_lock_interruptible(dev);
3128 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
3129 if (&obj->base == NULL) {
3130 mutex_unlock(&dev->struct_mutex);
3134 /* Need to make sure the object gets inactive eventually. */
3135 ret = i915_gem_object_flush_active(obj);
3142 /* Do this after OLR check to make sure we make forward progress polling
3143 * on this IOCTL with a timeout == 0 (like busy ioctl)
3145 if (args->timeout_ns == 0) {
3150 drm_gem_object_unreference(&obj->base);
3152 for (i = 0; i < I915_NUM_ENGINES; i++) {
3153 if (obj->last_read_req[i] == NULL)
3156 req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
3159 mutex_unlock(&dev->struct_mutex);
3161 for (i = 0; i < n; i++) {
3163 ret = __i915_wait_request(req[i], true,
3164 args->timeout_ns > 0 ? &args->timeout_ns : NULL,
3165 to_rps_client(file));
3166 i915_gem_request_unreference(req[i]);
3171 drm_gem_object_unreference(&obj->base);
3172 mutex_unlock(&dev->struct_mutex);
3177 __i915_gem_object_sync(struct drm_i915_gem_object *obj,
3178 struct intel_engine_cs *to,
3179 struct drm_i915_gem_request *from_req,
3180 struct drm_i915_gem_request **to_req)
3182 struct intel_engine_cs *from;
3185 from = i915_gem_request_get_engine(from_req);
3189 if (i915_gem_request_completed(from_req, true))
3192 if (!i915_semaphore_is_enabled(obj->base.dev)) {
3193 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3194 ret = __i915_wait_request(from_req,
3195 i915->mm.interruptible,
3197 &i915->rps.semaphores);
3201 i915_gem_object_retire_request(obj, from_req);
3203 int idx = intel_ring_sync_index(from, to);
3204 u32 seqno = i915_gem_request_get_seqno(from_req);
3208 if (seqno <= from->semaphore.sync_seqno[idx])
3211 if (*to_req == NULL) {
3212 struct drm_i915_gem_request *req;
3214 req = i915_gem_request_alloc(to, NULL);
3216 return PTR_ERR(req);
3221 trace_i915_gem_ring_sync_to(*to_req, from, from_req);
3222 ret = to->semaphore.sync_to(*to_req, from, seqno);
3226 /* We use last_read_req because sync_to()
3227 * might have just caused seqno wrap under
3230 from->semaphore.sync_seqno[idx] =
3231 i915_gem_request_get_seqno(obj->last_read_req[from->id]);
3238 * i915_gem_object_sync - sync an object to a ring.
3240 * @obj: object which may be in use on another ring.
3241 * @to: ring we wish to use the object on. May be NULL.
3242 * @to_req: request we wish to use the object for. See below.
3243 * This will be allocated and returned if a request is
3244 * required but not passed in.
3246 * This code is meant to abstract object synchronization with the GPU.
3247 * Calling with NULL implies synchronizing the object with the CPU
3248 * rather than a particular GPU ring. Conceptually we serialise writes
3249 * between engines inside the GPU. We only allow one engine to write
3250 * into a buffer at any time, but multiple readers. To ensure each has
3251 * a coherent view of memory, we must:
3253 * - If there is an outstanding write request to the object, the new
3254 * request must wait for it to complete (either CPU or in hw, requests
3255 * on the same ring will be naturally ordered).
3257 * - If we are a write request (pending_write_domain is set), the new
3258 * request must wait for outstanding read requests to complete.
3260 * For CPU synchronisation (NULL to) no request is required. For syncing with
3261 * rings to_req must be non-NULL. However, a request does not have to be
3262 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3263 * request will be allocated automatically and returned through *to_req. Note
3264 * that it is not guaranteed that commands will be emitted (because the system
3265 * might already be idle). Hence there is no need to create a request that
3266 * might never have any work submitted. Note further that if a request is
3267 * returned in *to_req, it is the responsibility of the caller to submit
3268 * that request (after potentially adding more work to it).
3270 * Returns 0 if successful, else propagates up the lower layer error.
3273 i915_gem_object_sync(struct drm_i915_gem_object *obj,
3274 struct intel_engine_cs *to,
3275 struct drm_i915_gem_request **to_req)
3277 const bool readonly = obj->base.pending_write_domain == 0;
3278 struct drm_i915_gem_request *req[I915_NUM_ENGINES];
3285 return i915_gem_object_wait_rendering(obj, readonly);
3289 if (obj->last_write_req)
3290 req[n++] = obj->last_write_req;
3292 for (i = 0; i < I915_NUM_ENGINES; i++)
3293 if (obj->last_read_req[i])
3294 req[n++] = obj->last_read_req[i];
3296 for (i = 0; i < n; i++) {
3297 ret = __i915_gem_object_sync(obj, to, req[i], to_req);
3305 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3307 u32 old_write_domain, old_read_domains;
3309 /* Force a pagefault for domain tracking on next user access */
3310 i915_gem_release_mmap(obj);
3312 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3315 old_read_domains = obj->base.read_domains;
3316 old_write_domain = obj->base.write_domain;
3318 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3319 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3321 trace_i915_gem_object_change_domain(obj,
3326 static void __i915_vma_iounmap(struct i915_vma *vma)
3328 GEM_BUG_ON(vma->pin_count);
3330 if (vma->iomap == NULL)
3333 io_mapping_unmap(vma->iomap);
3337 static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
3339 struct drm_i915_gem_object *obj = vma->obj;
3340 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3343 if (list_empty(&vma->obj_link))
3346 if (!drm_mm_node_allocated(&vma->node)) {
3347 i915_gem_vma_destroy(vma);
3354 BUG_ON(obj->pages == NULL);
3357 ret = i915_gem_object_wait_rendering(obj, false);
3362 if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3363 i915_gem_object_finish_gtt(obj);
3365 /* release the fence reg _after_ flushing */
3366 ret = i915_gem_object_put_fence(obj);
3370 __i915_vma_iounmap(vma);
3373 trace_i915_vma_unbind(vma);
3375 vma->vm->unbind_vma(vma);
3378 list_del_init(&vma->vm_link);
3380 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3381 obj->map_and_fenceable = false;
3382 } else if (vma->ggtt_view.pages) {
3383 sg_free_table(vma->ggtt_view.pages);
3384 kfree(vma->ggtt_view.pages);
3386 vma->ggtt_view.pages = NULL;
3389 drm_mm_remove_node(&vma->node);
3390 i915_gem_vma_destroy(vma);
3392 /* Since the unbound list is global, only move to that list if
3393 * no more VMAs exist. */
3394 if (list_empty(&obj->vma_list))
3395 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3397 /* And finally now the object is completely decoupled from this vma,
3398 * we can drop its hold on the backing storage and allow it to be
3399 * reaped by the shrinker.
3401 i915_gem_object_unpin_pages(obj);
3406 int i915_vma_unbind(struct i915_vma *vma)
3408 return __i915_vma_unbind(vma, true);
3411 int __i915_vma_unbind_no_wait(struct i915_vma *vma)
3413 return __i915_vma_unbind(vma, false);
3416 int i915_gpu_idle(struct drm_device *dev)
3418 struct drm_i915_private *dev_priv = dev->dev_private;
3419 struct intel_engine_cs *engine;
3422 /* Flush everything onto the inactive list. */
3423 for_each_engine(engine, dev_priv) {
3424 if (!i915.enable_execlists) {
3425 struct drm_i915_gem_request *req;
3427 req = i915_gem_request_alloc(engine, NULL);
3429 return PTR_ERR(req);
3431 ret = i915_switch_context(req);
3432 i915_add_request_no_flush(req);
3437 ret = intel_engine_idle(engine);
3442 WARN_ON(i915_verify_lists(dev));
3446 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3447 unsigned long cache_level)
3449 struct drm_mm_node *gtt_space = &vma->node;
3450 struct drm_mm_node *other;
3453 * On some machines we have to be careful when putting differing types
3454 * of snoopable memory together to avoid the prefetcher crossing memory
3455 * domains and dying. During vm initialisation, we decide whether or not
3456 * these constraints apply and set the drm_mm.color_adjust
3459 if (vma->vm->mm.color_adjust == NULL)
3462 if (!drm_mm_node_allocated(gtt_space))
3465 if (list_empty(>t_space->node_list))
3468 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3469 if (other->allocated && !other->hole_follows && other->color != cache_level)
3472 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3473 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3480 * Finds free space in the GTT aperture and binds the object or a view of it
3483 static struct i915_vma *
3484 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3485 struct i915_address_space *vm,
3486 const struct i915_ggtt_view *ggtt_view,
3490 struct drm_device *dev = obj->base.dev;
3491 struct drm_i915_private *dev_priv = to_i915(dev);
3492 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3493 u32 fence_alignment, unfenced_alignment;
3494 u32 search_flag, alloc_flag;
3496 u64 size, fence_size;
3497 struct i915_vma *vma;
3500 if (i915_is_ggtt(vm)) {
3503 if (WARN_ON(!ggtt_view))
3504 return ERR_PTR(-EINVAL);
3506 view_size = i915_ggtt_view_size(obj, ggtt_view);
3508 fence_size = i915_gem_get_gtt_size(dev,
3511 fence_alignment = i915_gem_get_gtt_alignment(dev,
3515 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3519 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3521 fence_size = i915_gem_get_gtt_size(dev,
3524 fence_alignment = i915_gem_get_gtt_alignment(dev,
3528 unfenced_alignment =
3529 i915_gem_get_gtt_alignment(dev,
3533 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3536 start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3538 if (flags & PIN_MAPPABLE)
3539 end = min_t(u64, end, ggtt->mappable_end);
3540 if (flags & PIN_ZONE_4G)
3541 end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE);
3544 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3546 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3547 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3548 ggtt_view ? ggtt_view->type : 0,
3550 return ERR_PTR(-EINVAL);
3553 /* If binding the object/GGTT view requires more space than the entire
3554 * aperture has, reject it early before evicting everything in a vain
3555 * attempt to find space.
3558 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3559 ggtt_view ? ggtt_view->type : 0,
3561 flags & PIN_MAPPABLE ? "mappable" : "total",
3563 return ERR_PTR(-E2BIG);
3566 ret = i915_gem_object_get_pages(obj);
3568 return ERR_PTR(ret);
3570 i915_gem_object_pin_pages(obj);
3572 vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3573 i915_gem_obj_lookup_or_create_vma(obj, vm);
3578 if (flags & PIN_OFFSET_FIXED) {
3579 uint64_t offset = flags & PIN_OFFSET_MASK;
3581 if (offset & (alignment - 1) || offset + size > end) {
3585 vma->node.start = offset;
3586 vma->node.size = size;
3587 vma->node.color = obj->cache_level;
3588 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3590 ret = i915_gem_evict_for_vma(vma);
3592 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3597 if (flags & PIN_HIGH) {
3598 search_flag = DRM_MM_SEARCH_BELOW;
3599 alloc_flag = DRM_MM_CREATE_TOP;
3601 search_flag = DRM_MM_SEARCH_DEFAULT;
3602 alloc_flag = DRM_MM_CREATE_DEFAULT;
3606 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3613 ret = i915_gem_evict_something(dev, vm, size, alignment,
3623 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3625 goto err_remove_node;
3628 trace_i915_vma_bind(vma, flags);
3629 ret = i915_vma_bind(vma, obj->cache_level, flags);
3631 goto err_remove_node;
3633 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3634 list_add_tail(&vma->vm_link, &vm->inactive_list);
3639 drm_mm_remove_node(&vma->node);
3641 i915_gem_vma_destroy(vma);
3644 i915_gem_object_unpin_pages(obj);
3649 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3652 /* If we don't have a page list set up, then we're not pinned
3653 * to GPU, and we can ignore the cache flush because it'll happen
3654 * again at bind time.
3656 if (obj->pages == NULL)
3660 * Stolen memory is always coherent with the GPU as it is explicitly
3661 * marked as wc by the system, or the system is cache-coherent.
3663 if (obj->stolen || obj->phys_handle)
3666 /* If the GPU is snooping the contents of the CPU cache,
3667 * we do not need to manually clear the CPU cache lines. However,
3668 * the caches are only snooped when the render cache is
3669 * flushed/invalidated. As we always have to emit invalidations
3670 * and flushes when moving into and out of the RENDER domain, correct
3671 * snooping behaviour occurs naturally as the result of our domain
3674 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3675 obj->cache_dirty = true;
3679 trace_i915_gem_object_clflush(obj);
3680 drm_clflush_sg(obj->pages);
3681 obj->cache_dirty = false;
3686 /** Flushes the GTT write domain for the object if it's dirty. */
3688 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3690 uint32_t old_write_domain;
3692 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3695 /* No actual flushing is required for the GTT write domain. Writes
3696 * to it immediately go to main memory as far as we know, so there's
3697 * no chipset flush. It also doesn't land in render cache.
3699 * However, we do have to enforce the order so that all writes through
3700 * the GTT land before any writes to the device, such as updates to
3705 old_write_domain = obj->base.write_domain;
3706 obj->base.write_domain = 0;
3708 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
3710 trace_i915_gem_object_change_domain(obj,
3711 obj->base.read_domains,
3715 /** Flushes the CPU write domain for the object if it's dirty. */
3717 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3719 uint32_t old_write_domain;
3721 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3724 if (i915_gem_clflush_object(obj, obj->pin_display))
3725 i915_gem_chipset_flush(obj->base.dev);
3727 old_write_domain = obj->base.write_domain;
3728 obj->base.write_domain = 0;
3730 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3732 trace_i915_gem_object_change_domain(obj,
3733 obj->base.read_domains,
3738 * Moves a single object to the GTT read, and possibly write domain.
3740 * This function returns when the move is complete, including waiting on
3744 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3746 struct drm_device *dev = obj->base.dev;
3747 struct drm_i915_private *dev_priv = to_i915(dev);
3748 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3749 uint32_t old_write_domain, old_read_domains;
3750 struct i915_vma *vma;
3753 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3756 ret = i915_gem_object_wait_rendering(obj, !write);
3760 /* Flush and acquire obj->pages so that we are coherent through
3761 * direct access in memory with previous cached writes through
3762 * shmemfs and that our cache domain tracking remains valid.
3763 * For example, if the obj->filp was moved to swap without us
3764 * being notified and releasing the pages, we would mistakenly
3765 * continue to assume that the obj remained out of the CPU cached
3768 ret = i915_gem_object_get_pages(obj);
3772 i915_gem_object_flush_cpu_write_domain(obj);
3774 /* Serialise direct access to this object with the barriers for
3775 * coherent writes from the GPU, by effectively invalidating the
3776 * GTT domain upon first access.
3778 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3781 old_write_domain = obj->base.write_domain;
3782 old_read_domains = obj->base.read_domains;
3784 /* It should now be out of any other write domains, and we can update
3785 * the domain values for our changes.
3787 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3788 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3790 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3791 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3795 trace_i915_gem_object_change_domain(obj,
3799 /* And bump the LRU for this access */
3800 vma = i915_gem_obj_to_ggtt(obj);
3801 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3802 list_move_tail(&vma->vm_link,
3803 &ggtt->base.inactive_list);
3809 * Changes the cache-level of an object across all VMA.
3811 * After this function returns, the object will be in the new cache-level
3812 * across all GTT and the contents of the backing storage will be coherent,
3813 * with respect to the new cache-level. In order to keep the backing storage
3814 * coherent for all users, we only allow a single cache level to be set
3815 * globally on the object and prevent it from being changed whilst the
3816 * hardware is reading from the object. That is if the object is currently
3817 * on the scanout it will be set to uncached (or equivalent display
3818 * cache coherency) and all non-MOCS GPU access will also be uncached so
3819 * that all direct access to the scanout remains coherent.
3821 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3822 enum i915_cache_level cache_level)
3824 struct drm_device *dev = obj->base.dev;
3825 struct i915_vma *vma, *next;
3829 if (obj->cache_level == cache_level)
3832 /* Inspect the list of currently bound VMA and unbind any that would
3833 * be invalid given the new cache-level. This is principally to
3834 * catch the issue of the CS prefetch crossing page boundaries and
3835 * reading an invalid PTE on older architectures.
3837 list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
3838 if (!drm_mm_node_allocated(&vma->node))
3841 if (vma->pin_count) {
3842 DRM_DEBUG("can not change the cache level of pinned objects\n");
3846 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3847 ret = i915_vma_unbind(vma);
3854 /* We can reuse the existing drm_mm nodes but need to change the
3855 * cache-level on the PTE. We could simply unbind them all and
3856 * rebind with the correct cache-level on next use. However since
3857 * we already have a valid slot, dma mapping, pages etc, we may as
3858 * rewrite the PTE in the belief that doing so tramples upon less
3859 * state and so involves less work.
3862 /* Before we change the PTE, the GPU must not be accessing it.
3863 * If we wait upon the object, we know that all the bound
3864 * VMA are no longer active.
3866 ret = i915_gem_object_wait_rendering(obj, false);
3870 if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) {
3871 /* Access to snoopable pages through the GTT is
3872 * incoherent and on some machines causes a hard
3873 * lockup. Relinquish the CPU mmaping to force
3874 * userspace to refault in the pages and we can
3875 * then double check if the GTT mapping is still
3876 * valid for that pointer access.
3878 i915_gem_release_mmap(obj);
3880 /* As we no longer need a fence for GTT access,
3881 * we can relinquish it now (and so prevent having
3882 * to steal a fence from someone else on the next
3883 * fence request). Note GPU activity would have
3884 * dropped the fence as all snoopable access is
3885 * supposed to be linear.
3887 ret = i915_gem_object_put_fence(obj);
3891 /* We either have incoherent backing store and
3892 * so no GTT access or the architecture is fully
3893 * coherent. In such cases, existing GTT mmaps
3894 * ignore the cache bit in the PTE and we can
3895 * rewrite it without confusing the GPU or having
3896 * to force userspace to fault back in its mmaps.
3900 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3901 if (!drm_mm_node_allocated(&vma->node))
3904 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3910 list_for_each_entry(vma, &obj->vma_list, obj_link)
3911 vma->node.color = cache_level;
3912 obj->cache_level = cache_level;
3915 /* Flush the dirty CPU caches to the backing storage so that the
3916 * object is now coherent at its new cache level (with respect
3917 * to the access domain).
3919 if (obj->cache_dirty &&
3920 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3921 cpu_write_needs_clflush(obj)) {
3922 if (i915_gem_clflush_object(obj, true))
3923 i915_gem_chipset_flush(obj->base.dev);
3929 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3930 struct drm_file *file)
3932 struct drm_i915_gem_caching *args = data;
3933 struct drm_i915_gem_object *obj;
3935 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3936 if (&obj->base == NULL)
3939 switch (obj->cache_level) {
3940 case I915_CACHE_LLC:
3941 case I915_CACHE_L3_LLC:
3942 args->caching = I915_CACHING_CACHED;
3946 args->caching = I915_CACHING_DISPLAY;
3950 args->caching = I915_CACHING_NONE;
3954 drm_gem_object_unreference_unlocked(&obj->base);
3958 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3959 struct drm_file *file)
3961 struct drm_i915_private *dev_priv = dev->dev_private;
3962 struct drm_i915_gem_caching *args = data;
3963 struct drm_i915_gem_object *obj;
3964 enum i915_cache_level level;
3967 switch (args->caching) {
3968 case I915_CACHING_NONE:
3969 level = I915_CACHE_NONE;
3971 case I915_CACHING_CACHED:
3973 * Due to a HW issue on BXT A stepping, GPU stores via a
3974 * snooped mapping may leave stale data in a corresponding CPU
3975 * cacheline, whereas normally such cachelines would get
3978 if (!HAS_LLC(dev) && !HAS_SNOOP(dev))
3981 level = I915_CACHE_LLC;
3983 case I915_CACHING_DISPLAY:
3984 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3990 intel_runtime_pm_get(dev_priv);
3992 ret = i915_mutex_lock_interruptible(dev);
3996 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3997 if (&obj->base == NULL) {
4002 ret = i915_gem_object_set_cache_level(obj, level);
4004 drm_gem_object_unreference(&obj->base);
4006 mutex_unlock(&dev->struct_mutex);
4008 intel_runtime_pm_put(dev_priv);
4014 * Prepare buffer for display plane (scanout, cursors, etc).
4015 * Can be called from an uninterruptible phase (modesetting) and allows
4016 * any flushes to be pipelined (for pageflips).
4019 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
4021 const struct i915_ggtt_view *view)
4023 u32 old_read_domains, old_write_domain;
4026 /* Mark the pin_display early so that we account for the
4027 * display coherency whilst setting up the cache domains.
4031 /* The display engine is not coherent with the LLC cache on gen6. As
4032 * a result, we make sure that the pinning that is about to occur is
4033 * done with uncached PTEs. This is lowest common denominator for all
4036 * However for gen6+, we could do better by using the GFDT bit instead
4037 * of uncaching, which would allow us to flush all the LLC-cached data
4038 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4040 ret = i915_gem_object_set_cache_level(obj,
4041 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
4043 goto err_unpin_display;
4045 /* As the user may map the buffer once pinned in the display plane
4046 * (e.g. libkms for the bootup splash), we have to ensure that we
4047 * always use map_and_fenceable for all scanout buffers.
4049 ret = i915_gem_object_ggtt_pin(obj, view, alignment,
4050 view->type == I915_GGTT_VIEW_NORMAL ?
4053 goto err_unpin_display;
4055 i915_gem_object_flush_cpu_write_domain(obj);
4057 old_write_domain = obj->base.write_domain;
4058 old_read_domains = obj->base.read_domains;
4060 /* It should now be out of any other write domains, and we can update
4061 * the domain values for our changes.
4063 obj->base.write_domain = 0;
4064 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4066 trace_i915_gem_object_change_domain(obj,
4078 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
4079 const struct i915_ggtt_view *view)
4081 if (WARN_ON(obj->pin_display == 0))
4084 i915_gem_object_ggtt_unpin_view(obj, view);
4090 * Moves a single object to the CPU read, and possibly write domain.
4092 * This function returns when the move is complete, including waiting on
4096 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4098 uint32_t old_write_domain, old_read_domains;
4101 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4104 ret = i915_gem_object_wait_rendering(obj, !write);
4108 i915_gem_object_flush_gtt_write_domain(obj);
4110 old_write_domain = obj->base.write_domain;
4111 old_read_domains = obj->base.read_domains;
4113 /* Flush the CPU cache if it's still invalid. */
4114 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4115 i915_gem_clflush_object(obj, false);
4117 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4120 /* It should now be out of any other write domains, and we can update
4121 * the domain values for our changes.
4123 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4125 /* If we're writing through the CPU, then the GPU read domains will
4126 * need to be invalidated at next use.
4129 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4130 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4133 trace_i915_gem_object_change_domain(obj,
4140 /* Throttle our rendering by waiting until the ring has completed our requests
4141 * emitted over 20 msec ago.
4143 * Note that if we were to use the current jiffies each time around the loop,
4144 * we wouldn't escape the function with any frames outstanding if the time to
4145 * render a frame was over 20ms.
4147 * This should get us reasonable parallelism between CPU and GPU but also
4148 * relatively low latency when blocking on a particular request to finish.
4151 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4153 struct drm_i915_private *dev_priv = dev->dev_private;
4154 struct drm_i915_file_private *file_priv = file->driver_priv;
4155 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4156 struct drm_i915_gem_request *request, *target = NULL;
4159 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4163 /* ABI: return -EIO if already wedged */
4164 if (i915_terminally_wedged(&dev_priv->gpu_error))
4167 spin_lock(&file_priv->mm.lock);
4168 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4169 if (time_after_eq(request->emitted_jiffies, recent_enough))
4173 * Note that the request might not have been submitted yet.
4174 * In which case emitted_jiffies will be zero.
4176 if (!request->emitted_jiffies)
4182 i915_gem_request_reference(target);
4183 spin_unlock(&file_priv->mm.lock);
4188 ret = __i915_wait_request(target, true, NULL, NULL);
4190 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4192 i915_gem_request_unreference(target);
4198 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4200 struct drm_i915_gem_object *obj = vma->obj;
4203 vma->node.start & (alignment - 1))
4206 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4209 if (flags & PIN_OFFSET_BIAS &&
4210 vma->node.start < (flags & PIN_OFFSET_MASK))
4213 if (flags & PIN_OFFSET_FIXED &&
4214 vma->node.start != (flags & PIN_OFFSET_MASK))
4220 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
4222 struct drm_i915_gem_object *obj = vma->obj;
4223 bool mappable, fenceable;
4224 u32 fence_size, fence_alignment;
4226 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4229 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4234 fenceable = (vma->node.size == fence_size &&
4235 (vma->node.start & (fence_alignment - 1)) == 0);
4237 mappable = (vma->node.start + fence_size <=
4238 to_i915(obj->base.dev)->ggtt.mappable_end);
4240 obj->map_and_fenceable = mappable && fenceable;
4244 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4245 struct i915_address_space *vm,
4246 const struct i915_ggtt_view *ggtt_view,
4250 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4251 struct i915_vma *vma;
4255 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4258 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4261 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4264 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4267 vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4268 i915_gem_obj_to_vma(obj, vm);
4271 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4274 if (i915_vma_misplaced(vma, alignment, flags)) {
4275 WARN(vma->pin_count,
4276 "bo is already pinned in %s with incorrect alignment:"
4277 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4278 " obj->map_and_fenceable=%d\n",
4279 ggtt_view ? "ggtt" : "ppgtt",
4280 upper_32_bits(vma->node.start),
4281 lower_32_bits(vma->node.start),
4283 !!(flags & PIN_MAPPABLE),
4284 obj->map_and_fenceable);
4285 ret = i915_vma_unbind(vma);
4293 bound = vma ? vma->bound : 0;
4294 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4295 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4298 return PTR_ERR(vma);
4300 ret = i915_vma_bind(vma, obj->cache_level, flags);
4305 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4306 (bound ^ vma->bound) & GLOBAL_BIND) {
4307 __i915_vma_set_map_and_fenceable(vma);
4308 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4316 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4317 struct i915_address_space *vm,
4321 return i915_gem_object_do_pin(obj, vm,
4322 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4327 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4328 const struct i915_ggtt_view *view,
4332 struct drm_device *dev = obj->base.dev;
4333 struct drm_i915_private *dev_priv = to_i915(dev);
4334 struct i915_ggtt *ggtt = &dev_priv->ggtt;
4338 return i915_gem_object_do_pin(obj, &ggtt->base, view,
4339 alignment, flags | PIN_GLOBAL);
4343 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4344 const struct i915_ggtt_view *view)
4346 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4348 WARN_ON(vma->pin_count == 0);
4349 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4355 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4356 struct drm_file *file)
4358 struct drm_i915_gem_busy *args = data;
4359 struct drm_i915_gem_object *obj;
4362 ret = i915_mutex_lock_interruptible(dev);
4366 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4367 if (&obj->base == NULL) {
4372 /* Count all active objects as busy, even if they are currently not used
4373 * by the gpu. Users of this interface expect objects to eventually
4374 * become non-busy without any further actions, therefore emit any
4375 * necessary flushes here.
4377 ret = i915_gem_object_flush_active(obj);
4385 for (i = 0; i < I915_NUM_ENGINES; i++) {
4386 struct drm_i915_gem_request *req;
4388 req = obj->last_read_req[i];
4390 args->busy |= 1 << (16 + req->engine->exec_id);
4392 if (obj->last_write_req)
4393 args->busy |= obj->last_write_req->engine->exec_id;
4397 drm_gem_object_unreference(&obj->base);
4399 mutex_unlock(&dev->struct_mutex);
4404 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4405 struct drm_file *file_priv)
4407 return i915_gem_ring_throttle(dev, file_priv);
4411 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4412 struct drm_file *file_priv)
4414 struct drm_i915_private *dev_priv = dev->dev_private;
4415 struct drm_i915_gem_madvise *args = data;
4416 struct drm_i915_gem_object *obj;
4419 switch (args->madv) {
4420 case I915_MADV_DONTNEED:
4421 case I915_MADV_WILLNEED:
4427 ret = i915_mutex_lock_interruptible(dev);
4431 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4432 if (&obj->base == NULL) {
4437 if (i915_gem_obj_is_pinned(obj)) {
4443 obj->tiling_mode != I915_TILING_NONE &&
4444 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4445 if (obj->madv == I915_MADV_WILLNEED)
4446 i915_gem_object_unpin_pages(obj);
4447 if (args->madv == I915_MADV_WILLNEED)
4448 i915_gem_object_pin_pages(obj);
4451 if (obj->madv != __I915_MADV_PURGED)
4452 obj->madv = args->madv;
4454 /* if the object is no longer attached, discard its backing storage */
4455 if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4456 i915_gem_object_truncate(obj);
4458 args->retained = obj->madv != __I915_MADV_PURGED;
4461 drm_gem_object_unreference(&obj->base);
4463 mutex_unlock(&dev->struct_mutex);
4467 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4468 const struct drm_i915_gem_object_ops *ops)
4472 INIT_LIST_HEAD(&obj->global_list);
4473 for (i = 0; i < I915_NUM_ENGINES; i++)
4474 INIT_LIST_HEAD(&obj->engine_list[i]);
4475 INIT_LIST_HEAD(&obj->obj_exec_link);
4476 INIT_LIST_HEAD(&obj->vma_list);
4477 INIT_LIST_HEAD(&obj->batch_pool_link);
4481 obj->fence_reg = I915_FENCE_REG_NONE;
4482 obj->madv = I915_MADV_WILLNEED;
4484 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4487 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4488 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE,
4489 .get_pages = i915_gem_object_get_pages_gtt,
4490 .put_pages = i915_gem_object_put_pages_gtt,
4493 struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
4496 struct drm_i915_gem_object *obj;
4497 struct address_space *mapping;
4501 obj = i915_gem_object_alloc(dev);
4503 return ERR_PTR(-ENOMEM);
4505 ret = drm_gem_object_init(dev, &obj->base, size);
4509 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4510 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4511 /* 965gm cannot relocate objects above 4GiB. */
4512 mask &= ~__GFP_HIGHMEM;
4513 mask |= __GFP_DMA32;
4516 mapping = file_inode(obj->base.filp)->i_mapping;
4517 mapping_set_gfp_mask(mapping, mask);
4519 i915_gem_object_init(obj, &i915_gem_object_ops);
4521 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4522 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4525 /* On some devices, we can have the GPU use the LLC (the CPU
4526 * cache) for about a 10% performance improvement
4527 * compared to uncached. Graphics requests other than
4528 * display scanout are coherent with the CPU in
4529 * accessing this cache. This means in this mode we
4530 * don't need to clflush on the CPU side, and on the
4531 * GPU side we only need to flush internal caches to
4532 * get data visible to the CPU.
4534 * However, we maintain the display planes as UC, and so
4535 * need to rebind when first used as such.
4537 obj->cache_level = I915_CACHE_LLC;
4539 obj->cache_level = I915_CACHE_NONE;
4541 trace_i915_gem_object_create(obj);
4546 i915_gem_object_free(obj);
4548 return ERR_PTR(ret);
4551 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4553 /* If we are the last user of the backing storage (be it shmemfs
4554 * pages or stolen etc), we know that the pages are going to be
4555 * immediately released. In this case, we can then skip copying
4556 * back the contents from the GPU.
4559 if (obj->madv != I915_MADV_WILLNEED)
4562 if (obj->base.filp == NULL)
4565 /* At first glance, this looks racy, but then again so would be
4566 * userspace racing mmap against close. However, the first external
4567 * reference to the filp can only be obtained through the
4568 * i915_gem_mmap_ioctl() which safeguards us against the user
4569 * acquiring such a reference whilst we are in the middle of
4570 * freeing the object.
4572 return atomic_long_read(&obj->base.filp->f_count) == 1;
4575 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4577 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4578 struct drm_device *dev = obj->base.dev;
4579 struct drm_i915_private *dev_priv = dev->dev_private;
4580 struct i915_vma *vma, *next;
4582 intel_runtime_pm_get(dev_priv);
4584 trace_i915_gem_object_destroy(obj);
4586 list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
4590 ret = i915_vma_unbind(vma);
4591 if (WARN_ON(ret == -ERESTARTSYS)) {
4592 bool was_interruptible;
4594 was_interruptible = dev_priv->mm.interruptible;
4595 dev_priv->mm.interruptible = false;
4597 WARN_ON(i915_vma_unbind(vma));
4599 dev_priv->mm.interruptible = was_interruptible;
4603 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4604 * before progressing. */
4606 i915_gem_object_unpin_pages(obj);
4608 WARN_ON(obj->frontbuffer_bits);
4610 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4611 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4612 obj->tiling_mode != I915_TILING_NONE)
4613 i915_gem_object_unpin_pages(obj);
4615 if (WARN_ON(obj->pages_pin_count))
4616 obj->pages_pin_count = 0;
4617 if (discard_backing_storage(obj))
4618 obj->madv = I915_MADV_DONTNEED;
4619 i915_gem_object_put_pages(obj);
4620 i915_gem_object_free_mmap_offset(obj);
4624 if (obj->base.import_attach)
4625 drm_prime_gem_destroy(&obj->base, NULL);
4627 if (obj->ops->release)
4628 obj->ops->release(obj);
4630 drm_gem_object_release(&obj->base);
4631 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4634 i915_gem_object_free(obj);
4636 intel_runtime_pm_put(dev_priv);
4639 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4640 struct i915_address_space *vm)
4642 struct i915_vma *vma;
4643 list_for_each_entry(vma, &obj->vma_list, obj_link) {
4644 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL &&
4651 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4652 const struct i915_ggtt_view *view)
4654 struct i915_vma *vma;
4658 list_for_each_entry(vma, &obj->vma_list, obj_link)
4659 if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view))
4664 void i915_gem_vma_destroy(struct i915_vma *vma)
4666 WARN_ON(vma->node.allocated);
4668 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4669 if (!list_empty(&vma->exec_list))
4673 i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm));
4675 list_del(&vma->obj_link);
4677 kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4681 i915_gem_stop_engines(struct drm_device *dev)
4683 struct drm_i915_private *dev_priv = dev->dev_private;
4684 struct intel_engine_cs *engine;
4686 for_each_engine(engine, dev_priv)
4687 dev_priv->gt.stop_engine(engine);
4691 i915_gem_suspend(struct drm_device *dev)
4693 struct drm_i915_private *dev_priv = dev->dev_private;
4696 mutex_lock(&dev->struct_mutex);
4697 ret = i915_gpu_idle(dev);
4701 i915_gem_retire_requests(dev);
4703 i915_gem_stop_engines(dev);
4704 i915_gem_context_lost(dev_priv);
4705 mutex_unlock(&dev->struct_mutex);
4707 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4708 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4709 flush_delayed_work(&dev_priv->mm.idle_work);
4711 /* Assert that we sucessfully flushed all the work and
4712 * reset the GPU back to its idle, low power state.
4714 WARN_ON(dev_priv->mm.busy);
4719 mutex_unlock(&dev->struct_mutex);
4723 void i915_gem_init_swizzling(struct drm_device *dev)
4725 struct drm_i915_private *dev_priv = dev->dev_private;
4727 if (INTEL_INFO(dev)->gen < 5 ||
4728 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4731 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4732 DISP_TILE_SURFACE_SWIZZLING);
4737 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4739 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4740 else if (IS_GEN7(dev))
4741 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4742 else if (IS_GEN8(dev))
4743 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4748 static void init_unused_ring(struct drm_device *dev, u32 base)
4750 struct drm_i915_private *dev_priv = dev->dev_private;
4752 I915_WRITE(RING_CTL(base), 0);
4753 I915_WRITE(RING_HEAD(base), 0);
4754 I915_WRITE(RING_TAIL(base), 0);
4755 I915_WRITE(RING_START(base), 0);
4758 static void init_unused_rings(struct drm_device *dev)
4761 init_unused_ring(dev, PRB1_BASE);
4762 init_unused_ring(dev, SRB0_BASE);
4763 init_unused_ring(dev, SRB1_BASE);
4764 init_unused_ring(dev, SRB2_BASE);
4765 init_unused_ring(dev, SRB3_BASE);
4766 } else if (IS_GEN2(dev)) {
4767 init_unused_ring(dev, SRB0_BASE);
4768 init_unused_ring(dev, SRB1_BASE);
4769 } else if (IS_GEN3(dev)) {
4770 init_unused_ring(dev, PRB1_BASE);
4771 init_unused_ring(dev, PRB2_BASE);
4775 int i915_gem_init_engines(struct drm_device *dev)
4777 struct drm_i915_private *dev_priv = dev->dev_private;
4780 ret = intel_init_render_ring_buffer(dev);
4785 ret = intel_init_bsd_ring_buffer(dev);
4787 goto cleanup_render_ring;
4791 ret = intel_init_blt_ring_buffer(dev);
4793 goto cleanup_bsd_ring;
4796 if (HAS_VEBOX(dev)) {
4797 ret = intel_init_vebox_ring_buffer(dev);
4799 goto cleanup_blt_ring;
4802 if (HAS_BSD2(dev)) {
4803 ret = intel_init_bsd2_ring_buffer(dev);
4805 goto cleanup_vebox_ring;
4811 intel_cleanup_engine(&dev_priv->engine[VECS]);
4813 intel_cleanup_engine(&dev_priv->engine[BCS]);
4815 intel_cleanup_engine(&dev_priv->engine[VCS]);
4816 cleanup_render_ring:
4817 intel_cleanup_engine(&dev_priv->engine[RCS]);
4823 i915_gem_init_hw(struct drm_device *dev)
4825 struct drm_i915_private *dev_priv = dev->dev_private;
4826 struct intel_engine_cs *engine;
4829 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4832 /* Double layer security blanket, see i915_gem_init() */
4833 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4835 if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
4836 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4838 if (IS_HASWELL(dev))
4839 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4840 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4842 if (HAS_PCH_NOP(dev)) {
4843 if (IS_IVYBRIDGE(dev)) {
4844 u32 temp = I915_READ(GEN7_MSG_CTL);
4845 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4846 I915_WRITE(GEN7_MSG_CTL, temp);
4847 } else if (INTEL_INFO(dev)->gen >= 7) {
4848 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4849 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4850 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4854 i915_gem_init_swizzling(dev);
4857 * At least 830 can leave some of the unused rings
4858 * "active" (ie. head != tail) after resume which
4859 * will prevent c3 entry. Makes sure all unused rings
4862 init_unused_rings(dev);
4864 BUG_ON(!dev_priv->kernel_context);
4866 ret = i915_ppgtt_init_hw(dev);
4868 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4872 /* Need to do basic initialisation of all rings first: */
4873 for_each_engine(engine, dev_priv) {
4874 ret = engine->init_hw(engine);
4879 intel_mocs_init_l3cc_table(dev);
4881 /* We can't enable contexts until all firmware is loaded */
4882 if (HAS_GUC_UCODE(dev)) {
4883 ret = intel_guc_ucode_load(dev);
4885 DRM_ERROR("Failed to initialize GuC, error %d\n", ret);
4892 * Increment the next seqno by 0x100 so we have a visible break
4893 * on re-initialisation
4895 ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100);
4898 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4902 int i915_gem_init(struct drm_device *dev)
4904 struct drm_i915_private *dev_priv = dev->dev_private;
4907 mutex_lock(&dev->struct_mutex);
4909 if (!i915.enable_execlists) {
4910 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
4911 dev_priv->gt.init_engines = i915_gem_init_engines;
4912 dev_priv->gt.cleanup_engine = intel_cleanup_engine;
4913 dev_priv->gt.stop_engine = intel_stop_engine;
4915 dev_priv->gt.execbuf_submit = intel_execlists_submission;
4916 dev_priv->gt.init_engines = intel_logical_rings_init;
4917 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4918 dev_priv->gt.stop_engine = intel_logical_ring_stop;
4921 /* This is just a security blanket to placate dragons.
4922 * On some systems, we very sporadically observe that the first TLBs
4923 * used by the CS may be stale, despite us poking the TLB reset. If
4924 * we hold the forcewake during initialisation these problems
4925 * just magically go away.
4927 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4929 ret = i915_gem_init_userptr(dev);
4933 i915_gem_init_ggtt(dev);
4935 ret = i915_gem_context_init(dev);
4939 ret = dev_priv->gt.init_engines(dev);
4943 ret = i915_gem_init_hw(dev);
4945 /* Allow ring initialisation to fail by marking the GPU as
4946 * wedged. But we only want to do this where the GPU is angry,
4947 * for all other failure, such as an allocation failure, bail.
4949 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4950 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4955 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4956 mutex_unlock(&dev->struct_mutex);
4962 i915_gem_cleanup_engines(struct drm_device *dev)
4964 struct drm_i915_private *dev_priv = dev->dev_private;
4965 struct intel_engine_cs *engine;
4967 for_each_engine(engine, dev_priv)
4968 dev_priv->gt.cleanup_engine(engine);
4972 init_engine_lists(struct intel_engine_cs *engine)
4974 INIT_LIST_HEAD(&engine->active_list);
4975 INIT_LIST_HEAD(&engine->request_list);
4979 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
4981 struct drm_device *dev = dev_priv->dev;
4983 if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
4984 !IS_CHERRYVIEW(dev_priv))
4985 dev_priv->num_fence_regs = 32;
4986 else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
4987 IS_I945GM(dev_priv) || IS_G33(dev_priv))
4988 dev_priv->num_fence_regs = 16;
4990 dev_priv->num_fence_regs = 8;
4992 if (intel_vgpu_active(dev))
4993 dev_priv->num_fence_regs =
4994 I915_READ(vgtif_reg(avail_rs.fence_num));
4996 /* Initialize fence registers to zero */
4997 i915_gem_restore_fences(dev);
4999 i915_gem_detect_bit_6_swizzle(dev);
5003 i915_gem_load_init(struct drm_device *dev)
5005 struct drm_i915_private *dev_priv = dev->dev_private;
5009 kmem_cache_create("i915_gem_object",
5010 sizeof(struct drm_i915_gem_object), 0,
5014 kmem_cache_create("i915_gem_vma",
5015 sizeof(struct i915_vma), 0,
5018 dev_priv->requests =
5019 kmem_cache_create("i915_gem_request",
5020 sizeof(struct drm_i915_gem_request), 0,
5024 INIT_LIST_HEAD(&dev_priv->vm_list);
5025 INIT_LIST_HEAD(&dev_priv->context_list);
5026 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5027 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5028 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5029 for (i = 0; i < I915_NUM_ENGINES; i++)
5030 init_engine_lists(&dev_priv->engine[i]);
5031 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5032 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5033 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5034 i915_gem_retire_work_handler);
5035 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5036 i915_gem_idle_work_handler);
5037 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5039 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5042 * Set initial sequence number for requests.
5043 * Using this number allows the wraparound to happen early,
5044 * catching any obvious problems.
5046 dev_priv->next_seqno = ((u32)~0 - 0x1100);
5047 dev_priv->last_seqno = ((u32)~0 - 0x1101);
5049 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5051 init_waitqueue_head(&dev_priv->pending_flip_queue);
5053 dev_priv->mm.interruptible = true;
5055 mutex_init(&dev_priv->fb_tracking.lock);
5058 void i915_gem_load_cleanup(struct drm_device *dev)
5060 struct drm_i915_private *dev_priv = to_i915(dev);
5062 kmem_cache_destroy(dev_priv->requests);
5063 kmem_cache_destroy(dev_priv->vmas);
5064 kmem_cache_destroy(dev_priv->objects);
5067 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5069 struct drm_i915_file_private *file_priv = file->driver_priv;
5071 /* Clean up our request list when the client is going away, so that
5072 * later retire_requests won't dereference our soon-to-be-gone
5075 spin_lock(&file_priv->mm.lock);
5076 while (!list_empty(&file_priv->mm.request_list)) {
5077 struct drm_i915_gem_request *request;
5079 request = list_first_entry(&file_priv->mm.request_list,
5080 struct drm_i915_gem_request,
5082 list_del(&request->client_list);
5083 request->file_priv = NULL;
5085 spin_unlock(&file_priv->mm.lock);
5087 if (!list_empty(&file_priv->rps.link)) {
5088 spin_lock(&to_i915(dev)->rps.client_lock);
5089 list_del(&file_priv->rps.link);
5090 spin_unlock(&to_i915(dev)->rps.client_lock);
5094 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5096 struct drm_i915_file_private *file_priv;
5099 DRM_DEBUG_DRIVER("\n");
5101 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5105 file->driver_priv = file_priv;
5106 file_priv->dev_priv = dev->dev_private;
5107 file_priv->file = file;
5108 INIT_LIST_HEAD(&file_priv->rps.link);
5110 spin_lock_init(&file_priv->mm.lock);
5111 INIT_LIST_HEAD(&file_priv->mm.request_list);
5113 file_priv->bsd_ring = -1;
5115 ret = i915_gem_context_open(dev, file);
5123 * i915_gem_track_fb - update frontbuffer tracking
5124 * @old: current GEM buffer for the frontbuffer slots
5125 * @new: new GEM buffer for the frontbuffer slots
5126 * @frontbuffer_bits: bitmask of frontbuffer slots
5128 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5129 * from @old and setting them in @new. Both @old and @new can be NULL.
5131 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5132 struct drm_i915_gem_object *new,
5133 unsigned frontbuffer_bits)
5136 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5137 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5138 old->frontbuffer_bits &= ~frontbuffer_bits;
5142 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5143 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5144 new->frontbuffer_bits |= frontbuffer_bits;
5148 /* All the new VM stuff */
5149 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5150 struct i915_address_space *vm)
5152 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5153 struct i915_vma *vma;
5155 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5157 list_for_each_entry(vma, &o->vma_list, obj_link) {
5159 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5162 return vma->node.start;
5165 WARN(1, "%s vma for this object not found.\n",
5166 i915_is_ggtt(vm) ? "global" : "ppgtt");
5170 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5171 const struct i915_ggtt_view *view)
5173 struct i915_vma *vma;
5175 list_for_each_entry(vma, &o->vma_list, obj_link)
5176 if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view))
5177 return vma->node.start;
5179 WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5183 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5184 struct i915_address_space *vm)
5186 struct i915_vma *vma;
5188 list_for_each_entry(vma, &o->vma_list, obj_link) {
5190 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5192 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5199 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5200 const struct i915_ggtt_view *view)
5202 struct i915_vma *vma;
5204 list_for_each_entry(vma, &o->vma_list, obj_link)
5206 i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5207 drm_mm_node_allocated(&vma->node))
5213 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5215 struct i915_vma *vma;
5217 list_for_each_entry(vma, &o->vma_list, obj_link)
5218 if (drm_mm_node_allocated(&vma->node))
5224 unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o)
5226 struct i915_vma *vma;
5228 GEM_BUG_ON(list_empty(&o->vma_list));
5230 list_for_each_entry(vma, &o->vma_list, obj_link) {
5232 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
5233 return vma->node.size;
5239 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5241 struct i915_vma *vma;
5242 list_for_each_entry(vma, &obj->vma_list, obj_link)
5243 if (vma->pin_count > 0)
5249 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5251 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n)
5255 /* Only default objects have per-page dirty tracking */
5256 if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0))
5259 page = i915_gem_object_get_page(obj, n);
5260 set_page_dirty(page);
5264 /* Allocate a new GEM object and fill it with the supplied data */
5265 struct drm_i915_gem_object *
5266 i915_gem_object_create_from_data(struct drm_device *dev,
5267 const void *data, size_t size)
5269 struct drm_i915_gem_object *obj;
5270 struct sg_table *sg;
5274 obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE));
5278 ret = i915_gem_object_set_to_cpu_domain(obj, true);
5282 ret = i915_gem_object_get_pages(obj);
5286 i915_gem_object_pin_pages(obj);
5288 bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
5289 obj->dirty = 1; /* Backing store is now out of date */
5290 i915_gem_object_unpin_pages(obj);
5292 if (WARN_ON(bytes != size)) {
5293 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
5301 drm_gem_object_unreference(&obj->base);
5302 return ERR_PTR(ret);