2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
46 i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
48 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
49 static void i915_gem_write_fence(struct drm_device *dev, int reg,
50 struct drm_i915_gem_object *obj);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
52 struct drm_i915_fence_reg *fence,
55 static bool cpu_cache_is_coherent(struct drm_device *dev,
56 enum i915_cache_level level)
58 return HAS_LLC(dev) || level != I915_CACHE_NONE;
61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
63 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
66 return obj->pin_display;
69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
72 i915_gem_release_mmap(obj);
74 /* As we do not have an associated fence register, we will force
75 * a tiling change if we ever need to acquire one.
77 obj->fence_dirty = false;
78 obj->fence_reg = I915_FENCE_REG_NONE;
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
85 spin_lock(&dev_priv->mm.object_stat_lock);
86 dev_priv->mm.object_count++;
87 dev_priv->mm.object_memory += size;
88 spin_unlock(&dev_priv->mm.object_stat_lock);
91 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
94 spin_lock(&dev_priv->mm.object_stat_lock);
95 dev_priv->mm.object_count--;
96 dev_priv->mm.object_memory -= size;
97 spin_unlock(&dev_priv->mm.object_stat_lock);
101 i915_gem_wait_for_error(struct i915_gpu_error *error)
105 #define EXIT_COND (!i915_reset_in_progress(error) || \
106 i915_terminally_wedged(error))
111 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
112 * userspace. If it takes that long something really bad is going on and
113 * we should simply try to bail out and fail as gracefully as possible.
115 ret = wait_event_interruptible_timeout(error->reset_queue,
119 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
121 } else if (ret < 0) {
129 int i915_mutex_lock_interruptible(struct drm_device *dev)
131 struct drm_i915_private *dev_priv = dev->dev_private;
134 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
138 ret = mutex_lock_interruptible(&dev->struct_mutex);
142 WARN_ON(i915_verify_lists(dev));
147 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
148 struct drm_file *file)
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 struct drm_i915_gem_get_aperture *args = data;
152 struct drm_i915_gem_object *obj;
156 mutex_lock(&dev->struct_mutex);
157 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
158 if (i915_gem_obj_is_pinned(obj))
159 pinned += i915_gem_obj_ggtt_size(obj);
160 mutex_unlock(&dev->struct_mutex);
162 args->aper_size = dev_priv->gtt.base.total;
163 args->aper_available_size = args->aper_size - pinned;
169 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
171 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
172 char *vaddr = obj->phys_handle->vaddr;
174 struct scatterlist *sg;
177 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
180 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
184 page = shmem_read_mapping_page(mapping, i);
186 return PTR_ERR(page);
188 src = kmap_atomic(page);
189 memcpy(vaddr, src, PAGE_SIZE);
190 drm_clflush_virt_range(vaddr, PAGE_SIZE);
193 page_cache_release(page);
197 i915_gem_chipset_flush(obj->base.dev);
199 st = kmalloc(sizeof(*st), GFP_KERNEL);
203 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
210 sg->length = obj->base.size;
212 sg_dma_address(sg) = obj->phys_handle->busaddr;
213 sg_dma_len(sg) = obj->base.size;
216 obj->has_dma_mapping = true;
221 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
225 BUG_ON(obj->madv == __I915_MADV_PURGED);
227 ret = i915_gem_object_set_to_cpu_domain(obj, true);
229 /* In the event of a disaster, abandon all caches and
232 WARN_ON(ret != -EIO);
233 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
236 if (obj->madv == I915_MADV_DONTNEED)
240 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
241 char *vaddr = obj->phys_handle->vaddr;
244 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
248 page = shmem_read_mapping_page(mapping, i);
252 dst = kmap_atomic(page);
253 drm_clflush_virt_range(vaddr, PAGE_SIZE);
254 memcpy(dst, vaddr, PAGE_SIZE);
257 set_page_dirty(page);
258 if (obj->madv == I915_MADV_WILLNEED)
259 mark_page_accessed(page);
260 page_cache_release(page);
266 sg_free_table(obj->pages);
269 obj->has_dma_mapping = false;
273 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
275 drm_pci_free(obj->base.dev, obj->phys_handle);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
279 .get_pages = i915_gem_object_get_pages_phys,
280 .put_pages = i915_gem_object_put_pages_phys,
281 .release = i915_gem_object_release_phys,
285 drop_pages(struct drm_i915_gem_object *obj)
287 struct i915_vma *vma, *next;
290 drm_gem_object_reference(&obj->base);
291 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
292 if (i915_vma_unbind(vma))
295 ret = i915_gem_object_put_pages(obj);
296 drm_gem_object_unreference(&obj->base);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
305 drm_dma_handle_t *phys;
308 if (obj->phys_handle) {
309 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
315 if (obj->madv != I915_MADV_WILLNEED)
318 if (obj->base.filp == NULL)
321 ret = drop_pages(obj);
325 /* create a new object */
326 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
330 obj->phys_handle = phys;
331 obj->ops = &i915_gem_phys_ops;
333 return i915_gem_object_get_pages(obj);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
338 struct drm_i915_gem_pwrite *args,
339 struct drm_file *file_priv)
341 struct drm_device *dev = obj->base.dev;
342 void *vaddr = obj->phys_handle->vaddr + args->offset;
343 char __user *user_data = to_user_ptr(args->data_ptr);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret = i915_gem_object_wait_rendering(obj, false);
353 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
354 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
355 unsigned long unwritten;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev->struct_mutex);
362 unwritten = copy_from_user(vaddr, user_data, args->size);
363 mutex_lock(&dev->struct_mutex);
370 drm_clflush_virt_range(vaddr, args->size);
371 i915_gem_chipset_flush(dev);
374 intel_fb_obj_flush(obj, false);
378 void *i915_gem_object_alloc(struct drm_device *dev)
380 struct drm_i915_private *dev_priv = dev->dev_private;
381 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
384 void i915_gem_object_free(struct drm_i915_gem_object *obj)
386 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
387 kmem_cache_free(dev_priv->objects, obj);
391 i915_gem_create(struct drm_file *file,
392 struct drm_device *dev,
396 struct drm_i915_gem_object *obj;
400 size = roundup(size, PAGE_SIZE);
404 /* Allocate the new object */
405 obj = i915_gem_alloc_object(dev, size);
409 ret = drm_gem_handle_create(file, &obj->base, &handle);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj->base);
420 i915_gem_dumb_create(struct drm_file *file,
421 struct drm_device *dev,
422 struct drm_mode_create_dumb *args)
424 /* have to work out size/pitch and return them */
425 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
426 args->size = args->pitch * args->height;
427 return i915_gem_create(file, dev,
428 args->size, &args->handle);
432 * Creates a new mm object and returns a handle to it.
435 i915_gem_create_ioctl(struct drm_device *dev, void *data,
436 struct drm_file *file)
438 struct drm_i915_gem_create *args = data;
440 return i915_gem_create(file, dev,
441 args->size, &args->handle);
445 __copy_to_user_swizzled(char __user *cpu_vaddr,
446 const char *gpu_vaddr, int gpu_offset,
449 int ret, cpu_offset = 0;
452 int cacheline_end = ALIGN(gpu_offset + 1, 64);
453 int this_length = min(cacheline_end - gpu_offset, length);
454 int swizzled_gpu_offset = gpu_offset ^ 64;
456 ret = __copy_to_user(cpu_vaddr + cpu_offset,
457 gpu_vaddr + swizzled_gpu_offset,
462 cpu_offset += this_length;
463 gpu_offset += this_length;
464 length -= this_length;
471 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
472 const char __user *cpu_vaddr,
475 int ret, cpu_offset = 0;
478 int cacheline_end = ALIGN(gpu_offset + 1, 64);
479 int this_length = min(cacheline_end - gpu_offset, length);
480 int swizzled_gpu_offset = gpu_offset ^ 64;
482 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
483 cpu_vaddr + cpu_offset,
488 cpu_offset += this_length;
489 gpu_offset += this_length;
490 length -= this_length;
497 * Pins the specified object's pages and synchronizes the object with
498 * GPU accesses. Sets needs_clflush to non-zero if the caller should
499 * flush the object from the CPU cache.
501 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
511 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
512 /* If we're not in the cpu read domain, set ourself into the gtt
513 * read domain and manually flush cachelines (if required). This
514 * optimizes for the case when the gpu will dirty the data
515 * anyway again before the next pread happens. */
516 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
518 ret = i915_gem_object_wait_rendering(obj, true);
523 ret = i915_gem_object_get_pages(obj);
527 i915_gem_object_pin_pages(obj);
532 /* Per-page copy function for the shmem pread fastpath.
533 * Flushes invalid cachelines before reading the target if
534 * needs_clflush is set. */
536 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
537 char __user *user_data,
538 bool page_do_bit17_swizzling, bool needs_clflush)
543 if (unlikely(page_do_bit17_swizzling))
546 vaddr = kmap_atomic(page);
548 drm_clflush_virt_range(vaddr + shmem_page_offset,
550 ret = __copy_to_user_inatomic(user_data,
551 vaddr + shmem_page_offset,
553 kunmap_atomic(vaddr);
555 return ret ? -EFAULT : 0;
559 shmem_clflush_swizzled_range(char *addr, unsigned long length,
562 if (unlikely(swizzled)) {
563 unsigned long start = (unsigned long) addr;
564 unsigned long end = (unsigned long) addr + length;
566 /* For swizzling simply ensure that we always flush both
567 * channels. Lame, but simple and it works. Swizzled
568 * pwrite/pread is far from a hotpath - current userspace
569 * doesn't use it at all. */
570 start = round_down(start, 128);
571 end = round_up(end, 128);
573 drm_clflush_virt_range((void *)start, end - start);
575 drm_clflush_virt_range(addr, length);
580 /* Only difference to the fast-path function is that this can handle bit17
581 * and uses non-atomic copy and kmap functions. */
583 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
584 char __user *user_data,
585 bool page_do_bit17_swizzling, bool needs_clflush)
592 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
594 page_do_bit17_swizzling);
596 if (page_do_bit17_swizzling)
597 ret = __copy_to_user_swizzled(user_data,
598 vaddr, shmem_page_offset,
601 ret = __copy_to_user(user_data,
602 vaddr + shmem_page_offset,
606 return ret ? - EFAULT : 0;
610 i915_gem_shmem_pread(struct drm_device *dev,
611 struct drm_i915_gem_object *obj,
612 struct drm_i915_gem_pread *args,
613 struct drm_file *file)
615 char __user *user_data;
618 int shmem_page_offset, page_length, ret = 0;
619 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
621 int needs_clflush = 0;
622 struct sg_page_iter sg_iter;
624 user_data = to_user_ptr(args->data_ptr);
627 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
629 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
633 offset = args->offset;
635 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
636 offset >> PAGE_SHIFT) {
637 struct page *page = sg_page_iter_page(&sg_iter);
642 /* Operation in this page
644 * shmem_page_offset = offset within page in shmem file
645 * page_length = bytes to copy for this page
647 shmem_page_offset = offset_in_page(offset);
648 page_length = remain;
649 if ((shmem_page_offset + page_length) > PAGE_SIZE)
650 page_length = PAGE_SIZE - shmem_page_offset;
652 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
653 (page_to_phys(page) & (1 << 17)) != 0;
655 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
656 user_data, page_do_bit17_swizzling,
661 mutex_unlock(&dev->struct_mutex);
663 if (likely(!i915.prefault_disable) && !prefaulted) {
664 ret = fault_in_multipages_writeable(user_data, remain);
665 /* Userspace is tricking us, but we've already clobbered
666 * its pages with the prefault and promised to write the
667 * data up to the first fault. Hence ignore any errors
668 * and just continue. */
673 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
674 user_data, page_do_bit17_swizzling,
677 mutex_lock(&dev->struct_mutex);
683 remain -= page_length;
684 user_data += page_length;
685 offset += page_length;
689 i915_gem_object_unpin_pages(obj);
695 * Reads data from the object referenced by handle.
697 * On error, the contents of *data are undefined.
700 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
701 struct drm_file *file)
703 struct drm_i915_gem_pread *args = data;
704 struct drm_i915_gem_object *obj;
710 if (!access_ok(VERIFY_WRITE,
711 to_user_ptr(args->data_ptr),
715 ret = i915_mutex_lock_interruptible(dev);
719 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
720 if (&obj->base == NULL) {
725 /* Bounds check source. */
726 if (args->offset > obj->base.size ||
727 args->size > obj->base.size - args->offset) {
732 /* prime objects have no backing filp to GEM pread/pwrite
735 if (!obj->base.filp) {
740 trace_i915_gem_object_pread(obj, args->offset, args->size);
742 ret = i915_gem_shmem_pread(dev, obj, args, file);
745 drm_gem_object_unreference(&obj->base);
747 mutex_unlock(&dev->struct_mutex);
751 /* This is the fast write path which cannot handle
752 * page faults in the source data
756 fast_user_write(struct io_mapping *mapping,
757 loff_t page_base, int page_offset,
758 char __user *user_data,
761 void __iomem *vaddr_atomic;
763 unsigned long unwritten;
765 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
766 /* We can use the cpu mem copy function because this is X86. */
767 vaddr = (void __force*)vaddr_atomic + page_offset;
768 unwritten = __copy_from_user_inatomic_nocache(vaddr,
770 io_mapping_unmap_atomic(vaddr_atomic);
775 * This is the fast pwrite path, where we copy the data directly from the
776 * user into the GTT, uncached.
779 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
780 struct drm_i915_gem_object *obj,
781 struct drm_i915_gem_pwrite *args,
782 struct drm_file *file)
784 struct drm_i915_private *dev_priv = dev->dev_private;
786 loff_t offset, page_base;
787 char __user *user_data;
788 int page_offset, page_length, ret;
790 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
794 ret = i915_gem_object_set_to_gtt_domain(obj, true);
798 ret = i915_gem_object_put_fence(obj);
802 user_data = to_user_ptr(args->data_ptr);
805 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
807 intel_fb_obj_invalidate(obj, ORIGIN_GTT);
810 /* Operation in this page
812 * page_base = page offset within aperture
813 * page_offset = offset within page
814 * page_length = bytes to copy for this page
816 page_base = offset & PAGE_MASK;
817 page_offset = offset_in_page(offset);
818 page_length = remain;
819 if ((page_offset + remain) > PAGE_SIZE)
820 page_length = PAGE_SIZE - page_offset;
822 /* If we get a fault while copying data, then (presumably) our
823 * source page isn't available. Return the error and we'll
824 * retry in the slow path.
826 if (fast_user_write(dev_priv->gtt.mappable, page_base,
827 page_offset, user_data, page_length)) {
832 remain -= page_length;
833 user_data += page_length;
834 offset += page_length;
838 intel_fb_obj_flush(obj, false);
840 i915_gem_object_ggtt_unpin(obj);
845 /* Per-page copy function for the shmem pwrite fastpath.
846 * Flushes invalid cachelines before writing to the target if
847 * needs_clflush_before is set and flushes out any written cachelines after
848 * writing if needs_clflush is set. */
850 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
851 char __user *user_data,
852 bool page_do_bit17_swizzling,
853 bool needs_clflush_before,
854 bool needs_clflush_after)
859 if (unlikely(page_do_bit17_swizzling))
862 vaddr = kmap_atomic(page);
863 if (needs_clflush_before)
864 drm_clflush_virt_range(vaddr + shmem_page_offset,
866 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
867 user_data, page_length);
868 if (needs_clflush_after)
869 drm_clflush_virt_range(vaddr + shmem_page_offset,
871 kunmap_atomic(vaddr);
873 return ret ? -EFAULT : 0;
876 /* Only difference to the fast-path function is that this can handle bit17
877 * and uses non-atomic copy and kmap functions. */
879 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
880 char __user *user_data,
881 bool page_do_bit17_swizzling,
882 bool needs_clflush_before,
883 bool needs_clflush_after)
889 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
890 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
892 page_do_bit17_swizzling);
893 if (page_do_bit17_swizzling)
894 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
898 ret = __copy_from_user(vaddr + shmem_page_offset,
901 if (needs_clflush_after)
902 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
904 page_do_bit17_swizzling);
907 return ret ? -EFAULT : 0;
911 i915_gem_shmem_pwrite(struct drm_device *dev,
912 struct drm_i915_gem_object *obj,
913 struct drm_i915_gem_pwrite *args,
914 struct drm_file *file)
918 char __user *user_data;
919 int shmem_page_offset, page_length, ret = 0;
920 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
921 int hit_slowpath = 0;
922 int needs_clflush_after = 0;
923 int needs_clflush_before = 0;
924 struct sg_page_iter sg_iter;
926 user_data = to_user_ptr(args->data_ptr);
929 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
931 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
932 /* If we're not in the cpu write domain, set ourself into the gtt
933 * write domain and manually flush cachelines (if required). This
934 * optimizes for the case when the gpu will use the data
935 * right away and we therefore have to clflush anyway. */
936 needs_clflush_after = cpu_write_needs_clflush(obj);
937 ret = i915_gem_object_wait_rendering(obj, false);
941 /* Same trick applies to invalidate partially written cachelines read
943 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
944 needs_clflush_before =
945 !cpu_cache_is_coherent(dev, obj->cache_level);
947 ret = i915_gem_object_get_pages(obj);
951 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
953 i915_gem_object_pin_pages(obj);
955 offset = args->offset;
958 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
959 offset >> PAGE_SHIFT) {
960 struct page *page = sg_page_iter_page(&sg_iter);
961 int partial_cacheline_write;
966 /* Operation in this page
968 * shmem_page_offset = offset within page in shmem file
969 * page_length = bytes to copy for this page
971 shmem_page_offset = offset_in_page(offset);
973 page_length = remain;
974 if ((shmem_page_offset + page_length) > PAGE_SIZE)
975 page_length = PAGE_SIZE - shmem_page_offset;
977 /* If we don't overwrite a cacheline completely we need to be
978 * careful to have up-to-date data by first clflushing. Don't
979 * overcomplicate things and flush the entire patch. */
980 partial_cacheline_write = needs_clflush_before &&
981 ((shmem_page_offset | page_length)
982 & (boot_cpu_data.x86_clflush_size - 1));
984 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
985 (page_to_phys(page) & (1 << 17)) != 0;
987 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
988 user_data, page_do_bit17_swizzling,
989 partial_cacheline_write,
990 needs_clflush_after);
995 mutex_unlock(&dev->struct_mutex);
996 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
997 user_data, page_do_bit17_swizzling,
998 partial_cacheline_write,
999 needs_clflush_after);
1001 mutex_lock(&dev->struct_mutex);
1007 remain -= page_length;
1008 user_data += page_length;
1009 offset += page_length;
1013 i915_gem_object_unpin_pages(obj);
1017 * Fixup: Flush cpu caches in case we didn't flush the dirty
1018 * cachelines in-line while writing and the object moved
1019 * out of the cpu write domain while we've dropped the lock.
1021 if (!needs_clflush_after &&
1022 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1023 if (i915_gem_clflush_object(obj, obj->pin_display))
1024 i915_gem_chipset_flush(dev);
1028 if (needs_clflush_after)
1029 i915_gem_chipset_flush(dev);
1031 intel_fb_obj_flush(obj, false);
1036 * Writes data to the object referenced by handle.
1038 * On error, the contents of the buffer that were to be modified are undefined.
1041 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1042 struct drm_file *file)
1044 struct drm_i915_private *dev_priv = dev->dev_private;
1045 struct drm_i915_gem_pwrite *args = data;
1046 struct drm_i915_gem_object *obj;
1049 if (args->size == 0)
1052 if (!access_ok(VERIFY_READ,
1053 to_user_ptr(args->data_ptr),
1057 if (likely(!i915.prefault_disable)) {
1058 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1064 intel_runtime_pm_get(dev_priv);
1066 ret = i915_mutex_lock_interruptible(dev);
1070 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1071 if (&obj->base == NULL) {
1076 /* Bounds check destination. */
1077 if (args->offset > obj->base.size ||
1078 args->size > obj->base.size - args->offset) {
1083 /* prime objects have no backing filp to GEM pread/pwrite
1086 if (!obj->base.filp) {
1091 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1094 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1095 * it would end up going through the fenced access, and we'll get
1096 * different detiling behavior between reading and writing.
1097 * pread/pwrite currently are reading and writing from the CPU
1098 * perspective, requiring manual detiling by the client.
1100 if (obj->tiling_mode == I915_TILING_NONE &&
1101 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1102 cpu_write_needs_clflush(obj)) {
1103 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1104 /* Note that the gtt paths might fail with non-page-backed user
1105 * pointers (e.g. gtt mappings when moving data between
1106 * textures). Fallback to the shmem path in that case. */
1109 if (ret == -EFAULT || ret == -ENOSPC) {
1110 if (obj->phys_handle)
1111 ret = i915_gem_phys_pwrite(obj, args, file);
1113 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1117 drm_gem_object_unreference(&obj->base);
1119 mutex_unlock(&dev->struct_mutex);
1121 intel_runtime_pm_put(dev_priv);
1127 i915_gem_check_wedge(struct i915_gpu_error *error,
1130 if (i915_reset_in_progress(error)) {
1131 /* Non-interruptible callers can't handle -EAGAIN, hence return
1132 * -EIO unconditionally for these. */
1136 /* Recovery complete, but the reset failed ... */
1137 if (i915_terminally_wedged(error))
1141 * Check if GPU Reset is in progress - we need intel_ring_begin
1142 * to work properly to reinit the hw state while the gpu is
1143 * still marked as reset-in-progress. Handle this with a flag.
1145 if (!error->reload_in_reset)
1152 static void fake_irq(unsigned long data)
1154 wake_up_process((struct task_struct *)data);
1157 static bool missed_irq(struct drm_i915_private *dev_priv,
1158 struct intel_engine_cs *ring)
1160 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1163 static int __i915_spin_request(struct drm_i915_gem_request *req)
1165 unsigned long timeout;
1167 if (i915_gem_request_get_ring(req)->irq_refcount)
1170 timeout = jiffies + 1;
1171 while (!need_resched()) {
1172 if (i915_gem_request_completed(req, true))
1175 if (time_after_eq(jiffies, timeout))
1178 cpu_relax_lowlatency();
1180 if (i915_gem_request_completed(req, false))
1187 * __i915_wait_request - wait until execution of request has finished
1189 * @reset_counter: reset sequence associated with the given request
1190 * @interruptible: do an interruptible wait (normally yes)
1191 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1193 * Note: It is of utmost importance that the passed in seqno and reset_counter
1194 * values have been read by the caller in an smp safe manner. Where read-side
1195 * locks are involved, it is sufficient to read the reset_counter before
1196 * unlocking the lock that protects the seqno. For lockless tricks, the
1197 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1200 * Returns 0 if the request was found within the alloted time. Else returns the
1201 * errno with remaining time filled in timeout argument.
1203 int __i915_wait_request(struct drm_i915_gem_request *req,
1204 unsigned reset_counter,
1207 struct intel_rps_client *rps)
1209 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1210 struct drm_device *dev = ring->dev;
1211 struct drm_i915_private *dev_priv = dev->dev_private;
1212 const bool irq_test_in_progress =
1213 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1215 unsigned long timeout_expire;
1219 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1221 if (list_empty(&req->list))
1224 if (i915_gem_request_completed(req, true))
1227 timeout_expire = timeout ?
1228 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1230 if (INTEL_INFO(dev_priv)->gen >= 6)
1231 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);
1233 /* Record current time in case interrupted by signal, or wedged */
1234 trace_i915_gem_request_wait_begin(req);
1235 before = ktime_get_raw_ns();
1237 /* Optimistic spin for the next jiffie before touching IRQs */
1238 ret = __i915_spin_request(req);
1242 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) {
1248 struct timer_list timer;
1250 prepare_to_wait(&ring->irq_queue, &wait,
1251 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1253 /* We need to check whether any gpu reset happened in between
1254 * the caller grabbing the seqno and now ... */
1255 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1256 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1257 * is truely gone. */
1258 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1264 if (i915_gem_request_completed(req, false)) {
1269 if (interruptible && signal_pending(current)) {
1274 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1279 timer.function = NULL;
1280 if (timeout || missed_irq(dev_priv, ring)) {
1281 unsigned long expire;
1283 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1284 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1285 mod_timer(&timer, expire);
1290 if (timer.function) {
1291 del_singleshot_timer_sync(&timer);
1292 destroy_timer_on_stack(&timer);
1295 if (!irq_test_in_progress)
1296 ring->irq_put(ring);
1298 finish_wait(&ring->irq_queue, &wait);
1301 now = ktime_get_raw_ns();
1302 trace_i915_gem_request_wait_end(req);
1305 s64 tres = *timeout - (now - before);
1307 *timeout = tres < 0 ? 0 : tres;
1310 * Apparently ktime isn't accurate enough and occasionally has a
1311 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1312 * things up to make the test happy. We allow up to 1 jiffy.
1314 * This is a regrssion from the timespec->ktime conversion.
1316 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1323 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
1324 struct drm_file *file)
1326 struct drm_i915_private *dev_private;
1327 struct drm_i915_file_private *file_priv;
1329 WARN_ON(!req || !file || req->file_priv);
1337 dev_private = req->ring->dev->dev_private;
1338 file_priv = file->driver_priv;
1340 spin_lock(&file_priv->mm.lock);
1341 req->file_priv = file_priv;
1342 list_add_tail(&req->client_list, &file_priv->mm.request_list);
1343 spin_unlock(&file_priv->mm.lock);
1345 req->pid = get_pid(task_pid(current));
1351 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1353 struct drm_i915_file_private *file_priv = request->file_priv;
1358 spin_lock(&file_priv->mm.lock);
1359 list_del(&request->client_list);
1360 request->file_priv = NULL;
1361 spin_unlock(&file_priv->mm.lock);
1363 put_pid(request->pid);
1364 request->pid = NULL;
1367 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
1369 trace_i915_gem_request_retire(request);
1371 /* We know the GPU must have read the request to have
1372 * sent us the seqno + interrupt, so use the position
1373 * of tail of the request to update the last known position
1376 * Note this requires that we are always called in request
1379 request->ringbuf->last_retired_head = request->postfix;
1381 list_del_init(&request->list);
1382 i915_gem_request_remove_from_client(request);
1384 i915_gem_request_unreference(request);
1388 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
1390 struct intel_engine_cs *engine = req->ring;
1391 struct drm_i915_gem_request *tmp;
1393 lockdep_assert_held(&engine->dev->struct_mutex);
1395 if (list_empty(&req->list))
1399 tmp = list_first_entry(&engine->request_list,
1400 typeof(*tmp), list);
1402 i915_gem_request_retire(tmp);
1403 } while (tmp != req);
1405 WARN_ON(i915_verify_lists(engine->dev));
1409 * Waits for a request to be signaled, and cleans up the
1410 * request and object lists appropriately for that event.
1413 i915_wait_request(struct drm_i915_gem_request *req)
1415 struct drm_device *dev;
1416 struct drm_i915_private *dev_priv;
1420 BUG_ON(req == NULL);
1422 dev = req->ring->dev;
1423 dev_priv = dev->dev_private;
1424 interruptible = dev_priv->mm.interruptible;
1426 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1428 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1432 ret = __i915_wait_request(req,
1433 atomic_read(&dev_priv->gpu_error.reset_counter),
1434 interruptible, NULL, NULL);
1438 __i915_gem_request_retire__upto(req);
1443 * Ensures that all rendering to the object has completed and the object is
1444 * safe to unbind from the GTT or access from the CPU.
1447 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1456 if (obj->last_write_req != NULL) {
1457 ret = i915_wait_request(obj->last_write_req);
1461 i = obj->last_write_req->ring->id;
1462 if (obj->last_read_req[i] == obj->last_write_req)
1463 i915_gem_object_retire__read(obj, i);
1465 i915_gem_object_retire__write(obj);
1468 for (i = 0; i < I915_NUM_RINGS; i++) {
1469 if (obj->last_read_req[i] == NULL)
1472 ret = i915_wait_request(obj->last_read_req[i]);
1476 i915_gem_object_retire__read(obj, i);
1478 RQ_BUG_ON(obj->active);
1485 i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
1486 struct drm_i915_gem_request *req)
1488 int ring = req->ring->id;
1490 if (obj->last_read_req[ring] == req)
1491 i915_gem_object_retire__read(obj, ring);
1492 else if (obj->last_write_req == req)
1493 i915_gem_object_retire__write(obj);
1495 __i915_gem_request_retire__upto(req);
1498 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1499 * as the object state may change during this call.
1501 static __must_check int
1502 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1503 struct intel_rps_client *rps,
1506 struct drm_device *dev = obj->base.dev;
1507 struct drm_i915_private *dev_priv = dev->dev_private;
1508 struct drm_i915_gem_request *requests[I915_NUM_RINGS];
1509 unsigned reset_counter;
1512 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1513 BUG_ON(!dev_priv->mm.interruptible);
1518 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1522 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1525 struct drm_i915_gem_request *req;
1527 req = obj->last_write_req;
1531 requests[n++] = i915_gem_request_reference(req);
1533 for (i = 0; i < I915_NUM_RINGS; i++) {
1534 struct drm_i915_gem_request *req;
1536 req = obj->last_read_req[i];
1540 requests[n++] = i915_gem_request_reference(req);
1544 mutex_unlock(&dev->struct_mutex);
1545 for (i = 0; ret == 0 && i < n; i++)
1546 ret = __i915_wait_request(requests[i], reset_counter, true,
1548 mutex_lock(&dev->struct_mutex);
1550 for (i = 0; i < n; i++) {
1552 i915_gem_object_retire_request(obj, requests[i]);
1553 i915_gem_request_unreference(requests[i]);
1559 static struct intel_rps_client *to_rps_client(struct drm_file *file)
1561 struct drm_i915_file_private *fpriv = file->driver_priv;
1566 * Called when user space prepares to use an object with the CPU, either
1567 * through the mmap ioctl's mapping or a GTT mapping.
1570 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1571 struct drm_file *file)
1573 struct drm_i915_gem_set_domain *args = data;
1574 struct drm_i915_gem_object *obj;
1575 uint32_t read_domains = args->read_domains;
1576 uint32_t write_domain = args->write_domain;
1579 /* Only handle setting domains to types used by the CPU. */
1580 if (write_domain & I915_GEM_GPU_DOMAINS)
1583 if (read_domains & I915_GEM_GPU_DOMAINS)
1586 /* Having something in the write domain implies it's in the read
1587 * domain, and only that read domain. Enforce that in the request.
1589 if (write_domain != 0 && read_domains != write_domain)
1592 ret = i915_mutex_lock_interruptible(dev);
1596 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1597 if (&obj->base == NULL) {
1602 /* Try to flush the object off the GPU without holding the lock.
1603 * We will repeat the flush holding the lock in the normal manner
1604 * to catch cases where we are gazumped.
1606 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1607 to_rps_client(file),
1612 if (read_domains & I915_GEM_DOMAIN_GTT)
1613 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1615 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1617 if (write_domain != 0)
1618 intel_fb_obj_invalidate(obj,
1619 write_domain == I915_GEM_DOMAIN_GTT ?
1620 ORIGIN_GTT : ORIGIN_CPU);
1623 drm_gem_object_unreference(&obj->base);
1625 mutex_unlock(&dev->struct_mutex);
1630 * Called when user space has done writes to this buffer
1633 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1634 struct drm_file *file)
1636 struct drm_i915_gem_sw_finish *args = data;
1637 struct drm_i915_gem_object *obj;
1640 ret = i915_mutex_lock_interruptible(dev);
1644 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1645 if (&obj->base == NULL) {
1650 /* Pinned buffers may be scanout, so flush the cache */
1651 if (obj->pin_display)
1652 i915_gem_object_flush_cpu_write_domain(obj);
1654 drm_gem_object_unreference(&obj->base);
1656 mutex_unlock(&dev->struct_mutex);
1661 * Maps the contents of an object, returning the address it is mapped
1664 * While the mapping holds a reference on the contents of the object, it doesn't
1665 * imply a ref on the object itself.
1669 * DRM driver writers who look a this function as an example for how to do GEM
1670 * mmap support, please don't implement mmap support like here. The modern way
1671 * to implement DRM mmap support is with an mmap offset ioctl (like
1672 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1673 * That way debug tooling like valgrind will understand what's going on, hiding
1674 * the mmap call in a driver private ioctl will break that. The i915 driver only
1675 * does cpu mmaps this way because we didn't know better.
1678 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1679 struct drm_file *file)
1681 struct drm_i915_gem_mmap *args = data;
1682 struct drm_gem_object *obj;
1685 if (args->flags & ~(I915_MMAP_WC))
1688 if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1691 obj = drm_gem_object_lookup(dev, file, args->handle);
1695 /* prime objects have no backing filp to GEM mmap
1699 drm_gem_object_unreference_unlocked(obj);
1703 addr = vm_mmap(obj->filp, 0, args->size,
1704 PROT_READ | PROT_WRITE, MAP_SHARED,
1706 if (args->flags & I915_MMAP_WC) {
1707 struct mm_struct *mm = current->mm;
1708 struct vm_area_struct *vma;
1710 down_write(&mm->mmap_sem);
1711 vma = find_vma(mm, addr);
1714 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1717 up_write(&mm->mmap_sem);
1719 drm_gem_object_unreference_unlocked(obj);
1720 if (IS_ERR((void *)addr))
1723 args->addr_ptr = (uint64_t) addr;
1729 * i915_gem_fault - fault a page into the GTT
1730 * vma: VMA in question
1733 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1734 * from userspace. The fault handler takes care of binding the object to
1735 * the GTT (if needed), allocating and programming a fence register (again,
1736 * only if needed based on whether the old reg is still valid or the object
1737 * is tiled) and inserting a new PTE into the faulting process.
1739 * Note that the faulting process may involve evicting existing objects
1740 * from the GTT and/or fence registers to make room. So performance may
1741 * suffer if the GTT working set is large or there are few fence registers
1744 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1746 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1747 struct drm_device *dev = obj->base.dev;
1748 struct drm_i915_private *dev_priv = dev->dev_private;
1749 struct i915_ggtt_view view = i915_ggtt_view_normal;
1750 pgoff_t page_offset;
1753 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1755 intel_runtime_pm_get(dev_priv);
1757 /* We don't use vmf->pgoff since that has the fake offset */
1758 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1761 ret = i915_mutex_lock_interruptible(dev);
1765 trace_i915_gem_object_fault(obj, page_offset, true, write);
1767 /* Try to flush the object off the GPU first without holding the lock.
1768 * Upon reacquiring the lock, we will perform our sanity checks and then
1769 * repeat the flush holding the lock in the normal manner to catch cases
1770 * where we are gazumped.
1772 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1776 /* Access to snoopable pages through the GTT is incoherent. */
1777 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1782 /* Use a partial view if the object is bigger than the aperture. */
1783 if (obj->base.size >= dev_priv->gtt.mappable_end &&
1784 obj->tiling_mode == I915_TILING_NONE) {
1785 static const unsigned int chunk_size = 256; // 1 MiB
1787 memset(&view, 0, sizeof(view));
1788 view.type = I915_GGTT_VIEW_PARTIAL;
1789 view.params.partial.offset = rounddown(page_offset, chunk_size);
1790 view.params.partial.size =
1793 (vma->vm_end - vma->vm_start)/PAGE_SIZE -
1794 view.params.partial.offset);
1797 /* Now pin it into the GTT if needed */
1798 ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
1802 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1806 ret = i915_gem_object_get_fence(obj);
1810 /* Finally, remap it using the new GTT offset */
1811 pfn = dev_priv->gtt.mappable_base +
1812 i915_gem_obj_ggtt_offset_view(obj, &view);
1815 if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
1816 /* Overriding existing pages in partial view does not cause
1817 * us any trouble as TLBs are still valid because the fault
1818 * is due to userspace losing part of the mapping or never
1819 * having accessed it before (at this partials' range).
1821 unsigned long base = vma->vm_start +
1822 (view.params.partial.offset << PAGE_SHIFT);
1825 for (i = 0; i < view.params.partial.size; i++) {
1826 ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
1831 obj->fault_mappable = true;
1833 if (!obj->fault_mappable) {
1834 unsigned long size = min_t(unsigned long,
1835 vma->vm_end - vma->vm_start,
1839 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1840 ret = vm_insert_pfn(vma,
1841 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1847 obj->fault_mappable = true;
1849 ret = vm_insert_pfn(vma,
1850 (unsigned long)vmf->virtual_address,
1854 i915_gem_object_ggtt_unpin_view(obj, &view);
1856 mutex_unlock(&dev->struct_mutex);
1861 * We eat errors when the gpu is terminally wedged to avoid
1862 * userspace unduly crashing (gl has no provisions for mmaps to
1863 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1864 * and so needs to be reported.
1866 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1867 ret = VM_FAULT_SIGBUS;
1872 * EAGAIN means the gpu is hung and we'll wait for the error
1873 * handler to reset everything when re-faulting in
1874 * i915_mutex_lock_interruptible.
1881 * EBUSY is ok: this just means that another thread
1882 * already did the job.
1884 ret = VM_FAULT_NOPAGE;
1891 ret = VM_FAULT_SIGBUS;
1894 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1895 ret = VM_FAULT_SIGBUS;
1899 intel_runtime_pm_put(dev_priv);
1904 * i915_gem_release_mmap - remove physical page mappings
1905 * @obj: obj in question
1907 * Preserve the reservation of the mmapping with the DRM core code, but
1908 * relinquish ownership of the pages back to the system.
1910 * It is vital that we remove the page mapping if we have mapped a tiled
1911 * object through the GTT and then lose the fence register due to
1912 * resource pressure. Similarly if the object has been moved out of the
1913 * aperture, than pages mapped into userspace must be revoked. Removing the
1914 * mapping will then trigger a page fault on the next user access, allowing
1915 * fixup by i915_gem_fault().
1918 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1920 if (!obj->fault_mappable)
1923 drm_vma_node_unmap(&obj->base.vma_node,
1924 obj->base.dev->anon_inode->i_mapping);
1925 obj->fault_mappable = false;
1929 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1931 struct drm_i915_gem_object *obj;
1933 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1934 i915_gem_release_mmap(obj);
1938 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1942 if (INTEL_INFO(dev)->gen >= 4 ||
1943 tiling_mode == I915_TILING_NONE)
1946 /* Previous chips need a power-of-two fence region when tiling */
1947 if (INTEL_INFO(dev)->gen == 3)
1948 gtt_size = 1024*1024;
1950 gtt_size = 512*1024;
1952 while (gtt_size < size)
1959 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1960 * @obj: object to check
1962 * Return the required GTT alignment for an object, taking into account
1963 * potential fence register mapping.
1966 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1967 int tiling_mode, bool fenced)
1970 * Minimum alignment is 4k (GTT page size), but might be greater
1971 * if a fence register is needed for the object.
1973 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1974 tiling_mode == I915_TILING_NONE)
1978 * Previous chips need to be aligned to the size of the smallest
1979 * fence register that can contain the object.
1981 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1984 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1986 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1989 if (drm_vma_node_has_offset(&obj->base.vma_node))
1992 dev_priv->mm.shrinker_no_lock_stealing = true;
1994 ret = drm_gem_create_mmap_offset(&obj->base);
1998 /* Badly fragmented mmap space? The only way we can recover
1999 * space is by destroying unwanted objects. We can't randomly release
2000 * mmap_offsets as userspace expects them to be persistent for the
2001 * lifetime of the objects. The closest we can is to release the
2002 * offsets on purgeable objects by truncating it and marking it purged,
2003 * which prevents userspace from ever using that object again.
2005 i915_gem_shrink(dev_priv,
2006 obj->base.size >> PAGE_SHIFT,
2008 I915_SHRINK_UNBOUND |
2009 I915_SHRINK_PURGEABLE);
2010 ret = drm_gem_create_mmap_offset(&obj->base);
2014 i915_gem_shrink_all(dev_priv);
2015 ret = drm_gem_create_mmap_offset(&obj->base);
2017 dev_priv->mm.shrinker_no_lock_stealing = false;
2022 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2024 drm_gem_free_mmap_offset(&obj->base);
2028 i915_gem_mmap_gtt(struct drm_file *file,
2029 struct drm_device *dev,
2033 struct drm_i915_gem_object *obj;
2036 ret = i915_mutex_lock_interruptible(dev);
2040 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
2041 if (&obj->base == NULL) {
2046 if (obj->madv != I915_MADV_WILLNEED) {
2047 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2052 ret = i915_gem_object_create_mmap_offset(obj);
2056 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2059 drm_gem_object_unreference(&obj->base);
2061 mutex_unlock(&dev->struct_mutex);
2066 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2068 * @data: GTT mapping ioctl data
2069 * @file: GEM object info
2071 * Simply returns the fake offset to userspace so it can mmap it.
2072 * The mmap call will end up in drm_gem_mmap(), which will set things
2073 * up so we can get faults in the handler above.
2075 * The fault handler will take care of binding the object into the GTT
2076 * (since it may have been evicted to make room for something), allocating
2077 * a fence register, and mapping the appropriate aperture address into
2081 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2082 struct drm_file *file)
2084 struct drm_i915_gem_mmap_gtt *args = data;
2086 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2089 /* Immediately discard the backing storage */
2091 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2093 i915_gem_object_free_mmap_offset(obj);
2095 if (obj->base.filp == NULL)
2098 /* Our goal here is to return as much of the memory as
2099 * is possible back to the system as we are called from OOM.
2100 * To do this we must instruct the shmfs to drop all of its
2101 * backing pages, *now*.
2103 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2104 obj->madv = __I915_MADV_PURGED;
2107 /* Try to discard unwanted pages */
2109 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2111 struct address_space *mapping;
2113 switch (obj->madv) {
2114 case I915_MADV_DONTNEED:
2115 i915_gem_object_truncate(obj);
2116 case __I915_MADV_PURGED:
2120 if (obj->base.filp == NULL)
2123 mapping = file_inode(obj->base.filp)->i_mapping,
2124 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2128 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2130 struct sg_page_iter sg_iter;
2133 BUG_ON(obj->madv == __I915_MADV_PURGED);
2135 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2137 /* In the event of a disaster, abandon all caches and
2138 * hope for the best.
2140 WARN_ON(ret != -EIO);
2141 i915_gem_clflush_object(obj, true);
2142 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2145 if (i915_gem_object_needs_bit17_swizzle(obj))
2146 i915_gem_object_save_bit_17_swizzle(obj);
2148 if (obj->madv == I915_MADV_DONTNEED)
2151 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2152 struct page *page = sg_page_iter_page(&sg_iter);
2155 set_page_dirty(page);
2157 if (obj->madv == I915_MADV_WILLNEED)
2158 mark_page_accessed(page);
2160 page_cache_release(page);
2164 sg_free_table(obj->pages);
2169 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2171 const struct drm_i915_gem_object_ops *ops = obj->ops;
2173 if (obj->pages == NULL)
2176 if (obj->pages_pin_count)
2179 BUG_ON(i915_gem_obj_bound_any(obj));
2181 /* ->put_pages might need to allocate memory for the bit17 swizzle
2182 * array, hence protect them from being reaped by removing them from gtt
2184 list_del(&obj->global_list);
2186 ops->put_pages(obj);
2189 i915_gem_object_invalidate(obj);
2195 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2197 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2199 struct address_space *mapping;
2200 struct sg_table *st;
2201 struct scatterlist *sg;
2202 struct sg_page_iter sg_iter;
2204 unsigned long last_pfn = 0; /* suppress gcc warning */
2207 /* Assert that the object is not currently in any GPU domain. As it
2208 * wasn't in the GTT, there shouldn't be any way it could have been in
2211 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2212 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2214 st = kmalloc(sizeof(*st), GFP_KERNEL);
2218 page_count = obj->base.size / PAGE_SIZE;
2219 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2224 /* Get the list of pages out of our struct file. They'll be pinned
2225 * at this point until we release them.
2227 * Fail silently without starting the shrinker
2229 mapping = file_inode(obj->base.filp)->i_mapping;
2230 gfp = mapping_gfp_mask(mapping);
2231 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2232 gfp &= ~(__GFP_IO | __GFP_WAIT);
2235 for (i = 0; i < page_count; i++) {
2236 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2238 i915_gem_shrink(dev_priv,
2241 I915_SHRINK_UNBOUND |
2242 I915_SHRINK_PURGEABLE);
2243 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2246 /* We've tried hard to allocate the memory by reaping
2247 * our own buffer, now let the real VM do its job and
2248 * go down in flames if truly OOM.
2250 i915_gem_shrink_all(dev_priv);
2251 page = shmem_read_mapping_page(mapping, i);
2255 #ifdef CONFIG_SWIOTLB
2256 if (swiotlb_nr_tbl()) {
2258 sg_set_page(sg, page, PAGE_SIZE, 0);
2263 if (!i || page_to_pfn(page) != last_pfn + 1) {
2267 sg_set_page(sg, page, PAGE_SIZE, 0);
2269 sg->length += PAGE_SIZE;
2271 last_pfn = page_to_pfn(page);
2273 /* Check that the i965g/gm workaround works. */
2274 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2276 #ifdef CONFIG_SWIOTLB
2277 if (!swiotlb_nr_tbl())
2282 if (i915_gem_object_needs_bit17_swizzle(obj))
2283 i915_gem_object_do_bit_17_swizzle(obj);
2285 if (obj->tiling_mode != I915_TILING_NONE &&
2286 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2287 i915_gem_object_pin_pages(obj);
2293 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2294 page_cache_release(sg_page_iter_page(&sg_iter));
2298 /* shmemfs first checks if there is enough memory to allocate the page
2299 * and reports ENOSPC should there be insufficient, along with the usual
2300 * ENOMEM for a genuine allocation failure.
2302 * We use ENOSPC in our driver to mean that we have run out of aperture
2303 * space and so want to translate the error from shmemfs back to our
2304 * usual understanding of ENOMEM.
2306 if (PTR_ERR(page) == -ENOSPC)
2309 return PTR_ERR(page);
2312 /* Ensure that the associated pages are gathered from the backing storage
2313 * and pinned into our object. i915_gem_object_get_pages() may be called
2314 * multiple times before they are released by a single call to
2315 * i915_gem_object_put_pages() - once the pages are no longer referenced
2316 * either as a result of memory pressure (reaping pages under the shrinker)
2317 * or as the object is itself released.
2320 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2322 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2323 const struct drm_i915_gem_object_ops *ops = obj->ops;
2329 if (obj->madv != I915_MADV_WILLNEED) {
2330 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2334 BUG_ON(obj->pages_pin_count);
2336 ret = ops->get_pages(obj);
2340 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2342 obj->get_page.sg = obj->pages->sgl;
2343 obj->get_page.last = 0;
2348 void i915_vma_move_to_active(struct i915_vma *vma,
2349 struct drm_i915_gem_request *req)
2351 struct drm_i915_gem_object *obj = vma->obj;
2352 struct intel_engine_cs *ring;
2354 ring = i915_gem_request_get_ring(req);
2356 /* Add a reference if we're newly entering the active list. */
2357 if (obj->active == 0)
2358 drm_gem_object_reference(&obj->base);
2359 obj->active |= intel_ring_flag(ring);
2361 list_move_tail(&obj->ring_list[ring->id], &ring->active_list);
2362 i915_gem_request_assign(&obj->last_read_req[ring->id], req);
2364 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2368 i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
2370 RQ_BUG_ON(obj->last_write_req == NULL);
2371 RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring)));
2373 i915_gem_request_assign(&obj->last_write_req, NULL);
2374 intel_fb_obj_flush(obj, true);
2378 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
2380 struct i915_vma *vma;
2382 RQ_BUG_ON(obj->last_read_req[ring] == NULL);
2383 RQ_BUG_ON(!(obj->active & (1 << ring)));
2385 list_del_init(&obj->ring_list[ring]);
2386 i915_gem_request_assign(&obj->last_read_req[ring], NULL);
2388 if (obj->last_write_req && obj->last_write_req->ring->id == ring)
2389 i915_gem_object_retire__write(obj);
2391 obj->active &= ~(1 << ring);
2395 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2396 if (!list_empty(&vma->mm_list))
2397 list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2400 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2401 drm_gem_object_unreference(&obj->base);
2405 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_engine_cs *ring;
2411 /* Carefully retire all requests without writing to the rings */
2412 for_each_ring(ring, dev_priv, i) {
2413 ret = intel_ring_idle(ring);
2417 i915_gem_retire_requests(dev);
2419 /* Finally reset hw state */
2420 for_each_ring(ring, dev_priv, i) {
2421 intel_ring_init_seqno(ring, seqno);
2423 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2424 ring->semaphore.sync_seqno[j] = 0;
2430 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2438 /* HWS page needs to be set less than what we
2439 * will inject to ring
2441 ret = i915_gem_init_seqno(dev, seqno - 1);
2445 /* Carefully set the last_seqno value so that wrap
2446 * detection still works
2448 dev_priv->next_seqno = seqno;
2449 dev_priv->last_seqno = seqno - 1;
2450 if (dev_priv->last_seqno == 0)
2451 dev_priv->last_seqno--;
2457 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2459 struct drm_i915_private *dev_priv = dev->dev_private;
2461 /* reserve 0 for non-seqno */
2462 if (dev_priv->next_seqno == 0) {
2463 int ret = i915_gem_init_seqno(dev, 0);
2467 dev_priv->next_seqno = 1;
2470 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2475 * NB: This function is not allowed to fail. Doing so would mean the the
2476 * request is not being tracked for completion but the work itself is
2477 * going to happen on the hardware. This would be a Bad Thing(tm).
2479 void __i915_add_request(struct drm_i915_gem_request *request,
2480 struct drm_i915_gem_object *obj,
2483 struct intel_engine_cs *ring;
2484 struct drm_i915_private *dev_priv;
2485 struct intel_ringbuffer *ringbuf;
2489 if (WARN_ON(request == NULL))
2492 ring = request->ring;
2493 dev_priv = ring->dev->dev_private;
2494 ringbuf = request->ringbuf;
2497 * To ensure that this call will not fail, space for its emissions
2498 * should already have been reserved in the ring buffer. Let the ring
2499 * know that it is time to use that space up.
2501 intel_ring_reserved_space_use(ringbuf);
2503 request_start = intel_ring_get_tail(ringbuf);
2505 * Emit any outstanding flushes - execbuf can fail to emit the flush
2506 * after having emitted the batchbuffer command. Hence we need to fix
2507 * things up similar to emitting the lazy request. The difference here
2508 * is that the flush _must_ happen before the next request, no matter
2512 if (i915.enable_execlists)
2513 ret = logical_ring_flush_all_caches(request);
2515 ret = intel_ring_flush_all_caches(request);
2516 /* Not allowed to fail! */
2517 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
2520 /* Record the position of the start of the request so that
2521 * should we detect the updated seqno part-way through the
2522 * GPU processing the request, we never over-estimate the
2523 * position of the head.
2525 request->postfix = intel_ring_get_tail(ringbuf);
2527 if (i915.enable_execlists)
2528 ret = ring->emit_request(request);
2530 ret = ring->add_request(request);
2532 request->tail = intel_ring_get_tail(ringbuf);
2534 /* Not allowed to fail! */
2535 WARN(ret, "emit|add_request failed: %d!\n", ret);
2537 request->head = request_start;
2539 /* Whilst this request exists, batch_obj will be on the
2540 * active_list, and so will hold the active reference. Only when this
2541 * request is retired will the the batch_obj be moved onto the
2542 * inactive_list and lose its active reference. Hence we do not need
2543 * to explicitly hold another reference here.
2545 request->batch_obj = obj;
2547 request->emitted_jiffies = jiffies;
2548 list_add_tail(&request->list, &ring->request_list);
2550 trace_i915_gem_request_add(request);
2552 i915_queue_hangcheck(ring->dev);
2554 queue_delayed_work(dev_priv->wq,
2555 &dev_priv->mm.retire_work,
2556 round_jiffies_up_relative(HZ));
2557 intel_mark_busy(dev_priv->dev);
2559 /* Sanity check that the reserved size was large enough. */
2560 intel_ring_reserved_space_end(ringbuf);
2563 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2564 const struct intel_context *ctx)
2566 unsigned long elapsed;
2568 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2570 if (ctx->hang_stats.banned)
2573 if (ctx->hang_stats.ban_period_seconds &&
2574 elapsed <= ctx->hang_stats.ban_period_seconds) {
2575 if (!i915_gem_context_is_default(ctx)) {
2576 DRM_DEBUG("context hanging too fast, banning!\n");
2578 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2579 if (i915_stop_ring_allow_warn(dev_priv))
2580 DRM_ERROR("gpu hanging too fast, banning!\n");
2588 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2589 struct intel_context *ctx,
2592 struct i915_ctx_hang_stats *hs;
2597 hs = &ctx->hang_stats;
2600 hs->banned = i915_context_is_banned(dev_priv, ctx);
2602 hs->guilty_ts = get_seconds();
2604 hs->batch_pending++;
2608 void i915_gem_request_free(struct kref *req_ref)
2610 struct drm_i915_gem_request *req = container_of(req_ref,
2612 struct intel_context *ctx = req->ctx;
2615 i915_gem_request_remove_from_client(req);
2618 if (i915.enable_execlists) {
2619 struct intel_engine_cs *ring = req->ring;
2621 if (ctx != ring->default_context)
2622 intel_lr_context_unpin(ring, ctx);
2625 i915_gem_context_unreference(ctx);
2628 kmem_cache_free(req->i915->requests, req);
2631 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2632 struct intel_context *ctx,
2633 struct drm_i915_gem_request **req_out)
2635 struct drm_i915_private *dev_priv = to_i915(ring->dev);
2636 struct drm_i915_gem_request *req;
2644 req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
2648 ret = i915_gem_get_seqno(ring->dev, &req->seqno);
2652 kref_init(&req->ref);
2653 req->i915 = dev_priv;
2656 i915_gem_context_reference(req->ctx);
2658 if (i915.enable_execlists)
2659 ret = intel_logical_ring_alloc_request_extras(req);
2661 ret = intel_ring_alloc_request_extras(req);
2663 i915_gem_context_unreference(req->ctx);
2668 * Reserve space in the ring buffer for all the commands required to
2669 * eventually emit this request. This is to guarantee that the
2670 * i915_add_request() call can't fail. Note that the reserve may need
2671 * to be redone if the request is not actually submitted straight
2672 * away, e.g. because a GPU scheduler has deferred it.
2674 if (i915.enable_execlists)
2675 ret = intel_logical_ring_reserve_space(req);
2677 ret = intel_ring_reserve_space(req);
2680 * At this point, the request is fully allocated even if not
2681 * fully prepared. Thus it can be cleaned up using the proper
2684 i915_gem_request_cancel(req);
2692 kmem_cache_free(dev_priv->requests, req);
2696 void i915_gem_request_cancel(struct drm_i915_gem_request *req)
2698 intel_ring_reserved_space_cancel(req->ringbuf);
2700 i915_gem_request_unreference(req);
2703 struct drm_i915_gem_request *
2704 i915_gem_find_active_request(struct intel_engine_cs *ring)
2706 struct drm_i915_gem_request *request;
2708 list_for_each_entry(request, &ring->request_list, list) {
2709 if (i915_gem_request_completed(request, false))
2718 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2719 struct intel_engine_cs *ring)
2721 struct drm_i915_gem_request *request;
2724 request = i915_gem_find_active_request(ring);
2726 if (request == NULL)
2729 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2731 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2733 list_for_each_entry_continue(request, &ring->request_list, list)
2734 i915_set_reset_status(dev_priv, request->ctx, false);
2737 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2738 struct intel_engine_cs *ring)
2740 while (!list_empty(&ring->active_list)) {
2741 struct drm_i915_gem_object *obj;
2743 obj = list_first_entry(&ring->active_list,
2744 struct drm_i915_gem_object,
2745 ring_list[ring->id]);
2747 i915_gem_object_retire__read(obj, ring->id);
2751 * Clear the execlists queue up before freeing the requests, as those
2752 * are the ones that keep the context and ringbuffer backing objects
2755 while (!list_empty(&ring->execlist_queue)) {
2756 struct drm_i915_gem_request *submit_req;
2758 submit_req = list_first_entry(&ring->execlist_queue,
2759 struct drm_i915_gem_request,
2761 list_del(&submit_req->execlist_link);
2763 if (submit_req->ctx != ring->default_context)
2764 intel_lr_context_unpin(ring, submit_req->ctx);
2766 i915_gem_request_unreference(submit_req);
2770 * We must free the requests after all the corresponding objects have
2771 * been moved off active lists. Which is the same order as the normal
2772 * retire_requests function does. This is important if object hold
2773 * implicit references on things like e.g. ppgtt address spaces through
2776 while (!list_empty(&ring->request_list)) {
2777 struct drm_i915_gem_request *request;
2779 request = list_first_entry(&ring->request_list,
2780 struct drm_i915_gem_request,
2783 i915_gem_request_retire(request);
2787 void i915_gem_restore_fences(struct drm_device *dev)
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2792 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2793 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2796 * Commit delayed tiling changes if we have an object still
2797 * attached to the fence, otherwise just clear the fence.
2800 i915_gem_object_update_fence(reg->obj, reg,
2801 reg->obj->tiling_mode);
2803 i915_gem_write_fence(dev, i, NULL);
2808 void i915_gem_reset(struct drm_device *dev)
2810 struct drm_i915_private *dev_priv = dev->dev_private;
2811 struct intel_engine_cs *ring;
2815 * Before we free the objects from the requests, we need to inspect
2816 * them for finding the guilty party. As the requests only borrow
2817 * their reference to the objects, the inspection must be done first.
2819 for_each_ring(ring, dev_priv, i)
2820 i915_gem_reset_ring_status(dev_priv, ring);
2822 for_each_ring(ring, dev_priv, i)
2823 i915_gem_reset_ring_cleanup(dev_priv, ring);
2825 i915_gem_context_reset(dev);
2827 i915_gem_restore_fences(dev);
2829 WARN_ON(i915_verify_lists(dev));
2833 * This function clears the request list as sequence numbers are passed.
2836 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2838 WARN_ON(i915_verify_lists(ring->dev));
2840 /* Retire requests first as we use it above for the early return.
2841 * If we retire requests last, we may use a later seqno and so clear
2842 * the requests lists without clearing the active list, leading to
2845 while (!list_empty(&ring->request_list)) {
2846 struct drm_i915_gem_request *request;
2848 request = list_first_entry(&ring->request_list,
2849 struct drm_i915_gem_request,
2852 if (!i915_gem_request_completed(request, true))
2855 i915_gem_request_retire(request);
2858 /* Move any buffers on the active list that are no longer referenced
2859 * by the ringbuffer to the flushing/inactive lists as appropriate,
2860 * before we free the context associated with the requests.
2862 while (!list_empty(&ring->active_list)) {
2863 struct drm_i915_gem_object *obj;
2865 obj = list_first_entry(&ring->active_list,
2866 struct drm_i915_gem_object,
2867 ring_list[ring->id]);
2869 if (!list_empty(&obj->last_read_req[ring->id]->list))
2872 i915_gem_object_retire__read(obj, ring->id);
2875 if (unlikely(ring->trace_irq_req &&
2876 i915_gem_request_completed(ring->trace_irq_req, true))) {
2877 ring->irq_put(ring);
2878 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2881 WARN_ON(i915_verify_lists(ring->dev));
2885 i915_gem_retire_requests(struct drm_device *dev)
2887 struct drm_i915_private *dev_priv = dev->dev_private;
2888 struct intel_engine_cs *ring;
2892 for_each_ring(ring, dev_priv, i) {
2893 i915_gem_retire_requests_ring(ring);
2894 idle &= list_empty(&ring->request_list);
2895 if (i915.enable_execlists) {
2896 unsigned long flags;
2898 spin_lock_irqsave(&ring->execlist_lock, flags);
2899 idle &= list_empty(&ring->execlist_queue);
2900 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2902 intel_execlists_retire_requests(ring);
2907 mod_delayed_work(dev_priv->wq,
2908 &dev_priv->mm.idle_work,
2909 msecs_to_jiffies(100));
2915 i915_gem_retire_work_handler(struct work_struct *work)
2917 struct drm_i915_private *dev_priv =
2918 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2919 struct drm_device *dev = dev_priv->dev;
2922 /* Come back later if the device is busy... */
2924 if (mutex_trylock(&dev->struct_mutex)) {
2925 idle = i915_gem_retire_requests(dev);
2926 mutex_unlock(&dev->struct_mutex);
2929 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2930 round_jiffies_up_relative(HZ));
2934 i915_gem_idle_work_handler(struct work_struct *work)
2936 struct drm_i915_private *dev_priv =
2937 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2938 struct drm_device *dev = dev_priv->dev;
2939 struct intel_engine_cs *ring;
2942 for_each_ring(ring, dev_priv, i)
2943 if (!list_empty(&ring->request_list))
2946 intel_mark_idle(dev);
2948 if (mutex_trylock(&dev->struct_mutex)) {
2949 struct intel_engine_cs *ring;
2952 for_each_ring(ring, dev_priv, i)
2953 i915_gem_batch_pool_fini(&ring->batch_pool);
2955 mutex_unlock(&dev->struct_mutex);
2960 * Ensures that an object will eventually get non-busy by flushing any required
2961 * write domains, emitting any outstanding lazy request and retiring and
2962 * completed requests.
2965 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2972 for (i = 0; i < I915_NUM_RINGS; i++) {
2973 struct drm_i915_gem_request *req;
2975 req = obj->last_read_req[i];
2979 if (list_empty(&req->list))
2982 if (i915_gem_request_completed(req, true)) {
2983 __i915_gem_request_retire__upto(req);
2985 i915_gem_object_retire__read(obj, i);
2993 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2994 * @DRM_IOCTL_ARGS: standard ioctl arguments
2996 * Returns 0 if successful, else an error is returned with the remaining time in
2997 * the timeout parameter.
2998 * -ETIME: object is still busy after timeout
2999 * -ERESTARTSYS: signal interrupted the wait
3000 * -ENONENT: object doesn't exist
3001 * Also possible, but rare:
3002 * -EAGAIN: GPU wedged
3004 * -ENODEV: Internal IRQ fail
3005 * -E?: The add request failed
3007 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3008 * non-zero timeout parameter the wait ioctl will wait for the given number of
3009 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3010 * without holding struct_mutex the object may become re-busied before this
3011 * function completes. A similar but shorter * race condition exists in the busy
3015 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3017 struct drm_i915_private *dev_priv = dev->dev_private;
3018 struct drm_i915_gem_wait *args = data;
3019 struct drm_i915_gem_object *obj;
3020 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3021 unsigned reset_counter;
3025 if (args->flags != 0)
3028 ret = i915_mutex_lock_interruptible(dev);
3032 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
3033 if (&obj->base == NULL) {
3034 mutex_unlock(&dev->struct_mutex);
3038 /* Need to make sure the object gets inactive eventually. */
3039 ret = i915_gem_object_flush_active(obj);
3046 /* Do this after OLR check to make sure we make forward progress polling
3047 * on this IOCTL with a timeout == 0 (like busy ioctl)
3049 if (args->timeout_ns == 0) {
3054 drm_gem_object_unreference(&obj->base);
3055 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3057 for (i = 0; i < I915_NUM_RINGS; i++) {
3058 if (obj->last_read_req[i] == NULL)
3061 req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
3064 mutex_unlock(&dev->struct_mutex);
3066 for (i = 0; i < n; i++) {
3068 ret = __i915_wait_request(req[i], reset_counter, true,
3069 args->timeout_ns > 0 ? &args->timeout_ns : NULL,
3071 i915_gem_request_unreference__unlocked(req[i]);
3076 drm_gem_object_unreference(&obj->base);
3077 mutex_unlock(&dev->struct_mutex);
3082 __i915_gem_object_sync(struct drm_i915_gem_object *obj,
3083 struct intel_engine_cs *to,
3084 struct drm_i915_gem_request *from_req,
3085 struct drm_i915_gem_request **to_req)
3087 struct intel_engine_cs *from;
3090 from = i915_gem_request_get_ring(from_req);
3094 if (i915_gem_request_completed(from_req, true))
3097 if (!i915_semaphore_is_enabled(obj->base.dev)) {
3098 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3099 ret = __i915_wait_request(from_req,
3100 atomic_read(&i915->gpu_error.reset_counter),
3101 i915->mm.interruptible,
3103 &i915->rps.semaphores);
3107 i915_gem_object_retire_request(obj, from_req);
3109 int idx = intel_ring_sync_index(from, to);
3110 u32 seqno = i915_gem_request_get_seqno(from_req);
3114 if (seqno <= from->semaphore.sync_seqno[idx])
3117 if (*to_req == NULL) {
3118 ret = i915_gem_request_alloc(to, to->default_context, to_req);
3123 trace_i915_gem_ring_sync_to(*to_req, from, from_req);
3124 ret = to->semaphore.sync_to(*to_req, from, seqno);
3128 /* We use last_read_req because sync_to()
3129 * might have just caused seqno wrap under
3132 from->semaphore.sync_seqno[idx] =
3133 i915_gem_request_get_seqno(obj->last_read_req[from->id]);
3140 * i915_gem_object_sync - sync an object to a ring.
3142 * @obj: object which may be in use on another ring.
3143 * @to: ring we wish to use the object on. May be NULL.
3144 * @to_req: request we wish to use the object for. See below.
3145 * This will be allocated and returned if a request is
3146 * required but not passed in.
3148 * This code is meant to abstract object synchronization with the GPU.
3149 * Calling with NULL implies synchronizing the object with the CPU
3150 * rather than a particular GPU ring. Conceptually we serialise writes
3151 * between engines inside the GPU. We only allow one engine to write
3152 * into a buffer at any time, but multiple readers. To ensure each has
3153 * a coherent view of memory, we must:
3155 * - If there is an outstanding write request to the object, the new
3156 * request must wait for it to complete (either CPU or in hw, requests
3157 * on the same ring will be naturally ordered).
3159 * - If we are a write request (pending_write_domain is set), the new
3160 * request must wait for outstanding read requests to complete.
3162 * For CPU synchronisation (NULL to) no request is required. For syncing with
3163 * rings to_req must be non-NULL. However, a request does not have to be
3164 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3165 * request will be allocated automatically and returned through *to_req. Note
3166 * that it is not guaranteed that commands will be emitted (because the system
3167 * might already be idle). Hence there is no need to create a request that
3168 * might never have any work submitted. Note further that if a request is
3169 * returned in *to_req, it is the responsibility of the caller to submit
3170 * that request (after potentially adding more work to it).
3172 * Returns 0 if successful, else propagates up the lower layer error.
3175 i915_gem_object_sync(struct drm_i915_gem_object *obj,
3176 struct intel_engine_cs *to,
3177 struct drm_i915_gem_request **to_req)
3179 const bool readonly = obj->base.pending_write_domain == 0;
3180 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3187 return i915_gem_object_wait_rendering(obj, readonly);
3191 if (obj->last_write_req)
3192 req[n++] = obj->last_write_req;
3194 for (i = 0; i < I915_NUM_RINGS; i++)
3195 if (obj->last_read_req[i])
3196 req[n++] = obj->last_read_req[i];
3198 for (i = 0; i < n; i++) {
3199 ret = __i915_gem_object_sync(obj, to, req[i], to_req);
3207 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3209 u32 old_write_domain, old_read_domains;
3211 /* Force a pagefault for domain tracking on next user access */
3212 i915_gem_release_mmap(obj);
3214 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3217 /* Wait for any direct GTT access to complete */
3220 old_read_domains = obj->base.read_domains;
3221 old_write_domain = obj->base.write_domain;
3223 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3224 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3226 trace_i915_gem_object_change_domain(obj,
3231 int i915_vma_unbind(struct i915_vma *vma)
3233 struct drm_i915_gem_object *obj = vma->obj;
3234 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3237 if (list_empty(&vma->vma_link))
3240 if (!drm_mm_node_allocated(&vma->node)) {
3241 i915_gem_vma_destroy(vma);
3248 BUG_ON(obj->pages == NULL);
3250 ret = i915_gem_object_wait_rendering(obj, false);
3253 /* Continue on if we fail due to EIO, the GPU is hung so we
3254 * should be safe and we need to cleanup or else we might
3255 * cause memory corruption through use-after-free.
3258 if (i915_is_ggtt(vma->vm) &&
3259 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3260 i915_gem_object_finish_gtt(obj);
3262 /* release the fence reg _after_ flushing */
3263 ret = i915_gem_object_put_fence(obj);
3268 trace_i915_vma_unbind(vma);
3270 vma->vm->unbind_vma(vma);
3273 list_del_init(&vma->mm_list);
3274 if (i915_is_ggtt(vma->vm)) {
3275 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3276 obj->map_and_fenceable = false;
3277 } else if (vma->ggtt_view.pages) {
3278 sg_free_table(vma->ggtt_view.pages);
3279 kfree(vma->ggtt_view.pages);
3280 vma->ggtt_view.pages = NULL;
3284 drm_mm_remove_node(&vma->node);
3285 i915_gem_vma_destroy(vma);
3287 /* Since the unbound list is global, only move to that list if
3288 * no more VMAs exist. */
3289 if (list_empty(&obj->vma_list)) {
3290 i915_gem_gtt_finish_object(obj);
3291 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3294 /* And finally now the object is completely decoupled from this vma,
3295 * we can drop its hold on the backing storage and allow it to be
3296 * reaped by the shrinker.
3298 i915_gem_object_unpin_pages(obj);
3303 int i915_gpu_idle(struct drm_device *dev)
3305 struct drm_i915_private *dev_priv = dev->dev_private;
3306 struct intel_engine_cs *ring;
3309 /* Flush everything onto the inactive list. */
3310 for_each_ring(ring, dev_priv, i) {
3311 if (!i915.enable_execlists) {
3312 struct drm_i915_gem_request *req;
3314 ret = i915_gem_request_alloc(ring, ring->default_context, &req);
3318 ret = i915_switch_context(req);
3320 i915_gem_request_cancel(req);
3324 i915_add_request_no_flush(req);
3327 ret = intel_ring_idle(ring);
3332 WARN_ON(i915_verify_lists(dev));
3336 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3337 struct drm_i915_gem_object *obj)
3339 struct drm_i915_private *dev_priv = dev->dev_private;
3341 int fence_pitch_shift;
3343 if (INTEL_INFO(dev)->gen >= 6) {
3344 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3345 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3347 fence_reg = FENCE_REG_965_0;
3348 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3351 fence_reg += reg * 8;
3353 /* To w/a incoherency with non-atomic 64-bit register updates,
3354 * we split the 64-bit update into two 32-bit writes. In order
3355 * for a partial fence not to be evaluated between writes, we
3356 * precede the update with write to turn off the fence register,
3357 * and only enable the fence as the last step.
3359 * For extra levels of paranoia, we make sure each step lands
3360 * before applying the next step.
3362 I915_WRITE(fence_reg, 0);
3363 POSTING_READ(fence_reg);
3366 u32 size = i915_gem_obj_ggtt_size(obj);
3369 /* Adjust fence size to match tiled area */
3370 if (obj->tiling_mode != I915_TILING_NONE) {
3371 uint32_t row_size = obj->stride *
3372 (obj->tiling_mode == I915_TILING_Y ? 32 : 8);
3373 size = (size / row_size) * row_size;
3376 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3378 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3379 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3380 if (obj->tiling_mode == I915_TILING_Y)
3381 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3382 val |= I965_FENCE_REG_VALID;
3384 I915_WRITE(fence_reg + 4, val >> 32);
3385 POSTING_READ(fence_reg + 4);
3387 I915_WRITE(fence_reg + 0, val);
3388 POSTING_READ(fence_reg);
3390 I915_WRITE(fence_reg + 4, 0);
3391 POSTING_READ(fence_reg + 4);
3395 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3396 struct drm_i915_gem_object *obj)
3398 struct drm_i915_private *dev_priv = dev->dev_private;
3402 u32 size = i915_gem_obj_ggtt_size(obj);
3406 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3407 (size & -size) != size ||
3408 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3409 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3410 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3412 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3417 /* Note: pitch better be a power of two tile widths */
3418 pitch_val = obj->stride / tile_width;
3419 pitch_val = ffs(pitch_val) - 1;
3421 val = i915_gem_obj_ggtt_offset(obj);
3422 if (obj->tiling_mode == I915_TILING_Y)
3423 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3424 val |= I915_FENCE_SIZE_BITS(size);
3425 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3426 val |= I830_FENCE_REG_VALID;
3431 reg = FENCE_REG_830_0 + reg * 4;
3433 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3435 I915_WRITE(reg, val);
3439 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3440 struct drm_i915_gem_object *obj)
3442 struct drm_i915_private *dev_priv = dev->dev_private;
3446 u32 size = i915_gem_obj_ggtt_size(obj);
3449 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3450 (size & -size) != size ||
3451 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3452 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3453 i915_gem_obj_ggtt_offset(obj), size);
3455 pitch_val = obj->stride / 128;
3456 pitch_val = ffs(pitch_val) - 1;
3458 val = i915_gem_obj_ggtt_offset(obj);
3459 if (obj->tiling_mode == I915_TILING_Y)
3460 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3461 val |= I830_FENCE_SIZE_BITS(size);
3462 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3463 val |= I830_FENCE_REG_VALID;
3467 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3468 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3471 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3473 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3476 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3477 struct drm_i915_gem_object *obj)
3479 struct drm_i915_private *dev_priv = dev->dev_private;
3481 /* Ensure that all CPU reads are completed before installing a fence
3482 * and all writes before removing the fence.
3484 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3487 WARN(obj && (!obj->stride || !obj->tiling_mode),
3488 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3489 obj->stride, obj->tiling_mode);
3492 i830_write_fence_reg(dev, reg, obj);
3493 else if (IS_GEN3(dev))
3494 i915_write_fence_reg(dev, reg, obj);
3495 else if (INTEL_INFO(dev)->gen >= 4)
3496 i965_write_fence_reg(dev, reg, obj);
3498 /* And similarly be paranoid that no direct access to this region
3499 * is reordered to before the fence is installed.
3501 if (i915_gem_object_needs_mb(obj))
3505 static inline int fence_number(struct drm_i915_private *dev_priv,
3506 struct drm_i915_fence_reg *fence)
3508 return fence - dev_priv->fence_regs;
3511 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3512 struct drm_i915_fence_reg *fence,
3515 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3516 int reg = fence_number(dev_priv, fence);
3518 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3521 obj->fence_reg = reg;
3523 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3525 obj->fence_reg = I915_FENCE_REG_NONE;
3527 list_del_init(&fence->lru_list);
3529 obj->fence_dirty = false;
3533 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3535 if (obj->last_fenced_req) {
3536 int ret = i915_wait_request(obj->last_fenced_req);
3540 i915_gem_request_assign(&obj->last_fenced_req, NULL);
3547 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3549 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3550 struct drm_i915_fence_reg *fence;
3553 ret = i915_gem_object_wait_fence(obj);
3557 if (obj->fence_reg == I915_FENCE_REG_NONE)
3560 fence = &dev_priv->fence_regs[obj->fence_reg];
3562 if (WARN_ON(fence->pin_count))
3565 i915_gem_object_fence_lost(obj);
3566 i915_gem_object_update_fence(obj, fence, false);
3571 static struct drm_i915_fence_reg *
3572 i915_find_fence_reg(struct drm_device *dev)
3574 struct drm_i915_private *dev_priv = dev->dev_private;
3575 struct drm_i915_fence_reg *reg, *avail;
3578 /* First try to find a free reg */
3580 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3581 reg = &dev_priv->fence_regs[i];
3585 if (!reg->pin_count)
3592 /* None available, try to steal one or wait for a user to finish */
3593 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3601 /* Wait for completion of pending flips which consume fences */
3602 if (intel_has_pending_fb_unpin(dev))
3603 return ERR_PTR(-EAGAIN);
3605 return ERR_PTR(-EDEADLK);
3609 * i915_gem_object_get_fence - set up fencing for an object
3610 * @obj: object to map through a fence reg
3612 * When mapping objects through the GTT, userspace wants to be able to write
3613 * to them without having to worry about swizzling if the object is tiled.
3614 * This function walks the fence regs looking for a free one for @obj,
3615 * stealing one if it can't find any.
3617 * It then sets up the reg based on the object's properties: address, pitch
3618 * and tiling format.
3620 * For an untiled surface, this removes any existing fence.
3623 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3625 struct drm_device *dev = obj->base.dev;
3626 struct drm_i915_private *dev_priv = dev->dev_private;
3627 bool enable = obj->tiling_mode != I915_TILING_NONE;
3628 struct drm_i915_fence_reg *reg;
3631 /* Have we updated the tiling parameters upon the object and so
3632 * will need to serialise the write to the associated fence register?
3634 if (obj->fence_dirty) {
3635 ret = i915_gem_object_wait_fence(obj);
3640 /* Just update our place in the LRU if our fence is getting reused. */
3641 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3642 reg = &dev_priv->fence_regs[obj->fence_reg];
3643 if (!obj->fence_dirty) {
3644 list_move_tail(®->lru_list,
3645 &dev_priv->mm.fence_list);
3648 } else if (enable) {
3649 if (WARN_ON(!obj->map_and_fenceable))
3652 reg = i915_find_fence_reg(dev);
3654 return PTR_ERR(reg);
3657 struct drm_i915_gem_object *old = reg->obj;
3659 ret = i915_gem_object_wait_fence(old);
3663 i915_gem_object_fence_lost(old);
3668 i915_gem_object_update_fence(obj, reg, enable);
3673 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3674 unsigned long cache_level)
3676 struct drm_mm_node *gtt_space = &vma->node;
3677 struct drm_mm_node *other;
3680 * On some machines we have to be careful when putting differing types
3681 * of snoopable memory together to avoid the prefetcher crossing memory
3682 * domains and dying. During vm initialisation, we decide whether or not
3683 * these constraints apply and set the drm_mm.color_adjust
3686 if (vma->vm->mm.color_adjust == NULL)
3689 if (!drm_mm_node_allocated(gtt_space))
3692 if (list_empty(>t_space->node_list))
3695 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3696 if (other->allocated && !other->hole_follows && other->color != cache_level)
3699 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3700 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3707 * Finds free space in the GTT aperture and binds the object or a view of it
3710 static struct i915_vma *
3711 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3712 struct i915_address_space *vm,
3713 const struct i915_ggtt_view *ggtt_view,
3717 struct drm_device *dev = obj->base.dev;
3718 struct drm_i915_private *dev_priv = dev->dev_private;
3719 u32 size, fence_size, fence_alignment, unfenced_alignment;
3721 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3723 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3724 struct i915_vma *vma;
3727 if (i915_is_ggtt(vm)) {
3730 if (WARN_ON(!ggtt_view))
3731 return ERR_PTR(-EINVAL);
3733 view_size = i915_ggtt_view_size(obj, ggtt_view);
3735 fence_size = i915_gem_get_gtt_size(dev,
3738 fence_alignment = i915_gem_get_gtt_alignment(dev,
3742 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3746 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3748 fence_size = i915_gem_get_gtt_size(dev,
3751 fence_alignment = i915_gem_get_gtt_alignment(dev,
3755 unfenced_alignment =
3756 i915_gem_get_gtt_alignment(dev,
3760 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3764 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3766 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3767 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3768 ggtt_view ? ggtt_view->type : 0,
3770 return ERR_PTR(-EINVAL);
3773 /* If binding the object/GGTT view requires more space than the entire
3774 * aperture has, reject it early before evicting everything in a vain
3775 * attempt to find space.
3778 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%llu\n",
3779 ggtt_view ? ggtt_view->type : 0,
3781 flags & PIN_MAPPABLE ? "mappable" : "total",
3783 return ERR_PTR(-E2BIG);
3786 ret = i915_gem_object_get_pages(obj);
3788 return ERR_PTR(ret);
3790 i915_gem_object_pin_pages(obj);
3792 vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3793 i915_gem_obj_lookup_or_create_vma(obj, vm);
3799 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3803 DRM_MM_SEARCH_DEFAULT,
3804 DRM_MM_CREATE_DEFAULT);
3806 ret = i915_gem_evict_something(dev, vm, size, alignment,
3815 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3817 goto err_remove_node;
3820 ret = i915_gem_gtt_prepare_object(obj);
3822 goto err_remove_node;
3824 trace_i915_vma_bind(vma, flags);
3825 ret = i915_vma_bind(vma, obj->cache_level, flags);
3827 goto err_finish_gtt;
3829 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3830 list_add_tail(&vma->mm_list, &vm->inactive_list);
3835 i915_gem_gtt_finish_object(obj);
3837 drm_mm_remove_node(&vma->node);
3839 i915_gem_vma_destroy(vma);
3842 i915_gem_object_unpin_pages(obj);
3847 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3850 /* If we don't have a page list set up, then we're not pinned
3851 * to GPU, and we can ignore the cache flush because it'll happen
3852 * again at bind time.
3854 if (obj->pages == NULL)
3858 * Stolen memory is always coherent with the GPU as it is explicitly
3859 * marked as wc by the system, or the system is cache-coherent.
3861 if (obj->stolen || obj->phys_handle)
3864 /* If the GPU is snooping the contents of the CPU cache,
3865 * we do not need to manually clear the CPU cache lines. However,
3866 * the caches are only snooped when the render cache is
3867 * flushed/invalidated. As we always have to emit invalidations
3868 * and flushes when moving into and out of the RENDER domain, correct
3869 * snooping behaviour occurs naturally as the result of our domain
3872 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3873 obj->cache_dirty = true;
3877 trace_i915_gem_object_clflush(obj);
3878 drm_clflush_sg(obj->pages);
3879 obj->cache_dirty = false;
3884 /** Flushes the GTT write domain for the object if it's dirty. */
3886 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3888 uint32_t old_write_domain;
3890 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3893 /* No actual flushing is required for the GTT write domain. Writes
3894 * to it immediately go to main memory as far as we know, so there's
3895 * no chipset flush. It also doesn't land in render cache.
3897 * However, we do have to enforce the order so that all writes through
3898 * the GTT land before any writes to the device, such as updates to
3903 old_write_domain = obj->base.write_domain;
3904 obj->base.write_domain = 0;
3906 intel_fb_obj_flush(obj, false);
3908 trace_i915_gem_object_change_domain(obj,
3909 obj->base.read_domains,
3913 /** Flushes the CPU write domain for the object if it's dirty. */
3915 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3917 uint32_t old_write_domain;
3919 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3922 if (i915_gem_clflush_object(obj, obj->pin_display))
3923 i915_gem_chipset_flush(obj->base.dev);
3925 old_write_domain = obj->base.write_domain;
3926 obj->base.write_domain = 0;
3928 intel_fb_obj_flush(obj, false);
3930 trace_i915_gem_object_change_domain(obj,
3931 obj->base.read_domains,
3936 * Moves a single object to the GTT read, and possibly write domain.
3938 * This function returns when the move is complete, including waiting on
3942 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3944 uint32_t old_write_domain, old_read_domains;
3945 struct i915_vma *vma;
3948 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3951 ret = i915_gem_object_wait_rendering(obj, !write);
3955 /* Flush and acquire obj->pages so that we are coherent through
3956 * direct access in memory with previous cached writes through
3957 * shmemfs and that our cache domain tracking remains valid.
3958 * For example, if the obj->filp was moved to swap without us
3959 * being notified and releasing the pages, we would mistakenly
3960 * continue to assume that the obj remained out of the CPU cached
3963 ret = i915_gem_object_get_pages(obj);
3967 i915_gem_object_flush_cpu_write_domain(obj);
3969 /* Serialise direct access to this object with the barriers for
3970 * coherent writes from the GPU, by effectively invalidating the
3971 * GTT domain upon first access.
3973 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3976 old_write_domain = obj->base.write_domain;
3977 old_read_domains = obj->base.read_domains;
3979 /* It should now be out of any other write domains, and we can update
3980 * the domain values for our changes.
3982 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3983 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3985 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3986 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3990 trace_i915_gem_object_change_domain(obj,
3994 /* And bump the LRU for this access */
3995 vma = i915_gem_obj_to_ggtt(obj);
3996 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3997 list_move_tail(&vma->mm_list,
3998 &to_i915(obj->base.dev)->gtt.base.inactive_list);
4003 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
4004 enum i915_cache_level cache_level)
4006 struct drm_device *dev = obj->base.dev;
4007 struct i915_vma *vma, *next;
4010 if (obj->cache_level == cache_level)
4013 if (i915_gem_obj_is_pinned(obj)) {
4014 DRM_DEBUG("can not change the cache level of pinned objects\n");
4018 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4019 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
4020 ret = i915_vma_unbind(vma);
4026 if (i915_gem_obj_bound_any(obj)) {
4027 ret = i915_gem_object_wait_rendering(obj, false);
4031 i915_gem_object_finish_gtt(obj);
4033 /* Before SandyBridge, you could not use tiling or fence
4034 * registers with snooped memory, so relinquish any fences
4035 * currently pointing to our region in the aperture.
4037 if (INTEL_INFO(dev)->gen < 6) {
4038 ret = i915_gem_object_put_fence(obj);
4043 list_for_each_entry(vma, &obj->vma_list, vma_link)
4044 if (drm_mm_node_allocated(&vma->node)) {
4045 ret = i915_vma_bind(vma, cache_level,
4052 list_for_each_entry(vma, &obj->vma_list, vma_link)
4053 vma->node.color = cache_level;
4054 obj->cache_level = cache_level;
4056 if (obj->cache_dirty &&
4057 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
4058 cpu_write_needs_clflush(obj)) {
4059 if (i915_gem_clflush_object(obj, true))
4060 i915_gem_chipset_flush(obj->base.dev);
4066 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
4067 struct drm_file *file)
4069 struct drm_i915_gem_caching *args = data;
4070 struct drm_i915_gem_object *obj;
4072 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4073 if (&obj->base == NULL)
4076 switch (obj->cache_level) {
4077 case I915_CACHE_LLC:
4078 case I915_CACHE_L3_LLC:
4079 args->caching = I915_CACHING_CACHED;
4083 args->caching = I915_CACHING_DISPLAY;
4087 args->caching = I915_CACHING_NONE;
4091 drm_gem_object_unreference_unlocked(&obj->base);
4095 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
4096 struct drm_file *file)
4098 struct drm_i915_gem_caching *args = data;
4099 struct drm_i915_gem_object *obj;
4100 enum i915_cache_level level;
4103 switch (args->caching) {
4104 case I915_CACHING_NONE:
4105 level = I915_CACHE_NONE;
4107 case I915_CACHING_CACHED:
4108 level = I915_CACHE_LLC;
4110 case I915_CACHING_DISPLAY:
4111 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
4117 ret = i915_mutex_lock_interruptible(dev);
4121 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4122 if (&obj->base == NULL) {
4127 ret = i915_gem_object_set_cache_level(obj, level);
4129 drm_gem_object_unreference(&obj->base);
4131 mutex_unlock(&dev->struct_mutex);
4136 * Prepare buffer for display plane (scanout, cursors, etc).
4137 * Can be called from an uninterruptible phase (modesetting) and allows
4138 * any flushes to be pipelined (for pageflips).
4141 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
4143 struct intel_engine_cs *pipelined,
4144 struct drm_i915_gem_request **pipelined_request,
4145 const struct i915_ggtt_view *view)
4147 u32 old_read_domains, old_write_domain;
4150 ret = i915_gem_object_sync(obj, pipelined, pipelined_request);
4154 /* Mark the pin_display early so that we account for the
4155 * display coherency whilst setting up the cache domains.
4159 /* The display engine is not coherent with the LLC cache on gen6. As
4160 * a result, we make sure that the pinning that is about to occur is
4161 * done with uncached PTEs. This is lowest common denominator for all
4164 * However for gen6+, we could do better by using the GFDT bit instead
4165 * of uncaching, which would allow us to flush all the LLC-cached data
4166 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4168 ret = i915_gem_object_set_cache_level(obj,
4169 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
4171 goto err_unpin_display;
4173 /* As the user may map the buffer once pinned in the display plane
4174 * (e.g. libkms for the bootup splash), we have to ensure that we
4175 * always use map_and_fenceable for all scanout buffers.
4177 ret = i915_gem_object_ggtt_pin(obj, view, alignment,
4178 view->type == I915_GGTT_VIEW_NORMAL ?
4181 goto err_unpin_display;
4183 i915_gem_object_flush_cpu_write_domain(obj);
4185 old_write_domain = obj->base.write_domain;
4186 old_read_domains = obj->base.read_domains;
4188 /* It should now be out of any other write domains, and we can update
4189 * the domain values for our changes.
4191 obj->base.write_domain = 0;
4192 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4194 trace_i915_gem_object_change_domain(obj,
4206 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
4207 const struct i915_ggtt_view *view)
4209 if (WARN_ON(obj->pin_display == 0))
4212 i915_gem_object_ggtt_unpin_view(obj, view);
4218 * Moves a single object to the CPU read, and possibly write domain.
4220 * This function returns when the move is complete, including waiting on
4224 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4226 uint32_t old_write_domain, old_read_domains;
4229 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4232 ret = i915_gem_object_wait_rendering(obj, !write);
4236 i915_gem_object_flush_gtt_write_domain(obj);
4238 old_write_domain = obj->base.write_domain;
4239 old_read_domains = obj->base.read_domains;
4241 /* Flush the CPU cache if it's still invalid. */
4242 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4243 i915_gem_clflush_object(obj, false);
4245 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4248 /* It should now be out of any other write domains, and we can update
4249 * the domain values for our changes.
4251 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4253 /* If we're writing through the CPU, then the GPU read domains will
4254 * need to be invalidated at next use.
4257 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4258 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4261 trace_i915_gem_object_change_domain(obj,
4268 /* Throttle our rendering by waiting until the ring has completed our requests
4269 * emitted over 20 msec ago.
4271 * Note that if we were to use the current jiffies each time around the loop,
4272 * we wouldn't escape the function with any frames outstanding if the time to
4273 * render a frame was over 20ms.
4275 * This should get us reasonable parallelism between CPU and GPU but also
4276 * relatively low latency when blocking on a particular request to finish.
4279 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4281 struct drm_i915_private *dev_priv = dev->dev_private;
4282 struct drm_i915_file_private *file_priv = file->driver_priv;
4283 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4284 struct drm_i915_gem_request *request, *target = NULL;
4285 unsigned reset_counter;
4288 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4292 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4296 spin_lock(&file_priv->mm.lock);
4297 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4298 if (time_after_eq(request->emitted_jiffies, recent_enough))
4302 * Note that the request might not have been submitted yet.
4303 * In which case emitted_jiffies will be zero.
4305 if (!request->emitted_jiffies)
4310 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4312 i915_gem_request_reference(target);
4313 spin_unlock(&file_priv->mm.lock);
4318 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4320 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4322 i915_gem_request_unreference__unlocked(target);
4328 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4330 struct drm_i915_gem_object *obj = vma->obj;
4333 vma->node.start & (alignment - 1))
4336 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4339 if (flags & PIN_OFFSET_BIAS &&
4340 vma->node.start < (flags & PIN_OFFSET_MASK))
4347 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4348 struct i915_address_space *vm,
4349 const struct i915_ggtt_view *ggtt_view,
4353 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4354 struct i915_vma *vma;
4358 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4361 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4364 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4367 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4370 vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4371 i915_gem_obj_to_vma(obj, vm);
4374 return PTR_ERR(vma);
4377 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4380 if (i915_vma_misplaced(vma, alignment, flags)) {
4381 unsigned long offset;
4382 offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) :
4383 i915_gem_obj_offset(obj, vm);
4384 WARN(vma->pin_count,
4385 "bo is already pinned in %s with incorrect alignment:"
4386 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4387 " obj->map_and_fenceable=%d\n",
4388 ggtt_view ? "ggtt" : "ppgtt",
4391 !!(flags & PIN_MAPPABLE),
4392 obj->map_and_fenceable);
4393 ret = i915_vma_unbind(vma);
4401 bound = vma ? vma->bound : 0;
4402 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4403 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4406 return PTR_ERR(vma);
4408 ret = i915_vma_bind(vma, obj->cache_level, flags);
4413 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4414 (bound ^ vma->bound) & GLOBAL_BIND) {
4415 bool mappable, fenceable;
4416 u32 fence_size, fence_alignment;
4418 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4421 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4426 fenceable = (vma->node.size == fence_size &&
4427 (vma->node.start & (fence_alignment - 1)) == 0);
4429 mappable = (vma->node.start + fence_size <=
4430 dev_priv->gtt.mappable_end);
4432 obj->map_and_fenceable = mappable && fenceable;
4434 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4442 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4443 struct i915_address_space *vm,
4447 return i915_gem_object_do_pin(obj, vm,
4448 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4453 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4454 const struct i915_ggtt_view *view,
4458 if (WARN_ONCE(!view, "no view specified"))
4461 return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view,
4462 alignment, flags | PIN_GLOBAL);
4466 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4467 const struct i915_ggtt_view *view)
4469 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4472 WARN_ON(vma->pin_count == 0);
4473 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4479 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4481 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4482 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4483 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4485 WARN_ON(!ggtt_vma ||
4486 dev_priv->fence_regs[obj->fence_reg].pin_count >
4487 ggtt_vma->pin_count);
4488 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4495 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4497 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4498 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4499 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4500 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4505 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4506 struct drm_file *file)
4508 struct drm_i915_gem_busy *args = data;
4509 struct drm_i915_gem_object *obj;
4512 ret = i915_mutex_lock_interruptible(dev);
4516 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4517 if (&obj->base == NULL) {
4522 /* Count all active objects as busy, even if they are currently not used
4523 * by the gpu. Users of this interface expect objects to eventually
4524 * become non-busy without any further actions, therefore emit any
4525 * necessary flushes here.
4527 ret = i915_gem_object_flush_active(obj);
4531 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4532 args->busy = obj->active << 16;
4533 if (obj->last_write_req)
4534 args->busy |= obj->last_write_req->ring->id;
4537 drm_gem_object_unreference(&obj->base);
4539 mutex_unlock(&dev->struct_mutex);
4544 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4545 struct drm_file *file_priv)
4547 return i915_gem_ring_throttle(dev, file_priv);
4551 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4552 struct drm_file *file_priv)
4554 struct drm_i915_private *dev_priv = dev->dev_private;
4555 struct drm_i915_gem_madvise *args = data;
4556 struct drm_i915_gem_object *obj;
4559 switch (args->madv) {
4560 case I915_MADV_DONTNEED:
4561 case I915_MADV_WILLNEED:
4567 ret = i915_mutex_lock_interruptible(dev);
4571 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4572 if (&obj->base == NULL) {
4577 if (i915_gem_obj_is_pinned(obj)) {
4583 obj->tiling_mode != I915_TILING_NONE &&
4584 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4585 if (obj->madv == I915_MADV_WILLNEED)
4586 i915_gem_object_unpin_pages(obj);
4587 if (args->madv == I915_MADV_WILLNEED)
4588 i915_gem_object_pin_pages(obj);
4591 if (obj->madv != __I915_MADV_PURGED)
4592 obj->madv = args->madv;
4594 /* if the object is no longer attached, discard its backing storage */
4595 if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4596 i915_gem_object_truncate(obj);
4598 args->retained = obj->madv != __I915_MADV_PURGED;
4601 drm_gem_object_unreference(&obj->base);
4603 mutex_unlock(&dev->struct_mutex);
4607 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4608 const struct drm_i915_gem_object_ops *ops)
4612 INIT_LIST_HEAD(&obj->global_list);
4613 for (i = 0; i < I915_NUM_RINGS; i++)
4614 INIT_LIST_HEAD(&obj->ring_list[i]);
4615 INIT_LIST_HEAD(&obj->obj_exec_link);
4616 INIT_LIST_HEAD(&obj->vma_list);
4617 INIT_LIST_HEAD(&obj->batch_pool_link);
4621 obj->fence_reg = I915_FENCE_REG_NONE;
4622 obj->madv = I915_MADV_WILLNEED;
4624 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4627 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4628 .get_pages = i915_gem_object_get_pages_gtt,
4629 .put_pages = i915_gem_object_put_pages_gtt,
4632 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4635 struct drm_i915_gem_object *obj;
4636 struct address_space *mapping;
4639 obj = i915_gem_object_alloc(dev);
4643 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4644 i915_gem_object_free(obj);
4648 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4649 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4650 /* 965gm cannot relocate objects above 4GiB. */
4651 mask &= ~__GFP_HIGHMEM;
4652 mask |= __GFP_DMA32;
4655 mapping = file_inode(obj->base.filp)->i_mapping;
4656 mapping_set_gfp_mask(mapping, mask);
4658 i915_gem_object_init(obj, &i915_gem_object_ops);
4660 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4661 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4664 /* On some devices, we can have the GPU use the LLC (the CPU
4665 * cache) for about a 10% performance improvement
4666 * compared to uncached. Graphics requests other than
4667 * display scanout are coherent with the CPU in
4668 * accessing this cache. This means in this mode we
4669 * don't need to clflush on the CPU side, and on the
4670 * GPU side we only need to flush internal caches to
4671 * get data visible to the CPU.
4673 * However, we maintain the display planes as UC, and so
4674 * need to rebind when first used as such.
4676 obj->cache_level = I915_CACHE_LLC;
4678 obj->cache_level = I915_CACHE_NONE;
4680 trace_i915_gem_object_create(obj);
4685 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4687 /* If we are the last user of the backing storage (be it shmemfs
4688 * pages or stolen etc), we know that the pages are going to be
4689 * immediately released. In this case, we can then skip copying
4690 * back the contents from the GPU.
4693 if (obj->madv != I915_MADV_WILLNEED)
4696 if (obj->base.filp == NULL)
4699 /* At first glance, this looks racy, but then again so would be
4700 * userspace racing mmap against close. However, the first external
4701 * reference to the filp can only be obtained through the
4702 * i915_gem_mmap_ioctl() which safeguards us against the user
4703 * acquiring such a reference whilst we are in the middle of
4704 * freeing the object.
4706 return atomic_long_read(&obj->base.filp->f_count) == 1;
4709 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4711 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4712 struct drm_device *dev = obj->base.dev;
4713 struct drm_i915_private *dev_priv = dev->dev_private;
4714 struct i915_vma *vma, *next;
4716 intel_runtime_pm_get(dev_priv);
4718 trace_i915_gem_object_destroy(obj);
4720 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4724 ret = i915_vma_unbind(vma);
4725 if (WARN_ON(ret == -ERESTARTSYS)) {
4726 bool was_interruptible;
4728 was_interruptible = dev_priv->mm.interruptible;
4729 dev_priv->mm.interruptible = false;
4731 WARN_ON(i915_vma_unbind(vma));
4733 dev_priv->mm.interruptible = was_interruptible;
4737 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4738 * before progressing. */
4740 i915_gem_object_unpin_pages(obj);
4742 WARN_ON(obj->frontbuffer_bits);
4744 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4745 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4746 obj->tiling_mode != I915_TILING_NONE)
4747 i915_gem_object_unpin_pages(obj);
4749 if (WARN_ON(obj->pages_pin_count))
4750 obj->pages_pin_count = 0;
4751 if (discard_backing_storage(obj))
4752 obj->madv = I915_MADV_DONTNEED;
4753 i915_gem_object_put_pages(obj);
4754 i915_gem_object_free_mmap_offset(obj);
4758 if (obj->base.import_attach)
4759 drm_prime_gem_destroy(&obj->base, NULL);
4761 if (obj->ops->release)
4762 obj->ops->release(obj);
4764 drm_gem_object_release(&obj->base);
4765 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4768 i915_gem_object_free(obj);
4770 intel_runtime_pm_put(dev_priv);
4773 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4774 struct i915_address_space *vm)
4776 struct i915_vma *vma;
4777 list_for_each_entry(vma, &obj->vma_list, vma_link) {
4778 if (i915_is_ggtt(vma->vm) &&
4779 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
4787 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4788 const struct i915_ggtt_view *view)
4790 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
4791 struct i915_vma *vma;
4793 if (WARN_ONCE(!view, "no view specified"))
4794 return ERR_PTR(-EINVAL);
4796 list_for_each_entry(vma, &obj->vma_list, vma_link)
4797 if (vma->vm == ggtt &&
4798 i915_ggtt_view_equal(&vma->ggtt_view, view))
4803 void i915_gem_vma_destroy(struct i915_vma *vma)
4805 struct i915_address_space *vm = NULL;
4806 WARN_ON(vma->node.allocated);
4808 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4809 if (!list_empty(&vma->exec_list))
4814 if (!i915_is_ggtt(vm))
4815 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4817 list_del(&vma->vma_link);
4819 kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4823 i915_gem_stop_ringbuffers(struct drm_device *dev)
4825 struct drm_i915_private *dev_priv = dev->dev_private;
4826 struct intel_engine_cs *ring;
4829 for_each_ring(ring, dev_priv, i)
4830 dev_priv->gt.stop_ring(ring);
4834 i915_gem_suspend(struct drm_device *dev)
4836 struct drm_i915_private *dev_priv = dev->dev_private;
4839 mutex_lock(&dev->struct_mutex);
4840 ret = i915_gpu_idle(dev);
4844 i915_gem_retire_requests(dev);
4846 i915_gem_stop_ringbuffers(dev);
4847 mutex_unlock(&dev->struct_mutex);
4849 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4850 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4851 flush_delayed_work(&dev_priv->mm.idle_work);
4853 /* Assert that we sucessfully flushed all the work and
4854 * reset the GPU back to its idle, low power state.
4856 WARN_ON(dev_priv->mm.busy);
4861 mutex_unlock(&dev->struct_mutex);
4865 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
4867 struct intel_engine_cs *ring = req->ring;
4868 struct drm_device *dev = ring->dev;
4869 struct drm_i915_private *dev_priv = dev->dev_private;
4870 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4871 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4874 if (!HAS_L3_DPF(dev) || !remap_info)
4877 ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);
4882 * Note: We do not worry about the concurrent register cacheline hang
4883 * here because no other code should access these registers other than
4884 * at initialization time.
4886 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4887 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4888 intel_ring_emit(ring, reg_base + i);
4889 intel_ring_emit(ring, remap_info[i/4]);
4892 intel_ring_advance(ring);
4897 void i915_gem_init_swizzling(struct drm_device *dev)
4899 struct drm_i915_private *dev_priv = dev->dev_private;
4901 if (INTEL_INFO(dev)->gen < 5 ||
4902 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4905 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4906 DISP_TILE_SURFACE_SWIZZLING);
4911 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4913 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4914 else if (IS_GEN7(dev))
4915 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4916 else if (IS_GEN8(dev))
4917 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4923 intel_enable_blt(struct drm_device *dev)
4928 /* The blitter was dysfunctional on early prototypes */
4929 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4930 DRM_INFO("BLT not supported on this pre-production hardware;"
4931 " graphics performance will be degraded.\n");
4938 static void init_unused_ring(struct drm_device *dev, u32 base)
4940 struct drm_i915_private *dev_priv = dev->dev_private;
4942 I915_WRITE(RING_CTL(base), 0);
4943 I915_WRITE(RING_HEAD(base), 0);
4944 I915_WRITE(RING_TAIL(base), 0);
4945 I915_WRITE(RING_START(base), 0);
4948 static void init_unused_rings(struct drm_device *dev)
4951 init_unused_ring(dev, PRB1_BASE);
4952 init_unused_ring(dev, SRB0_BASE);
4953 init_unused_ring(dev, SRB1_BASE);
4954 init_unused_ring(dev, SRB2_BASE);
4955 init_unused_ring(dev, SRB3_BASE);
4956 } else if (IS_GEN2(dev)) {
4957 init_unused_ring(dev, SRB0_BASE);
4958 init_unused_ring(dev, SRB1_BASE);
4959 } else if (IS_GEN3(dev)) {
4960 init_unused_ring(dev, PRB1_BASE);
4961 init_unused_ring(dev, PRB2_BASE);
4965 int i915_gem_init_rings(struct drm_device *dev)
4967 struct drm_i915_private *dev_priv = dev->dev_private;
4970 ret = intel_init_render_ring_buffer(dev);
4975 ret = intel_init_bsd_ring_buffer(dev);
4977 goto cleanup_render_ring;
4980 if (intel_enable_blt(dev)) {
4981 ret = intel_init_blt_ring_buffer(dev);
4983 goto cleanup_bsd_ring;
4986 if (HAS_VEBOX(dev)) {
4987 ret = intel_init_vebox_ring_buffer(dev);
4989 goto cleanup_blt_ring;
4992 if (HAS_BSD2(dev)) {
4993 ret = intel_init_bsd2_ring_buffer(dev);
4995 goto cleanup_vebox_ring;
4998 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
5000 goto cleanup_bsd2_ring;
5005 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
5007 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
5009 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
5011 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
5012 cleanup_render_ring:
5013 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
5019 i915_gem_init_hw(struct drm_device *dev)
5021 struct drm_i915_private *dev_priv = dev->dev_private;
5022 struct intel_engine_cs *ring;
5025 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
5028 /* Double layer security blanket, see i915_gem_init() */
5029 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5031 if (dev_priv->ellc_size)
5032 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
5034 if (IS_HASWELL(dev))
5035 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
5036 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
5038 if (HAS_PCH_NOP(dev)) {
5039 if (IS_IVYBRIDGE(dev)) {
5040 u32 temp = I915_READ(GEN7_MSG_CTL);
5041 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
5042 I915_WRITE(GEN7_MSG_CTL, temp);
5043 } else if (INTEL_INFO(dev)->gen >= 7) {
5044 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
5045 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
5046 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
5050 i915_gem_init_swizzling(dev);
5053 * At least 830 can leave some of the unused rings
5054 * "active" (ie. head != tail) after resume which
5055 * will prevent c3 entry. Makes sure all unused rings
5058 init_unused_rings(dev);
5060 BUG_ON(!dev_priv->ring[RCS].default_context);
5062 ret = i915_ppgtt_init_hw(dev);
5064 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
5068 /* Need to do basic initialisation of all rings first: */
5069 for_each_ring(ring, dev_priv, i) {
5070 ret = ring->init_hw(ring);
5075 /* Now it is safe to go back round and do everything else: */
5076 for_each_ring(ring, dev_priv, i) {
5077 struct drm_i915_gem_request *req;
5079 WARN_ON(!ring->default_context);
5081 ret = i915_gem_request_alloc(ring, ring->default_context, &req);
5083 i915_gem_cleanup_ringbuffer(dev);
5087 if (ring->id == RCS) {
5088 for (j = 0; j < NUM_L3_SLICES(dev); j++)
5089 i915_gem_l3_remap(req, j);
5092 ret = i915_ppgtt_init_ring(req);
5093 if (ret && ret != -EIO) {
5094 DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret);
5095 i915_gem_request_cancel(req);
5096 i915_gem_cleanup_ringbuffer(dev);
5100 ret = i915_gem_context_enable(req);
5101 if (ret && ret != -EIO) {
5102 DRM_ERROR("Context enable ring #%d failed %d\n", i, ret);
5103 i915_gem_request_cancel(req);
5104 i915_gem_cleanup_ringbuffer(dev);
5108 i915_add_request_no_flush(req);
5112 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5116 int i915_gem_init(struct drm_device *dev)
5118 struct drm_i915_private *dev_priv = dev->dev_private;
5121 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
5122 i915.enable_execlists);
5124 mutex_lock(&dev->struct_mutex);
5126 if (IS_VALLEYVIEW(dev)) {
5127 /* VLVA0 (potential hack), BIOS isn't actually waking us */
5128 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
5129 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
5130 VLV_GTLC_ALLOWWAKEACK), 10))
5131 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
5134 if (!i915.enable_execlists) {
5135 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
5136 dev_priv->gt.init_rings = i915_gem_init_rings;
5137 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
5138 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
5140 dev_priv->gt.execbuf_submit = intel_execlists_submission;
5141 dev_priv->gt.init_rings = intel_logical_rings_init;
5142 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
5143 dev_priv->gt.stop_ring = intel_logical_ring_stop;
5146 /* This is just a security blanket to placate dragons.
5147 * On some systems, we very sporadically observe that the first TLBs
5148 * used by the CS may be stale, despite us poking the TLB reset. If
5149 * we hold the forcewake during initialisation these problems
5150 * just magically go away.
5152 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5154 ret = i915_gem_init_userptr(dev);
5158 i915_gem_init_global_gtt(dev);
5160 ret = i915_gem_context_init(dev);
5164 ret = dev_priv->gt.init_rings(dev);
5168 ret = i915_gem_init_hw(dev);
5170 /* Allow ring initialisation to fail by marking the GPU as
5171 * wedged. But we only want to do this where the GPU is angry,
5172 * for all other failure, such as an allocation failure, bail.
5174 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5175 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
5180 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5181 mutex_unlock(&dev->struct_mutex);
5187 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190 struct intel_engine_cs *ring;
5193 for_each_ring(ring, dev_priv, i)
5194 dev_priv->gt.cleanup_ring(ring);
5198 init_ring_lists(struct intel_engine_cs *ring)
5200 INIT_LIST_HEAD(&ring->active_list);
5201 INIT_LIST_HEAD(&ring->request_list);
5204 void i915_init_vm(struct drm_i915_private *dev_priv,
5205 struct i915_address_space *vm)
5207 if (!i915_is_ggtt(vm))
5208 drm_mm_init(&vm->mm, vm->start, vm->total);
5209 vm->dev = dev_priv->dev;
5210 INIT_LIST_HEAD(&vm->active_list);
5211 INIT_LIST_HEAD(&vm->inactive_list);
5212 INIT_LIST_HEAD(&vm->global_link);
5213 list_add_tail(&vm->global_link, &dev_priv->vm_list);
5217 i915_gem_load(struct drm_device *dev)
5219 struct drm_i915_private *dev_priv = dev->dev_private;
5223 kmem_cache_create("i915_gem_object",
5224 sizeof(struct drm_i915_gem_object), 0,
5228 kmem_cache_create("i915_gem_vma",
5229 sizeof(struct i915_vma), 0,
5232 dev_priv->requests =
5233 kmem_cache_create("i915_gem_request",
5234 sizeof(struct drm_i915_gem_request), 0,
5238 INIT_LIST_HEAD(&dev_priv->vm_list);
5239 i915_init_vm(dev_priv, &dev_priv->gtt.base);
5241 INIT_LIST_HEAD(&dev_priv->context_list);
5242 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5243 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5244 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5245 for (i = 0; i < I915_NUM_RINGS; i++)
5246 init_ring_lists(&dev_priv->ring[i]);
5247 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5248 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5249 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5250 i915_gem_retire_work_handler);
5251 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5252 i915_gem_idle_work_handler);
5253 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5255 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5257 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5258 dev_priv->num_fence_regs = 32;
5259 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5260 dev_priv->num_fence_regs = 16;
5262 dev_priv->num_fence_regs = 8;
5264 if (intel_vgpu_active(dev))
5265 dev_priv->num_fence_regs =
5266 I915_READ(vgtif_reg(avail_rs.fence_num));
5268 /* Initialize fence registers to zero */
5269 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5270 i915_gem_restore_fences(dev);
5272 i915_gem_detect_bit_6_swizzle(dev);
5273 init_waitqueue_head(&dev_priv->pending_flip_queue);
5275 dev_priv->mm.interruptible = true;
5277 i915_gem_shrinker_init(dev_priv);
5279 mutex_init(&dev_priv->fb_tracking.lock);
5282 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5284 struct drm_i915_file_private *file_priv = file->driver_priv;
5286 /* Clean up our request list when the client is going away, so that
5287 * later retire_requests won't dereference our soon-to-be-gone
5290 spin_lock(&file_priv->mm.lock);
5291 while (!list_empty(&file_priv->mm.request_list)) {
5292 struct drm_i915_gem_request *request;
5294 request = list_first_entry(&file_priv->mm.request_list,
5295 struct drm_i915_gem_request,
5297 list_del(&request->client_list);
5298 request->file_priv = NULL;
5300 spin_unlock(&file_priv->mm.lock);
5302 if (!list_empty(&file_priv->rps.link)) {
5303 spin_lock(&to_i915(dev)->rps.client_lock);
5304 list_del(&file_priv->rps.link);
5305 spin_unlock(&to_i915(dev)->rps.client_lock);
5309 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5311 struct drm_i915_file_private *file_priv;
5314 DRM_DEBUG_DRIVER("\n");
5316 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5320 file->driver_priv = file_priv;
5321 file_priv->dev_priv = dev->dev_private;
5322 file_priv->file = file;
5323 INIT_LIST_HEAD(&file_priv->rps.link);
5325 spin_lock_init(&file_priv->mm.lock);
5326 INIT_LIST_HEAD(&file_priv->mm.request_list);
5328 ret = i915_gem_context_open(dev, file);
5336 * i915_gem_track_fb - update frontbuffer tracking
5337 * old: current GEM buffer for the frontbuffer slots
5338 * new: new GEM buffer for the frontbuffer slots
5339 * frontbuffer_bits: bitmask of frontbuffer slots
5341 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5342 * from @old and setting them in @new. Both @old and @new can be NULL.
5344 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5345 struct drm_i915_gem_object *new,
5346 unsigned frontbuffer_bits)
5349 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5350 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5351 old->frontbuffer_bits &= ~frontbuffer_bits;
5355 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5356 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5357 new->frontbuffer_bits |= frontbuffer_bits;
5361 /* All the new VM stuff */
5363 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5364 struct i915_address_space *vm)
5366 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5367 struct i915_vma *vma;
5369 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5371 list_for_each_entry(vma, &o->vma_list, vma_link) {
5372 if (i915_is_ggtt(vma->vm) &&
5373 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5376 return vma->node.start;
5379 WARN(1, "%s vma for this object not found.\n",
5380 i915_is_ggtt(vm) ? "global" : "ppgtt");
5385 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5386 const struct i915_ggtt_view *view)
5388 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5389 struct i915_vma *vma;
5391 list_for_each_entry(vma, &o->vma_list, vma_link)
5392 if (vma->vm == ggtt &&
5393 i915_ggtt_view_equal(&vma->ggtt_view, view))
5394 return vma->node.start;
5396 WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5400 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5401 struct i915_address_space *vm)
5403 struct i915_vma *vma;
5405 list_for_each_entry(vma, &o->vma_list, vma_link) {
5406 if (i915_is_ggtt(vma->vm) &&
5407 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5409 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5416 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5417 const struct i915_ggtt_view *view)
5419 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5420 struct i915_vma *vma;
5422 list_for_each_entry(vma, &o->vma_list, vma_link)
5423 if (vma->vm == ggtt &&
5424 i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5425 drm_mm_node_allocated(&vma->node))
5431 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5433 struct i915_vma *vma;
5435 list_for_each_entry(vma, &o->vma_list, vma_link)
5436 if (drm_mm_node_allocated(&vma->node))
5442 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5443 struct i915_address_space *vm)
5445 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5446 struct i915_vma *vma;
5448 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5450 BUG_ON(list_empty(&o->vma_list));
5452 list_for_each_entry(vma, &o->vma_list, vma_link) {
5453 if (i915_is_ggtt(vma->vm) &&
5454 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5457 return vma->node.size;
5462 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5464 struct i915_vma *vma;
5465 list_for_each_entry(vma, &obj->vma_list, vma_link)
5466 if (vma->pin_count > 0)