2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
43 bool map_and_fenceable,
45 static int i915_gem_phys_pwrite(struct drm_device *dev,
46 struct drm_i915_gem_object *obj,
47 struct drm_i915_gem_pwrite *args,
48 struct drm_file *file);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
65 i915_gem_release_mmap(obj);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj->fence_dirty = false;
71 obj->fence_reg = I915_FENCE_REG_NONE;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
78 dev_priv->mm.object_count++;
79 dev_priv->mm.object_memory += size;
82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
85 dev_priv->mm.object_count--;
86 dev_priv->mm.object_memory -= size;
90 i915_gem_wait_for_error(struct i915_gpu_error *error)
94 #define EXIT_COND (!i915_reset_in_progress(error) || \
95 i915_terminally_wedged(error))
100 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
101 * userspace. If it takes that long something really bad is going on and
102 * we should simply try to bail out and fail as gracefully as possible.
104 ret = wait_event_interruptible_timeout(error->reset_queue,
108 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
110 } else if (ret < 0) {
118 int i915_mutex_lock_interruptible(struct drm_device *dev)
120 struct drm_i915_private *dev_priv = dev->dev_private;
123 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
127 ret = mutex_lock_interruptible(&dev->struct_mutex);
131 WARN_ON(i915_verify_lists(dev));
136 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
138 return i915_gem_obj_ggtt_bound(obj) && !obj->active;
142 i915_gem_init_ioctl(struct drm_device *dev, void *data,
143 struct drm_file *file)
145 struct drm_i915_private *dev_priv = dev->dev_private;
146 struct drm_i915_gem_init *args = data;
148 if (drm_core_check_feature(dev, DRIVER_MODESET))
151 if (args->gtt_start >= args->gtt_end ||
152 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
155 /* GEM with user mode setting was never supported on ilk and later. */
156 if (INTEL_INFO(dev)->gen >= 5)
159 mutex_lock(&dev->struct_mutex);
160 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
162 dev_priv->gtt.mappable_end = args->gtt_end;
163 mutex_unlock(&dev->struct_mutex);
169 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
170 struct drm_file *file)
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct drm_i915_gem_get_aperture *args = data;
174 struct drm_i915_gem_object *obj;
178 mutex_lock(&dev->struct_mutex);
179 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
181 pinned += i915_gem_obj_ggtt_size(obj);
182 mutex_unlock(&dev->struct_mutex);
184 args->aper_size = dev_priv->gtt.total;
185 args->aper_available_size = args->aper_size - pinned;
190 void *i915_gem_object_alloc(struct drm_device *dev)
192 struct drm_i915_private *dev_priv = dev->dev_private;
193 return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
196 void i915_gem_object_free(struct drm_i915_gem_object *obj)
198 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
199 kmem_cache_free(dev_priv->slab, obj);
203 i915_gem_create(struct drm_file *file,
204 struct drm_device *dev,
208 struct drm_i915_gem_object *obj;
212 size = roundup(size, PAGE_SIZE);
216 /* Allocate the new object */
217 obj = i915_gem_alloc_object(dev, size);
221 ret = drm_gem_handle_create(file, &obj->base, &handle);
223 drm_gem_object_release(&obj->base);
224 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
225 i915_gem_object_free(obj);
229 /* drop reference from allocate - handle holds it now */
230 drm_gem_object_unreference(&obj->base);
231 trace_i915_gem_object_create(obj);
238 i915_gem_dumb_create(struct drm_file *file,
239 struct drm_device *dev,
240 struct drm_mode_create_dumb *args)
242 /* have to work out size/pitch and return them */
243 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
244 args->size = args->pitch * args->height;
245 return i915_gem_create(file, dev,
246 args->size, &args->handle);
249 int i915_gem_dumb_destroy(struct drm_file *file,
250 struct drm_device *dev,
253 return drm_gem_handle_delete(file, handle);
257 * Creates a new mm object and returns a handle to it.
260 i915_gem_create_ioctl(struct drm_device *dev, void *data,
261 struct drm_file *file)
263 struct drm_i915_gem_create *args = data;
265 return i915_gem_create(file, dev,
266 args->size, &args->handle);
270 __copy_to_user_swizzled(char __user *cpu_vaddr,
271 const char *gpu_vaddr, int gpu_offset,
274 int ret, cpu_offset = 0;
277 int cacheline_end = ALIGN(gpu_offset + 1, 64);
278 int this_length = min(cacheline_end - gpu_offset, length);
279 int swizzled_gpu_offset = gpu_offset ^ 64;
281 ret = __copy_to_user(cpu_vaddr + cpu_offset,
282 gpu_vaddr + swizzled_gpu_offset,
287 cpu_offset += this_length;
288 gpu_offset += this_length;
289 length -= this_length;
296 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
297 const char __user *cpu_vaddr,
300 int ret, cpu_offset = 0;
303 int cacheline_end = ALIGN(gpu_offset + 1, 64);
304 int this_length = min(cacheline_end - gpu_offset, length);
305 int swizzled_gpu_offset = gpu_offset ^ 64;
307 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
308 cpu_vaddr + cpu_offset,
313 cpu_offset += this_length;
314 gpu_offset += this_length;
315 length -= this_length;
321 /* Per-page copy function for the shmem pread fastpath.
322 * Flushes invalid cachelines before reading the target if
323 * needs_clflush is set. */
325 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
326 char __user *user_data,
327 bool page_do_bit17_swizzling, bool needs_clflush)
332 if (unlikely(page_do_bit17_swizzling))
335 vaddr = kmap_atomic(page);
337 drm_clflush_virt_range(vaddr + shmem_page_offset,
339 ret = __copy_to_user_inatomic(user_data,
340 vaddr + shmem_page_offset,
342 kunmap_atomic(vaddr);
344 return ret ? -EFAULT : 0;
348 shmem_clflush_swizzled_range(char *addr, unsigned long length,
351 if (unlikely(swizzled)) {
352 unsigned long start = (unsigned long) addr;
353 unsigned long end = (unsigned long) addr + length;
355 /* For swizzling simply ensure that we always flush both
356 * channels. Lame, but simple and it works. Swizzled
357 * pwrite/pread is far from a hotpath - current userspace
358 * doesn't use it at all. */
359 start = round_down(start, 128);
360 end = round_up(end, 128);
362 drm_clflush_virt_range((void *)start, end - start);
364 drm_clflush_virt_range(addr, length);
369 /* Only difference to the fast-path function is that this can handle bit17
370 * and uses non-atomic copy and kmap functions. */
372 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
373 char __user *user_data,
374 bool page_do_bit17_swizzling, bool needs_clflush)
381 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
383 page_do_bit17_swizzling);
385 if (page_do_bit17_swizzling)
386 ret = __copy_to_user_swizzled(user_data,
387 vaddr, shmem_page_offset,
390 ret = __copy_to_user(user_data,
391 vaddr + shmem_page_offset,
395 return ret ? - EFAULT : 0;
399 i915_gem_shmem_pread(struct drm_device *dev,
400 struct drm_i915_gem_object *obj,
401 struct drm_i915_gem_pread *args,
402 struct drm_file *file)
404 char __user *user_data;
407 int shmem_page_offset, page_length, ret = 0;
408 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
410 int needs_clflush = 0;
411 struct sg_page_iter sg_iter;
413 user_data = to_user_ptr(args->data_ptr);
416 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
418 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
419 /* If we're not in the cpu read domain, set ourself into the gtt
420 * read domain and manually flush cachelines (if required). This
421 * optimizes for the case when the gpu will dirty the data
422 * anyway again before the next pread happens. */
423 if (obj->cache_level == I915_CACHE_NONE)
425 if (i915_gem_obj_ggtt_bound(obj)) {
426 ret = i915_gem_object_set_to_gtt_domain(obj, false);
432 ret = i915_gem_object_get_pages(obj);
436 i915_gem_object_pin_pages(obj);
438 offset = args->offset;
440 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
441 offset >> PAGE_SHIFT) {
442 struct page *page = sg_page_iter_page(&sg_iter);
447 /* Operation in this page
449 * shmem_page_offset = offset within page in shmem file
450 * page_length = bytes to copy for this page
452 shmem_page_offset = offset_in_page(offset);
453 page_length = remain;
454 if ((shmem_page_offset + page_length) > PAGE_SIZE)
455 page_length = PAGE_SIZE - shmem_page_offset;
457 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
458 (page_to_phys(page) & (1 << 17)) != 0;
460 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
461 user_data, page_do_bit17_swizzling,
466 mutex_unlock(&dev->struct_mutex);
469 ret = fault_in_multipages_writeable(user_data, remain);
470 /* Userspace is tricking us, but we've already clobbered
471 * its pages with the prefault and promised to write the
472 * data up to the first fault. Hence ignore any errors
473 * and just continue. */
478 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
479 user_data, page_do_bit17_swizzling,
482 mutex_lock(&dev->struct_mutex);
485 mark_page_accessed(page);
490 remain -= page_length;
491 user_data += page_length;
492 offset += page_length;
496 i915_gem_object_unpin_pages(obj);
502 * Reads data from the object referenced by handle.
504 * On error, the contents of *data are undefined.
507 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
508 struct drm_file *file)
510 struct drm_i915_gem_pread *args = data;
511 struct drm_i915_gem_object *obj;
517 if (!access_ok(VERIFY_WRITE,
518 to_user_ptr(args->data_ptr),
522 ret = i915_mutex_lock_interruptible(dev);
526 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
527 if (&obj->base == NULL) {
532 /* Bounds check source. */
533 if (args->offset > obj->base.size ||
534 args->size > obj->base.size - args->offset) {
539 /* prime objects have no backing filp to GEM pread/pwrite
542 if (!obj->base.filp) {
547 trace_i915_gem_object_pread(obj, args->offset, args->size);
549 ret = i915_gem_shmem_pread(dev, obj, args, file);
552 drm_gem_object_unreference(&obj->base);
554 mutex_unlock(&dev->struct_mutex);
558 /* This is the fast write path which cannot handle
559 * page faults in the source data
563 fast_user_write(struct io_mapping *mapping,
564 loff_t page_base, int page_offset,
565 char __user *user_data,
568 void __iomem *vaddr_atomic;
570 unsigned long unwritten;
572 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
573 /* We can use the cpu mem copy function because this is X86. */
574 vaddr = (void __force*)vaddr_atomic + page_offset;
575 unwritten = __copy_from_user_inatomic_nocache(vaddr,
577 io_mapping_unmap_atomic(vaddr_atomic);
582 * This is the fast pwrite path, where we copy the data directly from the
583 * user into the GTT, uncached.
586 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
587 struct drm_i915_gem_object *obj,
588 struct drm_i915_gem_pwrite *args,
589 struct drm_file *file)
591 drm_i915_private_t *dev_priv = dev->dev_private;
593 loff_t offset, page_base;
594 char __user *user_data;
595 int page_offset, page_length, ret;
597 ret = i915_gem_object_pin(obj, 0, true, true);
601 ret = i915_gem_object_set_to_gtt_domain(obj, true);
605 ret = i915_gem_object_put_fence(obj);
609 user_data = to_user_ptr(args->data_ptr);
612 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
615 /* Operation in this page
617 * page_base = page offset within aperture
618 * page_offset = offset within page
619 * page_length = bytes to copy for this page
621 page_base = offset & PAGE_MASK;
622 page_offset = offset_in_page(offset);
623 page_length = remain;
624 if ((page_offset + remain) > PAGE_SIZE)
625 page_length = PAGE_SIZE - page_offset;
627 /* If we get a fault while copying data, then (presumably) our
628 * source page isn't available. Return the error and we'll
629 * retry in the slow path.
631 if (fast_user_write(dev_priv->gtt.mappable, page_base,
632 page_offset, user_data, page_length)) {
637 remain -= page_length;
638 user_data += page_length;
639 offset += page_length;
643 i915_gem_object_unpin(obj);
648 /* Per-page copy function for the shmem pwrite fastpath.
649 * Flushes invalid cachelines before writing to the target if
650 * needs_clflush_before is set and flushes out any written cachelines after
651 * writing if needs_clflush is set. */
653 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
654 char __user *user_data,
655 bool page_do_bit17_swizzling,
656 bool needs_clflush_before,
657 bool needs_clflush_after)
662 if (unlikely(page_do_bit17_swizzling))
665 vaddr = kmap_atomic(page);
666 if (needs_clflush_before)
667 drm_clflush_virt_range(vaddr + shmem_page_offset,
669 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
672 if (needs_clflush_after)
673 drm_clflush_virt_range(vaddr + shmem_page_offset,
675 kunmap_atomic(vaddr);
677 return ret ? -EFAULT : 0;
680 /* Only difference to the fast-path function is that this can handle bit17
681 * and uses non-atomic copy and kmap functions. */
683 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
684 char __user *user_data,
685 bool page_do_bit17_swizzling,
686 bool needs_clflush_before,
687 bool needs_clflush_after)
693 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
694 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
696 page_do_bit17_swizzling);
697 if (page_do_bit17_swizzling)
698 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
702 ret = __copy_from_user(vaddr + shmem_page_offset,
705 if (needs_clflush_after)
706 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
708 page_do_bit17_swizzling);
711 return ret ? -EFAULT : 0;
715 i915_gem_shmem_pwrite(struct drm_device *dev,
716 struct drm_i915_gem_object *obj,
717 struct drm_i915_gem_pwrite *args,
718 struct drm_file *file)
722 char __user *user_data;
723 int shmem_page_offset, page_length, ret = 0;
724 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
725 int hit_slowpath = 0;
726 int needs_clflush_after = 0;
727 int needs_clflush_before = 0;
728 struct sg_page_iter sg_iter;
730 user_data = to_user_ptr(args->data_ptr);
733 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
735 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
736 /* If we're not in the cpu write domain, set ourself into the gtt
737 * write domain and manually flush cachelines (if required). This
738 * optimizes for the case when the gpu will use the data
739 * right away and we therefore have to clflush anyway. */
740 if (obj->cache_level == I915_CACHE_NONE)
741 needs_clflush_after = 1;
742 if (i915_gem_obj_ggtt_bound(obj)) {
743 ret = i915_gem_object_set_to_gtt_domain(obj, true);
748 /* Same trick applies for invalidate partially written cachelines before
750 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
751 && obj->cache_level == I915_CACHE_NONE)
752 needs_clflush_before = 1;
754 ret = i915_gem_object_get_pages(obj);
758 i915_gem_object_pin_pages(obj);
760 offset = args->offset;
763 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
764 offset >> PAGE_SHIFT) {
765 struct page *page = sg_page_iter_page(&sg_iter);
766 int partial_cacheline_write;
771 /* Operation in this page
773 * shmem_page_offset = offset within page in shmem file
774 * page_length = bytes to copy for this page
776 shmem_page_offset = offset_in_page(offset);
778 page_length = remain;
779 if ((shmem_page_offset + page_length) > PAGE_SIZE)
780 page_length = PAGE_SIZE - shmem_page_offset;
782 /* If we don't overwrite a cacheline completely we need to be
783 * careful to have up-to-date data by first clflushing. Don't
784 * overcomplicate things and flush the entire patch. */
785 partial_cacheline_write = needs_clflush_before &&
786 ((shmem_page_offset | page_length)
787 & (boot_cpu_data.x86_clflush_size - 1));
789 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
790 (page_to_phys(page) & (1 << 17)) != 0;
792 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
793 user_data, page_do_bit17_swizzling,
794 partial_cacheline_write,
795 needs_clflush_after);
800 mutex_unlock(&dev->struct_mutex);
801 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
802 user_data, page_do_bit17_swizzling,
803 partial_cacheline_write,
804 needs_clflush_after);
806 mutex_lock(&dev->struct_mutex);
809 set_page_dirty(page);
810 mark_page_accessed(page);
815 remain -= page_length;
816 user_data += page_length;
817 offset += page_length;
821 i915_gem_object_unpin_pages(obj);
825 * Fixup: Flush cpu caches in case we didn't flush the dirty
826 * cachelines in-line while writing and the object moved
827 * out of the cpu write domain while we've dropped the lock.
829 if (!needs_clflush_after &&
830 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
831 i915_gem_clflush_object(obj);
832 i915_gem_chipset_flush(dev);
836 if (needs_clflush_after)
837 i915_gem_chipset_flush(dev);
843 * Writes data to the object referenced by handle.
845 * On error, the contents of the buffer that were to be modified are undefined.
848 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
849 struct drm_file *file)
851 struct drm_i915_gem_pwrite *args = data;
852 struct drm_i915_gem_object *obj;
858 if (!access_ok(VERIFY_READ,
859 to_user_ptr(args->data_ptr),
863 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
868 ret = i915_mutex_lock_interruptible(dev);
872 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
873 if (&obj->base == NULL) {
878 /* Bounds check destination. */
879 if (args->offset > obj->base.size ||
880 args->size > obj->base.size - args->offset) {
885 /* prime objects have no backing filp to GEM pread/pwrite
888 if (!obj->base.filp) {
893 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
896 /* We can only do the GTT pwrite on untiled buffers, as otherwise
897 * it would end up going through the fenced access, and we'll get
898 * different detiling behavior between reading and writing.
899 * pread/pwrite currently are reading and writing from the CPU
900 * perspective, requiring manual detiling by the client.
903 ret = i915_gem_phys_pwrite(dev, obj, args, file);
907 if (obj->cache_level == I915_CACHE_NONE &&
908 obj->tiling_mode == I915_TILING_NONE &&
909 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
910 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
911 /* Note that the gtt paths might fail with non-page-backed user
912 * pointers (e.g. gtt mappings when moving data between
913 * textures). Fallback to the shmem path in that case. */
916 if (ret == -EFAULT || ret == -ENOSPC)
917 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
920 drm_gem_object_unreference(&obj->base);
922 mutex_unlock(&dev->struct_mutex);
927 i915_gem_check_wedge(struct i915_gpu_error *error,
930 if (i915_reset_in_progress(error)) {
931 /* Non-interruptible callers can't handle -EAGAIN, hence return
932 * -EIO unconditionally for these. */
936 /* Recovery complete, but the reset failed ... */
937 if (i915_terminally_wedged(error))
947 * Compare seqno against outstanding lazy request. Emit a request if they are
951 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
955 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
958 if (seqno == ring->outstanding_lazy_request)
959 ret = i915_add_request(ring, NULL);
965 * __wait_seqno - wait until execution of seqno has finished
966 * @ring: the ring expected to report seqno
968 * @reset_counter: reset sequence associated with the given seqno
969 * @interruptible: do an interruptible wait (normally yes)
970 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
972 * Note: It is of utmost importance that the passed in seqno and reset_counter
973 * values have been read by the caller in an smp safe manner. Where read-side
974 * locks are involved, it is sufficient to read the reset_counter before
975 * unlocking the lock that protects the seqno. For lockless tricks, the
976 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
979 * Returns 0 if the seqno was found within the alloted time. Else returns the
980 * errno with remaining time filled in timeout argument.
982 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
983 unsigned reset_counter,
984 bool interruptible, struct timespec *timeout)
986 drm_i915_private_t *dev_priv = ring->dev->dev_private;
987 struct timespec before, now, wait_time={1,0};
988 unsigned long timeout_jiffies;
990 bool wait_forever = true;
993 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
996 trace_i915_gem_request_wait_begin(ring, seqno);
998 if (timeout != NULL) {
999 wait_time = *timeout;
1000 wait_forever = false;
1003 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1005 if (WARN_ON(!ring->irq_get(ring)))
1008 /* Record current time in case interrupted by signal, or wedged * */
1009 getrawmonotonic(&before);
1012 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1013 i915_reset_in_progress(&dev_priv->gpu_error) || \
1014 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1017 end = wait_event_interruptible_timeout(ring->irq_queue,
1021 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1024 /* We need to check whether any gpu reset happened in between
1025 * the caller grabbing the seqno and now ... */
1026 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1029 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1031 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1034 } while (end == 0 && wait_forever);
1036 getrawmonotonic(&now);
1038 ring->irq_put(ring);
1039 trace_i915_gem_request_wait_end(ring, seqno);
1043 struct timespec sleep_time = timespec_sub(now, before);
1044 *timeout = timespec_sub(*timeout, sleep_time);
1045 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1046 set_normalized_timespec(timeout, 0, 0);
1051 case -EAGAIN: /* Wedged */
1052 case -ERESTARTSYS: /* Signal */
1054 case 0: /* Timeout */
1056 default: /* Completed */
1057 WARN_ON(end < 0); /* We're not aware of other errors */
1063 * Waits for a sequence number to be signaled, and cleans up the
1064 * request and object lists appropriately for that event.
1067 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1069 struct drm_device *dev = ring->dev;
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071 bool interruptible = dev_priv->mm.interruptible;
1074 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1077 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1081 ret = i915_gem_check_olr(ring, seqno);
1085 return __wait_seqno(ring, seqno,
1086 atomic_read(&dev_priv->gpu_error.reset_counter),
1087 interruptible, NULL);
1091 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1092 struct intel_ring_buffer *ring)
1094 i915_gem_retire_requests_ring(ring);
1096 /* Manually manage the write flush as we may have not yet
1097 * retired the buffer.
1099 * Note that the last_write_seqno is always the earlier of
1100 * the two (read/write) seqno, so if we haved successfully waited,
1101 * we know we have passed the last write.
1103 obj->last_write_seqno = 0;
1104 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1110 * Ensures that all rendering to the object has completed and the object is
1111 * safe to unbind from the GTT or access from the CPU.
1113 static __must_check int
1114 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1117 struct intel_ring_buffer *ring = obj->ring;
1121 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1125 ret = i915_wait_seqno(ring, seqno);
1129 return i915_gem_object_wait_rendering__tail(obj, ring);
1132 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1133 * as the object state may change during this call.
1135 static __must_check int
1136 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1139 struct drm_device *dev = obj->base.dev;
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141 struct intel_ring_buffer *ring = obj->ring;
1142 unsigned reset_counter;
1146 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1147 BUG_ON(!dev_priv->mm.interruptible);
1149 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1153 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1157 ret = i915_gem_check_olr(ring, seqno);
1161 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1162 mutex_unlock(&dev->struct_mutex);
1163 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1164 mutex_lock(&dev->struct_mutex);
1168 return i915_gem_object_wait_rendering__tail(obj, ring);
1172 * Called when user space prepares to use an object with the CPU, either
1173 * through the mmap ioctl's mapping or a GTT mapping.
1176 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1177 struct drm_file *file)
1179 struct drm_i915_gem_set_domain *args = data;
1180 struct drm_i915_gem_object *obj;
1181 uint32_t read_domains = args->read_domains;
1182 uint32_t write_domain = args->write_domain;
1185 /* Only handle setting domains to types used by the CPU. */
1186 if (write_domain & I915_GEM_GPU_DOMAINS)
1189 if (read_domains & I915_GEM_GPU_DOMAINS)
1192 /* Having something in the write domain implies it's in the read
1193 * domain, and only that read domain. Enforce that in the request.
1195 if (write_domain != 0 && read_domains != write_domain)
1198 ret = i915_mutex_lock_interruptible(dev);
1202 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1203 if (&obj->base == NULL) {
1208 /* Try to flush the object off the GPU without holding the lock.
1209 * We will repeat the flush holding the lock in the normal manner
1210 * to catch cases where we are gazumped.
1212 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1216 if (read_domains & I915_GEM_DOMAIN_GTT) {
1217 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1219 /* Silently promote "you're not bound, there was nothing to do"
1220 * to success, since the client was just asking us to
1221 * make sure everything was done.
1226 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1230 drm_gem_object_unreference(&obj->base);
1232 mutex_unlock(&dev->struct_mutex);
1237 * Called when user space has done writes to this buffer
1240 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1241 struct drm_file *file)
1243 struct drm_i915_gem_sw_finish *args = data;
1244 struct drm_i915_gem_object *obj;
1247 ret = i915_mutex_lock_interruptible(dev);
1251 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1252 if (&obj->base == NULL) {
1257 /* Pinned buffers may be scanout, so flush the cache */
1259 i915_gem_object_flush_cpu_write_domain(obj);
1261 drm_gem_object_unreference(&obj->base);
1263 mutex_unlock(&dev->struct_mutex);
1268 * Maps the contents of an object, returning the address it is mapped
1271 * While the mapping holds a reference on the contents of the object, it doesn't
1272 * imply a ref on the object itself.
1275 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1276 struct drm_file *file)
1278 struct drm_i915_gem_mmap *args = data;
1279 struct drm_gem_object *obj;
1282 obj = drm_gem_object_lookup(dev, file, args->handle);
1286 /* prime objects have no backing filp to GEM mmap
1290 drm_gem_object_unreference_unlocked(obj);
1294 addr = vm_mmap(obj->filp, 0, args->size,
1295 PROT_READ | PROT_WRITE, MAP_SHARED,
1297 drm_gem_object_unreference_unlocked(obj);
1298 if (IS_ERR((void *)addr))
1301 args->addr_ptr = (uint64_t) addr;
1307 * i915_gem_fault - fault a page into the GTT
1308 * vma: VMA in question
1311 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1312 * from userspace. The fault handler takes care of binding the object to
1313 * the GTT (if needed), allocating and programming a fence register (again,
1314 * only if needed based on whether the old reg is still valid or the object
1315 * is tiled) and inserting a new PTE into the faulting process.
1317 * Note that the faulting process may involve evicting existing objects
1318 * from the GTT and/or fence registers to make room. So performance may
1319 * suffer if the GTT working set is large or there are few fence registers
1322 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1324 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1325 struct drm_device *dev = obj->base.dev;
1326 drm_i915_private_t *dev_priv = dev->dev_private;
1327 pgoff_t page_offset;
1330 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1332 /* We don't use vmf->pgoff since that has the fake offset */
1333 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1336 ret = i915_mutex_lock_interruptible(dev);
1340 trace_i915_gem_object_fault(obj, page_offset, true, write);
1342 /* Access to snoopable pages through the GTT is incoherent. */
1343 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1348 /* Now bind it into the GTT if needed */
1349 ret = i915_gem_object_pin(obj, 0, true, false);
1353 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1357 ret = i915_gem_object_get_fence(obj);
1361 obj->fault_mappable = true;
1363 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1367 /* Finally, remap it using the new GTT offset */
1368 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1370 i915_gem_object_unpin(obj);
1372 mutex_unlock(&dev->struct_mutex);
1376 /* If this -EIO is due to a gpu hang, give the reset code a
1377 * chance to clean up the mess. Otherwise return the proper
1379 if (i915_terminally_wedged(&dev_priv->gpu_error))
1380 return VM_FAULT_SIGBUS;
1382 /* Give the error handler a chance to run and move the
1383 * objects off the GPU active list. Next time we service the
1384 * fault, we should be able to transition the page into the
1385 * GTT without touching the GPU (and so avoid further
1386 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1387 * with coherency, just lost writes.
1395 * EBUSY is ok: this just means that another thread
1396 * already did the job.
1398 return VM_FAULT_NOPAGE;
1400 return VM_FAULT_OOM;
1402 return VM_FAULT_SIGBUS;
1404 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1405 return VM_FAULT_SIGBUS;
1410 * i915_gem_release_mmap - remove physical page mappings
1411 * @obj: obj in question
1413 * Preserve the reservation of the mmapping with the DRM core code, but
1414 * relinquish ownership of the pages back to the system.
1416 * It is vital that we remove the page mapping if we have mapped a tiled
1417 * object through the GTT and then lose the fence register due to
1418 * resource pressure. Similarly if the object has been moved out of the
1419 * aperture, than pages mapped into userspace must be revoked. Removing the
1420 * mapping will then trigger a page fault on the next user access, allowing
1421 * fixup by i915_gem_fault().
1424 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1426 if (!obj->fault_mappable)
1429 if (obj->base.dev->dev_mapping)
1430 unmap_mapping_range(obj->base.dev->dev_mapping,
1431 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1434 obj->fault_mappable = false;
1438 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1442 if (INTEL_INFO(dev)->gen >= 4 ||
1443 tiling_mode == I915_TILING_NONE)
1446 /* Previous chips need a power-of-two fence region when tiling */
1447 if (INTEL_INFO(dev)->gen == 3)
1448 gtt_size = 1024*1024;
1450 gtt_size = 512*1024;
1452 while (gtt_size < size)
1459 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1460 * @obj: object to check
1462 * Return the required GTT alignment for an object, taking into account
1463 * potential fence register mapping.
1466 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1467 int tiling_mode, bool fenced)
1470 * Minimum alignment is 4k (GTT page size), but might be greater
1471 * if a fence register is needed for the object.
1473 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1474 tiling_mode == I915_TILING_NONE)
1478 * Previous chips need to be aligned to the size of the smallest
1479 * fence register that can contain the object.
1481 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1484 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1486 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1489 if (obj->base.map_list.map)
1492 dev_priv->mm.shrinker_no_lock_stealing = true;
1494 ret = drm_gem_create_mmap_offset(&obj->base);
1498 /* Badly fragmented mmap space? The only way we can recover
1499 * space is by destroying unwanted objects. We can't randomly release
1500 * mmap_offsets as userspace expects them to be persistent for the
1501 * lifetime of the objects. The closest we can is to release the
1502 * offsets on purgeable objects by truncating it and marking it purged,
1503 * which prevents userspace from ever using that object again.
1505 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1506 ret = drm_gem_create_mmap_offset(&obj->base);
1510 i915_gem_shrink_all(dev_priv);
1511 ret = drm_gem_create_mmap_offset(&obj->base);
1513 dev_priv->mm.shrinker_no_lock_stealing = false;
1518 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1520 if (!obj->base.map_list.map)
1523 drm_gem_free_mmap_offset(&obj->base);
1527 i915_gem_mmap_gtt(struct drm_file *file,
1528 struct drm_device *dev,
1532 struct drm_i915_private *dev_priv = dev->dev_private;
1533 struct drm_i915_gem_object *obj;
1536 ret = i915_mutex_lock_interruptible(dev);
1540 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1541 if (&obj->base == NULL) {
1546 if (obj->base.size > dev_priv->gtt.mappable_end) {
1551 if (obj->madv != I915_MADV_WILLNEED) {
1552 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1557 ret = i915_gem_object_create_mmap_offset(obj);
1561 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1564 drm_gem_object_unreference(&obj->base);
1566 mutex_unlock(&dev->struct_mutex);
1571 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1573 * @data: GTT mapping ioctl data
1574 * @file: GEM object info
1576 * Simply returns the fake offset to userspace so it can mmap it.
1577 * The mmap call will end up in drm_gem_mmap(), which will set things
1578 * up so we can get faults in the handler above.
1580 * The fault handler will take care of binding the object into the GTT
1581 * (since it may have been evicted to make room for something), allocating
1582 * a fence register, and mapping the appropriate aperture address into
1586 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1587 struct drm_file *file)
1589 struct drm_i915_gem_mmap_gtt *args = data;
1591 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1594 /* Immediately discard the backing storage */
1596 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1598 struct inode *inode;
1600 i915_gem_object_free_mmap_offset(obj);
1602 if (obj->base.filp == NULL)
1605 /* Our goal here is to return as much of the memory as
1606 * is possible back to the system as we are called from OOM.
1607 * To do this we must instruct the shmfs to drop all of its
1608 * backing pages, *now*.
1610 inode = file_inode(obj->base.filp);
1611 shmem_truncate_range(inode, 0, (loff_t)-1);
1613 obj->madv = __I915_MADV_PURGED;
1617 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1619 return obj->madv == I915_MADV_DONTNEED;
1623 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1625 struct sg_page_iter sg_iter;
1628 BUG_ON(obj->madv == __I915_MADV_PURGED);
1630 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1632 /* In the event of a disaster, abandon all caches and
1633 * hope for the best.
1635 WARN_ON(ret != -EIO);
1636 i915_gem_clflush_object(obj);
1637 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1640 if (i915_gem_object_needs_bit17_swizzle(obj))
1641 i915_gem_object_save_bit_17_swizzle(obj);
1643 if (obj->madv == I915_MADV_DONTNEED)
1646 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1647 struct page *page = sg_page_iter_page(&sg_iter);
1650 set_page_dirty(page);
1652 if (obj->madv == I915_MADV_WILLNEED)
1653 mark_page_accessed(page);
1655 page_cache_release(page);
1659 sg_free_table(obj->pages);
1664 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1666 const struct drm_i915_gem_object_ops *ops = obj->ops;
1668 if (obj->pages == NULL)
1671 BUG_ON(i915_gem_obj_ggtt_bound(obj));
1673 if (obj->pages_pin_count)
1676 /* ->put_pages might need to allocate memory for the bit17 swizzle
1677 * array, hence protect them from being reaped by removing them from gtt
1679 list_del(&obj->global_list);
1681 ops->put_pages(obj);
1684 if (i915_gem_object_is_purgeable(obj))
1685 i915_gem_object_truncate(obj);
1691 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1692 bool purgeable_only)
1694 struct drm_i915_gem_object *obj, *next;
1697 list_for_each_entry_safe(obj, next,
1698 &dev_priv->mm.unbound_list,
1700 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1701 i915_gem_object_put_pages(obj) == 0) {
1702 count += obj->base.size >> PAGE_SHIFT;
1703 if (count >= target)
1708 list_for_each_entry_safe(obj, next,
1709 &dev_priv->mm.inactive_list,
1711 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1712 i915_gem_object_unbind(obj) == 0 &&
1713 i915_gem_object_put_pages(obj) == 0) {
1714 count += obj->base.size >> PAGE_SHIFT;
1715 if (count >= target)
1724 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1726 return __i915_gem_shrink(dev_priv, target, true);
1730 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1732 struct drm_i915_gem_object *obj, *next;
1734 i915_gem_evict_everything(dev_priv->dev);
1736 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1738 i915_gem_object_put_pages(obj);
1742 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1744 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1746 struct address_space *mapping;
1747 struct sg_table *st;
1748 struct scatterlist *sg;
1749 struct sg_page_iter sg_iter;
1751 unsigned long last_pfn = 0; /* suppress gcc warning */
1754 /* Assert that the object is not currently in any GPU domain. As it
1755 * wasn't in the GTT, there shouldn't be any way it could have been in
1758 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1759 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1761 st = kmalloc(sizeof(*st), GFP_KERNEL);
1765 page_count = obj->base.size / PAGE_SIZE;
1766 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1772 /* Get the list of pages out of our struct file. They'll be pinned
1773 * at this point until we release them.
1775 * Fail silently without starting the shrinker
1777 mapping = file_inode(obj->base.filp)->i_mapping;
1778 gfp = mapping_gfp_mask(mapping);
1779 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1780 gfp &= ~(__GFP_IO | __GFP_WAIT);
1783 for (i = 0; i < page_count; i++) {
1784 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1786 i915_gem_purge(dev_priv, page_count);
1787 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1790 /* We've tried hard to allocate the memory by reaping
1791 * our own buffer, now let the real VM do its job and
1792 * go down in flames if truly OOM.
1794 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1795 gfp |= __GFP_IO | __GFP_WAIT;
1797 i915_gem_shrink_all(dev_priv);
1798 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1802 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1803 gfp &= ~(__GFP_IO | __GFP_WAIT);
1805 #ifdef CONFIG_SWIOTLB
1806 if (swiotlb_nr_tbl()) {
1808 sg_set_page(sg, page, PAGE_SIZE, 0);
1813 if (!i || page_to_pfn(page) != last_pfn + 1) {
1817 sg_set_page(sg, page, PAGE_SIZE, 0);
1819 sg->length += PAGE_SIZE;
1821 last_pfn = page_to_pfn(page);
1823 #ifdef CONFIG_SWIOTLB
1824 if (!swiotlb_nr_tbl())
1829 if (i915_gem_object_needs_bit17_swizzle(obj))
1830 i915_gem_object_do_bit_17_swizzle(obj);
1836 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1837 page_cache_release(sg_page_iter_page(&sg_iter));
1840 return PTR_ERR(page);
1843 /* Ensure that the associated pages are gathered from the backing storage
1844 * and pinned into our object. i915_gem_object_get_pages() may be called
1845 * multiple times before they are released by a single call to
1846 * i915_gem_object_put_pages() - once the pages are no longer referenced
1847 * either as a result of memory pressure (reaping pages under the shrinker)
1848 * or as the object is itself released.
1851 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1853 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1854 const struct drm_i915_gem_object_ops *ops = obj->ops;
1860 if (obj->madv != I915_MADV_WILLNEED) {
1861 DRM_ERROR("Attempting to obtain a purgeable object\n");
1865 BUG_ON(obj->pages_pin_count);
1867 ret = ops->get_pages(obj);
1871 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1876 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1877 struct intel_ring_buffer *ring)
1879 struct drm_device *dev = obj->base.dev;
1880 struct drm_i915_private *dev_priv = dev->dev_private;
1881 u32 seqno = intel_ring_get_seqno(ring);
1883 BUG_ON(ring == NULL);
1884 if (obj->ring != ring && obj->last_write_seqno) {
1885 /* Keep the seqno relative to the current ring */
1886 obj->last_write_seqno = seqno;
1890 /* Add a reference if we're newly entering the active list. */
1892 drm_gem_object_reference(&obj->base);
1896 /* Move from whatever list we were on to the tail of execution. */
1897 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1898 list_move_tail(&obj->ring_list, &ring->active_list);
1900 obj->last_read_seqno = seqno;
1902 if (obj->fenced_gpu_access) {
1903 obj->last_fenced_seqno = seqno;
1905 /* Bump MRU to take account of the delayed flush */
1906 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1907 struct drm_i915_fence_reg *reg;
1909 reg = &dev_priv->fence_regs[obj->fence_reg];
1910 list_move_tail(®->lru_list,
1911 &dev_priv->mm.fence_list);
1917 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1919 struct drm_device *dev = obj->base.dev;
1920 struct drm_i915_private *dev_priv = dev->dev_private;
1922 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1923 BUG_ON(!obj->active);
1925 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1927 list_del_init(&obj->ring_list);
1930 obj->last_read_seqno = 0;
1931 obj->last_write_seqno = 0;
1932 obj->base.write_domain = 0;
1934 obj->last_fenced_seqno = 0;
1935 obj->fenced_gpu_access = false;
1938 drm_gem_object_unreference(&obj->base);
1940 WARN_ON(i915_verify_lists(dev));
1944 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1946 struct drm_i915_private *dev_priv = dev->dev_private;
1947 struct intel_ring_buffer *ring;
1950 /* Carefully retire all requests without writing to the rings */
1951 for_each_ring(ring, dev_priv, i) {
1952 ret = intel_ring_idle(ring);
1956 i915_gem_retire_requests(dev);
1958 /* Finally reset hw state */
1959 for_each_ring(ring, dev_priv, i) {
1960 intel_ring_init_seqno(ring, seqno);
1962 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1963 ring->sync_seqno[j] = 0;
1969 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1971 struct drm_i915_private *dev_priv = dev->dev_private;
1977 /* HWS page needs to be set less than what we
1978 * will inject to ring
1980 ret = i915_gem_init_seqno(dev, seqno - 1);
1984 /* Carefully set the last_seqno value so that wrap
1985 * detection still works
1987 dev_priv->next_seqno = seqno;
1988 dev_priv->last_seqno = seqno - 1;
1989 if (dev_priv->last_seqno == 0)
1990 dev_priv->last_seqno--;
1996 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1998 struct drm_i915_private *dev_priv = dev->dev_private;
2000 /* reserve 0 for non-seqno */
2001 if (dev_priv->next_seqno == 0) {
2002 int ret = i915_gem_init_seqno(dev, 0);
2006 dev_priv->next_seqno = 1;
2009 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2013 int __i915_add_request(struct intel_ring_buffer *ring,
2014 struct drm_file *file,
2015 struct drm_i915_gem_object *obj,
2018 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2019 struct drm_i915_gem_request *request;
2020 u32 request_ring_position, request_start;
2024 request_start = intel_ring_get_tail(ring);
2026 * Emit any outstanding flushes - execbuf can fail to emit the flush
2027 * after having emitted the batchbuffer command. Hence we need to fix
2028 * things up similar to emitting the lazy request. The difference here
2029 * is that the flush _must_ happen before the next request, no matter
2032 ret = intel_ring_flush_all_caches(ring);
2036 request = kmalloc(sizeof(*request), GFP_KERNEL);
2037 if (request == NULL)
2041 /* Record the position of the start of the request so that
2042 * should we detect the updated seqno part-way through the
2043 * GPU processing the request, we never over-estimate the
2044 * position of the head.
2046 request_ring_position = intel_ring_get_tail(ring);
2048 ret = ring->add_request(ring);
2054 request->seqno = intel_ring_get_seqno(ring);
2055 request->ring = ring;
2056 request->head = request_start;
2057 request->tail = request_ring_position;
2058 request->ctx = ring->last_context;
2059 request->batch_obj = obj;
2061 /* Whilst this request exists, batch_obj will be on the
2062 * active_list, and so will hold the active reference. Only when this
2063 * request is retired will the the batch_obj be moved onto the
2064 * inactive_list and lose its active reference. Hence we do not need
2065 * to explicitly hold another reference here.
2069 i915_gem_context_reference(request->ctx);
2071 request->emitted_jiffies = jiffies;
2072 was_empty = list_empty(&ring->request_list);
2073 list_add_tail(&request->list, &ring->request_list);
2074 request->file_priv = NULL;
2077 struct drm_i915_file_private *file_priv = file->driver_priv;
2079 spin_lock(&file_priv->mm.lock);
2080 request->file_priv = file_priv;
2081 list_add_tail(&request->client_list,
2082 &file_priv->mm.request_list);
2083 spin_unlock(&file_priv->mm.lock);
2086 trace_i915_gem_request_add(ring, request->seqno);
2087 ring->outstanding_lazy_request = 0;
2089 if (!dev_priv->ums.mm_suspended) {
2090 if (i915_enable_hangcheck) {
2091 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2092 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2095 queue_delayed_work(dev_priv->wq,
2096 &dev_priv->mm.retire_work,
2097 round_jiffies_up_relative(HZ));
2098 intel_mark_busy(dev_priv->dev);
2103 *out_seqno = request->seqno;
2108 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2110 struct drm_i915_file_private *file_priv = request->file_priv;
2115 spin_lock(&file_priv->mm.lock);
2116 if (request->file_priv) {
2117 list_del(&request->client_list);
2118 request->file_priv = NULL;
2120 spin_unlock(&file_priv->mm.lock);
2123 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)
2125 if (acthd >= i915_gem_obj_ggtt_offset(obj) &&
2126 acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
2132 static bool i915_head_inside_request(const u32 acthd_unmasked,
2133 const u32 request_start,
2134 const u32 request_end)
2136 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2138 if (request_start < request_end) {
2139 if (acthd >= request_start && acthd < request_end)
2141 } else if (request_start > request_end) {
2142 if (acthd >= request_start || acthd < request_end)
2149 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2150 const u32 acthd, bool *inside)
2152 /* There is a possibility that unmasked head address
2153 * pointing inside the ring, matches the batch_obj address range.
2154 * However this is extremely unlikely.
2157 if (request->batch_obj) {
2158 if (i915_head_inside_object(acthd, request->batch_obj)) {
2164 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2172 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2173 struct drm_i915_gem_request *request,
2176 struct i915_ctx_hang_stats *hs = NULL;
2177 bool inside, guilty;
2179 /* Innocent until proven guilty */
2182 if (ring->hangcheck.action != wait &&
2183 i915_request_guilty(request, acthd, &inside)) {
2184 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2186 inside ? "inside" : "flushing",
2187 request->batch_obj ?
2188 i915_gem_obj_ggtt_offset(request->batch_obj) : 0,
2189 request->ctx ? request->ctx->id : 0,
2195 /* If contexts are disabled or this is the default context, use
2196 * file_priv->reset_state
2198 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2199 hs = &request->ctx->hang_stats;
2200 else if (request->file_priv)
2201 hs = &request->file_priv->hang_stats;
2207 hs->batch_pending++;
2211 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2213 list_del(&request->list);
2214 i915_gem_request_remove_from_client(request);
2217 i915_gem_context_unreference(request->ctx);
2222 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2223 struct intel_ring_buffer *ring)
2225 u32 completed_seqno;
2228 acthd = intel_ring_get_active_head(ring);
2229 completed_seqno = ring->get_seqno(ring, false);
2231 while (!list_empty(&ring->request_list)) {
2232 struct drm_i915_gem_request *request;
2234 request = list_first_entry(&ring->request_list,
2235 struct drm_i915_gem_request,
2238 if (request->seqno > completed_seqno)
2239 i915_set_reset_status(ring, request, acthd);
2241 i915_gem_free_request(request);
2244 while (!list_empty(&ring->active_list)) {
2245 struct drm_i915_gem_object *obj;
2247 obj = list_first_entry(&ring->active_list,
2248 struct drm_i915_gem_object,
2251 i915_gem_object_move_to_inactive(obj);
2255 void i915_gem_restore_fences(struct drm_device *dev)
2257 struct drm_i915_private *dev_priv = dev->dev_private;
2260 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2261 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2262 i915_gem_write_fence(dev, i, reg->obj);
2266 void i915_gem_reset(struct drm_device *dev)
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269 struct drm_i915_gem_object *obj;
2270 struct intel_ring_buffer *ring;
2273 for_each_ring(ring, dev_priv, i)
2274 i915_gem_reset_ring_lists(dev_priv, ring);
2276 /* Move everything out of the GPU domains to ensure we do any
2277 * necessary invalidation upon reuse.
2279 list_for_each_entry(obj,
2280 &dev_priv->mm.inactive_list,
2283 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2286 i915_gem_restore_fences(dev);
2290 * This function clears the request list as sequence numbers are passed.
2293 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2297 if (list_empty(&ring->request_list))
2300 WARN_ON(i915_verify_lists(ring->dev));
2302 seqno = ring->get_seqno(ring, true);
2304 while (!list_empty(&ring->request_list)) {
2305 struct drm_i915_gem_request *request;
2307 request = list_first_entry(&ring->request_list,
2308 struct drm_i915_gem_request,
2311 if (!i915_seqno_passed(seqno, request->seqno))
2314 trace_i915_gem_request_retire(ring, request->seqno);
2315 /* We know the GPU must have read the request to have
2316 * sent us the seqno + interrupt, so use the position
2317 * of tail of the request to update the last known position
2320 ring->last_retired_head = request->tail;
2322 i915_gem_free_request(request);
2325 /* Move any buffers on the active list that are no longer referenced
2326 * by the ringbuffer to the flushing/inactive lists as appropriate.
2328 while (!list_empty(&ring->active_list)) {
2329 struct drm_i915_gem_object *obj;
2331 obj = list_first_entry(&ring->active_list,
2332 struct drm_i915_gem_object,
2335 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2338 i915_gem_object_move_to_inactive(obj);
2341 if (unlikely(ring->trace_irq_seqno &&
2342 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2343 ring->irq_put(ring);
2344 ring->trace_irq_seqno = 0;
2347 WARN_ON(i915_verify_lists(ring->dev));
2351 i915_gem_retire_requests(struct drm_device *dev)
2353 drm_i915_private_t *dev_priv = dev->dev_private;
2354 struct intel_ring_buffer *ring;
2357 for_each_ring(ring, dev_priv, i)
2358 i915_gem_retire_requests_ring(ring);
2362 i915_gem_retire_work_handler(struct work_struct *work)
2364 drm_i915_private_t *dev_priv;
2365 struct drm_device *dev;
2366 struct intel_ring_buffer *ring;
2370 dev_priv = container_of(work, drm_i915_private_t,
2371 mm.retire_work.work);
2372 dev = dev_priv->dev;
2374 /* Come back later if the device is busy... */
2375 if (!mutex_trylock(&dev->struct_mutex)) {
2376 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2377 round_jiffies_up_relative(HZ));
2381 i915_gem_retire_requests(dev);
2383 /* Send a periodic flush down the ring so we don't hold onto GEM
2384 * objects indefinitely.
2387 for_each_ring(ring, dev_priv, i) {
2388 if (ring->gpu_caches_dirty)
2389 i915_add_request(ring, NULL);
2391 idle &= list_empty(&ring->request_list);
2394 if (!dev_priv->ums.mm_suspended && !idle)
2395 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2396 round_jiffies_up_relative(HZ));
2398 intel_mark_idle(dev);
2400 mutex_unlock(&dev->struct_mutex);
2404 * Ensures that an object will eventually get non-busy by flushing any required
2405 * write domains, emitting any outstanding lazy request and retiring and
2406 * completed requests.
2409 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2414 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2418 i915_gem_retire_requests_ring(obj->ring);
2425 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2426 * @DRM_IOCTL_ARGS: standard ioctl arguments
2428 * Returns 0 if successful, else an error is returned with the remaining time in
2429 * the timeout parameter.
2430 * -ETIME: object is still busy after timeout
2431 * -ERESTARTSYS: signal interrupted the wait
2432 * -ENONENT: object doesn't exist
2433 * Also possible, but rare:
2434 * -EAGAIN: GPU wedged
2436 * -ENODEV: Internal IRQ fail
2437 * -E?: The add request failed
2439 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2440 * non-zero timeout parameter the wait ioctl will wait for the given number of
2441 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2442 * without holding struct_mutex the object may become re-busied before this
2443 * function completes. A similar but shorter * race condition exists in the busy
2447 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2449 drm_i915_private_t *dev_priv = dev->dev_private;
2450 struct drm_i915_gem_wait *args = data;
2451 struct drm_i915_gem_object *obj;
2452 struct intel_ring_buffer *ring = NULL;
2453 struct timespec timeout_stack, *timeout = NULL;
2454 unsigned reset_counter;
2458 if (args->timeout_ns >= 0) {
2459 timeout_stack = ns_to_timespec(args->timeout_ns);
2460 timeout = &timeout_stack;
2463 ret = i915_mutex_lock_interruptible(dev);
2467 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2468 if (&obj->base == NULL) {
2469 mutex_unlock(&dev->struct_mutex);
2473 /* Need to make sure the object gets inactive eventually. */
2474 ret = i915_gem_object_flush_active(obj);
2479 seqno = obj->last_read_seqno;
2486 /* Do this after OLR check to make sure we make forward progress polling
2487 * on this IOCTL with a 0 timeout (like busy ioctl)
2489 if (!args->timeout_ns) {
2494 drm_gem_object_unreference(&obj->base);
2495 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2496 mutex_unlock(&dev->struct_mutex);
2498 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2500 args->timeout_ns = timespec_to_ns(timeout);
2504 drm_gem_object_unreference(&obj->base);
2505 mutex_unlock(&dev->struct_mutex);
2510 * i915_gem_object_sync - sync an object to a ring.
2512 * @obj: object which may be in use on another ring.
2513 * @to: ring we wish to use the object on. May be NULL.
2515 * This code is meant to abstract object synchronization with the GPU.
2516 * Calling with NULL implies synchronizing the object with the CPU
2517 * rather than a particular GPU ring.
2519 * Returns 0 if successful, else propagates up the lower layer error.
2522 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2523 struct intel_ring_buffer *to)
2525 struct intel_ring_buffer *from = obj->ring;
2529 if (from == NULL || to == from)
2532 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2533 return i915_gem_object_wait_rendering(obj, false);
2535 idx = intel_ring_sync_index(from, to);
2537 seqno = obj->last_read_seqno;
2538 if (seqno <= from->sync_seqno[idx])
2541 ret = i915_gem_check_olr(obj->ring, seqno);
2545 ret = to->sync_to(to, from, seqno);
2547 /* We use last_read_seqno because sync_to()
2548 * might have just caused seqno wrap under
2551 from->sync_seqno[idx] = obj->last_read_seqno;
2556 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2558 u32 old_write_domain, old_read_domains;
2560 /* Force a pagefault for domain tracking on next user access */
2561 i915_gem_release_mmap(obj);
2563 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2566 /* Wait for any direct GTT access to complete */
2569 old_read_domains = obj->base.read_domains;
2570 old_write_domain = obj->base.write_domain;
2572 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2573 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2575 trace_i915_gem_object_change_domain(obj,
2581 * Unbinds an object from the GTT aperture.
2584 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2586 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2589 if (!i915_gem_obj_ggtt_bound(obj))
2595 BUG_ON(obj->pages == NULL);
2597 ret = i915_gem_object_finish_gpu(obj);
2600 /* Continue on if we fail due to EIO, the GPU is hung so we
2601 * should be safe and we need to cleanup or else we might
2602 * cause memory corruption through use-after-free.
2605 i915_gem_object_finish_gtt(obj);
2607 /* release the fence reg _after_ flushing */
2608 ret = i915_gem_object_put_fence(obj);
2612 trace_i915_gem_object_unbind(obj);
2614 if (obj->has_global_gtt_mapping)
2615 i915_gem_gtt_unbind_object(obj);
2616 if (obj->has_aliasing_ppgtt_mapping) {
2617 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2618 obj->has_aliasing_ppgtt_mapping = 0;
2620 i915_gem_gtt_finish_object(obj);
2621 i915_gem_object_unpin_pages(obj);
2623 list_del(&obj->mm_list);
2624 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2625 /* Avoid an unnecessary call to unbind on rebind. */
2626 obj->map_and_fenceable = true;
2628 drm_mm_remove_node(&obj->gtt_space);
2633 int i915_gpu_idle(struct drm_device *dev)
2635 drm_i915_private_t *dev_priv = dev->dev_private;
2636 struct intel_ring_buffer *ring;
2639 /* Flush everything onto the inactive list. */
2640 for_each_ring(ring, dev_priv, i) {
2641 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2645 ret = intel_ring_idle(ring);
2653 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2654 struct drm_i915_gem_object *obj)
2656 drm_i915_private_t *dev_priv = dev->dev_private;
2658 int fence_pitch_shift;
2660 if (INTEL_INFO(dev)->gen >= 6) {
2661 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2662 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2664 fence_reg = FENCE_REG_965_0;
2665 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2668 fence_reg += reg * 8;
2670 /* To w/a incoherency with non-atomic 64-bit register updates,
2671 * we split the 64-bit update into two 32-bit writes. In order
2672 * for a partial fence not to be evaluated between writes, we
2673 * precede the update with write to turn off the fence register,
2674 * and only enable the fence as the last step.
2676 * For extra levels of paranoia, we make sure each step lands
2677 * before applying the next step.
2679 I915_WRITE(fence_reg, 0);
2680 POSTING_READ(fence_reg);
2683 u32 size = i915_gem_obj_ggtt_size(obj);
2686 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2688 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2689 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2690 if (obj->tiling_mode == I915_TILING_Y)
2691 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2692 val |= I965_FENCE_REG_VALID;
2694 I915_WRITE(fence_reg + 4, val >> 32);
2695 POSTING_READ(fence_reg + 4);
2697 I915_WRITE(fence_reg + 0, val);
2698 POSTING_READ(fence_reg);
2700 I915_WRITE(fence_reg + 4, 0);
2701 POSTING_READ(fence_reg + 4);
2705 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2706 struct drm_i915_gem_object *obj)
2708 drm_i915_private_t *dev_priv = dev->dev_private;
2712 u32 size = i915_gem_obj_ggtt_size(obj);
2716 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2717 (size & -size) != size ||
2718 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2719 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2720 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2722 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2727 /* Note: pitch better be a power of two tile widths */
2728 pitch_val = obj->stride / tile_width;
2729 pitch_val = ffs(pitch_val) - 1;
2731 val = i915_gem_obj_ggtt_offset(obj);
2732 if (obj->tiling_mode == I915_TILING_Y)
2733 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2734 val |= I915_FENCE_SIZE_BITS(size);
2735 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2736 val |= I830_FENCE_REG_VALID;
2741 reg = FENCE_REG_830_0 + reg * 4;
2743 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2745 I915_WRITE(reg, val);
2749 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2750 struct drm_i915_gem_object *obj)
2752 drm_i915_private_t *dev_priv = dev->dev_private;
2756 u32 size = i915_gem_obj_ggtt_size(obj);
2759 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2760 (size & -size) != size ||
2761 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2762 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2763 i915_gem_obj_ggtt_offset(obj), size);
2765 pitch_val = obj->stride / 128;
2766 pitch_val = ffs(pitch_val) - 1;
2768 val = i915_gem_obj_ggtt_offset(obj);
2769 if (obj->tiling_mode == I915_TILING_Y)
2770 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2771 val |= I830_FENCE_SIZE_BITS(size);
2772 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2773 val |= I830_FENCE_REG_VALID;
2777 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2778 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2781 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2783 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2786 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2787 struct drm_i915_gem_object *obj)
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2791 /* Ensure that all CPU reads are completed before installing a fence
2792 * and all writes before removing the fence.
2794 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2797 switch (INTEL_INFO(dev)->gen) {
2801 case 4: i965_write_fence_reg(dev, reg, obj); break;
2802 case 3: i915_write_fence_reg(dev, reg, obj); break;
2803 case 2: i830_write_fence_reg(dev, reg, obj); break;
2807 /* And similarly be paranoid that no direct access to this region
2808 * is reordered to before the fence is installed.
2810 if (i915_gem_object_needs_mb(obj))
2814 static inline int fence_number(struct drm_i915_private *dev_priv,
2815 struct drm_i915_fence_reg *fence)
2817 return fence - dev_priv->fence_regs;
2820 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2821 struct drm_i915_fence_reg *fence,
2824 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2825 int reg = fence_number(dev_priv, fence);
2827 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2830 obj->fence_reg = reg;
2832 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2834 obj->fence_reg = I915_FENCE_REG_NONE;
2836 list_del_init(&fence->lru_list);
2841 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2843 if (obj->last_fenced_seqno) {
2844 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2848 obj->last_fenced_seqno = 0;
2851 obj->fenced_gpu_access = false;
2856 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2858 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2859 struct drm_i915_fence_reg *fence;
2862 ret = i915_gem_object_wait_fence(obj);
2866 if (obj->fence_reg == I915_FENCE_REG_NONE)
2869 fence = &dev_priv->fence_regs[obj->fence_reg];
2871 i915_gem_object_fence_lost(obj);
2872 i915_gem_object_update_fence(obj, fence, false);
2877 static struct drm_i915_fence_reg *
2878 i915_find_fence_reg(struct drm_device *dev)
2880 struct drm_i915_private *dev_priv = dev->dev_private;
2881 struct drm_i915_fence_reg *reg, *avail;
2884 /* First try to find a free reg */
2886 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2887 reg = &dev_priv->fence_regs[i];
2891 if (!reg->pin_count)
2898 /* None available, try to steal one or wait for a user to finish */
2899 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2910 * i915_gem_object_get_fence - set up fencing for an object
2911 * @obj: object to map through a fence reg
2913 * When mapping objects through the GTT, userspace wants to be able to write
2914 * to them without having to worry about swizzling if the object is tiled.
2915 * This function walks the fence regs looking for a free one for @obj,
2916 * stealing one if it can't find any.
2918 * It then sets up the reg based on the object's properties: address, pitch
2919 * and tiling format.
2921 * For an untiled surface, this removes any existing fence.
2924 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2926 struct drm_device *dev = obj->base.dev;
2927 struct drm_i915_private *dev_priv = dev->dev_private;
2928 bool enable = obj->tiling_mode != I915_TILING_NONE;
2929 struct drm_i915_fence_reg *reg;
2932 /* Have we updated the tiling parameters upon the object and so
2933 * will need to serialise the write to the associated fence register?
2935 if (obj->fence_dirty) {
2936 ret = i915_gem_object_wait_fence(obj);
2941 /* Just update our place in the LRU if our fence is getting reused. */
2942 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2943 reg = &dev_priv->fence_regs[obj->fence_reg];
2944 if (!obj->fence_dirty) {
2945 list_move_tail(®->lru_list,
2946 &dev_priv->mm.fence_list);
2949 } else if (enable) {
2950 reg = i915_find_fence_reg(dev);
2955 struct drm_i915_gem_object *old = reg->obj;
2957 ret = i915_gem_object_wait_fence(old);
2961 i915_gem_object_fence_lost(old);
2966 i915_gem_object_update_fence(obj, reg, enable);
2967 obj->fence_dirty = false;
2972 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2973 struct drm_mm_node *gtt_space,
2974 unsigned long cache_level)
2976 struct drm_mm_node *other;
2978 /* On non-LLC machines we have to be careful when putting differing
2979 * types of snoopable memory together to avoid the prefetcher
2980 * crossing memory domains and dying.
2985 if (!drm_mm_node_allocated(gtt_space))
2988 if (list_empty(>t_space->node_list))
2991 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2992 if (other->allocated && !other->hole_follows && other->color != cache_level)
2995 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2996 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3002 static void i915_gem_verify_gtt(struct drm_device *dev)
3005 struct drm_i915_private *dev_priv = dev->dev_private;
3006 struct drm_i915_gem_object *obj;
3009 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3010 if (obj->gtt_space == NULL) {
3011 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3016 if (obj->cache_level != obj->gtt_space->color) {
3017 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3018 i915_gem_obj_ggtt_offset(obj),
3019 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3021 obj->gtt_space->color);
3026 if (!i915_gem_valid_gtt_space(dev,
3028 obj->cache_level)) {
3029 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3030 i915_gem_obj_ggtt_offset(obj),
3031 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3043 * Finds free space in the GTT aperture and binds the object there.
3046 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3048 bool map_and_fenceable,
3051 struct drm_device *dev = obj->base.dev;
3052 drm_i915_private_t *dev_priv = dev->dev_private;
3053 u32 size, fence_size, fence_alignment, unfenced_alignment;
3054 bool mappable, fenceable;
3055 size_t gtt_max = map_and_fenceable ?
3056 dev_priv->gtt.mappable_end : dev_priv->gtt.total;
3059 fence_size = i915_gem_get_gtt_size(dev,
3062 fence_alignment = i915_gem_get_gtt_alignment(dev,
3064 obj->tiling_mode, true);
3065 unfenced_alignment =
3066 i915_gem_get_gtt_alignment(dev,
3068 obj->tiling_mode, false);
3071 alignment = map_and_fenceable ? fence_alignment :
3073 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3074 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3078 size = map_and_fenceable ? fence_size : obj->base.size;
3080 /* If the object is bigger than the entire aperture, reject it early
3081 * before evicting everything in a vain attempt to find space.
3083 if (obj->base.size > gtt_max) {
3084 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3086 map_and_fenceable ? "mappable" : "total",
3091 ret = i915_gem_object_get_pages(obj);
3095 i915_gem_object_pin_pages(obj);
3098 ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space,
3101 obj->cache_level, 0, gtt_max);
3103 ret = i915_gem_evict_something(dev, size, alignment,
3110 i915_gem_object_unpin_pages(obj);
3113 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &obj->gtt_space,
3114 obj->cache_level))) {
3115 i915_gem_object_unpin_pages(obj);
3116 drm_mm_remove_node(&obj->gtt_space);
3120 ret = i915_gem_gtt_prepare_object(obj);
3122 i915_gem_object_unpin_pages(obj);
3123 drm_mm_remove_node(&obj->gtt_space);
3127 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3128 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3131 i915_gem_obj_ggtt_size(obj) == fence_size &&
3132 (i915_gem_obj_ggtt_offset(obj) & (fence_alignment - 1)) == 0;
3134 mappable = i915_gem_obj_ggtt_offset(obj) + obj->base.size <=
3135 dev_priv->gtt.mappable_end;
3137 obj->map_and_fenceable = mappable && fenceable;
3139 trace_i915_gem_object_bind(obj, map_and_fenceable);
3140 i915_gem_verify_gtt(dev);
3145 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3147 /* If we don't have a page list set up, then we're not pinned
3148 * to GPU, and we can ignore the cache flush because it'll happen
3149 * again at bind time.
3151 if (obj->pages == NULL)
3155 * Stolen memory is always coherent with the GPU as it is explicitly
3156 * marked as wc by the system, or the system is cache-coherent.
3161 /* If the GPU is snooping the contents of the CPU cache,
3162 * we do not need to manually clear the CPU cache lines. However,
3163 * the caches are only snooped when the render cache is
3164 * flushed/invalidated. As we always have to emit invalidations
3165 * and flushes when moving into and out of the RENDER domain, correct
3166 * snooping behaviour occurs naturally as the result of our domain
3169 if (obj->cache_level != I915_CACHE_NONE)
3172 trace_i915_gem_object_clflush(obj);
3174 drm_clflush_sg(obj->pages);
3177 /** Flushes the GTT write domain for the object if it's dirty. */
3179 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3181 uint32_t old_write_domain;
3183 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3186 /* No actual flushing is required for the GTT write domain. Writes
3187 * to it immediately go to main memory as far as we know, so there's
3188 * no chipset flush. It also doesn't land in render cache.
3190 * However, we do have to enforce the order so that all writes through
3191 * the GTT land before any writes to the device, such as updates to
3196 old_write_domain = obj->base.write_domain;
3197 obj->base.write_domain = 0;
3199 trace_i915_gem_object_change_domain(obj,
3200 obj->base.read_domains,
3204 /** Flushes the CPU write domain for the object if it's dirty. */
3206 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3208 uint32_t old_write_domain;
3210 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3213 i915_gem_clflush_object(obj);
3214 i915_gem_chipset_flush(obj->base.dev);
3215 old_write_domain = obj->base.write_domain;
3216 obj->base.write_domain = 0;
3218 trace_i915_gem_object_change_domain(obj,
3219 obj->base.read_domains,
3224 * Moves a single object to the GTT read, and possibly write domain.
3226 * This function returns when the move is complete, including waiting on
3230 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3232 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3233 uint32_t old_write_domain, old_read_domains;
3236 /* Not valid to be called on unbound objects. */
3237 if (!i915_gem_obj_ggtt_bound(obj))
3240 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3243 ret = i915_gem_object_wait_rendering(obj, !write);
3247 i915_gem_object_flush_cpu_write_domain(obj);
3249 /* Serialise direct access to this object with the barriers for
3250 * coherent writes from the GPU, by effectively invalidating the
3251 * GTT domain upon first access.
3253 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3256 old_write_domain = obj->base.write_domain;
3257 old_read_domains = obj->base.read_domains;
3259 /* It should now be out of any other write domains, and we can update
3260 * the domain values for our changes.
3262 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3263 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3265 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3266 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3270 trace_i915_gem_object_change_domain(obj,
3274 /* And bump the LRU for this access */
3275 if (i915_gem_object_is_inactive(obj))
3276 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3281 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3282 enum i915_cache_level cache_level)
3284 struct drm_device *dev = obj->base.dev;
3285 drm_i915_private_t *dev_priv = dev->dev_private;
3288 if (obj->cache_level == cache_level)
3291 if (obj->pin_count) {
3292 DRM_DEBUG("can not change the cache level of pinned objects\n");
3296 if (!i915_gem_valid_gtt_space(dev, &obj->gtt_space, cache_level)) {
3297 ret = i915_gem_object_unbind(obj);
3302 if (i915_gem_obj_ggtt_bound(obj)) {
3303 ret = i915_gem_object_finish_gpu(obj);
3307 i915_gem_object_finish_gtt(obj);
3309 /* Before SandyBridge, you could not use tiling or fence
3310 * registers with snooped memory, so relinquish any fences
3311 * currently pointing to our region in the aperture.
3313 if (INTEL_INFO(dev)->gen < 6) {
3314 ret = i915_gem_object_put_fence(obj);
3319 if (obj->has_global_gtt_mapping)
3320 i915_gem_gtt_bind_object(obj, cache_level);
3321 if (obj->has_aliasing_ppgtt_mapping)
3322 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3325 i915_gem_obj_ggtt_set_color(obj, cache_level);
3328 if (cache_level == I915_CACHE_NONE) {
3329 u32 old_read_domains, old_write_domain;
3331 /* If we're coming from LLC cached, then we haven't
3332 * actually been tracking whether the data is in the
3333 * CPU cache or not, since we only allow one bit set
3334 * in obj->write_domain and have been skipping the clflushes.
3335 * Just set it to the CPU cache for now.
3337 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3338 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3340 old_read_domains = obj->base.read_domains;
3341 old_write_domain = obj->base.write_domain;
3343 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3344 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3346 trace_i915_gem_object_change_domain(obj,
3351 obj->cache_level = cache_level;
3352 i915_gem_verify_gtt(dev);
3356 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3357 struct drm_file *file)
3359 struct drm_i915_gem_caching *args = data;
3360 struct drm_i915_gem_object *obj;
3363 ret = i915_mutex_lock_interruptible(dev);
3367 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3368 if (&obj->base == NULL) {
3373 args->caching = obj->cache_level != I915_CACHE_NONE;
3375 drm_gem_object_unreference(&obj->base);
3377 mutex_unlock(&dev->struct_mutex);
3381 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3382 struct drm_file *file)
3384 struct drm_i915_gem_caching *args = data;
3385 struct drm_i915_gem_object *obj;
3386 enum i915_cache_level level;
3389 switch (args->caching) {
3390 case I915_CACHING_NONE:
3391 level = I915_CACHE_NONE;
3393 case I915_CACHING_CACHED:
3394 level = I915_CACHE_LLC;
3400 ret = i915_mutex_lock_interruptible(dev);
3404 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3405 if (&obj->base == NULL) {
3410 ret = i915_gem_object_set_cache_level(obj, level);
3412 drm_gem_object_unreference(&obj->base);
3414 mutex_unlock(&dev->struct_mutex);
3419 * Prepare buffer for display plane (scanout, cursors, etc).
3420 * Can be called from an uninterruptible phase (modesetting) and allows
3421 * any flushes to be pipelined (for pageflips).
3424 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3426 struct intel_ring_buffer *pipelined)
3428 u32 old_read_domains, old_write_domain;
3431 if (pipelined != obj->ring) {
3432 ret = i915_gem_object_sync(obj, pipelined);
3437 /* The display engine is not coherent with the LLC cache on gen6. As
3438 * a result, we make sure that the pinning that is about to occur is
3439 * done with uncached PTEs. This is lowest common denominator for all
3442 * However for gen6+, we could do better by using the GFDT bit instead
3443 * of uncaching, which would allow us to flush all the LLC-cached data
3444 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3446 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3450 /* As the user may map the buffer once pinned in the display plane
3451 * (e.g. libkms for the bootup splash), we have to ensure that we
3452 * always use map_and_fenceable for all scanout buffers.
3454 ret = i915_gem_object_pin(obj, alignment, true, false);
3458 i915_gem_object_flush_cpu_write_domain(obj);
3460 old_write_domain = obj->base.write_domain;
3461 old_read_domains = obj->base.read_domains;
3463 /* It should now be out of any other write domains, and we can update
3464 * the domain values for our changes.
3466 obj->base.write_domain = 0;
3467 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3469 trace_i915_gem_object_change_domain(obj,
3477 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3481 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3484 ret = i915_gem_object_wait_rendering(obj, false);
3488 /* Ensure that we invalidate the GPU's caches and TLBs. */
3489 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3494 * Moves a single object to the CPU read, and possibly write domain.
3496 * This function returns when the move is complete, including waiting on
3500 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3502 uint32_t old_write_domain, old_read_domains;
3505 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3508 ret = i915_gem_object_wait_rendering(obj, !write);
3512 i915_gem_object_flush_gtt_write_domain(obj);
3514 old_write_domain = obj->base.write_domain;
3515 old_read_domains = obj->base.read_domains;
3517 /* Flush the CPU cache if it's still invalid. */
3518 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3519 i915_gem_clflush_object(obj);
3521 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3524 /* It should now be out of any other write domains, and we can update
3525 * the domain values for our changes.
3527 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3529 /* If we're writing through the CPU, then the GPU read domains will
3530 * need to be invalidated at next use.
3533 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3534 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3537 trace_i915_gem_object_change_domain(obj,
3544 /* Throttle our rendering by waiting until the ring has completed our requests
3545 * emitted over 20 msec ago.
3547 * Note that if we were to use the current jiffies each time around the loop,
3548 * we wouldn't escape the function with any frames outstanding if the time to
3549 * render a frame was over 20ms.
3551 * This should get us reasonable parallelism between CPU and GPU but also
3552 * relatively low latency when blocking on a particular request to finish.
3555 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3557 struct drm_i915_private *dev_priv = dev->dev_private;
3558 struct drm_i915_file_private *file_priv = file->driver_priv;
3559 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3560 struct drm_i915_gem_request *request;
3561 struct intel_ring_buffer *ring = NULL;
3562 unsigned reset_counter;
3566 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3570 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3574 spin_lock(&file_priv->mm.lock);
3575 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3576 if (time_after_eq(request->emitted_jiffies, recent_enough))
3579 ring = request->ring;
3580 seqno = request->seqno;
3582 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3583 spin_unlock(&file_priv->mm.lock);
3588 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3590 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3596 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3598 bool map_and_fenceable,
3603 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3606 if (i915_gem_obj_ggtt_bound(obj)) {
3607 if ((alignment && i915_gem_obj_ggtt_offset(obj) & (alignment - 1)) ||
3608 (map_and_fenceable && !obj->map_and_fenceable)) {
3609 WARN(obj->pin_count,
3610 "bo is already pinned with incorrect alignment:"
3611 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3612 " obj->map_and_fenceable=%d\n",
3613 i915_gem_obj_ggtt_offset(obj), alignment,
3615 obj->map_and_fenceable);
3616 ret = i915_gem_object_unbind(obj);
3622 if (!i915_gem_obj_ggtt_bound(obj)) {
3623 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3625 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3631 if (!dev_priv->mm.aliasing_ppgtt)
3632 i915_gem_gtt_bind_object(obj, obj->cache_level);
3635 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3636 i915_gem_gtt_bind_object(obj, obj->cache_level);
3639 obj->pin_mappable |= map_and_fenceable;
3645 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3647 BUG_ON(obj->pin_count == 0);
3648 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
3650 if (--obj->pin_count == 0)
3651 obj->pin_mappable = false;
3655 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3656 struct drm_file *file)
3658 struct drm_i915_gem_pin *args = data;
3659 struct drm_i915_gem_object *obj;
3662 ret = i915_mutex_lock_interruptible(dev);
3666 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3667 if (&obj->base == NULL) {
3672 if (obj->madv != I915_MADV_WILLNEED) {
3673 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3678 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3679 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3685 if (obj->user_pin_count == 0) {
3686 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3691 obj->user_pin_count++;
3692 obj->pin_filp = file;
3694 /* XXX - flush the CPU caches for pinned objects
3695 * as the X server doesn't manage domains yet
3697 i915_gem_object_flush_cpu_write_domain(obj);
3698 args->offset = i915_gem_obj_ggtt_offset(obj);
3700 drm_gem_object_unreference(&obj->base);
3702 mutex_unlock(&dev->struct_mutex);
3707 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3708 struct drm_file *file)
3710 struct drm_i915_gem_pin *args = data;
3711 struct drm_i915_gem_object *obj;
3714 ret = i915_mutex_lock_interruptible(dev);
3718 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3719 if (&obj->base == NULL) {
3724 if (obj->pin_filp != file) {
3725 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3730 obj->user_pin_count--;
3731 if (obj->user_pin_count == 0) {
3732 obj->pin_filp = NULL;
3733 i915_gem_object_unpin(obj);
3737 drm_gem_object_unreference(&obj->base);
3739 mutex_unlock(&dev->struct_mutex);
3744 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3745 struct drm_file *file)
3747 struct drm_i915_gem_busy *args = data;
3748 struct drm_i915_gem_object *obj;
3751 ret = i915_mutex_lock_interruptible(dev);
3755 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3756 if (&obj->base == NULL) {
3761 /* Count all active objects as busy, even if they are currently not used
3762 * by the gpu. Users of this interface expect objects to eventually
3763 * become non-busy without any further actions, therefore emit any
3764 * necessary flushes here.
3766 ret = i915_gem_object_flush_active(obj);
3768 args->busy = obj->active;
3770 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3771 args->busy |= intel_ring_flag(obj->ring) << 16;
3774 drm_gem_object_unreference(&obj->base);
3776 mutex_unlock(&dev->struct_mutex);
3781 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3782 struct drm_file *file_priv)
3784 return i915_gem_ring_throttle(dev, file_priv);
3788 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3789 struct drm_file *file_priv)
3791 struct drm_i915_gem_madvise *args = data;
3792 struct drm_i915_gem_object *obj;
3795 switch (args->madv) {
3796 case I915_MADV_DONTNEED:
3797 case I915_MADV_WILLNEED:
3803 ret = i915_mutex_lock_interruptible(dev);
3807 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3808 if (&obj->base == NULL) {
3813 if (obj->pin_count) {
3818 if (obj->madv != __I915_MADV_PURGED)
3819 obj->madv = args->madv;
3821 /* if the object is no longer attached, discard its backing storage */
3822 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3823 i915_gem_object_truncate(obj);
3825 args->retained = obj->madv != __I915_MADV_PURGED;
3828 drm_gem_object_unreference(&obj->base);
3830 mutex_unlock(&dev->struct_mutex);
3834 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3835 const struct drm_i915_gem_object_ops *ops)
3837 INIT_LIST_HEAD(&obj->mm_list);
3838 INIT_LIST_HEAD(&obj->global_list);
3839 INIT_LIST_HEAD(&obj->ring_list);
3840 INIT_LIST_HEAD(&obj->exec_list);
3844 obj->fence_reg = I915_FENCE_REG_NONE;
3845 obj->madv = I915_MADV_WILLNEED;
3846 /* Avoid an unnecessary call to unbind on the first bind. */
3847 obj->map_and_fenceable = true;
3849 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3852 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3853 .get_pages = i915_gem_object_get_pages_gtt,
3854 .put_pages = i915_gem_object_put_pages_gtt,
3857 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3860 struct drm_i915_gem_object *obj;
3861 struct address_space *mapping;
3864 obj = i915_gem_object_alloc(dev);
3868 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3869 i915_gem_object_free(obj);
3873 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3874 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3875 /* 965gm cannot relocate objects above 4GiB. */
3876 mask &= ~__GFP_HIGHMEM;
3877 mask |= __GFP_DMA32;
3880 mapping = file_inode(obj->base.filp)->i_mapping;
3881 mapping_set_gfp_mask(mapping, mask);
3883 i915_gem_object_init(obj, &i915_gem_object_ops);
3885 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3886 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3889 /* On some devices, we can have the GPU use the LLC (the CPU
3890 * cache) for about a 10% performance improvement
3891 * compared to uncached. Graphics requests other than
3892 * display scanout are coherent with the CPU in
3893 * accessing this cache. This means in this mode we
3894 * don't need to clflush on the CPU side, and on the
3895 * GPU side we only need to flush internal caches to
3896 * get data visible to the CPU.
3898 * However, we maintain the display planes as UC, and so
3899 * need to rebind when first used as such.
3901 obj->cache_level = I915_CACHE_LLC;
3903 obj->cache_level = I915_CACHE_NONE;
3908 int i915_gem_init_object(struct drm_gem_object *obj)
3915 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3917 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3918 struct drm_device *dev = obj->base.dev;
3919 drm_i915_private_t *dev_priv = dev->dev_private;
3921 trace_i915_gem_object_destroy(obj);
3924 i915_gem_detach_phys_object(dev, obj);
3927 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3928 bool was_interruptible;
3930 was_interruptible = dev_priv->mm.interruptible;
3931 dev_priv->mm.interruptible = false;
3933 WARN_ON(i915_gem_object_unbind(obj));
3935 dev_priv->mm.interruptible = was_interruptible;
3938 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3939 * before progressing. */
3941 i915_gem_object_unpin_pages(obj);
3943 if (WARN_ON(obj->pages_pin_count))
3944 obj->pages_pin_count = 0;
3945 i915_gem_object_put_pages(obj);
3946 i915_gem_object_free_mmap_offset(obj);
3947 i915_gem_object_release_stolen(obj);
3951 if (obj->base.import_attach)
3952 drm_prime_gem_destroy(&obj->base, NULL);
3954 drm_gem_object_release(&obj->base);
3955 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3958 i915_gem_object_free(obj);
3962 i915_gem_idle(struct drm_device *dev)
3964 drm_i915_private_t *dev_priv = dev->dev_private;
3967 if (dev_priv->ums.mm_suspended) {
3968 mutex_unlock(&dev->struct_mutex);
3972 ret = i915_gpu_idle(dev);
3974 mutex_unlock(&dev->struct_mutex);
3977 i915_gem_retire_requests(dev);
3979 /* Under UMS, be paranoid and evict. */
3980 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3981 i915_gem_evict_everything(dev);
3983 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
3985 i915_kernel_lost_context(dev);
3986 i915_gem_cleanup_ringbuffer(dev);
3988 /* Cancel the retire work handler, which should be idle now. */
3989 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3994 void i915_gem_l3_remap(struct drm_device *dev)
3996 drm_i915_private_t *dev_priv = dev->dev_private;
4000 if (!HAS_L3_GPU_CACHE(dev))
4003 if (!dev_priv->l3_parity.remap_info)
4006 misccpctl = I915_READ(GEN7_MISCCPCTL);
4007 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4008 POSTING_READ(GEN7_MISCCPCTL);
4010 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4011 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4012 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4013 DRM_DEBUG("0x%x was already programmed to %x\n",
4014 GEN7_L3LOG_BASE + i, remap);
4015 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4016 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4017 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4020 /* Make sure all the writes land before disabling dop clock gating */
4021 POSTING_READ(GEN7_L3LOG_BASE);
4023 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4026 void i915_gem_init_swizzling(struct drm_device *dev)
4028 drm_i915_private_t *dev_priv = dev->dev_private;
4030 if (INTEL_INFO(dev)->gen < 5 ||
4031 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4034 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4035 DISP_TILE_SURFACE_SWIZZLING);
4040 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4042 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4043 else if (IS_GEN7(dev))
4044 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4050 intel_enable_blt(struct drm_device *dev)
4055 /* The blitter was dysfunctional on early prototypes */
4056 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4057 DRM_INFO("BLT not supported on this pre-production hardware;"
4058 " graphics performance will be degraded.\n");
4065 static int i915_gem_init_rings(struct drm_device *dev)
4067 struct drm_i915_private *dev_priv = dev->dev_private;
4070 ret = intel_init_render_ring_buffer(dev);
4075 ret = intel_init_bsd_ring_buffer(dev);
4077 goto cleanup_render_ring;
4080 if (intel_enable_blt(dev)) {
4081 ret = intel_init_blt_ring_buffer(dev);
4083 goto cleanup_bsd_ring;
4086 if (HAS_VEBOX(dev)) {
4087 ret = intel_init_vebox_ring_buffer(dev);
4089 goto cleanup_blt_ring;
4093 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4095 goto cleanup_vebox_ring;
4100 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4102 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4104 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4105 cleanup_render_ring:
4106 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4112 i915_gem_init_hw(struct drm_device *dev)
4114 drm_i915_private_t *dev_priv = dev->dev_private;
4117 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4120 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
4121 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4123 if (HAS_PCH_NOP(dev)) {
4124 u32 temp = I915_READ(GEN7_MSG_CTL);
4125 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4126 I915_WRITE(GEN7_MSG_CTL, temp);
4129 i915_gem_l3_remap(dev);
4131 i915_gem_init_swizzling(dev);
4133 ret = i915_gem_init_rings(dev);
4138 * XXX: There was some w/a described somewhere suggesting loading
4139 * contexts before PPGTT.
4141 i915_gem_context_init(dev);
4142 if (dev_priv->mm.aliasing_ppgtt) {
4143 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4145 i915_gem_cleanup_aliasing_ppgtt(dev);
4146 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4153 int i915_gem_init(struct drm_device *dev)
4155 struct drm_i915_private *dev_priv = dev->dev_private;
4158 mutex_lock(&dev->struct_mutex);
4160 if (IS_VALLEYVIEW(dev)) {
4161 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4162 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4163 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4164 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4167 i915_gem_init_global_gtt(dev);
4169 ret = i915_gem_init_hw(dev);
4170 mutex_unlock(&dev->struct_mutex);
4172 i915_gem_cleanup_aliasing_ppgtt(dev);
4176 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4177 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4178 dev_priv->dri1.allow_batchbuffer = 1;
4183 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4185 drm_i915_private_t *dev_priv = dev->dev_private;
4186 struct intel_ring_buffer *ring;
4189 for_each_ring(ring, dev_priv, i)
4190 intel_cleanup_ring_buffer(ring);
4194 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4195 struct drm_file *file_priv)
4197 struct drm_i915_private *dev_priv = dev->dev_private;
4200 if (drm_core_check_feature(dev, DRIVER_MODESET))
4203 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4204 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4205 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4208 mutex_lock(&dev->struct_mutex);
4209 dev_priv->ums.mm_suspended = 0;
4211 ret = i915_gem_init_hw(dev);
4213 mutex_unlock(&dev->struct_mutex);
4217 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4218 mutex_unlock(&dev->struct_mutex);
4220 ret = drm_irq_install(dev);
4222 goto cleanup_ringbuffer;
4227 mutex_lock(&dev->struct_mutex);
4228 i915_gem_cleanup_ringbuffer(dev);
4229 dev_priv->ums.mm_suspended = 1;
4230 mutex_unlock(&dev->struct_mutex);
4236 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4237 struct drm_file *file_priv)
4239 struct drm_i915_private *dev_priv = dev->dev_private;
4242 if (drm_core_check_feature(dev, DRIVER_MODESET))
4245 drm_irq_uninstall(dev);
4247 mutex_lock(&dev->struct_mutex);
4248 ret = i915_gem_idle(dev);
4250 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4251 * We need to replace this with a semaphore, or something.
4252 * And not confound ums.mm_suspended!
4255 dev_priv->ums.mm_suspended = 1;
4256 mutex_unlock(&dev->struct_mutex);
4262 i915_gem_lastclose(struct drm_device *dev)
4266 if (drm_core_check_feature(dev, DRIVER_MODESET))
4269 mutex_lock(&dev->struct_mutex);
4270 ret = i915_gem_idle(dev);
4272 DRM_ERROR("failed to idle hardware: %d\n", ret);
4273 mutex_unlock(&dev->struct_mutex);
4277 init_ring_lists(struct intel_ring_buffer *ring)
4279 INIT_LIST_HEAD(&ring->active_list);
4280 INIT_LIST_HEAD(&ring->request_list);
4284 i915_gem_load(struct drm_device *dev)
4286 drm_i915_private_t *dev_priv = dev->dev_private;
4290 kmem_cache_create("i915_gem_object",
4291 sizeof(struct drm_i915_gem_object), 0,
4295 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4296 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4297 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4298 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4299 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4300 for (i = 0; i < I915_NUM_RINGS; i++)
4301 init_ring_lists(&dev_priv->ring[i]);
4302 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4303 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4304 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4305 i915_gem_retire_work_handler);
4306 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4308 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4310 I915_WRITE(MI_ARB_STATE,
4311 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4314 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4316 /* Old X drivers will take 0-2 for front, back, depth buffers */
4317 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4318 dev_priv->fence_reg_start = 3;
4320 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4321 dev_priv->num_fence_regs = 32;
4322 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4323 dev_priv->num_fence_regs = 16;
4325 dev_priv->num_fence_regs = 8;
4327 /* Initialize fence registers to zero */
4328 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4329 i915_gem_restore_fences(dev);
4331 i915_gem_detect_bit_6_swizzle(dev);
4332 init_waitqueue_head(&dev_priv->pending_flip_queue);
4334 dev_priv->mm.interruptible = true;
4336 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4337 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4338 register_shrinker(&dev_priv->mm.inactive_shrinker);
4342 * Create a physically contiguous memory object for this object
4343 * e.g. for cursor + overlay regs
4345 static int i915_gem_init_phys_object(struct drm_device *dev,
4346 int id, int size, int align)
4348 drm_i915_private_t *dev_priv = dev->dev_private;
4349 struct drm_i915_gem_phys_object *phys_obj;
4352 if (dev_priv->mm.phys_objs[id - 1] || !size)
4355 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4361 phys_obj->handle = drm_pci_alloc(dev, size, align);
4362 if (!phys_obj->handle) {
4367 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4370 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4378 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4380 drm_i915_private_t *dev_priv = dev->dev_private;
4381 struct drm_i915_gem_phys_object *phys_obj;
4383 if (!dev_priv->mm.phys_objs[id - 1])
4386 phys_obj = dev_priv->mm.phys_objs[id - 1];
4387 if (phys_obj->cur_obj) {
4388 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4392 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4394 drm_pci_free(dev, phys_obj->handle);
4396 dev_priv->mm.phys_objs[id - 1] = NULL;
4399 void i915_gem_free_all_phys_object(struct drm_device *dev)
4403 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4404 i915_gem_free_phys_object(dev, i);
4407 void i915_gem_detach_phys_object(struct drm_device *dev,
4408 struct drm_i915_gem_object *obj)
4410 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4417 vaddr = obj->phys_obj->handle->vaddr;
4419 page_count = obj->base.size / PAGE_SIZE;
4420 for (i = 0; i < page_count; i++) {
4421 struct page *page = shmem_read_mapping_page(mapping, i);
4422 if (!IS_ERR(page)) {
4423 char *dst = kmap_atomic(page);
4424 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4427 drm_clflush_pages(&page, 1);
4429 set_page_dirty(page);
4430 mark_page_accessed(page);
4431 page_cache_release(page);
4434 i915_gem_chipset_flush(dev);
4436 obj->phys_obj->cur_obj = NULL;
4437 obj->phys_obj = NULL;
4441 i915_gem_attach_phys_object(struct drm_device *dev,
4442 struct drm_i915_gem_object *obj,
4446 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4447 drm_i915_private_t *dev_priv = dev->dev_private;
4452 if (id > I915_MAX_PHYS_OBJECT)
4455 if (obj->phys_obj) {
4456 if (obj->phys_obj->id == id)
4458 i915_gem_detach_phys_object(dev, obj);
4461 /* create a new object */
4462 if (!dev_priv->mm.phys_objs[id - 1]) {
4463 ret = i915_gem_init_phys_object(dev, id,
4464 obj->base.size, align);
4466 DRM_ERROR("failed to init phys object %d size: %zu\n",
4467 id, obj->base.size);
4472 /* bind to the object */
4473 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4474 obj->phys_obj->cur_obj = obj;
4476 page_count = obj->base.size / PAGE_SIZE;
4478 for (i = 0; i < page_count; i++) {
4482 page = shmem_read_mapping_page(mapping, i);
4484 return PTR_ERR(page);
4486 src = kmap_atomic(page);
4487 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4488 memcpy(dst, src, PAGE_SIZE);
4491 mark_page_accessed(page);
4492 page_cache_release(page);
4499 i915_gem_phys_pwrite(struct drm_device *dev,
4500 struct drm_i915_gem_object *obj,
4501 struct drm_i915_gem_pwrite *args,
4502 struct drm_file *file_priv)
4504 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4505 char __user *user_data = to_user_ptr(args->data_ptr);
4507 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4508 unsigned long unwritten;
4510 /* The physical object once assigned is fixed for the lifetime
4511 * of the obj, so we can safely drop the lock and continue
4514 mutex_unlock(&dev->struct_mutex);
4515 unwritten = copy_from_user(vaddr, user_data, args->size);
4516 mutex_lock(&dev->struct_mutex);
4521 i915_gem_chipset_flush(dev);
4525 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4527 struct drm_i915_file_private *file_priv = file->driver_priv;
4529 /* Clean up our request list when the client is going away, so that
4530 * later retire_requests won't dereference our soon-to-be-gone
4533 spin_lock(&file_priv->mm.lock);
4534 while (!list_empty(&file_priv->mm.request_list)) {
4535 struct drm_i915_gem_request *request;
4537 request = list_first_entry(&file_priv->mm.request_list,
4538 struct drm_i915_gem_request,
4540 list_del(&request->client_list);
4541 request->file_priv = NULL;
4543 spin_unlock(&file_priv->mm.lock);
4546 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4548 if (!mutex_is_locked(mutex))
4551 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4552 return mutex->owner == task;
4554 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4560 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4562 struct drm_i915_private *dev_priv =
4563 container_of(shrinker,
4564 struct drm_i915_private,
4565 mm.inactive_shrinker);
4566 struct drm_device *dev = dev_priv->dev;
4567 struct drm_i915_gem_object *obj;
4568 int nr_to_scan = sc->nr_to_scan;
4572 if (!mutex_trylock(&dev->struct_mutex)) {
4573 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4576 if (dev_priv->mm.shrinker_no_lock_stealing)
4583 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4585 nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4588 i915_gem_shrink_all(dev_priv);
4592 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4593 if (obj->pages_pin_count == 0)
4594 cnt += obj->base.size >> PAGE_SHIFT;
4595 list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list)
4596 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4597 cnt += obj->base.size >> PAGE_SHIFT;
4600 mutex_unlock(&dev->struct_mutex);