drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/shmem_fs.h>
  35 #include <linux/slab.h>
  36 #include <linux/swap.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-buf.h>
  39
  40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  42 static __must_check int
  43 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
  44                            struct i915_address_space *vm,
  45                            unsigned alignment,
  46                            bool map_and_fenceable,
  47                            bool nonblocking);
  48 static int i915_gem_phys_pwrite(struct drm_device *dev,
  49                                 struct drm_i915_gem_object *obj,
  50                                 struct drm_i915_gem_pwrite *args,
  51                                 struct drm_file *file);
  52
  53 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  54                                  struct drm_i915_gem_object *obj);
  55 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  56                                          struct drm_i915_fence_reg *fence,
  57                                          bool enable);
  58
  59 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  60                                     struct shrink_control *sc);
  61 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  62 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  63 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  64
  65 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  66 {
  67         if (obj->tiling_mode)
  68                 i915_gem_release_mmap(obj);
  69
  70         /* As we do not have an associated fence register, we will force
  71          * a tiling change if we ever need to acquire one.
  72          */
  73         obj->fence_dirty = false;
  74         obj->fence_reg = I915_FENCE_REG_NONE;
  75 }
  76
  77 /* some bookkeeping */
  78 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  79                                   size_t size)
  80 {
  81         spin_lock(&dev_priv->mm.object_stat_lock);
  82         dev_priv->mm.object_count++;
  83         dev_priv->mm.object_memory += size;
  84         spin_unlock(&dev_priv->mm.object_stat_lock);
  85 }
  86
  87 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  88                                      size_t size)
  89 {
  90         spin_lock(&dev_priv->mm.object_stat_lock);
  91         dev_priv->mm.object_count--;
  92         dev_priv->mm.object_memory -= size;
  93         spin_unlock(&dev_priv->mm.object_stat_lock);
  94 }
  95
  96 static int
  97 i915_gem_wait_for_error(struct i915_gpu_error *error)
  98 {
  99         int ret;
 100
 101 #define EXIT_COND (!i915_reset_in_progress(error) || \
 102                    i915_terminally_wedged(error))
 103         if (EXIT_COND)
 104                 return 0;
 105
 106         /*
 107          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 108          * userspace. If it takes that long something really bad is going on and
 109          * we should simply try to bail out and fail as gracefully as possible.
 110          */
 111         ret = wait_event_interruptible_timeout(error->reset_queue,
 112                                                EXIT_COND,
 113                                                10*HZ);
 114         if (ret == 0) {
 115                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 116                 return -EIO;
 117         } else if (ret < 0) {
 118                 return ret;
 119         }
 120 #undef EXIT_COND
 121
 122         return 0;
 123 }
 124
 125 int i915_mutex_lock_interruptible(struct drm_device *dev)
 126 {
 127         struct drm_i915_private *dev_priv = dev->dev_private;
 128         int ret;
 129
 130         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 131         if (ret)
 132                 return ret;
 133
 134         ret = mutex_lock_interruptible(&dev->struct_mutex);
 135         if (ret)
 136                 return ret;
 137
 138         WARN_ON(i915_verify_lists(dev));
 139         return 0;
 140 }
 141
 142 static inline bool
 143 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 144 {
 145         return i915_gem_obj_bound_any(obj) && !obj->active;
 146 }
 147
 148 int
 149 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 150                     struct drm_file *file)
 151 {
 152         struct drm_i915_private *dev_priv = dev->dev_private;
 153         struct drm_i915_gem_init *args = data;
 154
 155         if (drm_core_check_feature(dev, DRIVER_MODESET))
 156                 return -ENODEV;
 157
 158         if (args->gtt_start >= args->gtt_end ||
 159             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 160                 return -EINVAL;
 161
 162         /* GEM with user mode setting was never supported on ilk and later. */
 163         if (INTEL_INFO(dev)->gen >= 5)
 164                 return -ENODEV;
 165
 166         mutex_lock(&dev->struct_mutex);
 167         i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
 168                                   args->gtt_end);
 169         dev_priv->gtt.mappable_end = args->gtt_end;
 170         mutex_unlock(&dev->struct_mutex);
 171
 172         return 0;
 173 }
 174
 175 int
 176 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 177                             struct drm_file *file)
 178 {
 179         struct drm_i915_private *dev_priv = dev->dev_private;
 180         struct drm_i915_gem_get_aperture *args = data;
 181         struct drm_i915_gem_object *obj;
 182         size_t pinned;
 183
 184         pinned = 0;
 185         mutex_lock(&dev->struct_mutex);
 186         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 187                 if (obj->pin_count)
 188                         pinned += i915_gem_obj_ggtt_size(obj);
 189         mutex_unlock(&dev->struct_mutex);
 190
 191         args->aper_size = dev_priv->gtt.base.total;
 192         args->aper_available_size = args->aper_size - pinned;
 193
 194         return 0;
 195 }
 196
 197 void *i915_gem_object_alloc(struct drm_device *dev)
 198 {
 199         struct drm_i915_private *dev_priv = dev->dev_private;
 200         return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
 201 }
 202
 203 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 204 {
 205         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 206         kmem_cache_free(dev_priv->slab, obj);
 207 }
 208
 209 static int
 210 i915_gem_create(struct drm_file *file,
 211                 struct drm_device *dev,
 212                 uint64_t size,
 213                 uint32_t *handle_p)
 214 {
 215         struct drm_i915_gem_object *obj;
 216         int ret;
 217         u32 handle;
 218
 219         size = roundup(size, PAGE_SIZE);
 220         if (size == 0)
 221                 return -EINVAL;
 222
 223         /* Allocate the new object */
 224         obj = i915_gem_alloc_object(dev, size);
 225         if (obj == NULL)
 226                 return -ENOMEM;
 227
 228         ret = drm_gem_handle_create(file, &obj->base, &handle);
 229         /* drop reference from allocate - handle holds it now */
 230         drm_gem_object_unreference_unlocked(&obj->base);
 231         if (ret)
 232                 return ret;
 233
 234         *handle_p = handle;
 235         return 0;
 236 }
 237
 238 int
 239 i915_gem_dumb_create(struct drm_file *file,
 240                      struct drm_device *dev,
 241                      struct drm_mode_create_dumb *args)
 242 {
 243         /* have to work out size/pitch and return them */
 244         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 245         args->size = args->pitch * args->height;
 246         return i915_gem_create(file, dev,
 247                                args->size, &args->handle);
 248 }
 249
 250 /**
 251  * Creates a new mm object and returns a handle to it.
 252  */
 253 int
 254 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 255                       struct drm_file *file)
 256 {
 257         struct drm_i915_gem_create *args = data;
 258
 259         return i915_gem_create(file, dev,
 260                                args->size, &args->handle);
 261 }
 262
 263 static inline int
 264 __copy_to_user_swizzled(char __user *cpu_vaddr,
 265                         const char *gpu_vaddr, int gpu_offset,
 266                         int length)
 267 {
 268         int ret, cpu_offset = 0;
 269
 270         while (length > 0) {
 271                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 272                 int this_length = min(cacheline_end - gpu_offset, length);
 273                 int swizzled_gpu_offset = gpu_offset ^ 64;
 274
 275                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 276                                      gpu_vaddr + swizzled_gpu_offset,
 277                                      this_length);
 278                 if (ret)
 279                         return ret + length;
 280
 281                 cpu_offset += this_length;
 282                 gpu_offset += this_length;
 283                 length -= this_length;
 284         }
 285
 286         return 0;
 287 }
 288
 289 static inline int
 290 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 291                           const char __user *cpu_vaddr,
 292                           int length)
 293 {
 294         int ret, cpu_offset = 0;
 295
 296         while (length > 0) {
 297                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 298                 int this_length = min(cacheline_end - gpu_offset, length);
 299                 int swizzled_gpu_offset = gpu_offset ^ 64;
 300
 301                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 302                                        cpu_vaddr + cpu_offset,
 303                                        this_length);
 304                 if (ret)
 305                         return ret + length;
 306
 307                 cpu_offset += this_length;
 308                 gpu_offset += this_length;
 309                 length -= this_length;
 310         }
 311
 312         return 0;
 313 }
 314
 315 /* Per-page copy function for the shmem pread fastpath.
 316  * Flushes invalid cachelines before reading the target if
 317  * needs_clflush is set. */
 318 static int
 319 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 320                  char __user *user_data,
 321                  bool page_do_bit17_swizzling, bool needs_clflush)
 322 {
 323         char *vaddr;
 324         int ret;
 325
 326         if (unlikely(page_do_bit17_swizzling))
 327                 return -EINVAL;
 328
 329         vaddr = kmap_atomic(page);
 330         if (needs_clflush)
 331                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 332                                        page_length);
 333         ret = __copy_to_user_inatomic(user_data,
 334                                       vaddr + shmem_page_offset,
 335                                       page_length);
 336         kunmap_atomic(vaddr);
 337
 338         return ret ? -EFAULT : 0;
 339 }
 340
 341 static void
 342 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 343                              bool swizzled)
 344 {
 345         if (unlikely(swizzled)) {
 346                 unsigned long start = (unsigned long) addr;
 347                 unsigned long end = (unsigned long) addr + length;
 348
 349                 /* For swizzling simply ensure that we always flush both
 350                  * channels. Lame, but simple and it works. Swizzled
 351                  * pwrite/pread is far from a hotpath - current userspace
 352                  * doesn't use it at all. */
 353                 start = round_down(start, 128);
 354                 end = round_up(end, 128);
 355
 356                 drm_clflush_virt_range((void *)start, end - start);
 357         } else {
 358                 drm_clflush_virt_range(addr, length);
 359         }
 360
 361 }
 362
 363 /* Only difference to the fast-path function is that this can handle bit17
 364  * and uses non-atomic copy and kmap functions. */
 365 static int
 366 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 367                  char __user *user_data,
 368                  bool page_do_bit17_swizzling, bool needs_clflush)
 369 {
 370         char *vaddr;
 371         int ret;
 372
 373         vaddr = kmap(page);
 374         if (needs_clflush)
 375                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 376                                              page_length,
 377                                              page_do_bit17_swizzling);
 378
 379         if (page_do_bit17_swizzling)
 380                 ret = __copy_to_user_swizzled(user_data,
 381                                               vaddr, shmem_page_offset,
 382                                               page_length);
 383         else
 384                 ret = __copy_to_user(user_data,
 385                                      vaddr + shmem_page_offset,
 386                                      page_length);
 387         kunmap(page);
 388
 389         return ret ? - EFAULT : 0;
 390 }
 391
 392 static int
 393 i915_gem_shmem_pread(struct drm_device *dev,
 394                      struct drm_i915_gem_object *obj,
 395                      struct drm_i915_gem_pread *args,
 396                      struct drm_file *file)
 397 {
 398         char __user *user_data;
 399         ssize_t remain;
 400         loff_t offset;
 401         int shmem_page_offset, page_length, ret = 0;
 402         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 403         int prefaulted = 0;
 404         int needs_clflush = 0;
 405         struct sg_page_iter sg_iter;
 406
 407         user_data = to_user_ptr(args->data_ptr);
 408         remain = args->size;
 409
 410         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 411
 412         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 413                 /* If we're not in the cpu read domain, set ourself into the gtt
 414                  * read domain and manually flush cachelines (if required). This
 415                  * optimizes for the case when the gpu will dirty the data
 416                  * anyway again before the next pread happens. */
 417                 if (obj->cache_level == I915_CACHE_NONE)
 418                         needs_clflush = 1;
 419                 if (i915_gem_obj_bound_any(obj)) {
 420                         ret = i915_gem_object_set_to_gtt_domain(obj, false);
 421                         if (ret)
 422                                 return ret;
 423                 }
 424         }
 425
 426         ret = i915_gem_object_get_pages(obj);
 427         if (ret)
 428                 return ret;
 429
 430         i915_gem_object_pin_pages(obj);
 431
 432         offset = args->offset;
 433
 434         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 435                          offset >> PAGE_SHIFT) {
 436                 struct page *page = sg_page_iter_page(&sg_iter);
 437
 438                 if (remain <= 0)
 439                         break;
 440
 441                 /* Operation in this page
 442                  *
 443                  * shmem_page_offset = offset within page in shmem file
 444                  * page_length = bytes to copy for this page
 445                  */
 446                 shmem_page_offset = offset_in_page(offset);
 447                 page_length = remain;
 448                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 449                         page_length = PAGE_SIZE - shmem_page_offset;
 450
 451                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 452                         (page_to_phys(page) & (1 << 17)) != 0;
 453
 454                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 455                                        user_data, page_do_bit17_swizzling,
 456                                        needs_clflush);
 457                 if (ret == 0)
 458                         goto next_page;
 459
 460                 mutex_unlock(&dev->struct_mutex);
 461
 462                 if (likely(!i915_prefault_disable) && !prefaulted) {
 463                         ret = fault_in_multipages_writeable(user_data, remain);
 464                         /* Userspace is tricking us, but we've already clobbered
 465                          * its pages with the prefault and promised to write the
 466                          * data up to the first fault. Hence ignore any errors
 467                          * and just continue. */
 468                         (void)ret;
 469                         prefaulted = 1;
 470                 }
 471
 472                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 473                                        user_data, page_do_bit17_swizzling,
 474                                        needs_clflush);
 475
 476                 mutex_lock(&dev->struct_mutex);
 477
 478 next_page:
 479                 mark_page_accessed(page);
 480
 481                 if (ret)
 482                         goto out;
 483
 484                 remain -= page_length;
 485                 user_data += page_length;
 486                 offset += page_length;
 487         }
 488
 489 out:
 490         i915_gem_object_unpin_pages(obj);
 491
 492         return ret;
 493 }
 494
 495 /**
 496  * Reads data from the object referenced by handle.
 497  *
 498  * On error, the contents of *data are undefined.
 499  */
 500 int
 501 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 502                      struct drm_file *file)
 503 {
 504         struct drm_i915_gem_pread *args = data;
 505         struct drm_i915_gem_object *obj;
 506         int ret = 0;
 507
 508         if (args->size == 0)
 509                 return 0;
 510
 511         if (!access_ok(VERIFY_WRITE,
 512                        to_user_ptr(args->data_ptr),
 513                        args->size))
 514                 return -EFAULT;
 515
 516         ret = i915_mutex_lock_interruptible(dev);
 517         if (ret)
 518                 return ret;
 519
 520         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 521         if (&obj->base == NULL) {
 522                 ret = -ENOENT;
 523                 goto unlock;
 524         }
 525
 526         /* Bounds check source.  */
 527         if (args->offset > obj->base.size ||
 528             args->size > obj->base.size - args->offset) {
 529                 ret = -EINVAL;
 530                 goto out;
 531         }
 532
 533         /* prime objects have no backing filp to GEM pread/pwrite
 534          * pages from.
 535          */
 536         if (!obj->base.filp) {
 537                 ret = -EINVAL;
 538                 goto out;
 539         }
 540
 541         trace_i915_gem_object_pread(obj, args->offset, args->size);
 542
 543         ret = i915_gem_shmem_pread(dev, obj, args, file);
 544
 545 out:
 546         drm_gem_object_unreference(&obj->base);
 547 unlock:
 548         mutex_unlock(&dev->struct_mutex);
 549         return ret;
 550 }
 551
 552 /* This is the fast write path which cannot handle
 553  * page faults in the source data
 554  */
 555
 556 static inline int
 557 fast_user_write(struct io_mapping *mapping,
 558                 loff_t page_base, int page_offset,
 559                 char __user *user_data,
 560                 int length)
 561 {
 562         void __iomem *vaddr_atomic;
 563         void *vaddr;
 564         unsigned long unwritten;
 565
 566         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 567         /* We can use the cpu mem copy function because this is X86. */
 568         vaddr = (void __force*)vaddr_atomic + page_offset;
 569         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 570                                                       user_data, length);
 571         io_mapping_unmap_atomic(vaddr_atomic);
 572         return unwritten;
 573 }
 574
 575 /**
 576  * This is the fast pwrite path, where we copy the data directly from the
 577  * user into the GTT, uncached.
 578  */
 579 static int
 580 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 581                          struct drm_i915_gem_object *obj,
 582                          struct drm_i915_gem_pwrite *args,
 583                          struct drm_file *file)
 584 {
 585         drm_i915_private_t *dev_priv = dev->dev_private;
 586         ssize_t remain;
 587         loff_t offset, page_base;
 588         char __user *user_data;
 589         int page_offset, page_length, ret;
 590
 591         ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
 592         if (ret)
 593                 goto out;
 594
 595         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 596         if (ret)
 597                 goto out_unpin;
 598
 599         ret = i915_gem_object_put_fence(obj);
 600         if (ret)
 601                 goto out_unpin;
 602
 603         user_data = to_user_ptr(args->data_ptr);
 604         remain = args->size;
 605
 606         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 607
 608         while (remain > 0) {
 609                 /* Operation in this page
 610                  *
 611                  * page_base = page offset within aperture
 612                  * page_offset = offset within page
 613                  * page_length = bytes to copy for this page
 614                  */
 615                 page_base = offset & PAGE_MASK;
 616                 page_offset = offset_in_page(offset);
 617                 page_length = remain;
 618                 if ((page_offset + remain) > PAGE_SIZE)
 619                         page_length = PAGE_SIZE - page_offset;
 620
 621                 /* If we get a fault while copying data, then (presumably) our
 622                  * source page isn't available.  Return the error and we'll
 623                  * retry in the slow path.
 624                  */
 625                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 626                                     page_offset, user_data, page_length)) {
 627                         ret = -EFAULT;
 628                         goto out_unpin;
 629                 }
 630
 631                 remain -= page_length;
 632                 user_data += page_length;
 633                 offset += page_length;
 634         }
 635
 636 out_unpin:
 637         i915_gem_object_unpin(obj);
 638 out:
 639         return ret;
 640 }
 641
 642 /* Per-page copy function for the shmem pwrite fastpath.
 643  * Flushes invalid cachelines before writing to the target if
 644  * needs_clflush_before is set and flushes out any written cachelines after
 645  * writing if needs_clflush is set. */
 646 static int
 647 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 648                   char __user *user_data,
 649                   bool page_do_bit17_swizzling,
 650                   bool needs_clflush_before,
 651                   bool needs_clflush_after)
 652 {
 653         char *vaddr;
 654         int ret;
 655
 656         if (unlikely(page_do_bit17_swizzling))
 657                 return -EINVAL;
 658
 659         vaddr = kmap_atomic(page);
 660         if (needs_clflush_before)
 661                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 662                                        page_length);
 663         ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
 664                                                 user_data,
 665                                                 page_length);
 666         if (needs_clflush_after)
 667                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 668                                        page_length);
 669         kunmap_atomic(vaddr);
 670
 671         return ret ? -EFAULT : 0;
 672 }
 673
 674 /* Only difference to the fast-path function is that this can handle bit17
 675  * and uses non-atomic copy and kmap functions. */
 676 static int
 677 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 678                   char __user *user_data,
 679                   bool page_do_bit17_swizzling,
 680                   bool needs_clflush_before,
 681                   bool needs_clflush_after)
 682 {
 683         char *vaddr;
 684         int ret;
 685
 686         vaddr = kmap(page);
 687         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 688                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 689                                              page_length,
 690                                              page_do_bit17_swizzling);
 691         if (page_do_bit17_swizzling)
 692                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 693                                                 user_data,
 694                                                 page_length);
 695         else
 696                 ret = __copy_from_user(vaddr + shmem_page_offset,
 697                                        user_data,
 698                                        page_length);
 699         if (needs_clflush_after)
 700                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 701                                              page_length,
 702                                              page_do_bit17_swizzling);
 703         kunmap(page);
 704
 705         return ret ? -EFAULT : 0;
 706 }
 707
 708 static int
 709 i915_gem_shmem_pwrite(struct drm_device *dev,
 710                       struct drm_i915_gem_object *obj,
 711                       struct drm_i915_gem_pwrite *args,
 712                       struct drm_file *file)
 713 {
 714         ssize_t remain;
 715         loff_t offset;
 716         char __user *user_data;
 717         int shmem_page_offset, page_length, ret = 0;
 718         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 719         int hit_slowpath = 0;
 720         int needs_clflush_after = 0;
 721         int needs_clflush_before = 0;
 722         struct sg_page_iter sg_iter;
 723
 724         user_data = to_user_ptr(args->data_ptr);
 725         remain = args->size;
 726
 727         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 728
 729         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 730                 /* If we're not in the cpu write domain, set ourself into the gtt
 731                  * write domain and manually flush cachelines (if required). This
 732                  * optimizes for the case when the gpu will use the data
 733                  * right away and we therefore have to clflush anyway. */
 734                 if (obj->cache_level == I915_CACHE_NONE)
 735                         needs_clflush_after = 1;
 736                 if (i915_gem_obj_bound_any(obj)) {
 737                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 738                         if (ret)
 739                                 return ret;
 740                 }
 741         }
 742         /* Same trick applies for invalidate partially written cachelines before
 743          * writing.  */
 744         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
 745             && obj->cache_level == I915_CACHE_NONE)
 746                 needs_clflush_before = 1;
 747
 748         ret = i915_gem_object_get_pages(obj);
 749         if (ret)
 750                 return ret;
 751
 752         i915_gem_object_pin_pages(obj);
 753
 754         offset = args->offset;
 755         obj->dirty = 1;
 756
 757         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 758                          offset >> PAGE_SHIFT) {
 759                 struct page *page = sg_page_iter_page(&sg_iter);
 760                 int partial_cacheline_write;
 761
 762                 if (remain <= 0)
 763                         break;
 764
 765                 /* Operation in this page
 766                  *
 767                  * shmem_page_offset = offset within page in shmem file
 768                  * page_length = bytes to copy for this page
 769                  */
 770                 shmem_page_offset = offset_in_page(offset);
 771
 772                 page_length = remain;
 773                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 774                         page_length = PAGE_SIZE - shmem_page_offset;
 775
 776                 /* If we don't overwrite a cacheline completely we need to be
 777                  * careful to have up-to-date data by first clflushing. Don't
 778                  * overcomplicate things and flush the entire patch. */
 779                 partial_cacheline_write = needs_clflush_before &&
 780                         ((shmem_page_offset | page_length)
 781                                 & (boot_cpu_data.x86_clflush_size - 1));
 782
 783                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 784                         (page_to_phys(page) & (1 << 17)) != 0;
 785
 786                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 787                                         user_data, page_do_bit17_swizzling,
 788                                         partial_cacheline_write,
 789                                         needs_clflush_after);
 790                 if (ret == 0)
 791                         goto next_page;
 792
 793                 hit_slowpath = 1;
 794                 mutex_unlock(&dev->struct_mutex);
 795                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 796                                         user_data, page_do_bit17_swizzling,
 797                                         partial_cacheline_write,
 798                                         needs_clflush_after);
 799
 800                 mutex_lock(&dev->struct_mutex);
 801
 802 next_page:
 803                 set_page_dirty(page);
 804                 mark_page_accessed(page);
 805
 806                 if (ret)
 807                         goto out;
 808
 809                 remain -= page_length;
 810                 user_data += page_length;
 811                 offset += page_length;
 812         }
 813
 814 out:
 815         i915_gem_object_unpin_pages(obj);
 816
 817         if (hit_slowpath) {
 818                 /*
 819                  * Fixup: Flush cpu caches in case we didn't flush the dirty
 820                  * cachelines in-line while writing and the object moved
 821                  * out of the cpu write domain while we've dropped the lock.
 822                  */
 823                 if (!needs_clflush_after &&
 824                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 825                         i915_gem_clflush_object(obj);
 826                         i915_gem_chipset_flush(dev);
 827                 }
 828         }
 829
 830         if (needs_clflush_after)
 831                 i915_gem_chipset_flush(dev);
 832
 833         return ret;
 834 }
 835
 836 /**
 837  * Writes data to the object referenced by handle.
 838  *
 839  * On error, the contents of the buffer that were to be modified are undefined.
 840  */
 841 int
 842 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 843                       struct drm_file *file)
 844 {
 845         struct drm_i915_gem_pwrite *args = data;
 846         struct drm_i915_gem_object *obj;
 847         int ret;
 848
 849         if (args->size == 0)
 850                 return 0;
 851
 852         if (!access_ok(VERIFY_READ,
 853                        to_user_ptr(args->data_ptr),
 854                        args->size))
 855                 return -EFAULT;
 856
 857         if (likely(!i915_prefault_disable)) {
 858                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
 859                                                    args->size);
 860                 if (ret)
 861                         return -EFAULT;
 862         }
 863
 864         ret = i915_mutex_lock_interruptible(dev);
 865         if (ret)
 866                 return ret;
 867
 868         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 869         if (&obj->base == NULL) {
 870                 ret = -ENOENT;
 871                 goto unlock;
 872         }
 873
 874         /* Bounds check destination. */
 875         if (args->offset > obj->base.size ||
 876             args->size > obj->base.size - args->offset) {
 877                 ret = -EINVAL;
 878                 goto out;
 879         }
 880
 881         /* prime objects have no backing filp to GEM pread/pwrite
 882          * pages from.
 883          */
 884         if (!obj->base.filp) {
 885                 ret = -EINVAL;
 886                 goto out;
 887         }
 888
 889         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 890
 891         ret = -EFAULT;
 892         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 893          * it would end up going through the fenced access, and we'll get
 894          * different detiling behavior between reading and writing.
 895          * pread/pwrite currently are reading and writing from the CPU
 896          * perspective, requiring manual detiling by the client.
 897          */
 898         if (obj->phys_obj) {
 899                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 900                 goto out;
 901         }
 902
 903         if (obj->cache_level == I915_CACHE_NONE &&
 904             obj->tiling_mode == I915_TILING_NONE &&
 905             obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 906                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
 907                 /* Note that the gtt paths might fail with non-page-backed user
 908                  * pointers (e.g. gtt mappings when moving data between
 909                  * textures). Fallback to the shmem path in that case. */
 910         }
 911
 912         if (ret == -EFAULT || ret == -ENOSPC)
 913                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
 914
 915 out:
 916         drm_gem_object_unreference(&obj->base);
 917 unlock:
 918         mutex_unlock(&dev->struct_mutex);
 919         return ret;
 920 }
 921
 922 int
 923 i915_gem_check_wedge(struct i915_gpu_error *error,
 924                      bool interruptible)
 925 {
 926         if (i915_reset_in_progress(error)) {
 927                 /* Non-interruptible callers can't handle -EAGAIN, hence return
 928                  * -EIO unconditionally for these. */
 929                 if (!interruptible)
 930                         return -EIO;
 931
 932                 /* Recovery complete, but the reset failed ... */
 933                 if (i915_terminally_wedged(error))
 934                         return -EIO;
 935
 936                 return -EAGAIN;
 937         }
 938
 939         return 0;
 940 }
 941
 942 /*
 943  * Compare seqno against outstanding lazy request. Emit a request if they are
 944  * equal.
 945  */
 946 static int
 947 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
 948 {
 949         int ret;
 950
 951         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 952
 953         ret = 0;
 954         if (seqno == ring->outstanding_lazy_request)
 955                 ret = i915_add_request(ring, NULL);
 956
 957         return ret;
 958 }
 959
 960 /**
 961  * __wait_seqno - wait until execution of seqno has finished
 962  * @ring: the ring expected to report seqno
 963  * @seqno: duh!
 964  * @reset_counter: reset sequence associated with the given seqno
 965  * @interruptible: do an interruptible wait (normally yes)
 966  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
 967  *
 968  * Note: It is of utmost importance that the passed in seqno and reset_counter
 969  * values have been read by the caller in an smp safe manner. Where read-side
 970  * locks are involved, it is sufficient to read the reset_counter before
 971  * unlocking the lock that protects the seqno. For lockless tricks, the
 972  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
 973  * inserted.
 974  *
 975  * Returns 0 if the seqno was found within the alloted time. Else returns the
 976  * errno with remaining time filled in timeout argument.
 977  */
 978 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
 979                         unsigned reset_counter,
 980                         bool interruptible, struct timespec *timeout)
 981 {
 982         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 983         struct timespec before, now, wait_time={1,0};
 984         unsigned long timeout_jiffies;
 985         long end;
 986         bool wait_forever = true;
 987         int ret;
 988
 989         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
 990                 return 0;
 991
 992         trace_i915_gem_request_wait_begin(ring, seqno);
 993
 994         if (timeout != NULL) {
 995                 wait_time = *timeout;
 996                 wait_forever = false;
 997         }
 998
 999         timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1000
1001         if (WARN_ON(!ring->irq_get(ring)))
1002                 return -ENODEV;
1003
1004         /* Record current time in case interrupted by signal, or wedged * */
1005         getrawmonotonic(&before);
1006
1007 #define EXIT_COND \
1008         (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1009          i915_reset_in_progress(&dev_priv->gpu_error) || \
1010          reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1011         do {
1012                 if (interruptible)
1013                         end = wait_event_interruptible_timeout(ring->irq_queue,
1014                                                                EXIT_COND,
1015                                                                timeout_jiffies);
1016                 else
1017                         end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1018                                                  timeout_jiffies);
1019
1020                 /* We need to check whether any gpu reset happened in between
1021                  * the caller grabbing the seqno and now ... */
1022                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1023                         end = -EAGAIN;
1024
1025                 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1026                  * gone. */
1027                 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1028                 if (ret)
1029                         end = ret;
1030         } while (end == 0 && wait_forever);
1031
1032         getrawmonotonic(&now);
1033
1034         ring->irq_put(ring);
1035         trace_i915_gem_request_wait_end(ring, seqno);
1036 #undef EXIT_COND
1037
1038         if (timeout) {
1039                 struct timespec sleep_time = timespec_sub(now, before);
1040                 *timeout = timespec_sub(*timeout, sleep_time);
1041                 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1042                         set_normalized_timespec(timeout, 0, 0);
1043         }
1044
1045         switch (end) {
1046         case -EIO:
1047         case -EAGAIN: /* Wedged */
1048         case -ERESTARTSYS: /* Signal */
1049                 return (int)end;
1050         case 0: /* Timeout */
1051                 return -ETIME;
1052         default: /* Completed */
1053                 WARN_ON(end < 0); /* We're not aware of other errors */
1054                 return 0;
1055         }
1056 }
1057
1058 /**
1059  * Waits for a sequence number to be signaled, and cleans up the
1060  * request and object lists appropriately for that event.
1061  */
1062 int
1063 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1064 {
1065         struct drm_device *dev = ring->dev;
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067         bool interruptible = dev_priv->mm.interruptible;
1068         int ret;
1069
1070         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1071         BUG_ON(seqno == 0);
1072
1073         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1074         if (ret)
1075                 return ret;
1076
1077         ret = i915_gem_check_olr(ring, seqno);
1078         if (ret)
1079                 return ret;
1080
1081         return __wait_seqno(ring, seqno,
1082                             atomic_read(&dev_priv->gpu_error.reset_counter),
1083                             interruptible, NULL);
1084 }
1085
1086 static int
1087 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1088                                      struct intel_ring_buffer *ring)
1089 {
1090         i915_gem_retire_requests_ring(ring);
1091
1092         /* Manually manage the write flush as we may have not yet
1093          * retired the buffer.
1094          *
1095          * Note that the last_write_seqno is always the earlier of
1096          * the two (read/write) seqno, so if we haved successfully waited,
1097          * we know we have passed the last write.
1098          */
1099         obj->last_write_seqno = 0;
1100         obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1101
1102         return 0;
1103 }
1104
1105 /**
1106  * Ensures that all rendering to the object has completed and the object is
1107  * safe to unbind from the GTT or access from the CPU.
1108  */
1109 static __must_check int
1110 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1111                                bool readonly)
1112 {
1113         struct intel_ring_buffer *ring = obj->ring;
1114         u32 seqno;
1115         int ret;
1116
1117         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1118         if (seqno == 0)
1119                 return 0;
1120
1121         ret = i915_wait_seqno(ring, seqno);
1122         if (ret)
1123                 return ret;
1124
1125         return i915_gem_object_wait_rendering__tail(obj, ring);
1126 }
1127
1128 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1129  * as the object state may change during this call.
1130  */
1131 static __must_check int
1132 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1133                                             bool readonly)
1134 {
1135         struct drm_device *dev = obj->base.dev;
1136         struct drm_i915_private *dev_priv = dev->dev_private;
1137         struct intel_ring_buffer *ring = obj->ring;
1138         unsigned reset_counter;
1139         u32 seqno;
1140         int ret;
1141
1142         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1143         BUG_ON(!dev_priv->mm.interruptible);
1144
1145         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1146         if (seqno == 0)
1147                 return 0;
1148
1149         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1150         if (ret)
1151                 return ret;
1152
1153         ret = i915_gem_check_olr(ring, seqno);
1154         if (ret)
1155                 return ret;
1156
1157         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1158         mutex_unlock(&dev->struct_mutex);
1159         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1160         mutex_lock(&dev->struct_mutex);
1161         if (ret)
1162                 return ret;
1163
1164         return i915_gem_object_wait_rendering__tail(obj, ring);
1165 }
1166
1167 /**
1168  * Called when user space prepares to use an object with the CPU, either
1169  * through the mmap ioctl's mapping or a GTT mapping.
1170  */
1171 int
1172 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1173                           struct drm_file *file)
1174 {
1175         struct drm_i915_gem_set_domain *args = data;
1176         struct drm_i915_gem_object *obj;
1177         uint32_t read_domains = args->read_domains;
1178         uint32_t write_domain = args->write_domain;
1179         int ret;
1180
1181         /* Only handle setting domains to types used by the CPU. */
1182         if (write_domain & I915_GEM_GPU_DOMAINS)
1183                 return -EINVAL;
1184
1185         if (read_domains & I915_GEM_GPU_DOMAINS)
1186                 return -EINVAL;
1187
1188         /* Having something in the write domain implies it's in the read
1189          * domain, and only that read domain.  Enforce that in the request.
1190          */
1191         if (write_domain != 0 && read_domains != write_domain)
1192                 return -EINVAL;
1193
1194         ret = i915_mutex_lock_interruptible(dev);
1195         if (ret)
1196                 return ret;
1197
1198         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1199         if (&obj->base == NULL) {
1200                 ret = -ENOENT;
1201                 goto unlock;
1202         }
1203
1204         /* Try to flush the object off the GPU without holding the lock.
1205          * We will repeat the flush holding the lock in the normal manner
1206          * to catch cases where we are gazumped.
1207          */
1208         ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1209         if (ret)
1210                 goto unref;
1211
1212         if (read_domains & I915_GEM_DOMAIN_GTT) {
1213                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1214
1215                 /* Silently promote "you're not bound, there was nothing to do"
1216                  * to success, since the client was just asking us to
1217                  * make sure everything was done.
1218                  */
1219                 if (ret == -EINVAL)
1220                         ret = 0;
1221         } else {
1222                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1223         }
1224
1225 unref:
1226         drm_gem_object_unreference(&obj->base);
1227 unlock:
1228         mutex_unlock(&dev->struct_mutex);
1229         return ret;
1230 }
1231
1232 /**
1233  * Called when user space has done writes to this buffer
1234  */
1235 int
1236 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1237                          struct drm_file *file)
1238 {
1239         struct drm_i915_gem_sw_finish *args = data;
1240         struct drm_i915_gem_object *obj;
1241         int ret = 0;
1242
1243         ret = i915_mutex_lock_interruptible(dev);
1244         if (ret)
1245                 return ret;
1246
1247         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1248         if (&obj->base == NULL) {
1249                 ret = -ENOENT;
1250                 goto unlock;
1251         }
1252
1253         /* Pinned buffers may be scanout, so flush the cache */
1254         if (obj->pin_count)
1255                 i915_gem_object_flush_cpu_write_domain(obj);
1256
1257         drm_gem_object_unreference(&obj->base);
1258 unlock:
1259         mutex_unlock(&dev->struct_mutex);
1260         return ret;
1261 }
1262
1263 /**
1264  * Maps the contents of an object, returning the address it is mapped
1265  * into.
1266  *
1267  * While the mapping holds a reference on the contents of the object, it doesn't
1268  * imply a ref on the object itself.
1269  */
1270 int
1271 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1272                     struct drm_file *file)
1273 {
1274         struct drm_i915_gem_mmap *args = data;
1275         struct drm_gem_object *obj;
1276         unsigned long addr;
1277
1278         obj = drm_gem_object_lookup(dev, file, args->handle);
1279         if (obj == NULL)
1280                 return -ENOENT;
1281
1282         /* prime objects have no backing filp to GEM mmap
1283          * pages from.
1284          */
1285         if (!obj->filp) {
1286                 drm_gem_object_unreference_unlocked(obj);
1287                 return -EINVAL;
1288         }
1289
1290         addr = vm_mmap(obj->filp, 0, args->size,
1291                        PROT_READ | PROT_WRITE, MAP_SHARED,
1292                        args->offset);
1293         drm_gem_object_unreference_unlocked(obj);
1294         if (IS_ERR((void *)addr))
1295                 return addr;
1296
1297         args->addr_ptr = (uint64_t) addr;
1298
1299         return 0;
1300 }
1301
1302 /**
1303  * i915_gem_fault - fault a page into the GTT
1304  * vma: VMA in question
1305  * vmf: fault info
1306  *
1307  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1308  * from userspace.  The fault handler takes care of binding the object to
1309  * the GTT (if needed), allocating and programming a fence register (again,
1310  * only if needed based on whether the old reg is still valid or the object
1311  * is tiled) and inserting a new PTE into the faulting process.
1312  *
1313  * Note that the faulting process may involve evicting existing objects
1314  * from the GTT and/or fence registers to make room.  So performance may
1315  * suffer if the GTT working set is large or there are few fence registers
1316  * left.
1317  */
1318 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1319 {
1320         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1321         struct drm_device *dev = obj->base.dev;
1322         drm_i915_private_t *dev_priv = dev->dev_private;
1323         pgoff_t page_offset;
1324         unsigned long pfn;
1325         int ret = 0;
1326         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1327
1328         /* We don't use vmf->pgoff since that has the fake offset */
1329         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1330                 PAGE_SHIFT;
1331
1332         ret = i915_mutex_lock_interruptible(dev);
1333         if (ret)
1334                 goto out;
1335
1336         trace_i915_gem_object_fault(obj, page_offset, true, write);
1337
1338         /* Access to snoopable pages through the GTT is incoherent. */
1339         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1340                 ret = -EINVAL;
1341                 goto unlock;
1342         }
1343
1344         /* Now bind it into the GTT if needed */
1345         ret = i915_gem_obj_ggtt_pin(obj,  0, true, false);
1346         if (ret)
1347                 goto unlock;
1348
1349         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1350         if (ret)
1351                 goto unpin;
1352
1353         ret = i915_gem_object_get_fence(obj);
1354         if (ret)
1355                 goto unpin;
1356
1357         obj->fault_mappable = true;
1358
1359         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1360         pfn >>= PAGE_SHIFT;
1361         pfn += page_offset;
1362
1363         /* Finally, remap it using the new GTT offset */
1364         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1365 unpin:
1366         i915_gem_object_unpin(obj);
1367 unlock:
1368         mutex_unlock(&dev->struct_mutex);
1369 out:
1370         switch (ret) {
1371         case -EIO:
1372                 /* If this -EIO is due to a gpu hang, give the reset code a
1373                  * chance to clean up the mess. Otherwise return the proper
1374                  * SIGBUS. */
1375                 if (i915_terminally_wedged(&dev_priv->gpu_error))
1376                         return VM_FAULT_SIGBUS;
1377         case -EAGAIN:
1378                 /* Give the error handler a chance to run and move the
1379                  * objects off the GPU active list. Next time we service the
1380                  * fault, we should be able to transition the page into the
1381                  * GTT without touching the GPU (and so avoid further
1382                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1383                  * with coherency, just lost writes.
1384                  */
1385                 set_need_resched();
1386         case 0:
1387         case -ERESTARTSYS:
1388         case -EINTR:
1389         case -EBUSY:
1390                 /*
1391                  * EBUSY is ok: this just means that another thread
1392                  * already did the job.
1393                  */
1394                 return VM_FAULT_NOPAGE;
1395         case -ENOMEM:
1396                 return VM_FAULT_OOM;
1397         case -ENOSPC:
1398                 return VM_FAULT_SIGBUS;
1399         default:
1400                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1401                 return VM_FAULT_SIGBUS;
1402         }
1403 }
1404
1405 /**
1406  * i915_gem_release_mmap - remove physical page mappings
1407  * @obj: obj in question
1408  *
1409  * Preserve the reservation of the mmapping with the DRM core code, but
1410  * relinquish ownership of the pages back to the system.
1411  *
1412  * It is vital that we remove the page mapping if we have mapped a tiled
1413  * object through the GTT and then lose the fence register due to
1414  * resource pressure. Similarly if the object has been moved out of the
1415  * aperture, than pages mapped into userspace must be revoked. Removing the
1416  * mapping will then trigger a page fault on the next user access, allowing
1417  * fixup by i915_gem_fault().
1418  */
1419 void
1420 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1421 {
1422         if (!obj->fault_mappable)
1423                 return;
1424
1425         drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping);
1426         obj->fault_mappable = false;
1427 }
1428
1429 uint32_t
1430 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1431 {
1432         uint32_t gtt_size;
1433
1434         if (INTEL_INFO(dev)->gen >= 4 ||
1435             tiling_mode == I915_TILING_NONE)
1436                 return size;
1437
1438         /* Previous chips need a power-of-two fence region when tiling */
1439         if (INTEL_INFO(dev)->gen == 3)
1440                 gtt_size = 1024*1024;
1441         else
1442                 gtt_size = 512*1024;
1443
1444         while (gtt_size < size)
1445                 gtt_size <<= 1;
1446
1447         return gtt_size;
1448 }
1449
1450 /**
1451  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1452  * @obj: object to check
1453  *
1454  * Return the required GTT alignment for an object, taking into account
1455  * potential fence register mapping.
1456  */
1457 uint32_t
1458 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1459                            int tiling_mode, bool fenced)
1460 {
1461         /*
1462          * Minimum alignment is 4k (GTT page size), but might be greater
1463          * if a fence register is needed for the object.
1464          */
1465         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1466             tiling_mode == I915_TILING_NONE)
1467                 return 4096;
1468
1469         /*
1470          * Previous chips need to be aligned to the size of the smallest
1471          * fence register that can contain the object.
1472          */
1473         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1474 }
1475
1476 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1477 {
1478         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1479         int ret;
1480
1481         if (drm_vma_node_has_offset(&obj->base.vma_node))
1482                 return 0;
1483
1484         dev_priv->mm.shrinker_no_lock_stealing = true;
1485
1486         ret = drm_gem_create_mmap_offset(&obj->base);
1487         if (ret != -ENOSPC)
1488                 goto out;
1489
1490         /* Badly fragmented mmap space? The only way we can recover
1491          * space is by destroying unwanted objects. We can't randomly release
1492          * mmap_offsets as userspace expects them to be persistent for the
1493          * lifetime of the objects. The closest we can is to release the
1494          * offsets on purgeable objects by truncating it and marking it purged,
1495          * which prevents userspace from ever using that object again.
1496          */
1497         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1498         ret = drm_gem_create_mmap_offset(&obj->base);
1499         if (ret != -ENOSPC)
1500                 goto out;
1501
1502         i915_gem_shrink_all(dev_priv);
1503         ret = drm_gem_create_mmap_offset(&obj->base);
1504 out:
1505         dev_priv->mm.shrinker_no_lock_stealing = false;
1506
1507         return ret;
1508 }
1509
1510 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1511 {
1512         drm_gem_free_mmap_offset(&obj->base);
1513 }
1514
1515 int
1516 i915_gem_mmap_gtt(struct drm_file *file,
1517                   struct drm_device *dev,
1518                   uint32_t handle,
1519                   uint64_t *offset)
1520 {
1521         struct drm_i915_private *dev_priv = dev->dev_private;
1522         struct drm_i915_gem_object *obj;
1523         int ret;
1524
1525         ret = i915_mutex_lock_interruptible(dev);
1526         if (ret)
1527                 return ret;
1528
1529         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1530         if (&obj->base == NULL) {
1531                 ret = -ENOENT;
1532                 goto unlock;
1533         }
1534
1535         if (obj->base.size > dev_priv->gtt.mappable_end) {
1536                 ret = -E2BIG;
1537                 goto out;
1538         }
1539
1540         if (obj->madv != I915_MADV_WILLNEED) {
1541                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1542                 ret = -EINVAL;
1543                 goto out;
1544         }
1545
1546         ret = i915_gem_object_create_mmap_offset(obj);
1547         if (ret)
1548                 goto out;
1549
1550         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1551
1552 out:
1553         drm_gem_object_unreference(&obj->base);
1554 unlock:
1555         mutex_unlock(&dev->struct_mutex);
1556         return ret;
1557 }
1558
1559 /**
1560  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1561  * @dev: DRM device
1562  * @data: GTT mapping ioctl data
1563  * @file: GEM object info
1564  *
1565  * Simply returns the fake offset to userspace so it can mmap it.
1566  * The mmap call will end up in drm_gem_mmap(), which will set things
1567  * up so we can get faults in the handler above.
1568  *
1569  * The fault handler will take care of binding the object into the GTT
1570  * (since it may have been evicted to make room for something), allocating
1571  * a fence register, and mapping the appropriate aperture address into
1572  * userspace.
1573  */
1574 int
1575 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1576                         struct drm_file *file)
1577 {
1578         struct drm_i915_gem_mmap_gtt *args = data;
1579
1580         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1581 }
1582
1583 /* Immediately discard the backing storage */
1584 static void
1585 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1586 {
1587         struct inode *inode;
1588
1589         i915_gem_object_free_mmap_offset(obj);
1590
1591         if (obj->base.filp == NULL)
1592                 return;
1593
1594         /* Our goal here is to return as much of the memory as
1595          * is possible back to the system as we are called from OOM.
1596          * To do this we must instruct the shmfs to drop all of its
1597          * backing pages, *now*.
1598          */
1599         inode = file_inode(obj->base.filp);
1600         shmem_truncate_range(inode, 0, (loff_t)-1);
1601
1602         obj->madv = __I915_MADV_PURGED;
1603 }
1604
1605 static inline int
1606 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1607 {
1608         return obj->madv == I915_MADV_DONTNEED;
1609 }
1610
1611 static void
1612 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1613 {
1614         struct sg_page_iter sg_iter;
1615         int ret;
1616
1617         BUG_ON(obj->madv == __I915_MADV_PURGED);
1618
1619         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1620         if (ret) {
1621                 /* In the event of a disaster, abandon all caches and
1622                  * hope for the best.
1623                  */
1624                 WARN_ON(ret != -EIO);
1625                 i915_gem_clflush_object(obj);
1626                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1627         }
1628
1629         if (i915_gem_object_needs_bit17_swizzle(obj))
1630                 i915_gem_object_save_bit_17_swizzle(obj);
1631
1632         if (obj->madv == I915_MADV_DONTNEED)
1633                 obj->dirty = 0;
1634
1635         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1636                 struct page *page = sg_page_iter_page(&sg_iter);
1637
1638                 if (obj->dirty)
1639                         set_page_dirty(page);
1640
1641                 if (obj->madv == I915_MADV_WILLNEED)
1642                         mark_page_accessed(page);
1643
1644                 page_cache_release(page);
1645         }
1646         obj->dirty = 0;
1647
1648         sg_free_table(obj->pages);
1649         kfree(obj->pages);
1650 }
1651
1652 int
1653 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1654 {
1655         const struct drm_i915_gem_object_ops *ops = obj->ops;
1656
1657         if (obj->pages == NULL)
1658                 return 0;
1659
1660         if (obj->pages_pin_count)
1661                 return -EBUSY;
1662
1663         BUG_ON(i915_gem_obj_bound_any(obj));
1664
1665         /* ->put_pages might need to allocate memory for the bit17 swizzle
1666          * array, hence protect them from being reaped by removing them from gtt
1667          * lists early. */
1668         list_del(&obj->global_list);
1669
1670         ops->put_pages(obj);
1671         obj->pages = NULL;
1672
1673         if (i915_gem_object_is_purgeable(obj))
1674                 i915_gem_object_truncate(obj);
1675
1676         return 0;
1677 }
1678
1679 static long
1680 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1681                   bool purgeable_only)
1682 {
1683         struct drm_i915_gem_object *obj, *next;
1684         long count = 0;
1685
1686         list_for_each_entry_safe(obj, next,
1687                                  &dev_priv->mm.unbound_list,
1688                                  global_list) {
1689                 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1690                     i915_gem_object_put_pages(obj) == 0) {
1691                         count += obj->base.size >> PAGE_SHIFT;
1692                         if (count >= target)
1693                                 return count;
1694                 }
1695         }
1696
1697         list_for_each_entry_safe(obj, next, &dev_priv->mm.bound_list,
1698                                  global_list) {
1699                 struct i915_vma *vma, *v;
1700
1701                 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1702                         continue;
1703
1704                 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1705                         if (i915_vma_unbind(vma))
1706                                 break;
1707
1708                 if (!i915_gem_object_put_pages(obj)) {
1709                         count += obj->base.size >> PAGE_SHIFT;
1710                         if (count >= target)
1711                                 return count;
1712                 }
1713         }
1714
1715         return count;
1716 }
1717
1718 static long
1719 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1720 {
1721         return __i915_gem_shrink(dev_priv, target, true);
1722 }
1723
1724 static void
1725 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1726 {
1727         struct drm_i915_gem_object *obj, *next;
1728
1729         i915_gem_evict_everything(dev_priv->dev);
1730
1731         list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1732                                  global_list)
1733                 i915_gem_object_put_pages(obj);
1734 }
1735
1736 static int
1737 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1738 {
1739         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1740         int page_count, i;
1741         struct address_space *mapping;
1742         struct sg_table *st;
1743         struct scatterlist *sg;
1744         struct sg_page_iter sg_iter;
1745         struct page *page;
1746         unsigned long last_pfn = 0;     /* suppress gcc warning */
1747         gfp_t gfp;
1748
1749         /* Assert that the object is not currently in any GPU domain. As it
1750          * wasn't in the GTT, there shouldn't be any way it could have been in
1751          * a GPU cache
1752          */
1753         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1754         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1755
1756         st = kmalloc(sizeof(*st), GFP_KERNEL);
1757         if (st == NULL)
1758                 return -ENOMEM;
1759
1760         page_count = obj->base.size / PAGE_SIZE;
1761         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1762                 sg_free_table(st);
1763                 kfree(st);
1764                 return -ENOMEM;
1765         }
1766
1767         /* Get the list of pages out of our struct file.  They'll be pinned
1768          * at this point until we release them.
1769          *
1770          * Fail silently without starting the shrinker
1771          */
1772         mapping = file_inode(obj->base.filp)->i_mapping;
1773         gfp = mapping_gfp_mask(mapping);
1774         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1775         gfp &= ~(__GFP_IO | __GFP_WAIT);
1776         sg = st->sgl;
1777         st->nents = 0;
1778         for (i = 0; i < page_count; i++) {
1779                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1780                 if (IS_ERR(page)) {
1781                         i915_gem_purge(dev_priv, page_count);
1782                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1783                 }
1784                 if (IS_ERR(page)) {
1785                         /* We've tried hard to allocate the memory by reaping
1786                          * our own buffer, now let the real VM do its job and
1787                          * go down in flames if truly OOM.
1788                          */
1789                         gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1790                         gfp |= __GFP_IO | __GFP_WAIT;
1791
1792                         i915_gem_shrink_all(dev_priv);
1793                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1794                         if (IS_ERR(page))
1795                                 goto err_pages;
1796
1797                         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1798                         gfp &= ~(__GFP_IO | __GFP_WAIT);
1799                 }
1800 #ifdef CONFIG_SWIOTLB
1801                 if (swiotlb_nr_tbl()) {
1802                         st->nents++;
1803                         sg_set_page(sg, page, PAGE_SIZE, 0);
1804                         sg = sg_next(sg);
1805                         continue;
1806                 }
1807 #endif
1808                 if (!i || page_to_pfn(page) != last_pfn + 1) {
1809                         if (i)
1810                                 sg = sg_next(sg);
1811                         st->nents++;
1812                         sg_set_page(sg, page, PAGE_SIZE, 0);
1813                 } else {
1814                         sg->length += PAGE_SIZE;
1815                 }
1816                 last_pfn = page_to_pfn(page);
1817         }
1818 #ifdef CONFIG_SWIOTLB
1819         if (!swiotlb_nr_tbl())
1820 #endif
1821                 sg_mark_end(sg);
1822         obj->pages = st;
1823
1824         if (i915_gem_object_needs_bit17_swizzle(obj))
1825                 i915_gem_object_do_bit_17_swizzle(obj);
1826
1827         return 0;
1828
1829 err_pages:
1830         sg_mark_end(sg);
1831         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1832                 page_cache_release(sg_page_iter_page(&sg_iter));
1833         sg_free_table(st);
1834         kfree(st);
1835         return PTR_ERR(page);
1836 }
1837
1838 /* Ensure that the associated pages are gathered from the backing storage
1839  * and pinned into our object. i915_gem_object_get_pages() may be called
1840  * multiple times before they are released by a single call to
1841  * i915_gem_object_put_pages() - once the pages are no longer referenced
1842  * either as a result of memory pressure (reaping pages under the shrinker)
1843  * or as the object is itself released.
1844  */
1845 int
1846 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1847 {
1848         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1849         const struct drm_i915_gem_object_ops *ops = obj->ops;
1850         int ret;
1851
1852         if (obj->pages)
1853                 return 0;
1854
1855         if (obj->madv != I915_MADV_WILLNEED) {
1856                 DRM_ERROR("Attempting to obtain a purgeable object\n");
1857                 return -EINVAL;
1858         }
1859
1860         BUG_ON(obj->pages_pin_count);
1861
1862         ret = ops->get_pages(obj);
1863         if (ret)
1864                 return ret;
1865
1866         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1867         return 0;
1868 }
1869
1870 void
1871 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1872                                struct intel_ring_buffer *ring)
1873 {
1874         struct drm_device *dev = obj->base.dev;
1875         struct drm_i915_private *dev_priv = dev->dev_private;
1876         u32 seqno = intel_ring_get_seqno(ring);
1877
1878         BUG_ON(ring == NULL);
1879         if (obj->ring != ring && obj->last_write_seqno) {
1880                 /* Keep the seqno relative to the current ring */
1881                 obj->last_write_seqno = seqno;
1882         }
1883         obj->ring = ring;
1884
1885         /* Add a reference if we're newly entering the active list. */
1886         if (!obj->active) {
1887                 drm_gem_object_reference(&obj->base);
1888                 obj->active = 1;
1889         }
1890
1891         list_move_tail(&obj->ring_list, &ring->active_list);
1892
1893         obj->last_read_seqno = seqno;
1894
1895         if (obj->fenced_gpu_access) {
1896                 obj->last_fenced_seqno = seqno;
1897
1898                 /* Bump MRU to take account of the delayed flush */
1899                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1900                         struct drm_i915_fence_reg *reg;
1901
1902                         reg = &dev_priv->fence_regs[obj->fence_reg];
1903                         list_move_tail(&reg->lru_list,
1904                                        &dev_priv->mm.fence_list);
1905                 }
1906         }
1907 }
1908
1909 static void
1910 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1911 {
1912         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1913         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1914         struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1915
1916         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1917         BUG_ON(!obj->active);
1918
1919         list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list);
1920
1921         list_del_init(&obj->ring_list);
1922         obj->ring = NULL;
1923
1924         obj->last_read_seqno = 0;
1925         obj->last_write_seqno = 0;
1926         obj->base.write_domain = 0;
1927
1928         obj->last_fenced_seqno = 0;
1929         obj->fenced_gpu_access = false;
1930
1931         obj->active = 0;
1932         drm_gem_object_unreference(&obj->base);
1933
1934         WARN_ON(i915_verify_lists(dev));
1935 }
1936
1937 static int
1938 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1939 {
1940         struct drm_i915_private *dev_priv = dev->dev_private;
1941         struct intel_ring_buffer *ring;
1942         int ret, i, j;
1943
1944         /* Carefully retire all requests without writing to the rings */
1945         for_each_ring(ring, dev_priv, i) {
1946                 ret = intel_ring_idle(ring);
1947                 if (ret)
1948                         return ret;
1949         }
1950         i915_gem_retire_requests(dev);
1951
1952         /* Finally reset hw state */
1953         for_each_ring(ring, dev_priv, i) {
1954                 intel_ring_init_seqno(ring, seqno);
1955
1956                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1957                         ring->sync_seqno[j] = 0;
1958         }
1959
1960         return 0;
1961 }
1962
1963 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1964 {
1965         struct drm_i915_private *dev_priv = dev->dev_private;
1966         int ret;
1967
1968         if (seqno == 0)
1969                 return -EINVAL;
1970
1971         /* HWS page needs to be set less than what we
1972          * will inject to ring
1973          */
1974         ret = i915_gem_init_seqno(dev, seqno - 1);
1975         if (ret)
1976                 return ret;
1977
1978         /* Carefully set the last_seqno value so that wrap
1979          * detection still works
1980          */
1981         dev_priv->next_seqno = seqno;
1982         dev_priv->last_seqno = seqno - 1;
1983         if (dev_priv->last_seqno == 0)
1984                 dev_priv->last_seqno--;
1985
1986         return 0;
1987 }
1988
1989 int
1990 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1991 {
1992         struct drm_i915_private *dev_priv = dev->dev_private;
1993
1994         /* reserve 0 for non-seqno */
1995         if (dev_priv->next_seqno == 0) {
1996                 int ret = i915_gem_init_seqno(dev, 0);
1997                 if (ret)
1998                         return ret;
1999
2000                 dev_priv->next_seqno = 1;
2001         }
2002
2003         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2004         return 0;
2005 }
2006
2007 int __i915_add_request(struct intel_ring_buffer *ring,
2008                        struct drm_file *file,
2009                        struct drm_i915_gem_object *obj,
2010                        u32 *out_seqno)
2011 {
2012         drm_i915_private_t *dev_priv = ring->dev->dev_private;
2013         struct drm_i915_gem_request *request;
2014         u32 request_ring_position, request_start;
2015         int was_empty;
2016         int ret;
2017
2018         request_start = intel_ring_get_tail(ring);
2019         /*
2020          * Emit any outstanding flushes - execbuf can fail to emit the flush
2021          * after having emitted the batchbuffer command. Hence we need to fix
2022          * things up similar to emitting the lazy request. The difference here
2023          * is that the flush _must_ happen before the next request, no matter
2024          * what.
2025          */
2026         ret = intel_ring_flush_all_caches(ring);
2027         if (ret)
2028                 return ret;
2029
2030         request = kmalloc(sizeof(*request), GFP_KERNEL);
2031         if (request == NULL)
2032                 return -ENOMEM;
2033
2034
2035         /* Record the position of the start of the request so that
2036          * should we detect the updated seqno part-way through the
2037          * GPU processing the request, we never over-estimate the
2038          * position of the head.
2039          */
2040         request_ring_position = intel_ring_get_tail(ring);
2041
2042         ret = ring->add_request(ring);
2043         if (ret) {
2044                 kfree(request);
2045                 return ret;
2046         }
2047
2048         request->seqno = intel_ring_get_seqno(ring);
2049         request->ring = ring;
2050         request->head = request_start;
2051         request->tail = request_ring_position;
2052         request->ctx = ring->last_context;
2053         request->batch_obj = obj;
2054
2055         /* Whilst this request exists, batch_obj will be on the
2056          * active_list, and so will hold the active reference. Only when this
2057          * request is retired will the the batch_obj be moved onto the
2058          * inactive_list and lose its active reference. Hence we do not need
2059          * to explicitly hold another reference here.
2060          */
2061
2062         if (request->ctx)
2063                 i915_gem_context_reference(request->ctx);
2064
2065         request->emitted_jiffies = jiffies;
2066         was_empty = list_empty(&ring->request_list);
2067         list_add_tail(&request->list, &ring->request_list);
2068         request->file_priv = NULL;
2069
2070         if (file) {
2071                 struct drm_i915_file_private *file_priv = file->driver_priv;
2072
2073                 spin_lock(&file_priv->mm.lock);
2074                 request->file_priv = file_priv;
2075                 list_add_tail(&request->client_list,
2076                               &file_priv->mm.request_list);
2077                 spin_unlock(&file_priv->mm.lock);
2078         }
2079
2080         trace_i915_gem_request_add(ring, request->seqno);
2081         ring->outstanding_lazy_request = 0;
2082
2083         if (!dev_priv->ums.mm_suspended) {
2084                 i915_queue_hangcheck(ring->dev);
2085
2086                 if (was_empty) {
2087                         queue_delayed_work(dev_priv->wq,
2088                                            &dev_priv->mm.retire_work,
2089                                            round_jiffies_up_relative(HZ));
2090                         intel_mark_busy(dev_priv->dev);
2091                 }
2092         }
2093
2094         if (out_seqno)
2095                 *out_seqno = request->seqno;
2096         return 0;
2097 }
2098
2099 static inline void
2100 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2101 {
2102         struct drm_i915_file_private *file_priv = request->file_priv;
2103
2104         if (!file_priv)
2105                 return;
2106
2107         spin_lock(&file_priv->mm.lock);
2108         if (request->file_priv) {
2109                 list_del(&request->client_list);
2110                 request->file_priv = NULL;
2111         }
2112         spin_unlock(&file_priv->mm.lock);
2113 }
2114
2115 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj,
2116                                     struct i915_address_space *vm)
2117 {
2118         if (acthd >= i915_gem_obj_offset(obj, vm) &&
2119             acthd < i915_gem_obj_offset(obj, vm) + obj->base.size)
2120                 return true;
2121
2122         return false;
2123 }
2124
2125 static bool i915_head_inside_request(const u32 acthd_unmasked,
2126                                      const u32 request_start,
2127                                      const u32 request_end)
2128 {
2129         const u32 acthd = acthd_unmasked & HEAD_ADDR;
2130
2131         if (request_start < request_end) {
2132                 if (acthd >= request_start && acthd < request_end)
2133                         return true;
2134         } else if (request_start > request_end) {
2135                 if (acthd >= request_start || acthd < request_end)
2136                         return true;
2137         }
2138
2139         return false;
2140 }
2141
2142 static struct i915_address_space *
2143 request_to_vm(struct drm_i915_gem_request *request)
2144 {
2145         struct drm_i915_private *dev_priv = request->ring->dev->dev_private;
2146         struct i915_address_space *vm;
2147
2148         vm = &dev_priv->gtt.base;
2149
2150         return vm;
2151 }
2152
2153 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2154                                 const u32 acthd, bool *inside)
2155 {
2156         /* There is a possibility that unmasked head address
2157          * pointing inside the ring, matches the batch_obj address range.
2158          * However this is extremely unlikely.
2159          */
2160         if (request->batch_obj) {
2161                 if (i915_head_inside_object(acthd, request->batch_obj,
2162                                             request_to_vm(request))) {
2163                         *inside = true;
2164                         return true;
2165                 }
2166         }
2167
2168         if (i915_head_inside_request(acthd, request->head, request->tail)) {
2169                 *inside = false;
2170                 return true;
2171         }
2172
2173         return false;
2174 }
2175
2176 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2177                                   struct drm_i915_gem_request *request,
2178                                   u32 acthd)
2179 {
2180         struct i915_ctx_hang_stats *hs = NULL;
2181         bool inside, guilty;
2182         unsigned long offset = 0;
2183
2184         /* Innocent until proven guilty */
2185         guilty = false;
2186
2187         if (request->batch_obj)
2188                 offset = i915_gem_obj_offset(request->batch_obj,
2189                                              request_to_vm(request));
2190
2191         if (ring->hangcheck.action != wait &&
2192             i915_request_guilty(request, acthd, &inside)) {
2193                 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2194                           ring->name,
2195                           inside ? "inside" : "flushing",
2196                           offset,
2197                           request->ctx ? request->ctx->id : 0,
2198                           acthd);
2199
2200                 guilty = true;
2201         }
2202
2203         /* If contexts are disabled or this is the default context, use
2204          * file_priv->reset_state
2205          */
2206         if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2207                 hs = &request->ctx->hang_stats;
2208         else if (request->file_priv)
2209                 hs = &request->file_priv->hang_stats;
2210
2211         if (hs) {
2212                 if (guilty)
2213                         hs->batch_active++;
2214                 else
2215                         hs->batch_pending++;
2216         }
2217 }
2218
2219 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2220 {
2221         list_del(&request->list);
2222         i915_gem_request_remove_from_client(request);
2223
2224         if (request->ctx)
2225                 i915_gem_context_unreference(request->ctx);
2226
2227         kfree(request);
2228 }
2229
2230 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2231                                       struct intel_ring_buffer *ring)
2232 {
2233         u32 completed_seqno;
2234         u32 acthd;
2235
2236         acthd = intel_ring_get_active_head(ring);
2237         completed_seqno = ring->get_seqno(ring, false);
2238
2239         while (!list_empty(&ring->request_list)) {
2240                 struct drm_i915_gem_request *request;
2241
2242                 request = list_first_entry(&ring->request_list,
2243                                            struct drm_i915_gem_request,
2244                                            list);
2245
2246                 if (request->seqno > completed_seqno)
2247                         i915_set_reset_status(ring, request, acthd);
2248
2249                 i915_gem_free_request(request);
2250         }
2251
2252         while (!list_empty(&ring->active_list)) {
2253                 struct drm_i915_gem_object *obj;
2254
2255                 obj = list_first_entry(&ring->active_list,
2256                                        struct drm_i915_gem_object,
2257                                        ring_list);
2258
2259                 i915_gem_object_move_to_inactive(obj);
2260         }
2261 }
2262
2263 void i915_gem_restore_fences(struct drm_device *dev)
2264 {
2265         struct drm_i915_private *dev_priv = dev->dev_private;
2266         int i;
2267
2268         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2269                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2270
2271                 /*
2272                  * Commit delayed tiling changes if we have an object still
2273                  * attached to the fence, otherwise just clear the fence.
2274                  */
2275                 if (reg->obj) {
2276                         i915_gem_object_update_fence(reg->obj, reg,
2277                                                      reg->obj->tiling_mode);
2278                 } else {
2279                         i915_gem_write_fence(dev, i, NULL);
2280                 }
2281         }
2282 }
2283
2284 void i915_gem_reset(struct drm_device *dev)
2285 {
2286         struct drm_i915_private *dev_priv = dev->dev_private;
2287         struct intel_ring_buffer *ring;
2288         int i;
2289
2290         for_each_ring(ring, dev_priv, i)
2291                 i915_gem_reset_ring_lists(dev_priv, ring);
2292
2293         i915_gem_restore_fences(dev);
2294 }
2295
2296 /**
2297  * This function clears the request list as sequence numbers are passed.
2298  */
2299 void
2300 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2301 {
2302         uint32_t seqno;
2303
2304         if (list_empty(&ring->request_list))
2305                 return;
2306
2307         WARN_ON(i915_verify_lists(ring->dev));
2308
2309         seqno = ring->get_seqno(ring, true);
2310
2311         while (!list_empty(&ring->request_list)) {
2312                 struct drm_i915_gem_request *request;
2313
2314                 request = list_first_entry(&ring->request_list,
2315                                            struct drm_i915_gem_request,
2316                                            list);
2317
2318                 if (!i915_seqno_passed(seqno, request->seqno))
2319                         break;
2320
2321                 trace_i915_gem_request_retire(ring, request->seqno);
2322                 /* We know the GPU must have read the request to have
2323                  * sent us the seqno + interrupt, so use the position
2324                  * of tail of the request to update the last known position
2325                  * of the GPU head.
2326                  */
2327                 ring->last_retired_head = request->tail;
2328
2329                 i915_gem_free_request(request);
2330         }
2331
2332         /* Move any buffers on the active list that are no longer referenced
2333          * by the ringbuffer to the flushing/inactive lists as appropriate.
2334          */
2335         while (!list_empty(&ring->active_list)) {
2336                 struct drm_i915_gem_object *obj;
2337
2338                 obj = list_first_entry(&ring->active_list,
2339                                       struct drm_i915_gem_object,
2340                                       ring_list);
2341
2342                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2343                         break;
2344
2345                 i915_gem_object_move_to_inactive(obj);
2346         }
2347
2348         if (unlikely(ring->trace_irq_seqno &&
2349                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2350                 ring->irq_put(ring);
2351                 ring->trace_irq_seqno = 0;
2352         }
2353
2354         WARN_ON(i915_verify_lists(ring->dev));
2355 }
2356
2357 void
2358 i915_gem_retire_requests(struct drm_device *dev)
2359 {
2360         drm_i915_private_t *dev_priv = dev->dev_private;
2361         struct intel_ring_buffer *ring;
2362         int i;
2363
2364         for_each_ring(ring, dev_priv, i)
2365                 i915_gem_retire_requests_ring(ring);
2366 }
2367
2368 static void
2369 i915_gem_retire_work_handler(struct work_struct *work)
2370 {
2371         drm_i915_private_t *dev_priv;
2372         struct drm_device *dev;
2373         struct intel_ring_buffer *ring;
2374         bool idle;
2375         int i;
2376
2377         dev_priv = container_of(work, drm_i915_private_t,
2378                                 mm.retire_work.work);
2379         dev = dev_priv->dev;
2380
2381         /* Come back later if the device is busy... */
2382         if (!mutex_trylock(&dev->struct_mutex)) {
2383                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2384                                    round_jiffies_up_relative(HZ));
2385                 return;
2386         }
2387
2388         i915_gem_retire_requests(dev);
2389
2390         /* Send a periodic flush down the ring so we don't hold onto GEM
2391          * objects indefinitely.
2392          */
2393         idle = true;
2394         for_each_ring(ring, dev_priv, i) {
2395                 if (ring->gpu_caches_dirty)
2396                         i915_add_request(ring, NULL);
2397
2398                 idle &= list_empty(&ring->request_list);
2399         }
2400
2401         if (!dev_priv->ums.mm_suspended && !idle)
2402                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2403                                    round_jiffies_up_relative(HZ));
2404         if (idle)
2405                 intel_mark_idle(dev);
2406
2407         mutex_unlock(&dev->struct_mutex);
2408 }
2409
2410 /**
2411  * Ensures that an object will eventually get non-busy by flushing any required
2412  * write domains, emitting any outstanding lazy request and retiring and
2413  * completed requests.
2414  */
2415 static int
2416 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2417 {
2418         int ret;
2419
2420         if (obj->active) {
2421                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2422                 if (ret)
2423                         return ret;
2424
2425                 i915_gem_retire_requests_ring(obj->ring);
2426         }
2427
2428         return 0;
2429 }
2430
2431 /**
2432  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2433  * @DRM_IOCTL_ARGS: standard ioctl arguments
2434  *
2435  * Returns 0 if successful, else an error is returned with the remaining time in
2436  * the timeout parameter.
2437  *  -ETIME: object is still busy after timeout
2438  *  -ERESTARTSYS: signal interrupted the wait
2439  *  -ENONENT: object doesn't exist
2440  * Also possible, but rare:
2441  *  -EAGAIN: GPU wedged
2442  *  -ENOMEM: damn
2443  *  -ENODEV: Internal IRQ fail
2444  *  -E?: The add request failed
2445  *
2446  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2447  * non-zero timeout parameter the wait ioctl will wait for the given number of
2448  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2449  * without holding struct_mutex the object may become re-busied before this
2450  * function completes. A similar but shorter * race condition exists in the busy
2451  * ioctl
2452  */
2453 int
2454 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2455 {
2456         drm_i915_private_t *dev_priv = dev->dev_private;
2457         struct drm_i915_gem_wait *args = data;
2458         struct drm_i915_gem_object *obj;
2459         struct intel_ring_buffer *ring = NULL;
2460         struct timespec timeout_stack, *timeout = NULL;
2461         unsigned reset_counter;
2462         u32 seqno = 0;
2463         int ret = 0;
2464
2465         if (args->timeout_ns >= 0) {
2466                 timeout_stack = ns_to_timespec(args->timeout_ns);
2467                 timeout = &timeout_stack;
2468         }
2469
2470         ret = i915_mutex_lock_interruptible(dev);
2471         if (ret)
2472                 return ret;
2473
2474         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2475         if (&obj->base == NULL) {
2476                 mutex_unlock(&dev->struct_mutex);
2477                 return -ENOENT;
2478         }
2479
2480         /* Need to make sure the object gets inactive eventually. */
2481         ret = i915_gem_object_flush_active(obj);
2482         if (ret)
2483                 goto out;
2484
2485         if (obj->active) {
2486                 seqno = obj->last_read_seqno;
2487                 ring = obj->ring;
2488         }
2489
2490         if (seqno == 0)
2491                  goto out;
2492
2493         /* Do this after OLR check to make sure we make forward progress polling
2494          * on this IOCTL with a 0 timeout (like busy ioctl)
2495          */
2496         if (!args->timeout_ns) {
2497                 ret = -ETIME;
2498                 goto out;
2499         }
2500
2501         drm_gem_object_unreference(&obj->base);
2502         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2503         mutex_unlock(&dev->struct_mutex);
2504
2505         ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2506         if (timeout)
2507                 args->timeout_ns = timespec_to_ns(timeout);
2508         return ret;
2509
2510 out:
2511         drm_gem_object_unreference(&obj->base);
2512         mutex_unlock(&dev->struct_mutex);
2513         return ret;
2514 }
2515
2516 /**
2517  * i915_gem_object_sync - sync an object to a ring.
2518  *
2519  * @obj: object which may be in use on another ring.
2520  * @to: ring we wish to use the object on. May be NULL.
2521  *
2522  * This code is meant to abstract object synchronization with the GPU.
2523  * Calling with NULL implies synchronizing the object with the CPU
2524  * rather than a particular GPU ring.
2525  *
2526  * Returns 0 if successful, else propagates up the lower layer error.
2527  */
2528 int
2529 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2530                      struct intel_ring_buffer *to)
2531 {
2532         struct intel_ring_buffer *from = obj->ring;
2533         u32 seqno;
2534         int ret, idx;
2535
2536         if (from == NULL || to == from)
2537                 return 0;
2538
2539         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2540                 return i915_gem_object_wait_rendering(obj, false);
2541
2542         idx = intel_ring_sync_index(from, to);
2543
2544         seqno = obj->last_read_seqno;
2545         if (seqno <= from->sync_seqno[idx])
2546                 return 0;
2547
2548         ret = i915_gem_check_olr(obj->ring, seqno);
2549         if (ret)
2550                 return ret;
2551
2552         ret = to->sync_to(to, from, seqno);
2553         if (!ret)
2554                 /* We use last_read_seqno because sync_to()
2555                  * might have just caused seqno wrap under
2556                  * the radar.
2557                  */
2558                 from->sync_seqno[idx] = obj->last_read_seqno;
2559
2560         return ret;
2561 }
2562
2563 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2564 {
2565         u32 old_write_domain, old_read_domains;
2566
2567         /* Force a pagefault for domain tracking on next user access */
2568         i915_gem_release_mmap(obj);
2569
2570         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2571                 return;
2572
2573         /* Wait for any direct GTT access to complete */
2574         mb();
2575
2576         old_read_domains = obj->base.read_domains;
2577         old_write_domain = obj->base.write_domain;
2578
2579         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2580         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2581
2582         trace_i915_gem_object_change_domain(obj,
2583                                             old_read_domains,
2584                                             old_write_domain);
2585 }
2586
2587 int i915_vma_unbind(struct i915_vma *vma)
2588 {
2589         struct drm_i915_gem_object *obj = vma->obj;
2590         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2591         int ret;
2592
2593         if (list_empty(&vma->vma_link))
2594                 return 0;
2595
2596         if (obj->pin_count)
2597                 return -EBUSY;
2598
2599         BUG_ON(obj->pages == NULL);
2600
2601         ret = i915_gem_object_finish_gpu(obj);
2602         if (ret)
2603                 return ret;
2604         /* Continue on if we fail due to EIO, the GPU is hung so we
2605          * should be safe and we need to cleanup or else we might
2606          * cause memory corruption through use-after-free.
2607          */
2608
2609         i915_gem_object_finish_gtt(obj);
2610
2611         /* release the fence reg _after_ flushing */
2612         ret = i915_gem_object_put_fence(obj);
2613         if (ret)
2614                 return ret;
2615
2616         trace_i915_vma_unbind(vma);
2617
2618         if (obj->has_global_gtt_mapping)
2619                 i915_gem_gtt_unbind_object(obj);
2620         if (obj->has_aliasing_ppgtt_mapping) {
2621                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2622                 obj->has_aliasing_ppgtt_mapping = 0;
2623         }
2624         i915_gem_gtt_finish_object(obj);
2625         i915_gem_object_unpin_pages(obj);
2626
2627         list_del(&vma->mm_list);
2628         /* Avoid an unnecessary call to unbind on rebind. */
2629         if (i915_is_ggtt(vma->vm))
2630                 obj->map_and_fenceable = true;
2631
2632         drm_mm_remove_node(&vma->node);
2633         i915_gem_vma_destroy(vma);
2634
2635         /* Since the unbound list is global, only move to that list if
2636          * no more VMAs exist.
2637          * NB: Until we have real VMAs there will only ever be one */
2638         WARN_ON(!list_empty(&obj->vma_list));
2639         if (list_empty(&obj->vma_list))
2640                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2641
2642         return 0;
2643 }
2644
2645 /**
2646  * Unbinds an object from the global GTT aperture.
2647  */
2648 int
2649 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2650 {
2651         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2652         struct i915_address_space *ggtt = &dev_priv->gtt.base;
2653
2654         if (!i915_gem_obj_ggtt_bound(obj))
2655                 return 0;
2656
2657         if (obj->pin_count)
2658                 return -EBUSY;
2659
2660         BUG_ON(obj->pages == NULL);
2661
2662         return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2663 }
2664
2665 int i915_gpu_idle(struct drm_device *dev)
2666 {
2667         drm_i915_private_t *dev_priv = dev->dev_private;
2668         struct intel_ring_buffer *ring;
2669         int ret, i;
2670
2671         /* Flush everything onto the inactive list. */
2672         for_each_ring(ring, dev_priv, i) {
2673                 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2674                 if (ret)
2675                         return ret;
2676
2677                 ret = intel_ring_idle(ring);
2678                 if (ret)
2679                         return ret;
2680         }
2681
2682         return 0;
2683 }
2684
2685 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2686                                  struct drm_i915_gem_object *obj)
2687 {
2688         drm_i915_private_t *dev_priv = dev->dev_private;
2689         int fence_reg;
2690         int fence_pitch_shift;
2691
2692         if (INTEL_INFO(dev)->gen >= 6) {
2693                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2694                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2695         } else {
2696                 fence_reg = FENCE_REG_965_0;
2697                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2698         }
2699
2700         fence_reg += reg * 8;
2701
2702         /* To w/a incoherency with non-atomic 64-bit register updates,
2703          * we split the 64-bit update into two 32-bit writes. In order
2704          * for a partial fence not to be evaluated between writes, we
2705          * precede the update with write to turn off the fence register,
2706          * and only enable the fence as the last step.
2707          *
2708          * For extra levels of paranoia, we make sure each step lands
2709          * before applying the next step.
2710          */
2711         I915_WRITE(fence_reg, 0);
2712         POSTING_READ(fence_reg);
2713
2714         if (obj) {
2715                 u32 size = i915_gem_obj_ggtt_size(obj);
2716                 uint64_t val;
2717
2718                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2719                                  0xfffff000) << 32;
2720                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2721                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2722                 if (obj->tiling_mode == I915_TILING_Y)
2723                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2724                 val |= I965_FENCE_REG_VALID;
2725
2726                 I915_WRITE(fence_reg + 4, val >> 32);
2727                 POSTING_READ(fence_reg + 4);
2728
2729                 I915_WRITE(fence_reg + 0, val);
2730                 POSTING_READ(fence_reg);
2731         } else {
2732                 I915_WRITE(fence_reg + 4, 0);
2733                 POSTING_READ(fence_reg + 4);
2734         }
2735 }
2736
2737 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2738                                  struct drm_i915_gem_object *obj)
2739 {
2740         drm_i915_private_t *dev_priv = dev->dev_private;
2741         u32 val;
2742
2743         if (obj) {
2744                 u32 size = i915_gem_obj_ggtt_size(obj);
2745                 int pitch_val;
2746                 int tile_width;
2747
2748                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2749                      (size & -size) != size ||
2750                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2751                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2752                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2753
2754                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2755                         tile_width = 128;
2756                 else
2757                         tile_width = 512;
2758
2759                 /* Note: pitch better be a power of two tile widths */
2760                 pitch_val = obj->stride / tile_width;
2761                 pitch_val = ffs(pitch_val) - 1;
2762
2763                 val = i915_gem_obj_ggtt_offset(obj);
2764                 if (obj->tiling_mode == I915_TILING_Y)
2765                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2766                 val |= I915_FENCE_SIZE_BITS(size);
2767                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2768                 val |= I830_FENCE_REG_VALID;
2769         } else
2770                 val = 0;
2771
2772         if (reg < 8)
2773                 reg = FENCE_REG_830_0 + reg * 4;
2774         else
2775                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2776
2777         I915_WRITE(reg, val);
2778         POSTING_READ(reg);
2779 }
2780
2781 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2782                                 struct drm_i915_gem_object *obj)
2783 {
2784         drm_i915_private_t *dev_priv = dev->dev_private;
2785         uint32_t val;
2786
2787         if (obj) {
2788                 u32 size = i915_gem_obj_ggtt_size(obj);
2789                 uint32_t pitch_val;
2790
2791                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2792                      (size & -size) != size ||
2793                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2794                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2795                      i915_gem_obj_ggtt_offset(obj), size);
2796
2797                 pitch_val = obj->stride / 128;
2798                 pitch_val = ffs(pitch_val) - 1;
2799
2800                 val = i915_gem_obj_ggtt_offset(obj);
2801                 if (obj->tiling_mode == I915_TILING_Y)
2802                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2803                 val |= I830_FENCE_SIZE_BITS(size);
2804                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2805                 val |= I830_FENCE_REG_VALID;
2806         } else
2807                 val = 0;
2808
2809         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2810         POSTING_READ(FENCE_REG_830_0 + reg * 4);
2811 }
2812
2813 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2814 {
2815         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2816 }
2817
2818 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2819                                  struct drm_i915_gem_object *obj)
2820 {
2821         struct drm_i915_private *dev_priv = dev->dev_private;
2822
2823         /* Ensure that all CPU reads are completed before installing a fence
2824          * and all writes before removing the fence.
2825          */
2826         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2827                 mb();
2828
2829         WARN(obj && (!obj->stride || !obj->tiling_mode),
2830              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2831              obj->stride, obj->tiling_mode);
2832
2833         switch (INTEL_INFO(dev)->gen) {
2834         case 7:
2835         case 6:
2836         case 5:
2837         case 4: i965_write_fence_reg(dev, reg, obj); break;
2838         case 3: i915_write_fence_reg(dev, reg, obj); break;
2839         case 2: i830_write_fence_reg(dev, reg, obj); break;
2840         default: BUG();
2841         }
2842
2843         /* And similarly be paranoid that no direct access to this region
2844          * is reordered to before the fence is installed.
2845          */
2846         if (i915_gem_object_needs_mb(obj))
2847                 mb();
2848 }
2849
2850 static inline int fence_number(struct drm_i915_private *dev_priv,
2851                                struct drm_i915_fence_reg *fence)
2852 {
2853         return fence - dev_priv->fence_regs;
2854 }
2855
2856 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2857                                          struct drm_i915_fence_reg *fence,
2858                                          bool enable)
2859 {
2860         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2861         int reg = fence_number(dev_priv, fence);
2862
2863         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2864
2865         if (enable) {
2866                 obj->fence_reg = reg;
2867                 fence->obj = obj;
2868                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2869         } else {
2870                 obj->fence_reg = I915_FENCE_REG_NONE;
2871                 fence->obj = NULL;
2872                 list_del_init(&fence->lru_list);
2873         }
2874         obj->fence_dirty = false;
2875 }
2876
2877 static int
2878 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2879 {
2880         if (obj->last_fenced_seqno) {
2881                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2882                 if (ret)
2883                         return ret;
2884
2885                 obj->last_fenced_seqno = 0;
2886         }
2887
2888         obj->fenced_gpu_access = false;
2889         return 0;
2890 }
2891
2892 int
2893 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2894 {
2895         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2896         struct drm_i915_fence_reg *fence;
2897         int ret;
2898
2899         ret = i915_gem_object_wait_fence(obj);
2900         if (ret)
2901                 return ret;
2902
2903         if (obj->fence_reg == I915_FENCE_REG_NONE)
2904                 return 0;
2905
2906         fence = &dev_priv->fence_regs[obj->fence_reg];
2907
2908         i915_gem_object_fence_lost(obj);
2909         i915_gem_object_update_fence(obj, fence, false);
2910
2911         return 0;
2912 }
2913
2914 static struct drm_i915_fence_reg *
2915 i915_find_fence_reg(struct drm_device *dev)
2916 {
2917         struct drm_i915_private *dev_priv = dev->dev_private;
2918         struct drm_i915_fence_reg *reg, *avail;
2919         int i;
2920
2921         /* First try to find a free reg */
2922         avail = NULL;
2923         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2924                 reg = &dev_priv->fence_regs[i];
2925                 if (!reg->obj)
2926                         return reg;
2927
2928                 if (!reg->pin_count)
2929                         avail = reg;
2930         }
2931
2932         if (avail == NULL)
2933                 return NULL;
2934
2935         /* None available, try to steal one or wait for a user to finish */
2936         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2937                 if (reg->pin_count)
2938                         continue;
2939
2940                 return reg;
2941         }
2942
2943         return NULL;
2944 }
2945
2946 /**
2947  * i915_gem_object_get_fence - set up fencing for an object
2948  * @obj: object to map through a fence reg
2949  *
2950  * When mapping objects through the GTT, userspace wants to be able to write
2951  * to them without having to worry about swizzling if the object is tiled.
2952  * This function walks the fence regs looking for a free one for @obj,
2953  * stealing one if it can't find any.
2954  *
2955  * It then sets up the reg based on the object's properties: address, pitch
2956  * and tiling format.
2957  *
2958  * For an untiled surface, this removes any existing fence.
2959  */
2960 int
2961 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2962 {
2963         struct drm_device *dev = obj->base.dev;
2964         struct drm_i915_private *dev_priv = dev->dev_private;
2965         bool enable = obj->tiling_mode != I915_TILING_NONE;
2966         struct drm_i915_fence_reg *reg;
2967         int ret;
2968
2969         /* Have we updated the tiling parameters upon the object and so
2970          * will need to serialise the write to the associated fence register?
2971          */
2972         if (obj->fence_dirty) {
2973                 ret = i915_gem_object_wait_fence(obj);
2974                 if (ret)
2975                         return ret;
2976         }
2977
2978         /* Just update our place in the LRU if our fence is getting reused. */
2979         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2980                 reg = &dev_priv->fence_regs[obj->fence_reg];
2981                 if (!obj->fence_dirty) {
2982                         list_move_tail(&reg->lru_list,
2983                                        &dev_priv->mm.fence_list);
2984                         return 0;
2985                 }
2986         } else if (enable) {
2987                 reg = i915_find_fence_reg(dev);
2988                 if (reg == NULL)
2989                         return -EDEADLK;
2990
2991                 if (reg->obj) {
2992                         struct drm_i915_gem_object *old = reg->obj;
2993
2994                         ret = i915_gem_object_wait_fence(old);
2995                         if (ret)
2996                                 return ret;
2997
2998                         i915_gem_object_fence_lost(old);
2999                 }
3000         } else
3001                 return 0;
3002
3003         i915_gem_object_update_fence(obj, reg, enable);
3004
3005         return 0;
3006 }
3007
3008 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3009                                      struct drm_mm_node *gtt_space,
3010                                      unsigned long cache_level)
3011 {
3012         struct drm_mm_node *other;
3013
3014         /* On non-LLC machines we have to be careful when putting differing
3015          * types of snoopable memory together to avoid the prefetcher
3016          * crossing memory domains and dying.
3017          */
3018         if (HAS_LLC(dev))
3019                 return true;
3020
3021         if (!drm_mm_node_allocated(gtt_space))
3022                 return true;
3023
3024         if (list_empty(&gtt_space->node_list))
3025                 return true;
3026
3027         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3028         if (other->allocated && !other->hole_follows && other->color != cache_level)
3029                 return false;
3030
3031         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3032         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3033                 return false;
3034
3035         return true;
3036 }
3037
3038 static void i915_gem_verify_gtt(struct drm_device *dev)
3039 {
3040 #if WATCH_GTT
3041         struct drm_i915_private *dev_priv = dev->dev_private;
3042         struct drm_i915_gem_object *obj;
3043         int err = 0;
3044
3045         list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3046                 if (obj->gtt_space == NULL) {
3047                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
3048                         err++;
3049                         continue;
3050                 }
3051
3052                 if (obj->cache_level != obj->gtt_space->color) {
3053                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3054                                i915_gem_obj_ggtt_offset(obj),
3055                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3056                                obj->cache_level,
3057                                obj->gtt_space->color);
3058                         err++;
3059                         continue;
3060                 }
3061
3062                 if (!i915_gem_valid_gtt_space(dev,
3063                                               obj->gtt_space,
3064                                               obj->cache_level)) {
3065                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3066                                i915_gem_obj_ggtt_offset(obj),
3067                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3068                                obj->cache_level);
3069                         err++;
3070                         continue;
3071                 }
3072         }
3073
3074         WARN_ON(err);
3075 #endif
3076 }
3077
3078 /**
3079  * Finds free space in the GTT aperture and binds the object there.
3080  */
3081 static int
3082 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3083                            struct i915_address_space *vm,
3084                            unsigned alignment,
3085                            bool map_and_fenceable,
3086                            bool nonblocking)
3087 {
3088         struct drm_device *dev = obj->base.dev;
3089         drm_i915_private_t *dev_priv = dev->dev_private;
3090         u32 size, fence_size, fence_alignment, unfenced_alignment;
3091         bool mappable, fenceable;
3092         size_t gtt_max =
3093                 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
3094         struct i915_vma *vma;
3095         int ret;
3096
3097         if (WARN_ON(!list_empty(&obj->vma_list)))
3098                 return -EBUSY;
3099
3100         fence_size = i915_gem_get_gtt_size(dev,
3101                                            obj->base.size,
3102                                            obj->tiling_mode);
3103         fence_alignment = i915_gem_get_gtt_alignment(dev,
3104                                                      obj->base.size,
3105                                                      obj->tiling_mode, true);
3106         unfenced_alignment =
3107                 i915_gem_get_gtt_alignment(dev,
3108                                                     obj->base.size,
3109                                                     obj->tiling_mode, false);
3110
3111         if (alignment == 0)
3112                 alignment = map_and_fenceable ? fence_alignment :
3113                                                 unfenced_alignment;
3114         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3115                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3116                 return -EINVAL;
3117         }
3118
3119         size = map_and_fenceable ? fence_size : obj->base.size;
3120
3121         /* If the object is bigger than the entire aperture, reject it early
3122          * before evicting everything in a vain attempt to find space.
3123          */
3124         if (obj->base.size > gtt_max) {
3125                 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3126                           obj->base.size,
3127                           map_and_fenceable ? "mappable" : "total",
3128                           gtt_max);
3129                 return -E2BIG;
3130         }
3131
3132         ret = i915_gem_object_get_pages(obj);
3133         if (ret)
3134                 return ret;
3135
3136         i915_gem_object_pin_pages(obj);
3137
3138         /* FIXME: For now we only ever use 1 VMA per object */
3139         BUG_ON(!i915_is_ggtt(vm));
3140         WARN_ON(!list_empty(&obj->vma_list));
3141
3142         vma = i915_gem_vma_create(obj, vm);
3143         if (IS_ERR(vma)) {
3144                 ret = PTR_ERR(vma);
3145                 goto err_unpin;
3146         }
3147
3148 search_free:
3149         ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3150                                                   size, alignment,
3151                                                   obj->cache_level, 0, gtt_max,
3152                                                   DRM_MM_SEARCH_DEFAULT);
3153         if (ret) {
3154                 ret = i915_gem_evict_something(dev, vm, size, alignment,
3155                                                obj->cache_level,
3156                                                map_and_fenceable,
3157                                                nonblocking);
3158                 if (ret == 0)
3159                         goto search_free;
3160
3161                 goto err_free_vma;
3162         }
3163         if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3164                                               obj->cache_level))) {
3165                 ret = -EINVAL;
3166                 goto err_remove_node;
3167         }
3168
3169         ret = i915_gem_gtt_prepare_object(obj);
3170         if (ret)
3171                 goto err_remove_node;
3172
3173         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3174         list_add_tail(&vma->mm_list, &vm->inactive_list);
3175
3176         fenceable =
3177                 i915_is_ggtt(vm) &&
3178                 i915_gem_obj_ggtt_size(obj) == fence_size &&
3179                 (i915_gem_obj_ggtt_offset(obj) & (fence_alignment - 1)) == 0;
3180
3181         mappable =
3182                 i915_is_ggtt(vm) &&
3183                 vma->node.start + obj->base.size <= dev_priv->gtt.mappable_end;
3184
3185         /* Map and fenceable only changes if the VM is the global GGTT */
3186         if (i915_is_ggtt(vm))
3187                 obj->map_and_fenceable = mappable && fenceable;
3188
3189         trace_i915_vma_bind(vma, map_and_fenceable);
3190         i915_gem_verify_gtt(dev);
3191         return 0;
3192
3193 err_remove_node:
3194         drm_mm_remove_node(&vma->node);
3195 err_free_vma:
3196         i915_gem_vma_destroy(vma);
3197 err_unpin:
3198         i915_gem_object_unpin_pages(obj);
3199         return ret;
3200 }
3201
3202 void
3203 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3204 {
3205         /* If we don't have a page list set up, then we're not pinned
3206          * to GPU, and we can ignore the cache flush because it'll happen
3207          * again at bind time.
3208          */
3209         if (obj->pages == NULL)
3210                 return;
3211
3212         /*
3213          * Stolen memory is always coherent with the GPU as it is explicitly
3214          * marked as wc by the system, or the system is cache-coherent.
3215          */
3216         if (obj->stolen)
3217                 return;
3218
3219         /* If the GPU is snooping the contents of the CPU cache,
3220          * we do not need to manually clear the CPU cache lines.  However,
3221          * the caches are only snooped when the render cache is
3222          * flushed/invalidated.  As we always have to emit invalidations
3223          * and flushes when moving into and out of the RENDER domain, correct
3224          * snooping behaviour occurs naturally as the result of our domain
3225          * tracking.
3226          */
3227         if (obj->cache_level != I915_CACHE_NONE)
3228                 return;
3229
3230         trace_i915_gem_object_clflush(obj);
3231
3232         drm_clflush_sg(obj->pages);
3233 }
3234
3235 /** Flushes the GTT write domain for the object if it's dirty. */
3236 static void
3237 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3238 {
3239         uint32_t old_write_domain;
3240
3241         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3242                 return;
3243
3244         /* No actual flushing is required for the GTT write domain.  Writes
3245          * to it immediately go to main memory as far as we know, so there's
3246          * no chipset flush.  It also doesn't land in render cache.
3247          *
3248          * However, we do have to enforce the order so that all writes through
3249          * the GTT land before any writes to the device, such as updates to
3250          * the GATT itself.
3251          */
3252         wmb();
3253
3254         old_write_domain = obj->base.write_domain;
3255         obj->base.write_domain = 0;
3256
3257         trace_i915_gem_object_change_domain(obj,
3258                                             obj->base.read_domains,
3259                                             old_write_domain);
3260 }
3261
3262 /** Flushes the CPU write domain for the object if it's dirty. */
3263 static void
3264 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3265 {
3266         uint32_t old_write_domain;
3267
3268         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3269                 return;
3270
3271         i915_gem_clflush_object(obj);
3272         i915_gem_chipset_flush(obj->base.dev);
3273         old_write_domain = obj->base.write_domain;
3274         obj->base.write_domain = 0;
3275
3276         trace_i915_gem_object_change_domain(obj,
3277                                             obj->base.read_domains,
3278                                             old_write_domain);
3279 }
3280
3281 /**
3282  * Moves a single object to the GTT read, and possibly write domain.
3283  *
3284  * This function returns when the move is complete, including waiting on
3285  * flushes to occur.
3286  */
3287 int
3288 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3289 {
3290         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3291         uint32_t old_write_domain, old_read_domains;
3292         int ret;
3293
3294         /* Not valid to be called on unbound objects. */
3295         if (!i915_gem_obj_bound_any(obj))
3296                 return -EINVAL;
3297
3298         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3299                 return 0;
3300
3301         ret = i915_gem_object_wait_rendering(obj, !write);
3302         if (ret)
3303                 return ret;
3304
3305         i915_gem_object_flush_cpu_write_domain(obj);
3306
3307         /* Serialise direct access to this object with the barriers for
3308          * coherent writes from the GPU, by effectively invalidating the
3309          * GTT domain upon first access.
3310          */
3311         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3312                 mb();
3313
3314         old_write_domain = obj->base.write_domain;
3315         old_read_domains = obj->base.read_domains;
3316
3317         /* It should now be out of any other write domains, and we can update
3318          * the domain values for our changes.
3319          */
3320         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3321         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3322         if (write) {
3323                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3324                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3325                 obj->dirty = 1;
3326         }
3327
3328         trace_i915_gem_object_change_domain(obj,
3329                                             old_read_domains,
3330                                             old_write_domain);
3331
3332         /* And bump the LRU for this access */
3333         if (i915_gem_object_is_inactive(obj)) {
3334                 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
3335                                                            &dev_priv->gtt.base);
3336                 if (vma)
3337                         list_move_tail(&vma->mm_list,
3338                                        &dev_priv->gtt.base.inactive_list);
3339
3340         }
3341
3342         return 0;
3343 }
3344
3345 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3346                                     enum i915_cache_level cache_level)
3347 {
3348         struct drm_device *dev = obj->base.dev;
3349         drm_i915_private_t *dev_priv = dev->dev_private;
3350         struct i915_vma *vma;
3351         int ret;
3352
3353         if (obj->cache_level == cache_level)
3354                 return 0;
3355
3356         if (obj->pin_count) {
3357                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3358                 return -EBUSY;
3359         }
3360
3361         list_for_each_entry(vma, &obj->vma_list, vma_link) {
3362                 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3363                         ret = i915_vma_unbind(vma);
3364                         if (ret)
3365                                 return ret;
3366
3367                         break;
3368                 }
3369         }
3370
3371         if (i915_gem_obj_bound_any(obj)) {
3372                 ret = i915_gem_object_finish_gpu(obj);
3373                 if (ret)
3374                         return ret;
3375
3376                 i915_gem_object_finish_gtt(obj);
3377
3378                 /* Before SandyBridge, you could not use tiling or fence
3379                  * registers with snooped memory, so relinquish any fences
3380                  * currently pointing to our region in the aperture.
3381                  */
3382                 if (INTEL_INFO(dev)->gen < 6) {
3383                         ret = i915_gem_object_put_fence(obj);
3384                         if (ret)
3385                                 return ret;
3386                 }
3387
3388                 if (obj->has_global_gtt_mapping)
3389                         i915_gem_gtt_bind_object(obj, cache_level);
3390                 if (obj->has_aliasing_ppgtt_mapping)
3391                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3392                                                obj, cache_level);
3393         }
3394
3395         if (cache_level == I915_CACHE_NONE) {
3396                 u32 old_read_domains, old_write_domain;
3397
3398                 /* If we're coming from LLC cached, then we haven't
3399                  * actually been tracking whether the data is in the
3400                  * CPU cache or not, since we only allow one bit set
3401                  * in obj->write_domain and have been skipping the clflushes.
3402                  * Just set it to the CPU cache for now.
3403                  */
3404                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3405                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3406
3407                 old_read_domains = obj->base.read_domains;
3408                 old_write_domain = obj->base.write_domain;
3409
3410                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3411                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3412
3413                 trace_i915_gem_object_change_domain(obj,
3414                                                     old_read_domains,
3415                                                     old_write_domain);
3416         }
3417
3418         list_for_each_entry(vma, &obj->vma_list, vma_link)
3419                 vma->node.color = cache_level;
3420         obj->cache_level = cache_level;
3421         i915_gem_verify_gtt(dev);
3422         return 0;
3423 }
3424
3425 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3426                                struct drm_file *file)
3427 {
3428         struct drm_i915_gem_caching *args = data;
3429         struct drm_i915_gem_object *obj;
3430         int ret;
3431
3432         ret = i915_mutex_lock_interruptible(dev);
3433         if (ret)
3434                 return ret;
3435
3436         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3437         if (&obj->base == NULL) {
3438                 ret = -ENOENT;
3439                 goto unlock;
3440         }
3441
3442         args->caching = obj->cache_level != I915_CACHE_NONE;
3443
3444         drm_gem_object_unreference(&obj->base);
3445 unlock:
3446         mutex_unlock(&dev->struct_mutex);
3447         return ret;
3448 }
3449
3450 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3451                                struct drm_file *file)
3452 {
3453         struct drm_i915_gem_caching *args = data;
3454         struct drm_i915_gem_object *obj;
3455         enum i915_cache_level level;
3456         int ret;
3457
3458         switch (args->caching) {
3459         case I915_CACHING_NONE:
3460                 level = I915_CACHE_NONE;
3461                 break;
3462         case I915_CACHING_CACHED:
3463                 level = I915_CACHE_LLC;
3464                 break;
3465         default:
3466                 return -EINVAL;
3467         }
3468
3469         ret = i915_mutex_lock_interruptible(dev);
3470         if (ret)
3471                 return ret;
3472
3473         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3474         if (&obj->base == NULL) {
3475                 ret = -ENOENT;
3476                 goto unlock;
3477         }
3478
3479         ret = i915_gem_object_set_cache_level(obj, level);
3480
3481         drm_gem_object_unreference(&obj->base);
3482 unlock:
3483         mutex_unlock(&dev->struct_mutex);
3484         return ret;
3485 }
3486
3487 /*
3488  * Prepare buffer for display plane (scanout, cursors, etc).
3489  * Can be called from an uninterruptible phase (modesetting) and allows
3490  * any flushes to be pipelined (for pageflips).
3491  */
3492 int
3493 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3494                                      u32 alignment,
3495                                      struct intel_ring_buffer *pipelined)
3496 {
3497         u32 old_read_domains, old_write_domain;
3498         int ret;
3499
3500         if (pipelined != obj->ring) {
3501                 ret = i915_gem_object_sync(obj, pipelined);
3502                 if (ret)
3503                         return ret;
3504         }
3505
3506         /* The display engine is not coherent with the LLC cache on gen6.  As
3507          * a result, we make sure that the pinning that is about to occur is
3508          * done with uncached PTEs. This is lowest common denominator for all
3509          * chipsets.
3510          *
3511          * However for gen6+, we could do better by using the GFDT bit instead
3512          * of uncaching, which would allow us to flush all the LLC-cached data
3513          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3514          */
3515         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3516         if (ret)
3517                 return ret;
3518
3519         /* As the user may map the buffer once pinned in the display plane
3520          * (e.g. libkms for the bootup splash), we have to ensure that we
3521          * always use map_and_fenceable for all scanout buffers.
3522          */
3523         ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3524         if (ret)
3525                 return ret;
3526
3527         i915_gem_object_flush_cpu_write_domain(obj);
3528
3529         old_write_domain = obj->base.write_domain;
3530         old_read_domains = obj->base.read_domains;
3531
3532         /* It should now be out of any other write domains, and we can update
3533          * the domain values for our changes.
3534          */
3535         obj->base.write_domain = 0;
3536         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3537
3538         trace_i915_gem_object_change_domain(obj,
3539                                             old_read_domains,
3540                                             old_write_domain);
3541
3542         return 0;
3543 }
3544
3545 int
3546 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3547 {
3548         int ret;
3549
3550         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3551                 return 0;
3552
3553         ret = i915_gem_object_wait_rendering(obj, false);
3554         if (ret)
3555                 return ret;
3556
3557         /* Ensure that we invalidate the GPU's caches and TLBs. */
3558         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3559         return 0;
3560 }
3561
3562 /**
3563  * Moves a single object to the CPU read, and possibly write domain.
3564  *
3565  * This function returns when the move is complete, including waiting on
3566  * flushes to occur.
3567  */
3568 int
3569 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3570 {
3571         uint32_t old_write_domain, old_read_domains;
3572         int ret;
3573
3574         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3575                 return 0;
3576
3577         ret = i915_gem_object_wait_rendering(obj, !write);
3578         if (ret)
3579                 return ret;
3580
3581         i915_gem_object_flush_gtt_write_domain(obj);
3582
3583         old_write_domain = obj->base.write_domain;
3584         old_read_domains = obj->base.read_domains;
3585
3586         /* Flush the CPU cache if it's still invalid. */
3587         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3588                 i915_gem_clflush_object(obj);
3589
3590                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3591         }
3592
3593         /* It should now be out of any other write domains, and we can update
3594          * the domain values for our changes.
3595          */
3596         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3597
3598         /* If we're writing through the CPU, then the GPU read domains will
3599          * need to be invalidated at next use.
3600          */
3601         if (write) {
3602                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3603                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3604         }
3605
3606         trace_i915_gem_object_change_domain(obj,
3607                                             old_read_domains,
3608                                             old_write_domain);
3609
3610         return 0;
3611 }
3612
3613 /* Throttle our rendering by waiting until the ring has completed our requests
3614  * emitted over 20 msec ago.
3615  *
3616  * Note that if we were to use the current jiffies each time around the loop,
3617  * we wouldn't escape the function with any frames outstanding if the time to
3618  * render a frame was over 20ms.
3619  *
3620  * This should get us reasonable parallelism between CPU and GPU but also
3621  * relatively low latency when blocking on a particular request to finish.
3622  */
3623 static int
3624 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3625 {
3626         struct drm_i915_private *dev_priv = dev->dev_private;
3627         struct drm_i915_file_private *file_priv = file->driver_priv;
3628         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3629         struct drm_i915_gem_request *request;
3630         struct intel_ring_buffer *ring = NULL;
3631         unsigned reset_counter;
3632         u32 seqno = 0;
3633         int ret;
3634
3635         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3636         if (ret)
3637                 return ret;
3638
3639         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3640         if (ret)
3641                 return ret;
3642
3643         spin_lock(&file_priv->mm.lock);
3644         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3645                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3646                         break;
3647
3648                 ring = request->ring;
3649                 seqno = request->seqno;
3650         }
3651         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3652         spin_unlock(&file_priv->mm.lock);
3653
3654         if (seqno == 0)
3655                 return 0;
3656
3657         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3658         if (ret == 0)
3659                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3660
3661         return ret;
3662 }
3663
3664 int
3665 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3666                     struct i915_address_space *vm,
3667                     uint32_t alignment,
3668                     bool map_and_fenceable,
3669                     bool nonblocking)
3670 {
3671         struct i915_vma *vma;
3672         int ret;
3673
3674         if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3675                 return -EBUSY;
3676
3677         WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));
3678
3679         vma = i915_gem_obj_to_vma(obj, vm);
3680
3681         if (vma) {
3682                 if ((alignment &&
3683                      vma->node.start & (alignment - 1)) ||
3684                     (map_and_fenceable && !obj->map_and_fenceable)) {
3685                         WARN(obj->pin_count,
3686                              "bo is already pinned with incorrect alignment:"
3687                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3688                              " obj->map_and_fenceable=%d\n",
3689                              i915_gem_obj_offset(obj, vm), alignment,
3690                              map_and_fenceable,
3691                              obj->map_and_fenceable);
3692                         ret = i915_vma_unbind(vma);
3693                         if (ret)
3694                                 return ret;
3695                 }
3696         }
3697
3698         if (!i915_gem_obj_bound(obj, vm)) {
3699                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3700
3701                 ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
3702                                                  map_and_fenceable,
3703                                                  nonblocking);
3704                 if (ret)
3705                         return ret;
3706
3707                 if (!dev_priv->mm.aliasing_ppgtt)
3708                         i915_gem_gtt_bind_object(obj, obj->cache_level);
3709         }
3710
3711         if (!obj->has_global_gtt_mapping && map_and_fenceable)
3712                 i915_gem_gtt_bind_object(obj, obj->cache_level);
3713
3714         obj->pin_count++;
3715         obj->pin_mappable |= map_and_fenceable;
3716
3717         return 0;
3718 }
3719
3720 void
3721 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3722 {
3723         BUG_ON(obj->pin_count == 0);
3724         BUG_ON(!i915_gem_obj_bound_any(obj));
3725
3726         if (--obj->pin_count == 0)
3727                 obj->pin_mappable = false;
3728 }
3729
3730 int
3731 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3732                    struct drm_file *file)
3733 {
3734         struct drm_i915_gem_pin *args = data;
3735         struct drm_i915_gem_object *obj;
3736         int ret;
3737
3738         ret = i915_mutex_lock_interruptible(dev);
3739         if (ret)
3740                 return ret;
3741
3742         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3743         if (&obj->base == NULL) {
3744                 ret = -ENOENT;
3745                 goto unlock;
3746         }
3747
3748         if (obj->madv != I915_MADV_WILLNEED) {
3749                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3750                 ret = -EINVAL;
3751                 goto out;
3752         }
3753
3754         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3755                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3756                           args->handle);
3757                 ret = -EINVAL;
3758                 goto out;
3759         }
3760
3761         if (obj->user_pin_count == 0) {
3762                 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
3763                 if (ret)
3764                         goto out;
3765         }
3766
3767         obj->user_pin_count++;
3768         obj->pin_filp = file;
3769
3770         /* XXX - flush the CPU caches for pinned objects
3771          * as the X server doesn't manage domains yet
3772          */
3773         i915_gem_object_flush_cpu_write_domain(obj);
3774         args->offset = i915_gem_obj_ggtt_offset(obj);
3775 out:
3776         drm_gem_object_unreference(&obj->base);
3777 unlock:
3778         mutex_unlock(&dev->struct_mutex);
3779         return ret;
3780 }
3781
3782 int
3783 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3784                      struct drm_file *file)
3785 {
3786         struct drm_i915_gem_pin *args = data;
3787         struct drm_i915_gem_object *obj;
3788         int ret;
3789
3790         ret = i915_mutex_lock_interruptible(dev);
3791         if (ret)
3792                 return ret;
3793
3794         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3795         if (&obj->base == NULL) {
3796                 ret = -ENOENT;
3797                 goto unlock;
3798         }
3799
3800         if (obj->pin_filp != file) {
3801                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3802                           args->handle);
3803                 ret = -EINVAL;
3804                 goto out;
3805         }
3806         obj->user_pin_count--;
3807         if (obj->user_pin_count == 0) {
3808                 obj->pin_filp = NULL;
3809                 i915_gem_object_unpin(obj);
3810         }
3811
3812 out:
3813         drm_gem_object_unreference(&obj->base);
3814 unlock:
3815         mutex_unlock(&dev->struct_mutex);
3816         return ret;
3817 }
3818
3819 int
3820 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3821                     struct drm_file *file)
3822 {
3823         struct drm_i915_gem_busy *args = data;
3824         struct drm_i915_gem_object *obj;
3825         int ret;
3826
3827         ret = i915_mutex_lock_interruptible(dev);
3828         if (ret)
3829                 return ret;
3830
3831         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3832         if (&obj->base == NULL) {
3833                 ret = -ENOENT;
3834                 goto unlock;
3835         }
3836
3837         /* Count all active objects as busy, even if they are currently not used
3838          * by the gpu. Users of this interface expect objects to eventually
3839          * become non-busy without any further actions, therefore emit any
3840          * necessary flushes here.
3841          */
3842         ret = i915_gem_object_flush_active(obj);
3843
3844         args->busy = obj->active;
3845         if (obj->ring) {
3846                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3847                 args->busy |= intel_ring_flag(obj->ring) << 16;
3848         }
3849
3850         drm_gem_object_unreference(&obj->base);
3851 unlock:
3852         mutex_unlock(&dev->struct_mutex);
3853         return ret;
3854 }
3855
3856 int
3857 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3858                         struct drm_file *file_priv)
3859 {
3860         return i915_gem_ring_throttle(dev, file_priv);
3861 }
3862
3863 int
3864 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3865                        struct drm_file *file_priv)
3866 {
3867         struct drm_i915_gem_madvise *args = data;
3868         struct drm_i915_gem_object *obj;
3869         int ret;
3870
3871         switch (args->madv) {
3872         case I915_MADV_DONTNEED:
3873         case I915_MADV_WILLNEED:
3874             break;
3875         default:
3876             return -EINVAL;
3877         }
3878
3879         ret = i915_mutex_lock_interruptible(dev);
3880         if (ret)
3881                 return ret;
3882
3883         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3884         if (&obj->base == NULL) {
3885                 ret = -ENOENT;
3886                 goto unlock;
3887         }
3888
3889         if (obj->pin_count) {
3890                 ret = -EINVAL;
3891                 goto out;
3892         }
3893
3894         if (obj->madv != __I915_MADV_PURGED)
3895                 obj->madv = args->madv;
3896
3897         /* if the object is no longer attached, discard its backing storage */
3898         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3899                 i915_gem_object_truncate(obj);
3900
3901         args->retained = obj->madv != __I915_MADV_PURGED;
3902
3903 out:
3904         drm_gem_object_unreference(&obj->base);
3905 unlock:
3906         mutex_unlock(&dev->struct_mutex);
3907         return ret;
3908 }
3909
3910 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3911                           const struct drm_i915_gem_object_ops *ops)
3912 {
3913         INIT_LIST_HEAD(&obj->global_list);
3914         INIT_LIST_HEAD(&obj->ring_list);
3915         INIT_LIST_HEAD(&obj->exec_list);
3916         INIT_LIST_HEAD(&obj->vma_list);
3917
3918         obj->ops = ops;
3919
3920         obj->fence_reg = I915_FENCE_REG_NONE;
3921         obj->madv = I915_MADV_WILLNEED;
3922         /* Avoid an unnecessary call to unbind on the first bind. */
3923         obj->map_and_fenceable = true;
3924
3925         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3926 }
3927
3928 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3929         .get_pages = i915_gem_object_get_pages_gtt,
3930         .put_pages = i915_gem_object_put_pages_gtt,
3931 };
3932
3933 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3934                                                   size_t size)
3935 {
3936         struct drm_i915_gem_object *obj;
3937         struct address_space *mapping;
3938         gfp_t mask;
3939
3940         obj = i915_gem_object_alloc(dev);
3941         if (obj == NULL)
3942                 return NULL;
3943
3944         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3945                 i915_gem_object_free(obj);
3946                 return NULL;
3947         }
3948
3949         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3950         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3951                 /* 965gm cannot relocate objects above 4GiB. */
3952                 mask &= ~__GFP_HIGHMEM;
3953                 mask |= __GFP_DMA32;
3954         }
3955
3956         mapping = file_inode(obj->base.filp)->i_mapping;
3957         mapping_set_gfp_mask(mapping, mask);
3958
3959         i915_gem_object_init(obj, &i915_gem_object_ops);
3960
3961         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3962         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3963
3964         if (HAS_LLC(dev)) {
3965                 /* On some devices, we can have the GPU use the LLC (the CPU
3966                  * cache) for about a 10% performance improvement
3967                  * compared to uncached.  Graphics requests other than
3968                  * display scanout are coherent with the CPU in
3969                  * accessing this cache.  This means in this mode we
3970                  * don't need to clflush on the CPU side, and on the
3971                  * GPU side we only need to flush internal caches to
3972                  * get data visible to the CPU.
3973                  *
3974                  * However, we maintain the display planes as UC, and so
3975                  * need to rebind when first used as such.
3976                  */
3977                 obj->cache_level = I915_CACHE_LLC;
3978         } else
3979                 obj->cache_level = I915_CACHE_NONE;
3980
3981         trace_i915_gem_object_create(obj);
3982
3983         return obj;
3984 }
3985
3986 int i915_gem_init_object(struct drm_gem_object *obj)
3987 {
3988         BUG();
3989
3990         return 0;
3991 }
3992
3993 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3994 {
3995         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3996         struct drm_device *dev = obj->base.dev;
3997         drm_i915_private_t *dev_priv = dev->dev_private;
3998         struct i915_vma *vma, *next;
3999
4000         trace_i915_gem_object_destroy(obj);
4001
4002         if (obj->phys_obj)
4003                 i915_gem_detach_phys_object(dev, obj);
4004
4005         obj->pin_count = 0;
4006         /* NB: 0 or 1 elements */
4007         WARN_ON(!list_empty(&obj->vma_list) &&
4008                 !list_is_singular(&obj->vma_list));
4009         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4010                 int ret = i915_vma_unbind(vma);
4011                 if (WARN_ON(ret == -ERESTARTSYS)) {
4012                         bool was_interruptible;
4013
4014                         was_interruptible = dev_priv->mm.interruptible;
4015                         dev_priv->mm.interruptible = false;
4016
4017                         WARN_ON(i915_vma_unbind(vma));
4018
4019                         dev_priv->mm.interruptible = was_interruptible;
4020                 }
4021         }
4022
4023         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4024          * before progressing. */
4025         if (obj->stolen)
4026                 i915_gem_object_unpin_pages(obj);
4027
4028         if (WARN_ON(obj->pages_pin_count))
4029                 obj->pages_pin_count = 0;
4030         i915_gem_object_put_pages(obj);
4031         i915_gem_object_free_mmap_offset(obj);
4032         i915_gem_object_release_stolen(obj);
4033
4034         BUG_ON(obj->pages);
4035
4036         if (obj->base.import_attach)
4037                 drm_prime_gem_destroy(&obj->base, NULL);
4038
4039         drm_gem_object_release(&obj->base);
4040         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4041
4042         kfree(obj->bit_17);
4043         i915_gem_object_free(obj);
4044 }
4045
4046 struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
4047                                      struct i915_address_space *vm)
4048 {
4049         struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4050         if (vma == NULL)
4051                 return ERR_PTR(-ENOMEM);
4052
4053         INIT_LIST_HEAD(&vma->vma_link);
4054         INIT_LIST_HEAD(&vma->mm_list);
4055         vma->vm = vm;
4056         vma->obj = obj;
4057
4058         /* Keep GGTT vmas first to make debug easier */
4059         if (i915_is_ggtt(vm))
4060                 list_add(&vma->vma_link, &obj->vma_list);
4061         else
4062                 list_add_tail(&vma->vma_link, &obj->vma_list);
4063
4064         return vma;
4065 }
4066
4067 void i915_gem_vma_destroy(struct i915_vma *vma)
4068 {
4069         WARN_ON(vma->node.allocated);
4070         list_del(&vma->vma_link);
4071         kfree(vma);
4072 }
4073
4074 int
4075 i915_gem_idle(struct drm_device *dev)
4076 {
4077         drm_i915_private_t *dev_priv = dev->dev_private;
4078         int ret;
4079
4080         if (dev_priv->ums.mm_suspended) {
4081                 mutex_unlock(&dev->struct_mutex);
4082                 return 0;
4083         }
4084
4085         ret = i915_gpu_idle(dev);
4086         if (ret) {
4087                 mutex_unlock(&dev->struct_mutex);
4088                 return ret;
4089         }
4090         i915_gem_retire_requests(dev);
4091
4092         /* Under UMS, be paranoid and evict. */
4093         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4094                 i915_gem_evict_everything(dev);
4095
4096         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4097
4098         i915_kernel_lost_context(dev);
4099         i915_gem_cleanup_ringbuffer(dev);
4100
4101         /* Cancel the retire work handler, which should be idle now. */
4102         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4103
4104         return 0;
4105 }
4106
4107 void i915_gem_l3_remap(struct drm_device *dev)
4108 {
4109         drm_i915_private_t *dev_priv = dev->dev_private;
4110         u32 misccpctl;
4111         int i;
4112
4113         if (!HAS_L3_GPU_CACHE(dev))
4114                 return;
4115
4116         if (!dev_priv->l3_parity.remap_info)
4117                 return;
4118
4119         misccpctl = I915_READ(GEN7_MISCCPCTL);
4120         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4121         POSTING_READ(GEN7_MISCCPCTL);
4122
4123         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4124                 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4125                 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4126                         DRM_DEBUG("0x%x was already programmed to %x\n",
4127                                   GEN7_L3LOG_BASE + i, remap);
4128                 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4129                         DRM_DEBUG_DRIVER("Clearing remapped register\n");
4130                 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4131         }
4132
4133         /* Make sure all the writes land before disabling dop clock gating */
4134         POSTING_READ(GEN7_L3LOG_BASE);
4135
4136         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4137 }
4138
4139 void i915_gem_init_swizzling(struct drm_device *dev)
4140 {
4141         drm_i915_private_t *dev_priv = dev->dev_private;
4142
4143         if (INTEL_INFO(dev)->gen < 5 ||
4144             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4145                 return;
4146
4147         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4148                                  DISP_TILE_SURFACE_SWIZZLING);
4149
4150         if (IS_GEN5(dev))
4151                 return;
4152
4153         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4154         if (IS_GEN6(dev))
4155                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4156         else if (IS_GEN7(dev))
4157                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4158         else
4159                 BUG();
4160 }
4161
4162 static bool
4163 intel_enable_blt(struct drm_device *dev)
4164 {
4165         if (!HAS_BLT(dev))
4166                 return false;
4167
4168         /* The blitter was dysfunctional on early prototypes */
4169         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4170                 DRM_INFO("BLT not supported on this pre-production hardware;"
4171                          " graphics performance will be degraded.\n");
4172                 return false;
4173         }
4174
4175         return true;
4176 }
4177
4178 static int i915_gem_init_rings(struct drm_device *dev)
4179 {
4180         struct drm_i915_private *dev_priv = dev->dev_private;
4181         int ret;
4182
4183         ret = intel_init_render_ring_buffer(dev);
4184         if (ret)
4185                 return ret;
4186
4187         if (HAS_BSD(dev)) {
4188                 ret = intel_init_bsd_ring_buffer(dev);
4189                 if (ret)
4190                         goto cleanup_render_ring;
4191         }
4192
4193         if (intel_enable_blt(dev)) {
4194                 ret = intel_init_blt_ring_buffer(dev);
4195                 if (ret)
4196                         goto cleanup_bsd_ring;
4197         }
4198
4199         if (HAS_VEBOX(dev)) {
4200                 ret = intel_init_vebox_ring_buffer(dev);
4201                 if (ret)
4202                         goto cleanup_blt_ring;
4203         }
4204
4205
4206         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4207         if (ret)
4208                 goto cleanup_vebox_ring;
4209
4210         return 0;
4211
4212 cleanup_vebox_ring:
4213         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4214 cleanup_blt_ring:
4215         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4216 cleanup_bsd_ring:
4217         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4218 cleanup_render_ring:
4219         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4220
4221         return ret;
4222 }
4223
4224 int
4225 i915_gem_init_hw(struct drm_device *dev)
4226 {
4227         drm_i915_private_t *dev_priv = dev->dev_private;
4228         int ret;
4229
4230         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4231                 return -EIO;
4232
4233         if (dev_priv->ellc_size)
4234                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4235
4236         if (HAS_PCH_NOP(dev)) {
4237                 u32 temp = I915_READ(GEN7_MSG_CTL);
4238                 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4239                 I915_WRITE(GEN7_MSG_CTL, temp);
4240         }
4241
4242         i915_gem_l3_remap(dev);
4243
4244         i915_gem_init_swizzling(dev);
4245
4246         ret = i915_gem_init_rings(dev);
4247         if (ret)
4248                 return ret;
4249
4250         /*
4251          * XXX: There was some w/a described somewhere suggesting loading
4252          * contexts before PPGTT.
4253          */
4254         i915_gem_context_init(dev);
4255         if (dev_priv->mm.aliasing_ppgtt) {
4256                 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4257                 if (ret) {
4258                         i915_gem_cleanup_aliasing_ppgtt(dev);
4259                         DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4260                 }
4261         }
4262
4263         return 0;
4264 }
4265
4266 int i915_gem_init(struct drm_device *dev)
4267 {
4268         struct drm_i915_private *dev_priv = dev->dev_private;
4269         int ret;
4270
4271         mutex_lock(&dev->struct_mutex);
4272
4273         if (IS_VALLEYVIEW(dev)) {
4274                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4275                 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4276                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4277                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4278         }
4279
4280         i915_gem_init_global_gtt(dev);
4281
4282         ret = i915_gem_init_hw(dev);
4283         mutex_unlock(&dev->struct_mutex);
4284         if (ret) {
4285                 i915_gem_cleanup_aliasing_ppgtt(dev);
4286                 return ret;
4287         }
4288
4289         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4290         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4291                 dev_priv->dri1.allow_batchbuffer = 1;
4292         return 0;
4293 }
4294
4295 void
4296 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4297 {
4298         drm_i915_private_t *dev_priv = dev->dev_private;
4299         struct intel_ring_buffer *ring;
4300         int i;
4301
4302         for_each_ring(ring, dev_priv, i)
4303                 intel_cleanup_ring_buffer(ring);
4304 }
4305
4306 int
4307 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4308                        struct drm_file *file_priv)
4309 {
4310         struct drm_i915_private *dev_priv = dev->dev_private;
4311         int ret;
4312
4313         if (drm_core_check_feature(dev, DRIVER_MODESET))
4314                 return 0;
4315
4316         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4317                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4318                 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4319         }
4320
4321         mutex_lock(&dev->struct_mutex);
4322         dev_priv->ums.mm_suspended = 0;
4323
4324         ret = i915_gem_init_hw(dev);
4325         if (ret != 0) {
4326                 mutex_unlock(&dev->struct_mutex);
4327                 return ret;
4328         }
4329
4330         BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4331         mutex_unlock(&dev->struct_mutex);
4332
4333         ret = drm_irq_install(dev);
4334         if (ret)
4335                 goto cleanup_ringbuffer;
4336
4337         return 0;
4338
4339 cleanup_ringbuffer:
4340         mutex_lock(&dev->struct_mutex);
4341         i915_gem_cleanup_ringbuffer(dev);
4342         dev_priv->ums.mm_suspended = 1;
4343         mutex_unlock(&dev->struct_mutex);
4344
4345         return ret;
4346 }
4347
4348 int
4349 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4350                        struct drm_file *file_priv)
4351 {
4352         struct drm_i915_private *dev_priv = dev->dev_private;
4353         int ret;
4354
4355         if (drm_core_check_feature(dev, DRIVER_MODESET))
4356                 return 0;
4357
4358         drm_irq_uninstall(dev);
4359
4360         mutex_lock(&dev->struct_mutex);
4361         ret =  i915_gem_idle(dev);
4362
4363         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4364          * We need to replace this with a semaphore, or something.
4365          * And not confound ums.mm_suspended!
4366          */
4367         if (ret != 0)
4368                 dev_priv->ums.mm_suspended = 1;
4369         mutex_unlock(&dev->struct_mutex);
4370
4371         return ret;
4372 }
4373
4374 void
4375 i915_gem_lastclose(struct drm_device *dev)
4376 {
4377         int ret;
4378
4379         if (drm_core_check_feature(dev, DRIVER_MODESET))
4380                 return;
4381
4382         mutex_lock(&dev->struct_mutex);
4383         ret = i915_gem_idle(dev);
4384         if (ret)
4385                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4386         mutex_unlock(&dev->struct_mutex);
4387 }
4388
4389 static void
4390 init_ring_lists(struct intel_ring_buffer *ring)
4391 {
4392         INIT_LIST_HEAD(&ring->active_list);
4393         INIT_LIST_HEAD(&ring->request_list);
4394 }
4395
4396 static void i915_init_vm(struct drm_i915_private *dev_priv,
4397                          struct i915_address_space *vm)
4398 {
4399         vm->dev = dev_priv->dev;
4400         INIT_LIST_HEAD(&vm->active_list);
4401         INIT_LIST_HEAD(&vm->inactive_list);
4402         INIT_LIST_HEAD(&vm->global_link);
4403         list_add(&vm->global_link, &dev_priv->vm_list);
4404 }
4405
4406 void
4407 i915_gem_load(struct drm_device *dev)
4408 {
4409         drm_i915_private_t *dev_priv = dev->dev_private;
4410         int i;
4411
4412         dev_priv->slab =
4413                 kmem_cache_create("i915_gem_object",
4414                                   sizeof(struct drm_i915_gem_object), 0,
4415                                   SLAB_HWCACHE_ALIGN,
4416                                   NULL);
4417
4418         INIT_LIST_HEAD(&dev_priv->vm_list);
4419         i915_init_vm(dev_priv, &dev_priv->gtt.base);
4420
4421         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4422         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4423         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4424         for (i = 0; i < I915_NUM_RINGS; i++)
4425                 init_ring_lists(&dev_priv->ring[i]);
4426         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4427                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4428         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4429                           i915_gem_retire_work_handler);
4430         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4431
4432         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4433         if (IS_GEN3(dev)) {
4434                 I915_WRITE(MI_ARB_STATE,
4435                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4436         }
4437
4438         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4439
4440         /* Old X drivers will take 0-2 for front, back, depth buffers */
4441         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4442                 dev_priv->fence_reg_start = 3;
4443
4444         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4445                 dev_priv->num_fence_regs = 32;
4446         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4447                 dev_priv->num_fence_regs = 16;
4448         else
4449                 dev_priv->num_fence_regs = 8;
4450
4451         /* Initialize fence registers to zero */
4452         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4453         i915_gem_restore_fences(dev);
4454
4455         i915_gem_detect_bit_6_swizzle(dev);
4456         init_waitqueue_head(&dev_priv->pending_flip_queue);
4457
4458         dev_priv->mm.interruptible = true;
4459
4460         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4461         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4462         register_shrinker(&dev_priv->mm.inactive_shrinker);
4463 }
4464
4465 /*
4466  * Create a physically contiguous memory object for this object
4467  * e.g. for cursor + overlay regs
4468  */
4469 static int i915_gem_init_phys_object(struct drm_device *dev,
4470                                      int id, int size, int align)
4471 {
4472         drm_i915_private_t *dev_priv = dev->dev_private;
4473         struct drm_i915_gem_phys_object *phys_obj;
4474         int ret;
4475
4476         if (dev_priv->mm.phys_objs[id - 1] || !size)
4477                 return 0;
4478
4479         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4480         if (!phys_obj)
4481                 return -ENOMEM;
4482
4483         phys_obj->id = id;
4484
4485         phys_obj->handle = drm_pci_alloc(dev, size, align);
4486         if (!phys_obj->handle) {
4487                 ret = -ENOMEM;
4488                 goto kfree_obj;
4489         }
4490 #ifdef CONFIG_X86
4491         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4492 #endif
4493
4494         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4495
4496         return 0;
4497 kfree_obj:
4498         kfree(phys_obj);
4499         return ret;
4500 }
4501
4502 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4503 {
4504         drm_i915_private_t *dev_priv = dev->dev_private;
4505         struct drm_i915_gem_phys_object *phys_obj;
4506
4507         if (!dev_priv->mm.phys_objs[id - 1])
4508                 return;
4509
4510         phys_obj = dev_priv->mm.phys_objs[id - 1];
4511         if (phys_obj->cur_obj) {
4512                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4513         }
4514
4515 #ifdef CONFIG_X86
4516         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4517 #endif
4518         drm_pci_free(dev, phys_obj->handle);
4519         kfree(phys_obj);
4520         dev_priv->mm.phys_objs[id - 1] = NULL;
4521 }
4522
4523 void i915_gem_free_all_phys_object(struct drm_device *dev)
4524 {
4525         int i;
4526
4527         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4528                 i915_gem_free_phys_object(dev, i);
4529 }
4530
4531 void i915_gem_detach_phys_object(struct drm_device *dev,
4532                                  struct drm_i915_gem_object *obj)
4533 {
4534         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4535         char *vaddr;
4536         int i;
4537         int page_count;
4538
4539         if (!obj->phys_obj)
4540                 return;
4541         vaddr = obj->phys_obj->handle->vaddr;
4542
4543         page_count = obj->base.size / PAGE_SIZE;
4544         for (i = 0; i < page_count; i++) {
4545                 struct page *page = shmem_read_mapping_page(mapping, i);
4546                 if (!IS_ERR(page)) {
4547                         char *dst = kmap_atomic(page);
4548                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4549                         kunmap_atomic(dst);
4550
4551                         drm_clflush_pages(&page, 1);
4552
4553                         set_page_dirty(page);
4554                         mark_page_accessed(page);
4555                         page_cache_release(page);
4556                 }
4557         }
4558         i915_gem_chipset_flush(dev);
4559
4560         obj->phys_obj->cur_obj = NULL;
4561         obj->phys_obj = NULL;
4562 }
4563
4564 int
4565 i915_gem_attach_phys_object(struct drm_device *dev,
4566                             struct drm_i915_gem_object *obj,
4567                             int id,
4568                             int align)
4569 {
4570         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4571         drm_i915_private_t *dev_priv = dev->dev_private;
4572         int ret = 0;
4573         int page_count;
4574         int i;
4575
4576         if (id > I915_MAX_PHYS_OBJECT)
4577                 return -EINVAL;
4578
4579         if (obj->phys_obj) {
4580                 if (obj->phys_obj->id == id)
4581                         return 0;
4582                 i915_gem_detach_phys_object(dev, obj);
4583         }
4584
4585         /* create a new object */
4586         if (!dev_priv->mm.phys_objs[id - 1]) {
4587                 ret = i915_gem_init_phys_object(dev, id,
4588                                                 obj->base.size, align);
4589                 if (ret) {
4590                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4591                                   id, obj->base.size);
4592                         return ret;
4593                 }
4594         }
4595
4596         /* bind to the object */
4597         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4598         obj->phys_obj->cur_obj = obj;
4599
4600         page_count = obj->base.size / PAGE_SIZE;
4601
4602         for (i = 0; i < page_count; i++) {
4603                 struct page *page;
4604                 char *dst, *src;
4605
4606                 page = shmem_read_mapping_page(mapping, i);
4607                 if (IS_ERR(page))
4608                         return PTR_ERR(page);
4609
4610                 src = kmap_atomic(page);
4611                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4612                 memcpy(dst, src, PAGE_SIZE);
4613                 kunmap_atomic(src);
4614
4615                 mark_page_accessed(page);
4616                 page_cache_release(page);
4617         }
4618
4619         return 0;
4620 }
4621
4622 static int
4623 i915_gem_phys_pwrite(struct drm_device *dev,
4624                      struct drm_i915_gem_object *obj,
4625                      struct drm_i915_gem_pwrite *args,
4626                      struct drm_file *file_priv)
4627 {
4628         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4629         char __user *user_data = to_user_ptr(args->data_ptr);
4630
4631         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4632                 unsigned long unwritten;
4633
4634                 /* The physical object once assigned is fixed for the lifetime
4635                  * of the obj, so we can safely drop the lock and continue
4636                  * to access vaddr.
4637                  */
4638                 mutex_unlock(&dev->struct_mutex);
4639                 unwritten = copy_from_user(vaddr, user_data, args->size);
4640                 mutex_lock(&dev->struct_mutex);
4641                 if (unwritten)
4642                         return -EFAULT;
4643         }
4644
4645         i915_gem_chipset_flush(dev);
4646         return 0;
4647 }
4648
4649 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4650 {
4651         struct drm_i915_file_private *file_priv = file->driver_priv;
4652
4653         /* Clean up our request list when the client is going away, so that
4654          * later retire_requests won't dereference our soon-to-be-gone
4655          * file_priv.
4656          */
4657         spin_lock(&file_priv->mm.lock);
4658         while (!list_empty(&file_priv->mm.request_list)) {
4659                 struct drm_i915_gem_request *request;
4660
4661                 request = list_first_entry(&file_priv->mm.request_list,
4662                                            struct drm_i915_gem_request,
4663                                            client_list);
4664                 list_del(&request->client_list);
4665                 request->file_priv = NULL;
4666         }
4667         spin_unlock(&file_priv->mm.lock);
4668 }
4669
4670 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4671 {
4672         if (!mutex_is_locked(mutex))
4673                 return false;
4674
4675 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4676         return mutex->owner == task;
4677 #else
4678         /* Since UP may be pre-empted, we cannot assume that we own the lock */
4679         return false;
4680 #endif
4681 }
4682
4683 static int
4684 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4685 {
4686         struct drm_i915_private *dev_priv =
4687                 container_of(shrinker,
4688                              struct drm_i915_private,
4689                              mm.inactive_shrinker);
4690         struct drm_device *dev = dev_priv->dev;
4691         struct drm_i915_gem_object *obj;
4692         int nr_to_scan = sc->nr_to_scan;
4693         bool unlock = true;
4694         int cnt;
4695
4696         if (!mutex_trylock(&dev->struct_mutex)) {
4697                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4698                         return 0;
4699
4700                 if (dev_priv->mm.shrinker_no_lock_stealing)
4701                         return 0;
4702
4703                 unlock = false;
4704         }
4705
4706         if (nr_to_scan) {
4707                 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4708                 if (nr_to_scan > 0)
4709                         nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4710                                                         false);
4711                 if (nr_to_scan > 0)
4712                         i915_gem_shrink_all(dev_priv);
4713         }
4714
4715         cnt = 0;
4716         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4717                 if (obj->pages_pin_count == 0)
4718                         cnt += obj->base.size >> PAGE_SHIFT;
4719
4720         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
4721                 if (obj->active)
4722                         continue;
4723
4724                 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4725                         cnt += obj->base.size >> PAGE_SHIFT;
4726         }
4727
4728         if (unlock)
4729                 mutex_unlock(&dev->struct_mutex);
4730         return cnt;
4731 }
4732
4733 /* All the new VM stuff */
4734 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
4735                                   struct i915_address_space *vm)
4736 {
4737         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4738         struct i915_vma *vma;
4739
4740         if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4741                 vm = &dev_priv->gtt.base;
4742
4743         BUG_ON(list_empty(&o->vma_list));
4744         list_for_each_entry(vma, &o->vma_list, vma_link) {
4745                 if (vma->vm == vm)
4746                         return vma->node.start;
4747
4748         }
4749         return -1;
4750 }
4751
4752 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
4753                         struct i915_address_space *vm)
4754 {
4755         struct i915_vma *vma;
4756
4757         list_for_each_entry(vma, &o->vma_list, vma_link)
4758                 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
4759                         return true;
4760
4761         return false;
4762 }
4763
4764 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
4765 {
4766         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4767         struct i915_address_space *vm;
4768
4769         list_for_each_entry(vm, &dev_priv->vm_list, global_link)
4770                 if (i915_gem_obj_bound(o, vm))
4771                         return true;
4772
4773         return false;
4774 }
4775
4776 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
4777                                 struct i915_address_space *vm)
4778 {
4779         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4780         struct i915_vma *vma;
4781
4782         if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4783                 vm = &dev_priv->gtt.base;
4784
4785         BUG_ON(list_empty(&o->vma_list));
4786
4787         list_for_each_entry(vma, &o->vma_list, vma_link)
4788                 if (vma->vm == vm)
4789                         return vma->node.size;
4790
4791         return 0;
4792 }
4793
4794 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4795                                      struct i915_address_space *vm)
4796 {
4797         struct i915_vma *vma;
4798         list_for_each_entry(vma, &obj->vma_list, vma_link)
4799                 if (vma->vm == vm)
4800                         return vma;
4801
4802         return NULL;
4803 }